src/freedreno/vulkan/tu_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 #include "tu_private.h"
  29
  30 #include "registers/adreno_pm4.xml.h"
  31 #include "registers/adreno_common.xml.h"
  32
  33 #include "vk_format.h"
  34
  35 #include "tu_cs.h"
  36 #include "tu_blit.h"
  37
  38 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
  39
  40 void
  41 tu_bo_list_init(struct tu_bo_list *list)
  42 {
  43    list->count = list->capacity = 0;
  44    list->bo_infos = NULL;
  45 }
  46
  47 void
  48 tu_bo_list_destroy(struct tu_bo_list *list)
  49 {
  50    free(list->bo_infos);
  51 }
  52
  53 void
  54 tu_bo_list_reset(struct tu_bo_list *list)
  55 {
  56    list->count = 0;
  57 }
  58
  59 /**
  60  * \a flags consists of MSM_SUBMIT_BO_FLAGS.
  61  */
  62 static uint32_t
  63 tu_bo_list_add_info(struct tu_bo_list *list,
  64                     const struct drm_msm_gem_submit_bo *bo_info)
  65 {
  66    assert(bo_info->handle != 0);
  67
  68    for (uint32_t i = 0; i < list->count; ++i) {
  69       if (list->bo_infos[i].handle == bo_info->handle) {
  70          assert(list->bo_infos[i].presumed == bo_info->presumed);
  71          list->bo_infos[i].flags |= bo_info->flags;
  72          return i;
  73       }
  74    }
  75
  76    /* grow list->bo_infos if needed */
  77    if (list->count == list->capacity) {
  78       uint32_t new_capacity = MAX2(2 * list->count, 16);
  79       struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
  80          list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
  81       if (!new_bo_infos)
  82          return TU_BO_LIST_FAILED;
  83       list->bo_infos = new_bo_infos;
  84       list->capacity = new_capacity;
  85    }
  86
  87    list->bo_infos[list->count] = *bo_info;
  88    return list->count++;
  89 }
  90
  91 uint32_t
  92 tu_bo_list_add(struct tu_bo_list *list,
  93                const struct tu_bo *bo,
  94                uint32_t flags)
  95 {
  96    return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
  97                                        .flags = flags,
  98                                        .handle = bo->gem_handle,
  99                                        .presumed = bo->iova,
 100                                     });
 101 }
 102
 103 VkResult
 104 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
 105 {
 106    for (uint32_t i = 0; i < other->count; i++) {
 107       if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
 108          return VK_ERROR_OUT_OF_HOST_MEMORY;
 109    }
 110
 111    return VK_SUCCESS;
 112 }
 113
 114 static bool
 115 is_linear_mipmapped(const struct tu_image_view *iview)
 116 {
 117    return iview->image->layout.tile_mode == TILE6_LINEAR &&
 118           iview->base_mip != iview->image->level_count - 1;
 119 }
 120
 121 static bool
 122 force_sysmem(const struct tu_cmd_buffer *cmd,
 123              const struct VkRect2D *render_area)
 124 {
 125    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 126    const struct tu_physical_device *device = cmd->device->physical_device;
 127    bool has_linear_mipmapped_store = false;
 128    const struct tu_render_pass *pass = cmd->state.pass;
 129
 130    /* Iterate over all the places we call tu6_emit_store_attachment() */
 131    for (unsigned i = 0; i < pass->subpass_count; i++) {
 132       const struct tu_subpass *subpass = &pass->subpasses[i];
 133       if (subpass->resolve_attachments) {
 134          for (unsigned i = 0; i < subpass->color_count; i++) {
 135             uint32_t a = subpass->resolve_attachments[i].attachment;
 136             if (a != VK_ATTACHMENT_UNUSED &&
 137                 cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_STORE) {
 138                const struct tu_image_view *iview = fb->attachments[a].attachment;
 139                if (is_linear_mipmapped(iview)) {
 140                   has_linear_mipmapped_store = true;
 141                   break;
 142                }
 143             }
 144          }
 145       }
 146    }
 147
 148    for (unsigned i = 0; i < pass->attachment_count; i++) {
 149       if (pass->attachments[i].gmem_offset >= 0 &&
 150           cmd->state.pass->attachments[i].store_op == VK_ATTACHMENT_STORE_OP_STORE) {
 151          const struct tu_image_view *iview = fb->attachments[i].attachment;
 152          if (is_linear_mipmapped(iview)) {
 153             has_linear_mipmapped_store = true;
 154             break;
 155          }
 156       }
 157    }
 158
 159    /* Linear textures cannot have any padding between mipmap levels and their
 160     * height isn't padded, while at the same time the GMEM->MEM resolve does
 161     * not have per-pixel granularity, so if the image height isn't aligned to
 162     * the resolve granularity and the render area is tall enough, we may wind
 163     * up writing past the bottom of the image into the next miplevel or even
 164     * past the end of the image. For the last miplevel, the layout code should
 165     * insert enough padding so that the overdraw writes to the padding.  To
 166     * work around this, we force-enable sysmem rendering.
 167     */
 168    const uint32_t y2 = render_area->offset.y + render_area->extent.height;
 169    const uint32_t aligned_y2 = ALIGN_POT(y2, device->tile_align_h);
 170
 171    return has_linear_mipmapped_store && aligned_y2 > fb->height;
 172 }
 173
 174 static void
 175 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
 176                                     const struct tu_device *dev,
 177                                     uint32_t pixels)
 178 {
 179    const uint32_t tile_align_w = dev->physical_device->tile_align_w;
 180    const uint32_t tile_align_h = dev->physical_device->tile_align_h;
 181    const uint32_t max_tile_width = 1024; /* A6xx */
 182
 183    tiling->tile0.offset = (VkOffset2D) {
 184       .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
 185       .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
 186    };
 187
 188    const uint32_t ra_width =
 189       tiling->render_area.extent.width +
 190       (tiling->render_area.offset.x - tiling->tile0.offset.x);
 191    const uint32_t ra_height =
 192       tiling->render_area.extent.height +
 193       (tiling->render_area.offset.y - tiling->tile0.offset.y);
 194
 195    /* start from 1 tile */
 196    tiling->tile_count = (VkExtent2D) {
 197       .width = 1,
 198       .height = 1,
 199    };
 200    tiling->tile0.extent = (VkExtent2D) {
 201       .width = align(ra_width, tile_align_w),
 202       .height = align(ra_height, tile_align_h),
 203    };
 204
 205    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN)) {
 206       /* start with 2x2 tiles */
 207       tiling->tile_count.width = 2;
 208       tiling->tile_count.height = 2;
 209       tiling->tile0.extent.width = align(DIV_ROUND_UP(ra_width, 2), tile_align_w);
 210       tiling->tile0.extent.height = align(DIV_ROUND_UP(ra_height, 2), tile_align_h);
 211    }
 212
 213    /* do not exceed max tile width */
 214    while (tiling->tile0.extent.width > max_tile_width) {
 215       tiling->tile_count.width++;
 216       tiling->tile0.extent.width =
 217          align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 218    }
 219
 220    /* do not exceed gmem size */
 221    while (tiling->tile0.extent.width * tiling->tile0.extent.height > pixels) {
 222       if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
 223          tiling->tile_count.width++;
 224          tiling->tile0.extent.width =
 225             align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 226       } else {
 227          /* if this assert fails then layout is impossible.. */
 228          assert(tiling->tile0.extent.height > tile_align_h);
 229          tiling->tile_count.height++;
 230          tiling->tile0.extent.height =
 231             align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), tile_align_h);
 232       }
 233    }
 234 }
 235
 236 static void
 237 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
 238                                     const struct tu_device *dev)
 239 {
 240    const uint32_t max_pipe_count = 32; /* A6xx */
 241
 242    /* start from 1 tile per pipe */
 243    tiling->pipe0 = (VkExtent2D) {
 244       .width = 1,
 245       .height = 1,
 246    };
 247    tiling->pipe_count = tiling->tile_count;
 248
 249    /* do not exceed max pipe count vertically */
 250    while (tiling->pipe_count.height > max_pipe_count) {
 251       tiling->pipe0.height += 2;
 252       tiling->pipe_count.height =
 253          (tiling->tile_count.height + tiling->pipe0.height - 1) /
 254          tiling->pipe0.height;
 255    }
 256
 257    /* do not exceed max pipe count */
 258    while (tiling->pipe_count.width * tiling->pipe_count.height >
 259           max_pipe_count) {
 260       tiling->pipe0.width += 1;
 261       tiling->pipe_count.width =
 262          (tiling->tile_count.width + tiling->pipe0.width - 1) /
 263          tiling->pipe0.width;
 264    }
 265 }
 266
 267 static void
 268 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
 269                               const struct tu_device *dev)
 270 {
 271    const uint32_t max_pipe_count = 32; /* A6xx */
 272    const uint32_t used_pipe_count =
 273       tiling->pipe_count.width * tiling->pipe_count.height;
 274    const VkExtent2D last_pipe = {
 275       .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
 276       .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
 277    };
 278
 279    assert(used_pipe_count <= max_pipe_count);
 280    assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
 281
 282    for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
 283       for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
 284          const uint32_t pipe_x = tiling->pipe0.width * x;
 285          const uint32_t pipe_y = tiling->pipe0.height * y;
 286          const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
 287                                     ? last_pipe.width
 288                                     : tiling->pipe0.width;
 289          const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
 290                                     ? last_pipe.height
 291                                     : tiling->pipe0.height;
 292          const uint32_t n = tiling->pipe_count.width * y + x;
 293
 294          tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
 295                                   A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
 296                                   A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
 297                                   A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
 298          tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
 299       }
 300    }
 301
 302    memset(tiling->pipe_config + used_pipe_count, 0,
 303           sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
 304 }
 305
 306 static void
 307 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
 308                           const struct tu_device *dev,
 309                           uint32_t tx,
 310                           uint32_t ty,
 311                           struct tu_tile *tile)
 312 {
 313    /* find the pipe and the slot for tile (tx, ty) */
 314    const uint32_t px = tx / tiling->pipe0.width;
 315    const uint32_t py = ty / tiling->pipe0.height;
 316    const uint32_t sx = tx - tiling->pipe0.width * px;
 317    const uint32_t sy = ty - tiling->pipe0.height * py;
 318
 319    assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
 320    assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
 321    assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
 322
 323    /* convert to 1D indices */
 324    tile->pipe = tiling->pipe_count.width * py + px;
 325    tile->slot = tiling->pipe0.width * sy + sx;
 326
 327    /* get the blit area for the tile */
 328    tile->begin = (VkOffset2D) {
 329       .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
 330       .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
 331    };
 332    tile->end.x =
 333       (tx == tiling->tile_count.width - 1)
 334          ? tiling->render_area.offset.x + tiling->render_area.extent.width
 335          : tile->begin.x + tiling->tile0.extent.width;
 336    tile->end.y =
 337       (ty == tiling->tile_count.height - 1)
 338          ? tiling->render_area.offset.y + tiling->render_area.extent.height
 339          : tile->begin.y + tiling->tile0.extent.height;
 340 }
 341
 342 enum a3xx_msaa_samples
 343 tu_msaa_samples(uint32_t samples)
 344 {
 345    switch (samples) {
 346    case 1:
 347       return MSAA_ONE;
 348    case 2:
 349       return MSAA_TWO;
 350    case 4:
 351       return MSAA_FOUR;
 352    case 8:
 353       return MSAA_EIGHT;
 354    default:
 355       assert(!"invalid sample count");
 356       return MSAA_ONE;
 357    }
 358 }
 359
 360 static enum a4xx_index_size
 361 tu6_index_size(VkIndexType type)
 362 {
 363    switch (type) {
 364    case VK_INDEX_TYPE_UINT16:
 365       return INDEX4_SIZE_16_BIT;
 366    case VK_INDEX_TYPE_UINT32:
 367       return INDEX4_SIZE_32_BIT;
 368    default:
 369       unreachable("invalid VkIndexType");
 370       return INDEX4_SIZE_8_BIT;
 371    }
 372 }
 373
 374 unsigned
 375 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
 376                      struct tu_cs *cs,
 377                      enum vgt_event_type event,
 378                      bool need_seqno)
 379 {
 380    unsigned seqno = 0;
 381
 382    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
 383    tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
 384    if (need_seqno) {
 385       tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 386       seqno = ++cmd->scratch_seqno;
 387       tu_cs_emit(cs, seqno);
 388    }
 389
 390    return seqno;
 391 }
 392
 393 static void
 394 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 395 {
 396    tu6_emit_event_write(cmd, cs, 0x31, false);
 397 }
 398
 399 static void
 400 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 401 {
 402    tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
 403 }
 404
 405 static void
 406 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 407 {
 408    if (cmd->wait_for_idle) {
 409       tu_cs_emit_wfi(cs);
 410       cmd->wait_for_idle = false;
 411    }
 412 }
 413
 414 #define tu_image_view_ubwc_pitches(iview)                                \
 415    .pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip),          \
 416    .array_pitch = tu_image_ubwc_size(iview->image, iview->base_mip) >> 2
 417
 418 static void
 419 tu6_emit_zs(struct tu_cmd_buffer *cmd,
 420             const struct tu_subpass *subpass,
 421             struct tu_cs *cs)
 422 {
 423    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 424
 425    const uint32_t a = subpass->depth_stencil_attachment.attachment;
 426    if (a == VK_ATTACHMENT_UNUSED) {
 427       tu_cs_emit_regs(cs,
 428                       A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE),
 429                       A6XX_RB_DEPTH_BUFFER_PITCH(0),
 430                       A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
 431                       A6XX_RB_DEPTH_BUFFER_BASE(0),
 432                       A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
 433
 434       tu_cs_emit_regs(cs,
 435                       A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
 436
 437       tu_cs_emit_regs(cs,
 438                       A6XX_GRAS_LRZ_BUFFER_BASE(0),
 439                       A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 440                       A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 441
 442       tu_cs_emit_regs(cs, A6XX_RB_STENCIL_INFO(0));
 443
 444       return;
 445    }
 446
 447    const struct tu_image_view *iview = fb->attachments[a].attachment;
 448    enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
 449
 450    tu_cs_emit_regs(cs,
 451                    A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
 452                    A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)),
 453                    A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layout.layer_size),
 454                    A6XX_RB_DEPTH_BUFFER_BASE(tu_image_view_base_ref(iview)),
 455                    A6XX_RB_DEPTH_BUFFER_BASE_GMEM(cmd->state.pass->attachments[a].gmem_offset));
 456
 457    tu_cs_emit_regs(cs,
 458                    A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
 459
 460    tu_cs_emit_regs(cs,
 461                    A6XX_RB_DEPTH_FLAG_BUFFER_BASE(tu_image_view_ubwc_base_ref(iview)),
 462                    A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(tu_image_view_ubwc_pitches(iview)));
 463
 464    tu_cs_emit_regs(cs,
 465                    A6XX_GRAS_LRZ_BUFFER_BASE(0),
 466                    A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 467                    A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 468
 469    tu_cs_emit_regs(cs,
 470                    A6XX_RB_STENCIL_INFO(0));
 471
 472    /* enable zs? */
 473 }
 474
 475 static void
 476 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
 477              const struct tu_subpass *subpass,
 478              struct tu_cs *cs)
 479 {
 480    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 481    unsigned char mrt_comp[MAX_RTS] = { 0 };
 482    unsigned srgb_cntl = 0;
 483
 484    for (uint32_t i = 0; i < subpass->color_count; ++i) {
 485       uint32_t a = subpass->color_attachments[i].attachment;
 486       if (a == VK_ATTACHMENT_UNUSED)
 487          continue;
 488
 489       const struct tu_image_view *iview = fb->attachments[a].attachment;
 490       const enum a6xx_tile_mode tile_mode =
 491          tu6_get_image_tile_mode(iview->image, iview->base_mip);
 492
 493       mrt_comp[i] = 0xf;
 494
 495       if (vk_format_is_srgb(iview->vk_format))
 496          srgb_cntl |= (1 << i);
 497
 498       const struct tu_native_format *format =
 499          tu6_get_native_format(iview->vk_format);
 500       assert(format && format->rb >= 0);
 501
 502       tu_cs_emit_regs(cs,
 503                       A6XX_RB_MRT_BUF_INFO(i,
 504                                            .color_tile_mode = tile_mode,
 505                                            .color_format = format->rb,
 506                                            .color_swap = format->swap),
 507                       A6XX_RB_MRT_PITCH(i, tu_image_stride(iview->image, iview->base_mip)),
 508                       A6XX_RB_MRT_ARRAY_PITCH(i, iview->image->layout.layer_size),
 509                       A6XX_RB_MRT_BASE(i, tu_image_view_base_ref(iview)),
 510                       A6XX_RB_MRT_BASE_GMEM(i, cmd->state.pass->attachments[a].gmem_offset));
 511
 512       tu_cs_emit_regs(cs,
 513                       A6XX_SP_FS_MRT_REG(i,
 514                                          .color_format = format->rb,
 515                                          .color_sint = vk_format_is_sint(iview->vk_format),
 516                                          .color_uint = vk_format_is_uint(iview->vk_format)));
 517
 518       tu_cs_emit_regs(cs,
 519                       A6XX_RB_MRT_FLAG_BUFFER_ADDR(i, tu_image_view_ubwc_base_ref(iview)),
 520                       A6XX_RB_MRT_FLAG_BUFFER_PITCH(i, tu_image_view_ubwc_pitches(iview)));
 521    }
 522
 523    tu_cs_emit_regs(cs,
 524                    A6XX_RB_SRGB_CNTL(srgb_cntl));
 525
 526    tu_cs_emit_regs(cs,
 527                    A6XX_SP_SRGB_CNTL(srgb_cntl));
 528
 529    tu_cs_emit_regs(cs,
 530                    A6XX_RB_RENDER_COMPONENTS(
 531                       .rt0 = mrt_comp[0],
 532                       .rt1 = mrt_comp[1],
 533                       .rt2 = mrt_comp[2],
 534                       .rt3 = mrt_comp[3],
 535                       .rt4 = mrt_comp[4],
 536                       .rt5 = mrt_comp[5],
 537                       .rt6 = mrt_comp[6],
 538                       .rt7 = mrt_comp[7]));
 539
 540    tu_cs_emit_regs(cs,
 541                    A6XX_SP_FS_RENDER_COMPONENTS(
 542                       .rt0 = mrt_comp[0],
 543                       .rt1 = mrt_comp[1],
 544                       .rt2 = mrt_comp[2],
 545                       .rt3 = mrt_comp[3],
 546                       .rt4 = mrt_comp[4],
 547                       .rt5 = mrt_comp[5],
 548                       .rt6 = mrt_comp[6],
 549                       .rt7 = mrt_comp[7]));
 550 }
 551
 552 static void
 553 tu6_emit_msaa(struct tu_cmd_buffer *cmd,
 554               const struct tu_subpass *subpass,
 555               struct tu_cs *cs)
 556 {
 557    const enum a3xx_msaa_samples samples = tu_msaa_samples(subpass->samples);
 558    bool msaa_disable = samples == MSAA_ONE;
 559
 560    tu_cs_emit_regs(cs,
 561                    A6XX_SP_TP_RAS_MSAA_CNTL(samples),
 562                    A6XX_SP_TP_DEST_MSAA_CNTL(.samples = samples,
 563                                              .msaa_disable = msaa_disable));
 564
 565    tu_cs_emit_regs(cs,
 566                    A6XX_GRAS_RAS_MSAA_CNTL(samples),
 567                    A6XX_GRAS_DEST_MSAA_CNTL(.samples = samples,
 568                                             .msaa_disable = msaa_disable));
 569
 570    tu_cs_emit_regs(cs,
 571                    A6XX_RB_RAS_MSAA_CNTL(samples),
 572                    A6XX_RB_DEST_MSAA_CNTL(.samples = samples,
 573                                           .msaa_disable = msaa_disable));
 574
 575    tu_cs_emit_regs(cs,
 576                    A6XX_RB_MSAA_CNTL(samples));
 577 }
 578
 579 static void
 580 tu6_emit_bin_size(struct tu_cs *cs,
 581                   uint32_t bin_w, uint32_t bin_h, uint32_t flags)
 582 {
 583    tu_cs_emit_regs(cs,
 584                    A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
 585                                          .binh = bin_h,
 586                                          .dword = flags));
 587
 588    tu_cs_emit_regs(cs,
 589                    A6XX_RB_BIN_CONTROL(.binw = bin_w,
 590                                        .binh = bin_h,
 591                                        .dword = flags));
 592
 593    /* no flag for RB_BIN_CONTROL2... */
 594    tu_cs_emit_regs(cs,
 595                    A6XX_RB_BIN_CONTROL2(.binw = bin_w,
 596                                         .binh = bin_h));
 597 }
 598
 599 static void
 600 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
 601                      const struct tu_subpass *subpass,
 602                      struct tu_cs *cs,
 603                      bool binning)
 604 {
 605    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 606    uint32_t cntl = 0;
 607    cntl |= A6XX_RB_RENDER_CNTL_UNK4;
 608    if (binning) {
 609       cntl |= A6XX_RB_RENDER_CNTL_BINNING;
 610    } else {
 611       uint32_t mrts_ubwc_enable = 0;
 612       for (uint32_t i = 0; i < subpass->color_count; ++i) {
 613          uint32_t a = subpass->color_attachments[i].attachment;
 614          if (a == VK_ATTACHMENT_UNUSED)
 615             continue;
 616
 617          const struct tu_image_view *iview = fb->attachments[a].attachment;
 618          if (iview->image->layout.ubwc_layer_size != 0)
 619             mrts_ubwc_enable |= 1 << i;
 620       }
 621
 622       cntl |= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable);
 623
 624       const uint32_t a = subpass->depth_stencil_attachment.attachment;
 625       if (a != VK_ATTACHMENT_UNUSED) {
 626          const struct tu_image_view *iview = fb->attachments[a].attachment;
 627          if (iview->image->layout.ubwc_layer_size != 0)
 628             cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH;
 629       }
 630
 631       /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
 632        * in order to set it correctly for the different subpasses. However,
 633        * that means the packets we're emitting also happen during binning. So
 634        * we need to guard the write on !BINNING at CP execution time.
 635        */
 636       tu_cs_reserve(cs, 3 + 4);
 637       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 638       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
 639                      CP_COND_REG_EXEC_0_GMEM | CP_COND_REG_EXEC_0_SYSMEM);
 640       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(4));
 641    }
 642
 643    tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
 644    tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
 645    tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
 646    tu_cs_emit(cs, cntl);
 647 }
 648
 649 static void
 650 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
 651 {
 652    const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
 653    uint32_t x1 = render_area->offset.x;
 654    uint32_t y1 = render_area->offset.y;
 655    uint32_t x2 = x1 + render_area->extent.width - 1;
 656    uint32_t y2 = y1 + render_area->extent.height - 1;
 657
 658    /* TODO: alignment requirement seems to be less than tile_align_w/h */
 659    if (align) {
 660       x1 = x1 & ~cmd->device->physical_device->tile_align_w;
 661       y1 = y1 & ~cmd->device->physical_device->tile_align_h;
 662       x2 = ALIGN_POT(x2 + 1, cmd->device->physical_device->tile_align_w) - 1;
 663       y2 = ALIGN_POT(y2 + 1, cmd->device->physical_device->tile_align_h) - 1;
 664    }
 665
 666    tu_cs_emit_regs(cs,
 667                    A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
 668                    A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
 669 }
 670
 671 static void
 672 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
 673                    struct tu_cs *cs,
 674                    const struct tu_image_view *iview,
 675                    uint32_t gmem_offset,
 676                    bool resolve)
 677 {
 678    tu_cs_emit_regs(cs,
 679                    A6XX_RB_BLIT_INFO(.unk0 = !resolve, .gmem = !resolve));
 680
 681    const struct tu_native_format *format =
 682       tu6_get_native_format(iview->vk_format);
 683    assert(format && format->rb >= 0);
 684
 685    enum a6xx_tile_mode tile_mode =
 686       tu6_get_image_tile_mode(iview->image, iview->base_mip);
 687    tu_cs_emit_regs(cs,
 688                    A6XX_RB_BLIT_DST_INFO(
 689                       .tile_mode = tile_mode,
 690                       .samples = tu_msaa_samples(iview->image->samples),
 691                       .color_format = format->rb,
 692                       .color_swap = format->swap,
 693                       .flags = iview->image->layout.ubwc_layer_size != 0),
 694                    A6XX_RB_BLIT_DST(tu_image_view_base_ref(iview)),
 695                    A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)),
 696                    A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layout.layer_size));
 697
 698    if (iview->image->layout.ubwc_layer_size) {
 699       tu_cs_emit_regs(cs,
 700                       A6XX_RB_BLIT_FLAG_DST(tu_image_view_ubwc_base_ref(iview)),
 701                       A6XX_RB_BLIT_FLAG_DST_PITCH(tu_image_view_ubwc_pitches(iview)));
 702    }
 703
 704    tu_cs_emit_regs(cs,
 705                    A6XX_RB_BLIT_BASE_GMEM(gmem_offset));
 706 }
 707
 708 static void
 709 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 710 {
 711    tu6_emit_event_write(cmd, cs, BLIT, false);
 712 }
 713
 714 static void
 715 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
 716                         struct tu_cs *cs,
 717                         uint32_t x1,
 718                         uint32_t y1,
 719                         uint32_t x2,
 720                         uint32_t y2)
 721 {
 722    tu_cs_emit_regs(cs,
 723                    A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
 724                    A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
 725
 726    tu_cs_emit_regs(cs,
 727                    A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
 728                    A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
 729 }
 730
 731 static void
 732 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
 733                        struct tu_cs *cs,
 734                        uint32_t x1,
 735                        uint32_t y1)
 736 {
 737    tu_cs_emit_regs(cs,
 738                    A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
 739
 740    tu_cs_emit_regs(cs,
 741                    A6XX_RB_WINDOW_OFFSET2(.x = x1, .y = y1));
 742
 743    tu_cs_emit_regs(cs,
 744                    A6XX_SP_WINDOW_OFFSET(.x = x1, .y = y1));
 745
 746    tu_cs_emit_regs(cs,
 747                    A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
 748 }
 749
 750 static bool
 751 use_hw_binning(struct tu_cmd_buffer *cmd)
 752 {
 753    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 754
 755    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
 756       return false;
 757
 758    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN))
 759       return true;
 760
 761    return (tiling->tile_count.width * tiling->tile_count.height) > 2;
 762 }
 763
 764 static bool
 765 use_sysmem_rendering(struct tu_cmd_buffer *cmd)
 766 {
 767    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_SYSMEM))
 768       return true;
 769
 770    return cmd->state.tiling_config.force_sysmem;
 771 }
 772
 773 static void
 774 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
 775                      struct tu_cs *cs,
 776                      const struct tu_tile *tile)
 777 {
 778    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 779    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD));
 780
 781    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 782    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
 783
 784    const uint32_t x1 = tile->begin.x;
 785    const uint32_t y1 = tile->begin.y;
 786    const uint32_t x2 = tile->end.x - 1;
 787    const uint32_t y2 = tile->end.y - 1;
 788    tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
 789    tu6_emit_window_offset(cmd, cs, x1, y1);
 790
 791    tu_cs_emit_regs(cs,
 792                    A6XX_VPC_SO_OVERRIDE(.so_disable = true));
 793
 794    if (use_hw_binning(cmd)) {
 795       tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
 796
 797       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 798       tu_cs_emit(cs, 0x0);
 799
 800       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
 801       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
 802                      A6XX_CP_REG_TEST_0_BIT(0) |
 803                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
 804
 805       tu_cs_reserve(cs, 3 + 11);
 806       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 807       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
 808       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(11));
 809
 810       /* if (no overflow) */ {
 811          tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
 812          tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
 813                         CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
 814          tu_cs_emit_qw(cs, cmd->vsc_data.iova + tile->pipe * cmd->vsc_data_pitch);
 815          tu_cs_emit_qw(cs, cmd->vsc_data.iova + (tile->pipe * 4) + (32 * cmd->vsc_data_pitch));
 816          tu_cs_emit_qw(cs, cmd->vsc_data2.iova + (tile->pipe * cmd->vsc_data2_pitch));
 817
 818          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 819          tu_cs_emit(cs, 0x0);
 820
 821          /* use a NOP packet to skip over the 'else' side: */
 822          tu_cs_emit_pkt7(cs, CP_NOP, 2);
 823       } /* else */ {
 824          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 825          tu_cs_emit(cs, 0x1);
 826       }
 827
 828       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 829       tu_cs_emit(cs, 0x0);
 830
 831       tu_cs_emit_regs(cs,
 832                       A6XX_RB_UNKNOWN_8804(0));
 833
 834       tu_cs_emit_regs(cs,
 835                       A6XX_SP_TP_UNKNOWN_B304(0));
 836
 837       tu_cs_emit_regs(cs,
 838                       A6XX_GRAS_UNKNOWN_80A4(0));
 839    } else {
 840       tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 841       tu_cs_emit(cs, 0x1);
 842
 843       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 844       tu_cs_emit(cs, 0x0);
 845    }
 846 }
 847
 848 static void
 849 tu6_emit_load_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a)
 850 {
 851    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 852    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 853    const struct tu_image_view *iview = fb->attachments[a].attachment;
 854    const struct tu_render_pass_attachment *attachment =
 855       &cmd->state.pass->attachments[a];
 856
 857    if (attachment->gmem_offset < 0)
 858       return;
 859
 860    const uint32_t x1 = tiling->render_area.offset.x;
 861    const uint32_t y1 = tiling->render_area.offset.y;
 862    const uint32_t x2 = x1 + tiling->render_area.extent.width;
 863    const uint32_t y2 = y1 + tiling->render_area.extent.height;
 864    const uint32_t tile_x2 =
 865       tiling->tile0.offset.x + tiling->tile0.extent.width * tiling->tile_count.width;
 866    const uint32_t tile_y2 =
 867       tiling->tile0.offset.y + tiling->tile0.extent.height * tiling->tile_count.height;
 868    bool need_load =
 869       x1 != tiling->tile0.offset.x || x2 != MIN2(fb->width, tile_x2) ||
 870       y1 != tiling->tile0.offset.y || y2 != MIN2(fb->height, tile_y2);
 871
 872    if (need_load)
 873       tu_finishme("improve handling of unaligned render area");
 874
 875    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
 876       need_load = true;
 877
 878    if (vk_format_has_stencil(iview->vk_format) &&
 879        attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
 880       need_load = true;
 881
 882    if (need_load) {
 883       tu6_emit_blit_info(cmd, cs, iview, attachment->gmem_offset, false);
 884       tu6_emit_blit(cmd, cs);
 885    }
 886 }
 887
 888 static void
 889 tu6_emit_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
 890                           uint32_t a,
 891                           const VkRenderPassBeginInfo *info)
 892 {
 893    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 894    const struct tu_image_view *iview = fb->attachments[a].attachment;
 895    const struct tu_render_pass_attachment *attachment =
 896       &cmd->state.pass->attachments[a];
 897    unsigned clear_mask = 0;
 898
 899    /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
 900    if (attachment->gmem_offset < 0)
 901       return;
 902
 903    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
 904       clear_mask = 0xf;
 905
 906    if (vk_format_has_stencil(iview->vk_format)) {
 907       clear_mask &= 0x1;
 908       if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
 909          clear_mask |= 0x2;
 910    }
 911    if (!clear_mask)
 912       return;
 913
 914    tu_clear_gmem_attachment(cmd, cs, a, clear_mask,
 915                             &info->pClearValues[a]);
 916 }
 917
 918 static void
 919 tu6_emit_predicated_blit(struct tu_cmd_buffer *cmd,
 920                          struct tu_cs *cs,
 921                          uint32_t a,
 922                          uint32_t gmem_a,
 923                          bool resolve)
 924 {
 925    const uint32_t space = 14 + 6;
 926    struct tu_cond_exec_state state;
 927
 928    VkResult result = tu_cond_exec_start(cmd->device, cs, &state,
 929                                         CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
 930                                         CP_COND_REG_EXEC_0_GMEM,
 931                                         space);
 932    if (result != VK_SUCCESS) {
 933       cmd->record_result = result;
 934       return;
 935    }
 936
 937    tu6_emit_blit_info(cmd, cs,
 938                       cmd->state.framebuffer->attachments[a].attachment,
 939                       cmd->state.pass->attachments[gmem_a].gmem_offset, resolve);
 940    tu6_emit_blit(cmd, cs);
 941
 942    tu_cond_exec_end(cs, &state);
 943 }
 944
 945 static void
 946 tu6_emit_sysmem_resolve(struct tu_cmd_buffer *cmd,
 947                         struct tu_cs *cs,
 948                         uint32_t a,
 949                         uint32_t gmem_a)
 950 {
 951    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 952    const struct tu_image_view *dst = fb->attachments[a].attachment;
 953    const struct tu_image_view *src = fb->attachments[gmem_a].attachment;
 954
 955    tu_blit(cmd, cs, &(struct tu_blit) {
 956       .dst = sysmem_attachment_surf(dst, dst->base_layer,
 957                                     &cmd->state.tiling_config.render_area),
 958       .src = sysmem_attachment_surf(src, src->base_layer,
 959                                     &cmd->state.tiling_config.render_area),
 960       .layers = fb->layers,
 961    });
 962 }
 963
 964
 965 /* Emit a MSAA resolve operation, with both gmem and sysmem paths. */
 966 static void tu6_emit_resolve(struct tu_cmd_buffer *cmd,
 967                              struct tu_cs *cs,
 968                              uint32_t a,
 969                              uint32_t gmem_a)
 970 {
 971    if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
 972       return;
 973
 974    tu6_emit_predicated_blit(cmd, cs, a, gmem_a, true);
 975
 976    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 977    const uint32_t space = 25 + 66 * fb->layers + 17;
 978    struct tu_cond_exec_state state;
 979
 980    VkResult result = tu_cond_exec_start(cmd->device, cs, &state,
 981                                         CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
 982                                         CP_COND_REG_EXEC_0_SYSMEM,
 983                                         space);
 984    if (result != VK_SUCCESS) {
 985       cmd->record_result = result;
 986       return;
 987    }
 988
 989    tu6_emit_sysmem_resolve(cmd, cs, a, gmem_a);
 990    tu_cond_exec_end(cs, &state);
 991 }
 992
 993 static void
 994 tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
 995                           struct tu_cs *cs,
 996                           uint32_t a,
 997                           uint32_t gmem_a)
 998 {
 999    if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
1000       return;
1001
1002    tu6_emit_blit_info(cmd, cs,
1003                       cmd->state.framebuffer->attachments[a].attachment,
1004                       cmd->state.pass->attachments[gmem_a].gmem_offset, true);
1005    tu6_emit_blit(cmd, cs);
1006 }
1007
1008 static void
1009 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1010 {
1011    const struct tu_render_pass *pass = cmd->state.pass;
1012    const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
1013
1014    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1015    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1016                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1017                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
1018    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1019    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1020
1021    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1022    tu_cs_emit(cs, 0x0);
1023
1024    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1025    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
1026
1027    tu6_emit_blit_scissor(cmd, cs, true);
1028
1029    for (uint32_t a = 0; a < pass->attachment_count; ++a) {
1030       if (pass->attachments[a].gmem_offset >= 0)
1031          tu6_emit_store_attachment(cmd, cs, a, a);
1032    }
1033
1034    if (subpass->resolve_attachments) {
1035       for (unsigned i = 0; i < subpass->color_count; i++) {
1036          uint32_t a = subpass->resolve_attachments[i].attachment;
1037          if (a != VK_ATTACHMENT_UNUSED)
1038             tu6_emit_store_attachment(cmd, cs, a,
1039                                       subpass->color_attachments[i].attachment);
1040       }
1041    }
1042 }
1043
1044 static void
1045 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
1046 {
1047    tu_cs_emit_regs(cs,
1048                    A6XX_PC_RESTART_INDEX(restart_index));
1049 }
1050
1051 static void
1052 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1053 {
1054    tu6_emit_cache_flush(cmd, cs);
1055
1056    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
1057
1058    tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x10000000);
1059    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
1060    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1061    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
1062    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1063    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
1064    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1065    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1066    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1067
1068    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
1069    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1070    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
1071    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
1072    tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
1073    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
1074    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
1075    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1076    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
1077    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
1078    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
1079    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
1080    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1081    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
1082
1083    tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
1084
1085    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
1086    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
1087    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
1088
1089    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
1090    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
1091    tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
1092    tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
1093    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
1094    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
1095    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
1096    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
1097    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
1098    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
1099    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
1100    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
1101
1102    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
1103    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
1104
1105    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
1106    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
1107
1108    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
1109                         A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1110
1111    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
1112    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
1113    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
1114
1115    tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
1116    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
1117
1118    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
1119
1120    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
1121
1122    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
1123    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
1124    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1125    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1126    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
1127    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
1128    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
1129    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
1130    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
1131    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1132    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1133    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1134    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
1135    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1136    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1137    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1138    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
1139    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
1140    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
1141    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
1142    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1143
1144    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
1145
1146    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
1147
1148    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
1149
1150    /* we don't use this yet.. probably best to disable.. */
1151    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1152    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1153                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1154                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
1155    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1156    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1157
1158    tu_cs_emit_regs(cs,
1159                    A6XX_VPC_SO_BUFFER_BASE(0),
1160                    A6XX_VPC_SO_BUFFER_SIZE(0));
1161
1162    tu_cs_emit_regs(cs,
1163                    A6XX_VPC_SO_FLUSH_BASE(0));
1164
1165    tu_cs_emit_regs(cs,
1166                    A6XX_VPC_SO_BUF_CNTL(0));
1167
1168    tu_cs_emit_regs(cs,
1169                    A6XX_VPC_SO_BUFFER_OFFSET(0, 0));
1170
1171    tu_cs_emit_regs(cs,
1172                    A6XX_VPC_SO_BUFFER_BASE(1, 0),
1173                    A6XX_VPC_SO_BUFFER_SIZE(1, 0));
1174
1175    tu_cs_emit_regs(cs,
1176                    A6XX_VPC_SO_BUFFER_OFFSET(1, 0),
1177                    A6XX_VPC_SO_FLUSH_BASE(1, 0),
1178                    A6XX_VPC_SO_BUFFER_BASE(2, 0),
1179                    A6XX_VPC_SO_BUFFER_SIZE(2, 0));
1180
1181    tu_cs_emit_regs(cs,
1182                    A6XX_VPC_SO_BUFFER_OFFSET(2, 0),
1183                    A6XX_VPC_SO_FLUSH_BASE(2, 0),
1184                    A6XX_VPC_SO_BUFFER_BASE(3, 0),
1185                    A6XX_VPC_SO_BUFFER_SIZE(3, 0));
1186
1187    tu_cs_emit_regs(cs,
1188                    A6XX_VPC_SO_BUFFER_OFFSET(3, 0),
1189                    A6XX_VPC_SO_FLUSH_BASE(3, 0));
1190
1191    tu_cs_emit_regs(cs,
1192                    A6XX_SP_HS_CTRL_REG0(0));
1193
1194    tu_cs_emit_regs(cs,
1195                    A6XX_SP_GS_CTRL_REG0(0));
1196
1197    tu_cs_emit_regs(cs,
1198                    A6XX_GRAS_LRZ_CNTL(0));
1199
1200    tu_cs_emit_regs(cs,
1201                    A6XX_RB_LRZ_CNTL(0));
1202
1203    tu_cs_sanity_check(cs);
1204 }
1205
1206 static void
1207 tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1208 {
1209    unsigned seqno;
1210
1211    seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_AND_INV_EVENT, true);
1212
1213    tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
1214    tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1215                   CP_WAIT_REG_MEM_0_POLL_MEMORY);
1216    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1217    tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(seqno));
1218    tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
1219    tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1220
1221    seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1222
1223    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4);
1224    tu_cs_emit(cs, CP_WAIT_MEM_GTE_0_RESERVED(0));
1225    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1226    tu_cs_emit(cs, CP_WAIT_MEM_GTE_3_REF(seqno));
1227 }
1228
1229 static void
1230 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1231 {
1232    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1233
1234    tu_cs_emit_regs(cs,
1235                    A6XX_VSC_BIN_SIZE(.width = tiling->tile0.extent.width,
1236                                      .height = tiling->tile0.extent.height),
1237                    A6XX_VSC_SIZE_ADDRESS(.bo = &cmd->vsc_data,
1238                                          .bo_offset = 32 * cmd->vsc_data_pitch));
1239
1240    tu_cs_emit_regs(cs,
1241                    A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
1242                                       .ny = tiling->tile_count.height));
1243
1244    tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1245    for (unsigned i = 0; i < 32; i++)
1246       tu_cs_emit(cs, tiling->pipe_config[i]);
1247
1248    tu_cs_emit_regs(cs,
1249                    A6XX_VSC_PIPE_DATA2_ADDRESS(.bo = &cmd->vsc_data2),
1250                    A6XX_VSC_PIPE_DATA2_PITCH(cmd->vsc_data2_pitch),
1251                    A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd->vsc_data2.size));
1252
1253    tu_cs_emit_regs(cs,
1254                    A6XX_VSC_PIPE_DATA_ADDRESS(.bo = &cmd->vsc_data),
1255                    A6XX_VSC_PIPE_DATA_PITCH(cmd->vsc_data_pitch),
1256                    A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd->vsc_data.size));
1257 }
1258
1259 static void
1260 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1261 {
1262    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1263    const uint32_t used_pipe_count =
1264       tiling->pipe_count.width * tiling->pipe_count.height;
1265
1266    /* Clear vsc_scratch: */
1267    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
1268    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1269    tu_cs_emit(cs, 0x0);
1270
1271    /* Check for overflow, write vsc_scratch if detected: */
1272    for (int i = 0; i < used_pipe_count; i++) {
1273       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1274       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1275             CP_COND_WRITE5_0_WRITE_MEMORY);
1276       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
1277       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1278       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data_pitch));
1279       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1280       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1281       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_data_pitch));
1282
1283       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1284       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1285             CP_COND_WRITE5_0_WRITE_MEMORY);
1286       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
1287       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1288       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data2_pitch));
1289       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1290       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1291       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_data2_pitch));
1292    }
1293
1294    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1295
1296    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1297
1298    tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
1299    tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
1300          CP_MEM_TO_REG_0_CNT(1 - 1));
1301    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1302
1303    /*
1304     * This is a bit awkward, we really want a way to invert the
1305     * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1306     * execute cmds to use hwbinning when a bit is *not* set.  This
1307     * dance is to invert OVERFLOW_FLAG_REG
1308     *
1309     * A CP_NOP packet is used to skip executing the 'else' clause
1310     * if (b0 set)..
1311     */
1312
1313    /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1314    tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1315    tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1316          A6XX_CP_REG_TEST_0_BIT(0) |
1317          A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1318
1319    tu_cs_reserve(cs, 3 + 7);
1320    tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1321    tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1322    tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(7));
1323
1324    /* if (b0 set) */ {
1325       /*
1326        * On overflow, mirror the value to control->vsc_overflow
1327        * which CPU is checking to detect overflow (see
1328        * check_vsc_overflow())
1329        */
1330       tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1331       tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
1332             CP_REG_TO_MEM_0_CNT(0));
1333       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_OVERFLOW);
1334
1335       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1336       tu_cs_emit(cs, 0x0);
1337
1338       tu_cs_emit_pkt7(cs, CP_NOP, 2);  /* skip 'else' when 'if' is taken */
1339    } /* else */ {
1340       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1341       tu_cs_emit(cs, 0x1);
1342    }
1343 }
1344
1345 static void
1346 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1347 {
1348    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1349    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1350
1351    uint32_t x1 = tiling->tile0.offset.x;
1352    uint32_t y1 = tiling->tile0.offset.y;
1353    uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
1354    uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
1355
1356    tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
1357
1358    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1359    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1360
1361    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1362    tu_cs_emit(cs, 0x1);
1363
1364    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1365    tu_cs_emit(cs, 0x1);
1366
1367    tu_cs_emit_wfi(cs);
1368
1369    tu_cs_emit_regs(cs,
1370                    A6XX_VFD_MODE_CNTL(.binning_pass = true));
1371
1372    update_vsc_pipe(cmd, cs);
1373
1374    tu_cs_emit_regs(cs,
1375                    A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1376
1377    tu_cs_emit_regs(cs,
1378                    A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1379
1380    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1381    tu_cs_emit(cs, UNK_2C);
1382
1383    tu_cs_emit_regs(cs,
1384                    A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
1385
1386    tu_cs_emit_regs(cs,
1387                    A6XX_SP_TP_WINDOW_OFFSET(.x = 0, .y = 0));
1388
1389    /* emit IB to binning drawcmds: */
1390    tu_cs_emit_call(cs, &cmd->draw_cs);
1391
1392    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1393    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1394                   CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1395                   CP_SET_DRAW_STATE__0_GROUP_ID(0));
1396    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1397    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1398
1399    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1400    tu_cs_emit(cs, UNK_2D);
1401
1402    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1403    tu6_cache_flush(cmd, cs);
1404
1405    tu_cs_emit_wfi(cs);
1406
1407    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1408
1409    emit_vsc_overflow_test(cmd, cs);
1410
1411    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1412    tu_cs_emit(cs, 0x0);
1413
1414    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1415    tu_cs_emit(cs, 0x0);
1416
1417    tu_cs_emit_wfi(cs);
1418
1419    tu_cs_emit_regs(cs,
1420                    A6XX_RB_CCU_CNTL(.unknown = phys_dev->magic.RB_CCU_CNTL_gmem));
1421
1422    cmd->wait_for_idle = false;
1423 }
1424
1425 static void
1426 tu_emit_sysmem_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1427                                 uint32_t a,
1428                                 const VkRenderPassBeginInfo *info)
1429 {
1430    const struct tu_framebuffer *fb = cmd->state.framebuffer;
1431    const struct tu_image_view *iview = fb->attachments[a].attachment;
1432    const struct tu_render_pass_attachment *attachment =
1433       &cmd->state.pass->attachments[a];
1434    unsigned clear_mask = 0;
1435
1436    /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
1437    if (attachment->gmem_offset < 0)
1438       return;
1439
1440    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1441       clear_mask = 0xf;
1442    }
1443
1444    if (vk_format_has_stencil(iview->vk_format)) {
1445       clear_mask &= 0x1;
1446       if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
1447          clear_mask |= 0x2;
1448       if (clear_mask != 0x3)
1449          tu_finishme("depth/stencil only load op");
1450    }
1451
1452    if (!clear_mask)
1453       return;
1454
1455    tu_clear_sysmem_attachment(cmd, cs, a,
1456                               &info->pClearValues[a], &(struct VkClearRect) {
1457       .rect = info->renderArea,
1458       .baseArrayLayer = iview->base_layer,
1459       .layerCount = iview->layer_count,
1460    });
1461 }
1462
1463 static void
1464 tu_cmd_prepare_sysmem_clear_ib(struct tu_cmd_buffer *cmd,
1465                                const VkRenderPassBeginInfo *info)
1466 {
1467    const struct tu_framebuffer *fb = cmd->state.framebuffer;
1468    const uint32_t blit_cmd_space = 25 + 66 * fb->layers + 17;
1469    const uint32_t clear_space =
1470       blit_cmd_space * cmd->state.pass->attachment_count + 5;
1471
1472    struct tu_cs sub_cs;
1473
1474    VkResult result =
1475       tu_cs_begin_sub_stream(&cmd->sub_cs, clear_space, &sub_cs);
1476    if (result != VK_SUCCESS) {
1477       cmd->record_result = result;
1478       return;
1479    }
1480
1481    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1482       tu_emit_sysmem_clear_attachment(cmd, &sub_cs, i, info);
1483
1484    /* TODO: We shouldn't need this flush, but without it we'd have an empty IB
1485     * when nothing clears which we currently can't handle.
1486     */
1487    tu6_emit_event_write(cmd, &sub_cs, PC_CCU_FLUSH_COLOR_TS, true);
1488
1489    cmd->state.sysmem_clear_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1490 }
1491
1492 static void
1493 tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1494                         const struct VkRect2D *renderArea)
1495 {
1496    const struct tu_framebuffer *fb = cmd->state.framebuffer;
1497    if (fb->width > 0 && fb->height > 0) {
1498       tu6_emit_window_scissor(cmd, cs,
1499                               0, 0, fb->width - 1, fb->height - 1);
1500    } else {
1501       tu6_emit_window_scissor(cmd, cs, 0, 0, 0, 0);
1502    }
1503
1504    tu6_emit_window_offset(cmd, cs, 0, 0);
1505
1506    tu6_emit_bin_size(cs, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1507
1508    tu_cs_emit_ib(cs, &cmd->state.sysmem_clear_ib);
1509
1510    tu6_emit_lrz_flush(cmd, cs);
1511
1512    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1513    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
1514
1515    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1516    tu_cs_emit(cs, 0x0);
1517
1518    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_COLOR, false);
1519    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH, false);
1520    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1521
1522    tu6_emit_wfi(cmd, cs);
1523    tu_cs_emit_regs(cs,
1524                    A6XX_RB_CCU_CNTL(0x10000000));
1525
1526    /* enable stream-out, with sysmem there is only one pass: */
1527    tu_cs_emit_regs(cs,
1528                    A6XX_VPC_SO_OVERRIDE(.so_disable = false));
1529
1530    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1531    tu_cs_emit(cs, 0x1);
1532
1533    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1534    tu_cs_emit(cs, 0x0);
1535
1536    tu_cs_sanity_check(cs);
1537 }
1538
1539 static void
1540 tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1541 {
1542    /* Do any resolves of the last subpass. These are handled in the
1543     * tile_store_ib in the gmem path.
1544     */
1545
1546    const struct tu_subpass *subpass = cmd->state.subpass;
1547    if (subpass->resolve_attachments) {
1548       for (unsigned i = 0; i < subpass->color_count; i++) {
1549          uint32_t a = subpass->resolve_attachments[i].attachment;
1550          if (a != VK_ATTACHMENT_UNUSED)
1551             tu6_emit_sysmem_resolve(cmd, cs, a,
1552                                     subpass->color_attachments[i].attachment);
1553       }
1554    }
1555
1556    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1557
1558    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1559    tu_cs_emit(cs, 0x0);
1560
1561    tu6_emit_lrz_flush(cmd, cs);
1562
1563    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
1564    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
1565
1566    tu_cs_sanity_check(cs);
1567 }
1568
1569
1570 static void
1571 tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1572 {
1573    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1574
1575    tu6_emit_lrz_flush(cmd, cs);
1576
1577    /* lrz clear? */
1578
1579    tu6_emit_cache_flush(cmd, cs);
1580
1581    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1582    tu_cs_emit(cs, 0x0);
1583
1584    /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1585    tu6_emit_wfi(cmd, cs);
1586    tu_cs_emit_regs(cs,
1587                    A6XX_RB_CCU_CNTL(phys_dev->magic.RB_CCU_CNTL_gmem));
1588
1589    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1590    if (use_hw_binning(cmd)) {
1591       tu6_emit_bin_size(cs,
1592                         tiling->tile0.extent.width,
1593                         tiling->tile0.extent.height,
1594                         A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
1595
1596       tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true);
1597
1598       tu6_emit_binning_pass(cmd, cs);
1599
1600       tu6_emit_bin_size(cs,
1601                         tiling->tile0.extent.width,
1602                         tiling->tile0.extent.height,
1603                         A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
1604
1605       tu_cs_emit_regs(cs,
1606                       A6XX_VFD_MODE_CNTL(0));
1607
1608       tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1609
1610       tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1611
1612       tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1613       tu_cs_emit(cs, 0x1);
1614    } else {
1615       tu6_emit_bin_size(cs,
1616                         tiling->tile0.extent.width,
1617                         tiling->tile0.extent.height,
1618                         0x6000000);
1619    }
1620
1621    tu_cs_sanity_check(cs);
1622 }
1623
1624 static void
1625 tu6_render_tile(struct tu_cmd_buffer *cmd,
1626                 struct tu_cs *cs,
1627                 const struct tu_tile *tile)
1628 {
1629    tu6_emit_tile_select(cmd, cs, tile);
1630    tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1631
1632    tu_cs_emit_call(cs, &cmd->draw_cs);
1633    cmd->wait_for_idle = true;
1634
1635    if (use_hw_binning(cmd)) {
1636       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1637       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1638                      A6XX_CP_REG_TEST_0_BIT(0) |
1639                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1640
1641       tu_cs_reserve(cs, 3 + 2);
1642       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1643       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1644       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(2));
1645
1646       /* if (no overflow) */ {
1647          tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1648          tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
1649       }
1650    }
1651
1652    tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1653
1654    tu_cs_sanity_check(cs);
1655 }
1656
1657 static void
1658 tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1659 {
1660    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1661
1662    tu_cs_emit_regs(cs,
1663                    A6XX_GRAS_LRZ_CNTL(0));
1664
1665    tu6_emit_lrz_flush(cmd, cs);
1666
1667    tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1668
1669    tu_cs_sanity_check(cs);
1670 }
1671
1672 static void
1673 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1674 {
1675    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1676
1677    tu6_tile_render_begin(cmd, &cmd->cs);
1678
1679    for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1680       for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1681          struct tu_tile tile;
1682          tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1683          tu6_render_tile(cmd, &cmd->cs, &tile);
1684       }
1685    }
1686
1687    tu6_tile_render_end(cmd, &cmd->cs);
1688 }
1689
1690 static void
1691 tu_cmd_render_sysmem(struct tu_cmd_buffer *cmd)
1692 {
1693    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1694
1695    tu6_sysmem_render_begin(cmd, &cmd->cs, &tiling->render_area);
1696
1697    tu_cs_emit_call(&cmd->cs, &cmd->draw_cs);
1698    cmd->wait_for_idle = true;
1699
1700    tu6_sysmem_render_end(cmd, &cmd->cs);
1701 }
1702
1703 static void
1704 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd,
1705                             const VkRenderPassBeginInfo *info)
1706 {
1707    const uint32_t tile_load_space =
1708       2 * 3 /* blit_scissor */ +
1709       (20 /* load */ + 19 /* clear */) * cmd->state.pass->attachment_count +
1710       2 /* cache invalidate */;
1711
1712    struct tu_cs sub_cs;
1713
1714    VkResult result =
1715       tu_cs_begin_sub_stream(&cmd->sub_cs, tile_load_space, &sub_cs);
1716    if (result != VK_SUCCESS) {
1717       cmd->record_result = result;
1718       return;
1719    }
1720
1721    tu6_emit_blit_scissor(cmd, &sub_cs, true);
1722
1723    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1724       tu6_emit_load_attachment(cmd, &sub_cs, i);
1725
1726    tu6_emit_blit_scissor(cmd, &sub_cs, false);
1727
1728    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1729       tu6_emit_clear_attachment(cmd, &sub_cs, i, info);
1730
1731    /* invalidate because reading input attachments will cache GMEM and
1732     * the cache isn''t updated when GMEM is written
1733     * TODO: is there a no-cache bit for textures?
1734     */
1735    if (cmd->state.subpass->input_count)
1736       tu6_emit_event_write(cmd, &sub_cs, CACHE_INVALIDATE, false);
1737
1738    cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1739 }
1740
1741 static void
1742 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1743 {
1744    const uint32_t tile_store_space = 32 + 23 * cmd->state.pass->attachment_count;
1745    struct tu_cs sub_cs;
1746
1747    VkResult result =
1748       tu_cs_begin_sub_stream(&cmd->sub_cs, tile_store_space, &sub_cs);
1749    if (result != VK_SUCCESS) {
1750       cmd->record_result = result;
1751       return;
1752    }
1753
1754    /* emit to tile-store sub_cs */
1755    tu6_emit_tile_store(cmd, &sub_cs);
1756
1757    cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1758 }
1759
1760 static void
1761 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1762                             const VkRect2D *render_area)
1763 {
1764    const struct tu_device *dev = cmd->device;
1765    struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1766
1767    tiling->render_area = *render_area;
1768    tiling->force_sysmem = force_sysmem(cmd, render_area);
1769
1770    tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass->gmem_pixels);
1771    tu_tiling_config_update_pipe_layout(tiling, dev);
1772    tu_tiling_config_update_pipes(tiling, dev);
1773 }
1774
1775 const struct tu_dynamic_state default_dynamic_state = {
1776    .viewport =
1777      {
1778        .count = 0,
1779      },
1780    .scissor =
1781      {
1782        .count = 0,
1783      },
1784    .line_width = 1.0f,
1785    .depth_bias =
1786      {
1787        .bias = 0.0f,
1788        .clamp = 0.0f,
1789        .slope = 0.0f,
1790      },
1791    .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1792    .depth_bounds =
1793      {
1794        .min = 0.0f,
1795        .max = 1.0f,
1796      },
1797    .stencil_compare_mask =
1798      {
1799        .front = ~0u,
1800        .back = ~0u,
1801      },
1802    .stencil_write_mask =
1803      {
1804        .front = ~0u,
1805        .back = ~0u,
1806      },
1807    .stencil_reference =
1808      {
1809        .front = 0u,
1810        .back = 0u,
1811      },
1812 };
1813
1814 static void UNUSED /* FINISHME */
1815 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1816                       const struct tu_dynamic_state *src)
1817 {
1818    struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1819    uint32_t copy_mask = src->mask;
1820    uint32_t dest_mask = 0;
1821
1822    tu_use_args(cmd_buffer); /* FINISHME */
1823
1824    /* Make sure to copy the number of viewports/scissors because they can
1825     * only be specified at pipeline creation time.
1826     */
1827    dest->viewport.count = src->viewport.count;
1828    dest->scissor.count = src->scissor.count;
1829    dest->discard_rectangle.count = src->discard_rectangle.count;
1830
1831    if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1832       if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1833                  src->viewport.count * sizeof(VkViewport))) {
1834          typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1835                       src->viewport.count);
1836          dest_mask |= TU_DYNAMIC_VIEWPORT;
1837       }
1838    }
1839
1840    if (copy_mask & TU_DYNAMIC_SCISSOR) {
1841       if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1842                  src->scissor.count * sizeof(VkRect2D))) {
1843          typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1844                       src->scissor.count);
1845          dest_mask |= TU_DYNAMIC_SCISSOR;
1846       }
1847    }
1848
1849    if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1850       if (dest->line_width != src->line_width) {
1851          dest->line_width = src->line_width;
1852          dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1853       }
1854    }
1855
1856    if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1857       if (memcmp(&dest->depth_bias, &src->depth_bias,
1858                  sizeof(src->depth_bias))) {
1859          dest->depth_bias = src->depth_bias;
1860          dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1861       }
1862    }
1863
1864    if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1865       if (memcmp(&dest->blend_constants, &src->blend_constants,
1866                  sizeof(src->blend_constants))) {
1867          typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1868          dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1869       }
1870    }
1871
1872    if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1873       if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1874                  sizeof(src->depth_bounds))) {
1875          dest->depth_bounds = src->depth_bounds;
1876          dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1877       }
1878    }
1879
1880    if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1881       if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1882                  sizeof(src->stencil_compare_mask))) {
1883          dest->stencil_compare_mask = src->stencil_compare_mask;
1884          dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1885       }
1886    }
1887
1888    if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1889       if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1890                  sizeof(src->stencil_write_mask))) {
1891          dest->stencil_write_mask = src->stencil_write_mask;
1892          dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1893       }
1894    }
1895
1896    if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1897       if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1898                  sizeof(src->stencil_reference))) {
1899          dest->stencil_reference = src->stencil_reference;
1900          dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1901       }
1902    }
1903
1904    if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1905       if (memcmp(&dest->discard_rectangle.rectangles,
1906                  &src->discard_rectangle.rectangles,
1907                  src->discard_rectangle.count * sizeof(VkRect2D))) {
1908          typed_memcpy(dest->discard_rectangle.rectangles,
1909                       src->discard_rectangle.rectangles,
1910                       src->discard_rectangle.count);
1911          dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1912       }
1913    }
1914 }
1915
1916 static VkResult
1917 tu_create_cmd_buffer(struct tu_device *device,
1918                      struct tu_cmd_pool *pool,
1919                      VkCommandBufferLevel level,
1920                      VkCommandBuffer *pCommandBuffer)
1921 {
1922    struct tu_cmd_buffer *cmd_buffer;
1923    cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1924                           VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1925    if (cmd_buffer == NULL)
1926       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1927
1928    cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1929    cmd_buffer->device = device;
1930    cmd_buffer->pool = pool;
1931    cmd_buffer->level = level;
1932
1933    if (pool) {
1934       list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1935       cmd_buffer->queue_family_index = pool->queue_family_index;
1936
1937    } else {
1938       /* Init the pool_link so we can safely call list_del when we destroy
1939        * the command buffer
1940        */
1941       list_inithead(&cmd_buffer->pool_link);
1942       cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1943    }
1944
1945    tu_bo_list_init(&cmd_buffer->bo_list);
1946    tu_cs_init(&cmd_buffer->cs, device, TU_CS_MODE_GROW, 4096);
1947    tu_cs_init(&cmd_buffer->draw_cs, device, TU_CS_MODE_GROW, 4096);
1948    tu_cs_init(&cmd_buffer->draw_epilogue_cs, device, TU_CS_MODE_GROW, 4096);
1949    tu_cs_init(&cmd_buffer->sub_cs, device, TU_CS_MODE_SUB_STREAM, 2048);
1950
1951    *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1952
1953    list_inithead(&cmd_buffer->upload.list);
1954
1955    VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1956    if (result != VK_SUCCESS)
1957       goto fail_scratch_bo;
1958
1959    /* TODO: resize on overflow */
1960    cmd_buffer->vsc_data_pitch = device->vsc_data_pitch;
1961    cmd_buffer->vsc_data2_pitch = device->vsc_data2_pitch;
1962    cmd_buffer->vsc_data = device->vsc_data;
1963    cmd_buffer->vsc_data2 = device->vsc_data2;
1964
1965    return VK_SUCCESS;
1966
1967 fail_scratch_bo:
1968    list_del(&cmd_buffer->pool_link);
1969    return result;
1970 }
1971
1972 static void
1973 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1974 {
1975    tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1976
1977    list_del(&cmd_buffer->pool_link);
1978
1979    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1980       free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1981
1982    tu_cs_finish(&cmd_buffer->cs);
1983    tu_cs_finish(&cmd_buffer->draw_cs);
1984    tu_cs_finish(&cmd_buffer->draw_epilogue_cs);
1985    tu_cs_finish(&cmd_buffer->sub_cs);
1986
1987    tu_bo_list_destroy(&cmd_buffer->bo_list);
1988    vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1989 }
1990
1991 static VkResult
1992 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1993 {
1994    cmd_buffer->wait_for_idle = true;
1995
1996    cmd_buffer->record_result = VK_SUCCESS;
1997
1998    tu_bo_list_reset(&cmd_buffer->bo_list);
1999    tu_cs_reset(&cmd_buffer->cs);
2000    tu_cs_reset(&cmd_buffer->draw_cs);
2001    tu_cs_reset(&cmd_buffer->draw_epilogue_cs);
2002    tu_cs_reset(&cmd_buffer->sub_cs);
2003
2004    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
2005       cmd_buffer->descriptors[i].valid = 0;
2006       cmd_buffer->descriptors[i].push_dirty = false;
2007    }
2008
2009    cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
2010
2011    return cmd_buffer->record_result;
2012 }
2013
2014 VkResult
2015 tu_AllocateCommandBuffers(VkDevice _device,
2016                           const VkCommandBufferAllocateInfo *pAllocateInfo,
2017                           VkCommandBuffer *pCommandBuffers)
2018 {
2019    TU_FROM_HANDLE(tu_device, device, _device);
2020    TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
2021
2022    VkResult result = VK_SUCCESS;
2023    uint32_t i;
2024
2025    for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2026
2027       if (!list_is_empty(&pool->free_cmd_buffers)) {
2028          struct tu_cmd_buffer *cmd_buffer = list_first_entry(
2029             &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
2030
2031          list_del(&cmd_buffer->pool_link);
2032          list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2033
2034          result = tu_reset_cmd_buffer(cmd_buffer);
2035          cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2036          cmd_buffer->level = pAllocateInfo->level;
2037
2038          pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
2039       } else {
2040          result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
2041                                        &pCommandBuffers[i]);
2042       }
2043       if (result != VK_SUCCESS)
2044          break;
2045    }
2046
2047    if (result != VK_SUCCESS) {
2048       tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
2049                             pCommandBuffers);
2050
2051       /* From the Vulkan 1.0.66 spec:
2052        *
2053        * "vkAllocateCommandBuffers can be used to create multiple
2054        *  command buffers. If the creation of any of those command
2055        *  buffers fails, the implementation must destroy all
2056        *  successfully created command buffer objects from this
2057        *  command, set all entries of the pCommandBuffers array to
2058        *  NULL and return the error."
2059        */
2060       memset(pCommandBuffers, 0,
2061              sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2062    }
2063
2064    return result;
2065 }
2066
2067 void
2068 tu_FreeCommandBuffers(VkDevice device,
2069                       VkCommandPool commandPool,
2070                       uint32_t commandBufferCount,
2071                       const VkCommandBuffer *pCommandBuffers)
2072 {
2073    for (uint32_t i = 0; i < commandBufferCount; i++) {
2074       TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2075
2076       if (cmd_buffer) {
2077          if (cmd_buffer->pool) {
2078             list_del(&cmd_buffer->pool_link);
2079             list_addtail(&cmd_buffer->pool_link,
2080                          &cmd_buffer->pool->free_cmd_buffers);
2081          } else
2082             tu_cmd_buffer_destroy(cmd_buffer);
2083       }
2084    }
2085 }
2086
2087 VkResult
2088 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
2089                       VkCommandBufferResetFlags flags)
2090 {
2091    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2092    return tu_reset_cmd_buffer(cmd_buffer);
2093 }
2094
2095 VkResult
2096 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
2097                       const VkCommandBufferBeginInfo *pBeginInfo)
2098 {
2099    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2100    VkResult result = VK_SUCCESS;
2101
2102    if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
2103       /* If the command buffer has already been resetted with
2104        * vkResetCommandBuffer, no need to do it again.
2105        */
2106       result = tu_reset_cmd_buffer(cmd_buffer);
2107       if (result != VK_SUCCESS)
2108          return result;
2109    }
2110
2111    memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2112    cmd_buffer->usage_flags = pBeginInfo->flags;
2113
2114    tu_cs_begin(&cmd_buffer->cs);
2115    tu_cs_begin(&cmd_buffer->draw_cs);
2116    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
2117
2118    cmd_buffer->scratch_seqno = 0;
2119
2120    /* setup initial configuration into command buffer */
2121    if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2122       switch (cmd_buffer->queue_family_index) {
2123       case TU_QUEUE_GENERAL:
2124          tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
2125          break;
2126       default:
2127          break;
2128       }
2129    } else if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2130               (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2131       assert(pBeginInfo->pInheritanceInfo);
2132       cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2133       cmd_buffer->state.subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2134    }
2135
2136    cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
2137
2138    return VK_SUCCESS;
2139 }
2140
2141 void
2142 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
2143                         uint32_t firstBinding,
2144                         uint32_t bindingCount,
2145                         const VkBuffer *pBuffers,
2146                         const VkDeviceSize *pOffsets)
2147 {
2148    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2149
2150    assert(firstBinding + bindingCount <= MAX_VBS);
2151
2152    for (uint32_t i = 0; i < bindingCount; i++) {
2153       cmd->state.vb.buffers[firstBinding + i] =
2154          tu_buffer_from_handle(pBuffers[i]);
2155       cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
2156    }
2157
2158    /* VB states depend on VkPipelineVertexInputStateCreateInfo */
2159    cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
2160 }
2161
2162 void
2163 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
2164                       VkBuffer buffer,
2165                       VkDeviceSize offset,
2166                       VkIndexType indexType)
2167 {
2168    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2169    TU_FROM_HANDLE(tu_buffer, buf, buffer);
2170
2171    /* initialize/update the restart index */
2172    if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
2173       struct tu_cs *draw_cs = &cmd->draw_cs;
2174
2175       tu6_emit_restart_index(
2176          draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
2177
2178       tu_cs_sanity_check(draw_cs);
2179    }
2180
2181    /* track the BO */
2182    if (cmd->state.index_buffer != buf)
2183       tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
2184
2185    cmd->state.index_buffer = buf;
2186    cmd->state.index_offset = offset;
2187    cmd->state.index_type = indexType;
2188 }
2189
2190 void
2191 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
2192                          VkPipelineBindPoint pipelineBindPoint,
2193                          VkPipelineLayout _layout,
2194                          uint32_t firstSet,
2195                          uint32_t descriptorSetCount,
2196                          const VkDescriptorSet *pDescriptorSets,
2197                          uint32_t dynamicOffsetCount,
2198                          const uint32_t *pDynamicOffsets)
2199 {
2200    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2201    TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
2202    unsigned dyn_idx = 0;
2203
2204    struct tu_descriptor_state *descriptors_state =
2205       tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2206
2207    for (unsigned i = 0; i < descriptorSetCount; ++i) {
2208       unsigned idx = i + firstSet;
2209       TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
2210
2211       descriptors_state->sets[idx] = set;
2212       descriptors_state->valid |= (1u << idx);
2213
2214       for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2215          unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2216          assert(dyn_idx < dynamicOffsetCount);
2217
2218          descriptors_state->dynamic_buffers[idx] =
2219          set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
2220       }
2221    }
2222
2223    cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
2224 }
2225
2226 void
2227 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
2228                     VkPipelineLayout layout,
2229                     VkShaderStageFlags stageFlags,
2230                     uint32_t offset,
2231                     uint32_t size,
2232                     const void *pValues)
2233 {
2234    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2235    memcpy((void*) cmd->push_constants + offset, pValues, size);
2236    cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
2237 }
2238
2239 VkResult
2240 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
2241 {
2242    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2243
2244    if (cmd_buffer->scratch_seqno) {
2245       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
2246                      MSM_SUBMIT_BO_WRITE);
2247    }
2248
2249    if (cmd_buffer->use_vsc_data) {
2250       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data,
2251                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2252       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data2,
2253                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2254    }
2255
2256    for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
2257       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
2258                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2259    }
2260
2261    for (uint32_t i = 0; i < cmd_buffer->draw_epilogue_cs.bo_count; i++) {
2262       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_epilogue_cs.bos[i],
2263                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2264    }
2265
2266    for (uint32_t i = 0; i < cmd_buffer->sub_cs.bo_count; i++) {
2267       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->sub_cs.bos[i],
2268                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2269    }
2270
2271    tu_cs_end(&cmd_buffer->cs);
2272    tu_cs_end(&cmd_buffer->draw_cs);
2273    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
2274
2275    cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
2276
2277    return cmd_buffer->record_result;
2278 }
2279
2280 void
2281 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
2282                    VkPipelineBindPoint pipelineBindPoint,
2283                    VkPipeline _pipeline)
2284 {
2285    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2286    TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2287
2288    switch (pipelineBindPoint) {
2289    case VK_PIPELINE_BIND_POINT_GRAPHICS:
2290       cmd->state.pipeline = pipeline;
2291       cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
2292       break;
2293    case VK_PIPELINE_BIND_POINT_COMPUTE:
2294       cmd->state.compute_pipeline = pipeline;
2295       cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
2296       break;
2297    default:
2298       unreachable("unrecognized pipeline bind point");
2299       break;
2300    }
2301
2302    tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2303                   MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2304    for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2305       tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2306                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2307    }
2308 }
2309
2310 void
2311 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2312                   uint32_t firstViewport,
2313                   uint32_t viewportCount,
2314                   const VkViewport *pViewports)
2315 {
2316    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2317    struct tu_cs *draw_cs = &cmd->draw_cs;
2318
2319    assert(firstViewport == 0 && viewportCount == 1);
2320    tu6_emit_viewport(draw_cs, pViewports);
2321
2322    tu_cs_sanity_check(draw_cs);
2323 }
2324
2325 void
2326 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2327                  uint32_t firstScissor,
2328                  uint32_t scissorCount,
2329                  const VkRect2D *pScissors)
2330 {
2331    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2332    struct tu_cs *draw_cs = &cmd->draw_cs;
2333
2334    assert(firstScissor == 0 && scissorCount == 1);
2335    tu6_emit_scissor(draw_cs, pScissors);
2336
2337    tu_cs_sanity_check(draw_cs);
2338 }
2339
2340 void
2341 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2342 {
2343    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2344
2345    cmd->state.dynamic.line_width = lineWidth;
2346
2347    /* line width depends on VkPipelineRasterizationStateCreateInfo */
2348    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2349 }
2350
2351 void
2352 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2353                    float depthBiasConstantFactor,
2354                    float depthBiasClamp,
2355                    float depthBiasSlopeFactor)
2356 {
2357    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2358    struct tu_cs *draw_cs = &cmd->draw_cs;
2359
2360    tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
2361                        depthBiasSlopeFactor);
2362
2363    tu_cs_sanity_check(draw_cs);
2364 }
2365
2366 void
2367 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2368                         const float blendConstants[4])
2369 {
2370    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2371    struct tu_cs *draw_cs = &cmd->draw_cs;
2372
2373    tu6_emit_blend_constants(draw_cs, blendConstants);
2374
2375    tu_cs_sanity_check(draw_cs);
2376 }
2377
2378 void
2379 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2380                      float minDepthBounds,
2381                      float maxDepthBounds)
2382 {
2383 }
2384
2385 void
2386 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2387                             VkStencilFaceFlags faceMask,
2388                             uint32_t compareMask)
2389 {
2390    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2391
2392    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2393       cmd->state.dynamic.stencil_compare_mask.front = compareMask;
2394    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2395       cmd->state.dynamic.stencil_compare_mask.back = compareMask;
2396
2397    /* the front/back compare masks must be updated together */
2398    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2399 }
2400
2401 void
2402 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2403                           VkStencilFaceFlags faceMask,
2404                           uint32_t writeMask)
2405 {
2406    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2407
2408    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2409       cmd->state.dynamic.stencil_write_mask.front = writeMask;
2410    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2411       cmd->state.dynamic.stencil_write_mask.back = writeMask;
2412
2413    /* the front/back write masks must be updated together */
2414    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2415 }
2416
2417 void
2418 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2419                           VkStencilFaceFlags faceMask,
2420                           uint32_t reference)
2421 {
2422    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2423
2424    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2425       cmd->state.dynamic.stencil_reference.front = reference;
2426    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2427       cmd->state.dynamic.stencil_reference.back = reference;
2428
2429    /* the front/back references must be updated together */
2430    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2431 }
2432
2433 void
2434 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2435                       uint32_t commandBufferCount,
2436                       const VkCommandBuffer *pCmdBuffers)
2437 {
2438    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2439    VkResult result;
2440
2441    assert(commandBufferCount > 0);
2442
2443    for (uint32_t i = 0; i < commandBufferCount; i++) {
2444       TU_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
2445
2446       result = tu_bo_list_merge(&cmd->bo_list, &secondary->bo_list);
2447       if (result != VK_SUCCESS) {
2448          cmd->record_result = result;
2449          break;
2450       }
2451
2452       result = tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
2453       if (result != VK_SUCCESS) {
2454          cmd->record_result = result;
2455          break;
2456       }
2457
2458       result = tu_cs_add_entries(&cmd->draw_epilogue_cs,
2459             &secondary->draw_epilogue_cs);
2460       if (result != VK_SUCCESS) {
2461          cmd->record_result = result;
2462          break;
2463       }
2464    }
2465    cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
2466 }
2467
2468 VkResult
2469 tu_CreateCommandPool(VkDevice _device,
2470                      const VkCommandPoolCreateInfo *pCreateInfo,
2471                      const VkAllocationCallbacks *pAllocator,
2472                      VkCommandPool *pCmdPool)
2473 {
2474    TU_FROM_HANDLE(tu_device, device, _device);
2475    struct tu_cmd_pool *pool;
2476
2477    pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2478                     VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2479    if (pool == NULL)
2480       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2481
2482    if (pAllocator)
2483       pool->alloc = *pAllocator;
2484    else
2485       pool->alloc = device->alloc;
2486
2487    list_inithead(&pool->cmd_buffers);
2488    list_inithead(&pool->free_cmd_buffers);
2489
2490    pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2491
2492    *pCmdPool = tu_cmd_pool_to_handle(pool);
2493
2494    return VK_SUCCESS;
2495 }
2496
2497 void
2498 tu_DestroyCommandPool(VkDevice _device,
2499                       VkCommandPool commandPool,
2500                       const VkAllocationCallbacks *pAllocator)
2501 {
2502    TU_FROM_HANDLE(tu_device, device, _device);
2503    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2504
2505    if (!pool)
2506       return;
2507
2508    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2509                             &pool->cmd_buffers, pool_link)
2510    {
2511       tu_cmd_buffer_destroy(cmd_buffer);
2512    }
2513
2514    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2515                             &pool->free_cmd_buffers, pool_link)
2516    {
2517       tu_cmd_buffer_destroy(cmd_buffer);
2518    }
2519
2520    vk_free2(&device->alloc, pAllocator, pool);
2521 }
2522
2523 VkResult
2524 tu_ResetCommandPool(VkDevice device,
2525                     VkCommandPool commandPool,
2526                     VkCommandPoolResetFlags flags)
2527 {
2528    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2529    VkResult result;
2530
2531    list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2532                        pool_link)
2533    {
2534       result = tu_reset_cmd_buffer(cmd_buffer);
2535       if (result != VK_SUCCESS)
2536          return result;
2537    }
2538
2539    return VK_SUCCESS;
2540 }
2541
2542 void
2543 tu_TrimCommandPool(VkDevice device,
2544                    VkCommandPool commandPool,
2545                    VkCommandPoolTrimFlags flags)
2546 {
2547    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2548
2549    if (!pool)
2550       return;
2551
2552    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2553                             &pool->free_cmd_buffers, pool_link)
2554    {
2555       tu_cmd_buffer_destroy(cmd_buffer);
2556    }
2557 }
2558
2559 void
2560 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2561                       const VkRenderPassBeginInfo *pRenderPassBegin,
2562                       VkSubpassContents contents)
2563 {
2564    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2565    TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2566    TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
2567
2568    cmd->state.pass = pass;
2569    cmd->state.subpass = pass->subpasses;
2570    cmd->state.framebuffer = fb;
2571
2572    tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
2573    tu_cmd_prepare_sysmem_clear_ib(cmd, pRenderPassBegin);
2574    tu_cmd_prepare_tile_load_ib(cmd, pRenderPassBegin);
2575    tu_cmd_prepare_tile_store_ib(cmd);
2576
2577    tu6_emit_zs(cmd, cmd->state.subpass, &cmd->draw_cs);
2578    tu6_emit_mrt(cmd, cmd->state.subpass, &cmd->draw_cs);
2579    tu6_emit_msaa(cmd, cmd->state.subpass, &cmd->draw_cs);
2580    tu6_emit_render_cntl(cmd, cmd->state.subpass, &cmd->draw_cs, false);
2581
2582    /* note: use_hw_binning only checks tiling config */
2583    if (use_hw_binning(cmd))
2584       cmd->use_vsc_data = true;
2585
2586    for (uint32_t i = 0; i < fb->attachment_count; ++i) {
2587       const struct tu_image_view *iview = fb->attachments[i].attachment;
2588       tu_bo_list_add(&cmd->bo_list, iview->image->bo,
2589                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2590    }
2591 }
2592
2593 void
2594 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
2595                        const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2596                        const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2597 {
2598    tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2599                          pSubpassBeginInfo->contents);
2600 }
2601
2602 void
2603 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2604 {
2605    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2606    const struct tu_render_pass *pass = cmd->state.pass;
2607    struct tu_cs *cs = &cmd->draw_cs;
2608
2609    const struct tu_subpass *subpass = cmd->state.subpass++;
2610    /* TODO:
2611     * if msaa samples change between subpasses,
2612     * attachment store is broken for some attachments
2613     */
2614    if (subpass->resolve_attachments) {
2615       tu6_emit_blit_scissor(cmd, cs, true);
2616       for (unsigned i = 0; i < subpass->color_count; i++) {
2617          uint32_t a = subpass->resolve_attachments[i].attachment;
2618          if (a != VK_ATTACHMENT_UNUSED) {
2619             tu6_emit_resolve(cmd, cs, a,
2620                              subpass->color_attachments[i].attachment);
2621          }
2622       }
2623    }
2624
2625    /* invalidate because reading input attachments will cache GMEM and
2626     * the cache isn''t updated when GMEM is written
2627     * TODO: is there a no-cache bit for textures?
2628     */
2629    if (cmd->state.subpass->input_count)
2630       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2631
2632    /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2633    tu6_emit_zs(cmd, cmd->state.subpass, cs);
2634    tu6_emit_mrt(cmd, cmd->state.subpass, cs);
2635    tu6_emit_msaa(cmd, cmd->state.subpass, cs);
2636    tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, false);
2637
2638    /* Emit flushes so that input attachments will read the correct value. This
2639     * is for sysmem only, although it shouldn't do much harm on gmem.
2640     */
2641    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
2642    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
2643
2644    /* TODO:
2645     * since we don't know how to do GMEM->GMEM resolve,
2646     * resolve attachments are resolved to memory then loaded to GMEM again if needed
2647     */
2648    if (subpass->resolve_attachments) {
2649       for (unsigned i = 0; i < subpass->color_count; i++) {
2650          uint32_t a = subpass->resolve_attachments[i].attachment;
2651          if (a != VK_ATTACHMENT_UNUSED && pass->attachments[a].gmem_offset >= 0) {
2652                tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
2653                tu6_emit_predicated_blit(cmd, cs, a, a, false);
2654          }
2655       }
2656    }
2657 }
2658
2659 void
2660 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
2661                    const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2662                    const VkSubpassEndInfoKHR *pSubpassEndInfo)
2663 {
2664    tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2665 }
2666
2667 struct tu_draw_info
2668 {
2669    /**
2670     * Number of vertices.
2671     */
2672    uint32_t count;
2673
2674    /**
2675     * Index of the first vertex.
2676     */
2677    int32_t vertex_offset;
2678
2679    /**
2680     * First instance id.
2681     */
2682    uint32_t first_instance;
2683
2684    /**
2685     * Number of instances.
2686     */
2687    uint32_t instance_count;
2688
2689    /**
2690     * First index (indexed draws only).
2691     */
2692    uint32_t first_index;
2693
2694    /**
2695     * Whether it's an indexed draw.
2696     */
2697    bool indexed;
2698
2699    /**
2700     * Indirect draw parameters resource.
2701     */
2702    struct tu_buffer *indirect;
2703    uint64_t indirect_offset;
2704    uint32_t stride;
2705
2706    /**
2707     * Draw count parameters resource.
2708     */
2709    struct tu_buffer *count_buffer;
2710    uint64_t count_buffer_offset;
2711 };
2712
2713 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2714 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2715
2716 enum tu_draw_state_group_id
2717 {
2718    TU_DRAW_STATE_PROGRAM,
2719    TU_DRAW_STATE_PROGRAM_BINNING,
2720    TU_DRAW_STATE_VI,
2721    TU_DRAW_STATE_VI_BINNING,
2722    TU_DRAW_STATE_VP,
2723    TU_DRAW_STATE_RAST,
2724    TU_DRAW_STATE_DS,
2725    TU_DRAW_STATE_BLEND,
2726    TU_DRAW_STATE_VS_CONST,
2727    TU_DRAW_STATE_FS_CONST,
2728    TU_DRAW_STATE_VS_TEX,
2729    TU_DRAW_STATE_FS_TEX_SYSMEM,
2730    TU_DRAW_STATE_FS_TEX_GMEM,
2731    TU_DRAW_STATE_FS_IBO,
2732    TU_DRAW_STATE_VS_PARAMS,
2733
2734    TU_DRAW_STATE_COUNT,
2735 };
2736
2737 struct tu_draw_state_group
2738 {
2739    enum tu_draw_state_group_id id;
2740    uint32_t enable_mask;
2741    struct tu_cs_entry ib;
2742 };
2743
2744 const static struct tu_sampler*
2745 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2746             const struct tu_descriptor_map *map, unsigned i,
2747             unsigned array_index)
2748 {
2749    assert(descriptors_state->valid & (1 << map->set[i]));
2750
2751    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2752    assert(map->binding[i] < set->layout->binding_count);
2753
2754    const struct tu_descriptor_set_binding_layout *layout =
2755       &set->layout->binding[map->binding[i]];
2756
2757    if (layout->immutable_samplers_offset) {
2758       const struct tu_sampler *immutable_samplers =
2759          tu_immutable_samplers(set->layout, layout);
2760
2761       return &immutable_samplers[array_index];
2762    }
2763
2764    switch (layout->type) {
2765    case VK_DESCRIPTOR_TYPE_SAMPLER:
2766       return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2767    case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2768       return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS +
2769                                                    array_index *
2770                                                    (A6XX_TEX_CONST_DWORDS +
2771                                                     sizeof(struct tu_sampler) / 4)];
2772    default:
2773       unreachable("unimplemented descriptor type");
2774       break;
2775    }
2776 }
2777
2778 static void
2779 write_tex_const(struct tu_cmd_buffer *cmd,
2780                 uint32_t *dst,
2781                 struct tu_descriptor_state *descriptors_state,
2782                 const struct tu_descriptor_map *map,
2783                 unsigned i, unsigned array_index, bool is_sysmem)
2784 {
2785    assert(descriptors_state->valid & (1 << map->set[i]));
2786
2787    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2788    assert(map->binding[i] < set->layout->binding_count);
2789
2790    const struct tu_descriptor_set_binding_layout *layout =
2791       &set->layout->binding[map->binding[i]];
2792
2793    switch (layout->type) {
2794    case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2795    case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2796    case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2797    case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
2798       memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2799                                    array_index * A6XX_TEX_CONST_DWORDS],
2800              A6XX_TEX_CONST_DWORDS * 4);
2801       break;
2802    case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2803       memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2804                                    array_index *
2805                                    (A6XX_TEX_CONST_DWORDS +
2806                                     sizeof(struct tu_sampler) / 4)],
2807              A6XX_TEX_CONST_DWORDS * 4);
2808       break;
2809    default:
2810       unreachable("unimplemented descriptor type");
2811       break;
2812    }
2813
2814    if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT && !is_sysmem) {
2815       const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2816       uint32_t a = cmd->state.subpass->input_attachments[map->value[i] +
2817                                                          array_index].attachment;
2818       const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
2819
2820       assert(att->gmem_offset >= 0);
2821
2822       dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
2823       dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
2824       dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
2825       dst[2] |=
2826          A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
2827          A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
2828       dst[3] = 0;
2829       dst[4] = 0x100000 + att->gmem_offset;
2830       dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
2831       for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2832          dst[i] = 0;
2833
2834       if (cmd->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
2835          tu_finishme("patch input attachment pitch for secondary cmd buffer");
2836    }
2837 }
2838
2839 static void
2840 write_image_ibo(struct tu_cmd_buffer *cmd,
2841                 uint32_t *dst,
2842                 struct tu_descriptor_state *descriptors_state,
2843                 const struct tu_descriptor_map *map,
2844                 unsigned i, unsigned array_index)
2845 {
2846    assert(descriptors_state->valid & (1 << map->set[i]));
2847
2848    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2849    assert(map->binding[i] < set->layout->binding_count);
2850
2851    const struct tu_descriptor_set_binding_layout *layout =
2852       &set->layout->binding[map->binding[i]];
2853
2854    assert(layout->type == VK_DESCRIPTOR_TYPE_STORAGE_IMAGE);
2855
2856    memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2857                                 (array_index * 2 + 1) * A6XX_TEX_CONST_DWORDS],
2858           A6XX_TEX_CONST_DWORDS * 4);
2859 }
2860
2861 static uint64_t
2862 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2863            const struct tu_descriptor_map *map,
2864            unsigned i, unsigned array_index)
2865 {
2866    assert(descriptors_state->valid & (1 << map->set[i]));
2867
2868    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2869    assert(map->binding[i] < set->layout->binding_count);
2870
2871    const struct tu_descriptor_set_binding_layout *layout =
2872       &set->layout->binding[map->binding[i]];
2873
2874    switch (layout->type) {
2875    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2876    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2877       return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset +
2878                                                 array_index];
2879    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2880    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2881       return (uint64_t) set->mapped_ptr[layout->offset / 4 + array_index * 2 + 1] << 32 |
2882                         set->mapped_ptr[layout->offset / 4 + array_index * 2];
2883    default:
2884       unreachable("unimplemented descriptor type");
2885       break;
2886    }
2887 }
2888
2889 static inline uint32_t
2890 tu6_stage2opcode(gl_shader_stage type)
2891 {
2892    switch (type) {
2893    case MESA_SHADER_VERTEX:
2894    case MESA_SHADER_TESS_CTRL:
2895    case MESA_SHADER_TESS_EVAL:
2896    case MESA_SHADER_GEOMETRY:
2897       return CP_LOAD_STATE6_GEOM;
2898    case MESA_SHADER_FRAGMENT:
2899    case MESA_SHADER_COMPUTE:
2900    case MESA_SHADER_KERNEL:
2901       return CP_LOAD_STATE6_FRAG;
2902    default:
2903       unreachable("bad shader type");
2904    }
2905 }
2906
2907 static inline enum a6xx_state_block
2908 tu6_stage2shadersb(gl_shader_stage type)
2909 {
2910    switch (type) {
2911    case MESA_SHADER_VERTEX:
2912       return SB6_VS_SHADER;
2913    case MESA_SHADER_FRAGMENT:
2914       return SB6_FS_SHADER;
2915    case MESA_SHADER_COMPUTE:
2916    case MESA_SHADER_KERNEL:
2917       return SB6_CS_SHADER;
2918    default:
2919       unreachable("bad shader type");
2920       return ~0;
2921    }
2922 }
2923
2924 static void
2925 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2926                      struct tu_descriptor_state *descriptors_state,
2927                      gl_shader_stage type,
2928                      uint32_t *push_constants)
2929 {
2930    const struct tu_program_descriptor_linkage *link =
2931       &pipeline->program.link[type];
2932    const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2933
2934    for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2935       if (state->range[i].start < state->range[i].end) {
2936          uint32_t size = state->range[i].end - state->range[i].start;
2937          uint32_t offset = state->range[i].start;
2938
2939          /* and even if the start of the const buffer is before
2940           * first_immediate, the end may not be:
2941           */
2942          size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2943
2944          if (size == 0)
2945             continue;
2946
2947          /* things should be aligned to vec4: */
2948          debug_assert((state->range[i].offset % 16) == 0);
2949          debug_assert((size % 16) == 0);
2950          debug_assert((offset % 16) == 0);
2951
2952          if (i == 0) {
2953             /* push constants */
2954             tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2955             tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2956                   CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2957                   CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2958                   CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2959                   CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2960             tu_cs_emit(cs, 0);
2961             tu_cs_emit(cs, 0);
2962             for (unsigned i = 0; i < size / 4; i++)
2963                tu_cs_emit(cs, push_constants[i + offset / 4]);
2964             continue;
2965          }
2966
2967          /* Look through the UBO map to find our UBO index, and get the VA for
2968           * that UBO.
2969           */
2970          uint64_t va = 0;
2971          uint32_t ubo_idx = i - 1;
2972          uint32_t ubo_map_base = 0;
2973          for (int j = 0; j < link->ubo_map.num; j++) {
2974             if (ubo_idx >= ubo_map_base &&
2975                 ubo_idx < ubo_map_base + link->ubo_map.array_size[j]) {
2976                va = buffer_ptr(descriptors_state, &link->ubo_map, j,
2977                                ubo_idx - ubo_map_base);
2978                break;
2979             }
2980             ubo_map_base += link->ubo_map.array_size[j];
2981          }
2982          assert(va);
2983
2984          tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2985          tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2986                CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2987                CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2988                CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2989                CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2990          tu_cs_emit_qw(cs, va + offset);
2991       }
2992    }
2993 }
2994
2995 static void
2996 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2997               struct tu_descriptor_state *descriptors_state,
2998               gl_shader_stage type)
2999 {
3000    const struct tu_program_descriptor_linkage *link =
3001       &pipeline->program.link[type];
3002
3003    uint32_t num = MIN2(link->ubo_map.num_desc, link->const_state.num_ubos);
3004    uint32_t anum = align(num, 2);
3005
3006    if (!num)
3007       return;
3008
3009    tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
3010    tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
3011          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3012          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3013          CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3014          CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
3015    tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
3016    tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
3017
3018    unsigned emitted = 0;
3019    for (unsigned i = 0; emitted < num && i < link->ubo_map.num; i++) {
3020       for (unsigned j = 0; emitted < num && j < link->ubo_map.array_size[i]; j++) {
3021          tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i, j));
3022          emitted++;
3023       }
3024    }
3025
3026    for (; emitted < anum; emitted++) {
3027       tu_cs_emit(cs, 0xffffffff);
3028       tu_cs_emit(cs, 0xffffffff);
3029    }
3030 }
3031
3032 static struct tu_cs_entry
3033 tu6_emit_consts(struct tu_cmd_buffer *cmd,
3034                 const struct tu_pipeline *pipeline,
3035                 struct tu_descriptor_state *descriptors_state,
3036                 gl_shader_stage type)
3037 {
3038    struct tu_cs cs;
3039    tu_cs_begin_sub_stream(&cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
3040
3041    tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
3042    tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
3043
3044    return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
3045 }
3046
3047 static VkResult
3048 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
3049                    const struct tu_draw_info *draw,
3050                    struct tu_cs_entry *entry)
3051 {
3052    /* TODO: fill out more than just base instance */
3053    const struct tu_program_descriptor_linkage *link =
3054       &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
3055    const struct ir3_const_state *const_state = &link->const_state;
3056    struct tu_cs cs;
3057
3058    if (const_state->offsets.driver_param >= link->constlen) {
3059       *entry = (struct tu_cs_entry) {};
3060       return VK_SUCCESS;
3061    }
3062
3063    VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 8, &cs);
3064    if (result != VK_SUCCESS)
3065       return result;
3066
3067    tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
3068    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(const_state->offsets.driver_param) |
3069          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3070          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3071          CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
3072          CP_LOAD_STATE6_0_NUM_UNIT(1));
3073    tu_cs_emit(&cs, 0);
3074    tu_cs_emit(&cs, 0);
3075
3076    STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
3077
3078    tu_cs_emit(&cs, 0);
3079    tu_cs_emit(&cs, 0);
3080    tu_cs_emit(&cs, draw->first_instance);
3081    tu_cs_emit(&cs, 0);
3082
3083    *entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
3084    return VK_SUCCESS;
3085 }
3086
3087 static VkResult
3088 tu6_emit_textures(struct tu_cmd_buffer *cmd,
3089                   const struct tu_pipeline *pipeline,
3090                   struct tu_descriptor_state *descriptors_state,
3091                   gl_shader_stage type,
3092                   struct tu_cs_entry *entry,
3093                   bool *needs_border,
3094                   bool is_sysmem)
3095 {
3096    struct tu_cs *draw_state = &cmd->sub_cs;
3097    const struct tu_program_descriptor_linkage *link =
3098       &pipeline->program.link[type];
3099    VkResult result;
3100
3101    if (link->texture_map.num_desc == 0 && link->sampler_map.num_desc == 0) {
3102       *entry = (struct tu_cs_entry) {};
3103       return VK_SUCCESS;
3104    }
3105
3106    /* allocate and fill texture state */
3107    struct ts_cs_memory tex_const;
3108    result = tu_cs_alloc(draw_state, link->texture_map.num_desc,
3109                         A6XX_TEX_CONST_DWORDS, &tex_const);
3110    if (result != VK_SUCCESS)
3111       return result;
3112
3113    int tex_index = 0;
3114    for (unsigned i = 0; i < link->texture_map.num; i++) {
3115       for (int j = 0; j < link->texture_map.array_size[i]; j++) {
3116          write_tex_const(cmd,
3117                          &tex_const.map[A6XX_TEX_CONST_DWORDS * tex_index++],
3118                          descriptors_state, &link->texture_map, i, j,
3119                          is_sysmem);
3120       }
3121    }
3122
3123    /* allocate and fill sampler state */
3124    struct ts_cs_memory tex_samp = { 0 };
3125    if (link->sampler_map.num_desc) {
3126       result = tu_cs_alloc(draw_state, link->sampler_map.num_desc,
3127                            A6XX_TEX_SAMP_DWORDS, &tex_samp);
3128       if (result != VK_SUCCESS)
3129          return result;
3130
3131       int sampler_index = 0;
3132       for (unsigned i = 0; i < link->sampler_map.num; i++) {
3133          for (int j = 0; j < link->sampler_map.array_size[i]; j++) {
3134             const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3135                                                            &link->sampler_map,
3136                                                            i, j);
3137             memcpy(&tex_samp.map[A6XX_TEX_SAMP_DWORDS * sampler_index++],
3138                    sampler->state, sizeof(sampler->state));
3139             *needs_border |= sampler->needs_border;
3140          }
3141       }
3142    }
3143
3144    unsigned tex_samp_reg, tex_const_reg, tex_count_reg;
3145    enum a6xx_state_block sb;
3146
3147    switch (type) {
3148    case MESA_SHADER_VERTEX:
3149       sb = SB6_VS_TEX;
3150       tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
3151       tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
3152       tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
3153       break;
3154    case MESA_SHADER_FRAGMENT:
3155       sb = SB6_FS_TEX;
3156       tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
3157       tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
3158       tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
3159       break;
3160    case MESA_SHADER_COMPUTE:
3161       sb = SB6_CS_TEX;
3162       tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
3163       tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
3164       tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
3165       break;
3166    default:
3167       unreachable("bad state block");
3168    }
3169
3170    struct tu_cs cs;
3171    result = tu_cs_begin_sub_stream(draw_state, 16, &cs);
3172    if (result != VK_SUCCESS)
3173       return result;
3174
3175    if (link->sampler_map.num_desc) {
3176       /* output sampler state: */
3177       tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
3178       tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3179                  CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
3180                  CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3181                  CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3182                  CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num_desc));
3183       tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
3184
3185       tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
3186       tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
3187    }
3188
3189    /* emit texture state: */
3190    tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
3191    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3192       CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3193       CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3194       CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3195       CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num_desc));
3196    tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
3197
3198    tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
3199    tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
3200
3201    tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
3202    tu_cs_emit(&cs, link->texture_map.num_desc);
3203
3204    *entry = tu_cs_end_sub_stream(draw_state, &cs);
3205    return VK_SUCCESS;
3206 }
3207
3208 static VkResult
3209 tu6_emit_ibo(struct tu_cmd_buffer *cmd,
3210              const struct tu_pipeline *pipeline,
3211              struct tu_descriptor_state *descriptors_state,
3212              gl_shader_stage type,
3213              struct tu_cs_entry *entry)
3214 {
3215    struct tu_cs *draw_state = &cmd->sub_cs;
3216    const struct tu_program_descriptor_linkage *link =
3217       &pipeline->program.link[type];
3218    VkResult result;
3219
3220    unsigned num_desc = link->ssbo_map.num_desc + link->image_map.num_desc;
3221
3222    if (num_desc == 0) {
3223       *entry = (struct tu_cs_entry) {};
3224       return VK_SUCCESS;
3225    }
3226
3227    struct ts_cs_memory ibo_const;
3228    result = tu_cs_alloc(draw_state, num_desc,
3229                         A6XX_TEX_CONST_DWORDS, &ibo_const);
3230    if (result != VK_SUCCESS)
3231       return result;
3232
3233    int ssbo_index = 0;
3234    for (unsigned i = 0; i < link->ssbo_map.num; i++) {
3235       for (int j = 0; j < link->ssbo_map.array_size[i]; j++) {
3236          uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
3237
3238          uint64_t va = buffer_ptr(descriptors_state, &link->ssbo_map, i, j);
3239          /* We don't expose robustBufferAccess, so leave the size unlimited. */
3240          uint32_t sz = MAX_STORAGE_BUFFER_RANGE / 4;
3241
3242          dst[0] = A6XX_IBO_0_FMT(FMT6_32_UINT);
3243          dst[1] = A6XX_IBO_1_WIDTH(sz & MASK(15)) |
3244                   A6XX_IBO_1_HEIGHT(sz >> 15);
3245          dst[2] = A6XX_IBO_2_UNK4 |
3246                   A6XX_IBO_2_UNK31 |
3247                   A6XX_IBO_2_TYPE(A6XX_TEX_1D);
3248          dst[3] = 0;
3249          dst[4] = va;
3250          dst[5] = va >> 32;
3251          for (int i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
3252             dst[i] = 0;
3253
3254          ssbo_index++;
3255       }
3256    }
3257
3258    for (unsigned i = 0; i < link->image_map.num; i++) {
3259       for (int j = 0; j < link->image_map.array_size[i]; j++) {
3260          uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
3261
3262          write_image_ibo(cmd, dst,
3263                          descriptors_state, &link->image_map, i, j);
3264
3265          ssbo_index++;
3266       }
3267    }
3268
3269    assert(ssbo_index == num_desc);
3270
3271    struct tu_cs cs;
3272    result = tu_cs_begin_sub_stream(draw_state, 7, &cs);
3273    if (result != VK_SUCCESS)
3274       return result;
3275
3276    uint32_t opcode, ibo_addr_reg;
3277    enum a6xx_state_block sb;
3278    enum a6xx_state_type st;
3279
3280    switch (type) {
3281    case MESA_SHADER_FRAGMENT:
3282       opcode = CP_LOAD_STATE6;
3283       st = ST6_SHADER;
3284       sb = SB6_IBO;
3285       ibo_addr_reg = REG_A6XX_SP_IBO_LO;
3286       break;
3287    case MESA_SHADER_COMPUTE:
3288       opcode = CP_LOAD_STATE6_FRAG;
3289       st = ST6_IBO;
3290       sb = SB6_CS_SHADER;
3291       ibo_addr_reg = REG_A6XX_SP_CS_IBO_LO;
3292       break;
3293    default:
3294       unreachable("unsupported stage for ibos");
3295    }
3296
3297    /* emit texture state: */
3298    tu_cs_emit_pkt7(&cs, opcode, 3);
3299    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3300               CP_LOAD_STATE6_0_STATE_TYPE(st) |
3301               CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3302               CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3303               CP_LOAD_STATE6_0_NUM_UNIT(num_desc));
3304    tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3305
3306    tu_cs_emit_pkt4(&cs, ibo_addr_reg, 2);
3307    tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3308
3309    *entry = tu_cs_end_sub_stream(draw_state, &cs);
3310    return VK_SUCCESS;
3311 }
3312
3313 struct PACKED bcolor_entry {
3314    uint32_t fp32[4];
3315    uint16_t ui16[4];
3316    int16_t  si16[4];
3317    uint16_t fp16[4];
3318    uint16_t rgb565;
3319    uint16_t rgb5a1;
3320    uint16_t rgba4;
3321    uint8_t __pad0[2];
3322    uint8_t  ui8[4];
3323    int8_t   si8[4];
3324    uint32_t rgb10a2;
3325    uint32_t z24; /* also s8? */
3326    uint16_t srgb[4];      /* appears to duplicate fp16[], but clamped, used for srgb */
3327    uint8_t  __pad1[56];
3328 } border_color[] = {
3329    [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] = {},
3330    [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK] = {},
3331    [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] = {
3332       .fp32[3] = 0x3f800000,
3333       .ui16[3] = 0xffff,
3334       .si16[3] = 0x7fff,
3335       .fp16[3] = 0x3c00,
3336       .rgb5a1 = 0x8000,
3337       .rgba4 = 0xf000,
3338       .ui8[3] = 0xff,
3339       .si8[3] = 0x7f,
3340       .rgb10a2 = 0xc0000000,
3341       .srgb[3] = 0x3c00,
3342    },
3343    [VK_BORDER_COLOR_INT_OPAQUE_BLACK] = {
3344       .fp32[3] = 1,
3345       .fp16[3] = 1,
3346    },
3347    [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE] = {
3348       .fp32[0 ... 3] = 0x3f800000,
3349       .ui16[0 ... 3] = 0xffff,
3350       .si16[0 ... 3] = 0x7fff,
3351       .fp16[0 ... 3] = 0x3c00,
3352       .rgb565 = 0xffff,
3353       .rgb5a1 = 0xffff,
3354       .rgba4 = 0xffff,
3355       .ui8[0 ... 3] = 0xff,
3356       .si8[0 ... 3] = 0x7f,
3357       .rgb10a2 = 0xffffffff,
3358       .z24 = 0xffffff,
3359       .srgb[0 ... 3] = 0x3c00,
3360    },
3361    [VK_BORDER_COLOR_INT_OPAQUE_WHITE] = {
3362       .fp32[0 ... 3] = 1,
3363       .fp16[0 ... 3] = 1,
3364    },
3365 };
3366
3367 static VkResult
3368 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
3369                       struct tu_cs *cs)
3370 {
3371    STATIC_ASSERT(sizeof(struct bcolor_entry) == 128);
3372
3373    const struct tu_pipeline *pipeline = cmd->state.pipeline;
3374    struct tu_descriptor_state *descriptors_state =
3375       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3376    const struct tu_descriptor_map *vs_sampler =
3377       &pipeline->program.link[MESA_SHADER_VERTEX].sampler_map;
3378    const struct tu_descriptor_map *fs_sampler =
3379       &pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map;
3380    struct ts_cs_memory ptr;
3381
3382    VkResult result = tu_cs_alloc(&cmd->sub_cs,
3383                                  vs_sampler->num_desc + fs_sampler->num_desc,
3384                                  128 / 4,
3385                                  &ptr);
3386    if (result != VK_SUCCESS)
3387       return result;
3388
3389    for (unsigned i = 0; i < vs_sampler->num; i++) {
3390       for (unsigned j = 0; j < vs_sampler->array_size[i]; j++) {
3391          const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3392                                                         vs_sampler, i, j);
3393          memcpy(ptr.map, &border_color[sampler->border], 128);
3394          ptr.map += 128 / 4;
3395       }
3396    }
3397
3398    for (unsigned i = 0; i < fs_sampler->num; i++) {
3399       for (unsigned j = 0; j < fs_sampler->array_size[i]; j++) {
3400          const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3401                                                         fs_sampler, i, j);
3402          memcpy(ptr.map, &border_color[sampler->border], 128);
3403          ptr.map += 128 / 4;
3404       }
3405    }
3406
3407    tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
3408    tu_cs_emit_qw(cs, ptr.iova);
3409    return VK_SUCCESS;
3410 }
3411
3412 static VkResult
3413 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
3414                      struct tu_cs *cs,
3415                      const struct tu_draw_info *draw)
3416 {
3417    const struct tu_pipeline *pipeline = cmd->state.pipeline;
3418    const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
3419    struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
3420    uint32_t draw_state_group_count = 0;
3421    VkResult result;
3422
3423    struct tu_descriptor_state *descriptors_state =
3424       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3425
3426    /* TODO lrz */
3427
3428    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
3429    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
3430    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
3431
3432    tu_cs_emit_regs(cs,
3433                    A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart =
3434                                             pipeline->ia.primitive_restart && draw->indexed));
3435
3436    if (cmd->state.dirty &
3437           (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
3438        (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
3439       tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
3440                             dynamic->line_width);
3441    }
3442
3443    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
3444        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
3445       tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
3446                                     dynamic->stencil_compare_mask.back);
3447    }
3448
3449    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
3450        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
3451       tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
3452                                   dynamic->stencil_write_mask.back);
3453    }
3454
3455    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
3456        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
3457       tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
3458                                  dynamic->stencil_reference.back);
3459    }
3460
3461    if (cmd->state.dirty &
3462        (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
3463       for (uint32_t i = 0; i < pipeline->vi.count; i++) {
3464          const uint32_t binding = pipeline->vi.bindings[i];
3465          const uint32_t stride = pipeline->vi.strides[i];
3466          const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
3467          const VkDeviceSize offset = buf->bo_offset +
3468                                      cmd->state.vb.offsets[binding] +
3469                                      pipeline->vi.offsets[i];
3470          const VkDeviceSize size =
3471             offset < buf->bo->size ? buf->bo->size - offset : 0;
3472
3473          tu_cs_emit_regs(cs,
3474                          A6XX_VFD_FETCH_BASE(i, .bo = buf->bo, .bo_offset = offset),
3475                          A6XX_VFD_FETCH_SIZE(i, size),
3476                          A6XX_VFD_FETCH_STRIDE(i, stride));
3477       }
3478    }
3479
3480    if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
3481       draw_state_groups[draw_state_group_count++] =
3482          (struct tu_draw_state_group) {
3483             .id = TU_DRAW_STATE_PROGRAM,
3484             .enable_mask = ENABLE_DRAW,
3485             .ib = pipeline->program.state_ib,
3486          };
3487       draw_state_groups[draw_state_group_count++] =
3488          (struct tu_draw_state_group) {
3489             .id = TU_DRAW_STATE_PROGRAM_BINNING,
3490             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3491             .ib = pipeline->program.binning_state_ib,
3492          };
3493       draw_state_groups[draw_state_group_count++] =
3494          (struct tu_draw_state_group) {
3495             .id = TU_DRAW_STATE_VI,
3496             .enable_mask = ENABLE_DRAW,
3497             .ib = pipeline->vi.state_ib,
3498          };
3499       draw_state_groups[draw_state_group_count++] =
3500          (struct tu_draw_state_group) {
3501             .id = TU_DRAW_STATE_VI_BINNING,
3502             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3503             .ib = pipeline->vi.binning_state_ib,
3504          };
3505       draw_state_groups[draw_state_group_count++] =
3506          (struct tu_draw_state_group) {
3507             .id = TU_DRAW_STATE_VP,
3508             .enable_mask = ENABLE_ALL,
3509             .ib = pipeline->vp.state_ib,
3510          };
3511       draw_state_groups[draw_state_group_count++] =
3512          (struct tu_draw_state_group) {
3513             .id = TU_DRAW_STATE_RAST,
3514             .enable_mask = ENABLE_ALL,
3515             .ib = pipeline->rast.state_ib,
3516          };
3517       draw_state_groups[draw_state_group_count++] =
3518          (struct tu_draw_state_group) {
3519             .id = TU_DRAW_STATE_DS,
3520             .enable_mask = ENABLE_ALL,
3521             .ib = pipeline->ds.state_ib,
3522          };
3523       draw_state_groups[draw_state_group_count++] =
3524          (struct tu_draw_state_group) {
3525             .id = TU_DRAW_STATE_BLEND,
3526             .enable_mask = ENABLE_ALL,
3527             .ib = pipeline->blend.state_ib,
3528          };
3529    }
3530
3531    if (cmd->state.dirty &
3532          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_PUSH_CONSTANTS)) {
3533       draw_state_groups[draw_state_group_count++] =
3534          (struct tu_draw_state_group) {
3535             .id = TU_DRAW_STATE_VS_CONST,
3536             .enable_mask = ENABLE_ALL,
3537             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
3538          };
3539       draw_state_groups[draw_state_group_count++] =
3540          (struct tu_draw_state_group) {
3541             .id = TU_DRAW_STATE_FS_CONST,
3542             .enable_mask = ENABLE_DRAW,
3543             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
3544          };
3545    }
3546
3547    if (cmd->state.dirty &
3548          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
3549       bool needs_border = false;
3550       struct tu_cs_entry vs_tex, fs_tex_sysmem, fs_tex_gmem, fs_ibo;
3551
3552       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3553                                  MESA_SHADER_VERTEX, &vs_tex, &needs_border,
3554                                  false);
3555       if (result != VK_SUCCESS)
3556          return result;
3557
3558       /* TODO: we could emit just one texture descriptor draw state when there
3559        * are no input attachments, which is the most common case. We could
3560        * also split out the sampler state, which doesn't change even for input
3561        * attachments.
3562        */
3563       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3564                                  MESA_SHADER_FRAGMENT, &fs_tex_sysmem,
3565                                  &needs_border, true);
3566       if (result != VK_SUCCESS)
3567          return result;
3568
3569       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3570                                  MESA_SHADER_FRAGMENT, &fs_tex_gmem,
3571                                  &needs_border, false);
3572       if (result != VK_SUCCESS)
3573          return result;
3574
3575       result = tu6_emit_ibo(cmd, pipeline, descriptors_state,
3576                             MESA_SHADER_FRAGMENT, &fs_ibo);
3577       if (result != VK_SUCCESS)
3578          return result;
3579
3580       draw_state_groups[draw_state_group_count++] =
3581          (struct tu_draw_state_group) {
3582             .id = TU_DRAW_STATE_VS_TEX,
3583             .enable_mask = ENABLE_ALL,
3584             .ib = vs_tex,
3585          };
3586       draw_state_groups[draw_state_group_count++] =
3587          (struct tu_draw_state_group) {
3588             .id = TU_DRAW_STATE_FS_TEX_GMEM,
3589             .enable_mask = CP_SET_DRAW_STATE__0_GMEM,
3590             .ib = fs_tex_gmem,
3591          };
3592       draw_state_groups[draw_state_group_count++] =
3593          (struct tu_draw_state_group) {
3594             .id = TU_DRAW_STATE_FS_TEX_SYSMEM,
3595             .enable_mask = CP_SET_DRAW_STATE__0_SYSMEM,
3596             .ib = fs_tex_sysmem,
3597          };
3598       draw_state_groups[draw_state_group_count++] =
3599          (struct tu_draw_state_group) {
3600             .id = TU_DRAW_STATE_FS_IBO,
3601             .enable_mask = ENABLE_DRAW,
3602             .ib = fs_ibo,
3603          };
3604
3605       if (needs_border) {
3606          result = tu6_emit_border_color(cmd, cs);
3607          if (result != VK_SUCCESS)
3608             return result;
3609       }
3610    }
3611
3612    struct tu_cs_entry vs_params;
3613    result = tu6_emit_vs_params(cmd, draw, &vs_params);
3614    if (result != VK_SUCCESS)
3615       return result;
3616
3617    draw_state_groups[draw_state_group_count++] =
3618       (struct tu_draw_state_group) {
3619          .id = TU_DRAW_STATE_VS_PARAMS,
3620          .enable_mask = ENABLE_ALL,
3621          .ib = vs_params,
3622       };
3623
3624    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
3625    for (uint32_t i = 0; i < draw_state_group_count; i++) {
3626       const struct tu_draw_state_group *group = &draw_state_groups[i];
3627       debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
3628       uint32_t cp_set_draw_state =
3629          CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
3630          group->enable_mask |
3631          CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
3632       uint64_t iova;
3633       if (group->ib.size) {
3634          iova = group->ib.bo->iova + group->ib.offset;
3635       } else {
3636          cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
3637          iova = 0;
3638       }
3639
3640       tu_cs_emit(cs, cp_set_draw_state);
3641       tu_cs_emit_qw(cs, iova);
3642    }
3643
3644    tu_cs_sanity_check(cs);
3645
3646    /* track BOs */
3647    if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
3648       for (uint32_t i = 0; i < MAX_VBS; i++) {
3649          const struct tu_buffer *buf = cmd->state.vb.buffers[i];
3650          if (buf)
3651             tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
3652       }
3653    }
3654    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3655       unsigned i;
3656       for_each_bit(i, descriptors_state->valid) {
3657          struct tu_descriptor_set *set = descriptors_state->sets[i];
3658          for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3659             if (set->descriptors[j]) {
3660                tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3661                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3662             }
3663       }
3664    }
3665
3666    /* Fragment shader state overwrites compute shader state, so flag the
3667     * compute pipeline for re-emit.
3668     */
3669    cmd->state.dirty = TU_CMD_DIRTY_COMPUTE_PIPELINE;
3670    return VK_SUCCESS;
3671 }
3672
3673 static void
3674 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
3675                      struct tu_cs *cs,
3676                      const struct tu_draw_info *draw)
3677 {
3678
3679    const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3680
3681    tu_cs_emit_regs(cs,
3682                    A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
3683                    A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
3684
3685    /* TODO hw binning */
3686    if (draw->indexed) {
3687       const enum a4xx_index_size index_size =
3688          tu6_index_size(cmd->state.index_type);
3689       const uint32_t index_bytes =
3690          (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3691       const struct tu_buffer *buf = cmd->state.index_buffer;
3692       const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
3693                                   index_bytes * draw->first_index;
3694       const uint32_t size = index_bytes * draw->count;
3695
3696       const uint32_t cp_draw_indx =
3697          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3698          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3699          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3700          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3701
3702       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
3703       tu_cs_emit(cs, cp_draw_indx);
3704       tu_cs_emit(cs, draw->instance_count);
3705       tu_cs_emit(cs, draw->count);
3706       tu_cs_emit(cs, 0x0); /* XXX */
3707       tu_cs_emit_qw(cs, buf->bo->iova + offset);
3708       tu_cs_emit(cs, size);
3709    } else {
3710       const uint32_t cp_draw_indx =
3711          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3712          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3713          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3714
3715       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
3716       tu_cs_emit(cs, cp_draw_indx);
3717       tu_cs_emit(cs, draw->instance_count);
3718       tu_cs_emit(cs, draw->count);
3719    }
3720 }
3721
3722 static void
3723 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
3724 {
3725    struct tu_cs *cs = &cmd->draw_cs;
3726    VkResult result;
3727
3728    result = tu6_bind_draw_states(cmd, cs, draw);
3729    if (result != VK_SUCCESS) {
3730       cmd->record_result = result;
3731       return;
3732    }
3733
3734    if (draw->indirect) {
3735       tu_finishme("indirect draw");
3736       return;
3737    }
3738
3739    tu6_emit_draw_direct(cmd, cs, draw);
3740
3741    cmd->wait_for_idle = true;
3742
3743    tu_cs_sanity_check(cs);
3744 }
3745
3746 void
3747 tu_CmdDraw(VkCommandBuffer commandBuffer,
3748            uint32_t vertexCount,
3749            uint32_t instanceCount,
3750            uint32_t firstVertex,
3751            uint32_t firstInstance)
3752 {
3753    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3754    struct tu_draw_info info = {};
3755
3756    info.count = vertexCount;
3757    info.instance_count = instanceCount;
3758    info.first_instance = firstInstance;
3759    info.vertex_offset = firstVertex;
3760
3761    tu_draw(cmd_buffer, &info);
3762 }
3763
3764 void
3765 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3766                   uint32_t indexCount,
3767                   uint32_t instanceCount,
3768                   uint32_t firstIndex,
3769                   int32_t vertexOffset,
3770                   uint32_t firstInstance)
3771 {
3772    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3773    struct tu_draw_info info = {};
3774
3775    info.indexed = true;
3776    info.count = indexCount;
3777    info.instance_count = instanceCount;
3778    info.first_index = firstIndex;
3779    info.vertex_offset = vertexOffset;
3780    info.first_instance = firstInstance;
3781
3782    tu_draw(cmd_buffer, &info);
3783 }
3784
3785 void
3786 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3787                    VkBuffer _buffer,
3788                    VkDeviceSize offset,
3789                    uint32_t drawCount,
3790                    uint32_t stride)
3791 {
3792    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3793    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3794    struct tu_draw_info info = {};
3795
3796    info.count = drawCount;
3797    info.indirect = buffer;
3798    info.indirect_offset = offset;
3799    info.stride = stride;
3800
3801    tu_draw(cmd_buffer, &info);
3802 }
3803
3804 void
3805 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3806                           VkBuffer _buffer,
3807                           VkDeviceSize offset,
3808                           uint32_t drawCount,
3809                           uint32_t stride)
3810 {
3811    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3812    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3813    struct tu_draw_info info = {};
3814
3815    info.indexed = true;
3816    info.count = drawCount;
3817    info.indirect = buffer;
3818    info.indirect_offset = offset;
3819    info.stride = stride;
3820
3821    tu_draw(cmd_buffer, &info);
3822 }
3823
3824 struct tu_dispatch_info
3825 {
3826    /**
3827     * Determine the layout of the grid (in block units) to be used.
3828     */
3829    uint32_t blocks[3];
3830
3831    /**
3832     * A starting offset for the grid. If unaligned is set, the offset
3833     * must still be aligned.
3834     */
3835    uint32_t offsets[3];
3836    /**
3837     * Whether it's an unaligned compute dispatch.
3838     */
3839    bool unaligned;
3840
3841    /**
3842     * Indirect compute parameters resource.
3843     */
3844    struct tu_buffer *indirect;
3845    uint64_t indirect_offset;
3846 };
3847
3848 static void
3849 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3850                               const struct tu_dispatch_info *info)
3851 {
3852    gl_shader_stage type = MESA_SHADER_COMPUTE;
3853    const struct tu_program_descriptor_linkage *link =
3854       &pipeline->program.link[type];
3855    const struct ir3_const_state *const_state = &link->const_state;
3856    uint32_t offset = const_state->offsets.driver_param;
3857
3858    if (link->constlen <= offset)
3859       return;
3860
3861    if (!info->indirect) {
3862       uint32_t driver_params[IR3_DP_CS_COUNT] = {
3863          [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
3864          [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
3865          [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
3866          [IR3_DP_LOCAL_GROUP_SIZE_X] = pipeline->compute.local_size[0],
3867          [IR3_DP_LOCAL_GROUP_SIZE_Y] = pipeline->compute.local_size[1],
3868          [IR3_DP_LOCAL_GROUP_SIZE_Z] = pipeline->compute.local_size[2],
3869       };
3870
3871       uint32_t num_consts = MIN2(const_state->num_driver_params,
3872                                  (link->constlen - offset) * 4);
3873       /* push constants */
3874       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
3875       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
3876                  CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3877                  CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3878                  CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3879                  CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
3880       tu_cs_emit(cs, 0);
3881       tu_cs_emit(cs, 0);
3882       uint32_t i;
3883       for (i = 0; i < num_consts; i++)
3884          tu_cs_emit(cs, driver_params[i]);
3885    } else {
3886       tu_finishme("Indirect driver params");
3887    }
3888 }
3889
3890 static void
3891 tu_dispatch(struct tu_cmd_buffer *cmd,
3892             const struct tu_dispatch_info *info)
3893 {
3894    struct tu_cs *cs = &cmd->cs;
3895    struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3896    struct tu_descriptor_state *descriptors_state =
3897       &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3898    VkResult result;
3899
3900    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3901       tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3902
3903    struct tu_cs_entry ib;
3904
3905    ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3906    if (ib.size)
3907       tu_cs_emit_ib(cs, &ib);
3908
3909    tu_emit_compute_driver_params(cs, pipeline, info);
3910
3911    bool needs_border;
3912    result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3913                               MESA_SHADER_COMPUTE, &ib, &needs_border, false);
3914    if (result != VK_SUCCESS) {
3915       cmd->record_result = result;
3916       return;
3917    }
3918
3919    if (ib.size)
3920       tu_cs_emit_ib(cs, &ib);
3921
3922    if (needs_border)
3923       tu_finishme("compute border color");
3924
3925    result = tu6_emit_ibo(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE, &ib);
3926    if (result != VK_SUCCESS) {
3927       cmd->record_result = result;
3928       return;
3929    }
3930
3931    if (ib.size)
3932       tu_cs_emit_ib(cs, &ib);
3933
3934    /* track BOs */
3935    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3936       unsigned i;
3937       for_each_bit(i, descriptors_state->valid) {
3938          struct tu_descriptor_set *set = descriptors_state->sets[i];
3939          for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3940             if (set->descriptors[j]) {
3941                tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3942                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3943             }
3944       }
3945    }
3946
3947    /* Compute shader state overwrites fragment shader state, so we flag the
3948     * graphics pipeline for re-emit.
3949     */
3950    cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
3951
3952    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3953    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
3954
3955    const uint32_t *local_size = pipeline->compute.local_size;
3956    const uint32_t *num_groups = info->blocks;
3957    tu_cs_emit_regs(cs,
3958                    A6XX_HLSQ_CS_NDRANGE_0(.kerneldim = 3,
3959                                           .localsizex = local_size[0] - 1,
3960                                           .localsizey = local_size[1] - 1,
3961                                           .localsizez = local_size[2] - 1),
3962                    A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x = local_size[0] * num_groups[0]),
3963                    A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x = 0),
3964                    A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y = local_size[1] * num_groups[1]),
3965                    A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y = 0),
3966                    A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z = local_size[2] * num_groups[2]),
3967                    A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z = 0));
3968
3969    tu_cs_emit_regs(cs,
3970                    A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3971                    A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3972                    A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3973
3974    if (info->indirect) {
3975       uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3976
3977       tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3978                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3979
3980       tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3981       tu_cs_emit(cs, 0x00000000);
3982       tu_cs_emit_qw(cs, iova);
3983       tu_cs_emit(cs,
3984                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3985                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3986                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3987    } else {
3988       tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3989       tu_cs_emit(cs, 0x00000000);
3990       tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3991       tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3992       tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3993    }
3994
3995    tu_cs_emit_wfi(cs);
3996
3997    tu6_emit_cache_flush(cmd, cs);
3998 }
3999
4000 void
4001 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
4002                    uint32_t base_x,
4003                    uint32_t base_y,
4004                    uint32_t base_z,
4005                    uint32_t x,
4006                    uint32_t y,
4007                    uint32_t z)
4008 {
4009    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4010    struct tu_dispatch_info info = {};
4011
4012    info.blocks[0] = x;
4013    info.blocks[1] = y;
4014    info.blocks[2] = z;
4015
4016    info.offsets[0] = base_x;
4017    info.offsets[1] = base_y;
4018    info.offsets[2] = base_z;
4019    tu_dispatch(cmd_buffer, &info);
4020 }
4021
4022 void
4023 tu_CmdDispatch(VkCommandBuffer commandBuffer,
4024                uint32_t x,
4025                uint32_t y,
4026                uint32_t z)
4027 {
4028    tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4029 }
4030
4031 void
4032 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
4033                        VkBuffer _buffer,
4034                        VkDeviceSize offset)
4035 {
4036    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4037    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
4038    struct tu_dispatch_info info = {};
4039
4040    info.indirect = buffer;
4041    info.indirect_offset = offset;
4042
4043    tu_dispatch(cmd_buffer, &info);
4044 }
4045
4046 void
4047 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
4048 {
4049    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4050
4051    tu_cs_end(&cmd_buffer->draw_cs);
4052    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
4053
4054    if (use_sysmem_rendering(cmd_buffer))
4055       tu_cmd_render_sysmem(cmd_buffer);
4056    else
4057       tu_cmd_render_tiles(cmd_buffer);
4058
4059    /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
4060       rendered */
4061    tu_cs_discard_entries(&cmd_buffer->draw_cs);
4062    tu_cs_begin(&cmd_buffer->draw_cs);
4063    tu_cs_discard_entries(&cmd_buffer->draw_epilogue_cs);
4064    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
4065
4066    cmd_buffer->state.pass = NULL;
4067    cmd_buffer->state.subpass = NULL;
4068    cmd_buffer->state.framebuffer = NULL;
4069 }
4070
4071 void
4072 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
4073                      const VkSubpassEndInfoKHR *pSubpassEndInfo)
4074 {
4075    tu_CmdEndRenderPass(commandBuffer);
4076 }
4077
4078 struct tu_barrier_info
4079 {
4080    uint32_t eventCount;
4081    const VkEvent *pEvents;
4082    VkPipelineStageFlags srcStageMask;
4083 };
4084
4085 static void
4086 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
4087            uint32_t memoryBarrierCount,
4088            const VkMemoryBarrier *pMemoryBarriers,
4089            uint32_t bufferMemoryBarrierCount,
4090            const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4091            uint32_t imageMemoryBarrierCount,
4092            const VkImageMemoryBarrier *pImageMemoryBarriers,
4093            const struct tu_barrier_info *info)
4094 {
4095 }
4096
4097 void
4098 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
4099                       VkPipelineStageFlags srcStageMask,
4100                       VkPipelineStageFlags destStageMask,
4101                       VkBool32 byRegion,
4102                       uint32_t memoryBarrierCount,
4103                       const VkMemoryBarrier *pMemoryBarriers,
4104                       uint32_t bufferMemoryBarrierCount,
4105                       const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4106                       uint32_t imageMemoryBarrierCount,
4107                       const VkImageMemoryBarrier *pImageMemoryBarriers)
4108 {
4109    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
4110    struct tu_barrier_info info;
4111
4112    info.eventCount = 0;
4113    info.pEvents = NULL;
4114    info.srcStageMask = srcStageMask;
4115
4116    tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4117               bufferMemoryBarrierCount, pBufferMemoryBarriers,
4118               imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4119 }
4120
4121 static void
4122 write_event(struct tu_cmd_buffer *cmd, struct tu_event *event, unsigned value)
4123 {
4124    struct tu_cs *cs = &cmd->cs;
4125
4126    tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_WRITE);
4127
4128    /* TODO: any flush required before/after ? */
4129
4130    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
4131    tu_cs_emit_qw(cs, event->bo.iova); /* ADDR_LO/HI */
4132    tu_cs_emit(cs, value);
4133 }
4134
4135 void
4136 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
4137                VkEvent _event,
4138                VkPipelineStageFlags stageMask)
4139 {
4140    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4141    TU_FROM_HANDLE(tu_event, event, _event);
4142
4143    write_event(cmd, event, 1);
4144 }
4145
4146 void
4147 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
4148                  VkEvent _event,
4149                  VkPipelineStageFlags stageMask)
4150 {
4151    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4152    TU_FROM_HANDLE(tu_event, event, _event);
4153
4154    write_event(cmd, event, 0);
4155 }
4156
4157 void
4158 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
4159                  uint32_t eventCount,
4160                  const VkEvent *pEvents,
4161                  VkPipelineStageFlags srcStageMask,
4162                  VkPipelineStageFlags dstStageMask,
4163                  uint32_t memoryBarrierCount,
4164                  const VkMemoryBarrier *pMemoryBarriers,
4165                  uint32_t bufferMemoryBarrierCount,
4166                  const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4167                  uint32_t imageMemoryBarrierCount,
4168                  const VkImageMemoryBarrier *pImageMemoryBarriers)
4169 {
4170    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4171    struct tu_cs *cs = &cmd->cs;
4172
4173    /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
4174
4175    for (uint32_t i = 0; i < eventCount; i++) {
4176       const struct tu_event *event = (const struct tu_event*) pEvents[i];
4177
4178       tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_READ);
4179
4180       tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
4181       tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
4182                      CP_WAIT_REG_MEM_0_POLL_MEMORY);
4183       tu_cs_emit_qw(cs, event->bo.iova); /* POLL_ADDR_LO/HI */
4184       tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1));
4185       tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u));
4186       tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
4187    }
4188 }
4189
4190 void
4191 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
4192 {
4193    /* No-op */
4194 }