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turnip: Set up the correct tiling mode for small attachments.
[mesa.git] / src / freedreno / vulkan / tu_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32 #include "registers/a6xx.xml.h"
33
34 #include "vk_format.h"
35
36 #include "tu_cs.h"
37
38 void
39 tu_bo_list_init(struct tu_bo_list *list)
40 {
41 list->count = list->capacity = 0;
42 list->bo_infos = NULL;
43 }
44
45 void
46 tu_bo_list_destroy(struct tu_bo_list *list)
47 {
48 free(list->bo_infos);
49 }
50
51 void
52 tu_bo_list_reset(struct tu_bo_list *list)
53 {
54 list->count = 0;
55 }
56
57 /**
58 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
59 */
60 static uint32_t
61 tu_bo_list_add_info(struct tu_bo_list *list,
62 const struct drm_msm_gem_submit_bo *bo_info)
63 {
64 for (uint32_t i = 0; i < list->count; ++i) {
65 if (list->bo_infos[i].handle == bo_info->handle) {
66 assert(list->bo_infos[i].presumed == bo_info->presumed);
67 list->bo_infos[i].flags |= bo_info->flags;
68 return i;
69 }
70 }
71
72 /* grow list->bo_infos if needed */
73 if (list->count == list->capacity) {
74 uint32_t new_capacity = MAX2(2 * list->count, 16);
75 struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
76 list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
77 if (!new_bo_infos)
78 return TU_BO_LIST_FAILED;
79 list->bo_infos = new_bo_infos;
80 list->capacity = new_capacity;
81 }
82
83 list->bo_infos[list->count] = *bo_info;
84 return list->count++;
85 }
86
87 uint32_t
88 tu_bo_list_add(struct tu_bo_list *list,
89 const struct tu_bo *bo,
90 uint32_t flags)
91 {
92 return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
93 .flags = flags,
94 .handle = bo->gem_handle,
95 .presumed = bo->iova,
96 });
97 }
98
99 VkResult
100 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
101 {
102 for (uint32_t i = 0; i < other->count; i++) {
103 if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
104 return VK_ERROR_OUT_OF_HOST_MEMORY;
105 }
106
107 return VK_SUCCESS;
108 }
109
110 static VkResult
111 tu_tiling_config_update_gmem_layout(struct tu_tiling_config *tiling,
112 const struct tu_device *dev)
113 {
114 const uint32_t gmem_size = dev->physical_device->gmem_size;
115 uint32_t offset = 0;
116
117 for (uint32_t i = 0; i < tiling->buffer_count; i++) {
118 /* 16KB-aligned */
119 offset = align(offset, 0x4000);
120
121 tiling->gmem_offsets[i] = offset;
122 offset += tiling->tile0.extent.width * tiling->tile0.extent.height *
123 tiling->buffer_cpp[i];
124 }
125
126 return offset <= gmem_size ? VK_SUCCESS : VK_ERROR_OUT_OF_DEVICE_MEMORY;
127 }
128
129 static void
130 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
131 const struct tu_device *dev)
132 {
133 const uint32_t tile_align_w = dev->physical_device->tile_align_w;
134 const uint32_t tile_align_h = dev->physical_device->tile_align_h;
135 const uint32_t max_tile_width = 1024; /* A6xx */
136
137 tiling->tile0.offset = (VkOffset2D) {
138 .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
139 .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
140 };
141
142 const uint32_t ra_width =
143 tiling->render_area.extent.width +
144 (tiling->render_area.offset.x - tiling->tile0.offset.x);
145 const uint32_t ra_height =
146 tiling->render_area.extent.height +
147 (tiling->render_area.offset.y - tiling->tile0.offset.y);
148
149 /* start from 1 tile */
150 tiling->tile_count = (VkExtent2D) {
151 .width = 1,
152 .height = 1,
153 };
154 tiling->tile0.extent = (VkExtent2D) {
155 .width = align(ra_width, tile_align_w),
156 .height = align(ra_height, tile_align_h),
157 };
158
159 /* do not exceed max tile width */
160 while (tiling->tile0.extent.width > max_tile_width) {
161 tiling->tile_count.width++;
162 tiling->tile0.extent.width =
163 align(ra_width / tiling->tile_count.width, tile_align_w);
164 }
165
166 /* do not exceed gmem size */
167 while (tu_tiling_config_update_gmem_layout(tiling, dev) != VK_SUCCESS) {
168 if (tiling->tile0.extent.width > tiling->tile0.extent.height) {
169 tiling->tile_count.width++;
170 tiling->tile0.extent.width =
171 align(ra_width / tiling->tile_count.width, tile_align_w);
172 } else {
173 tiling->tile_count.height++;
174 tiling->tile0.extent.height =
175 align(ra_height / tiling->tile_count.height, tile_align_h);
176 }
177 }
178 }
179
180 static void
181 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
182 const struct tu_device *dev)
183 {
184 const uint32_t max_pipe_count = 32; /* A6xx */
185
186 /* start from 1 tile per pipe */
187 tiling->pipe0 = (VkExtent2D) {
188 .width = 1,
189 .height = 1,
190 };
191 tiling->pipe_count = tiling->tile_count;
192
193 /* do not exceed max pipe count vertically */
194 while (tiling->pipe_count.height > max_pipe_count) {
195 tiling->pipe0.height += 2;
196 tiling->pipe_count.height =
197 (tiling->tile_count.height + tiling->pipe0.height - 1) /
198 tiling->pipe0.height;
199 }
200
201 /* do not exceed max pipe count */
202 while (tiling->pipe_count.width * tiling->pipe_count.height >
203 max_pipe_count) {
204 tiling->pipe0.width += 1;
205 tiling->pipe_count.width =
206 (tiling->tile_count.width + tiling->pipe0.width - 1) /
207 tiling->pipe0.width;
208 }
209 }
210
211 static void
212 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
213 const struct tu_device *dev)
214 {
215 const uint32_t max_pipe_count = 32; /* A6xx */
216 const uint32_t used_pipe_count =
217 tiling->pipe_count.width * tiling->pipe_count.height;
218 const VkExtent2D last_pipe = {
219 .width = tiling->tile_count.width % tiling->pipe0.width,
220 .height = tiling->tile_count.height % tiling->pipe0.height,
221 };
222
223 assert(used_pipe_count <= max_pipe_count);
224 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
225
226 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
227 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
228 const uint32_t pipe_x = tiling->pipe0.width * x;
229 const uint32_t pipe_y = tiling->pipe0.height * y;
230 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
231 ? last_pipe.width
232 : tiling->pipe0.width;
233 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
234 ? last_pipe.height
235 : tiling->pipe0.height;
236 const uint32_t n = tiling->pipe_count.width * y + x;
237
238 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
239 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
240 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
241 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
242 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
243 }
244 }
245
246 memset(tiling->pipe_config + used_pipe_count, 0,
247 sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
248 }
249
250 static void
251 tu_tiling_config_update(struct tu_tiling_config *tiling,
252 const struct tu_device *dev,
253 const uint32_t *buffer_cpp,
254 uint32_t buffer_count,
255 const VkRect2D *render_area)
256 {
257 /* see if there is any real change */
258 const bool ra_changed =
259 render_area &&
260 memcmp(&tiling->render_area, render_area, sizeof(*render_area));
261 const bool buf_changed = tiling->buffer_count != buffer_count ||
262 memcmp(tiling->buffer_cpp, buffer_cpp,
263 sizeof(*buffer_cpp) * buffer_count);
264 if (!ra_changed && !buf_changed)
265 return;
266
267 if (ra_changed)
268 tiling->render_area = *render_area;
269
270 if (buf_changed) {
271 memcpy(tiling->buffer_cpp, buffer_cpp,
272 sizeof(*buffer_cpp) * buffer_count);
273 tiling->buffer_count = buffer_count;
274 }
275
276 tu_tiling_config_update_tile_layout(tiling, dev);
277 tu_tiling_config_update_pipe_layout(tiling, dev);
278 tu_tiling_config_update_pipes(tiling, dev);
279 }
280
281 static void
282 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
283 const struct tu_device *dev,
284 uint32_t tx,
285 uint32_t ty,
286 struct tu_tile *tile)
287 {
288 /* find the pipe and the slot for tile (tx, ty) */
289 const uint32_t px = tx / tiling->pipe0.width;
290 const uint32_t py = ty / tiling->pipe0.height;
291 const uint32_t sx = tx - tiling->pipe0.width * px;
292 const uint32_t sy = ty - tiling->pipe0.height * py;
293
294 assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
295 assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
296 assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
297
298 /* convert to 1D indices */
299 tile->pipe = tiling->pipe_count.width * py + px;
300 tile->slot = tiling->pipe0.width * sy + sx;
301
302 /* get the blit area for the tile */
303 tile->begin = (VkOffset2D) {
304 .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
305 .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
306 };
307 tile->end.x =
308 (tx == tiling->tile_count.width - 1)
309 ? tiling->render_area.offset.x + tiling->render_area.extent.width
310 : tile->begin.x + tiling->tile0.extent.width;
311 tile->end.y =
312 (ty == tiling->tile_count.height - 1)
313 ? tiling->render_area.offset.y + tiling->render_area.extent.height
314 : tile->begin.y + tiling->tile0.extent.height;
315 }
316
317 static enum a3xx_msaa_samples
318 tu6_msaa_samples(uint32_t samples)
319 {
320 switch (samples) {
321 case 1:
322 return MSAA_ONE;
323 case 2:
324 return MSAA_TWO;
325 case 4:
326 return MSAA_FOUR;
327 case 8:
328 return MSAA_EIGHT;
329 default:
330 assert(!"invalid sample count");
331 return MSAA_ONE;
332 }
333 }
334
335 static enum a4xx_index_size
336 tu6_index_size(VkIndexType type)
337 {
338 switch (type) {
339 case VK_INDEX_TYPE_UINT16:
340 return INDEX4_SIZE_16_BIT;
341 case VK_INDEX_TYPE_UINT32:
342 return INDEX4_SIZE_32_BIT;
343 default:
344 unreachable("invalid VkIndexType");
345 return INDEX4_SIZE_8_BIT;
346 }
347 }
348
349 static void
350 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
351 {
352 tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
353 }
354
355 void
356 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
357 struct tu_cs *cs,
358 enum vgt_event_type event,
359 bool need_seqno)
360 {
361 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
362 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
363 if (need_seqno) {
364 tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
365 tu_cs_emit(cs, ++cmd->scratch_seqno);
366 }
367 }
368
369 static void
370 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
371 {
372 tu6_emit_event_write(cmd, cs, 0x31, false);
373 }
374
375 static void
376 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
377 {
378 tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
379 }
380
381 static void
382 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
383 {
384 if (cmd->wait_for_idle) {
385 tu_cs_emit_wfi(cs);
386 cmd->wait_for_idle = false;
387 }
388 }
389
390 static void
391 tu6_emit_zs(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
392 {
393 const struct tu_subpass *subpass = cmd->state.subpass;
394
395 const uint32_t a = subpass->depth_stencil_attachment.attachment;
396 if (a == VK_ATTACHMENT_UNUSED) {
397 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
398 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
399 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
400 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
401 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
402 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
403 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
404
405 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
406 tu_cs_emit(cs,
407 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
408
409 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
410 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
411 tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
412 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
413 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
414 tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
415
416 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
417 tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
418
419 return;
420 }
421
422 /* enable zs? */
423 }
424
425 static void
426 tu6_emit_mrt(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
427 {
428 const struct tu_framebuffer *fb = cmd->state.framebuffer;
429 const struct tu_subpass *subpass = cmd->state.subpass;
430 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
431 unsigned char mrt_comp[MAX_RTS] = { 0 };
432 unsigned srgb_cntl = 0;
433
434 uint32_t gmem_index = 0;
435 for (uint32_t i = 0; i < subpass->color_count; ++i) {
436 uint32_t a = subpass->color_attachments[i].attachment;
437 if (a == VK_ATTACHMENT_UNUSED)
438 continue;
439
440 const struct tu_image_view *iview = fb->attachments[a].attachment;
441 const struct tu_image_level *slice =
442 &iview->image->levels[iview->base_mip];
443 const enum a6xx_tile_mode tile_mode =
444 tu6_get_image_tile_mode(iview->image, iview->base_mip);
445 uint32_t stride = 0;
446 uint32_t offset = 0;
447
448 mrt_comp[i] = 0xf;
449
450 if (vk_format_is_srgb(iview->vk_format))
451 srgb_cntl |= (1 << i);
452
453 const struct tu_native_format *format =
454 tu6_get_native_format(iview->vk_format);
455 assert(format && format->rb >= 0);
456
457 offset = slice->offset + slice->size * iview->base_layer;
458 stride = slice->pitch * iview->image->cpp;
459
460 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
461 tu_cs_emit(cs, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format->rb) |
462 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
463 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format->swap));
464 tu_cs_emit(cs, A6XX_RB_MRT_PITCH(stride));
465 tu_cs_emit(cs, A6XX_RB_MRT_ARRAY_PITCH(slice->size));
466 tu_cs_emit_qw(cs, iview->image->bo->iova + iview->image->bo_offset +
467 offset); /* BASE_LO/HI */
468 tu_cs_emit(
469 cs, tiling->gmem_offsets[gmem_index++]); /* RB_MRT[i].BASE_GMEM */
470
471 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_MRT_REG(i), 1);
472 tu_cs_emit(cs, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format->rb));
473
474 #if 0
475 /* when we support UBWC, these would be the system memory
476 * addr/pitch/etc:
477 */
478 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 4);
479 tu_cs_emit(cs, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
480 tu_cs_emit(cs, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
481 tu_cs_emit(cs, A6XX_RB_MRT_FLAG_BUFFER_PITCH(0));
482 tu_cs_emit(cs, A6XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
483 #endif
484 }
485
486 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SRGB_CNTL, 1);
487 tu_cs_emit(cs, srgb_cntl);
488
489 tu_cs_emit_pkt4(cs, REG_A6XX_SP_SRGB_CNTL, 1);
490 tu_cs_emit(cs, srgb_cntl);
491
492 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_COMPONENTS, 1);
493 tu_cs_emit(cs, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
494 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
495 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
496 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
497 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
498 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
499 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
500 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
501
502 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
503 tu_cs_emit(cs, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
504 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
505 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
506 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
507 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
508 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
509 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
510 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
511 }
512
513 static void
514 tu6_emit_msaa(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
515 {
516 const struct tu_subpass *subpass = cmd->state.subpass;
517 const enum a3xx_msaa_samples samples =
518 tu6_msaa_samples(subpass->max_sample_count);
519
520 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
521 tu_cs_emit(cs, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
522 tu_cs_emit(
523 cs, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
524 ((samples == MSAA_ONE) ? A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE
525 : 0));
526
527 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
528 tu_cs_emit(cs, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
529 tu_cs_emit(
530 cs,
531 A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
532 ((samples == MSAA_ONE) ? A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE : 0));
533
534 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
535 tu_cs_emit(cs, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
536 tu_cs_emit(
537 cs,
538 A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
539 ((samples == MSAA_ONE) ? A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE : 0));
540
541 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_CNTL, 1);
542 tu_cs_emit(cs, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
543 }
544
545 static void
546 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
547 {
548 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
549 const uint32_t bin_w = tiling->tile0.extent.width;
550 const uint32_t bin_h = tiling->tile0.extent.height;
551
552 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_BIN_CONTROL, 1);
553 tu_cs_emit(cs, A6XX_GRAS_BIN_CONTROL_BINW(bin_w) |
554 A6XX_GRAS_BIN_CONTROL_BINH(bin_h) | flags);
555
556 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL, 1);
557 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL_BINW(bin_w) |
558 A6XX_RB_BIN_CONTROL_BINH(bin_h) | flags);
559
560 /* no flag for RB_BIN_CONTROL2... */
561 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL2, 1);
562 tu_cs_emit(cs, A6XX_RB_BIN_CONTROL2_BINW(bin_w) |
563 A6XX_RB_BIN_CONTROL2_BINH(bin_h));
564 }
565
566 static void
567 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
568 struct tu_cs *cs,
569 bool binning)
570 {
571 uint32_t cntl = 0;
572 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
573 if (binning)
574 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
575
576 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
577 tu_cs_emit(cs, 0x2);
578 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
579 tu_cs_emit(cs, cntl);
580 }
581
582 static void
583 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
584 {
585 const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
586 const uint32_t x1 = render_area->offset.x;
587 const uint32_t y1 = render_area->offset.y;
588 const uint32_t x2 = x1 + render_area->extent.width - 1;
589 const uint32_t y2 = y1 + render_area->extent.height - 1;
590
591 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
592 tu_cs_emit(cs,
593 A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
594 tu_cs_emit(cs,
595 A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
596 }
597
598 static void
599 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
600 struct tu_cs *cs,
601 const struct tu_image_view *iview,
602 uint32_t gmem_offset,
603 uint32_t blit_info)
604 {
605 const struct tu_image_level *slice =
606 &iview->image->levels[iview->base_mip];
607 const uint32_t offset = slice->offset + slice->size * iview->base_layer;
608 const uint32_t stride = slice->pitch * iview->image->cpp;
609 const enum a3xx_msaa_samples samples = tu6_msaa_samples(1);
610
611 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
612 tu_cs_emit(cs, blit_info);
613
614 const struct tu_native_format *format =
615 tu6_get_native_format(iview->vk_format);
616 assert(format && format->rb >= 0);
617
618 enum a6xx_tile_mode tile_mode =
619 tu6_get_image_tile_mode(iview->image, iview->base_mip);
620 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 5);
621 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
622 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
623 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
624 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format->swap));
625 tu_cs_emit_qw(cs,
626 iview->image->bo->iova + iview->image->bo_offset + offset);
627 tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(stride));
628 tu_cs_emit(cs, A6XX_RB_BLIT_DST_ARRAY_PITCH(slice->size));
629
630 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
631 tu_cs_emit(cs, gmem_offset);
632 }
633
634 static void
635 tu6_emit_blit_clear(struct tu_cmd_buffer *cmd,
636 struct tu_cs *cs,
637 const struct tu_image_view *iview,
638 uint32_t gmem_offset,
639 const VkClearValue *clear_value)
640 {
641 const enum a3xx_msaa_samples samples = tu6_msaa_samples(1);
642
643 const struct tu_native_format *format =
644 tu6_get_native_format(iview->vk_format);
645 assert(format && format->rb >= 0);
646 /* must be WZYX; other values are ignored */
647 const enum a3xx_color_swap swap = WZYX;
648
649 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
650 tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(iview->image->tile_mode) |
651 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
652 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
653 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap));
654
655 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
656 tu_cs_emit(cs, A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
657
658 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
659 tu_cs_emit(cs, gmem_offset);
660
661 tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
662 tu_cs_emit(cs, 0);
663
664 /* pack clear_value into WZYX order */
665 uint32_t clear_vals[4] = { 0 };
666 tu_pack_clear_value(clear_value, iview->vk_format, clear_vals);
667
668 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
669 tu_cs_emit(cs, clear_vals[0]);
670 tu_cs_emit(cs, clear_vals[1]);
671 tu_cs_emit(cs, clear_vals[2]);
672 tu_cs_emit(cs, clear_vals[3]);
673 }
674
675 static void
676 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
677 {
678 tu6_emit_marker(cmd, cs);
679 tu6_emit_event_write(cmd, cs, BLIT, false);
680 tu6_emit_marker(cmd, cs);
681 }
682
683 static void
684 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
685 struct tu_cs *cs,
686 uint32_t x1,
687 uint32_t y1,
688 uint32_t x2,
689 uint32_t y2)
690 {
691 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
692 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
693 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
694 tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
695 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
696
697 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
698 tu_cs_emit(
699 cs, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
700 tu_cs_emit(
701 cs, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
702 }
703
704 static void
705 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
706 struct tu_cs *cs,
707 uint32_t x1,
708 uint32_t y1)
709 {
710 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
711 tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
712
713 tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET2, 1);
714 tu_cs_emit(cs,
715 A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
716
717 tu_cs_emit_pkt4(cs, REG_A6XX_SP_WINDOW_OFFSET, 1);
718 tu_cs_emit(cs, A6XX_SP_WINDOW_OFFSET_X(x1) | A6XX_SP_WINDOW_OFFSET_Y(y1));
719
720 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
721 tu_cs_emit(
722 cs, A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
723 }
724
725 static void
726 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
727 struct tu_cs *cs,
728 const struct tu_tile *tile)
729 {
730 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
731 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
732
733 tu6_emit_marker(cmd, cs);
734 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
735 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
736 tu6_emit_marker(cmd, cs);
737
738 const uint32_t x1 = tile->begin.x;
739 const uint32_t y1 = tile->begin.y;
740 const uint32_t x2 = tile->end.x - 1;
741 const uint32_t y2 = tile->end.y - 1;
742 tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
743 tu6_emit_window_offset(cmd, cs, x1, y1);
744
745 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_OVERRIDE, 1);
746 tu_cs_emit(cs, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
747
748 if (false) {
749 /* hw binning? */
750 } else {
751 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
752 tu_cs_emit(cs, 0x1);
753
754 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
755 tu_cs_emit(cs, 0x0);
756 }
757 }
758
759 static void
760 tu6_emit_tile_load(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
761 {
762 const struct tu_framebuffer *fb = cmd->state.framebuffer;
763 const struct tu_subpass *subpass = cmd->state.subpass;
764 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
765 const struct tu_attachment_state *attachments = cmd->state.attachments;
766
767 tu6_emit_blit_scissor(cmd, cs);
768
769 uint32_t gmem_index = 0;
770 for (uint32_t i = 0; i < subpass->color_count; ++i) {
771 const uint32_t a = subpass->color_attachments[i].attachment;
772 if (a == VK_ATTACHMENT_UNUSED)
773 continue;
774
775 const struct tu_image_view *iview = fb->attachments[a].attachment;
776 const struct tu_attachment_state *att = attachments + a;
777 if (att->pending_clear_aspects) {
778 assert(att->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
779 tu6_emit_blit_clear(cmd, cs, iview,
780 tiling->gmem_offsets[gmem_index++],
781 &att->clear_value);
782 } else {
783 tu6_emit_blit_info(cmd, cs, iview,
784 tiling->gmem_offsets[gmem_index++],
785 A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM);
786 }
787
788 tu6_emit_blit(cmd, cs);
789 }
790
791 /* load/clear zs? */
792 }
793
794 static void
795 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
796 {
797 const struct tu_framebuffer *fb = cmd->state.framebuffer;
798 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
799
800 if (false) {
801 /* hw binning? */
802 }
803
804 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
805 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
806 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
807 CP_SET_DRAW_STATE__0_GROUP_ID(0));
808 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
809 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
810
811 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
812 tu_cs_emit(cs, 0x0);
813
814 tu6_emit_marker(cmd, cs);
815 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
816 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
817 tu6_emit_marker(cmd, cs);
818
819 tu6_emit_blit_scissor(cmd, cs);
820
821 uint32_t gmem_index = 0;
822 for (uint32_t i = 0; i < cmd->state.subpass->color_count; ++i) {
823 uint32_t a = cmd->state.subpass->color_attachments[i].attachment;
824 if (a == VK_ATTACHMENT_UNUSED)
825 continue;
826
827 const struct tu_image_view *iview = fb->attachments[a].attachment;
828 tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[gmem_index++],
829 0);
830 tu6_emit_blit(cmd, cs);
831 }
832 }
833
834 static void
835 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
836 {
837 tu_cs_emit_pkt4(cs, REG_A6XX_PC_RESTART_INDEX, 1);
838 tu_cs_emit(cs, restart_index);
839 }
840
841 static void
842 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
843 {
844 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
845 if (result != VK_SUCCESS) {
846 cmd->record_result = result;
847 return;
848 }
849
850 tu6_emit_cache_flush(cmd, cs);
851
852 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
853
854 tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
855 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
856 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
857 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
858 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
859 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
860 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
861 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
862 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
863
864 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
865 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
866 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
867 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
868 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
869 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
870 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
871 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
872 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
873 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
874 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
875 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
876 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
877 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
878
879 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
880
881 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
882 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
883 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
884
885 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
886 tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
887 tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
888 tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
889 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
890 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
891 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
892 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
893 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
894 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
895 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
896 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
897
898 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
899 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
900
901 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
902 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
903
904 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
905 A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
906
907 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
908 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
909 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
910
911 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B06, 0);
912 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B06, 0);
913
914 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
915
916 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
917
918 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
919 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
920 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
921 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
922 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
923 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
924 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
925 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
926 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
927 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
928 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
929 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
930 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
931 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
932 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
933 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
934 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
935 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
936 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
937 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
938 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
939
940 tu6_emit_marker(cmd, cs);
941
942 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
943
944 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
945
946 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
947
948 /* we don't use this yet.. probably best to disable.. */
949 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
950 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
951 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
952 CP_SET_DRAW_STATE__0_GROUP_ID(0));
953 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
954 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
955
956 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
957 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
958 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
959 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
960
961 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
962 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
963 tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
964
965 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUF_CNTL, 1);
966 tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUF_CNTL */
967
968 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
969 tu_cs_emit(cs, 0x00000000); /* UNKNOWN_E2AB */
970
971 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
972 tu_cs_emit(cs, 0x00000000);
973 tu_cs_emit(cs, 0x00000000);
974 tu_cs_emit(cs, 0x00000000);
975
976 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
977 tu_cs_emit(cs, 0x00000000);
978 tu_cs_emit(cs, 0x00000000);
979 tu_cs_emit(cs, 0x00000000);
980 tu_cs_emit(cs, 0x00000000);
981 tu_cs_emit(cs, 0x00000000);
982 tu_cs_emit(cs, 0x00000000);
983
984 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
985 tu_cs_emit(cs, 0x00000000);
986 tu_cs_emit(cs, 0x00000000);
987 tu_cs_emit(cs, 0x00000000);
988 tu_cs_emit(cs, 0x00000000);
989 tu_cs_emit(cs, 0x00000000);
990 tu_cs_emit(cs, 0x00000000);
991
992 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
993 tu_cs_emit(cs, 0x00000000);
994 tu_cs_emit(cs, 0x00000000);
995 tu_cs_emit(cs, 0x00000000);
996
997 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CTRL_REG0, 1);
998 tu_cs_emit(cs, 0x00000000);
999
1000 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1001 tu_cs_emit(cs, 0x00000000);
1002
1003 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1004 tu_cs_emit(cs, 0x00000000);
1005
1006 tu_cs_emit_pkt4(cs, REG_A6XX_RB_LRZ_CNTL, 1);
1007 tu_cs_emit(cs, 0x00000000);
1008
1009 tu_cs_sanity_check(cs);
1010 }
1011
1012 static void
1013 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1014 {
1015 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
1016 if (result != VK_SUCCESS) {
1017 cmd->record_result = result;
1018 return;
1019 }
1020
1021 tu6_emit_lrz_flush(cmd, cs);
1022
1023 /* lrz clear? */
1024
1025 tu6_emit_cache_flush(cmd, cs);
1026
1027 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1028 tu_cs_emit(cs, 0x0);
1029
1030 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1031 tu6_emit_wfi(cmd, cs);
1032 tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1033 tu_cs_emit(cs, 0x7c400004); /* RB_CCU_CNTL */
1034
1035 tu6_emit_zs(cmd, cs);
1036 tu6_emit_mrt(cmd, cs);
1037 tu6_emit_msaa(cmd, cs);
1038
1039 if (false) {
1040 /* hw binning? */
1041 } else {
1042 tu6_emit_bin_size(cmd, cs, 0x6000000);
1043 /* no draws */
1044 }
1045
1046 tu6_emit_render_cntl(cmd, cs, false);
1047
1048 tu_cs_sanity_check(cs);
1049 }
1050
1051 static void
1052 tu6_render_tile(struct tu_cmd_buffer *cmd,
1053 struct tu_cs *cs,
1054 const struct tu_tile *tile)
1055 {
1056 const uint32_t render_tile_space = 64 + tu_cs_get_call_size(&cmd->draw_cs);
1057 VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1058 if (result != VK_SUCCESS) {
1059 cmd->record_result = result;
1060 return;
1061 }
1062
1063 tu6_emit_tile_select(cmd, cs, tile);
1064 tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1065
1066 tu_cs_emit_call(cs, &cmd->draw_cs);
1067 cmd->wait_for_idle = true;
1068
1069 tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1070
1071 tu_cs_sanity_check(cs);
1072 }
1073
1074 static void
1075 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1076 {
1077 VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1078 if (result != VK_SUCCESS) {
1079 cmd->record_result = result;
1080 return;
1081 }
1082
1083 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1084 tu_cs_emit(cs, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1085
1086 tu6_emit_lrz_flush(cmd, cs);
1087
1088 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1089
1090 tu_cs_sanity_check(cs);
1091 }
1092
1093 static void
1094 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1095 {
1096 const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1097
1098 tu6_render_begin(cmd, &cmd->cs);
1099
1100 for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1101 for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1102 struct tu_tile tile;
1103 tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1104 tu6_render_tile(cmd, &cmd->cs, &tile);
1105 }
1106 }
1107
1108 tu6_render_end(cmd, &cmd->cs);
1109 }
1110
1111 static void
1112 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd)
1113 {
1114 const uint32_t tile_load_space = 16 + 32 * MAX_RTS;
1115 const struct tu_subpass *subpass = cmd->state.subpass;
1116 struct tu_attachment_state *attachments = cmd->state.attachments;
1117 struct tu_cs sub_cs;
1118
1119 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1120 tile_load_space, &sub_cs);
1121 if (result != VK_SUCCESS) {
1122 cmd->record_result = result;
1123 return;
1124 }
1125
1126 /* emit to tile-load sub_cs */
1127 tu6_emit_tile_load(cmd, &sub_cs);
1128
1129 cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1130
1131 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1132 const uint32_t a = subpass->color_attachments[i].attachment;
1133 if (a != VK_ATTACHMENT_UNUSED)
1134 attachments[a].pending_clear_aspects = 0;
1135 }
1136 }
1137
1138 static void
1139 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1140 {
1141 const uint32_t tile_store_space = 32 + 32 * MAX_RTS;
1142 struct tu_cs sub_cs;
1143
1144 VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->tile_cs,
1145 tile_store_space, &sub_cs);
1146 if (result != VK_SUCCESS) {
1147 cmd->record_result = result;
1148 return;
1149 }
1150
1151 /* emit to tile-store sub_cs */
1152 tu6_emit_tile_store(cmd, &sub_cs);
1153
1154 cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->tile_cs, &sub_cs);
1155 }
1156
1157 static void
1158 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1159 const VkRect2D *render_area)
1160 {
1161 const struct tu_device *dev = cmd->device;
1162 const struct tu_render_pass *pass = cmd->state.pass;
1163 const struct tu_subpass *subpass = cmd->state.subpass;
1164 struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1165
1166 uint32_t buffer_cpp[MAX_RTS + 2];
1167 uint32_t buffer_count = 0;
1168
1169 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1170 const uint32_t a = subpass->color_attachments[i].attachment;
1171 if (a == VK_ATTACHMENT_UNUSED)
1172 continue;
1173
1174 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1175 buffer_cpp[buffer_count++] =
1176 vk_format_get_blocksize(att->format) * att->samples;
1177 }
1178
1179 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1180 const uint32_t a = subpass->depth_stencil_attachment.attachment;
1181 const struct tu_render_pass_attachment *att = &pass->attachments[a];
1182
1183 /* TODO */
1184 assert(att->format != VK_FORMAT_D32_SFLOAT_S8_UINT);
1185
1186 buffer_cpp[buffer_count++] =
1187 vk_format_get_blocksize(att->format) * att->samples;
1188 }
1189
1190 tu_tiling_config_update(tiling, dev, buffer_cpp, buffer_count,
1191 render_area);
1192 }
1193
1194 const struct tu_dynamic_state default_dynamic_state = {
1195 .viewport =
1196 {
1197 .count = 0,
1198 },
1199 .scissor =
1200 {
1201 .count = 0,
1202 },
1203 .line_width = 1.0f,
1204 .depth_bias =
1205 {
1206 .bias = 0.0f,
1207 .clamp = 0.0f,
1208 .slope = 0.0f,
1209 },
1210 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1211 .depth_bounds =
1212 {
1213 .min = 0.0f,
1214 .max = 1.0f,
1215 },
1216 .stencil_compare_mask =
1217 {
1218 .front = ~0u,
1219 .back = ~0u,
1220 },
1221 .stencil_write_mask =
1222 {
1223 .front = ~0u,
1224 .back = ~0u,
1225 },
1226 .stencil_reference =
1227 {
1228 .front = 0u,
1229 .back = 0u,
1230 },
1231 };
1232
1233 static void UNUSED /* FINISHME */
1234 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1235 const struct tu_dynamic_state *src)
1236 {
1237 struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1238 uint32_t copy_mask = src->mask;
1239 uint32_t dest_mask = 0;
1240
1241 tu_use_args(cmd_buffer); /* FINISHME */
1242
1243 /* Make sure to copy the number of viewports/scissors because they can
1244 * only be specified at pipeline creation time.
1245 */
1246 dest->viewport.count = src->viewport.count;
1247 dest->scissor.count = src->scissor.count;
1248 dest->discard_rectangle.count = src->discard_rectangle.count;
1249
1250 if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1251 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1252 src->viewport.count * sizeof(VkViewport))) {
1253 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1254 src->viewport.count);
1255 dest_mask |= TU_DYNAMIC_VIEWPORT;
1256 }
1257 }
1258
1259 if (copy_mask & TU_DYNAMIC_SCISSOR) {
1260 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1261 src->scissor.count * sizeof(VkRect2D))) {
1262 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1263 src->scissor.count);
1264 dest_mask |= TU_DYNAMIC_SCISSOR;
1265 }
1266 }
1267
1268 if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1269 if (dest->line_width != src->line_width) {
1270 dest->line_width = src->line_width;
1271 dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1272 }
1273 }
1274
1275 if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1276 if (memcmp(&dest->depth_bias, &src->depth_bias,
1277 sizeof(src->depth_bias))) {
1278 dest->depth_bias = src->depth_bias;
1279 dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1280 }
1281 }
1282
1283 if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1284 if (memcmp(&dest->blend_constants, &src->blend_constants,
1285 sizeof(src->blend_constants))) {
1286 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1287 dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1288 }
1289 }
1290
1291 if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1292 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1293 sizeof(src->depth_bounds))) {
1294 dest->depth_bounds = src->depth_bounds;
1295 dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1296 }
1297 }
1298
1299 if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1300 if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1301 sizeof(src->stencil_compare_mask))) {
1302 dest->stencil_compare_mask = src->stencil_compare_mask;
1303 dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1304 }
1305 }
1306
1307 if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1308 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1309 sizeof(src->stencil_write_mask))) {
1310 dest->stencil_write_mask = src->stencil_write_mask;
1311 dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1312 }
1313 }
1314
1315 if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1316 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1317 sizeof(src->stencil_reference))) {
1318 dest->stencil_reference = src->stencil_reference;
1319 dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1320 }
1321 }
1322
1323 if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1324 if (memcmp(&dest->discard_rectangle.rectangles,
1325 &src->discard_rectangle.rectangles,
1326 src->discard_rectangle.count * sizeof(VkRect2D))) {
1327 typed_memcpy(dest->discard_rectangle.rectangles,
1328 src->discard_rectangle.rectangles,
1329 src->discard_rectangle.count);
1330 dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1331 }
1332 }
1333 }
1334
1335 static VkResult
1336 tu_create_cmd_buffer(struct tu_device *device,
1337 struct tu_cmd_pool *pool,
1338 VkCommandBufferLevel level,
1339 VkCommandBuffer *pCommandBuffer)
1340 {
1341 struct tu_cmd_buffer *cmd_buffer;
1342 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1343 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1344 if (cmd_buffer == NULL)
1345 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1346
1347 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1348 cmd_buffer->device = device;
1349 cmd_buffer->pool = pool;
1350 cmd_buffer->level = level;
1351
1352 if (pool) {
1353 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1354 cmd_buffer->queue_family_index = pool->queue_family_index;
1355
1356 } else {
1357 /* Init the pool_link so we can safely call list_del when we destroy
1358 * the command buffer
1359 */
1360 list_inithead(&cmd_buffer->pool_link);
1361 cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1362 }
1363
1364 tu_bo_list_init(&cmd_buffer->bo_list);
1365 tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1366 tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1367 tu_cs_init(&cmd_buffer->draw_state, TU_CS_MODE_SUB_STREAM, 2048);
1368 tu_cs_init(&cmd_buffer->tile_cs, TU_CS_MODE_SUB_STREAM, 1024);
1369
1370 *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1371
1372 list_inithead(&cmd_buffer->upload.list);
1373
1374 cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1375 cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1376
1377 VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1378 if (result != VK_SUCCESS)
1379 return result;
1380
1381 return VK_SUCCESS;
1382 }
1383
1384 static void
1385 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1386 {
1387 tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1388
1389 list_del(&cmd_buffer->pool_link);
1390
1391 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1392 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1393
1394 tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1395 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1396 tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_state);
1397 tu_cs_finish(cmd_buffer->device, &cmd_buffer->tile_cs);
1398
1399 tu_bo_list_destroy(&cmd_buffer->bo_list);
1400 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1401 }
1402
1403 static VkResult
1404 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1405 {
1406 cmd_buffer->wait_for_idle = true;
1407
1408 cmd_buffer->record_result = VK_SUCCESS;
1409
1410 tu_bo_list_reset(&cmd_buffer->bo_list);
1411 tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1412 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1413 tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_state);
1414 tu_cs_reset(cmd_buffer->device, &cmd_buffer->tile_cs);
1415
1416 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1417 cmd_buffer->descriptors[i].dirty = 0;
1418 cmd_buffer->descriptors[i].valid = 0;
1419 cmd_buffer->descriptors[i].push_dirty = false;
1420 }
1421
1422 cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1423
1424 return cmd_buffer->record_result;
1425 }
1426
1427 static VkResult
1428 tu_cmd_state_setup_attachments(struct tu_cmd_buffer *cmd_buffer,
1429 const VkRenderPassBeginInfo *info)
1430 {
1431 struct tu_cmd_state *state = &cmd_buffer->state;
1432 const struct tu_framebuffer *fb = state->framebuffer;
1433 const struct tu_render_pass *pass = state->pass;
1434
1435 for (uint32_t i = 0; i < fb->attachment_count; ++i) {
1436 const struct tu_image_view *iview = fb->attachments[i].attachment;
1437 tu_bo_list_add(&cmd_buffer->bo_list, iview->image->bo,
1438 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1439 }
1440
1441 if (pass->attachment_count == 0) {
1442 state->attachments = NULL;
1443 return VK_SUCCESS;
1444 }
1445
1446 state->attachments =
1447 vk_alloc(&cmd_buffer->pool->alloc,
1448 pass->attachment_count * sizeof(state->attachments[0]), 8,
1449 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1450 if (state->attachments == NULL) {
1451 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1452 return cmd_buffer->record_result;
1453 }
1454
1455 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1456 const struct tu_render_pass_attachment *att = &pass->attachments[i];
1457 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1458 VkImageAspectFlags clear_aspects = 0;
1459
1460 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1461 /* color attachment */
1462 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1463 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1464 }
1465 } else {
1466 /* depthstencil attachment */
1467 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1468 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1469 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1470 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1471 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1472 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1473 }
1474 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1475 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1476 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1477 }
1478 }
1479
1480 state->attachments[i].pending_clear_aspects = clear_aspects;
1481 state->attachments[i].cleared_views = 0;
1482 if (clear_aspects && info) {
1483 assert(info->clearValueCount > i);
1484 state->attachments[i].clear_value = info->pClearValues[i];
1485 }
1486
1487 state->attachments[i].current_layout = att->initial_layout;
1488 }
1489
1490 return VK_SUCCESS;
1491 }
1492
1493 VkResult
1494 tu_AllocateCommandBuffers(VkDevice _device,
1495 const VkCommandBufferAllocateInfo *pAllocateInfo,
1496 VkCommandBuffer *pCommandBuffers)
1497 {
1498 TU_FROM_HANDLE(tu_device, device, _device);
1499 TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1500
1501 VkResult result = VK_SUCCESS;
1502 uint32_t i;
1503
1504 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1505
1506 if (!list_empty(&pool->free_cmd_buffers)) {
1507 struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1508 &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1509
1510 list_del(&cmd_buffer->pool_link);
1511 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1512
1513 result = tu_reset_cmd_buffer(cmd_buffer);
1514 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1515 cmd_buffer->level = pAllocateInfo->level;
1516
1517 pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1518 } else {
1519 result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1520 &pCommandBuffers[i]);
1521 }
1522 if (result != VK_SUCCESS)
1523 break;
1524 }
1525
1526 if (result != VK_SUCCESS) {
1527 tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1528 pCommandBuffers);
1529
1530 /* From the Vulkan 1.0.66 spec:
1531 *
1532 * "vkAllocateCommandBuffers can be used to create multiple
1533 * command buffers. If the creation of any of those command
1534 * buffers fails, the implementation must destroy all
1535 * successfully created command buffer objects from this
1536 * command, set all entries of the pCommandBuffers array to
1537 * NULL and return the error."
1538 */
1539 memset(pCommandBuffers, 0,
1540 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1541 }
1542
1543 return result;
1544 }
1545
1546 void
1547 tu_FreeCommandBuffers(VkDevice device,
1548 VkCommandPool commandPool,
1549 uint32_t commandBufferCount,
1550 const VkCommandBuffer *pCommandBuffers)
1551 {
1552 for (uint32_t i = 0; i < commandBufferCount; i++) {
1553 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1554
1555 if (cmd_buffer) {
1556 if (cmd_buffer->pool) {
1557 list_del(&cmd_buffer->pool_link);
1558 list_addtail(&cmd_buffer->pool_link,
1559 &cmd_buffer->pool->free_cmd_buffers);
1560 } else
1561 tu_cmd_buffer_destroy(cmd_buffer);
1562 }
1563 }
1564 }
1565
1566 VkResult
1567 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1568 VkCommandBufferResetFlags flags)
1569 {
1570 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1571 return tu_reset_cmd_buffer(cmd_buffer);
1572 }
1573
1574 VkResult
1575 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1576 const VkCommandBufferBeginInfo *pBeginInfo)
1577 {
1578 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1579 VkResult result = VK_SUCCESS;
1580
1581 if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1582 /* If the command buffer has already been resetted with
1583 * vkResetCommandBuffer, no need to do it again.
1584 */
1585 result = tu_reset_cmd_buffer(cmd_buffer);
1586 if (result != VK_SUCCESS)
1587 return result;
1588 }
1589
1590 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1591 cmd_buffer->usage_flags = pBeginInfo->flags;
1592
1593 tu_cs_begin(&cmd_buffer->cs);
1594
1595 cmd_buffer->marker_seqno = 0;
1596 cmd_buffer->scratch_seqno = 0;
1597
1598 /* setup initial configuration into command buffer */
1599 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1600 switch (cmd_buffer->queue_family_index) {
1601 case TU_QUEUE_GENERAL:
1602 tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1603 break;
1604 default:
1605 break;
1606 }
1607 }
1608
1609 cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1610
1611 return VK_SUCCESS;
1612 }
1613
1614 void
1615 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1616 uint32_t firstBinding,
1617 uint32_t bindingCount,
1618 const VkBuffer *pBuffers,
1619 const VkDeviceSize *pOffsets)
1620 {
1621 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1622
1623 assert(firstBinding + bindingCount <= MAX_VBS);
1624
1625 for (uint32_t i = 0; i < bindingCount; i++) {
1626 cmd->state.vb.buffers[firstBinding + i] =
1627 tu_buffer_from_handle(pBuffers[i]);
1628 cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1629 }
1630
1631 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1632 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1633 }
1634
1635 void
1636 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1637 VkBuffer buffer,
1638 VkDeviceSize offset,
1639 VkIndexType indexType)
1640 {
1641 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1642 TU_FROM_HANDLE(tu_buffer, buf, buffer);
1643
1644 /* initialize/update the restart index */
1645 if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1646 struct tu_cs *draw_cs = &cmd->draw_cs;
1647 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1648 if (result != VK_SUCCESS) {
1649 cmd->record_result = result;
1650 return;
1651 }
1652
1653 tu6_emit_restart_index(
1654 draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1655
1656 tu_cs_sanity_check(draw_cs);
1657 }
1658
1659 /* track the BO */
1660 if (cmd->state.index_buffer != buf)
1661 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1662
1663 cmd->state.index_buffer = buf;
1664 cmd->state.index_offset = offset;
1665 cmd->state.index_type = indexType;
1666 }
1667
1668 void
1669 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1670 VkPipelineBindPoint pipelineBindPoint,
1671 VkPipelineLayout _layout,
1672 uint32_t firstSet,
1673 uint32_t descriptorSetCount,
1674 const VkDescriptorSet *pDescriptorSets,
1675 uint32_t dynamicOffsetCount,
1676 const uint32_t *pDynamicOffsets)
1677 {
1678 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1679
1680 struct tu_descriptor_state *descriptors_state =
1681 tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1682
1683 for (unsigned i = 0; i < descriptorSetCount; ++i) {
1684 unsigned idx = i + firstSet;
1685 TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1686
1687 descriptors_state->sets[idx] = set;
1688 descriptors_state->valid |= (1u << idx);
1689 }
1690
1691 cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1692 }
1693
1694 void
1695 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1696 VkPipelineLayout layout,
1697 VkShaderStageFlags stageFlags,
1698 uint32_t offset,
1699 uint32_t size,
1700 const void *pValues)
1701 {
1702 }
1703
1704 VkResult
1705 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1706 {
1707 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1708
1709 if (cmd_buffer->scratch_seqno) {
1710 tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
1711 MSM_SUBMIT_BO_WRITE);
1712 }
1713
1714 for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
1715 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
1716 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1717 }
1718
1719 for (uint32_t i = 0; i < cmd_buffer->draw_state.bo_count; i++) {
1720 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_state.bos[i],
1721 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1722 }
1723
1724 for (uint32_t i = 0; i < cmd_buffer->tile_cs.bo_count; i++) {
1725 tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->tile_cs.bos[i],
1726 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1727 }
1728
1729 tu_cs_end(&cmd_buffer->cs);
1730
1731 assert(!cmd_buffer->state.attachments);
1732
1733 cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
1734
1735 return cmd_buffer->record_result;
1736 }
1737
1738 void
1739 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
1740 VkPipelineBindPoint pipelineBindPoint,
1741 VkPipeline _pipeline)
1742 {
1743 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1744 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1745
1746 switch (pipelineBindPoint) {
1747 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1748 cmd->state.pipeline = pipeline;
1749 cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
1750 break;
1751 case VK_PIPELINE_BIND_POINT_COMPUTE:
1752 tu_finishme("binding compute pipeline");
1753 break;
1754 default:
1755 unreachable("unrecognized pipeline bind point");
1756 break;
1757 }
1758 }
1759
1760 void
1761 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
1762 uint32_t firstViewport,
1763 uint32_t viewportCount,
1764 const VkViewport *pViewports)
1765 {
1766 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1767 struct tu_cs *draw_cs = &cmd->draw_cs;
1768
1769 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
1770 if (result != VK_SUCCESS) {
1771 cmd->record_result = result;
1772 return;
1773 }
1774
1775 assert(firstViewport == 0 && viewportCount == 1);
1776 tu6_emit_viewport(draw_cs, pViewports);
1777
1778 tu_cs_sanity_check(draw_cs);
1779 }
1780
1781 void
1782 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
1783 uint32_t firstScissor,
1784 uint32_t scissorCount,
1785 const VkRect2D *pScissors)
1786 {
1787 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1788 struct tu_cs *draw_cs = &cmd->draw_cs;
1789
1790 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
1791 if (result != VK_SUCCESS) {
1792 cmd->record_result = result;
1793 return;
1794 }
1795
1796 assert(firstScissor == 0 && scissorCount == 1);
1797 tu6_emit_scissor(draw_cs, pScissors);
1798
1799 tu_cs_sanity_check(draw_cs);
1800 }
1801
1802 void
1803 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
1804 {
1805 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1806
1807 cmd->state.dynamic.line_width = lineWidth;
1808
1809 /* line width depends on VkPipelineRasterizationStateCreateInfo */
1810 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
1811 }
1812
1813 void
1814 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
1815 float depthBiasConstantFactor,
1816 float depthBiasClamp,
1817 float depthBiasSlopeFactor)
1818 {
1819 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1820 struct tu_cs *draw_cs = &cmd->draw_cs;
1821
1822 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
1823 if (result != VK_SUCCESS) {
1824 cmd->record_result = result;
1825 return;
1826 }
1827
1828 tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
1829 depthBiasSlopeFactor);
1830
1831 tu_cs_sanity_check(draw_cs);
1832 }
1833
1834 void
1835 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
1836 const float blendConstants[4])
1837 {
1838 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1839 struct tu_cs *draw_cs = &cmd->draw_cs;
1840
1841 VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
1842 if (result != VK_SUCCESS) {
1843 cmd->record_result = result;
1844 return;
1845 }
1846
1847 tu6_emit_blend_constants(draw_cs, blendConstants);
1848
1849 tu_cs_sanity_check(draw_cs);
1850 }
1851
1852 void
1853 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
1854 float minDepthBounds,
1855 float maxDepthBounds)
1856 {
1857 }
1858
1859 void
1860 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
1861 VkStencilFaceFlags faceMask,
1862 uint32_t compareMask)
1863 {
1864 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1865
1866 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1867 cmd->state.dynamic.stencil_compare_mask.front = compareMask;
1868 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1869 cmd->state.dynamic.stencil_compare_mask.back = compareMask;
1870
1871 /* the front/back compare masks must be updated together */
1872 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
1873 }
1874
1875 void
1876 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
1877 VkStencilFaceFlags faceMask,
1878 uint32_t writeMask)
1879 {
1880 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1881
1882 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1883 cmd->state.dynamic.stencil_write_mask.front = writeMask;
1884 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1885 cmd->state.dynamic.stencil_write_mask.back = writeMask;
1886
1887 /* the front/back write masks must be updated together */
1888 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
1889 }
1890
1891 void
1892 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
1893 VkStencilFaceFlags faceMask,
1894 uint32_t reference)
1895 {
1896 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1897
1898 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
1899 cmd->state.dynamic.stencil_reference.front = reference;
1900 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
1901 cmd->state.dynamic.stencil_reference.back = reference;
1902
1903 /* the front/back references must be updated together */
1904 cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
1905 }
1906
1907 void
1908 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
1909 uint32_t commandBufferCount,
1910 const VkCommandBuffer *pCmdBuffers)
1911 {
1912 }
1913
1914 VkResult
1915 tu_CreateCommandPool(VkDevice _device,
1916 const VkCommandPoolCreateInfo *pCreateInfo,
1917 const VkAllocationCallbacks *pAllocator,
1918 VkCommandPool *pCmdPool)
1919 {
1920 TU_FROM_HANDLE(tu_device, device, _device);
1921 struct tu_cmd_pool *pool;
1922
1923 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1924 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1925 if (pool == NULL)
1926 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1927
1928 if (pAllocator)
1929 pool->alloc = *pAllocator;
1930 else
1931 pool->alloc = device->alloc;
1932
1933 list_inithead(&pool->cmd_buffers);
1934 list_inithead(&pool->free_cmd_buffers);
1935
1936 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
1937
1938 *pCmdPool = tu_cmd_pool_to_handle(pool);
1939
1940 return VK_SUCCESS;
1941 }
1942
1943 void
1944 tu_DestroyCommandPool(VkDevice _device,
1945 VkCommandPool commandPool,
1946 const VkAllocationCallbacks *pAllocator)
1947 {
1948 TU_FROM_HANDLE(tu_device, device, _device);
1949 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
1950
1951 if (!pool)
1952 return;
1953
1954 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
1955 &pool->cmd_buffers, pool_link)
1956 {
1957 tu_cmd_buffer_destroy(cmd_buffer);
1958 }
1959
1960 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
1961 &pool->free_cmd_buffers, pool_link)
1962 {
1963 tu_cmd_buffer_destroy(cmd_buffer);
1964 }
1965
1966 vk_free2(&device->alloc, pAllocator, pool);
1967 }
1968
1969 VkResult
1970 tu_ResetCommandPool(VkDevice device,
1971 VkCommandPool commandPool,
1972 VkCommandPoolResetFlags flags)
1973 {
1974 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
1975 VkResult result;
1976
1977 list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
1978 pool_link)
1979 {
1980 result = tu_reset_cmd_buffer(cmd_buffer);
1981 if (result != VK_SUCCESS)
1982 return result;
1983 }
1984
1985 return VK_SUCCESS;
1986 }
1987
1988 void
1989 tu_TrimCommandPool(VkDevice device,
1990 VkCommandPool commandPool,
1991 VkCommandPoolTrimFlags flags)
1992 {
1993 TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
1994
1995 if (!pool)
1996 return;
1997
1998 list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
1999 &pool->free_cmd_buffers, pool_link)
2000 {
2001 tu_cmd_buffer_destroy(cmd_buffer);
2002 }
2003 }
2004
2005 void
2006 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2007 const VkRenderPassBeginInfo *pRenderPassBegin,
2008 VkSubpassContents contents)
2009 {
2010 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2011 TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2012 TU_FROM_HANDLE(tu_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2013 VkResult result;
2014
2015 cmd_buffer->state.pass = pass;
2016 cmd_buffer->state.subpass = pass->subpasses;
2017 cmd_buffer->state.framebuffer = framebuffer;
2018
2019 result = tu_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
2020 if (result != VK_SUCCESS)
2021 return;
2022
2023 tu_cmd_update_tiling_config(cmd_buffer, &pRenderPassBegin->renderArea);
2024 tu_cmd_prepare_tile_load_ib(cmd_buffer);
2025 tu_cmd_prepare_tile_store_ib(cmd_buffer);
2026
2027 /* draw_cs should contain entries only for this render pass */
2028 assert(!cmd_buffer->draw_cs.entry_count);
2029 tu_cs_begin(&cmd_buffer->draw_cs);
2030 }
2031
2032 void
2033 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer,
2034 const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2035 const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2036 {
2037 tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2038 pSubpassBeginInfo->contents);
2039 }
2040
2041 void
2042 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2043 {
2044 TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2045
2046 tu_cmd_render_tiles(cmd);
2047
2048 cmd->state.subpass++;
2049
2050 tu_cmd_update_tiling_config(cmd, NULL);
2051 tu_cmd_prepare_tile_load_ib(cmd);
2052 tu_cmd_prepare_tile_store_ib(cmd);
2053 }
2054
2055 void
2056 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer,
2057 const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2058 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2059 {
2060 tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2061 }
2062
2063 struct tu_draw_info
2064 {
2065 /**
2066 * Number of vertices.
2067 */
2068 uint32_t count;
2069
2070 /**
2071 * Index of the first vertex.
2072 */
2073 int32_t vertex_offset;
2074
2075 /**
2076 * First instance id.
2077 */
2078 uint32_t first_instance;
2079
2080 /**
2081 * Number of instances.
2082 */
2083 uint32_t instance_count;
2084
2085 /**
2086 * First index (indexed draws only).
2087 */
2088 uint32_t first_index;
2089
2090 /**
2091 * Whether it's an indexed draw.
2092 */
2093 bool indexed;
2094
2095 /**
2096 * Indirect draw parameters resource.
2097 */
2098 struct tu_buffer *indirect;
2099 uint64_t indirect_offset;
2100 uint32_t stride;
2101
2102 /**
2103 * Draw count parameters resource.
2104 */
2105 struct tu_buffer *count_buffer;
2106 uint64_t count_buffer_offset;
2107 };
2108
2109 enum tu_draw_state_group_id
2110 {
2111 TU_DRAW_STATE_PROGRAM,
2112 TU_DRAW_STATE_PROGRAM_BINNING,
2113 TU_DRAW_STATE_VI,
2114 TU_DRAW_STATE_VI_BINNING,
2115 TU_DRAW_STATE_VP,
2116 TU_DRAW_STATE_RAST,
2117 TU_DRAW_STATE_DS,
2118 TU_DRAW_STATE_BLEND,
2119 TU_DRAW_STATE_VS_CONST,
2120 TU_DRAW_STATE_FS_CONST,
2121 TU_DRAW_STATE_VS_TEX,
2122 TU_DRAW_STATE_FS_TEX,
2123
2124 TU_DRAW_STATE_COUNT,
2125 };
2126
2127 struct tu_draw_state_group
2128 {
2129 enum tu_draw_state_group_id id;
2130 uint32_t enable_mask;
2131 struct tu_cs_entry ib;
2132 };
2133
2134 static uint32_t*
2135 map_get(struct tu_descriptor_state *descriptors_state,
2136 const struct tu_descriptor_map *map, unsigned i)
2137 {
2138 assert(descriptors_state->valid & (1 << map->set[i]));
2139
2140 struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2141
2142 assert(map->binding[i] < set->layout->binding_count);
2143
2144 return &set->mapped_ptr[set->layout->binding[map->binding[i]].offset / 4];
2145 }
2146
2147 static inline uint32_t
2148 tu6_stage2opcode(gl_shader_stage type)
2149 {
2150 switch (type) {
2151 case MESA_SHADER_VERTEX:
2152 case MESA_SHADER_TESS_CTRL:
2153 case MESA_SHADER_TESS_EVAL:
2154 case MESA_SHADER_GEOMETRY:
2155 return CP_LOAD_STATE6_GEOM;
2156 case MESA_SHADER_FRAGMENT:
2157 case MESA_SHADER_COMPUTE:
2158 case MESA_SHADER_KERNEL:
2159 return CP_LOAD_STATE6_FRAG;
2160 default:
2161 unreachable("bad shader type");
2162 }
2163 }
2164
2165 static inline enum a6xx_state_block
2166 tu6_stage2shadersb(gl_shader_stage type)
2167 {
2168 switch (type) {
2169 case MESA_SHADER_VERTEX:
2170 return SB6_VS_SHADER;
2171 case MESA_SHADER_FRAGMENT:
2172 return SB6_FS_SHADER;
2173 case MESA_SHADER_COMPUTE:
2174 case MESA_SHADER_KERNEL:
2175 return SB6_CS_SHADER;
2176 default:
2177 unreachable("bad shader type");
2178 return ~0;
2179 }
2180 }
2181
2182 static void
2183 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2184 struct tu_descriptor_state *descriptors_state,
2185 gl_shader_stage type)
2186 {
2187 const struct tu_program_descriptor_linkage *link =
2188 &pipeline->program.link[type];
2189 const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2190
2191 for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2192 if (state->range[i].start < state->range[i].end) {
2193 assert(i && i - 1 < link->ubo_map.num);
2194 uint32_t *ptr = map_get(descriptors_state, &link->ubo_map, i - 1);
2195
2196 uint32_t size = state->range[i].end - state->range[i].start;
2197 uint32_t offset = state->range[i].start;
2198
2199 /* and even if the start of the const buffer is before
2200 * first_immediate, the end may not be:
2201 */
2202 size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2203
2204 if (size == 0)
2205 continue;
2206
2207 /* things should be aligned to vec4: */
2208 debug_assert((state->range[i].offset % 16) == 0);
2209 debug_assert((size % 16) == 0);
2210 debug_assert((offset % 16) == 0);
2211
2212 uint64_t addr = (uint64_t) ptr[1] << 32 | ptr[0];
2213 addr += state->range[i].offset;
2214
2215 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2216 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2217 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2218 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2219 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2220 CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2221 tu_cs_emit_qw(cs, addr);
2222 }
2223 }
2224 }
2225
2226 static void
2227 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2228 struct tu_descriptor_state *descriptors_state,
2229 gl_shader_stage type)
2230 {
2231 const struct tu_program_descriptor_linkage *link =
2232 &pipeline->program.link[type];
2233
2234 uint32_t anum = align(link->ubo_map.num, 2);
2235 uint32_t i;
2236
2237 if (!link->ubo_map.num)
2238 return;
2239
2240 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2241 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->offset_ubo) |
2242 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2243 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2244 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2245 CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2246 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2247 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2248
2249 for (i = 0; i < link->ubo_map.num; i++) {
2250 uint32_t *ptr = map_get(descriptors_state, &link->ubo_map, i);
2251 tu_cs_emit(cs, ptr[0]);
2252 tu_cs_emit(cs, ptr[1]);
2253 }
2254
2255 for (; i < anum; i++) {
2256 tu_cs_emit(cs, 0xffffffff);
2257 tu_cs_emit(cs, 0xffffffff);
2258 }
2259 }
2260
2261 static struct tu_cs_entry
2262 tu6_emit_consts(struct tu_device *device, struct tu_cs *draw_state,
2263 const struct tu_pipeline *pipeline,
2264 struct tu_descriptor_state *descriptors_state,
2265 gl_shader_stage type)
2266 {
2267 struct tu_cs cs;
2268 tu_cs_begin_sub_stream(device, draw_state, 512, &cs); /* TODO: maximum size? */
2269
2270 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type);
2271 tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2272
2273 return tu_cs_end_sub_stream(draw_state, &cs);
2274 }
2275
2276 static struct tu_cs_entry
2277 tu6_emit_textures(struct tu_device *device, struct tu_cs *draw_state,
2278 const struct tu_pipeline *pipeline,
2279 struct tu_descriptor_state *descriptors_state,
2280 gl_shader_stage type, bool *needs_border)
2281 {
2282 const struct tu_program_descriptor_linkage *link =
2283 &pipeline->program.link[type];
2284
2285 uint32_t size = link->texture_map.num * A6XX_TEX_CONST_DWORDS +
2286 link->sampler_map.num * A6XX_TEX_SAMP_DWORDS;
2287 if (!size)
2288 return (struct tu_cs_entry) {};
2289
2290 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
2291 enum a6xx_state_block sb;
2292
2293 switch (type) {
2294 case MESA_SHADER_VERTEX:
2295 sb = SB6_VS_TEX;
2296 opcode = CP_LOAD_STATE6_GEOM;
2297 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2298 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2299 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2300 break;
2301 case MESA_SHADER_FRAGMENT:
2302 sb = SB6_FS_TEX;
2303 opcode = CP_LOAD_STATE6_FRAG;
2304 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2305 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2306 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2307 break;
2308 case MESA_SHADER_COMPUTE:
2309 sb = SB6_CS_TEX;
2310 opcode = CP_LOAD_STATE6_FRAG;
2311 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2312 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2313 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2314 break;
2315 default:
2316 unreachable("bad state block");
2317 }
2318
2319 struct tu_cs cs;
2320 tu_cs_begin_sub_stream(device, draw_state, size, &cs);
2321
2322 for (unsigned i = 0; i < link->texture_map.num; i++) {
2323 uint32_t *ptr = map_get(descriptors_state, &link->texture_map, i);
2324
2325 for (unsigned j = 0; j < A6XX_TEX_CONST_DWORDS; j++)
2326 tu_cs_emit(&cs, ptr[j]);
2327 }
2328
2329 for (unsigned i = 0; i < link->sampler_map.num; i++) {
2330 uint32_t *ptr = map_get(descriptors_state, &link->sampler_map, i);
2331 struct tu_sampler *sampler = (void*) &ptr[A6XX_TEX_CONST_DWORDS];
2332
2333 for (unsigned j = 0; j < A6XX_TEX_SAMP_DWORDS; j++)
2334 tu_cs_emit(&cs, sampler->state[j]);
2335
2336 *needs_border |= sampler->needs_border;
2337 }
2338
2339 struct tu_cs_entry entry = tu_cs_end_sub_stream(draw_state, &cs);
2340
2341 uint64_t tex_addr = entry.bo->iova + entry.offset;
2342 uint64_t samp_addr = tex_addr + link->texture_map.num * A6XX_TEX_CONST_DWORDS*4;
2343
2344 tu_cs_begin_sub_stream(device, draw_state, 64, &cs);
2345
2346 /* output sampler state: */
2347 tu_cs_emit_pkt7(&cs, opcode, 3);
2348 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2349 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2350 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2351 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2352 CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num));
2353 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2354
2355 tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2356 tu_cs_emit_qw(&cs, samp_addr); /* SRC_ADDR_LO/HI */
2357
2358 /* emit texture state: */
2359 tu_cs_emit_pkt7(&cs, opcode, 3);
2360 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2361 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2362 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2363 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2364 CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num));
2365 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2366
2367 tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2368 tu_cs_emit_qw(&cs, tex_addr); /* SRC_ADDR_LO/HI */
2369
2370 tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2371 tu_cs_emit(&cs, link->texture_map.num);
2372
2373 return tu_cs_end_sub_stream(draw_state, &cs);
2374 }
2375
2376 static void
2377 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
2378 struct tu_cs *cs)
2379 {
2380 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2381
2382 #define A6XX_BORDER_COLOR_DWORDS (128/4)
2383 uint32_t size = A6XX_BORDER_COLOR_DWORDS *
2384 (pipeline->program.link[MESA_SHADER_VERTEX].sampler_map.num +
2385 pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map.num) +
2386 A6XX_BORDER_COLOR_DWORDS - 1; /* room for alignment */
2387
2388 struct tu_cs border_cs;
2389 tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, size, &border_cs);
2390
2391 /* TODO: actually fill with border color */
2392 for (unsigned i = 0; i < size; i++)
2393 tu_cs_emit(&border_cs, 0);
2394
2395 struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->draw_state, &border_cs);
2396
2397 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
2398 tu_cs_emit_qw(cs, align(entry.bo->iova + entry.offset, 128));
2399 }
2400
2401 static void
2402 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
2403 struct tu_cs *cs,
2404 const struct tu_draw_info *draw)
2405 {
2406 const struct tu_pipeline *pipeline = cmd->state.pipeline;
2407 const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
2408 struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
2409 uint32_t draw_state_group_count = 0;
2410
2411 struct tu_descriptor_state *descriptors_state =
2412 &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2413
2414 VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
2415 if (result != VK_SUCCESS) {
2416 cmd->record_result = result;
2417 return;
2418 }
2419
2420 /* TODO lrz */
2421
2422 uint32_t pc_primitive_cntl = 0;
2423 if (pipeline->ia.primitive_restart && draw->indexed)
2424 pc_primitive_cntl |= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART;
2425
2426 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
2427 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
2428 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
2429
2430 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
2431 tu_cs_emit(cs, pc_primitive_cntl);
2432
2433 if (cmd->state.dirty &
2434 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
2435 (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
2436 tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
2437 dynamic->line_width);
2438 }
2439
2440 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
2441 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2442 tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
2443 dynamic->stencil_compare_mask.back);
2444 }
2445
2446 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
2447 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2448 tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
2449 dynamic->stencil_write_mask.back);
2450 }
2451
2452 if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
2453 (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2454 tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
2455 dynamic->stencil_reference.back);
2456 }
2457
2458 if (cmd->state.dirty &
2459 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
2460 for (uint32_t i = 0; i < pipeline->vi.count; i++) {
2461 const uint32_t binding = pipeline->vi.bindings[i];
2462 const uint32_t stride = pipeline->vi.strides[i];
2463 const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
2464 const VkDeviceSize offset = buf->bo_offset +
2465 cmd->state.vb.offsets[binding] +
2466 pipeline->vi.offsets[i];
2467 const VkDeviceSize size =
2468 offset < buf->bo->size ? buf->bo->size - offset : 0;
2469
2470 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH(i), 4);
2471 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2472 tu_cs_emit(cs, size);
2473 tu_cs_emit(cs, stride);
2474 }
2475 }
2476
2477 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2478 draw_state_groups[draw_state_group_count++] =
2479 (struct tu_draw_state_group) {
2480 .id = TU_DRAW_STATE_PROGRAM,
2481 .enable_mask = 0x6,
2482 .ib = pipeline->program.state_ib,
2483 };
2484 draw_state_groups[draw_state_group_count++] =
2485 (struct tu_draw_state_group) {
2486 .id = TU_DRAW_STATE_PROGRAM_BINNING,
2487 .enable_mask = 0x1,
2488 .ib = pipeline->program.binning_state_ib,
2489 };
2490 draw_state_groups[draw_state_group_count++] =
2491 (struct tu_draw_state_group) {
2492 .id = TU_DRAW_STATE_VI,
2493 .enable_mask = 0x6,
2494 .ib = pipeline->vi.state_ib,
2495 };
2496 draw_state_groups[draw_state_group_count++] =
2497 (struct tu_draw_state_group) {
2498 .id = TU_DRAW_STATE_VI_BINNING,
2499 .enable_mask = 0x1,
2500 .ib = pipeline->vi.binning_state_ib,
2501 };
2502 draw_state_groups[draw_state_group_count++] =
2503 (struct tu_draw_state_group) {
2504 .id = TU_DRAW_STATE_VP,
2505 .enable_mask = 0x7,
2506 .ib = pipeline->vp.state_ib,
2507 };
2508 draw_state_groups[draw_state_group_count++] =
2509 (struct tu_draw_state_group) {
2510 .id = TU_DRAW_STATE_RAST,
2511 .enable_mask = 0x7,
2512 .ib = pipeline->rast.state_ib,
2513 };
2514 draw_state_groups[draw_state_group_count++] =
2515 (struct tu_draw_state_group) {
2516 .id = TU_DRAW_STATE_DS,
2517 .enable_mask = 0x7,
2518 .ib = pipeline->ds.state_ib,
2519 };
2520 draw_state_groups[draw_state_group_count++] =
2521 (struct tu_draw_state_group) {
2522 .id = TU_DRAW_STATE_BLEND,
2523 .enable_mask = 0x7,
2524 .ib = pipeline->blend.state_ib,
2525 };
2526 }
2527
2528 if (cmd->state.dirty &
2529 (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
2530 bool needs_border = false;
2531
2532 draw_state_groups[draw_state_group_count++] =
2533 (struct tu_draw_state_group) {
2534 .id = TU_DRAW_STATE_VS_CONST,
2535 .enable_mask = 0x7,
2536 .ib = tu6_emit_consts(cmd->device, &cmd->draw_state, pipeline,
2537 descriptors_state, MESA_SHADER_VERTEX)
2538 };
2539 draw_state_groups[draw_state_group_count++] =
2540 (struct tu_draw_state_group) {
2541 .id = TU_DRAW_STATE_FS_CONST,
2542 .enable_mask = 0x6,
2543 .ib = tu6_emit_consts(cmd->device, &cmd->draw_state, pipeline,
2544 descriptors_state, MESA_SHADER_FRAGMENT)
2545 };
2546 draw_state_groups[draw_state_group_count++] =
2547 (struct tu_draw_state_group) {
2548 .id = TU_DRAW_STATE_VS_TEX,
2549 .enable_mask = 0x7,
2550 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2551 descriptors_state, MESA_SHADER_VERTEX,
2552 &needs_border)
2553 };
2554 draw_state_groups[draw_state_group_count++] =
2555 (struct tu_draw_state_group) {
2556 .id = TU_DRAW_STATE_FS_TEX,
2557 .enable_mask = 0x6,
2558 .ib = tu6_emit_textures(cmd->device, &cmd->draw_state, pipeline,
2559 descriptors_state, MESA_SHADER_FRAGMENT,
2560 &needs_border)
2561 };
2562
2563 if (needs_border)
2564 tu6_emit_border_color(cmd, cs);
2565 }
2566
2567 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
2568 for (uint32_t i = 0; i < draw_state_group_count; i++) {
2569 const struct tu_draw_state_group *group = &draw_state_groups[i];
2570
2571 uint32_t cp_set_draw_state =
2572 CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
2573 CP_SET_DRAW_STATE__0_ENABLE_MASK(group->enable_mask) |
2574 CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
2575 uint64_t iova;
2576 if (group->ib.size) {
2577 iova = group->ib.bo->iova + group->ib.offset;
2578 } else {
2579 cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
2580 iova = 0;
2581 }
2582
2583 tu_cs_emit(cs, cp_set_draw_state);
2584 tu_cs_emit_qw(cs, iova);
2585 }
2586
2587 tu_cs_sanity_check(cs);
2588
2589 /* track BOs */
2590 if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2591 tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2592 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2593 for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2594 tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2595 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2596 }
2597 }
2598 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
2599 for (uint32_t i = 0; i < MAX_VBS; i++) {
2600 const struct tu_buffer *buf = cmd->state.vb.buffers[i];
2601 if (buf)
2602 tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
2603 }
2604 }
2605 if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
2606 unsigned i;
2607 for_each_bit(i, descriptors_state->valid) {
2608 struct tu_descriptor_set *set = descriptors_state->sets[i];
2609 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2610 if (set->descriptors[j]) {
2611 tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
2612 MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2613 }
2614 }
2615 }
2616 cmd->state.dirty = 0;
2617 }
2618
2619 static void
2620 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
2621 struct tu_cs *cs,
2622 const struct tu_draw_info *draw)
2623 {
2624
2625 const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
2626
2627 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_INDEX_OFFSET, 2);
2628 tu_cs_emit(cs, draw->vertex_offset);
2629 tu_cs_emit(cs, draw->first_instance);
2630
2631 /* TODO hw binning */
2632 if (draw->indexed) {
2633 const enum a4xx_index_size index_size =
2634 tu6_index_size(cmd->state.index_type);
2635 const uint32_t index_bytes =
2636 (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
2637 const struct tu_buffer *buf = cmd->state.index_buffer;
2638 const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
2639 index_bytes * draw->first_index;
2640 const uint32_t size = index_bytes * draw->count;
2641
2642 const uint32_t cp_draw_indx =
2643 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2644 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
2645 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
2646 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2647
2648 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
2649 tu_cs_emit(cs, cp_draw_indx);
2650 tu_cs_emit(cs, draw->instance_count);
2651 tu_cs_emit(cs, draw->count);
2652 tu_cs_emit(cs, 0x0); /* XXX */
2653 tu_cs_emit_qw(cs, buf->bo->iova + offset);
2654 tu_cs_emit(cs, size);
2655 } else {
2656 const uint32_t cp_draw_indx =
2657 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
2658 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
2659 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY) | 0x2000;
2660
2661 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
2662 tu_cs_emit(cs, cp_draw_indx);
2663 tu_cs_emit(cs, draw->instance_count);
2664 tu_cs_emit(cs, draw->count);
2665 }
2666 }
2667
2668 static void
2669 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
2670 {
2671 struct tu_cs *cs = &cmd->draw_cs;
2672
2673 tu6_bind_draw_states(cmd, cs, draw);
2674
2675 VkResult result = tu_cs_reserve_space(cmd->device, cs, 32);
2676 if (result != VK_SUCCESS) {
2677 cmd->record_result = result;
2678 return;
2679 }
2680
2681 if (draw->indirect) {
2682 tu_finishme("indirect draw");
2683 return;
2684 }
2685
2686 /* TODO tu6_emit_marker should pick different regs depending on cs */
2687 tu6_emit_marker(cmd, cs);
2688 tu6_emit_draw_direct(cmd, cs, draw);
2689 tu6_emit_marker(cmd, cs);
2690
2691 cmd->wait_for_idle = true;
2692
2693 tu_cs_sanity_check(cs);
2694 }
2695
2696 void
2697 tu_CmdDraw(VkCommandBuffer commandBuffer,
2698 uint32_t vertexCount,
2699 uint32_t instanceCount,
2700 uint32_t firstVertex,
2701 uint32_t firstInstance)
2702 {
2703 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2704 struct tu_draw_info info = {};
2705
2706 info.count = vertexCount;
2707 info.instance_count = instanceCount;
2708 info.first_instance = firstInstance;
2709 info.vertex_offset = firstVertex;
2710
2711 tu_draw(cmd_buffer, &info);
2712 }
2713
2714 void
2715 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
2716 uint32_t indexCount,
2717 uint32_t instanceCount,
2718 uint32_t firstIndex,
2719 int32_t vertexOffset,
2720 uint32_t firstInstance)
2721 {
2722 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2723 struct tu_draw_info info = {};
2724
2725 info.indexed = true;
2726 info.count = indexCount;
2727 info.instance_count = instanceCount;
2728 info.first_index = firstIndex;
2729 info.vertex_offset = vertexOffset;
2730 info.first_instance = firstInstance;
2731
2732 tu_draw(cmd_buffer, &info);
2733 }
2734
2735 void
2736 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
2737 VkBuffer _buffer,
2738 VkDeviceSize offset,
2739 uint32_t drawCount,
2740 uint32_t stride)
2741 {
2742 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2743 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2744 struct tu_draw_info info = {};
2745
2746 info.count = drawCount;
2747 info.indirect = buffer;
2748 info.indirect_offset = offset;
2749 info.stride = stride;
2750
2751 tu_draw(cmd_buffer, &info);
2752 }
2753
2754 void
2755 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
2756 VkBuffer _buffer,
2757 VkDeviceSize offset,
2758 uint32_t drawCount,
2759 uint32_t stride)
2760 {
2761 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2762 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2763 struct tu_draw_info info = {};
2764
2765 info.indexed = true;
2766 info.count = drawCount;
2767 info.indirect = buffer;
2768 info.indirect_offset = offset;
2769 info.stride = stride;
2770
2771 tu_draw(cmd_buffer, &info);
2772 }
2773
2774 struct tu_dispatch_info
2775 {
2776 /**
2777 * Determine the layout of the grid (in block units) to be used.
2778 */
2779 uint32_t blocks[3];
2780
2781 /**
2782 * A starting offset for the grid. If unaligned is set, the offset
2783 * must still be aligned.
2784 */
2785 uint32_t offsets[3];
2786 /**
2787 * Whether it's an unaligned compute dispatch.
2788 */
2789 bool unaligned;
2790
2791 /**
2792 * Indirect compute parameters resource.
2793 */
2794 struct tu_buffer *indirect;
2795 uint64_t indirect_offset;
2796 };
2797
2798 static void
2799 tu_dispatch(struct tu_cmd_buffer *cmd_buffer,
2800 const struct tu_dispatch_info *info)
2801 {
2802 }
2803
2804 void
2805 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
2806 uint32_t base_x,
2807 uint32_t base_y,
2808 uint32_t base_z,
2809 uint32_t x,
2810 uint32_t y,
2811 uint32_t z)
2812 {
2813 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2814 struct tu_dispatch_info info = {};
2815
2816 info.blocks[0] = x;
2817 info.blocks[1] = y;
2818 info.blocks[2] = z;
2819
2820 info.offsets[0] = base_x;
2821 info.offsets[1] = base_y;
2822 info.offsets[2] = base_z;
2823 tu_dispatch(cmd_buffer, &info);
2824 }
2825
2826 void
2827 tu_CmdDispatch(VkCommandBuffer commandBuffer,
2828 uint32_t x,
2829 uint32_t y,
2830 uint32_t z)
2831 {
2832 tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
2833 }
2834
2835 void
2836 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
2837 VkBuffer _buffer,
2838 VkDeviceSize offset)
2839 {
2840 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2841 TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
2842 struct tu_dispatch_info info = {};
2843
2844 info.indirect = buffer;
2845 info.indirect_offset = offset;
2846
2847 tu_dispatch(cmd_buffer, &info);
2848 }
2849
2850 void
2851 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
2852 {
2853 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2854
2855 tu_cs_end(&cmd_buffer->draw_cs);
2856
2857 tu_cmd_render_tiles(cmd_buffer);
2858
2859 /* discard draw_cs entries now that the tiles are rendered */
2860 tu_cs_discard_entries(&cmd_buffer->draw_cs);
2861
2862 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2863 cmd_buffer->state.attachments = NULL;
2864
2865 cmd_buffer->state.pass = NULL;
2866 cmd_buffer->state.subpass = NULL;
2867 cmd_buffer->state.framebuffer = NULL;
2868 }
2869
2870 void
2871 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer,
2872 const VkSubpassEndInfoKHR *pSubpassEndInfo)
2873 {
2874 tu_CmdEndRenderPass(commandBuffer);
2875 }
2876
2877 struct tu_barrier_info
2878 {
2879 uint32_t eventCount;
2880 const VkEvent *pEvents;
2881 VkPipelineStageFlags srcStageMask;
2882 };
2883
2884 static void
2885 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
2886 uint32_t memoryBarrierCount,
2887 const VkMemoryBarrier *pMemoryBarriers,
2888 uint32_t bufferMemoryBarrierCount,
2889 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
2890 uint32_t imageMemoryBarrierCount,
2891 const VkImageMemoryBarrier *pImageMemoryBarriers,
2892 const struct tu_barrier_info *info)
2893 {
2894 }
2895
2896 void
2897 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
2898 VkPipelineStageFlags srcStageMask,
2899 VkPipelineStageFlags destStageMask,
2900 VkBool32 byRegion,
2901 uint32_t memoryBarrierCount,
2902 const VkMemoryBarrier *pMemoryBarriers,
2903 uint32_t bufferMemoryBarrierCount,
2904 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
2905 uint32_t imageMemoryBarrierCount,
2906 const VkImageMemoryBarrier *pImageMemoryBarriers)
2907 {
2908 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2909 struct tu_barrier_info info;
2910
2911 info.eventCount = 0;
2912 info.pEvents = NULL;
2913 info.srcStageMask = srcStageMask;
2914
2915 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
2916 bufferMemoryBarrierCount, pBufferMemoryBarriers,
2917 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
2918 }
2919
2920 static void
2921 write_event(struct tu_cmd_buffer *cmd_buffer,
2922 struct tu_event *event,
2923 VkPipelineStageFlags stageMask,
2924 unsigned value)
2925 {
2926 }
2927
2928 void
2929 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
2930 VkEvent _event,
2931 VkPipelineStageFlags stageMask)
2932 {
2933 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2934 TU_FROM_HANDLE(tu_event, event, _event);
2935
2936 write_event(cmd_buffer, event, stageMask, 1);
2937 }
2938
2939 void
2940 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
2941 VkEvent _event,
2942 VkPipelineStageFlags stageMask)
2943 {
2944 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2945 TU_FROM_HANDLE(tu_event, event, _event);
2946
2947 write_event(cmd_buffer, event, stageMask, 0);
2948 }
2949
2950 void
2951 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
2952 uint32_t eventCount,
2953 const VkEvent *pEvents,
2954 VkPipelineStageFlags srcStageMask,
2955 VkPipelineStageFlags dstStageMask,
2956 uint32_t memoryBarrierCount,
2957 const VkMemoryBarrier *pMemoryBarriers,
2958 uint32_t bufferMemoryBarrierCount,
2959 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
2960 uint32_t imageMemoryBarrierCount,
2961 const VkImageMemoryBarrier *pImageMemoryBarriers)
2962 {
2963 TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2964 struct tu_barrier_info info;
2965
2966 info.eventCount = eventCount;
2967 info.pEvents = pEvents;
2968 info.srcStageMask = 0;
2969
2970 tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
2971 bufferMemoryBarrierCount, pBufferMemoryBarriers,
2972 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
2973 }
2974
2975 void
2976 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
2977 {
2978 /* No-op */
2979 }