2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
33 #include "vk_format.h"
38 tu_bo_list_init(struct tu_bo_list
*list
)
40 list
->count
= list
->capacity
= 0;
41 list
->bo_infos
= NULL
;
45 tu_bo_list_destroy(struct tu_bo_list
*list
)
51 tu_bo_list_reset(struct tu_bo_list
*list
)
57 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 tu_bo_list_add_info(struct tu_bo_list
*list
,
61 const struct drm_msm_gem_submit_bo
*bo_info
)
63 assert(bo_info
->handle
!= 0);
65 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
66 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
67 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
68 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
73 /* grow list->bo_infos if needed */
74 if (list
->count
== list
->capacity
) {
75 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
76 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
77 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
79 return TU_BO_LIST_FAILED
;
80 list
->bo_infos
= new_bo_infos
;
81 list
->capacity
= new_capacity
;
84 list
->bo_infos
[list
->count
] = *bo_info
;
89 tu_bo_list_add(struct tu_bo_list
*list
,
90 const struct tu_bo
*bo
,
93 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
95 .handle
= bo
->gem_handle
,
101 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
103 for (uint32_t i
= 0; i
< other
->count
; i
++) {
104 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
105 return VK_ERROR_OUT_OF_HOST_MEMORY
;
112 tu_tiling_config_update_tile_layout(struct tu_tiling_config
*tiling
,
113 const struct tu_device
*dev
,
114 const struct tu_render_pass
*pass
)
116 const uint32_t tile_align_w
= pass
->tile_align_w
;
117 const uint32_t max_tile_width
= 1024;
119 /* note: don't offset the tiling config by render_area.offset,
120 * because binning pass can't deal with it
121 * this means we might end up with more tiles than necessary,
122 * but load/store/etc are still scissored to the render_area
124 tiling
->tile0
.offset
= (VkOffset2D
) {};
126 const uint32_t ra_width
=
127 tiling
->render_area
.extent
.width
+
128 (tiling
->render_area
.offset
.x
- tiling
->tile0
.offset
.x
);
129 const uint32_t ra_height
=
130 tiling
->render_area
.extent
.height
+
131 (tiling
->render_area
.offset
.y
- tiling
->tile0
.offset
.y
);
133 /* start from 1 tile */
134 tiling
->tile_count
= (VkExtent2D
) {
138 tiling
->tile0
.extent
= (VkExtent2D
) {
139 .width
= util_align_npot(ra_width
, tile_align_w
),
140 .height
= align(ra_height
, TILE_ALIGN_H
),
143 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
)) {
144 /* start with 2x2 tiles */
145 tiling
->tile_count
.width
= 2;
146 tiling
->tile_count
.height
= 2;
147 tiling
->tile0
.extent
.width
= util_align_npot(DIV_ROUND_UP(ra_width
, 2), tile_align_w
);
148 tiling
->tile0
.extent
.height
= align(DIV_ROUND_UP(ra_height
, 2), TILE_ALIGN_H
);
151 /* do not exceed max tile width */
152 while (tiling
->tile0
.extent
.width
> max_tile_width
) {
153 tiling
->tile_count
.width
++;
154 tiling
->tile0
.extent
.width
=
155 util_align_npot(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
158 /* will force to sysmem, don't bother trying to have a valid tile config
159 * TODO: just skip all GMEM stuff when sysmem is forced?
161 if (!pass
->gmem_pixels
)
164 /* do not exceed gmem size */
165 while (tiling
->tile0
.extent
.width
* tiling
->tile0
.extent
.height
> pass
->gmem_pixels
) {
166 if (tiling
->tile0
.extent
.width
> MAX2(tile_align_w
, tiling
->tile0
.extent
.height
)) {
167 tiling
->tile_count
.width
++;
168 tiling
->tile0
.extent
.width
=
169 util_align_npot(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
171 /* if this assert fails then layout is impossible.. */
172 assert(tiling
->tile0
.extent
.height
> TILE_ALIGN_H
);
173 tiling
->tile_count
.height
++;
174 tiling
->tile0
.extent
.height
=
175 align(DIV_ROUND_UP(ra_height
, tiling
->tile_count
.height
), TILE_ALIGN_H
);
181 tu_tiling_config_update_pipe_layout(struct tu_tiling_config
*tiling
,
182 const struct tu_device
*dev
)
184 const uint32_t max_pipe_count
= 32; /* A6xx */
186 /* start from 1 tile per pipe */
187 tiling
->pipe0
= (VkExtent2D
) {
191 tiling
->pipe_count
= tiling
->tile_count
;
193 while (tiling
->pipe_count
.width
* tiling
->pipe_count
.height
> max_pipe_count
) {
194 if (tiling
->pipe0
.width
< tiling
->pipe0
.height
) {
195 tiling
->pipe0
.width
+= 1;
196 tiling
->pipe_count
.width
=
197 DIV_ROUND_UP(tiling
->tile_count
.width
, tiling
->pipe0
.width
);
199 tiling
->pipe0
.height
+= 1;
200 tiling
->pipe_count
.height
=
201 DIV_ROUND_UP(tiling
->tile_count
.height
, tiling
->pipe0
.height
);
207 tu_tiling_config_update_pipes(struct tu_tiling_config
*tiling
,
208 const struct tu_device
*dev
)
210 const uint32_t max_pipe_count
= 32; /* A6xx */
211 const uint32_t used_pipe_count
=
212 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
213 const VkExtent2D last_pipe
= {
214 .width
= (tiling
->tile_count
.width
- 1) % tiling
->pipe0
.width
+ 1,
215 .height
= (tiling
->tile_count
.height
- 1) % tiling
->pipe0
.height
+ 1,
218 assert(used_pipe_count
<= max_pipe_count
);
219 assert(max_pipe_count
<= ARRAY_SIZE(tiling
->pipe_config
));
221 for (uint32_t y
= 0; y
< tiling
->pipe_count
.height
; y
++) {
222 for (uint32_t x
= 0; x
< tiling
->pipe_count
.width
; x
++) {
223 const uint32_t pipe_x
= tiling
->pipe0
.width
* x
;
224 const uint32_t pipe_y
= tiling
->pipe0
.height
* y
;
225 const uint32_t pipe_w
= (x
== tiling
->pipe_count
.width
- 1)
227 : tiling
->pipe0
.width
;
228 const uint32_t pipe_h
= (y
== tiling
->pipe_count
.height
- 1)
230 : tiling
->pipe0
.height
;
231 const uint32_t n
= tiling
->pipe_count
.width
* y
+ x
;
233 tiling
->pipe_config
[n
] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x
) |
234 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y
) |
235 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w
) |
236 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h
);
237 tiling
->pipe_sizes
[n
] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w
* pipe_h
);
241 memset(tiling
->pipe_config
+ used_pipe_count
, 0,
242 sizeof(uint32_t) * (max_pipe_count
- used_pipe_count
));
246 tu_tiling_config_get_tile(const struct tu_tiling_config
*tiling
,
247 const struct tu_device
*dev
,
250 struct tu_tile
*tile
)
252 /* find the pipe and the slot for tile (tx, ty) */
253 const uint32_t px
= tx
/ tiling
->pipe0
.width
;
254 const uint32_t py
= ty
/ tiling
->pipe0
.height
;
255 const uint32_t sx
= tx
- tiling
->pipe0
.width
* px
;
256 const uint32_t sy
= ty
- tiling
->pipe0
.height
* py
;
257 /* last pipe has different width */
258 const uint32_t pipe_width
=
259 MIN2(tiling
->pipe0
.width
,
260 tiling
->tile_count
.width
- px
* tiling
->pipe0
.width
);
262 assert(tx
< tiling
->tile_count
.width
&& ty
< tiling
->tile_count
.height
);
263 assert(px
< tiling
->pipe_count
.width
&& py
< tiling
->pipe_count
.height
);
264 assert(sx
< tiling
->pipe0
.width
&& sy
< tiling
->pipe0
.height
);
266 /* convert to 1D indices */
267 tile
->pipe
= tiling
->pipe_count
.width
* py
+ px
;
268 tile
->slot
= pipe_width
* sy
+ sx
;
270 /* get the blit area for the tile */
271 tile
->begin
= (VkOffset2D
) {
272 .x
= tiling
->tile0
.offset
.x
+ tiling
->tile0
.extent
.width
* tx
,
273 .y
= tiling
->tile0
.offset
.y
+ tiling
->tile0
.extent
.height
* ty
,
276 (tx
== tiling
->tile_count
.width
- 1)
277 ? tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
278 : tile
->begin
.x
+ tiling
->tile0
.extent
.width
;
280 (ty
== tiling
->tile_count
.height
- 1)
281 ? tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
282 : tile
->begin
.y
+ tiling
->tile0
.extent
.height
;
286 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
288 enum vgt_event_type event
)
290 bool need_seqno
= false;
295 case PC_CCU_FLUSH_DEPTH_TS
:
296 case PC_CCU_FLUSH_COLOR_TS
:
297 case PC_CCU_RESOLVE_TS
:
304 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
305 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
307 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
313 tu6_emit_flushes(struct tu_cmd_buffer
*cmd_buffer
,
315 enum tu_cmd_flush_bits flushes
)
317 /* Experiments show that invalidating CCU while it still has data in it
318 * doesn't work, so make sure to always flush before invalidating in case
319 * any data remains that hasn't yet been made available through a barrier.
320 * However it does seem to work for UCHE.
322 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_COLOR
|
323 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
))
324 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_COLOR_TS
);
325 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
326 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
))
327 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_DEPTH_TS
);
328 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_COLOR
)
329 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_COLOR
);
330 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
)
331 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_DEPTH
);
332 if (flushes
& TU_CMD_FLAG_CACHE_FLUSH
)
333 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_FLUSH_TS
);
334 if (flushes
& TU_CMD_FLAG_CACHE_INVALIDATE
)
335 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_INVALIDATE
);
336 if (flushes
& TU_CMD_FLAG_WFI
)
340 /* "Normal" cache flushes, that don't require any special handling */
343 tu_emit_cache_flush(struct tu_cmd_buffer
*cmd_buffer
,
346 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.cache
.flush_bits
);
347 cmd_buffer
->state
.cache
.flush_bits
= 0;
350 /* Renderpass cache flushes */
353 tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
356 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.renderpass_cache
.flush_bits
);
357 cmd_buffer
->state
.renderpass_cache
.flush_bits
= 0;
360 /* Cache flushes for things that use the color/depth read/write path (i.e.
361 * blits and draws). This deals with changing CCU state as well as the usual
366 tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
368 enum tu_cmd_ccu_state ccu_state
)
370 enum tu_cmd_flush_bits flushes
= cmd_buffer
->state
.cache
.flush_bits
;
372 assert(ccu_state
!= TU_CMD_CCU_UNKNOWN
);
374 /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
375 * the CCU may also contain data that we haven't flushed out yet, so we
376 * also need to flush. Also, in order to program RB_CCU_CNTL, we need to
377 * emit a WFI as it isn't pipelined.
379 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
380 if (cmd_buffer
->state
.ccu_state
!= TU_CMD_CCU_GMEM
) {
382 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
383 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
384 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
385 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
386 TU_CMD_FLAG_CCU_FLUSH_DEPTH
);
389 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
390 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
392 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
393 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
394 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
);
397 tu6_emit_flushes(cmd_buffer
, cs
, flushes
);
398 cmd_buffer
->state
.cache
.flush_bits
= 0;
400 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
401 struct tu_physical_device
*phys_dev
= cmd_buffer
->device
->physical_device
;
403 A6XX_RB_CCU_CNTL(.offset
=
404 ccu_state
== TU_CMD_CCU_GMEM
?
405 phys_dev
->ccu_offset_gmem
:
406 phys_dev
->ccu_offset_bypass
,
407 .gmem
= ccu_state
== TU_CMD_CCU_GMEM
));
408 cmd_buffer
->state
.ccu_state
= ccu_state
;
413 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
414 const struct tu_subpass
*subpass
,
417 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
419 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
420 if (a
== VK_ATTACHMENT_UNUSED
) {
422 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
423 A6XX_RB_DEPTH_BUFFER_PITCH(0),
424 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
425 A6XX_RB_DEPTH_BUFFER_BASE(0),
426 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
429 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
432 A6XX_GRAS_LRZ_BUFFER_BASE(0),
433 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
434 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
436 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
441 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
442 const struct tu_render_pass_attachment
*attachment
=
443 &cmd
->state
.pass
->attachments
[a
];
444 enum a6xx_depth_format fmt
= tu6_pipe2depth(attachment
->format
);
446 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
447 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
).value
);
448 tu_cs_image_ref(cs
, iview
, 0);
449 tu_cs_emit(cs
, attachment
->gmem_offset
);
452 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
454 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
455 tu_cs_image_flag_ref(cs
, iview
, 0);
458 A6XX_GRAS_LRZ_BUFFER_BASE(0),
459 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
460 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
462 if (attachment
->format
== VK_FORMAT_S8_UINT
) {
463 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 6);
464 tu_cs_emit(cs
, A6XX_RB_STENCIL_INFO(.separate_stencil
= true).value
);
465 tu_cs_image_ref(cs
, iview
, 0);
466 tu_cs_emit(cs
, attachment
->gmem_offset
);
469 A6XX_RB_STENCIL_INFO(0));
474 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
475 const struct tu_subpass
*subpass
,
478 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
480 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
481 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
482 if (a
== VK_ATTACHMENT_UNUSED
)
485 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
487 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
488 tu_cs_emit(cs
, iview
->RB_MRT_BUF_INFO
);
489 tu_cs_image_ref(cs
, iview
, 0);
490 tu_cs_emit(cs
, cmd
->state
.pass
->attachments
[a
].gmem_offset
);
493 A6XX_SP_FS_MRT_REG(i
, .dword
= iview
->SP_FS_MRT_REG
));
495 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i
), 3);
496 tu_cs_image_flag_ref(cs
, iview
, 0);
500 A6XX_RB_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
502 A6XX_SP_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
504 tu_cs_emit_regs(cs
, A6XX_GRAS_MAX_LAYER_INDEX(fb
->layers
- 1));
508 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
510 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
511 bool msaa_disable
= samples
== MSAA_ONE
;
514 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
515 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
516 .msaa_disable
= msaa_disable
));
519 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
520 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
521 .msaa_disable
= msaa_disable
));
524 A6XX_RB_RAS_MSAA_CNTL(samples
),
525 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
526 .msaa_disable
= msaa_disable
));
529 A6XX_RB_MSAA_CNTL(samples
));
533 tu6_emit_bin_size(struct tu_cs
*cs
,
534 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
537 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
542 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
546 /* no flag for RB_BIN_CONTROL2... */
548 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
553 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
554 const struct tu_subpass
*subpass
,
558 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
560 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
562 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
564 uint32_t mrts_ubwc_enable
= 0;
565 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
566 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
567 if (a
== VK_ATTACHMENT_UNUSED
)
570 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
571 if (iview
->ubwc_enabled
)
572 mrts_ubwc_enable
|= 1 << i
;
575 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
577 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
578 if (a
!= VK_ATTACHMENT_UNUSED
) {
579 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
580 if (iview
->ubwc_enabled
)
581 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
584 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
585 * in order to set it correctly for the different subpasses. However,
586 * that means the packets we're emitting also happen during binning. So
587 * we need to guard the write on !BINNING at CP execution time.
589 tu_cs_reserve(cs
, 3 + 4);
590 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
591 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
592 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
593 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
596 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
597 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
598 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
599 tu_cs_emit(cs
, cntl
);
603 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
605 const VkRect2D
*render_area
= &cmd
->state
.tiling_config
.render_area
;
606 uint32_t x1
= render_area
->offset
.x
;
607 uint32_t y1
= render_area
->offset
.y
;
608 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
609 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
612 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
613 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
614 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
615 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
619 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
620 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
624 tu6_emit_window_scissor(struct tu_cs
*cs
,
631 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
632 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
635 A6XX_GRAS_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
636 A6XX_GRAS_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
640 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
643 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
646 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
649 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
652 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
656 tu_cs_emit_draw_state(struct tu_cs
*cs
, uint32_t id
, struct tu_draw_state state
)
658 uint32_t enable_mask
;
660 case TU_DRAW_STATE_PROGRAM
:
661 case TU_DRAW_STATE_VI
:
662 case TU_DRAW_STATE_FS_CONST
:
663 /* The blob seems to not enable this (DESC_SETS_LOAD) for binning, even
664 * when resources would actually be used in the binning shader.
665 * Presumably the overhead of prefetching the resources isn't
668 case TU_DRAW_STATE_DESC_SETS_LOAD
:
669 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
670 CP_SET_DRAW_STATE__0_SYSMEM
;
672 case TU_DRAW_STATE_PROGRAM_BINNING
:
673 case TU_DRAW_STATE_VI_BINNING
:
674 enable_mask
= CP_SET_DRAW_STATE__0_BINNING
;
676 case TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
:
677 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
;
679 case TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
:
680 enable_mask
= CP_SET_DRAW_STATE__0_SYSMEM
;
683 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
684 CP_SET_DRAW_STATE__0_SYSMEM
|
685 CP_SET_DRAW_STATE__0_BINNING
;
689 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(state
.size
) |
691 CP_SET_DRAW_STATE__0_GROUP_ID(id
) |
692 COND(!state
.size
, CP_SET_DRAW_STATE__0_DISABLE
));
693 tu_cs_emit_qw(cs
, state
.iova
);
696 /* note: get rid of this eventually */
698 tu_cs_emit_sds_ib(struct tu_cs
*cs
, uint32_t id
, struct tu_cs_entry entry
)
700 tu_cs_emit_draw_state(cs
, id
, (struct tu_draw_state
) {
701 .iova
= entry
.size
? entry
.bo
->iova
+ entry
.offset
: 0,
702 .size
= entry
.size
/ 4,
707 use_hw_binning(struct tu_cmd_buffer
*cmd
)
709 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
711 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
714 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
717 return (tiling
->tile_count
.width
* tiling
->tile_count
.height
) > 2;
721 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
723 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
726 /* can't fit attachments into gmem */
727 if (!cmd
->state
.pass
->gmem_pixels
)
730 if (cmd
->state
.framebuffer
->layers
> 1)
736 return cmd
->state
.tiling_config
.force_sysmem
;
740 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
742 const struct tu_tile
*tile
)
744 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
745 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
747 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
748 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
750 const uint32_t x1
= tile
->begin
.x
;
751 const uint32_t y1
= tile
->begin
.y
;
752 const uint32_t x2
= tile
->end
.x
- 1;
753 const uint32_t y2
= tile
->end
.y
- 1;
754 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
755 tu6_emit_window_offset(cs
, x1
, y1
);
758 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
760 if (use_hw_binning(cmd
)) {
761 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
763 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
766 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5
, 7);
767 tu_cs_emit(cs
, cmd
->state
.tiling_config
.pipe_sizes
[tile
->pipe
] |
768 CP_SET_BIN_DATA5_0_VSC_N(tile
->slot
));
769 tu_cs_emit_qw(cs
, cmd
->vsc_draw_strm
.iova
+ tile
->pipe
* cmd
->vsc_draw_strm_pitch
);
770 tu_cs_emit_qw(cs
, cmd
->vsc_draw_strm
.iova
+ (tile
->pipe
* 4) + (32 * cmd
->vsc_draw_strm_pitch
));
771 tu_cs_emit_qw(cs
, cmd
->vsc_prim_strm
.iova
+ (tile
->pipe
* cmd
->vsc_prim_strm_pitch
));
773 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
776 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
779 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
782 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
788 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
793 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
794 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
795 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
797 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.tiling_config
.render_area
);
801 tu6_emit_sysmem_resolves(struct tu_cmd_buffer
*cmd
,
803 const struct tu_subpass
*subpass
)
805 if (subpass
->resolve_attachments
) {
806 /* From the documentation for vkCmdNextSubpass, section 7.4 "Render Pass
809 * End-of-subpass multisample resolves are treated as color
810 * attachment writes for the purposes of synchronization. That is,
811 * they are considered to execute in the
812 * VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage and
813 * their writes are synchronized with
814 * VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT. Synchronization between
815 * rendering within a subpass and any resolve operations at the end
816 * of the subpass occurs automatically, without need for explicit
817 * dependencies or pipeline barriers. However, if the resolve
818 * attachment is also used in a different subpass, an explicit
819 * dependency is needed.
821 * We use the CP_BLIT path for sysmem resolves, which is really a
822 * transfer command, so we have to manually flush similar to the gmem
823 * resolve case. However, a flush afterwards isn't needed because of the
824 * last sentence and the fact that we're in sysmem mode.
826 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
);
827 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
829 /* Wait for the flushes to land before using the 2D engine */
832 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
833 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
834 if (a
== VK_ATTACHMENT_UNUSED
)
837 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
838 subpass
->color_attachments
[i
].attachment
);
844 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
846 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
847 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
849 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
850 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
851 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
852 CP_SET_DRAW_STATE__0_GROUP_ID(0));
853 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
854 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
856 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
859 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
860 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
862 tu6_emit_blit_scissor(cmd
, cs
, true);
864 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
865 if (pass
->attachments
[a
].gmem_offset
>= 0)
866 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
869 if (subpass
->resolve_attachments
) {
870 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
871 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
872 if (a
!= VK_ATTACHMENT_UNUSED
)
873 tu_store_gmem_attachment(cmd
, cs
, a
,
874 subpass
->color_attachments
[i
].attachment
);
880 tu6_emit_restart_index(struct tu_cs
*cs
, uint32_t restart_index
)
883 A6XX_PC_RESTART_INDEX(restart_index
));
887 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
889 const struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
891 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
893 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 0xfffff);
896 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
897 cmd
->state
.ccu_state
= TU_CMD_CCU_SYSMEM
;
898 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
899 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
900 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
901 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
902 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
903 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
904 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
905 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
907 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
908 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
909 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
910 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
911 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
912 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
913 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BB11
, 0);
914 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
915 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
916 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
917 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
918 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
919 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
920 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_GS_SIV_CNTL
, 0x0000ffff);
922 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
923 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
924 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
926 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
928 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
930 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
931 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
932 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
933 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
934 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
935 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
936 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
937 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
938 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
939 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
940 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
942 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9101
, 0xffff00);
943 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
945 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9236
,
946 A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
947 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
949 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_SO_OVERRIDE
,
950 A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
952 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
953 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
954 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9990
, 0);
956 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
957 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
959 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
961 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
963 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
964 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_809B
, 0);
965 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
966 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
967 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
968 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
969 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
970 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9981
, 0x3);
971 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
972 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9108
, 0x3);
973 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
974 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8878
, 0);
975 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8879
, 0);
976 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
978 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
980 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
982 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
984 /* we don't use this yet.. probably best to disable.. */
985 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
986 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
987 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
988 CP_SET_DRAW_STATE__0_GROUP_ID(0));
989 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
990 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
992 /* Set not to use streamout by default, */
993 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
994 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
996 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
1000 A6XX_SP_HS_CTRL_REG0(0));
1003 A6XX_SP_GS_CTRL_REG0(0));
1006 A6XX_GRAS_LRZ_CNTL(0));
1009 A6XX_RB_LRZ_CNTL(0));
1012 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
1014 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
1016 tu_cs_sanity_check(cs
);
1020 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1022 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1025 A6XX_VSC_BIN_SIZE(.width
= tiling
->tile0
.extent
.width
,
1026 .height
= tiling
->tile0
.extent
.height
),
1027 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo
= &cmd
->vsc_draw_strm
,
1028 .bo_offset
= 32 * cmd
->vsc_draw_strm_pitch
));
1031 A6XX_VSC_BIN_COUNT(.nx
= tiling
->tile_count
.width
,
1032 .ny
= tiling
->tile_count
.height
));
1034 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1035 for (unsigned i
= 0; i
< 32; i
++)
1036 tu_cs_emit(cs
, tiling
->pipe_config
[i
]);
1039 A6XX_VSC_PRIM_STRM_ADDRESS(.bo
= &cmd
->vsc_prim_strm
),
1040 A6XX_VSC_PRIM_STRM_PITCH(cmd
->vsc_prim_strm_pitch
),
1041 A6XX_VSC_PRIM_STRM_LIMIT(cmd
->vsc_prim_strm_pitch
- 64));
1044 A6XX_VSC_DRAW_STRM_ADDRESS(.bo
= &cmd
->vsc_draw_strm
),
1045 A6XX_VSC_DRAW_STRM_PITCH(cmd
->vsc_draw_strm_pitch
),
1046 A6XX_VSC_DRAW_STRM_LIMIT(cmd
->vsc_draw_strm_pitch
- 64));
1050 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1052 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1053 const uint32_t used_pipe_count
=
1054 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
1056 /* Clear vsc_scratch: */
1057 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
1058 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1059 tu_cs_emit(cs
, 0x0);
1061 /* Check for overflow, write vsc_scratch if detected: */
1062 for (int i
= 0; i
< used_pipe_count
; i
++) {
1063 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1064 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1065 CP_COND_WRITE5_0_WRITE_MEMORY
);
1066 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i
)));
1067 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1068 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_draw_strm_pitch
- 64));
1069 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1070 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1071 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd
->vsc_draw_strm_pitch
));
1073 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1074 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1075 CP_COND_WRITE5_0_WRITE_MEMORY
);
1076 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i
)));
1077 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1078 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_prim_strm_pitch
- 64));
1079 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1080 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1081 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd
->vsc_prim_strm_pitch
));
1084 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
1088 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1090 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1091 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1093 uint32_t x1
= tiling
->tile0
.offset
.x
;
1094 uint32_t y1
= tiling
->tile0
.offset
.y
;
1095 uint32_t x2
= tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
- 1;
1096 uint32_t y2
= tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
- 1;
1098 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
1100 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1101 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
1103 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1104 tu_cs_emit(cs
, 0x1);
1106 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1107 tu_cs_emit(cs
, 0x1);
1112 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
1114 update_vsc_pipe(cmd
, cs
);
1117 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1120 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1122 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1123 tu_cs_emit(cs
, UNK_2C
);
1126 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
1129 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
1131 /* emit IB to binning drawcmds: */
1132 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1134 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1135 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1136 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1137 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1138 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1139 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1141 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1142 tu_cs_emit(cs
, UNK_2D
);
1144 /* This flush is probably required because the VSC, which produces the
1145 * visibility stream, is a client of UCHE, whereas the CP needs to read the
1146 * visibility stream (without caching) to do draw skipping. The
1147 * WFI+WAIT_FOR_ME combination guarantees that the binning commands
1148 * submitted are finished before reading the VSC regs (in
1149 * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
1152 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
);
1156 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1158 emit_vsc_overflow_test(cmd
, cs
);
1160 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1161 tu_cs_emit(cs
, 0x0);
1163 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1164 tu_cs_emit(cs
, 0x0);
1168 tu_emit_input_attachments(struct tu_cmd_buffer
*cmd
,
1169 const struct tu_subpass
*subpass
,
1170 struct tu_cs_entry
*ib
,
1173 /* note: we can probably emit input attachments just once for the whole
1174 * renderpass, this would avoid emitting both sysmem/gmem versions
1176 * emit two texture descriptors for each input, as a workaround for
1177 * d24s8, which can be sampled as both float (depth) and integer (stencil)
1178 * tu_shader lowers uint input attachment loads to use the 2nd descriptor
1180 * TODO: a smarter workaround
1183 if (!subpass
->input_count
)
1186 struct ts_cs_memory texture
;
1187 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, subpass
->input_count
* 2,
1188 A6XX_TEX_CONST_DWORDS
, &texture
);
1189 assert(result
== VK_SUCCESS
);
1191 for (unsigned i
= 0; i
< subpass
->input_count
* 2; i
++) {
1192 uint32_t a
= subpass
->input_attachments
[i
/ 2].attachment
;
1193 if (a
== VK_ATTACHMENT_UNUSED
)
1196 struct tu_image_view
*iview
=
1197 cmd
->state
.framebuffer
->attachments
[a
].attachment
;
1198 const struct tu_render_pass_attachment
*att
=
1199 &cmd
->state
.pass
->attachments
[a
];
1200 uint32_t *dst
= &texture
.map
[A6XX_TEX_CONST_DWORDS
* i
];
1202 memcpy(dst
, iview
->descriptor
, A6XX_TEX_CONST_DWORDS
* 4);
1204 if (i
% 2 == 1 && att
->format
== VK_FORMAT_D24_UNORM_S8_UINT
) {
1205 /* note this works because spec says fb and input attachments
1206 * must use identity swizzle
1208 dst
[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK
|
1209 A6XX_TEX_CONST_0_SWIZ_X__MASK
| A6XX_TEX_CONST_0_SWIZ_Y__MASK
|
1210 A6XX_TEX_CONST_0_SWIZ_Z__MASK
| A6XX_TEX_CONST_0_SWIZ_W__MASK
);
1211 dst
[0] |= A6XX_TEX_CONST_0_FMT(FMT6_S8Z24_UINT
) |
1212 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_Y
) |
1213 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO
) |
1214 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO
) |
1215 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE
);
1221 /* patched for gmem */
1222 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
1223 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
1225 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
1226 A6XX_TEX_CONST_2_PITCH(cmd
->state
.tiling_config
.tile0
.extent
.width
* att
->cpp
);
1228 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ att
->gmem_offset
;
1229 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
1230 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
1235 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 9, &cs
);
1237 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_FRAG
, 3);
1238 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1239 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1240 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
1241 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_TEX
) |
1242 CP_LOAD_STATE6_0_NUM_UNIT(subpass
->input_count
* 2));
1243 tu_cs_emit_qw(&cs
, texture
.iova
);
1245 tu_cs_emit_pkt4(&cs
, REG_A6XX_SP_FS_TEX_CONST_LO
, 2);
1246 tu_cs_emit_qw(&cs
, texture
.iova
);
1248 tu_cs_emit_regs(&cs
, A6XX_SP_FS_TEX_COUNT(subpass
->input_count
* 2));
1250 *ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
1254 tu_set_input_attachments(struct tu_cmd_buffer
*cmd
, const struct tu_subpass
*subpass
)
1256 struct tu_cs
*cs
= &cmd
->draw_cs
;
1258 tu_emit_input_attachments(cmd
, subpass
, &cmd
->state
.ia_gmem_ib
, true);
1259 tu_emit_input_attachments(cmd
, subpass
, &cmd
->state
.ia_sysmem_ib
, false);
1261 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 6);
1262 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
, cmd
->state
.ia_gmem_ib
);
1263 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
, cmd
->state
.ia_sysmem_ib
);
1267 tu_emit_renderpass_begin(struct tu_cmd_buffer
*cmd
,
1268 const VkRenderPassBeginInfo
*info
)
1270 struct tu_cs
*cs
= &cmd
->draw_cs
;
1272 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1274 tu6_emit_blit_scissor(cmd
, cs
, true);
1276 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1277 tu_load_gmem_attachment(cmd
, cs
, i
, false);
1279 tu6_emit_blit_scissor(cmd
, cs
, false);
1281 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1282 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1284 tu_cond_exec_end(cs
);
1286 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1288 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1289 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1291 tu_cond_exec_end(cs
);
1295 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
,
1296 const struct VkRect2D
*renderArea
)
1298 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1300 assert(fb
->width
> 0 && fb
->height
> 0);
1301 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1302 tu6_emit_window_offset(cs
, 0, 0);
1304 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1306 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1308 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1309 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1311 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1312 tu_cs_emit(cs
, 0x0);
1314 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_SYSMEM
);
1316 /* enable stream-out, with sysmem there is only one pass: */
1318 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
1320 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1321 tu_cs_emit(cs
, 0x1);
1323 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1324 tu_cs_emit(cs
, 0x0);
1326 tu_cs_sanity_check(cs
);
1330 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1332 /* Do any resolves of the last subpass. These are handled in the
1333 * tile_store_ib in the gmem path.
1335 tu6_emit_sysmem_resolves(cmd
, cs
, cmd
->state
.subpass
);
1337 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1339 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1340 tu_cs_emit(cs
, 0x0);
1342 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1344 tu_cs_sanity_check(cs
);
1348 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1350 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1352 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1356 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1357 tu_cs_emit(cs
, 0x0);
1359 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_GMEM
);
1361 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1362 if (use_hw_binning(cmd
)) {
1363 /* enable stream-out during binning pass: */
1364 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1366 tu6_emit_bin_size(cs
,
1367 tiling
->tile0
.extent
.width
,
1368 tiling
->tile0
.extent
.height
,
1369 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1371 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1373 tu6_emit_binning_pass(cmd
, cs
);
1375 /* and disable stream-out for draw pass: */
1376 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=true));
1378 tu6_emit_bin_size(cs
,
1379 tiling
->tile0
.extent
.width
,
1380 tiling
->tile0
.extent
.height
,
1381 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1384 A6XX_VFD_MODE_CNTL(0));
1386 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1388 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1390 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1391 tu_cs_emit(cs
, 0x1);
1393 /* no binning pass, so enable stream-out for draw pass:: */
1394 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1396 tu6_emit_bin_size(cs
,
1397 tiling
->tile0
.extent
.width
,
1398 tiling
->tile0
.extent
.height
,
1402 tu_cs_sanity_check(cs
);
1406 tu6_render_tile(struct tu_cmd_buffer
*cmd
,
1408 const struct tu_tile
*tile
)
1410 tu6_emit_tile_select(cmd
, cs
, tile
);
1412 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1414 if (use_hw_binning(cmd
)) {
1415 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1416 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1419 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1421 tu_cs_sanity_check(cs
);
1425 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1427 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1430 A6XX_GRAS_LRZ_CNTL(0));
1432 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1434 tu6_emit_event_write(cmd
, cs
, PC_CCU_RESOLVE_TS
);
1436 tu_cs_sanity_check(cs
);
1440 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1442 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1444 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1446 for (uint32_t y
= 0; y
< tiling
->tile_count
.height
; y
++) {
1447 for (uint32_t x
= 0; x
< tiling
->tile_count
.width
; x
++) {
1448 struct tu_tile tile
;
1449 tu_tiling_config_get_tile(tiling
, cmd
->device
, x
, y
, &tile
);
1450 tu6_render_tile(cmd
, &cmd
->cs
, &tile
);
1454 tu6_tile_render_end(cmd
, &cmd
->cs
);
1458 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1460 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1462 tu6_sysmem_render_begin(cmd
, &cmd
->cs
, &tiling
->render_area
);
1464 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1466 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1470 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1472 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1473 struct tu_cs sub_cs
;
1476 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1477 if (result
!= VK_SUCCESS
) {
1478 cmd
->record_result
= result
;
1482 /* emit to tile-store sub_cs */
1483 tu6_emit_tile_store(cmd
, &sub_cs
);
1485 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1489 tu_cmd_update_tiling_config(struct tu_cmd_buffer
*cmd
,
1490 const VkRect2D
*render_area
)
1492 const struct tu_device
*dev
= cmd
->device
;
1493 struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1495 tiling
->render_area
= *render_area
;
1496 tiling
->force_sysmem
= false;
1498 tu_tiling_config_update_tile_layout(tiling
, dev
, cmd
->state
.pass
);
1499 tu_tiling_config_update_pipe_layout(tiling
, dev
);
1500 tu_tiling_config_update_pipes(tiling
, dev
);
1504 tu_create_cmd_buffer(struct tu_device
*device
,
1505 struct tu_cmd_pool
*pool
,
1506 VkCommandBufferLevel level
,
1507 VkCommandBuffer
*pCommandBuffer
)
1509 struct tu_cmd_buffer
*cmd_buffer
;
1510 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
1511 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1512 if (cmd_buffer
== NULL
)
1513 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1515 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1516 cmd_buffer
->device
= device
;
1517 cmd_buffer
->pool
= pool
;
1518 cmd_buffer
->level
= level
;
1521 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1522 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1525 /* Init the pool_link so we can safely call list_del when we destroy
1526 * the command buffer
1528 list_inithead(&cmd_buffer
->pool_link
);
1529 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1532 tu_bo_list_init(&cmd_buffer
->bo_list
);
1533 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1534 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1535 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1536 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1538 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1540 list_inithead(&cmd_buffer
->upload
.list
);
1542 VkResult result
= tu_bo_init_new(device
, &cmd_buffer
->scratch_bo
, 0x1000);
1543 if (result
!= VK_SUCCESS
)
1544 goto fail_scratch_bo
;
1546 /* TODO: resize on overflow */
1547 cmd_buffer
->vsc_draw_strm_pitch
= device
->vsc_draw_strm_pitch
;
1548 cmd_buffer
->vsc_prim_strm_pitch
= device
->vsc_prim_strm_pitch
;
1549 cmd_buffer
->vsc_draw_strm
= device
->vsc_draw_strm
;
1550 cmd_buffer
->vsc_prim_strm
= device
->vsc_prim_strm
;
1555 list_del(&cmd_buffer
->pool_link
);
1560 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1562 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->scratch_bo
);
1564 list_del(&cmd_buffer
->pool_link
);
1566 tu_cs_finish(&cmd_buffer
->cs
);
1567 tu_cs_finish(&cmd_buffer
->draw_cs
);
1568 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1569 tu_cs_finish(&cmd_buffer
->sub_cs
);
1571 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1572 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
1576 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1578 cmd_buffer
->record_result
= VK_SUCCESS
;
1580 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1581 tu_cs_reset(&cmd_buffer
->cs
);
1582 tu_cs_reset(&cmd_buffer
->draw_cs
);
1583 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1584 tu_cs_reset(&cmd_buffer
->sub_cs
);
1586 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++)
1587 memset(&cmd_buffer
->descriptors
[i
].sets
, 0, sizeof(cmd_buffer
->descriptors
[i
].sets
));
1589 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1591 return cmd_buffer
->record_result
;
1595 tu_AllocateCommandBuffers(VkDevice _device
,
1596 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1597 VkCommandBuffer
*pCommandBuffers
)
1599 TU_FROM_HANDLE(tu_device
, device
, _device
);
1600 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1602 VkResult result
= VK_SUCCESS
;
1605 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1607 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1608 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1609 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1611 list_del(&cmd_buffer
->pool_link
);
1612 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1614 result
= tu_reset_cmd_buffer(cmd_buffer
);
1615 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1616 cmd_buffer
->level
= pAllocateInfo
->level
;
1618 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1620 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1621 &pCommandBuffers
[i
]);
1623 if (result
!= VK_SUCCESS
)
1627 if (result
!= VK_SUCCESS
) {
1628 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1631 /* From the Vulkan 1.0.66 spec:
1633 * "vkAllocateCommandBuffers can be used to create multiple
1634 * command buffers. If the creation of any of those command
1635 * buffers fails, the implementation must destroy all
1636 * successfully created command buffer objects from this
1637 * command, set all entries of the pCommandBuffers array to
1638 * NULL and return the error."
1640 memset(pCommandBuffers
, 0,
1641 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1648 tu_FreeCommandBuffers(VkDevice device
,
1649 VkCommandPool commandPool
,
1650 uint32_t commandBufferCount
,
1651 const VkCommandBuffer
*pCommandBuffers
)
1653 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1654 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1657 if (cmd_buffer
->pool
) {
1658 list_del(&cmd_buffer
->pool_link
);
1659 list_addtail(&cmd_buffer
->pool_link
,
1660 &cmd_buffer
->pool
->free_cmd_buffers
);
1662 tu_cmd_buffer_destroy(cmd_buffer
);
1668 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1669 VkCommandBufferResetFlags flags
)
1671 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1672 return tu_reset_cmd_buffer(cmd_buffer
);
1675 /* Initialize the cache, assuming all necessary flushes have happened but *not*
1679 tu_cache_init(struct tu_cache_state
*cache
)
1681 cache
->flush_bits
= 0;
1682 cache
->pending_flush_bits
= TU_CMD_FLAG_ALL_INVALIDATE
;
1686 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1687 const VkCommandBufferBeginInfo
*pBeginInfo
)
1689 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1690 VkResult result
= VK_SUCCESS
;
1692 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1693 /* If the command buffer has already been resetted with
1694 * vkResetCommandBuffer, no need to do it again.
1696 result
= tu_reset_cmd_buffer(cmd_buffer
);
1697 if (result
!= VK_SUCCESS
)
1701 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1702 tu_cache_init(&cmd_buffer
->state
.cache
);
1703 tu_cache_init(&cmd_buffer
->state
.renderpass_cache
);
1704 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1706 tu_cs_begin(&cmd_buffer
->cs
);
1707 tu_cs_begin(&cmd_buffer
->draw_cs
);
1708 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1710 /* setup initial configuration into command buffer */
1711 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1712 switch (cmd_buffer
->queue_family_index
) {
1713 case TU_QUEUE_GENERAL
:
1714 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1719 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1720 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1721 assert(pBeginInfo
->pInheritanceInfo
);
1722 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1723 cmd_buffer
->state
.subpass
=
1724 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1726 /* When executing in the middle of another command buffer, the CCU
1729 cmd_buffer
->state
.ccu_state
= TU_CMD_CCU_UNKNOWN
;
1733 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1738 /* Sets vertex buffers to HW binding points. We emit VBs in SDS (so that bin
1739 * rendering can skip over unused state), so we need to collect all the
1740 * bindings together into a single state emit at draw time.
1743 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1744 uint32_t firstBinding
,
1745 uint32_t bindingCount
,
1746 const VkBuffer
*pBuffers
,
1747 const VkDeviceSize
*pOffsets
)
1749 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1751 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1753 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1754 struct tu_buffer
*buf
= tu_buffer_from_handle(pBuffers
[i
]);
1756 cmd
->state
.vb
.buffers
[firstBinding
+ i
] = buf
;
1757 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1759 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1762 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1766 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1768 VkDeviceSize offset
,
1769 VkIndexType indexType
)
1771 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1772 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1774 /* initialize/update the restart index */
1775 if (!cmd
->state
.index_buffer
|| cmd
->state
.index_type
!= indexType
) {
1776 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1778 tu6_emit_restart_index(
1779 draw_cs
, indexType
== VK_INDEX_TYPE_UINT32
? 0xffffffff : 0xffff);
1781 tu_cs_sanity_check(draw_cs
);
1785 if (cmd
->state
.index_buffer
!= buf
)
1786 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1788 cmd
->state
.index_buffer
= buf
;
1789 cmd
->state
.index_offset
= offset
;
1790 cmd
->state
.index_type
= indexType
;
1794 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1795 VkPipelineBindPoint pipelineBindPoint
,
1796 VkPipelineLayout _layout
,
1798 uint32_t descriptorSetCount
,
1799 const VkDescriptorSet
*pDescriptorSets
,
1800 uint32_t dynamicOffsetCount
,
1801 const uint32_t *pDynamicOffsets
)
1803 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1804 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1805 unsigned dyn_idx
= 0;
1807 struct tu_descriptor_state
*descriptors_state
=
1808 tu_get_descriptors_state(cmd
, pipelineBindPoint
);
1810 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1811 unsigned idx
= i
+ firstSet
;
1812 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1814 descriptors_state
->sets
[idx
] = set
;
1816 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1817 /* update the contents of the dynamic descriptor set */
1818 unsigned src_idx
= j
;
1819 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1820 assert(dyn_idx
< dynamicOffsetCount
);
1823 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1825 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1826 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1828 /* Patch the storage/uniform descriptors right away. */
1829 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1830 /* Note: we can assume here that the addition won't roll over and
1831 * change the SIZE field.
1833 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1838 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1839 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1840 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1847 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
1848 if (set
->buffers
[j
]) {
1849 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
1850 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1854 if (set
->size
> 0) {
1855 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
1856 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1859 assert(dyn_idx
== dynamicOffsetCount
);
1861 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
, hlsq_update_value
;
1862 uint64_t addr
[MAX_SETS
+ 1] = {};
1865 for (uint32_t i
= 0; i
< MAX_SETS
; i
++) {
1866 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
1868 addr
[i
] = set
->va
| 3;
1871 if (layout
->dynamic_offset_count
) {
1872 /* allocate and fill out dynamic descriptor set */
1873 struct ts_cs_memory dynamic_desc_set
;
1874 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, layout
->dynamic_offset_count
,
1875 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
1876 assert(result
== VK_SUCCESS
);
1878 memcpy(dynamic_desc_set
.map
, descriptors_state
->dynamic_descriptors
,
1879 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
1880 addr
[MAX_SETS
] = dynamic_desc_set
.iova
| 3;
1883 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1884 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
1885 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
1886 hlsq_update_value
= 0x7c000;
1888 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
| TU_CMD_DIRTY_SHADER_CONSTS
;
1890 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1892 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
1893 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
1894 hlsq_update_value
= 0x3e00;
1896 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
;
1899 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 24, &cs
);
1901 tu_cs_emit_pkt4(&cs
, sp_bindless_base_reg
, 10);
1902 tu_cs_emit_array(&cs
, (const uint32_t*) addr
, 10);
1903 tu_cs_emit_pkt4(&cs
, hlsq_bindless_base_reg
, 10);
1904 tu_cs_emit_array(&cs
, (const uint32_t*) addr
, 10);
1905 tu_cs_emit_regs(&cs
, A6XX_HLSQ_UPDATE_CNTL(.dword
= hlsq_update_value
));
1907 struct tu_cs_entry ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
1908 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1909 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
1910 tu_cs_emit_sds_ib(&cmd
->draw_cs
, TU_DRAW_STATE_DESC_SETS
, ib
);
1911 cmd
->state
.desc_sets_ib
= ib
;
1913 /* note: for compute we could emit directly, instead of a CP_INDIRECT
1914 * however, the blob uses draw states for compute
1916 tu_cs_emit_ib(&cmd
->cs
, &ib
);
1920 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
1921 uint32_t firstBinding
,
1922 uint32_t bindingCount
,
1923 const VkBuffer
*pBuffers
,
1924 const VkDeviceSize
*pOffsets
,
1925 const VkDeviceSize
*pSizes
)
1927 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1928 assert(firstBinding
+ bindingCount
<= IR3_MAX_SO_BUFFERS
);
1930 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1931 uint32_t idx
= firstBinding
+ i
;
1932 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
1934 if (pOffsets
[i
] != 0)
1935 cmd
->state
.streamout_reset
|= 1 << idx
;
1937 cmd
->state
.streamout_buf
.buffers
[idx
] = buf
;
1938 cmd
->state
.streamout_buf
.offsets
[idx
] = pOffsets
[i
];
1939 cmd
->state
.streamout_buf
.sizes
[idx
] = pSizes
[i
];
1941 cmd
->state
.streamout_enabled
|= 1 << idx
;
1944 cmd
->state
.dirty
|= TU_CMD_DIRTY_STREAMOUT_BUFFERS
;
1947 void tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1948 uint32_t firstCounterBuffer
,
1949 uint32_t counterBufferCount
,
1950 const VkBuffer
*pCounterBuffers
,
1951 const VkDeviceSize
*pCounterBufferOffsets
)
1953 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1954 /* TODO do something with counter buffer? */
1957 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1958 uint32_t firstCounterBuffer
,
1959 uint32_t counterBufferCount
,
1960 const VkBuffer
*pCounterBuffers
,
1961 const VkDeviceSize
*pCounterBufferOffsets
)
1963 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1964 /* TODO do something with counter buffer? */
1966 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1967 cmd
->state
.streamout_enabled
= 0;
1971 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1972 VkPipelineLayout layout
,
1973 VkShaderStageFlags stageFlags
,
1976 const void *pValues
)
1978 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1979 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1980 cmd
->state
.dirty
|= TU_CMD_DIRTY_SHADER_CONSTS
;
1983 /* Flush everything which has been made available but we haven't actually
1987 tu_flush_all_pending(struct tu_cache_state
*cache
)
1989 cache
->flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
1990 cache
->pending_flush_bits
&= ~TU_CMD_FLAG_ALL_FLUSH
;
1994 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
1996 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1998 /* We currently flush CCU at the end of the command buffer, like
1999 * what the blob does. There's implicit synchronization around every
2000 * vkQueueSubmit, but the kernel only flushes the UCHE, and we don't
2001 * know yet if this command buffer will be the last in the submit so we
2002 * have to defensively flush everything else.
2004 * TODO: We could definitely do better than this, since these flushes
2005 * aren't required by Vulkan, but we'd need kernel support to do that.
2006 * Ideally, we'd like the kernel to flush everything afterwards, so that we
2007 * wouldn't have to do any flushes here, and when submitting multiple
2008 * command buffers there wouldn't be any unnecessary flushes in between.
2010 if (cmd_buffer
->state
.pass
) {
2011 tu_flush_all_pending(&cmd_buffer
->state
.renderpass_cache
);
2012 tu_emit_cache_flush_renderpass(cmd_buffer
, &cmd_buffer
->draw_cs
);
2014 tu_flush_all_pending(&cmd_buffer
->state
.cache
);
2015 cmd_buffer
->state
.cache
.flush_bits
|=
2016 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
2017 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
2018 tu_emit_cache_flush(cmd_buffer
, &cmd_buffer
->cs
);
2021 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->scratch_bo
,
2022 MSM_SUBMIT_BO_WRITE
);
2024 if (cmd_buffer
->use_vsc_data
) {
2025 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_draw_strm
,
2026 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2027 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_prim_strm
,
2028 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2031 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->border_color
,
2032 MSM_SUBMIT_BO_READ
);
2034 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
2035 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
2036 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2039 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
2040 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
2041 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2044 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
2045 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
2046 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2049 tu_cs_end(&cmd_buffer
->cs
);
2050 tu_cs_end(&cmd_buffer
->draw_cs
);
2051 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
2053 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
2055 return cmd_buffer
->record_result
;
2059 tu_cmd_dynamic_state(struct tu_cmd_buffer
*cmd
, uint32_t id
, uint32_t size
)
2061 struct ts_cs_memory memory
;
2064 /* TODO: share this logic with tu_pipeline_static_state */
2065 tu_cs_alloc(&cmd
->sub_cs
, size
, 1, &memory
);
2066 tu_cs_init_external(&cs
, memory
.map
, memory
.map
+ size
);
2068 tu_cs_reserve_space(&cs
, size
);
2070 assert(id
< ARRAY_SIZE(cmd
->state
.dynamic_state
));
2071 cmd
->state
.dynamic_state
[id
].iova
= memory
.iova
;
2072 cmd
->state
.dynamic_state
[id
].size
= size
;
2074 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
2075 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DYNAMIC
+ id
, cmd
->state
.dynamic_state
[id
]);
2081 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
2082 VkPipelineBindPoint pipelineBindPoint
,
2083 VkPipeline _pipeline
)
2085 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2086 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2088 tu_bo_list_add(&cmd
->bo_list
, &pipeline
->program
.binary_bo
,
2089 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2090 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2091 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2092 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2095 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
) {
2096 cmd
->state
.compute_pipeline
= pipeline
;
2097 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
2101 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
);
2103 cmd
->state
.pipeline
= pipeline
;
2104 cmd
->state
.dirty
|= TU_CMD_DIRTY_SHADER_CONSTS
;
2106 struct tu_cs
*cs
= &cmd
->draw_cs
;
2107 uint32_t mask
= ~pipeline
->dynamic_state_mask
& BITFIELD_MASK(TU_DYNAMIC_STATE_COUNT
);
2110 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (7 + util_bitcount(mask
)));
2111 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state_ib
);
2112 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state_ib
);
2113 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state_ib
);
2114 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state_ib
);
2115 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast
.state_ib
);
2116 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DS
, pipeline
->ds
.state_ib
);
2117 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend
.state_ib
);
2119 for_each_bit(i
, mask
)
2120 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
, pipeline
->dynamic_state
[i
]);
2122 /* If the new pipeline requires more VBs than we had previously set up, we
2123 * need to re-emit them in SDS. If it requires the same set or fewer, we
2124 * can just re-use the old SDS.
2126 if (pipeline
->vi
.bindings_used
& ~cmd
->vertex_bindings_set
)
2127 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
2129 /* If the pipeline needs a dynamic descriptor, re-emit descriptor sets */
2130 if (pipeline
->layout
->dynamic_offset_count
)
2131 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
;
2133 /* dynamic linewidth state depends pipeline state's gras_su_cntl
2134 * so the dynamic state ib must be updated when pipeline changes
2136 if (pipeline
->dynamic_state_mask
& BIT(VK_DYNAMIC_STATE_LINE_WIDTH
)) {
2137 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2139 cmd
->state
.dynamic_gras_su_cntl
&= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2140 cmd
->state
.dynamic_gras_su_cntl
|= pipeline
->gras_su_cntl
;
2142 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2147 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2148 uint32_t firstViewport
,
2149 uint32_t viewportCount
,
2150 const VkViewport
*pViewports
)
2152 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2153 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_VIEWPORT
, 18);
2155 assert(firstViewport
== 0 && viewportCount
== 1);
2157 tu6_emit_viewport(&cs
, pViewports
);
2161 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2162 uint32_t firstScissor
,
2163 uint32_t scissorCount
,
2164 const VkRect2D
*pScissors
)
2166 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2167 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_SCISSOR
, 3);
2169 assert(firstScissor
== 0 && scissorCount
== 1);
2171 tu6_emit_scissor(&cs
, pScissors
);
2175 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2177 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2178 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2180 cmd
->state
.dynamic_gras_su_cntl
&= ~A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2181 cmd
->state
.dynamic_gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(lineWidth
/ 2.0f
);
2183 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2187 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2188 float depthBiasConstantFactor
,
2189 float depthBiasClamp
,
2190 float depthBiasSlopeFactor
)
2192 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2193 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BIAS
, 4);
2195 tu6_emit_depth_bias(&cs
, depthBiasConstantFactor
, depthBiasClamp
, depthBiasSlopeFactor
);
2199 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2200 const float blendConstants
[4])
2202 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2203 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_BLEND_CONSTANTS
, 5);
2205 tu_cs_emit_pkt4(&cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2206 tu_cs_emit_array(&cs
, (const uint32_t *) blendConstants
, 4);
2210 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2211 float minDepthBounds
,
2212 float maxDepthBounds
)
2217 update_stencil_mask(uint32_t *value
, VkStencilFaceFlags face
, uint32_t mask
)
2219 if (face
& VK_STENCIL_FACE_FRONT_BIT
)
2220 *value
|= A6XX_RB_STENCILMASK_MASK(mask
);
2221 if (face
& VK_STENCIL_FACE_BACK_BIT
)
2222 *value
|= A6XX_RB_STENCILMASK_BFMASK(mask
);
2226 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2227 VkStencilFaceFlags faceMask
,
2228 uint32_t compareMask
)
2230 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2231 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
, 2);
2233 update_stencil_mask(&cmd
->state
.dynamic_stencil_mask
, faceMask
, compareMask
);
2235 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILMASK(.dword
= cmd
->state
.dynamic_stencil_mask
));
2239 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2240 VkStencilFaceFlags faceMask
,
2243 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2244 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
, 2);
2246 update_stencil_mask(&cmd
->state
.dynamic_stencil_wrmask
, faceMask
, writeMask
);
2248 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILWRMASK(.dword
= cmd
->state
.dynamic_stencil_wrmask
));
2252 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2253 VkStencilFaceFlags faceMask
,
2256 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2257 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_REFERENCE
, 2);
2259 update_stencil_mask(&cmd
->state
.dynamic_stencil_ref
, faceMask
, reference
);
2261 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILREF(.dword
= cmd
->state
.dynamic_stencil_ref
));
2265 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer
,
2266 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
2268 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2269 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
, 9);
2271 assert(pSampleLocationsInfo
);
2273 tu6_emit_sample_locations(&cs
, pSampleLocationsInfo
);
2277 tu_flush_for_access(struct tu_cache_state
*cache
,
2278 enum tu_cmd_access_mask src_mask
,
2279 enum tu_cmd_access_mask dst_mask
)
2281 enum tu_cmd_flush_bits flush_bits
= 0;
2283 if (src_mask
& TU_ACCESS_SYSMEM_WRITE
) {
2284 cache
->pending_flush_bits
|= TU_CMD_FLAG_ALL_INVALIDATE
;
2287 #define SRC_FLUSH(domain, flush, invalidate) \
2288 if (src_mask & TU_ACCESS_##domain##_WRITE) { \
2289 cache->pending_flush_bits |= TU_CMD_FLAG_##flush | \
2290 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2293 SRC_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2294 SRC_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2295 SRC_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2299 #define SRC_INCOHERENT_FLUSH(domain, flush, invalidate) \
2300 if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
2301 flush_bits |= TU_CMD_FLAG_##flush; \
2302 cache->pending_flush_bits |= \
2303 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2306 SRC_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2307 SRC_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2309 #undef SRC_INCOHERENT_FLUSH
2311 if (dst_mask
& (TU_ACCESS_SYSMEM_READ
| TU_ACCESS_SYSMEM_WRITE
)) {
2312 flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
2315 #define DST_FLUSH(domain, flush, invalidate) \
2316 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2317 TU_ACCESS_##domain##_WRITE)) { \
2318 flush_bits |= cache->pending_flush_bits & \
2319 (TU_CMD_FLAG_##invalidate | \
2320 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2323 DST_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2324 DST_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2325 DST_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2329 #define DST_INCOHERENT_FLUSH(domain, flush, invalidate) \
2330 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2331 TU_ACCESS_##domain##_WRITE)) { \
2332 flush_bits |= TU_CMD_FLAG_##invalidate | \
2333 (cache->pending_flush_bits & \
2334 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2337 DST_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2338 DST_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2340 #undef DST_INCOHERENT_FLUSH
2342 if (dst_mask
& TU_ACCESS_WFI_READ
) {
2343 flush_bits
|= TU_CMD_FLAG_WFI
;
2346 cache
->flush_bits
|= flush_bits
;
2347 cache
->pending_flush_bits
&= ~flush_bits
;
2350 static enum tu_cmd_access_mask
2351 vk2tu_access(VkAccessFlags flags
, bool gmem
)
2353 enum tu_cmd_access_mask mask
= 0;
2355 /* If the GPU writes a buffer that is then read by an indirect draw
2356 * command, we theoretically need a WFI + WAIT_FOR_ME combination to
2357 * wait for the writes to complete. The WAIT_FOR_ME is performed as part
2358 * of the draw by the firmware, so we just need to execute a WFI.
2361 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
|
2362 VK_ACCESS_MEMORY_READ_BIT
)) {
2363 mask
|= TU_ACCESS_WFI_READ
;
2367 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
| /* Read performed by CP */
2368 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
| /* Read performed by CP, I think */
2369 VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
| /* Read performed by CP */
2370 VK_ACCESS_HOST_READ_BIT
| /* sysmem by definition */
2371 VK_ACCESS_MEMORY_READ_BIT
)) {
2372 mask
|= TU_ACCESS_SYSMEM_READ
;
2376 (VK_ACCESS_HOST_WRITE_BIT
|
2377 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
| /* Write performed by CP, I think */
2378 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2379 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2383 (VK_ACCESS_INDEX_READ_BIT
| /* Read performed by PC, I think */
2384 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
| /* Read performed by VFD */
2385 VK_ACCESS_UNIFORM_READ_BIT
| /* Read performed by SP */
2386 /* TODO: Is there a no-cache bit for textures so that we can ignore
2389 VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
| /* Read performed by TP */
2390 VK_ACCESS_SHADER_READ_BIT
| /* Read perfomed by SP/TP */
2391 VK_ACCESS_MEMORY_READ_BIT
)) {
2392 mask
|= TU_ACCESS_UCHE_READ
;
2396 (VK_ACCESS_SHADER_WRITE_BIT
| /* Write performed by SP */
2397 VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
| /* Write performed by VPC */
2398 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2399 mask
|= TU_ACCESS_UCHE_WRITE
;
2402 /* When using GMEM, the CCU is always flushed automatically to GMEM, and
2403 * then GMEM is flushed to sysmem. Furthermore, we already had to flush any
2404 * previous writes in sysmem mode when transitioning to GMEM. Therefore we
2405 * can ignore CCU and pretend that color attachments and transfers use
2410 (VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
|
2411 VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT
|
2412 VK_ACCESS_MEMORY_READ_BIT
)) {
2414 mask
|= TU_ACCESS_SYSMEM_READ
;
2416 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_READ
;
2420 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
|
2421 VK_ACCESS_MEMORY_READ_BIT
)) {
2423 mask
|= TU_ACCESS_SYSMEM_READ
;
2425 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
;
2429 (VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
|
2430 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2432 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2434 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2439 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
|
2440 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2442 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2444 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2448 /* When the dst access is a transfer read/write, it seems we sometimes need
2449 * to insert a WFI after any flushes, to guarantee that the flushes finish
2450 * before the 2D engine starts. However the opposite (i.e. a WFI after
2451 * CP_BLIT and before any subsequent flush) does not seem to be needed, and
2452 * the blob doesn't emit such a WFI.
2456 (VK_ACCESS_TRANSFER_WRITE_BIT
|
2457 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2459 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2461 mask
|= TU_ACCESS_CCU_COLOR_WRITE
;
2463 mask
|= TU_ACCESS_WFI_READ
;
2467 (VK_ACCESS_TRANSFER_READ_BIT
| /* Access performed by TP */
2468 VK_ACCESS_MEMORY_READ_BIT
)) {
2469 mask
|= TU_ACCESS_UCHE_READ
| TU_ACCESS_WFI_READ
;
2477 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2478 uint32_t commandBufferCount
,
2479 const VkCommandBuffer
*pCmdBuffers
)
2481 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2484 assert(commandBufferCount
> 0);
2486 /* Emit any pending flushes. */
2487 if (cmd
->state
.pass
) {
2488 tu_flush_all_pending(&cmd
->state
.renderpass_cache
);
2489 tu_emit_cache_flush_renderpass(cmd
, &cmd
->draw_cs
);
2491 tu_flush_all_pending(&cmd
->state
.cache
);
2492 tu_emit_cache_flush(cmd
, &cmd
->cs
);
2495 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2496 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2498 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2499 if (result
!= VK_SUCCESS
) {
2500 cmd
->record_result
= result
;
2504 if (secondary
->usage_flags
&
2505 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2506 assert(tu_cs_is_empty(&secondary
->cs
));
2508 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2509 if (result
!= VK_SUCCESS
) {
2510 cmd
->record_result
= result
;
2514 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2515 &secondary
->draw_epilogue_cs
);
2516 if (result
!= VK_SUCCESS
) {
2517 cmd
->record_result
= result
;
2521 if (secondary
->has_tess
)
2522 cmd
->has_tess
= true;
2524 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2525 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2527 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2528 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2529 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2532 tu_cs_add_entries(&cmd
->cs
, &secondary
->cs
);
2535 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2537 /* After executing secondary command buffers, there may have been arbitrary
2538 * flushes executed, so when we encounter a pipeline barrier with a
2539 * srcMask, we have to assume that we need to invalidate. Therefore we need
2540 * to re-initialize the cache with all pending invalidate bits set.
2542 if (cmd
->state
.pass
) {
2543 tu_cache_init(&cmd
->state
.renderpass_cache
);
2545 tu_cache_init(&cmd
->state
.cache
);
2550 tu_CreateCommandPool(VkDevice _device
,
2551 const VkCommandPoolCreateInfo
*pCreateInfo
,
2552 const VkAllocationCallbacks
*pAllocator
,
2553 VkCommandPool
*pCmdPool
)
2555 TU_FROM_HANDLE(tu_device
, device
, _device
);
2556 struct tu_cmd_pool
*pool
;
2558 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2559 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2561 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2564 pool
->alloc
= *pAllocator
;
2566 pool
->alloc
= device
->alloc
;
2568 list_inithead(&pool
->cmd_buffers
);
2569 list_inithead(&pool
->free_cmd_buffers
);
2571 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2573 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2579 tu_DestroyCommandPool(VkDevice _device
,
2580 VkCommandPool commandPool
,
2581 const VkAllocationCallbacks
*pAllocator
)
2583 TU_FROM_HANDLE(tu_device
, device
, _device
);
2584 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2589 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2590 &pool
->cmd_buffers
, pool_link
)
2592 tu_cmd_buffer_destroy(cmd_buffer
);
2595 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2596 &pool
->free_cmd_buffers
, pool_link
)
2598 tu_cmd_buffer_destroy(cmd_buffer
);
2601 vk_free2(&device
->alloc
, pAllocator
, pool
);
2605 tu_ResetCommandPool(VkDevice device
,
2606 VkCommandPool commandPool
,
2607 VkCommandPoolResetFlags flags
)
2609 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2612 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2615 result
= tu_reset_cmd_buffer(cmd_buffer
);
2616 if (result
!= VK_SUCCESS
)
2624 tu_TrimCommandPool(VkDevice device
,
2625 VkCommandPool commandPool
,
2626 VkCommandPoolTrimFlags flags
)
2628 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2633 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2634 &pool
->free_cmd_buffers
, pool_link
)
2636 tu_cmd_buffer_destroy(cmd_buffer
);
2641 tu_subpass_barrier(struct tu_cmd_buffer
*cmd_buffer
,
2642 const struct tu_subpass_barrier
*barrier
,
2645 /* Note: we don't know until the end of the subpass whether we'll use
2646 * sysmem, so assume sysmem here to be safe.
2648 struct tu_cache_state
*cache
=
2649 external
? &cmd_buffer
->state
.cache
: &cmd_buffer
->state
.renderpass_cache
;
2650 enum tu_cmd_access_mask src_flags
=
2651 vk2tu_access(barrier
->src_access_mask
, false);
2652 enum tu_cmd_access_mask dst_flags
=
2653 vk2tu_access(barrier
->dst_access_mask
, false);
2655 if (barrier
->incoherent_ccu_color
)
2656 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2657 if (barrier
->incoherent_ccu_depth
)
2658 src_flags
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2660 tu_flush_for_access(cache
, src_flags
, dst_flags
);
2664 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2665 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2666 VkSubpassContents contents
)
2668 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2669 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2670 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2672 cmd
->state
.pass
= pass
;
2673 cmd
->state
.subpass
= pass
->subpasses
;
2674 cmd
->state
.framebuffer
= fb
;
2676 tu_cmd_update_tiling_config(cmd
, &pRenderPassBegin
->renderArea
);
2677 tu_cmd_prepare_tile_store_ib(cmd
);
2679 /* Note: because this is external, any flushes will happen before draw_cs
2680 * gets called. However deferred flushes could have to happen later as part
2683 tu_subpass_barrier(cmd
, &pass
->subpasses
[0].start_barrier
, true);
2684 cmd
->state
.renderpass_cache
.pending_flush_bits
=
2685 cmd
->state
.cache
.pending_flush_bits
;
2686 cmd
->state
.renderpass_cache
.flush_bits
= 0;
2688 tu_emit_renderpass_begin(cmd
, pRenderPassBegin
);
2690 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2691 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2692 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2693 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2695 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2697 /* note: use_hw_binning only checks tiling config */
2698 if (use_hw_binning(cmd
))
2699 cmd
->use_vsc_data
= true;
2701 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2702 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2703 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2704 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2707 cmd
->state
.dirty
|= TU_CMD_DIRTY_DRAW_STATE
;
2711 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2712 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2713 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2715 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2716 pSubpassBeginInfo
->contents
);
2720 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2722 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2723 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2724 struct tu_cs
*cs
= &cmd
->draw_cs
;
2726 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2728 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2730 if (subpass
->resolve_attachments
) {
2731 tu6_emit_blit_scissor(cmd
, cs
, true);
2733 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2734 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2735 if (a
== VK_ATTACHMENT_UNUSED
)
2738 tu_store_gmem_attachment(cmd
, cs
, a
,
2739 subpass
->color_attachments
[i
].attachment
);
2741 if (pass
->attachments
[a
].gmem_offset
< 0)
2745 * check if the resolved attachment is needed by later subpasses,
2746 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2748 tu_finishme("missing GMEM->GMEM resolve path\n");
2749 tu_load_gmem_attachment(cmd
, cs
, a
, true);
2753 tu_cond_exec_end(cs
);
2755 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2757 tu6_emit_sysmem_resolves(cmd
, cs
, subpass
);
2759 tu_cond_exec_end(cs
);
2761 /* Handle dependencies for the next subpass */
2762 tu_subpass_barrier(cmd
, &cmd
->state
.subpass
->start_barrier
, false);
2764 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2765 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2766 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2767 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2768 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2770 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2774 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2775 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2776 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2778 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2784 * Number of vertices.
2789 * Index of the first vertex.
2791 int32_t vertex_offset
;
2794 * First instance id.
2796 uint32_t first_instance
;
2799 * Number of instances.
2801 uint32_t instance_count
;
2804 * First index (indexed draws only).
2806 uint32_t first_index
;
2809 * Whether it's an indexed draw.
2814 * Indirect draw parameters resource.
2816 struct tu_buffer
*indirect
;
2817 uint64_t indirect_offset
;
2821 * Draw count parameters resource.
2823 struct tu_buffer
*count_buffer
;
2824 uint64_t count_buffer_offset
;
2827 * Stream output parameters resource.
2829 struct tu_buffer
*streamout_buffer
;
2830 uint64_t streamout_buffer_offset
;
2834 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2835 struct tu_descriptor_state
*descriptors_state
,
2836 gl_shader_stage type
,
2837 uint32_t *push_constants
)
2839 const struct tu_program_descriptor_linkage
*link
=
2840 &pipeline
->program
.link
[type
];
2841 const struct ir3_ubo_analysis_state
*state
= &link
->const_state
.ubo_state
;
2843 if (link
->push_consts
.count
> 0) {
2844 unsigned num_units
= link
->push_consts
.count
;
2845 unsigned offset
= link
->push_consts
.lo
;
2846 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2847 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2848 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2849 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2850 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2851 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2854 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2855 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2858 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2859 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2860 uint32_t offset
= state
->range
[i
].start
;
2862 /* and even if the start of the const buffer is before
2863 * first_immediate, the end may not be:
2865 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2870 /* things should be aligned to vec4: */
2871 debug_assert((state
->range
[i
].offset
% 16) == 0);
2872 debug_assert((size
% 16) == 0);
2873 debug_assert((offset
% 16) == 0);
2875 /* Dig out the descriptor from the descriptor state and read the VA from
2878 assert(state
->range
[i
].ubo
.bindless
);
2879 uint32_t *base
= state
->range
[i
].ubo
.bindless_base
== MAX_SETS
?
2880 descriptors_state
->dynamic_descriptors
:
2881 descriptors_state
->sets
[state
->range
[i
].ubo
.bindless_base
]->mapped_ptr
;
2882 unsigned block
= state
->range
[i
].ubo
.block
;
2883 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2884 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2887 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2888 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2889 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2890 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2891 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2892 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2893 tu_cs_emit_qw(cs
, va
+ offset
);
2897 static struct tu_cs_entry
2898 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2899 const struct tu_pipeline
*pipeline
,
2900 struct tu_descriptor_state
*descriptors_state
,
2901 gl_shader_stage type
)
2904 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2906 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2908 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2912 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
2913 const struct tu_draw_info
*draw
,
2914 struct tu_cs_entry
*entry
)
2916 /* TODO: fill out more than just base instance */
2917 const struct tu_program_descriptor_linkage
*link
=
2918 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
2919 const struct ir3_const_state
*const_state
= &link
->const_state
;
2922 if (const_state
->offsets
.driver_param
>= link
->constlen
) {
2923 *entry
= (struct tu_cs_entry
) {};
2927 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 8, &cs
);
2928 if (result
!= VK_SUCCESS
)
2931 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2932 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(const_state
->offsets
.driver_param
) |
2933 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2934 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2935 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
2936 CP_LOAD_STATE6_0_NUM_UNIT(1));
2940 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
2944 tu_cs_emit(&cs
, draw
->first_instance
);
2947 *entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2951 static struct tu_cs_entry
2952 tu6_emit_vertex_buffers(struct tu_cmd_buffer
*cmd
,
2953 const struct tu_pipeline
*pipeline
)
2956 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 4 * MAX_VBS
, &cs
);
2959 for_each_bit(binding
, pipeline
->vi
.bindings_used
) {
2960 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2961 const VkDeviceSize offset
= buf
->bo_offset
+
2962 cmd
->state
.vb
.offsets
[binding
];
2964 tu_cs_emit_regs(&cs
,
2965 A6XX_VFD_FETCH_BASE(binding
, .bo
= buf
->bo
, .bo_offset
= offset
),
2966 A6XX_VFD_FETCH_SIZE(binding
, buf
->size
- offset
));
2970 cmd
->vertex_bindings_set
= pipeline
->vi
.bindings_used
;
2972 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2976 tu6_emit_streamout(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
2978 struct tu_streamout_state
*tf
= &cmd
->state
.pipeline
->streamout
;
2980 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2981 struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
2986 offset
= cmd
->state
.streamout_buf
.offsets
[i
];
2988 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_BASE(i
, .bo
= buf
->bo
,
2989 .bo_offset
= buf
->bo_offset
));
2990 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_SIZE(i
, buf
->size
));
2992 if (cmd
->state
.streamout_reset
& (1 << i
)) {
2993 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, offset
));
2994 cmd
->state
.streamout_reset
&= ~(1 << i
);
2996 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
2997 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i
)) |
2998 CP_MEM_TO_REG_0_SHIFT_BY_2
| CP_MEM_TO_REG_0_UNK31
|
2999 CP_MEM_TO_REG_0_CNT(0));
3000 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+
3001 ctrl_offset(flush_base
[i
].offset
));
3004 tu_cs_emit_regs(cs
, A6XX_VPC_SO_FLUSH_BASE(i
, .bo
= &cmd
->scratch_bo
,
3006 ctrl_offset(flush_base
[i
])));
3009 if (cmd
->state
.streamout_enabled
) {
3010 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * tf
->prog_count
));
3011 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
3012 tu_cs_emit(cs
, tf
->vpc_so_buf_cntl
);
3013 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(0));
3014 tu_cs_emit(cs
, tf
->ncomp
[0]);
3015 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(1));
3016 tu_cs_emit(cs
, tf
->ncomp
[1]);
3017 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(2));
3018 tu_cs_emit(cs
, tf
->ncomp
[2]);
3019 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(3));
3020 tu_cs_emit(cs
, tf
->ncomp
[3]);
3021 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
3022 tu_cs_emit(cs
, A6XX_VPC_SO_CNTL_ENABLE
);
3023 for (unsigned i
= 0; i
< tf
->prog_count
; i
++) {
3024 tu_cs_emit(cs
, REG_A6XX_VPC_SO_PROG
);
3025 tu_cs_emit(cs
, tf
->prog
[i
]);
3028 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
3029 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
3031 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
3037 get_tess_param_bo_size(const struct tu_pipeline
*pipeline
,
3038 const struct tu_draw_info
*draw_info
)
3040 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
3041 * Still not sure what to do here, so just allocate a reasonably large
3042 * BO and hope for the best for now.
3043 * (maxTessellationControlPerVertexOutputComponents * 2048 vertices +
3044 * maxTessellationControlPerPatchOutputComponents * 512 patches) */
3045 if (draw_info
->indirect
) {
3046 return ((128 * 2048) + (128 * 512)) * 4;
3049 /* For each patch, adreno lays out the tess param BO in memory as:
3050 * (v_input[0][0])...(v_input[i][j])(p_input[0])...(p_input[k]).
3051 * where i = # vertices per patch, j = # per-vertex outputs, and
3052 * k = # per-patch outputs.*/
3053 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
3054 uint32_t num_patches
= draw_info
->count
/ verts_per_patch
;
3055 return draw_info
->count
* pipeline
->tess
.per_vertex_output_size
+
3056 pipeline
->tess
.per_patch_output_size
* num_patches
;
3060 get_tess_factor_bo_size(const struct tu_pipeline
*pipeline
,
3061 const struct tu_draw_info
*draw_info
)
3063 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
3064 * Still not sure what to do here, so just allocate a reasonably large
3065 * BO and hope for the best for now.
3066 * (quad factor stride * 512 patches) */
3067 if (draw_info
->indirect
) {
3068 return (28 * 512) * 4;
3071 /* Each distinct patch gets its own tess factor output. */
3072 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
3073 uint32_t num_patches
= draw_info
->count
/ verts_per_patch
;
3074 uint32_t factor_stride
;
3075 switch (pipeline
->tess
.patch_type
) {
3076 case IR3_TESS_ISOLINES
:
3079 case IR3_TESS_TRIANGLES
:
3082 case IR3_TESS_QUADS
:
3086 unreachable("bad tessmode");
3088 return factor_stride
* num_patches
;
3092 tu6_emit_tess_consts(struct tu_cmd_buffer
*cmd
,
3093 const struct tu_draw_info
*draw
,
3094 const struct tu_pipeline
*pipeline
,
3095 struct tu_cs_entry
*entry
)
3098 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 20, &cs
);
3099 if (result
!= VK_SUCCESS
)
3102 uint64_t tess_factor_size
= get_tess_factor_bo_size(pipeline
, draw
);
3103 uint64_t tess_param_size
= get_tess_param_bo_size(pipeline
, draw
);
3104 uint64_t tess_bo_size
= tess_factor_size
+ tess_param_size
;
3105 if (tess_bo_size
> 0) {
3106 struct tu_bo
*tess_bo
;
3107 result
= tu_get_scratch_bo(cmd
->device
, tess_bo_size
, &tess_bo
);
3108 if (result
!= VK_SUCCESS
)
3111 tu_bo_list_add(&cmd
->bo_list
, tess_bo
,
3112 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3113 uint64_t tess_factor_iova
= tess_bo
->iova
;
3114 uint64_t tess_param_iova
= tess_factor_iova
+ tess_factor_size
;
3116 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
3117 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.hs_bo_regid
) |
3118 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3119 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3120 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_HS_SHADER
) |
3121 CP_LOAD_STATE6_0_NUM_UNIT(1));
3122 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
3123 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
3124 tu_cs_emit_qw(&cs
, tess_param_iova
);
3125 tu_cs_emit_qw(&cs
, tess_factor_iova
);
3127 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
3128 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.ds_bo_regid
) |
3129 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3130 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3131 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_DS_SHADER
) |
3132 CP_LOAD_STATE6_0_NUM_UNIT(1));
3133 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
3134 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
3135 tu_cs_emit_qw(&cs
, tess_param_iova
);
3136 tu_cs_emit_qw(&cs
, tess_factor_iova
);
3138 tu_cs_emit_pkt4(&cs
, REG_A6XX_PC_TESSFACTOR_ADDR_LO
, 2);
3139 tu_cs_emit_qw(&cs
, tess_factor_iova
);
3141 /* TODO: Without this WFI here, the hardware seems unable to read these
3142 * addresses we just emitted. Freedreno emits these consts as part of
3143 * IB1 instead of in a draw state which might make this WFI unnecessary,
3144 * but it requires a bit more indirection (SS6_INDIRECT for consts). */
3145 tu_cs_emit_wfi(&cs
);
3147 *entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
3152 tu6_bind_draw_states(struct tu_cmd_buffer
*cmd
,
3154 const struct tu_draw_info
*draw
)
3156 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3159 struct tu_descriptor_state
*descriptors_state
=
3160 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
3164 tu_cs_emit_regs(cs
, A6XX_PC_PRIMITIVE_CNTL_0(
3165 .primitive_restart
=
3166 pipeline
->ia
.primitive_restart
&& draw
->indexed
,
3167 .tess_upper_left_domain_origin
=
3168 pipeline
->tess
.upper_left_domain_origin
));
3170 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
3171 cmd
->state
.shader_const_ib
[MESA_SHADER_VERTEX
] =
3172 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
);
3173 cmd
->state
.shader_const_ib
[MESA_SHADER_TESS_CTRL
] =
3174 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_CTRL
);
3175 cmd
->state
.shader_const_ib
[MESA_SHADER_TESS_EVAL
] =
3176 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_EVAL
);
3177 cmd
->state
.shader_const_ib
[MESA_SHADER_GEOMETRY
] =
3178 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_GEOMETRY
);
3179 cmd
->state
.shader_const_ib
[MESA_SHADER_FRAGMENT
] =
3180 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
);
3183 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
)
3184 tu6_emit_streamout(cmd
, cs
);
3186 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) {
3187 /* We need to reload the descriptors every time the descriptor sets
3188 * change. However, the commands we send only depend on the pipeline
3189 * because the whole point is to cache descriptors which are used by the
3190 * pipeline. There's a problem here, in that the firmware has an
3191 * "optimization" which skips executing groups that are set to the same
3192 * value as the last draw. This means that if the descriptor sets change
3193 * but not the pipeline, we'd try to re-execute the same buffer which
3194 * the firmware would ignore and we wouldn't pre-load the new
3195 * descriptors. The blob seems to re-emit the LOAD_STATE group whenever
3196 * the descriptor sets change, which we emulate here by copying the
3197 * pre-prepared buffer.
3199 const struct tu_cs_entry
*load_entry
= &pipeline
->load_state
.state_ib
;
3200 if (load_entry
->size
> 0) {
3201 struct tu_cs load_cs
;
3202 result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, load_entry
->size
, &load_cs
);
3203 if (result
!= VK_SUCCESS
)
3205 tu_cs_emit_array(&load_cs
,
3206 (uint32_t *)((char *)load_entry
->bo
->map
+ load_entry
->offset
),
3207 load_entry
->size
/ 4);
3208 cmd
->state
.desc_sets_load_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &load_cs
);
3210 cmd
->state
.desc_sets_load_ib
.size
= 0;
3214 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3215 cmd
->state
.vertex_buffers_ib
= tu6_emit_vertex_buffers(cmd
, pipeline
);
3217 struct tu_cs_entry vs_params
;
3218 result
= tu6_emit_vs_params(cmd
, draw
, &vs_params
);
3219 if (result
!= VK_SUCCESS
)
3223 pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
3224 struct tu_cs_entry tess_consts
= {};
3226 cmd
->has_tess
= true;
3227 result
= tu6_emit_tess_consts(cmd
, draw
, pipeline
, &tess_consts
);
3228 if (result
!= VK_SUCCESS
)
3232 /* for the first draw in a renderpass, re-emit all the draw states
3234 * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
3235 * used, then draw states must be re-emitted. note however this only happens
3236 * in the sysmem path, so this can be skipped this for the gmem path (TODO)
3238 * the two input attachment states are excluded because secondary command
3239 * buffer doesn't have a state ib to restore it, and not re-emitting them
3240 * is OK since CmdClearAttachments won't disable/overwrite them
3242 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DRAW_STATE
) {
3243 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (TU_DRAW_STATE_COUNT
- 2));
3245 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state_ib
);
3246 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state_ib
);
3247 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
3248 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state_ib
);
3249 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state_ib
);
3250 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast
.state_ib
);
3251 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DS
, pipeline
->ds
.state_ib
);
3252 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend
.state_ib
);
3253 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_VERTEX
]);
3254 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_TESS_CTRL
]);
3255 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_TESS_EVAL
]);
3256 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_GEOMETRY
]);
3257 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_FRAGMENT
]);
3258 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets_ib
);
3259 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, cmd
->state
.desc_sets_load_ib
);
3260 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers_ib
);
3261 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VS_PARAMS
, vs_params
);
3263 for (uint32_t i
= 0; i
< ARRAY_SIZE(cmd
->state
.dynamic_state
); i
++) {
3264 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
,
3265 ((pipeline
->dynamic_state_mask
& BIT(i
)) ?
3266 cmd
->state
.dynamic_state
[i
] :
3267 pipeline
->dynamic_state
[i
]));
3271 /* emit draw states that were just updated
3272 * note we eventually don't want to have to emit anything here
3274 uint32_t draw_state_count
=
3276 ((cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) ? 5 : 0) +
3277 ((cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) ? 1 : 0) +
3278 ((cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) ? 1 : 0) +
3281 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_count
);
3283 /* We may need to re-emit tess consts if the current draw call is
3284 * sufficiently larger than the last draw call. */
3286 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
3287 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
3288 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_VERTEX
]);
3289 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_TESS_CTRL
]);
3290 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_TESS_EVAL
]);
3291 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_GEOMETRY
]);
3292 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_FRAGMENT
]);
3294 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
)
3295 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, cmd
->state
.desc_sets_load_ib
);
3296 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3297 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers_ib
);
3298 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VS_PARAMS
, vs_params
);
3301 tu_cs_sanity_check(cs
);
3304 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
) {
3305 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3306 const struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
3308 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
,
3309 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3314 /* There are too many graphics dirty bits to list here, so just list the
3315 * bits to preserve instead. The only things not emitted here are
3316 * compute-related state.
3318 cmd
->state
.dirty
&= (TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
| TU_CMD_DIRTY_COMPUTE_PIPELINE
);
3323 compute_tess_draw0(struct tu_pipeline
*pipeline
)
3325 uint32_t patch_type
= pipeline
->tess
.patch_type
;
3326 uint32_t tess_draw0
= 0;
3327 switch (patch_type
) {
3328 case IR3_TESS_TRIANGLES
:
3329 tess_draw0
= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_TRIANGLES
);
3331 case IR3_TESS_ISOLINES
:
3332 tess_draw0
= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_ISOLINES
);
3335 case IR3_TESS_QUADS
:
3336 tess_draw0
= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS
);
3339 unreachable("invalid tess patch type");
3341 if (patch_type
!= IR3_TESS_NONE
)
3342 tess_draw0
|= CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3347 tu6_emit_draw_indirect(struct tu_cmd_buffer
*cmd
,
3349 const struct tu_draw_info
*draw
)
3351 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3352 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3353 VK_SHADER_STAGE_GEOMETRY_BIT
;
3356 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3357 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3359 uint32_t tess_draw0
= compute_tess_draw0(cmd
->state
.pipeline
);
3360 if (draw
->indexed
) {
3361 const enum a4xx_index_size index_size
=
3362 tu6_index_size(cmd
->state
.index_type
);
3363 const uint32_t index_bytes
=
3364 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3365 const struct tu_buffer
*index_buf
= cmd
->state
.index_buffer
;
3366 unsigned max_indicies
=
3367 (index_buf
->size
- cmd
->state
.index_offset
) / index_bytes
;
3369 const uint32_t cp_draw_indx
=
3370 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3371 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3372 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3373 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3375 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
);
3377 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_INDIRECT
, 6);
3378 tu_cs_emit(cs
, cp_draw_indx
);
3379 tu_cs_emit_qw(cs
, index_buf
->bo
->iova
+ cmd
->state
.index_offset
);
3380 tu_cs_emit(cs
, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies
));
3381 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3383 const uint32_t cp_draw_indx
=
3384 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3385 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3386 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3388 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
);
3390 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT
, 3);
3391 tu_cs_emit(cs
, cp_draw_indx
);
3392 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3395 tu_bo_list_add(&cmd
->bo_list
, draw
->indirect
->bo
, MSM_SUBMIT_BO_READ
);
3399 tu6_emit_draw_direct(struct tu_cmd_buffer
*cmd
,
3401 const struct tu_draw_info
*draw
)
3404 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3405 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3406 VK_SHADER_STAGE_GEOMETRY_BIT
;
3409 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3410 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3412 uint32_t tess_draw0
= compute_tess_draw0(cmd
->state
.pipeline
);
3413 /* TODO hw binning */
3414 if (draw
->indexed
) {
3415 const enum a4xx_index_size index_size
=
3416 tu6_index_size(cmd
->state
.index_type
);
3417 const uint32_t index_bytes
=
3418 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3419 const struct tu_buffer
*buf
= cmd
->state
.index_buffer
;
3420 const VkDeviceSize offset
= buf
->bo_offset
+ cmd
->state
.index_offset
+
3421 index_bytes
* draw
->first_index
;
3422 const uint32_t size
= index_bytes
* draw
->count
;
3424 const uint32_t cp_draw_indx
=
3425 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3426 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3427 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3428 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3430 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
);
3432 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3433 tu_cs_emit(cs
, cp_draw_indx
);
3434 tu_cs_emit(cs
, draw
->instance_count
);
3435 tu_cs_emit(cs
, draw
->count
);
3436 tu_cs_emit(cs
, 0x0); /* XXX */
3437 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ offset
);
3438 tu_cs_emit(cs
, size
);
3440 const uint32_t cp_draw_indx
=
3441 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3442 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3443 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3445 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
);
3447 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3448 tu_cs_emit(cs
, cp_draw_indx
);
3449 tu_cs_emit(cs
, draw
->instance_count
);
3450 tu_cs_emit(cs
, draw
->count
);
3455 tu_draw(struct tu_cmd_buffer
*cmd
, const struct tu_draw_info
*draw
)
3457 struct tu_cs
*cs
= &cmd
->draw_cs
;
3460 tu_emit_cache_flush_renderpass(cmd
, cs
);
3462 result
= tu6_bind_draw_states(cmd
, cs
, draw
);
3463 if (result
!= VK_SUCCESS
) {
3464 cmd
->record_result
= result
;
3469 tu6_emit_draw_indirect(cmd
, cs
, draw
);
3471 tu6_emit_draw_direct(cmd
, cs
, draw
);
3473 if (cmd
->state
.streamout_enabled
) {
3474 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3475 if (cmd
->state
.streamout_enabled
& (1 << i
))
3476 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
);
3480 tu_cs_sanity_check(cs
);
3484 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3485 uint32_t vertexCount
,
3486 uint32_t instanceCount
,
3487 uint32_t firstVertex
,
3488 uint32_t firstInstance
)
3490 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3491 struct tu_draw_info info
= {};
3493 info
.count
= vertexCount
;
3494 info
.instance_count
= instanceCount
;
3495 info
.first_instance
= firstInstance
;
3496 info
.vertex_offset
= firstVertex
;
3498 tu_draw(cmd_buffer
, &info
);
3502 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3503 uint32_t indexCount
,
3504 uint32_t instanceCount
,
3505 uint32_t firstIndex
,
3506 int32_t vertexOffset
,
3507 uint32_t firstInstance
)
3509 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3510 struct tu_draw_info info
= {};
3512 info
.indexed
= true;
3513 info
.count
= indexCount
;
3514 info
.instance_count
= instanceCount
;
3515 info
.first_index
= firstIndex
;
3516 info
.vertex_offset
= vertexOffset
;
3517 info
.first_instance
= firstInstance
;
3519 tu_draw(cmd_buffer
, &info
);
3523 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3525 VkDeviceSize offset
,
3529 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3530 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3531 struct tu_draw_info info
= {};
3533 info
.count
= drawCount
;
3534 info
.indirect
= buffer
;
3535 info
.indirect_offset
= offset
;
3536 info
.stride
= stride
;
3538 tu_draw(cmd_buffer
, &info
);
3542 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3544 VkDeviceSize offset
,
3548 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3549 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3550 struct tu_draw_info info
= {};
3552 info
.indexed
= true;
3553 info
.count
= drawCount
;
3554 info
.indirect
= buffer
;
3555 info
.indirect_offset
= offset
;
3556 info
.stride
= stride
;
3558 tu_draw(cmd_buffer
, &info
);
3561 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3562 uint32_t instanceCount
,
3563 uint32_t firstInstance
,
3564 VkBuffer _counterBuffer
,
3565 VkDeviceSize counterBufferOffset
,
3566 uint32_t counterOffset
,
3567 uint32_t vertexStride
)
3569 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3570 TU_FROM_HANDLE(tu_buffer
, buffer
, _counterBuffer
);
3572 struct tu_draw_info info
= {};
3574 info
.instance_count
= instanceCount
;
3575 info
.first_instance
= firstInstance
;
3576 info
.streamout_buffer
= buffer
;
3577 info
.streamout_buffer_offset
= counterBufferOffset
;
3578 info
.stride
= vertexStride
;
3580 tu_draw(cmd_buffer
, &info
);
3583 struct tu_dispatch_info
3586 * Determine the layout of the grid (in block units) to be used.
3591 * A starting offset for the grid. If unaligned is set, the offset
3592 * must still be aligned.
3594 uint32_t offsets
[3];
3596 * Whether it's an unaligned compute dispatch.
3601 * Indirect compute parameters resource.
3603 struct tu_buffer
*indirect
;
3604 uint64_t indirect_offset
;
3608 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3609 const struct tu_dispatch_info
*info
)
3611 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3612 const struct tu_program_descriptor_linkage
*link
=
3613 &pipeline
->program
.link
[type
];
3614 const struct ir3_const_state
*const_state
= &link
->const_state
;
3615 uint32_t offset
= const_state
->offsets
.driver_param
;
3617 if (link
->constlen
<= offset
)
3620 if (!info
->indirect
) {
3621 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3622 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3623 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3624 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3625 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3626 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3627 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3630 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3631 (link
->constlen
- offset
) * 4);
3632 /* push constants */
3633 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3634 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3635 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3636 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3637 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3638 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3642 for (i
= 0; i
< num_consts
; i
++)
3643 tu_cs_emit(cs
, driver_params
[i
]);
3645 tu_finishme("Indirect driver params");
3650 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3651 const struct tu_dispatch_info
*info
)
3653 struct tu_cs
*cs
= &cmd
->cs
;
3654 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3655 struct tu_descriptor_state
*descriptors_state
=
3656 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3658 /* TODO: We could probably flush less if we add a compute_flush_bits
3661 tu_emit_cache_flush(cmd
, cs
);
3663 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_PIPELINE
)
3664 tu_cs_emit_ib(cs
, &pipeline
->program
.state_ib
);
3666 struct tu_cs_entry ib
;
3668 ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
);
3670 tu_cs_emit_ib(cs
, &ib
);
3672 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3674 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
) &&
3675 pipeline
->load_state
.state_ib
.size
> 0) {
3676 tu_cs_emit_ib(cs
, &pipeline
->load_state
.state_ib
);
3680 ~(TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
| TU_CMD_DIRTY_COMPUTE_PIPELINE
);
3682 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3683 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3685 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3686 const uint32_t *num_groups
= info
->blocks
;
3688 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3689 .localsizex
= local_size
[0] - 1,
3690 .localsizey
= local_size
[1] - 1,
3691 .localsizez
= local_size
[2] - 1),
3692 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3693 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3694 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3695 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3696 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3697 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3700 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3701 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3702 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3704 if (info
->indirect
) {
3705 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3707 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3708 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3710 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3711 tu_cs_emit(cs
, 0x00000000);
3712 tu_cs_emit_qw(cs
, iova
);
3714 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3715 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3716 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3718 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3719 tu_cs_emit(cs
, 0x00000000);
3720 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3721 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3722 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3729 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3737 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3738 struct tu_dispatch_info info
= {};
3744 info
.offsets
[0] = base_x
;
3745 info
.offsets
[1] = base_y
;
3746 info
.offsets
[2] = base_z
;
3747 tu_dispatch(cmd_buffer
, &info
);
3751 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3756 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3760 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3762 VkDeviceSize offset
)
3764 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3765 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3766 struct tu_dispatch_info info
= {};
3768 info
.indirect
= buffer
;
3769 info
.indirect_offset
= offset
;
3771 tu_dispatch(cmd_buffer
, &info
);
3775 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3777 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3779 tu_cs_end(&cmd_buffer
->draw_cs
);
3780 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3782 if (use_sysmem_rendering(cmd_buffer
))
3783 tu_cmd_render_sysmem(cmd_buffer
);
3785 tu_cmd_render_tiles(cmd_buffer
);
3787 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3789 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3790 tu_cs_begin(&cmd_buffer
->draw_cs
);
3791 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3792 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3794 cmd_buffer
->state
.cache
.pending_flush_bits
|=
3795 cmd_buffer
->state
.renderpass_cache
.pending_flush_bits
;
3796 tu_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
, true);
3798 cmd_buffer
->state
.pass
= NULL
;
3799 cmd_buffer
->state
.subpass
= NULL
;
3800 cmd_buffer
->state
.framebuffer
= NULL
;
3804 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3805 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3807 tu_CmdEndRenderPass(commandBuffer
);
3810 struct tu_barrier_info
3812 uint32_t eventCount
;
3813 const VkEvent
*pEvents
;
3814 VkPipelineStageFlags srcStageMask
;
3818 tu_barrier(struct tu_cmd_buffer
*cmd
,
3819 uint32_t memoryBarrierCount
,
3820 const VkMemoryBarrier
*pMemoryBarriers
,
3821 uint32_t bufferMemoryBarrierCount
,
3822 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3823 uint32_t imageMemoryBarrierCount
,
3824 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3825 const struct tu_barrier_info
*info
)
3827 struct tu_cs
*cs
= cmd
->state
.pass
? &cmd
->draw_cs
: &cmd
->cs
;
3828 VkAccessFlags srcAccessMask
= 0;
3829 VkAccessFlags dstAccessMask
= 0;
3831 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3832 srcAccessMask
|= pMemoryBarriers
[i
].srcAccessMask
;
3833 dstAccessMask
|= pMemoryBarriers
[i
].dstAccessMask
;
3836 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3837 srcAccessMask
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
3838 dstAccessMask
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
3841 enum tu_cmd_access_mask src_flags
= 0;
3842 enum tu_cmd_access_mask dst_flags
= 0;
3844 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3845 TU_FROM_HANDLE(tu_image
, image
, pImageMemoryBarriers
[i
].image
);
3846 VkImageLayout old_layout
= pImageMemoryBarriers
[i
].oldLayout
;
3847 /* For non-linear images, PREINITIALIZED is the same as UNDEFINED */
3848 if (old_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
3849 (image
->tiling
!= VK_IMAGE_TILING_LINEAR
&&
3850 old_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
)) {
3851 /* The underlying memory for this image may have been used earlier
3852 * within the same queue submission for a different image, which
3853 * means that there may be old, stale cache entries which are in the
3854 * "wrong" location, which could cause problems later after writing
3855 * to the image. We don't want these entries being flushed later and
3856 * overwriting the actual image, so we need to flush the CCU.
3858 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
3860 srcAccessMask
|= pImageMemoryBarriers
[i
].srcAccessMask
;
3861 dstAccessMask
|= pImageMemoryBarriers
[i
].dstAccessMask
;
3864 /* Inside a renderpass, we don't know yet whether we'll be using sysmem
3865 * so we have to use the sysmem flushes.
3867 bool gmem
= cmd
->state
.ccu_state
== TU_CMD_CCU_GMEM
&&
3869 src_flags
|= vk2tu_access(srcAccessMask
, gmem
);
3870 dst_flags
|= vk2tu_access(dstAccessMask
, gmem
);
3872 struct tu_cache_state
*cache
=
3873 cmd
->state
.pass
? &cmd
->state
.renderpass_cache
: &cmd
->state
.cache
;
3874 tu_flush_for_access(cache
, src_flags
, dst_flags
);
3876 for (uint32_t i
= 0; i
< info
->eventCount
; i
++) {
3877 TU_FROM_HANDLE(tu_event
, event
, info
->pEvents
[i
]);
3879 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3881 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3882 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3883 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3884 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3885 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3886 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3887 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3892 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3893 VkPipelineStageFlags srcStageMask
,
3894 VkPipelineStageFlags dstStageMask
,
3895 VkDependencyFlags dependencyFlags
,
3896 uint32_t memoryBarrierCount
,
3897 const VkMemoryBarrier
*pMemoryBarriers
,
3898 uint32_t bufferMemoryBarrierCount
,
3899 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3900 uint32_t imageMemoryBarrierCount
,
3901 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3903 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3904 struct tu_barrier_info info
;
3906 info
.eventCount
= 0;
3907 info
.pEvents
= NULL
;
3908 info
.srcStageMask
= srcStageMask
;
3910 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3911 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3912 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3916 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
,
3917 VkPipelineStageFlags stageMask
, unsigned value
)
3919 struct tu_cs
*cs
= &cmd
->cs
;
3921 /* vkCmdSetEvent/vkCmdResetEvent cannot be called inside a render pass */
3922 assert(!cmd
->state
.pass
);
3924 tu_emit_cache_flush(cmd
, cs
);
3926 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3928 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
3929 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
3931 VkPipelineStageFlags top_of_pipe_flags
=
3932 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
3933 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
;
3935 if (!(stageMask
& ~top_of_pipe_flags
)) {
3936 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3937 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3938 tu_cs_emit(cs
, value
);
3940 /* Use a RB_DONE_TS event to wait for everything to complete. */
3941 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 4);
3942 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS
));
3943 tu_cs_emit_qw(cs
, event
->bo
.iova
);
3944 tu_cs_emit(cs
, value
);
3949 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3951 VkPipelineStageFlags stageMask
)
3953 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3954 TU_FROM_HANDLE(tu_event
, event
, _event
);
3956 write_event(cmd
, event
, stageMask
, 1);
3960 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3962 VkPipelineStageFlags stageMask
)
3964 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3965 TU_FROM_HANDLE(tu_event
, event
, _event
);
3967 write_event(cmd
, event
, stageMask
, 0);
3971 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3972 uint32_t eventCount
,
3973 const VkEvent
*pEvents
,
3974 VkPipelineStageFlags srcStageMask
,
3975 VkPipelineStageFlags dstStageMask
,
3976 uint32_t memoryBarrierCount
,
3977 const VkMemoryBarrier
*pMemoryBarriers
,
3978 uint32_t bufferMemoryBarrierCount
,
3979 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3980 uint32_t imageMemoryBarrierCount
,
3981 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3983 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3984 struct tu_barrier_info info
;
3986 info
.eventCount
= eventCount
;
3987 info
.pEvents
= pEvents
;
3988 info
.srcStageMask
= 0;
3990 tu_barrier(cmd
, memoryBarrierCount
, pMemoryBarriers
,
3991 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3992 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3996 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)