src/freedreno/vulkan/tu_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 #include "tu_private.h"
  29
  30 #include "registers/adreno_pm4.xml.h"
  31 #include "registers/adreno_common.xml.h"
  32
  33 #include "vk_format.h"
  34
  35 #include "tu_cs.h"
  36
  37 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
  38
  39 void
  40 tu_bo_list_init(struct tu_bo_list *list)
  41 {
  42    list->count = list->capacity = 0;
  43    list->bo_infos = NULL;
  44 }
  45
  46 void
  47 tu_bo_list_destroy(struct tu_bo_list *list)
  48 {
  49    free(list->bo_infos);
  50 }
  51
  52 void
  53 tu_bo_list_reset(struct tu_bo_list *list)
  54 {
  55    list->count = 0;
  56 }
  57
  58 /**
  59  * \a flags consists of MSM_SUBMIT_BO_FLAGS.
  60  */
  61 static uint32_t
  62 tu_bo_list_add_info(struct tu_bo_list *list,
  63                     const struct drm_msm_gem_submit_bo *bo_info)
  64 {
  65    assert(bo_info->handle != 0);
  66
  67    for (uint32_t i = 0; i < list->count; ++i) {
  68       if (list->bo_infos[i].handle == bo_info->handle) {
  69          assert(list->bo_infos[i].presumed == bo_info->presumed);
  70          list->bo_infos[i].flags |= bo_info->flags;
  71          return i;
  72       }
  73    }
  74
  75    /* grow list->bo_infos if needed */
  76    if (list->count == list->capacity) {
  77       uint32_t new_capacity = MAX2(2 * list->count, 16);
  78       struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
  79          list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
  80       if (!new_bo_infos)
  81          return TU_BO_LIST_FAILED;
  82       list->bo_infos = new_bo_infos;
  83       list->capacity = new_capacity;
  84    }
  85
  86    list->bo_infos[list->count] = *bo_info;
  87    return list->count++;
  88 }
  89
  90 uint32_t
  91 tu_bo_list_add(struct tu_bo_list *list,
  92                const struct tu_bo *bo,
  93                uint32_t flags)
  94 {
  95    return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
  96                                        .flags = flags,
  97                                        .handle = bo->gem_handle,
  98                                        .presumed = bo->iova,
  99                                     });
 100 }
 101
 102 VkResult
 103 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
 104 {
 105    for (uint32_t i = 0; i < other->count; i++) {
 106       if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
 107          return VK_ERROR_OUT_OF_HOST_MEMORY;
 108    }
 109
 110    return VK_SUCCESS;
 111 }
 112
 113 static void
 114 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
 115                                     const struct tu_device *dev,
 116                                     uint32_t pixels)
 117 {
 118    const uint32_t tile_align_w = 64; /* note: 32 when no input attachments */
 119    const uint32_t tile_align_h = 16;
 120    const uint32_t max_tile_width = 1024;
 121
 122    /* note: don't offset the tiling config by render_area.offset,
 123     * because binning pass can't deal with it
 124     * this means we might end up with more tiles than necessary,
 125     * but load/store/etc are still scissored to the render_area
 126     */
 127    tiling->tile0.offset = (VkOffset2D) {};
 128
 129    const uint32_t ra_width =
 130       tiling->render_area.extent.width +
 131       (tiling->render_area.offset.x - tiling->tile0.offset.x);
 132    const uint32_t ra_height =
 133       tiling->render_area.extent.height +
 134       (tiling->render_area.offset.y - tiling->tile0.offset.y);
 135
 136    /* start from 1 tile */
 137    tiling->tile_count = (VkExtent2D) {
 138       .width = 1,
 139       .height = 1,
 140    };
 141    tiling->tile0.extent = (VkExtent2D) {
 142       .width = align(ra_width, tile_align_w),
 143       .height = align(ra_height, tile_align_h),
 144    };
 145
 146    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN)) {
 147       /* start with 2x2 tiles */
 148       tiling->tile_count.width = 2;
 149       tiling->tile_count.height = 2;
 150       tiling->tile0.extent.width = align(DIV_ROUND_UP(ra_width, 2), tile_align_w);
 151       tiling->tile0.extent.height = align(DIV_ROUND_UP(ra_height, 2), tile_align_h);
 152    }
 153
 154    /* do not exceed max tile width */
 155    while (tiling->tile0.extent.width > max_tile_width) {
 156       tiling->tile_count.width++;
 157       tiling->tile0.extent.width =
 158          align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 159    }
 160
 161    /* will force to sysmem, don't bother trying to have a valid tile config
 162     * TODO: just skip all GMEM stuff when sysmem is forced?
 163     */
 164    if (!pixels)
 165       return;
 166
 167    /* do not exceed gmem size */
 168    while (tiling->tile0.extent.width * tiling->tile0.extent.height > pixels) {
 169       if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
 170          tiling->tile_count.width++;
 171          tiling->tile0.extent.width =
 172             align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 173       } else {
 174          /* if this assert fails then layout is impossible.. */
 175          assert(tiling->tile0.extent.height > tile_align_h);
 176          tiling->tile_count.height++;
 177          tiling->tile0.extent.height =
 178             align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), tile_align_h);
 179       }
 180    }
 181 }
 182
 183 static void
 184 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
 185                                     const struct tu_device *dev)
 186 {
 187    const uint32_t max_pipe_count = 32; /* A6xx */
 188
 189    /* start from 1 tile per pipe */
 190    tiling->pipe0 = (VkExtent2D) {
 191       .width = 1,
 192       .height = 1,
 193    };
 194    tiling->pipe_count = tiling->tile_count;
 195
 196    while (tiling->pipe_count.width * tiling->pipe_count.height > max_pipe_count) {
 197       if (tiling->pipe0.width < tiling->pipe0.height) {
 198          tiling->pipe0.width += 1;
 199          tiling->pipe_count.width =
 200             DIV_ROUND_UP(tiling->tile_count.width, tiling->pipe0.width);
 201       } else {
 202          tiling->pipe0.height += 1;
 203          tiling->pipe_count.height =
 204             DIV_ROUND_UP(tiling->tile_count.height, tiling->pipe0.height);
 205       }
 206    }
 207 }
 208
 209 static void
 210 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
 211                               const struct tu_device *dev)
 212 {
 213    const uint32_t max_pipe_count = 32; /* A6xx */
 214    const uint32_t used_pipe_count =
 215       tiling->pipe_count.width * tiling->pipe_count.height;
 216    const VkExtent2D last_pipe = {
 217       .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
 218       .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
 219    };
 220
 221    assert(used_pipe_count <= max_pipe_count);
 222    assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
 223
 224    for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
 225       for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
 226          const uint32_t pipe_x = tiling->pipe0.width * x;
 227          const uint32_t pipe_y = tiling->pipe0.height * y;
 228          const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
 229                                     ? last_pipe.width
 230                                     : tiling->pipe0.width;
 231          const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
 232                                     ? last_pipe.height
 233                                     : tiling->pipe0.height;
 234          const uint32_t n = tiling->pipe_count.width * y + x;
 235
 236          tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
 237                                   A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
 238                                   A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
 239                                   A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
 240          tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
 241       }
 242    }
 243
 244    memset(tiling->pipe_config + used_pipe_count, 0,
 245           sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
 246 }
 247
 248 static void
 249 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
 250                           const struct tu_device *dev,
 251                           uint32_t tx,
 252                           uint32_t ty,
 253                           struct tu_tile *tile)
 254 {
 255    /* find the pipe and the slot for tile (tx, ty) */
 256    const uint32_t px = tx / tiling->pipe0.width;
 257    const uint32_t py = ty / tiling->pipe0.height;
 258    const uint32_t sx = tx - tiling->pipe0.width * px;
 259    const uint32_t sy = ty - tiling->pipe0.height * py;
 260    /* last pipe has different width */
 261    const uint32_t pipe_width =
 262       MIN2(tiling->pipe0.width,
 263            tiling->tile_count.width - px * tiling->pipe0.width);
 264
 265    assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
 266    assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
 267    assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
 268
 269    /* convert to 1D indices */
 270    tile->pipe = tiling->pipe_count.width * py + px;
 271    tile->slot = pipe_width * sy + sx;
 272
 273    /* get the blit area for the tile */
 274    tile->begin = (VkOffset2D) {
 275       .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
 276       .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
 277    };
 278    tile->end.x =
 279       (tx == tiling->tile_count.width - 1)
 280          ? tiling->render_area.offset.x + tiling->render_area.extent.width
 281          : tile->begin.x + tiling->tile0.extent.width;
 282    tile->end.y =
 283       (ty == tiling->tile_count.height - 1)
 284          ? tiling->render_area.offset.y + tiling->render_area.extent.height
 285          : tile->begin.y + tiling->tile0.extent.height;
 286 }
 287
 288 enum a3xx_msaa_samples
 289 tu_msaa_samples(uint32_t samples)
 290 {
 291    switch (samples) {
 292    case 1:
 293       return MSAA_ONE;
 294    case 2:
 295       return MSAA_TWO;
 296    case 4:
 297       return MSAA_FOUR;
 298    case 8:
 299       return MSAA_EIGHT;
 300    default:
 301       assert(!"invalid sample count");
 302       return MSAA_ONE;
 303    }
 304 }
 305
 306 static enum a4xx_index_size
 307 tu6_index_size(VkIndexType type)
 308 {
 309    switch (type) {
 310    case VK_INDEX_TYPE_UINT16:
 311       return INDEX4_SIZE_16_BIT;
 312    case VK_INDEX_TYPE_UINT32:
 313       return INDEX4_SIZE_32_BIT;
 314    default:
 315       unreachable("invalid VkIndexType");
 316       return INDEX4_SIZE_8_BIT;
 317    }
 318 }
 319
 320 unsigned
 321 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
 322                      struct tu_cs *cs,
 323                      enum vgt_event_type event,
 324                      bool need_seqno)
 325 {
 326    unsigned seqno = 0;
 327
 328    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
 329    tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
 330    if (need_seqno) {
 331       tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 332       seqno = ++cmd->scratch_seqno;
 333       tu_cs_emit(cs, seqno);
 334    }
 335
 336    return seqno;
 337 }
 338
 339 static void
 340 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 341 {
 342    tu6_emit_event_write(cmd, cs, 0x31, false);
 343 }
 344
 345 static void
 346 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 347 {
 348    tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
 349 }
 350
 351 static void
 352 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 353 {
 354    if (cmd->wait_for_idle) {
 355       tu_cs_emit_wfi(cs);
 356       cmd->wait_for_idle = false;
 357    }
 358 }
 359
 360 static void
 361 tu6_emit_zs(struct tu_cmd_buffer *cmd,
 362             const struct tu_subpass *subpass,
 363             struct tu_cs *cs)
 364 {
 365    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 366
 367    const uint32_t a = subpass->depth_stencil_attachment.attachment;
 368    if (a == VK_ATTACHMENT_UNUSED) {
 369       tu_cs_emit_regs(cs,
 370                       A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE),
 371                       A6XX_RB_DEPTH_BUFFER_PITCH(0),
 372                       A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
 373                       A6XX_RB_DEPTH_BUFFER_BASE(0),
 374                       A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
 375
 376       tu_cs_emit_regs(cs,
 377                       A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
 378
 379       tu_cs_emit_regs(cs,
 380                       A6XX_GRAS_LRZ_BUFFER_BASE(0),
 381                       A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 382                       A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 383
 384       tu_cs_emit_regs(cs, A6XX_RB_STENCIL_INFO(0));
 385
 386       return;
 387    }
 388
 389    const struct tu_image_view *iview = fb->attachments[a].attachment;
 390    enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
 391
 392    tu_cs_emit_regs(cs,
 393                    A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
 394                    A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)),
 395                    A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layout.layer_size),
 396                    A6XX_RB_DEPTH_BUFFER_BASE(tu_image_view_base_ref(iview)),
 397                    A6XX_RB_DEPTH_BUFFER_BASE_GMEM(cmd->state.pass->attachments[a].gmem_offset));
 398
 399    tu_cs_emit_regs(cs,
 400                    A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
 401
 402    tu_cs_emit_regs(cs,
 403                    A6XX_RB_DEPTH_FLAG_BUFFER_BASE(tu_image_view_ubwc_base_ref(iview)),
 404                    A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(tu_image_view_ubwc_pitches(iview)));
 405
 406    tu_cs_emit_regs(cs,
 407                    A6XX_GRAS_LRZ_BUFFER_BASE(0),
 408                    A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 409                    A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 410
 411    tu_cs_emit_regs(cs,
 412                    A6XX_RB_STENCIL_INFO(0));
 413
 414    /* enable zs? */
 415 }
 416
 417 static void
 418 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
 419              const struct tu_subpass *subpass,
 420              struct tu_cs *cs)
 421 {
 422    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 423    unsigned char mrt_comp[MAX_RTS] = { 0 };
 424    unsigned srgb_cntl = 0;
 425
 426    for (uint32_t i = 0; i < subpass->color_count; ++i) {
 427       uint32_t a = subpass->color_attachments[i].attachment;
 428       if (a == VK_ATTACHMENT_UNUSED)
 429          continue;
 430
 431       const struct tu_image_view *iview = fb->attachments[a].attachment;
 432
 433       mrt_comp[i] = 0xf;
 434
 435       if (vk_format_is_srgb(iview->vk_format))
 436          srgb_cntl |= (1 << i);
 437
 438       struct tu_native_format format =
 439          tu6_format_image(iview->image, iview->vk_format, iview->base_mip);
 440
 441       tu_cs_emit_regs(cs,
 442                       A6XX_RB_MRT_BUF_INFO(i,
 443                                            .color_tile_mode = format.tile_mode,
 444                                            .color_format = format.fmt,
 445                                            .color_swap = format.swap),
 446                       A6XX_RB_MRT_PITCH(i, tu_image_stride(iview->image, iview->base_mip)),
 447                       A6XX_RB_MRT_ARRAY_PITCH(i, iview->image->layout.layer_size),
 448                       A6XX_RB_MRT_BASE(i, tu_image_view_base_ref(iview)),
 449                       A6XX_RB_MRT_BASE_GMEM(i, cmd->state.pass->attachments[a].gmem_offset));
 450
 451       tu_cs_emit_regs(cs,
 452                       A6XX_SP_FS_MRT_REG(i,
 453                                          .color_format = format.fmt,
 454                                          .color_sint = vk_format_is_sint(iview->vk_format),
 455                                          .color_uint = vk_format_is_uint(iview->vk_format)));
 456
 457       tu_cs_emit_regs(cs,
 458                       A6XX_RB_MRT_FLAG_BUFFER_ADDR(i, tu_image_view_ubwc_base_ref(iview)),
 459                       A6XX_RB_MRT_FLAG_BUFFER_PITCH(i, tu_image_view_ubwc_pitches(iview)));
 460    }
 461
 462    tu_cs_emit_regs(cs,
 463                    A6XX_RB_SRGB_CNTL(.dword = srgb_cntl));
 464
 465    tu_cs_emit_regs(cs,
 466                    A6XX_SP_SRGB_CNTL(.dword = srgb_cntl));
 467
 468    tu_cs_emit_regs(cs,
 469                    A6XX_RB_RENDER_COMPONENTS(
 470                       .rt0 = mrt_comp[0],
 471                       .rt1 = mrt_comp[1],
 472                       .rt2 = mrt_comp[2],
 473                       .rt3 = mrt_comp[3],
 474                       .rt4 = mrt_comp[4],
 475                       .rt5 = mrt_comp[5],
 476                       .rt6 = mrt_comp[6],
 477                       .rt7 = mrt_comp[7]));
 478
 479    tu_cs_emit_regs(cs,
 480                    A6XX_SP_FS_RENDER_COMPONENTS(
 481                       .rt0 = mrt_comp[0],
 482                       .rt1 = mrt_comp[1],
 483                       .rt2 = mrt_comp[2],
 484                       .rt3 = mrt_comp[3],
 485                       .rt4 = mrt_comp[4],
 486                       .rt5 = mrt_comp[5],
 487                       .rt6 = mrt_comp[6],
 488                       .rt7 = mrt_comp[7]));
 489
 490    // XXX: We probably can't hardcode LAYER_CNTL_TYPE.
 491    tu_cs_emit_regs(cs,
 492                    A6XX_GRAS_LAYER_CNTL(.layered = fb->layers > 1,
 493                                         .type = LAYER_2D_ARRAY));
 494 }
 495
 496 void
 497 tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits vk_samples)
 498 {
 499    const enum a3xx_msaa_samples samples = tu_msaa_samples(vk_samples);
 500    bool msaa_disable = samples == MSAA_ONE;
 501
 502    tu_cs_emit_regs(cs,
 503                    A6XX_SP_TP_RAS_MSAA_CNTL(samples),
 504                    A6XX_SP_TP_DEST_MSAA_CNTL(.samples = samples,
 505                                              .msaa_disable = msaa_disable));
 506
 507    tu_cs_emit_regs(cs,
 508                    A6XX_GRAS_RAS_MSAA_CNTL(samples),
 509                    A6XX_GRAS_DEST_MSAA_CNTL(.samples = samples,
 510                                             .msaa_disable = msaa_disable));
 511
 512    tu_cs_emit_regs(cs,
 513                    A6XX_RB_RAS_MSAA_CNTL(samples),
 514                    A6XX_RB_DEST_MSAA_CNTL(.samples = samples,
 515                                           .msaa_disable = msaa_disable));
 516
 517    tu_cs_emit_regs(cs,
 518                    A6XX_RB_MSAA_CNTL(samples));
 519 }
 520
 521 static void
 522 tu6_emit_bin_size(struct tu_cs *cs,
 523                   uint32_t bin_w, uint32_t bin_h, uint32_t flags)
 524 {
 525    tu_cs_emit_regs(cs,
 526                    A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
 527                                          .binh = bin_h,
 528                                          .dword = flags));
 529
 530    tu_cs_emit_regs(cs,
 531                    A6XX_RB_BIN_CONTROL(.binw = bin_w,
 532                                        .binh = bin_h,
 533                                        .dword = flags));
 534
 535    /* no flag for RB_BIN_CONTROL2... */
 536    tu_cs_emit_regs(cs,
 537                    A6XX_RB_BIN_CONTROL2(.binw = bin_w,
 538                                         .binh = bin_h));
 539 }
 540
 541 static void
 542 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
 543                      const struct tu_subpass *subpass,
 544                      struct tu_cs *cs,
 545                      bool binning)
 546 {
 547    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 548    uint32_t cntl = 0;
 549    cntl |= A6XX_RB_RENDER_CNTL_UNK4;
 550    if (binning) {
 551       cntl |= A6XX_RB_RENDER_CNTL_BINNING;
 552    } else {
 553       uint32_t mrts_ubwc_enable = 0;
 554       for (uint32_t i = 0; i < subpass->color_count; ++i) {
 555          uint32_t a = subpass->color_attachments[i].attachment;
 556          if (a == VK_ATTACHMENT_UNUSED)
 557             continue;
 558
 559          const struct tu_image_view *iview = fb->attachments[a].attachment;
 560          if (iview->image->layout.ubwc_layer_size != 0)
 561             mrts_ubwc_enable |= 1 << i;
 562       }
 563
 564       cntl |= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable);
 565
 566       const uint32_t a = subpass->depth_stencil_attachment.attachment;
 567       if (a != VK_ATTACHMENT_UNUSED) {
 568          const struct tu_image_view *iview = fb->attachments[a].attachment;
 569          if (iview->image->layout.ubwc_layer_size != 0)
 570             cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH;
 571       }
 572
 573       /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
 574        * in order to set it correctly for the different subpasses. However,
 575        * that means the packets we're emitting also happen during binning. So
 576        * we need to guard the write on !BINNING at CP execution time.
 577        */
 578       tu_cs_reserve(cs, 3 + 4);
 579       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 580       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
 581                      CP_COND_REG_EXEC_0_GMEM | CP_COND_REG_EXEC_0_SYSMEM);
 582       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(4));
 583    }
 584
 585    tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
 586    tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
 587    tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
 588    tu_cs_emit(cs, cntl);
 589 }
 590
 591 static void
 592 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
 593 {
 594    const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
 595    uint32_t x1 = render_area->offset.x;
 596    uint32_t y1 = render_area->offset.y;
 597    uint32_t x2 = x1 + render_area->extent.width - 1;
 598    uint32_t y2 = y1 + render_area->extent.height - 1;
 599
 600    if (align) {
 601       x1 = x1 & ~(GMEM_ALIGN_W - 1);
 602       y1 = y1 & ~(GMEM_ALIGN_H - 1);
 603       x2 = ALIGN_POT(x2 + 1, GMEM_ALIGN_W) - 1;
 604       y2 = ALIGN_POT(y2 + 1, GMEM_ALIGN_H) - 1;
 605    }
 606
 607    tu_cs_emit_regs(cs,
 608                    A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
 609                    A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
 610 }
 611
 612 void
 613 tu6_emit_window_scissor(struct tu_cs *cs,
 614                         uint32_t x1,
 615                         uint32_t y1,
 616                         uint32_t x2,
 617                         uint32_t y2)
 618 {
 619    tu_cs_emit_regs(cs,
 620                    A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
 621                    A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
 622
 623    tu_cs_emit_regs(cs,
 624                    A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
 625                    A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
 626 }
 627
 628 void
 629 tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1)
 630 {
 631    tu_cs_emit_regs(cs,
 632                    A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
 633
 634    tu_cs_emit_regs(cs,
 635                    A6XX_RB_WINDOW_OFFSET2(.x = x1, .y = y1));
 636
 637    tu_cs_emit_regs(cs,
 638                    A6XX_SP_WINDOW_OFFSET(.x = x1, .y = y1));
 639
 640    tu_cs_emit_regs(cs,
 641                    A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
 642 }
 643
 644 static bool
 645 use_hw_binning(struct tu_cmd_buffer *cmd)
 646 {
 647    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 648
 649    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
 650       return false;
 651
 652    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN))
 653       return true;
 654
 655    return (tiling->tile_count.width * tiling->tile_count.height) > 2;
 656 }
 657
 658 static bool
 659 use_sysmem_rendering(struct tu_cmd_buffer *cmd)
 660 {
 661    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_SYSMEM))
 662       return true;
 663
 664    /* can't fit attachments into gmem */
 665    if (!cmd->state.pass->gmem_pixels)
 666       return true;
 667
 668    if (cmd->state.framebuffer->layers > 1)
 669       return true;
 670
 671    return cmd->state.tiling_config.force_sysmem;
 672 }
 673
 674 static void
 675 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
 676                      struct tu_cs *cs,
 677                      const struct tu_tile *tile)
 678 {
 679    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 680    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD));
 681
 682    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 683    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
 684
 685    const uint32_t x1 = tile->begin.x;
 686    const uint32_t y1 = tile->begin.y;
 687    const uint32_t x2 = tile->end.x - 1;
 688    const uint32_t y2 = tile->end.y - 1;
 689    tu6_emit_window_scissor(cs, x1, y1, x2, y2);
 690    tu6_emit_window_offset(cs, x1, y1);
 691
 692    tu_cs_emit_regs(cs,
 693                    A6XX_VPC_SO_OVERRIDE(.so_disable = false));
 694
 695    if (use_hw_binning(cmd)) {
 696       tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
 697
 698       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 699       tu_cs_emit(cs, 0x0);
 700
 701       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
 702       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
 703                      A6XX_CP_REG_TEST_0_BIT(0) |
 704                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
 705
 706       tu_cs_reserve(cs, 3 + 11);
 707       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 708       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
 709       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(11));
 710
 711       /* if (no overflow) */ {
 712          tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
 713          tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
 714                         CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
 715          tu_cs_emit_qw(cs, cmd->vsc_data.iova + tile->pipe * cmd->vsc_data_pitch);
 716          tu_cs_emit_qw(cs, cmd->vsc_data.iova + (tile->pipe * 4) + (32 * cmd->vsc_data_pitch));
 717          tu_cs_emit_qw(cs, cmd->vsc_data2.iova + (tile->pipe * cmd->vsc_data2_pitch));
 718
 719          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 720          tu_cs_emit(cs, 0x0);
 721
 722          /* use a NOP packet to skip over the 'else' side: */
 723          tu_cs_emit_pkt7(cs, CP_NOP, 2);
 724       } /* else */ {
 725          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 726          tu_cs_emit(cs, 0x1);
 727       }
 728
 729       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 730       tu_cs_emit(cs, 0x0);
 731
 732       tu_cs_emit_regs(cs,
 733                       A6XX_RB_UNKNOWN_8804(0));
 734
 735       tu_cs_emit_regs(cs,
 736                       A6XX_SP_TP_UNKNOWN_B304(0));
 737
 738       tu_cs_emit_regs(cs,
 739                       A6XX_GRAS_UNKNOWN_80A4(0));
 740    } else {
 741       tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 742       tu_cs_emit(cs, 0x1);
 743
 744       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 745       tu_cs_emit(cs, 0x0);
 746    }
 747 }
 748
 749 static void
 750 tu6_emit_sysmem_resolve(struct tu_cmd_buffer *cmd,
 751                         struct tu_cs *cs,
 752                         uint32_t a,
 753                         uint32_t gmem_a)
 754 {
 755    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 756    struct tu_image_view *dst = fb->attachments[a].attachment;
 757    struct tu_image_view *src = fb->attachments[gmem_a].attachment;
 758
 759    tu_resolve_sysmem(cmd, cs, src, dst, fb->layers, &cmd->state.tiling_config.render_area);
 760 }
 761
 762 static void
 763 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 764 {
 765    const struct tu_render_pass *pass = cmd->state.pass;
 766    const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
 767
 768    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
 769    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
 770                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
 771                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
 772    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
 773    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
 774
 775    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 776    tu_cs_emit(cs, 0x0);
 777
 778    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 779    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
 780
 781    /* blit scissor may have been changed by CmdClearAttachments */
 782    tu6_emit_blit_scissor(cmd, cs, false);
 783
 784    for (uint32_t a = 0; a < pass->attachment_count; ++a) {
 785       if (pass->attachments[a].gmem_offset >= 0)
 786          tu_store_gmem_attachment(cmd, cs, a, a);
 787    }
 788
 789    if (subpass->resolve_attachments) {
 790       for (unsigned i = 0; i < subpass->color_count; i++) {
 791          uint32_t a = subpass->resolve_attachments[i].attachment;
 792          if (a != VK_ATTACHMENT_UNUSED)
 793             tu_store_gmem_attachment(cmd, cs, a,
 794                                      subpass->color_attachments[i].attachment);
 795       }
 796    }
 797 }
 798
 799 static void
 800 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
 801 {
 802    tu_cs_emit_regs(cs,
 803                    A6XX_PC_RESTART_INDEX(restart_index));
 804 }
 805
 806 static void
 807 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 808 {
 809    const struct tu_physical_device *phys_dev = cmd->device->physical_device;
 810
 811    tu6_emit_cache_flush(cmd, cs);
 812
 813    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
 814
 815    tu_cs_emit_regs(cs,
 816                    A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_bypass));
 817    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
 818    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
 819    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
 820    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
 821    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
 822    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
 823    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
 824    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
 825
 826    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
 827    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
 828    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
 829    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
 830    tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
 831    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
 832    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
 833    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
 834    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
 835    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
 836    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A982, 0);
 837    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
 838    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
 839    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_GS_SIV_CNTL, 0x0000ffff);
 840
 841    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
 842    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
 843    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
 844
 845    tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
 846
 847    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
 848
 849    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
 850    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
 851    tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
 852    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
 853    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
 854    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
 855    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
 856    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
 857    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
 858    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
 859    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
 860
 861    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
 862    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
 863
 864    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
 865    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
 866
 867    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
 868                         A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
 869
 870    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
 871    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
 872    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
 873    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
 874
 875    tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
 876    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
 877
 878    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
 879
 880    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
 881
 882    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
 883    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
 884    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
 885    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
 886    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
 887    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
 888    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
 889    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
 890    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
 891    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
 892    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
 893    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
 894    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
 895    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
 896    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
 897    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
 898    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
 899    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
 900    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
 901    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
 902    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
 903
 904    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
 905
 906    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
 907
 908    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
 909
 910    /* we don't use this yet.. probably best to disable.. */
 911    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
 912    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
 913                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
 914                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
 915    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
 916    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
 917
 918    /* Set not to use streamout by default, */
 919    tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
 920    tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
 921    tu_cs_emit(cs, 0);
 922    tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
 923    tu_cs_emit(cs, 0);
 924
 925    tu_cs_emit_regs(cs,
 926                    A6XX_SP_HS_CTRL_REG0(0));
 927
 928    tu_cs_emit_regs(cs,
 929                    A6XX_SP_GS_CTRL_REG0(0));
 930
 931    tu_cs_emit_regs(cs,
 932                    A6XX_GRAS_LRZ_CNTL(0));
 933
 934    tu_cs_emit_regs(cs,
 935                    A6XX_RB_LRZ_CNTL(0));
 936
 937    tu_cs_emit_regs(cs,
 938                    A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo = &cmd->device->border_color));
 939    tu_cs_emit_regs(cs,
 940                    A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo = &cmd->device->border_color));
 941
 942    tu_cs_sanity_check(cs);
 943 }
 944
 945 static void
 946 tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 947 {
 948    unsigned seqno;
 949
 950    seqno = tu6_emit_event_write(cmd, cs, RB_DONE_TS, true);
 951
 952    tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
 953    tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
 954                   CP_WAIT_REG_MEM_0_POLL_MEMORY);
 955    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 956    tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(seqno));
 957    tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
 958    tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
 959
 960    seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
 961
 962    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4);
 963    tu_cs_emit(cs, CP_WAIT_MEM_GTE_0_RESERVED(0));
 964    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 965    tu_cs_emit(cs, CP_WAIT_MEM_GTE_3_REF(seqno));
 966 }
 967
 968 static void
 969 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 970 {
 971    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 972
 973    tu_cs_emit_regs(cs,
 974                    A6XX_VSC_BIN_SIZE(.width = tiling->tile0.extent.width,
 975                                      .height = tiling->tile0.extent.height),
 976                    A6XX_VSC_SIZE_ADDRESS(.bo = &cmd->vsc_data,
 977                                          .bo_offset = 32 * cmd->vsc_data_pitch));
 978
 979    tu_cs_emit_regs(cs,
 980                    A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
 981                                       .ny = tiling->tile_count.height));
 982
 983    tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
 984    for (unsigned i = 0; i < 32; i++)
 985       tu_cs_emit(cs, tiling->pipe_config[i]);
 986
 987    tu_cs_emit_regs(cs,
 988                    A6XX_VSC_PIPE_DATA2_ADDRESS(.bo = &cmd->vsc_data2),
 989                    A6XX_VSC_PIPE_DATA2_PITCH(cmd->vsc_data2_pitch),
 990                    A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd->vsc_data2.size));
 991
 992    tu_cs_emit_regs(cs,
 993                    A6XX_VSC_PIPE_DATA_ADDRESS(.bo = &cmd->vsc_data),
 994                    A6XX_VSC_PIPE_DATA_PITCH(cmd->vsc_data_pitch),
 995                    A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd->vsc_data.size));
 996 }
 997
 998 static void
 999 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1000 {
1001    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1002    const uint32_t used_pipe_count =
1003       tiling->pipe_count.width * tiling->pipe_count.height;
1004
1005    /* Clear vsc_scratch: */
1006    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
1007    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
1008    tu_cs_emit(cs, 0x0);
1009
1010    /* Check for overflow, write vsc_scratch if detected: */
1011    for (int i = 0; i < used_pipe_count; i++) {
1012       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1013       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1014             CP_COND_WRITE5_0_WRITE_MEMORY);
1015       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
1016       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1017       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data_pitch));
1018       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1019       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
1020       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_data_pitch));
1021
1022       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1023       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1024             CP_COND_WRITE5_0_WRITE_MEMORY);
1025       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
1026       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1027       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data2_pitch));
1028       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1029       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
1030       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_data2_pitch));
1031    }
1032
1033    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1034
1035    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1036
1037    tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
1038    tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
1039          CP_MEM_TO_REG_0_CNT(1 - 1));
1040    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
1041
1042    /*
1043     * This is a bit awkward, we really want a way to invert the
1044     * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1045     * execute cmds to use hwbinning when a bit is *not* set.  This
1046     * dance is to invert OVERFLOW_FLAG_REG
1047     *
1048     * A CP_NOP packet is used to skip executing the 'else' clause
1049     * if (b0 set)..
1050     */
1051
1052    /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1053    tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1054    tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1055          A6XX_CP_REG_TEST_0_BIT(0) |
1056          A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1057
1058    tu_cs_reserve(cs, 3 + 7);
1059    tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1060    tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1061    tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(7));
1062
1063    /* if (b0 set) */ {
1064       /*
1065        * On overflow, mirror the value to control->vsc_overflow
1066        * which CPU is checking to detect overflow (see
1067        * check_vsc_overflow())
1068        */
1069       tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1070       tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
1071             CP_REG_TO_MEM_0_CNT(0));
1072       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_overflow));
1073
1074       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1075       tu_cs_emit(cs, 0x0);
1076
1077       tu_cs_emit_pkt7(cs, CP_NOP, 2);  /* skip 'else' when 'if' is taken */
1078    } /* else */ {
1079       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1080       tu_cs_emit(cs, 0x1);
1081    }
1082 }
1083
1084 static void
1085 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1086 {
1087    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1088    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1089
1090    uint32_t x1 = tiling->tile0.offset.x;
1091    uint32_t y1 = tiling->tile0.offset.y;
1092    uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
1093    uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
1094
1095    tu6_emit_window_scissor(cs, x1, y1, x2, y2);
1096
1097    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1098    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1099
1100    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1101    tu_cs_emit(cs, 0x1);
1102
1103    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1104    tu_cs_emit(cs, 0x1);
1105
1106    tu_cs_emit_wfi(cs);
1107
1108    tu_cs_emit_regs(cs,
1109                    A6XX_VFD_MODE_CNTL(.binning_pass = true));
1110
1111    update_vsc_pipe(cmd, cs);
1112
1113    tu_cs_emit_regs(cs,
1114                    A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1115
1116    tu_cs_emit_regs(cs,
1117                    A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1118
1119    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1120    tu_cs_emit(cs, UNK_2C);
1121
1122    tu_cs_emit_regs(cs,
1123                    A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
1124
1125    tu_cs_emit_regs(cs,
1126                    A6XX_SP_TP_WINDOW_OFFSET(.x = 0, .y = 0));
1127
1128    /* emit IB to binning drawcmds: */
1129    tu_cs_emit_call(cs, &cmd->draw_cs);
1130
1131    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1132    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1133                   CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1134                   CP_SET_DRAW_STATE__0_GROUP_ID(0));
1135    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1136    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1137
1138    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1139    tu_cs_emit(cs, UNK_2D);
1140
1141    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1142    tu6_cache_flush(cmd, cs);
1143
1144    tu_cs_emit_wfi(cs);
1145
1146    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1147
1148    emit_vsc_overflow_test(cmd, cs);
1149
1150    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1151    tu_cs_emit(cs, 0x0);
1152
1153    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1154    tu_cs_emit(cs, 0x0);
1155
1156    cmd->wait_for_idle = false;
1157 }
1158
1159 static void
1160 tu_emit_load_clear(struct tu_cmd_buffer *cmd,
1161                    const VkRenderPassBeginInfo *info)
1162 {
1163    struct tu_cs *cs = &cmd->draw_cs;
1164
1165    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
1166
1167    tu6_emit_blit_scissor(cmd, cs, true);
1168
1169    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1170       tu_load_gmem_attachment(cmd, cs, i);
1171
1172    tu6_emit_blit_scissor(cmd, cs, false);
1173
1174    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1175       tu_clear_gmem_attachment(cmd, cs, i, info);
1176
1177    tu_cond_exec_end(cs);
1178
1179    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
1180
1181    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1182       tu_clear_sysmem_attachment(cmd, cs, i, info);
1183
1184    tu_cond_exec_end(cs);
1185 }
1186
1187 static void
1188 tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1189                         const struct VkRect2D *renderArea)
1190 {
1191    const struct tu_physical_device *phys_dev = cmd->device->physical_device;
1192    const struct tu_framebuffer *fb = cmd->state.framebuffer;
1193
1194    assert(fb->width > 0 && fb->height > 0);
1195    tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
1196    tu6_emit_window_offset(cs, 0, 0);
1197
1198    tu6_emit_bin_size(cs, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1199
1200    tu6_emit_lrz_flush(cmd, cs);
1201
1202    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1203    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
1204
1205    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1206    tu_cs_emit(cs, 0x0);
1207
1208    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_COLOR, false);
1209    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH, false);
1210    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1211
1212    tu6_emit_wfi(cmd, cs);
1213    tu_cs_emit_regs(cs,
1214                    A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_bypass));
1215
1216    /* enable stream-out, with sysmem there is only one pass: */
1217    tu_cs_emit_regs(cs,
1218                    A6XX_VPC_SO_OVERRIDE(.so_disable = false));
1219
1220    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1221    tu_cs_emit(cs, 0x1);
1222
1223    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1224    tu_cs_emit(cs, 0x0);
1225
1226    tu_cs_sanity_check(cs);
1227 }
1228
1229 static void
1230 tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1231 {
1232    /* Do any resolves of the last subpass. These are handled in the
1233     * tile_store_ib in the gmem path.
1234     */
1235    const struct tu_subpass *subpass = cmd->state.subpass;
1236    if (subpass->resolve_attachments) {
1237       for (unsigned i = 0; i < subpass->color_count; i++) {
1238          uint32_t a = subpass->resolve_attachments[i].attachment;
1239          if (a != VK_ATTACHMENT_UNUSED)
1240             tu6_emit_sysmem_resolve(cmd, cs, a,
1241                                     subpass->color_attachments[i].attachment);
1242       }
1243    }
1244
1245    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1246
1247    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1248    tu_cs_emit(cs, 0x0);
1249
1250    tu6_emit_lrz_flush(cmd, cs);
1251
1252    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
1253    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
1254
1255    tu_cs_sanity_check(cs);
1256 }
1257
1258
1259 static void
1260 tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1261 {
1262    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1263
1264    tu6_emit_lrz_flush(cmd, cs);
1265
1266    /* lrz clear? */
1267
1268    tu6_emit_cache_flush(cmd, cs);
1269
1270    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1271    tu_cs_emit(cs, 0x0);
1272
1273    /* TODO: flushing with barriers instead of blindly always flushing */
1274    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
1275    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
1276    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_COLOR, false);
1277    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH, false);
1278
1279    tu_cs_emit_wfi(cs);
1280    tu_cs_emit_regs(cs,
1281                    A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_gmem, .gmem = 1));
1282
1283    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1284    if (use_hw_binning(cmd)) {
1285       /* enable stream-out during binning pass: */
1286       tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=false));
1287
1288       tu6_emit_bin_size(cs,
1289                         tiling->tile0.extent.width,
1290                         tiling->tile0.extent.height,
1291                         A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
1292
1293       tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true);
1294
1295       tu6_emit_binning_pass(cmd, cs);
1296
1297       /* and disable stream-out for draw pass: */
1298       tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=true));
1299
1300       tu6_emit_bin_size(cs,
1301                         tiling->tile0.extent.width,
1302                         tiling->tile0.extent.height,
1303                         A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
1304
1305       tu_cs_emit_regs(cs,
1306                       A6XX_VFD_MODE_CNTL(0));
1307
1308       tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1309
1310       tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1311
1312       tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1313       tu_cs_emit(cs, 0x1);
1314    } else {
1315       /* no binning pass, so enable stream-out for draw pass:: */
1316       tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=false));
1317
1318       tu6_emit_bin_size(cs,
1319                         tiling->tile0.extent.width,
1320                         tiling->tile0.extent.height,
1321                         0x6000000);
1322    }
1323
1324    tu_cs_sanity_check(cs);
1325 }
1326
1327 static void
1328 tu6_render_tile(struct tu_cmd_buffer *cmd,
1329                 struct tu_cs *cs,
1330                 const struct tu_tile *tile)
1331 {
1332    tu6_emit_tile_select(cmd, cs, tile);
1333
1334    tu_cs_emit_call(cs, &cmd->draw_cs);
1335    cmd->wait_for_idle = true;
1336
1337    if (use_hw_binning(cmd)) {
1338       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1339       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1340                      A6XX_CP_REG_TEST_0_BIT(0) |
1341                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1342
1343       tu_cs_reserve(cs, 3 + 2);
1344       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1345       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1346       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(2));
1347
1348       /* if (no overflow) */ {
1349          tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1350          tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
1351       }
1352    }
1353
1354    tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1355
1356    tu_cs_sanity_check(cs);
1357 }
1358
1359 static void
1360 tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1361 {
1362    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1363
1364    tu_cs_emit_regs(cs,
1365                    A6XX_GRAS_LRZ_CNTL(0));
1366
1367    tu6_emit_lrz_flush(cmd, cs);
1368
1369    tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1370
1371    tu_cs_sanity_check(cs);
1372 }
1373
1374 static void
1375 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1376 {
1377    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1378
1379    tu6_tile_render_begin(cmd, &cmd->cs);
1380
1381    for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1382       for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1383          struct tu_tile tile;
1384          tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1385          tu6_render_tile(cmd, &cmd->cs, &tile);
1386       }
1387    }
1388
1389    tu6_tile_render_end(cmd, &cmd->cs);
1390 }
1391
1392 static void
1393 tu_cmd_render_sysmem(struct tu_cmd_buffer *cmd)
1394 {
1395    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1396
1397    tu6_sysmem_render_begin(cmd, &cmd->cs, &tiling->render_area);
1398
1399    tu_cs_emit_call(&cmd->cs, &cmd->draw_cs);
1400    cmd->wait_for_idle = true;
1401
1402    tu6_sysmem_render_end(cmd, &cmd->cs);
1403 }
1404
1405 static void
1406 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1407 {
1408    const uint32_t tile_store_space = 11 + (35 * 2) * cmd->state.pass->attachment_count;
1409    struct tu_cs sub_cs;
1410
1411    VkResult result =
1412       tu_cs_begin_sub_stream(&cmd->sub_cs, tile_store_space, &sub_cs);
1413    if (result != VK_SUCCESS) {
1414       cmd->record_result = result;
1415       return;
1416    }
1417
1418    /* emit to tile-store sub_cs */
1419    tu6_emit_tile_store(cmd, &sub_cs);
1420
1421    cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1422 }
1423
1424 static void
1425 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1426                             const VkRect2D *render_area)
1427 {
1428    const struct tu_device *dev = cmd->device;
1429    struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1430
1431    tiling->render_area = *render_area;
1432    tiling->force_sysmem = false;
1433
1434    tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass->gmem_pixels);
1435    tu_tiling_config_update_pipe_layout(tiling, dev);
1436    tu_tiling_config_update_pipes(tiling, dev);
1437 }
1438
1439 const struct tu_dynamic_state default_dynamic_state = {
1440    .viewport =
1441      {
1442        .count = 0,
1443      },
1444    .scissor =
1445      {
1446        .count = 0,
1447      },
1448    .line_width = 1.0f,
1449    .depth_bias =
1450      {
1451        .bias = 0.0f,
1452        .clamp = 0.0f,
1453        .slope = 0.0f,
1454      },
1455    .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1456    .depth_bounds =
1457      {
1458        .min = 0.0f,
1459        .max = 1.0f,
1460      },
1461    .stencil_compare_mask =
1462      {
1463        .front = ~0u,
1464        .back = ~0u,
1465      },
1466    .stencil_write_mask =
1467      {
1468        .front = ~0u,
1469        .back = ~0u,
1470      },
1471    .stencil_reference =
1472      {
1473        .front = 0u,
1474        .back = 0u,
1475      },
1476 };
1477
1478 static void UNUSED /* FINISHME */
1479 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1480                       const struct tu_dynamic_state *src)
1481 {
1482    struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1483    uint32_t copy_mask = src->mask;
1484    uint32_t dest_mask = 0;
1485
1486    tu_use_args(cmd_buffer); /* FINISHME */
1487
1488    /* Make sure to copy the number of viewports/scissors because they can
1489     * only be specified at pipeline creation time.
1490     */
1491    dest->viewport.count = src->viewport.count;
1492    dest->scissor.count = src->scissor.count;
1493    dest->discard_rectangle.count = src->discard_rectangle.count;
1494
1495    if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1496       if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1497                  src->viewport.count * sizeof(VkViewport))) {
1498          typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1499                       src->viewport.count);
1500          dest_mask |= TU_DYNAMIC_VIEWPORT;
1501       }
1502    }
1503
1504    if (copy_mask & TU_DYNAMIC_SCISSOR) {
1505       if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1506                  src->scissor.count * sizeof(VkRect2D))) {
1507          typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1508                       src->scissor.count);
1509          dest_mask |= TU_DYNAMIC_SCISSOR;
1510       }
1511    }
1512
1513    if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1514       if (dest->line_width != src->line_width) {
1515          dest->line_width = src->line_width;
1516          dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1517       }
1518    }
1519
1520    if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1521       if (memcmp(&dest->depth_bias, &src->depth_bias,
1522                  sizeof(src->depth_bias))) {
1523          dest->depth_bias = src->depth_bias;
1524          dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1525       }
1526    }
1527
1528    if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1529       if (memcmp(&dest->blend_constants, &src->blend_constants,
1530                  sizeof(src->blend_constants))) {
1531          typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1532          dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1533       }
1534    }
1535
1536    if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1537       if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1538                  sizeof(src->depth_bounds))) {
1539          dest->depth_bounds = src->depth_bounds;
1540          dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1541       }
1542    }
1543
1544    if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1545       if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1546                  sizeof(src->stencil_compare_mask))) {
1547          dest->stencil_compare_mask = src->stencil_compare_mask;
1548          dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1549       }
1550    }
1551
1552    if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1553       if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1554                  sizeof(src->stencil_write_mask))) {
1555          dest->stencil_write_mask = src->stencil_write_mask;
1556          dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1557       }
1558    }
1559
1560    if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1561       if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1562                  sizeof(src->stencil_reference))) {
1563          dest->stencil_reference = src->stencil_reference;
1564          dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1565       }
1566    }
1567
1568    if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1569       if (memcmp(&dest->discard_rectangle.rectangles,
1570                  &src->discard_rectangle.rectangles,
1571                  src->discard_rectangle.count * sizeof(VkRect2D))) {
1572          typed_memcpy(dest->discard_rectangle.rectangles,
1573                       src->discard_rectangle.rectangles,
1574                       src->discard_rectangle.count);
1575          dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1576       }
1577    }
1578 }
1579
1580 static VkResult
1581 tu_create_cmd_buffer(struct tu_device *device,
1582                      struct tu_cmd_pool *pool,
1583                      VkCommandBufferLevel level,
1584                      VkCommandBuffer *pCommandBuffer)
1585 {
1586    struct tu_cmd_buffer *cmd_buffer;
1587    cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1588                           VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1589    if (cmd_buffer == NULL)
1590       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1591
1592    cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1593    cmd_buffer->device = device;
1594    cmd_buffer->pool = pool;
1595    cmd_buffer->level = level;
1596
1597    if (pool) {
1598       list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1599       cmd_buffer->queue_family_index = pool->queue_family_index;
1600
1601    } else {
1602       /* Init the pool_link so we can safely call list_del when we destroy
1603        * the command buffer
1604        */
1605       list_inithead(&cmd_buffer->pool_link);
1606       cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1607    }
1608
1609    tu_bo_list_init(&cmd_buffer->bo_list);
1610    tu_cs_init(&cmd_buffer->cs, device, TU_CS_MODE_GROW, 4096);
1611    tu_cs_init(&cmd_buffer->draw_cs, device, TU_CS_MODE_GROW, 4096);
1612    tu_cs_init(&cmd_buffer->draw_epilogue_cs, device, TU_CS_MODE_GROW, 4096);
1613    tu_cs_init(&cmd_buffer->sub_cs, device, TU_CS_MODE_SUB_STREAM, 2048);
1614
1615    *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1616
1617    list_inithead(&cmd_buffer->upload.list);
1618
1619    VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1620    if (result != VK_SUCCESS)
1621       goto fail_scratch_bo;
1622
1623    /* TODO: resize on overflow */
1624    cmd_buffer->vsc_data_pitch = device->vsc_data_pitch;
1625    cmd_buffer->vsc_data2_pitch = device->vsc_data2_pitch;
1626    cmd_buffer->vsc_data = device->vsc_data;
1627    cmd_buffer->vsc_data2 = device->vsc_data2;
1628
1629    return VK_SUCCESS;
1630
1631 fail_scratch_bo:
1632    list_del(&cmd_buffer->pool_link);
1633    return result;
1634 }
1635
1636 static void
1637 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1638 {
1639    tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1640
1641    list_del(&cmd_buffer->pool_link);
1642
1643    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1644       free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1645
1646    tu_cs_finish(&cmd_buffer->cs);
1647    tu_cs_finish(&cmd_buffer->draw_cs);
1648    tu_cs_finish(&cmd_buffer->draw_epilogue_cs);
1649    tu_cs_finish(&cmd_buffer->sub_cs);
1650
1651    tu_bo_list_destroy(&cmd_buffer->bo_list);
1652    vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1653 }
1654
1655 static VkResult
1656 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1657 {
1658    cmd_buffer->wait_for_idle = true;
1659
1660    cmd_buffer->record_result = VK_SUCCESS;
1661
1662    tu_bo_list_reset(&cmd_buffer->bo_list);
1663    tu_cs_reset(&cmd_buffer->cs);
1664    tu_cs_reset(&cmd_buffer->draw_cs);
1665    tu_cs_reset(&cmd_buffer->draw_epilogue_cs);
1666    tu_cs_reset(&cmd_buffer->sub_cs);
1667
1668    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1669       cmd_buffer->descriptors[i].valid = 0;
1670       cmd_buffer->descriptors[i].push_dirty = false;
1671    }
1672
1673    cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1674
1675    return cmd_buffer->record_result;
1676 }
1677
1678 VkResult
1679 tu_AllocateCommandBuffers(VkDevice _device,
1680                           const VkCommandBufferAllocateInfo *pAllocateInfo,
1681                           VkCommandBuffer *pCommandBuffers)
1682 {
1683    TU_FROM_HANDLE(tu_device, device, _device);
1684    TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1685
1686    VkResult result = VK_SUCCESS;
1687    uint32_t i;
1688
1689    for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1690
1691       if (!list_is_empty(&pool->free_cmd_buffers)) {
1692          struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1693             &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1694
1695          list_del(&cmd_buffer->pool_link);
1696          list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1697
1698          result = tu_reset_cmd_buffer(cmd_buffer);
1699          cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1700          cmd_buffer->level = pAllocateInfo->level;
1701
1702          pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1703       } else {
1704          result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1705                                        &pCommandBuffers[i]);
1706       }
1707       if (result != VK_SUCCESS)
1708          break;
1709    }
1710
1711    if (result != VK_SUCCESS) {
1712       tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1713                             pCommandBuffers);
1714
1715       /* From the Vulkan 1.0.66 spec:
1716        *
1717        * "vkAllocateCommandBuffers can be used to create multiple
1718        *  command buffers. If the creation of any of those command
1719        *  buffers fails, the implementation must destroy all
1720        *  successfully created command buffer objects from this
1721        *  command, set all entries of the pCommandBuffers array to
1722        *  NULL and return the error."
1723        */
1724       memset(pCommandBuffers, 0,
1725              sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1726    }
1727
1728    return result;
1729 }
1730
1731 void
1732 tu_FreeCommandBuffers(VkDevice device,
1733                       VkCommandPool commandPool,
1734                       uint32_t commandBufferCount,
1735                       const VkCommandBuffer *pCommandBuffers)
1736 {
1737    for (uint32_t i = 0; i < commandBufferCount; i++) {
1738       TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1739
1740       if (cmd_buffer) {
1741          if (cmd_buffer->pool) {
1742             list_del(&cmd_buffer->pool_link);
1743             list_addtail(&cmd_buffer->pool_link,
1744                          &cmd_buffer->pool->free_cmd_buffers);
1745          } else
1746             tu_cmd_buffer_destroy(cmd_buffer);
1747       }
1748    }
1749 }
1750
1751 VkResult
1752 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1753                       VkCommandBufferResetFlags flags)
1754 {
1755    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1756    return tu_reset_cmd_buffer(cmd_buffer);
1757 }
1758
1759 VkResult
1760 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1761                       const VkCommandBufferBeginInfo *pBeginInfo)
1762 {
1763    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1764    VkResult result = VK_SUCCESS;
1765
1766    if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1767       /* If the command buffer has already been resetted with
1768        * vkResetCommandBuffer, no need to do it again.
1769        */
1770       result = tu_reset_cmd_buffer(cmd_buffer);
1771       if (result != VK_SUCCESS)
1772          return result;
1773    }
1774
1775    memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1776    cmd_buffer->usage_flags = pBeginInfo->flags;
1777
1778    tu_cs_begin(&cmd_buffer->cs);
1779    tu_cs_begin(&cmd_buffer->draw_cs);
1780    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
1781
1782    cmd_buffer->scratch_seqno = 0;
1783
1784    /* setup initial configuration into command buffer */
1785    if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1786       switch (cmd_buffer->queue_family_index) {
1787       case TU_QUEUE_GENERAL:
1788          tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1789          break;
1790       default:
1791          break;
1792       }
1793    } else if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
1794               (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
1795       assert(pBeginInfo->pInheritanceInfo);
1796       cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1797       cmd_buffer->state.subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1798    }
1799
1800    cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1801
1802    return VK_SUCCESS;
1803 }
1804
1805 void
1806 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1807                         uint32_t firstBinding,
1808                         uint32_t bindingCount,
1809                         const VkBuffer *pBuffers,
1810                         const VkDeviceSize *pOffsets)
1811 {
1812    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1813
1814    assert(firstBinding + bindingCount <= MAX_VBS);
1815
1816    for (uint32_t i = 0; i < bindingCount; i++) {
1817       cmd->state.vb.buffers[firstBinding + i] =
1818          tu_buffer_from_handle(pBuffers[i]);
1819       cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1820    }
1821
1822    /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1823    cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1824 }
1825
1826 void
1827 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1828                       VkBuffer buffer,
1829                       VkDeviceSize offset,
1830                       VkIndexType indexType)
1831 {
1832    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1833    TU_FROM_HANDLE(tu_buffer, buf, buffer);
1834
1835    /* initialize/update the restart index */
1836    if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1837       struct tu_cs *draw_cs = &cmd->draw_cs;
1838
1839       tu6_emit_restart_index(
1840          draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1841
1842       tu_cs_sanity_check(draw_cs);
1843    }
1844
1845    /* track the BO */
1846    if (cmd->state.index_buffer != buf)
1847       tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1848
1849    cmd->state.index_buffer = buf;
1850    cmd->state.index_offset = offset;
1851    cmd->state.index_type = indexType;
1852 }
1853
1854 void
1855 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1856                          VkPipelineBindPoint pipelineBindPoint,
1857                          VkPipelineLayout _layout,
1858                          uint32_t firstSet,
1859                          uint32_t descriptorSetCount,
1860                          const VkDescriptorSet *pDescriptorSets,
1861                          uint32_t dynamicOffsetCount,
1862                          const uint32_t *pDynamicOffsets)
1863 {
1864    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1865    TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1866    unsigned dyn_idx = 0;
1867
1868    struct tu_descriptor_state *descriptors_state =
1869       tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1870
1871    for (unsigned i = 0; i < descriptorSetCount; ++i) {
1872       unsigned idx = i + firstSet;
1873       TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1874
1875       descriptors_state->sets[idx] = set;
1876       descriptors_state->valid |= (1u << idx);
1877
1878       /* Note: the actual input attachment indices come from the shader
1879        * itself, so we can't generate the patched versions of these until
1880        * draw time when both the pipeline and descriptors are bound and
1881        * we're inside the render pass.
1882        */
1883       unsigned dst_idx = layout->set[idx].input_attachment_start;
1884       memcpy(&descriptors_state->input_attachments[dst_idx * A6XX_TEX_CONST_DWORDS],
1885              set->dynamic_descriptors,
1886              set->layout->input_attachment_count * A6XX_TEX_CONST_DWORDS * 4);
1887
1888       for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1889          /* Dynamic buffers come after input attachments in the descriptor set
1890           * itself, but due to how the Vulkan descriptor set binding works, we
1891           * have to put input attachments and dynamic buffers in separate
1892           * buffers in the descriptor_state and then combine them at draw
1893           * time. Binding a descriptor set only invalidates the descriptor
1894           * sets after it, but if we try to tightly pack the descriptors after
1895           * the input attachments then we could corrupt dynamic buffers in the
1896           * descriptor set before it, or we'd have to move all the dynamic
1897           * buffers over. We just put them into separate buffers to make
1898           * binding as well as the later patching of input attachments easy.
1899           */
1900          unsigned src_idx = j + set->layout->input_attachment_count;
1901          unsigned dst_idx = j + layout->set[idx].dynamic_offset_start;
1902          assert(dyn_idx < dynamicOffsetCount);
1903
1904          uint32_t *dst =
1905             &descriptors_state->dynamic_descriptors[dst_idx * A6XX_TEX_CONST_DWORDS];
1906          uint32_t *src =
1907             &set->dynamic_descriptors[src_idx * A6XX_TEX_CONST_DWORDS];
1908          uint32_t offset = pDynamicOffsets[dyn_idx];
1909
1910          /* Patch the storage/uniform descriptors right away. */
1911          if (layout->set[idx].layout->dynamic_ubo & (1 << j)) {
1912             /* Note: we can assume here that the addition won't roll over and
1913              * change the SIZE field.
1914              */
1915             uint64_t va = src[0] | ((uint64_t)src[1] << 32);
1916             va += offset;
1917             dst[0] = va;
1918             dst[1] = va >> 32;
1919          } else {
1920             memcpy(dst, src, A6XX_TEX_CONST_DWORDS * 4);
1921             /* Note: A6XX_IBO_5_DEPTH is always 0 */
1922             uint64_t va = dst[4] | ((uint64_t)dst[5] << 32);
1923             va += offset;
1924             dst[4] = va;
1925             dst[5] = va >> 32;
1926          }
1927       }
1928    }
1929
1930    if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE)
1931       cmd_buffer->state.dirty |= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS;
1932    else
1933       cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1934 }
1935
1936 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,
1937                                            uint32_t firstBinding,
1938                                            uint32_t bindingCount,
1939                                            const VkBuffer *pBuffers,
1940                                            const VkDeviceSize *pOffsets,
1941                                            const VkDeviceSize *pSizes)
1942 {
1943    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1944    assert(firstBinding + bindingCount <= IR3_MAX_SO_BUFFERS);
1945
1946    for (uint32_t i = 0; i < bindingCount; i++) {
1947       uint32_t idx = firstBinding + i;
1948       TU_FROM_HANDLE(tu_buffer, buf, pBuffers[i]);
1949
1950       if (pOffsets[i] != 0)
1951          cmd->state.streamout_reset |= 1 << idx;
1952
1953       cmd->state.streamout_buf.buffers[idx] = buf;
1954       cmd->state.streamout_buf.offsets[idx] = pOffsets[i];
1955       cmd->state.streamout_buf.sizes[idx] = pSizes[i];
1956
1957       cmd->state.streamout_enabled |= 1 << idx;
1958    }
1959
1960    cmd->state.dirty |= TU_CMD_DIRTY_STREAMOUT_BUFFERS;
1961 }
1962
1963 void tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,
1964                                        uint32_t firstCounterBuffer,
1965                                        uint32_t counterBufferCount,
1966                                        const VkBuffer *pCounterBuffers,
1967                                        const VkDeviceSize *pCounterBufferOffsets)
1968 {
1969    assert(firstCounterBuffer + counterBufferCount <= IR3_MAX_SO_BUFFERS);
1970    /* TODO do something with counter buffer? */
1971 }
1972
1973 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,
1974                                        uint32_t firstCounterBuffer,
1975                                        uint32_t counterBufferCount,
1976                                        const VkBuffer *pCounterBuffers,
1977                                        const VkDeviceSize *pCounterBufferOffsets)
1978 {
1979    assert(firstCounterBuffer + counterBufferCount <= IR3_MAX_SO_BUFFERS);
1980    /* TODO do something with counter buffer? */
1981
1982    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1983    cmd->state.streamout_enabled = 0;
1984 }
1985
1986 void
1987 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1988                     VkPipelineLayout layout,
1989                     VkShaderStageFlags stageFlags,
1990                     uint32_t offset,
1991                     uint32_t size,
1992                     const void *pValues)
1993 {
1994    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1995    memcpy((void*) cmd->push_constants + offset, pValues, size);
1996    cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
1997 }
1998
1999 VkResult
2000 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
2001 {
2002    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2003
2004    if (cmd_buffer->scratch_seqno) {
2005       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
2006                      MSM_SUBMIT_BO_WRITE);
2007    }
2008
2009    if (cmd_buffer->use_vsc_data) {
2010       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data,
2011                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2012       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data2,
2013                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2014    }
2015
2016    tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->device->border_color,
2017                   MSM_SUBMIT_BO_READ);
2018
2019    for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
2020       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
2021                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2022    }
2023
2024    for (uint32_t i = 0; i < cmd_buffer->draw_epilogue_cs.bo_count; i++) {
2025       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_epilogue_cs.bos[i],
2026                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2027    }
2028
2029    for (uint32_t i = 0; i < cmd_buffer->sub_cs.bo_count; i++) {
2030       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->sub_cs.bos[i],
2031                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2032    }
2033
2034    tu_cs_end(&cmd_buffer->cs);
2035    tu_cs_end(&cmd_buffer->draw_cs);
2036    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
2037
2038    cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
2039
2040    return cmd_buffer->record_result;
2041 }
2042
2043 void
2044 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
2045                    VkPipelineBindPoint pipelineBindPoint,
2046                    VkPipeline _pipeline)
2047 {
2048    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2049    TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2050
2051    switch (pipelineBindPoint) {
2052    case VK_PIPELINE_BIND_POINT_GRAPHICS:
2053       cmd->state.pipeline = pipeline;
2054       cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
2055       break;
2056    case VK_PIPELINE_BIND_POINT_COMPUTE:
2057       cmd->state.compute_pipeline = pipeline;
2058       cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
2059       break;
2060    default:
2061       unreachable("unrecognized pipeline bind point");
2062       break;
2063    }
2064
2065    tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2066                   MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2067    for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2068       tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2069                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2070    }
2071 }
2072
2073 void
2074 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2075                   uint32_t firstViewport,
2076                   uint32_t viewportCount,
2077                   const VkViewport *pViewports)
2078 {
2079    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2080
2081    assert(firstViewport == 0 && viewportCount == 1);
2082    cmd->state.dynamic.viewport.viewports[0] = pViewports[0];
2083    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_VIEWPORT;
2084 }
2085
2086 void
2087 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2088                  uint32_t firstScissor,
2089                  uint32_t scissorCount,
2090                  const VkRect2D *pScissors)
2091 {
2092    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2093
2094    assert(firstScissor == 0 && scissorCount == 1);
2095    cmd->state.dynamic.scissor.scissors[0] = pScissors[0];
2096    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_SCISSOR;
2097 }
2098
2099 void
2100 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2101 {
2102    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2103
2104    cmd->state.dynamic.line_width = lineWidth;
2105
2106    /* line width depends on VkPipelineRasterizationStateCreateInfo */
2107    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2108 }
2109
2110 void
2111 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2112                    float depthBiasConstantFactor,
2113                    float depthBiasClamp,
2114                    float depthBiasSlopeFactor)
2115 {
2116    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2117    struct tu_cs *draw_cs = &cmd->draw_cs;
2118
2119    tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
2120                        depthBiasSlopeFactor);
2121
2122    tu_cs_sanity_check(draw_cs);
2123 }
2124
2125 void
2126 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2127                         const float blendConstants[4])
2128 {
2129    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2130    struct tu_cs *draw_cs = &cmd->draw_cs;
2131
2132    tu6_emit_blend_constants(draw_cs, blendConstants);
2133
2134    tu_cs_sanity_check(draw_cs);
2135 }
2136
2137 void
2138 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2139                      float minDepthBounds,
2140                      float maxDepthBounds)
2141 {
2142 }
2143
2144 void
2145 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2146                             VkStencilFaceFlags faceMask,
2147                             uint32_t compareMask)
2148 {
2149    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2150
2151    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2152       cmd->state.dynamic.stencil_compare_mask.front = compareMask;
2153    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2154       cmd->state.dynamic.stencil_compare_mask.back = compareMask;
2155
2156    /* the front/back compare masks must be updated together */
2157    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2158 }
2159
2160 void
2161 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2162                           VkStencilFaceFlags faceMask,
2163                           uint32_t writeMask)
2164 {
2165    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2166
2167    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2168       cmd->state.dynamic.stencil_write_mask.front = writeMask;
2169    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2170       cmd->state.dynamic.stencil_write_mask.back = writeMask;
2171
2172    /* the front/back write masks must be updated together */
2173    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2174 }
2175
2176 void
2177 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2178                           VkStencilFaceFlags faceMask,
2179                           uint32_t reference)
2180 {
2181    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2182
2183    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2184       cmd->state.dynamic.stencil_reference.front = reference;
2185    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2186       cmd->state.dynamic.stencil_reference.back = reference;
2187
2188    /* the front/back references must be updated together */
2189    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2190 }
2191
2192 void
2193 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2194                       uint32_t commandBufferCount,
2195                       const VkCommandBuffer *pCmdBuffers)
2196 {
2197    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2198    VkResult result;
2199
2200    assert(commandBufferCount > 0);
2201
2202    for (uint32_t i = 0; i < commandBufferCount; i++) {
2203       TU_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
2204
2205       result = tu_bo_list_merge(&cmd->bo_list, &secondary->bo_list);
2206       if (result != VK_SUCCESS) {
2207          cmd->record_result = result;
2208          break;
2209       }
2210
2211       if (secondary->usage_flags &
2212           VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2213          assert(tu_cs_is_empty(&secondary->cs));
2214
2215          result = tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
2216          if (result != VK_SUCCESS) {
2217             cmd->record_result = result;
2218             break;
2219          }
2220
2221          result = tu_cs_add_entries(&cmd->draw_epilogue_cs,
2222                &secondary->draw_epilogue_cs);
2223          if (result != VK_SUCCESS) {
2224             cmd->record_result = result;
2225             break;
2226          }
2227       } else {
2228          assert(tu_cs_is_empty(&secondary->draw_cs));
2229          assert(tu_cs_is_empty(&secondary->draw_epilogue_cs));
2230
2231          for (uint32_t j = 0; j < secondary->cs.bo_count; j++) {
2232             tu_bo_list_add(&cmd->bo_list, secondary->cs.bos[j],
2233                            MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2234          }
2235
2236          tu_cs_emit_call(&cmd->cs, &secondary->cs);
2237       }
2238    }
2239    cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
2240 }
2241
2242 VkResult
2243 tu_CreateCommandPool(VkDevice _device,
2244                      const VkCommandPoolCreateInfo *pCreateInfo,
2245                      const VkAllocationCallbacks *pAllocator,
2246                      VkCommandPool *pCmdPool)
2247 {
2248    TU_FROM_HANDLE(tu_device, device, _device);
2249    struct tu_cmd_pool *pool;
2250
2251    pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2252                     VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2253    if (pool == NULL)
2254       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2255
2256    if (pAllocator)
2257       pool->alloc = *pAllocator;
2258    else
2259       pool->alloc = device->alloc;
2260
2261    list_inithead(&pool->cmd_buffers);
2262    list_inithead(&pool->free_cmd_buffers);
2263
2264    pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2265
2266    *pCmdPool = tu_cmd_pool_to_handle(pool);
2267
2268    return VK_SUCCESS;
2269 }
2270
2271 void
2272 tu_DestroyCommandPool(VkDevice _device,
2273                       VkCommandPool commandPool,
2274                       const VkAllocationCallbacks *pAllocator)
2275 {
2276    TU_FROM_HANDLE(tu_device, device, _device);
2277    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2278
2279    if (!pool)
2280       return;
2281
2282    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2283                             &pool->cmd_buffers, pool_link)
2284    {
2285       tu_cmd_buffer_destroy(cmd_buffer);
2286    }
2287
2288    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2289                             &pool->free_cmd_buffers, pool_link)
2290    {
2291       tu_cmd_buffer_destroy(cmd_buffer);
2292    }
2293
2294    vk_free2(&device->alloc, pAllocator, pool);
2295 }
2296
2297 VkResult
2298 tu_ResetCommandPool(VkDevice device,
2299                     VkCommandPool commandPool,
2300                     VkCommandPoolResetFlags flags)
2301 {
2302    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2303    VkResult result;
2304
2305    list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2306                        pool_link)
2307    {
2308       result = tu_reset_cmd_buffer(cmd_buffer);
2309       if (result != VK_SUCCESS)
2310          return result;
2311    }
2312
2313    return VK_SUCCESS;
2314 }
2315
2316 void
2317 tu_TrimCommandPool(VkDevice device,
2318                    VkCommandPool commandPool,
2319                    VkCommandPoolTrimFlags flags)
2320 {
2321    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2322
2323    if (!pool)
2324       return;
2325
2326    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2327                             &pool->free_cmd_buffers, pool_link)
2328    {
2329       tu_cmd_buffer_destroy(cmd_buffer);
2330    }
2331 }
2332
2333 void
2334 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2335                       const VkRenderPassBeginInfo *pRenderPassBegin,
2336                       VkSubpassContents contents)
2337 {
2338    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2339    TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2340    TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
2341
2342    cmd->state.pass = pass;
2343    cmd->state.subpass = pass->subpasses;
2344    cmd->state.framebuffer = fb;
2345
2346    tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
2347    tu_cmd_prepare_tile_store_ib(cmd);
2348
2349    tu_emit_load_clear(cmd, pRenderPassBegin);
2350
2351    tu6_emit_zs(cmd, cmd->state.subpass, &cmd->draw_cs);
2352    tu6_emit_mrt(cmd, cmd->state.subpass, &cmd->draw_cs);
2353    tu6_emit_msaa(&cmd->draw_cs, cmd->state.subpass->samples);
2354    tu6_emit_render_cntl(cmd, cmd->state.subpass, &cmd->draw_cs, false);
2355
2356    /* note: use_hw_binning only checks tiling config */
2357    if (use_hw_binning(cmd))
2358       cmd->use_vsc_data = true;
2359
2360    for (uint32_t i = 0; i < fb->attachment_count; ++i) {
2361       const struct tu_image_view *iview = fb->attachments[i].attachment;
2362       tu_bo_list_add(&cmd->bo_list, iview->image->bo,
2363                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2364    }
2365
2366    /* Flag input attachment descriptors for re-emission if necessary */
2367    cmd->state.dirty |= TU_CMD_DIRTY_INPUT_ATTACHMENTS;
2368 }
2369
2370 void
2371 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
2372                        const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2373                        const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2374 {
2375    tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2376                          pSubpassBeginInfo->contents);
2377 }
2378
2379 void
2380 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2381 {
2382    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2383    const struct tu_render_pass *pass = cmd->state.pass;
2384    struct tu_cs *cs = &cmd->draw_cs;
2385
2386    const struct tu_subpass *subpass = cmd->state.subpass++;
2387
2388    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
2389
2390    if (subpass->resolve_attachments) {
2391       for (unsigned i = 0; i < subpass->color_count; i++) {
2392          uint32_t a = subpass->resolve_attachments[i].attachment;
2393          if (a == VK_ATTACHMENT_UNUSED)
2394             continue;
2395
2396          tu_store_gmem_attachment(cmd, cs, a,
2397                                     subpass->color_attachments[i].attachment);
2398
2399          if (pass->attachments[a].gmem_offset < 0)
2400             continue;
2401
2402          /* TODO:
2403           * check if the resolved attachment is needed by later subpasses,
2404           * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2405           */
2406          tu_finishme("missing GMEM->GMEM resolve path\n");
2407          tu_emit_load_gmem_attachment(cmd, cs, a);
2408       }
2409    }
2410
2411    tu_cond_exec_end(cs);
2412
2413    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
2414
2415    /* Emit flushes so that input attachments will read the correct value.
2416     * TODO: use subpass dependencies to flush or not
2417     */
2418    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
2419    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
2420
2421    if (subpass->resolve_attachments) {
2422       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2423
2424       for (unsigned i = 0; i < subpass->color_count; i++) {
2425          uint32_t a = subpass->resolve_attachments[i].attachment;
2426          if (a == VK_ATTACHMENT_UNUSED)
2427             continue;
2428
2429          tu6_emit_sysmem_resolve(cmd, cs, a,
2430                                  subpass->color_attachments[i].attachment);
2431       }
2432
2433       tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
2434    }
2435
2436    tu_cond_exec_end(cs);
2437
2438    /* subpass->input_count > 0 then texture cache invalidate is likely to be needed */
2439    if (cmd->state.subpass->input_count)
2440       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2441
2442    /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2443    tu6_emit_zs(cmd, cmd->state.subpass, cs);
2444    tu6_emit_mrt(cmd, cmd->state.subpass, cs);
2445    tu6_emit_msaa(cs, cmd->state.subpass->samples);
2446    tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, false);
2447
2448    /* Flag input attachment descriptors for re-emission if necessary */
2449    cmd->state.dirty |= TU_CMD_DIRTY_INPUT_ATTACHMENTS;
2450 }
2451
2452 void
2453 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
2454                    const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2455                    const VkSubpassEndInfoKHR *pSubpassEndInfo)
2456 {
2457    tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2458 }
2459
2460 struct tu_draw_info
2461 {
2462    /**
2463     * Number of vertices.
2464     */
2465    uint32_t count;
2466
2467    /**
2468     * Index of the first vertex.
2469     */
2470    int32_t vertex_offset;
2471
2472    /**
2473     * First instance id.
2474     */
2475    uint32_t first_instance;
2476
2477    /**
2478     * Number of instances.
2479     */
2480    uint32_t instance_count;
2481
2482    /**
2483     * First index (indexed draws only).
2484     */
2485    uint32_t first_index;
2486
2487    /**
2488     * Whether it's an indexed draw.
2489     */
2490    bool indexed;
2491
2492    /**
2493     * Indirect draw parameters resource.
2494     */
2495    struct tu_buffer *indirect;
2496    uint64_t indirect_offset;
2497    uint32_t stride;
2498
2499    /**
2500     * Draw count parameters resource.
2501     */
2502    struct tu_buffer *count_buffer;
2503    uint64_t count_buffer_offset;
2504
2505    /**
2506     * Stream output parameters resource.
2507     */
2508    struct tu_buffer *streamout_buffer;
2509    uint64_t streamout_buffer_offset;
2510 };
2511
2512 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2513 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2514 #define ENABLE_NON_GMEM (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_SYSMEM)
2515
2516 enum tu_draw_state_group_id
2517 {
2518    TU_DRAW_STATE_PROGRAM,
2519    TU_DRAW_STATE_PROGRAM_BINNING,
2520    TU_DRAW_STATE_VI,
2521    TU_DRAW_STATE_VI_BINNING,
2522    TU_DRAW_STATE_VP,
2523    TU_DRAW_STATE_RAST,
2524    TU_DRAW_STATE_DS,
2525    TU_DRAW_STATE_BLEND,
2526    TU_DRAW_STATE_VS_CONST,
2527    TU_DRAW_STATE_FS_CONST,
2528    TU_DRAW_STATE_DESC_SETS,
2529    TU_DRAW_STATE_DESC_SETS_GMEM,
2530    TU_DRAW_STATE_DESC_SETS_LOAD,
2531    TU_DRAW_STATE_VS_PARAMS,
2532
2533    TU_DRAW_STATE_COUNT,
2534 };
2535
2536 struct tu_draw_state_group
2537 {
2538    enum tu_draw_state_group_id id;
2539    uint32_t enable_mask;
2540    struct tu_cs_entry ib;
2541 };
2542
2543 static inline uint32_t
2544 tu6_stage2opcode(gl_shader_stage type)
2545 {
2546    switch (type) {
2547    case MESA_SHADER_VERTEX:
2548    case MESA_SHADER_TESS_CTRL:
2549    case MESA_SHADER_TESS_EVAL:
2550    case MESA_SHADER_GEOMETRY:
2551       return CP_LOAD_STATE6_GEOM;
2552    case MESA_SHADER_FRAGMENT:
2553    case MESA_SHADER_COMPUTE:
2554    case MESA_SHADER_KERNEL:
2555       return CP_LOAD_STATE6_FRAG;
2556    default:
2557       unreachable("bad shader type");
2558    }
2559 }
2560
2561 static inline enum a6xx_state_block
2562 tu6_stage2shadersb(gl_shader_stage type)
2563 {
2564    switch (type) {
2565    case MESA_SHADER_VERTEX:
2566       return SB6_VS_SHADER;
2567    case MESA_SHADER_FRAGMENT:
2568       return SB6_FS_SHADER;
2569    case MESA_SHADER_COMPUTE:
2570    case MESA_SHADER_KERNEL:
2571       return SB6_CS_SHADER;
2572    default:
2573       unreachable("bad shader type");
2574       return ~0;
2575    }
2576 }
2577
2578 static void
2579 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2580                      struct tu_descriptor_state *descriptors_state,
2581                      gl_shader_stage type,
2582                      uint32_t *push_constants)
2583 {
2584    const struct tu_program_descriptor_linkage *link =
2585       &pipeline->program.link[type];
2586    const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2587
2588    if (link->push_consts.count > 0) {
2589       unsigned num_units = link->push_consts.count;
2590       unsigned offset = link->push_consts.lo;
2591       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_units * 4);
2592       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
2593             CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2594             CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2595             CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2596             CP_LOAD_STATE6_0_NUM_UNIT(num_units));
2597       tu_cs_emit(cs, 0);
2598       tu_cs_emit(cs, 0);
2599       for (unsigned i = 0; i < num_units * 4; i++)
2600          tu_cs_emit(cs, push_constants[i + offset * 4]);
2601    }
2602
2603    for (uint32_t i = 0; i < state->num_enabled; i++) {
2604       uint32_t size = state->range[i].end - state->range[i].start;
2605       uint32_t offset = state->range[i].start;
2606
2607       /* and even if the start of the const buffer is before
2608        * first_immediate, the end may not be:
2609        */
2610       size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2611
2612       if (size == 0)
2613          continue;
2614
2615       /* things should be aligned to vec4: */
2616       debug_assert((state->range[i].offset % 16) == 0);
2617       debug_assert((size % 16) == 0);
2618       debug_assert((offset % 16) == 0);
2619
2620       /* Dig out the descriptor from the descriptor state and read the VA from
2621        * it.
2622        */
2623       assert(state->range[i].bindless);
2624       uint32_t *base = state->range[i].bindless_base == MAX_SETS ?
2625          descriptors_state->dynamic_descriptors :
2626          descriptors_state->sets[state->range[i].bindless_base]->mapped_ptr;
2627       unsigned block = state->range[i].block;
2628       /* If the block in the shader here is in the dynamic descriptor set, it
2629        * is an index into the dynamic descriptor set which is combined from
2630        * dynamic descriptors and input attachments on-the-fly, and we don't
2631        * have access to it here. Instead we work backwards to get the index
2632        * into dynamic_descriptors.
2633        */
2634       if (state->range[i].bindless_base == MAX_SETS)
2635          block -= pipeline->layout->input_attachment_count;
2636       uint32_t *desc = base + block * A6XX_TEX_CONST_DWORDS;
2637       uint64_t va = desc[0] | ((uint64_t)(desc[1] & A6XX_UBO_1_BASE_HI__MASK) << 32);
2638       assert(va);
2639
2640       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2641       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2642             CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2643             CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2644             CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2645             CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2646       tu_cs_emit_qw(cs, va + offset);
2647    }
2648 }
2649
2650 static struct tu_cs_entry
2651 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2652                 const struct tu_pipeline *pipeline,
2653                 struct tu_descriptor_state *descriptors_state,
2654                 gl_shader_stage type)
2655 {
2656    struct tu_cs cs;
2657    tu_cs_begin_sub_stream(&cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
2658
2659    tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2660
2661    return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2662 }
2663
2664 static VkResult
2665 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
2666                    const struct tu_draw_info *draw,
2667                    struct tu_cs_entry *entry)
2668 {
2669    /* TODO: fill out more than just base instance */
2670    const struct tu_program_descriptor_linkage *link =
2671       &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
2672    const struct ir3_const_state *const_state = &link->const_state;
2673    struct tu_cs cs;
2674
2675    if (const_state->offsets.driver_param >= link->constlen) {
2676       *entry = (struct tu_cs_entry) {};
2677       return VK_SUCCESS;
2678    }
2679
2680    VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 8, &cs);
2681    if (result != VK_SUCCESS)
2682       return result;
2683
2684    tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
2685    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(const_state->offsets.driver_param) |
2686          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2687          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2688          CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
2689          CP_LOAD_STATE6_0_NUM_UNIT(1));
2690    tu_cs_emit(&cs, 0);
2691    tu_cs_emit(&cs, 0);
2692
2693    STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
2694
2695    tu_cs_emit(&cs, 0);
2696    tu_cs_emit(&cs, 0);
2697    tu_cs_emit(&cs, draw->first_instance);
2698    tu_cs_emit(&cs, 0);
2699
2700    *entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2701    return VK_SUCCESS;
2702 }
2703
2704 static VkResult
2705 tu6_emit_descriptor_sets(struct tu_cmd_buffer *cmd,
2706                          const struct tu_pipeline *pipeline,
2707                          VkPipelineBindPoint bind_point,
2708                          struct tu_cs_entry *entry,
2709                          bool gmem)
2710 {
2711    struct tu_cs *draw_state = &cmd->sub_cs;
2712    struct tu_pipeline_layout *layout = pipeline->layout;
2713    struct tu_descriptor_state *descriptors_state =
2714       tu_get_descriptors_state(cmd, bind_point);
2715    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2716    const uint32_t *input_attachment_idx =
2717       pipeline->program.input_attachment_idx;
2718    uint32_t num_dynamic_descs = layout->dynamic_offset_count +
2719       layout->input_attachment_count;
2720    struct ts_cs_memory dynamic_desc_set;
2721    VkResult result;
2722
2723    if (num_dynamic_descs > 0) {
2724       /* allocate and fill out dynamic descriptor set */
2725       result = tu_cs_alloc(draw_state, num_dynamic_descs,
2726                            A6XX_TEX_CONST_DWORDS, &dynamic_desc_set);
2727       if (result != VK_SUCCESS)
2728          return result;
2729
2730       memcpy(dynamic_desc_set.map, descriptors_state->input_attachments,
2731              layout->input_attachment_count * A6XX_TEX_CONST_DWORDS * 4);
2732
2733       if (gmem) {
2734          /* Patch input attachments to refer to GMEM instead */
2735          for (unsigned i = 0; i < layout->input_attachment_count; i++) {
2736             uint32_t *dst =
2737                &dynamic_desc_set.map[A6XX_TEX_CONST_DWORDS * i];
2738
2739             /* The compiler has already laid out input_attachment_idx in the
2740              * final order of input attachments, so there's no need to go
2741              * through the pipeline layout finding input attachments.
2742              */
2743             unsigned attachment_idx = input_attachment_idx[i];
2744
2745             /* It's possible for the pipeline layout to include an input
2746              * attachment which doesn't actually exist for the current
2747              * subpass. Of course, this is only valid so long as the pipeline
2748              * doesn't try to actually load that attachment. Just skip
2749              * patching in that scenario to avoid out-of-bounds accesses.
2750              */
2751             if (attachment_idx >= cmd->state.subpass->input_count)
2752                continue;
2753
2754             uint32_t a = cmd->state.subpass->input_attachments[attachment_idx].attachment;
2755             const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
2756
2757             assert(att->gmem_offset >= 0);
2758
2759             dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
2760             dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
2761             dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
2762             dst[2] |=
2763                A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
2764                A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
2765             dst[3] = 0;
2766             dst[4] = cmd->device->physical_device->gmem_base + att->gmem_offset;
2767             dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
2768             for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2769                dst[i] = 0;
2770
2771             if (cmd->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
2772                tu_finishme("patch input attachment pitch for secondary cmd buffer");
2773          }
2774       }
2775
2776       memcpy(dynamic_desc_set.map + layout->input_attachment_count * A6XX_TEX_CONST_DWORDS,
2777              descriptors_state->dynamic_descriptors,
2778              layout->dynamic_offset_count * A6XX_TEX_CONST_DWORDS * 4);
2779    }
2780
2781    uint32_t sp_bindless_base_reg, hlsq_bindless_base_reg;
2782    uint32_t hlsq_update_value;
2783    switch (bind_point) {
2784    case VK_PIPELINE_BIND_POINT_GRAPHICS:
2785       sp_bindless_base_reg = REG_A6XX_SP_BINDLESS_BASE(0);
2786       hlsq_bindless_base_reg = REG_A6XX_HLSQ_BINDLESS_BASE(0);
2787       hlsq_update_value = 0x7c000;
2788       break;
2789    case VK_PIPELINE_BIND_POINT_COMPUTE:
2790       sp_bindless_base_reg = REG_A6XX_SP_CS_BINDLESS_BASE(0);
2791       hlsq_bindless_base_reg = REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
2792       hlsq_update_value = 0x3e00;
2793       break;
2794    default:
2795       unreachable("bad bind point");
2796    }
2797
2798    /* Be careful here to *not* refer to the pipeline, so that if only the
2799     * pipeline changes we don't have to emit this again (except if there are
2800     * dynamic descriptors in the pipeline layout). This means always emitting
2801     * all the valid descriptors, which means that we always have to put the
2802     * dynamic descriptor in the driver-only slot at the end
2803     */
2804    uint32_t num_user_sets = util_last_bit(descriptors_state->valid);
2805    uint32_t num_sets = num_user_sets;
2806    if (num_dynamic_descs > 0) {
2807       num_user_sets = MAX_SETS;
2808       num_sets = num_user_sets + 1;
2809    }
2810
2811    unsigned regs[2] = { sp_bindless_base_reg, hlsq_bindless_base_reg };
2812
2813    struct tu_cs cs;
2814    result = tu_cs_begin_sub_stream(draw_state, ARRAY_SIZE(regs) * (1 + num_sets * 2) + 2, &cs);
2815    if (result != VK_SUCCESS)
2816       return result;
2817
2818    if (num_sets > 0) {
2819       for (unsigned i = 0; i < ARRAY_SIZE(regs); i++) {
2820          tu_cs_emit_pkt4(&cs, regs[i], num_sets * 2);
2821          for (unsigned j = 0; j < num_user_sets; j++) {
2822             if (descriptors_state->valid & (1 << j)) {
2823                /* magic | 3 copied from the blob */
2824                tu_cs_emit_qw(&cs, descriptors_state->sets[j]->va | 3);
2825             } else {
2826                tu_cs_emit_qw(&cs, 0 | 3);
2827             }
2828          }
2829          if (num_dynamic_descs > 0) {
2830             tu_cs_emit_qw(&cs, dynamic_desc_set.iova | 3);
2831          }
2832       }
2833
2834       tu_cs_emit_regs(&cs, A6XX_HLSQ_UPDATE_CNTL(hlsq_update_value));
2835    }
2836
2837    *entry = tu_cs_end_sub_stream(draw_state, &cs);
2838    return VK_SUCCESS;
2839 }
2840
2841 static void
2842 tu6_emit_streamout(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
2843 {
2844    struct tu_streamout_state *tf = &cmd->state.pipeline->streamout;
2845
2846    for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2847       struct tu_buffer *buf = cmd->state.streamout_buf.buffers[i];
2848       if (!buf)
2849          continue;
2850
2851       uint32_t offset;
2852       offset = cmd->state.streamout_buf.offsets[i];
2853
2854       tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_BASE(i, .bo = buf->bo,
2855                                                      .bo_offset = buf->bo_offset));
2856       tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_SIZE(i, buf->size));
2857
2858       if (cmd->state.streamout_reset & (1 << i)) {
2859          offset *= tf->stride[i];
2860
2861          tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_OFFSET(i, offset));
2862          cmd->state.streamout_reset &= ~(1  << i);
2863       } else {
2864          tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
2865          tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i)) |
2866                         CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
2867                         CP_MEM_TO_REG_0_CNT(0));
2868          tu_cs_emit_qw(cs, cmd->scratch_bo.iova +
2869                            ctrl_offset(flush_base[i].offset));
2870       }
2871
2872       tu_cs_emit_regs(cs, A6XX_VPC_SO_FLUSH_BASE(i, .bo = &cmd->scratch_bo,
2873                                                     .bo_offset =
2874                                                        ctrl_offset(flush_base[i])));
2875    }
2876
2877    if (cmd->state.streamout_enabled) {
2878       tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
2879       tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
2880       tu_cs_emit(cs, tf->vpc_so_buf_cntl);
2881       tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(0));
2882       tu_cs_emit(cs, tf->ncomp[0]);
2883       tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(1));
2884       tu_cs_emit(cs, tf->ncomp[1]);
2885       tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(2));
2886       tu_cs_emit(cs, tf->ncomp[2]);
2887       tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(3));
2888       tu_cs_emit(cs, tf->ncomp[3]);
2889       tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
2890       tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
2891       for (unsigned i = 0; i < tf->prog_count; i++) {
2892          tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
2893          tu_cs_emit(cs, tf->prog[i]);
2894       }
2895    } else {
2896       tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
2897       tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
2898       tu_cs_emit(cs, 0);
2899       tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
2900       tu_cs_emit(cs, 0);
2901    }
2902 }
2903
2904 static VkResult
2905 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
2906                      struct tu_cs *cs,
2907                      const struct tu_draw_info *draw)
2908 {
2909    const struct tu_pipeline *pipeline = cmd->state.pipeline;
2910    const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
2911    struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
2912    uint32_t draw_state_group_count = 0;
2913    VkResult result;
2914
2915    struct tu_descriptor_state *descriptors_state =
2916       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2917
2918    /* TODO lrz */
2919
2920    tu_cs_emit_regs(cs,
2921                    A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart =
2922                                             pipeline->ia.primitive_restart && draw->indexed));
2923
2924    if (cmd->state.dirty &
2925           (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
2926        (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
2927       tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
2928                             dynamic->line_width);
2929    }
2930
2931    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
2932        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2933       tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
2934                                     dynamic->stencil_compare_mask.back);
2935    }
2936
2937    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
2938        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2939       tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
2940                                   dynamic->stencil_write_mask.back);
2941    }
2942
2943    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
2944        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2945       tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
2946                                  dynamic->stencil_reference.back);
2947    }
2948
2949    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2950        (pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
2951       tu6_emit_viewport(cs, &cmd->state.dynamic.viewport.viewports[0]);
2952    }
2953
2954    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_SCISSOR) &&
2955        (pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
2956       tu6_emit_scissor(cs, &cmd->state.dynamic.scissor.scissors[0]);
2957    }
2958
2959    if (cmd->state.dirty &
2960        (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
2961       for (uint32_t i = 0; i < pipeline->vi.count; i++) {
2962          const uint32_t binding = pipeline->vi.bindings[i];
2963          const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
2964          const VkDeviceSize offset = buf->bo_offset +
2965                                      cmd->state.vb.offsets[binding];
2966          const VkDeviceSize size =
2967             offset < buf->size ? buf->size - offset : 0;
2968
2969          tu_cs_emit_regs(cs,
2970                          A6XX_VFD_FETCH_BASE(i, .bo = buf->bo, .bo_offset = offset),
2971                          A6XX_VFD_FETCH_SIZE(i, size));
2972       }
2973    }
2974
2975    if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2976       draw_state_groups[draw_state_group_count++] =
2977          (struct tu_draw_state_group) {
2978             .id = TU_DRAW_STATE_PROGRAM,
2979             .enable_mask = ENABLE_DRAW,
2980             .ib = pipeline->program.state_ib,
2981          };
2982       draw_state_groups[draw_state_group_count++] =
2983          (struct tu_draw_state_group) {
2984             .id = TU_DRAW_STATE_PROGRAM_BINNING,
2985             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
2986             .ib = pipeline->program.binning_state_ib,
2987          };
2988       draw_state_groups[draw_state_group_count++] =
2989          (struct tu_draw_state_group) {
2990             .id = TU_DRAW_STATE_VI,
2991             .enable_mask = ENABLE_DRAW,
2992             .ib = pipeline->vi.state_ib,
2993          };
2994       draw_state_groups[draw_state_group_count++] =
2995          (struct tu_draw_state_group) {
2996             .id = TU_DRAW_STATE_VI_BINNING,
2997             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
2998             .ib = pipeline->vi.binning_state_ib,
2999          };
3000       draw_state_groups[draw_state_group_count++] =
3001          (struct tu_draw_state_group) {
3002             .id = TU_DRAW_STATE_VP,
3003             .enable_mask = ENABLE_ALL,
3004             .ib = pipeline->vp.state_ib,
3005          };
3006       draw_state_groups[draw_state_group_count++] =
3007          (struct tu_draw_state_group) {
3008             .id = TU_DRAW_STATE_RAST,
3009             .enable_mask = ENABLE_ALL,
3010             .ib = pipeline->rast.state_ib,
3011          };
3012       draw_state_groups[draw_state_group_count++] =
3013          (struct tu_draw_state_group) {
3014             .id = TU_DRAW_STATE_DS,
3015             .enable_mask = ENABLE_ALL,
3016             .ib = pipeline->ds.state_ib,
3017          };
3018       draw_state_groups[draw_state_group_count++] =
3019          (struct tu_draw_state_group) {
3020             .id = TU_DRAW_STATE_BLEND,
3021             .enable_mask = ENABLE_ALL,
3022             .ib = pipeline->blend.state_ib,
3023          };
3024    }
3025
3026    if (cmd->state.dirty &
3027          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_PUSH_CONSTANTS)) {
3028       draw_state_groups[draw_state_group_count++] =
3029          (struct tu_draw_state_group) {
3030             .id = TU_DRAW_STATE_VS_CONST,
3031             .enable_mask = ENABLE_ALL,
3032             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
3033          };
3034       draw_state_groups[draw_state_group_count++] =
3035          (struct tu_draw_state_group) {
3036             .id = TU_DRAW_STATE_FS_CONST,
3037             .enable_mask = ENABLE_DRAW,
3038             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
3039          };
3040    }
3041
3042    if (cmd->state.dirty & TU_CMD_DIRTY_STREAMOUT_BUFFERS)
3043       tu6_emit_streamout(cmd, cs);
3044
3045    /* If there are any any dynamic descriptors, then we may need to re-emit
3046     * them after every pipeline change in case the number of input attachments
3047     * changes. We also always need to re-emit after a pipeline change if there
3048     * are any input attachments, because the input attachment index comes from
3049     * the pipeline. Finally, it can also happen that the subpass changes
3050     * without the pipeline changing, in which case the GMEM descriptors need
3051     * to be patched differently.
3052     *
3053     * TODO: We could probably be clever and avoid re-emitting state on
3054     * pipeline changes if the number of input attachments is always 0. We
3055     * could also only re-emit dynamic state.
3056     */
3057    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS ||
3058        ((pipeline->layout->dynamic_offset_count +
3059          pipeline->layout->input_attachment_count > 0) &&
3060         cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) ||
3061        (pipeline->layout->input_attachment_count > 0 &&
3062         cmd->state.dirty & TU_CMD_DIRTY_INPUT_ATTACHMENTS)) {
3063       struct tu_cs_entry desc_sets, desc_sets_gmem;
3064       bool need_gmem_desc_set = pipeline->layout->input_attachment_count > 0;
3065
3066       result = tu6_emit_descriptor_sets(cmd, pipeline,
3067                                         VK_PIPELINE_BIND_POINT_GRAPHICS,
3068                                         &desc_sets, false);
3069       if (result != VK_SUCCESS)
3070          return result;
3071
3072       draw_state_groups[draw_state_group_count++] =
3073          (struct tu_draw_state_group) {
3074             .id = TU_DRAW_STATE_DESC_SETS,
3075             .enable_mask = need_gmem_desc_set ? ENABLE_NON_GMEM : ENABLE_ALL,
3076             .ib = desc_sets,
3077          };
3078
3079       if (need_gmem_desc_set) {
3080          result = tu6_emit_descriptor_sets(cmd, pipeline,
3081                                            VK_PIPELINE_BIND_POINT_GRAPHICS,
3082                                            &desc_sets_gmem, true);
3083          if (result != VK_SUCCESS)
3084             return result;
3085
3086          draw_state_groups[draw_state_group_count++] =
3087             (struct tu_draw_state_group) {
3088                .id = TU_DRAW_STATE_DESC_SETS_GMEM,
3089                .enable_mask = CP_SET_DRAW_STATE__0_GMEM,
3090                .ib = desc_sets_gmem,
3091             };
3092       }
3093
3094       /* We need to reload the descriptors every time the descriptor sets
3095        * change. However, the commands we send only depend on the pipeline
3096        * because the whole point is to cache descriptors which are used by the
3097        * pipeline. There's a problem here, in that the firmware has an
3098        * "optimization" which skips executing groups that are set to the same
3099        * value as the last draw. This means that if the descriptor sets change
3100        * but not the pipeline, we'd try to re-execute the same buffer which
3101        * the firmware would ignore and we wouldn't pre-load the new
3102        * descriptors. The blob seems to re-emit the LOAD_STATE group whenever
3103        * the descriptor sets change, which we emulate here by copying the
3104        * pre-prepared buffer.
3105        */
3106       const struct tu_cs_entry *load_entry = &pipeline->load_state.state_ib;
3107       if (load_entry->size > 0) {
3108          struct tu_cs load_cs;
3109          result = tu_cs_begin_sub_stream(&cmd->sub_cs, load_entry->size, &load_cs);
3110          if (result != VK_SUCCESS)
3111             return result;
3112          tu_cs_emit_array(&load_cs,
3113                           (uint32_t *)((char  *)load_entry->bo->map + load_entry->offset),
3114                           load_entry->size / 4);
3115          struct tu_cs_entry load_copy = tu_cs_end_sub_stream(&cmd->sub_cs, &load_cs);
3116
3117          draw_state_groups[draw_state_group_count++] =
3118             (struct tu_draw_state_group) {
3119                .id = TU_DRAW_STATE_DESC_SETS_LOAD,
3120                /* The blob seems to not enable this for binning, even when
3121                 * resources would actually be used in the binning shader.
3122                 * Presumably the overhead of prefetching the resources isn't
3123                 * worth it.
3124                 */
3125                .enable_mask = ENABLE_DRAW,
3126                .ib = load_copy,
3127             };
3128       }
3129    }
3130
3131    struct tu_cs_entry vs_params;
3132    result = tu6_emit_vs_params(cmd, draw, &vs_params);
3133    if (result != VK_SUCCESS)
3134       return result;
3135
3136    draw_state_groups[draw_state_group_count++] =
3137       (struct tu_draw_state_group) {
3138          .id = TU_DRAW_STATE_VS_PARAMS,
3139          .enable_mask = ENABLE_ALL,
3140          .ib = vs_params,
3141       };
3142
3143    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
3144    for (uint32_t i = 0; i < draw_state_group_count; i++) {
3145       const struct tu_draw_state_group *group = &draw_state_groups[i];
3146       debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
3147       uint32_t cp_set_draw_state =
3148          CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
3149          group->enable_mask |
3150          CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
3151       uint64_t iova;
3152       if (group->ib.size) {
3153          iova = group->ib.bo->iova + group->ib.offset;
3154       } else {
3155          cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
3156          iova = 0;
3157       }
3158
3159       tu_cs_emit(cs, cp_set_draw_state);
3160       tu_cs_emit_qw(cs, iova);
3161    }
3162
3163    tu_cs_sanity_check(cs);
3164
3165    /* track BOs */
3166    if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
3167       for (uint32_t i = 0; i < MAX_VBS; i++) {
3168          const struct tu_buffer *buf = cmd->state.vb.buffers[i];
3169          if (buf)
3170             tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
3171       }
3172    }
3173    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3174       unsigned i;
3175       for_each_bit(i, descriptors_state->valid) {
3176          struct tu_descriptor_set *set = descriptors_state->sets[i];
3177          for (unsigned j = 0; j < set->layout->buffer_count; ++j) {
3178             if (set->buffers[j]) {
3179                tu_bo_list_add(&cmd->bo_list, set->buffers[j],
3180                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3181             }
3182          }
3183          if (set->size > 0) {
3184             tu_bo_list_add(&cmd->bo_list, &set->pool->bo,
3185                            MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
3186          }
3187       }
3188    }
3189    if (cmd->state.dirty & TU_CMD_DIRTY_STREAMOUT_BUFFERS) {
3190       for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
3191          const struct tu_buffer *buf = cmd->state.streamout_buf.buffers[i];
3192          if (buf) {
3193             tu_bo_list_add(&cmd->bo_list, buf->bo,
3194                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3195          }
3196       }
3197    }
3198
3199    /* There are too many graphics dirty bits to list here, so just list the
3200     * bits to preserve instead. The only things not emitted here are
3201     * compute-related state.
3202     */
3203    cmd->state.dirty &= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS;
3204
3205    /* Fragment shader state overwrites compute shader state, so flag the
3206     * compute pipeline for re-emit.
3207     */
3208    cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
3209    return VK_SUCCESS;
3210 }
3211
3212 static void
3213 tu6_emit_draw_indirect(struct tu_cmd_buffer *cmd,
3214                      struct tu_cs *cs,
3215                      const struct tu_draw_info *draw)
3216 {
3217    const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3218    bool has_gs = cmd->state.pipeline->active_stages &
3219                  VK_SHADER_STAGE_GEOMETRY_BIT;
3220
3221    tu_cs_emit_regs(cs,
3222                    A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
3223                    A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
3224
3225    if (draw->indexed) {
3226       const enum a4xx_index_size index_size =
3227          tu6_index_size(cmd->state.index_type);
3228       const uint32_t index_bytes =
3229          (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3230       const struct tu_buffer *index_buf = cmd->state.index_buffer;
3231       unsigned max_indicies =
3232          (index_buf->size - cmd->state.index_offset) / index_bytes;
3233
3234       const uint32_t cp_draw_indx =
3235          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3236          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3237          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3238          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
3239          COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
3240
3241       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_INDIRECT, 6);
3242       tu_cs_emit(cs, cp_draw_indx);
3243       tu_cs_emit_qw(cs, index_buf->bo->iova + cmd->state.index_offset);
3244       tu_cs_emit(cs, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
3245       tu_cs_emit_qw(cs, draw->indirect->bo->iova + draw->indirect_offset);
3246    } else {
3247       const uint32_t cp_draw_indx =
3248          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3249          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3250          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
3251          COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
3252
3253       tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT, 3);
3254       tu_cs_emit(cs, cp_draw_indx);
3255       tu_cs_emit_qw(cs, draw->indirect->bo->iova + draw->indirect_offset);
3256    }
3257
3258    tu_bo_list_add(&cmd->bo_list, draw->indirect->bo, MSM_SUBMIT_BO_READ);
3259 }
3260
3261 static void
3262 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
3263                      struct tu_cs *cs,
3264                      const struct tu_draw_info *draw)
3265 {
3266
3267    const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3268    bool has_gs = cmd->state.pipeline->active_stages &
3269                  VK_SHADER_STAGE_GEOMETRY_BIT;
3270
3271    tu_cs_emit_regs(cs,
3272                    A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
3273                    A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
3274
3275    /* TODO hw binning */
3276    if (draw->indexed) {
3277       const enum a4xx_index_size index_size =
3278          tu6_index_size(cmd->state.index_type);
3279       const uint32_t index_bytes =
3280          (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3281       const struct tu_buffer *buf = cmd->state.index_buffer;
3282       const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
3283                                   index_bytes * draw->first_index;
3284       const uint32_t size = index_bytes * draw->count;
3285
3286       const uint32_t cp_draw_indx =
3287          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3288          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3289          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3290          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
3291          COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
3292
3293       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
3294       tu_cs_emit(cs, cp_draw_indx);
3295       tu_cs_emit(cs, draw->instance_count);
3296       tu_cs_emit(cs, draw->count);
3297       tu_cs_emit(cs, 0x0); /* XXX */
3298       tu_cs_emit_qw(cs, buf->bo->iova + offset);
3299       tu_cs_emit(cs, size);
3300    } else {
3301       const uint32_t cp_draw_indx =
3302          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3303          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3304          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
3305          COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
3306
3307       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
3308       tu_cs_emit(cs, cp_draw_indx);
3309       tu_cs_emit(cs, draw->instance_count);
3310       tu_cs_emit(cs, draw->count);
3311    }
3312 }
3313
3314 static void
3315 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
3316 {
3317    struct tu_cs *cs = &cmd->draw_cs;
3318    VkResult result;
3319
3320    result = tu6_bind_draw_states(cmd, cs, draw);
3321    if (result != VK_SUCCESS) {
3322       cmd->record_result = result;
3323       return;
3324    }
3325
3326    if (draw->indirect)
3327       tu6_emit_draw_indirect(cmd, cs, draw);
3328    else
3329       tu6_emit_draw_direct(cmd, cs, draw);
3330
3331    if (cmd->state.streamout_enabled) {
3332       for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
3333          if (cmd->state.streamout_enabled & (1 << i))
3334             tu6_emit_event_write(cmd, cs, FLUSH_SO_0 + i, false);
3335       }
3336    }
3337
3338    cmd->wait_for_idle = true;
3339
3340    tu_cs_sanity_check(cs);
3341 }
3342
3343 void
3344 tu_CmdDraw(VkCommandBuffer commandBuffer,
3345            uint32_t vertexCount,
3346            uint32_t instanceCount,
3347            uint32_t firstVertex,
3348            uint32_t firstInstance)
3349 {
3350    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3351    struct tu_draw_info info = {};
3352
3353    info.count = vertexCount;
3354    info.instance_count = instanceCount;
3355    info.first_instance = firstInstance;
3356    info.vertex_offset = firstVertex;
3357
3358    tu_draw(cmd_buffer, &info);
3359 }
3360
3361 void
3362 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3363                   uint32_t indexCount,
3364                   uint32_t instanceCount,
3365                   uint32_t firstIndex,
3366                   int32_t vertexOffset,
3367                   uint32_t firstInstance)
3368 {
3369    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3370    struct tu_draw_info info = {};
3371
3372    info.indexed = true;
3373    info.count = indexCount;
3374    info.instance_count = instanceCount;
3375    info.first_index = firstIndex;
3376    info.vertex_offset = vertexOffset;
3377    info.first_instance = firstInstance;
3378
3379    tu_draw(cmd_buffer, &info);
3380 }
3381
3382 void
3383 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3384                    VkBuffer _buffer,
3385                    VkDeviceSize offset,
3386                    uint32_t drawCount,
3387                    uint32_t stride)
3388 {
3389    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3390    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3391    struct tu_draw_info info = {};
3392
3393    info.count = drawCount;
3394    info.indirect = buffer;
3395    info.indirect_offset = offset;
3396    info.stride = stride;
3397
3398    tu_draw(cmd_buffer, &info);
3399 }
3400
3401 void
3402 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3403                           VkBuffer _buffer,
3404                           VkDeviceSize offset,
3405                           uint32_t drawCount,
3406                           uint32_t stride)
3407 {
3408    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3409    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3410    struct tu_draw_info info = {};
3411
3412    info.indexed = true;
3413    info.count = drawCount;
3414    info.indirect = buffer;
3415    info.indirect_offset = offset;
3416    info.stride = stride;
3417
3418    tu_draw(cmd_buffer, &info);
3419 }
3420
3421 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer,
3422                                     uint32_t instanceCount,
3423                                     uint32_t firstInstance,
3424                                     VkBuffer _counterBuffer,
3425                                     VkDeviceSize counterBufferOffset,
3426                                     uint32_t counterOffset,
3427                                     uint32_t vertexStride)
3428 {
3429    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3430    TU_FROM_HANDLE(tu_buffer, buffer, _counterBuffer);
3431
3432    struct tu_draw_info info = {};
3433
3434    info.instance_count = instanceCount;
3435    info.first_instance = firstInstance;
3436    info.streamout_buffer = buffer;
3437    info.streamout_buffer_offset = counterBufferOffset;
3438    info.stride = vertexStride;
3439
3440    tu_draw(cmd_buffer, &info);
3441 }
3442
3443 struct tu_dispatch_info
3444 {
3445    /**
3446     * Determine the layout of the grid (in block units) to be used.
3447     */
3448    uint32_t blocks[3];
3449
3450    /**
3451     * A starting offset for the grid. If unaligned is set, the offset
3452     * must still be aligned.
3453     */
3454    uint32_t offsets[3];
3455    /**
3456     * Whether it's an unaligned compute dispatch.
3457     */
3458    bool unaligned;
3459
3460    /**
3461     * Indirect compute parameters resource.
3462     */
3463    struct tu_buffer *indirect;
3464    uint64_t indirect_offset;
3465 };
3466
3467 static void
3468 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3469                               const struct tu_dispatch_info *info)
3470 {
3471    gl_shader_stage type = MESA_SHADER_COMPUTE;
3472    const struct tu_program_descriptor_linkage *link =
3473       &pipeline->program.link[type];
3474    const struct ir3_const_state *const_state = &link->const_state;
3475    uint32_t offset = const_state->offsets.driver_param;
3476
3477    if (link->constlen <= offset)
3478       return;
3479
3480    if (!info->indirect) {
3481       uint32_t driver_params[IR3_DP_CS_COUNT] = {
3482          [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
3483          [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
3484          [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
3485          [IR3_DP_LOCAL_GROUP_SIZE_X] = pipeline->compute.local_size[0],
3486          [IR3_DP_LOCAL_GROUP_SIZE_Y] = pipeline->compute.local_size[1],
3487          [IR3_DP_LOCAL_GROUP_SIZE_Z] = pipeline->compute.local_size[2],
3488       };
3489
3490       uint32_t num_consts = MIN2(const_state->num_driver_params,
3491                                  (link->constlen - offset) * 4);
3492       /* push constants */
3493       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
3494       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
3495                  CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3496                  CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3497                  CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3498                  CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
3499       tu_cs_emit(cs, 0);
3500       tu_cs_emit(cs, 0);
3501       uint32_t i;
3502       for (i = 0; i < num_consts; i++)
3503          tu_cs_emit(cs, driver_params[i]);
3504    } else {
3505       tu_finishme("Indirect driver params");
3506    }
3507 }
3508
3509 static void
3510 tu_dispatch(struct tu_cmd_buffer *cmd,
3511             const struct tu_dispatch_info *info)
3512 {
3513    struct tu_cs *cs = &cmd->cs;
3514    struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3515    struct tu_descriptor_state *descriptors_state =
3516       &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3517    VkResult result;
3518
3519    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3520       tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3521
3522    struct tu_cs_entry ib;
3523
3524    ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3525    if (ib.size)
3526       tu_cs_emit_ib(cs, &ib);
3527
3528    tu_emit_compute_driver_params(cs, pipeline, info);
3529
3530    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS) {
3531       result = tu6_emit_descriptor_sets(cmd, pipeline,
3532                                         VK_PIPELINE_BIND_POINT_COMPUTE, &ib,
3533                                         false);
3534       if (result != VK_SUCCESS) {
3535          cmd->record_result = result;
3536          return;
3537       }
3538
3539       /* track BOs */
3540       unsigned i;
3541       for_each_bit(i, descriptors_state->valid) {
3542          struct tu_descriptor_set *set = descriptors_state->sets[i];
3543          for (unsigned j = 0; j < set->layout->buffer_count; ++j) {
3544             if (set->buffers[j]) {
3545                tu_bo_list_add(&cmd->bo_list, set->buffers[j],
3546                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3547             }
3548          }
3549
3550          if (set->size > 0) {
3551             tu_bo_list_add(&cmd->bo_list, &set->pool->bo,
3552                            MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
3553          }
3554       }
3555    }
3556
3557    if (ib.size)
3558       tu_cs_emit_ib(cs, &ib);
3559
3560    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS)
3561       tu_cs_emit_ib(cs, &pipeline->load_state.state_ib);
3562
3563    cmd->state.dirty &=
3564       ~(TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS | TU_CMD_DIRTY_COMPUTE_PIPELINE);
3565
3566    /* Compute shader state overwrites fragment shader state, so we flag the
3567     * graphics pipeline for re-emit.
3568     */
3569    cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
3570
3571    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3572    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
3573
3574    const uint32_t *local_size = pipeline->compute.local_size;
3575    const uint32_t *num_groups = info->blocks;
3576    tu_cs_emit_regs(cs,
3577                    A6XX_HLSQ_CS_NDRANGE_0(.kerneldim = 3,
3578                                           .localsizex = local_size[0] - 1,
3579                                           .localsizey = local_size[1] - 1,
3580                                           .localsizez = local_size[2] - 1),
3581                    A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x = local_size[0] * num_groups[0]),
3582                    A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x = 0),
3583                    A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y = local_size[1] * num_groups[1]),
3584                    A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y = 0),
3585                    A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z = local_size[2] * num_groups[2]),
3586                    A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z = 0));
3587
3588    tu_cs_emit_regs(cs,
3589                    A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3590                    A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3591                    A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3592
3593    if (info->indirect) {
3594       uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3595
3596       tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3597                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3598
3599       tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3600       tu_cs_emit(cs, 0x00000000);
3601       tu_cs_emit_qw(cs, iova);
3602       tu_cs_emit(cs,
3603                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3604                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3605                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3606    } else {
3607       tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3608       tu_cs_emit(cs, 0x00000000);
3609       tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3610       tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3611       tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3612    }
3613
3614    tu_cs_emit_wfi(cs);
3615
3616    tu6_emit_cache_flush(cmd, cs);
3617 }
3618
3619 void
3620 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
3621                    uint32_t base_x,
3622                    uint32_t base_y,
3623                    uint32_t base_z,
3624                    uint32_t x,
3625                    uint32_t y,
3626                    uint32_t z)
3627 {
3628    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3629    struct tu_dispatch_info info = {};
3630
3631    info.blocks[0] = x;
3632    info.blocks[1] = y;
3633    info.blocks[2] = z;
3634
3635    info.offsets[0] = base_x;
3636    info.offsets[1] = base_y;
3637    info.offsets[2] = base_z;
3638    tu_dispatch(cmd_buffer, &info);
3639 }
3640
3641 void
3642 tu_CmdDispatch(VkCommandBuffer commandBuffer,
3643                uint32_t x,
3644                uint32_t y,
3645                uint32_t z)
3646 {
3647    tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3648 }
3649
3650 void
3651 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
3652                        VkBuffer _buffer,
3653                        VkDeviceSize offset)
3654 {
3655    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3656    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3657    struct tu_dispatch_info info = {};
3658
3659    info.indirect = buffer;
3660    info.indirect_offset = offset;
3661
3662    tu_dispatch(cmd_buffer, &info);
3663 }
3664
3665 void
3666 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3667 {
3668    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3669
3670    tu_cs_end(&cmd_buffer->draw_cs);
3671    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
3672
3673    if (use_sysmem_rendering(cmd_buffer))
3674       tu_cmd_render_sysmem(cmd_buffer);
3675    else
3676       tu_cmd_render_tiles(cmd_buffer);
3677
3678    /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3679       rendered */
3680    tu_cs_discard_entries(&cmd_buffer->draw_cs);
3681    tu_cs_begin(&cmd_buffer->draw_cs);
3682    tu_cs_discard_entries(&cmd_buffer->draw_epilogue_cs);
3683    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
3684
3685    cmd_buffer->state.pass = NULL;
3686    cmd_buffer->state.subpass = NULL;
3687    cmd_buffer->state.framebuffer = NULL;
3688 }
3689
3690 void
3691 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
3692                      const VkSubpassEndInfoKHR *pSubpassEndInfo)
3693 {
3694    tu_CmdEndRenderPass(commandBuffer);
3695 }
3696
3697 struct tu_barrier_info
3698 {
3699    uint32_t eventCount;
3700    const VkEvent *pEvents;
3701    VkPipelineStageFlags srcStageMask;
3702 };
3703
3704 static void
3705 tu_barrier(struct tu_cmd_buffer *cmd,
3706            uint32_t memoryBarrierCount,
3707            const VkMemoryBarrier *pMemoryBarriers,
3708            uint32_t bufferMemoryBarrierCount,
3709            const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3710            uint32_t imageMemoryBarrierCount,
3711            const VkImageMemoryBarrier *pImageMemoryBarriers,
3712            const struct tu_barrier_info *info)
3713 {
3714    /* renderpass case is only for subpass self-dependencies
3715     * which means syncing the render output with texture cache
3716     * note: only the CACHE_INVALIDATE is needed in GMEM mode
3717     * and in sysmem mode we might not need either color/depth flush
3718     */
3719    if (cmd->state.pass) {
3720       tu6_emit_event_write(cmd, &cmd->draw_cs, PC_CCU_FLUSH_COLOR_TS, true);
3721       tu6_emit_event_write(cmd, &cmd->draw_cs, PC_CCU_FLUSH_DEPTH_TS, true);
3722       tu6_emit_event_write(cmd, &cmd->draw_cs, CACHE_INVALIDATE, false);
3723       return;
3724    }
3725 }
3726
3727 void
3728 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3729                       VkPipelineStageFlags srcStageMask,
3730                       VkPipelineStageFlags dstStageMask,
3731                       VkDependencyFlags dependencyFlags,
3732                       uint32_t memoryBarrierCount,
3733                       const VkMemoryBarrier *pMemoryBarriers,
3734                       uint32_t bufferMemoryBarrierCount,
3735                       const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3736                       uint32_t imageMemoryBarrierCount,
3737                       const VkImageMemoryBarrier *pImageMemoryBarriers)
3738 {
3739    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3740    struct tu_barrier_info info;
3741
3742    info.eventCount = 0;
3743    info.pEvents = NULL;
3744    info.srcStageMask = srcStageMask;
3745
3746    tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3747               bufferMemoryBarrierCount, pBufferMemoryBarriers,
3748               imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3749 }
3750
3751 static void
3752 write_event(struct tu_cmd_buffer *cmd, struct tu_event *event, unsigned value)
3753 {
3754    struct tu_cs *cs = &cmd->cs;
3755
3756    tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_WRITE);
3757
3758    /* TODO: any flush required before/after ? */
3759
3760    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
3761    tu_cs_emit_qw(cs, event->bo.iova); /* ADDR_LO/HI */
3762    tu_cs_emit(cs, value);
3763 }
3764
3765 void
3766 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3767                VkEvent _event,
3768                VkPipelineStageFlags stageMask)
3769 {
3770    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3771    TU_FROM_HANDLE(tu_event, event, _event);
3772
3773    write_event(cmd, event, 1);
3774 }
3775
3776 void
3777 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3778                  VkEvent _event,
3779                  VkPipelineStageFlags stageMask)
3780 {
3781    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3782    TU_FROM_HANDLE(tu_event, event, _event);
3783
3784    write_event(cmd, event, 0);
3785 }
3786
3787 void
3788 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3789                  uint32_t eventCount,
3790                  const VkEvent *pEvents,
3791                  VkPipelineStageFlags srcStageMask,
3792                  VkPipelineStageFlags dstStageMask,
3793                  uint32_t memoryBarrierCount,
3794                  const VkMemoryBarrier *pMemoryBarriers,
3795                  uint32_t bufferMemoryBarrierCount,
3796                  const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3797                  uint32_t imageMemoryBarrierCount,
3798                  const VkImageMemoryBarrier *pImageMemoryBarriers)
3799 {
3800    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3801    struct tu_cs *cs = &cmd->cs;
3802
3803    /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
3804
3805    for (uint32_t i = 0; i < eventCount; i++) {
3806       TU_FROM_HANDLE(tu_event, event, pEvents[i]);
3807
3808       tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_READ);
3809
3810       tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
3811       tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
3812                      CP_WAIT_REG_MEM_0_POLL_MEMORY);
3813       tu_cs_emit_qw(cs, event->bo.iova); /* POLL_ADDR_LO/HI */
3814       tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1));
3815       tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u));
3816       tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3817    }
3818 }
3819
3820 void
3821 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3822 {
3823    /* No-op */
3824 }