2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
33 #include "vk_format.h"
38 tu_bo_list_init(struct tu_bo_list
*list
)
40 list
->count
= list
->capacity
= 0;
41 list
->bo_infos
= NULL
;
45 tu_bo_list_destroy(struct tu_bo_list
*list
)
51 tu_bo_list_reset(struct tu_bo_list
*list
)
57 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 tu_bo_list_add_info(struct tu_bo_list
*list
,
61 const struct drm_msm_gem_submit_bo
*bo_info
)
63 assert(bo_info
->handle
!= 0);
65 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
66 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
67 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
68 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
73 /* grow list->bo_infos if needed */
74 if (list
->count
== list
->capacity
) {
75 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
76 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
77 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
79 return TU_BO_LIST_FAILED
;
80 list
->bo_infos
= new_bo_infos
;
81 list
->capacity
= new_capacity
;
84 list
->bo_infos
[list
->count
] = *bo_info
;
89 tu_bo_list_add(struct tu_bo_list
*list
,
90 const struct tu_bo
*bo
,
93 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
95 .handle
= bo
->gem_handle
,
101 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
103 for (uint32_t i
= 0; i
< other
->count
; i
++) {
104 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
105 return VK_ERROR_OUT_OF_HOST_MEMORY
;
112 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
114 enum vgt_event_type event
)
116 bool need_seqno
= false;
121 case PC_CCU_FLUSH_DEPTH_TS
:
122 case PC_CCU_FLUSH_COLOR_TS
:
123 case PC_CCU_RESOLVE_TS
:
130 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
131 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
133 tu_cs_emit_qw(cs
, global_iova(cmd
, seqno_dummy
));
139 tu6_emit_flushes(struct tu_cmd_buffer
*cmd_buffer
,
141 enum tu_cmd_flush_bits flushes
)
143 /* Experiments show that invalidating CCU while it still has data in it
144 * doesn't work, so make sure to always flush before invalidating in case
145 * any data remains that hasn't yet been made available through a barrier.
146 * However it does seem to work for UCHE.
148 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_COLOR
|
149 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
))
150 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_COLOR_TS
);
151 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
152 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
))
153 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_DEPTH_TS
);
154 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_COLOR
)
155 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_COLOR
);
156 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
)
157 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_DEPTH
);
158 if (flushes
& TU_CMD_FLAG_CACHE_FLUSH
)
159 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_FLUSH_TS
);
160 if (flushes
& TU_CMD_FLAG_CACHE_INVALIDATE
)
161 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_INVALIDATE
);
162 if (flushes
& TU_CMD_FLAG_WAIT_MEM_WRITES
)
163 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
164 if (flushes
& TU_CMD_FLAG_WAIT_FOR_IDLE
)
166 if (flushes
& TU_CMD_FLAG_WAIT_FOR_ME
)
167 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
170 /* "Normal" cache flushes, that don't require any special handling */
173 tu_emit_cache_flush(struct tu_cmd_buffer
*cmd_buffer
,
176 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.cache
.flush_bits
);
177 cmd_buffer
->state
.cache
.flush_bits
= 0;
180 /* Renderpass cache flushes */
183 tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
186 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.renderpass_cache
.flush_bits
);
187 cmd_buffer
->state
.renderpass_cache
.flush_bits
= 0;
190 /* Cache flushes for things that use the color/depth read/write path (i.e.
191 * blits and draws). This deals with changing CCU state as well as the usual
196 tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
198 enum tu_cmd_ccu_state ccu_state
)
200 enum tu_cmd_flush_bits flushes
= cmd_buffer
->state
.cache
.flush_bits
;
202 assert(ccu_state
!= TU_CMD_CCU_UNKNOWN
);
204 /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
205 * the CCU may also contain data that we haven't flushed out yet, so we
206 * also need to flush. Also, in order to program RB_CCU_CNTL, we need to
207 * emit a WFI as it isn't pipelined.
209 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
210 if (cmd_buffer
->state
.ccu_state
!= TU_CMD_CCU_GMEM
) {
212 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
213 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
214 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
215 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
216 TU_CMD_FLAG_CCU_FLUSH_DEPTH
);
219 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
220 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
221 TU_CMD_FLAG_WAIT_FOR_IDLE
;
222 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
223 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
224 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
225 TU_CMD_FLAG_WAIT_FOR_IDLE
);
228 tu6_emit_flushes(cmd_buffer
, cs
, flushes
);
229 cmd_buffer
->state
.cache
.flush_bits
= 0;
231 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
232 struct tu_physical_device
*phys_dev
= cmd_buffer
->device
->physical_device
;
234 A6XX_RB_CCU_CNTL(.offset
=
235 ccu_state
== TU_CMD_CCU_GMEM
?
236 phys_dev
->ccu_offset_gmem
:
237 phys_dev
->ccu_offset_bypass
,
238 .gmem
= ccu_state
== TU_CMD_CCU_GMEM
));
239 cmd_buffer
->state
.ccu_state
= ccu_state
;
244 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
245 const struct tu_subpass
*subpass
,
248 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
250 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
251 if (a
== VK_ATTACHMENT_UNUSED
) {
253 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
254 A6XX_RB_DEPTH_BUFFER_PITCH(0),
255 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
256 A6XX_RB_DEPTH_BUFFER_BASE(0),
257 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
260 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
263 A6XX_GRAS_LRZ_BUFFER_BASE(0),
264 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
265 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
267 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
272 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
273 const struct tu_render_pass_attachment
*attachment
=
274 &cmd
->state
.pass
->attachments
[a
];
275 enum a6xx_depth_format fmt
= tu6_pipe2depth(attachment
->format
);
277 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
278 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
).value
);
279 tu_cs_image_ref(cs
, iview
, 0);
280 tu_cs_emit(cs
, attachment
->gmem_offset
);
283 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
285 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
286 tu_cs_image_flag_ref(cs
, iview
, 0);
289 A6XX_GRAS_LRZ_BUFFER_BASE(0),
290 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
291 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
293 if (attachment
->format
== VK_FORMAT_S8_UINT
) {
294 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 6);
295 tu_cs_emit(cs
, A6XX_RB_STENCIL_INFO(.separate_stencil
= true).value
);
296 tu_cs_image_ref(cs
, iview
, 0);
297 tu_cs_emit(cs
, attachment
->gmem_offset
);
300 A6XX_RB_STENCIL_INFO(0));
305 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
306 const struct tu_subpass
*subpass
,
309 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
311 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
312 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
313 if (a
== VK_ATTACHMENT_UNUSED
)
316 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
318 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
319 tu_cs_emit(cs
, iview
->RB_MRT_BUF_INFO
);
320 tu_cs_image_ref(cs
, iview
, 0);
321 tu_cs_emit(cs
, cmd
->state
.pass
->attachments
[a
].gmem_offset
);
324 A6XX_SP_FS_MRT_REG(i
, .dword
= iview
->SP_FS_MRT_REG
));
326 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i
), 3);
327 tu_cs_image_flag_ref(cs
, iview
, 0);
331 A6XX_RB_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
333 A6XX_SP_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
335 tu_cs_emit_regs(cs
, A6XX_GRAS_MAX_LAYER_INDEX(fb
->layers
- 1));
339 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
341 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
342 bool msaa_disable
= samples
== MSAA_ONE
;
345 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
346 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
347 .msaa_disable
= msaa_disable
));
350 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
351 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
352 .msaa_disable
= msaa_disable
));
355 A6XX_RB_RAS_MSAA_CNTL(samples
),
356 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
357 .msaa_disable
= msaa_disable
));
360 A6XX_RB_MSAA_CNTL(samples
));
364 tu6_emit_bin_size(struct tu_cs
*cs
,
365 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
368 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
373 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
377 /* no flag for RB_BIN_CONTROL2... */
379 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
384 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
385 const struct tu_subpass
*subpass
,
389 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
391 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
393 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
395 uint32_t mrts_ubwc_enable
= 0;
396 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
397 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
398 if (a
== VK_ATTACHMENT_UNUSED
)
401 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
402 if (iview
->ubwc_enabled
)
403 mrts_ubwc_enable
|= 1 << i
;
406 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
408 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
409 if (a
!= VK_ATTACHMENT_UNUSED
) {
410 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
411 if (iview
->ubwc_enabled
)
412 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
415 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
416 * in order to set it correctly for the different subpasses. However,
417 * that means the packets we're emitting also happen during binning. So
418 * we need to guard the write on !BINNING at CP execution time.
420 tu_cs_reserve(cs
, 3 + 4);
421 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
422 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
423 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
424 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
427 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
428 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
429 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
430 tu_cs_emit(cs
, cntl
);
434 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
436 const VkRect2D
*render_area
= &cmd
->state
.render_area
;
437 uint32_t x1
= render_area
->offset
.x
;
438 uint32_t y1
= render_area
->offset
.y
;
439 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
440 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
443 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
444 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
445 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
446 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
450 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
451 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
455 tu6_emit_window_scissor(struct tu_cs
*cs
,
462 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
463 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
466 A6XX_GRAS_2D_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
467 A6XX_GRAS_2D_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
471 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
474 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
477 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
480 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
483 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
487 tu_cs_emit_draw_state(struct tu_cs
*cs
, uint32_t id
, struct tu_draw_state state
)
489 uint32_t enable_mask
;
491 case TU_DRAW_STATE_PROGRAM
:
492 case TU_DRAW_STATE_VI
:
493 case TU_DRAW_STATE_FS_CONST
:
494 /* The blob seems to not enable this (DESC_SETS_LOAD) for binning, even
495 * when resources would actually be used in the binning shader.
496 * Presumably the overhead of prefetching the resources isn't
499 case TU_DRAW_STATE_DESC_SETS_LOAD
:
500 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
501 CP_SET_DRAW_STATE__0_SYSMEM
;
503 case TU_DRAW_STATE_PROGRAM_BINNING
:
504 case TU_DRAW_STATE_VI_BINNING
:
505 enable_mask
= CP_SET_DRAW_STATE__0_BINNING
;
507 case TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
:
508 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
;
510 case TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
:
511 enable_mask
= CP_SET_DRAW_STATE__0_SYSMEM
;
514 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
515 CP_SET_DRAW_STATE__0_SYSMEM
|
516 CP_SET_DRAW_STATE__0_BINNING
;
520 /* We need to reload the descriptors every time the descriptor sets
521 * change. However, the commands we send only depend on the pipeline
522 * because the whole point is to cache descriptors which are used by the
523 * pipeline. There's a problem here, in that the firmware has an
524 * "optimization" which skips executing groups that are set to the same
525 * value as the last draw. This means that if the descriptor sets change
526 * but not the pipeline, we'd try to re-execute the same buffer which
527 * the firmware would ignore and we wouldn't pre-load the new
528 * descriptors. Set the DIRTY bit to avoid this optimization
530 if (id
== TU_DRAW_STATE_DESC_SETS_LOAD
)
531 enable_mask
|= CP_SET_DRAW_STATE__0_DIRTY
;
533 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(state
.size
) |
535 CP_SET_DRAW_STATE__0_GROUP_ID(id
) |
536 COND(!state
.size
, CP_SET_DRAW_STATE__0_DISABLE
));
537 tu_cs_emit_qw(cs
, state
.iova
);
541 use_hw_binning(struct tu_cmd_buffer
*cmd
)
543 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
545 /* XFB commands are emitted for BINNING || SYSMEM, which makes it incompatible
546 * with non-hw binning GMEM rendering. this is required because some of the
547 * XFB commands need to only be executed once
549 if (cmd
->state
.xfb_used
)
552 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
555 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
558 return (fb
->tile_count
.width
* fb
->tile_count
.height
) > 2;
562 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
564 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
567 /* can't fit attachments into gmem */
568 if (!cmd
->state
.pass
->gmem_pixels
)
571 if (cmd
->state
.framebuffer
->layers
> 1)
581 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
583 uint32_t tx
, uint32_t ty
, uint32_t pipe
, uint32_t slot
)
585 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
587 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
588 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
590 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
591 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
593 const uint32_t x1
= fb
->tile0
.width
* tx
;
594 const uint32_t y1
= fb
->tile0
.height
* ty
;
595 const uint32_t x2
= x1
+ fb
->tile0
.width
- 1;
596 const uint32_t y2
= y1
+ fb
->tile0
.height
- 1;
597 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
598 tu6_emit_window_offset(cs
, x1
, y1
);
600 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
602 if (use_hw_binning(cmd
)) {
603 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
605 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
608 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5_OFFSET
, 4);
609 tu_cs_emit(cs
, fb
->pipe_sizes
[pipe
] |
610 CP_SET_BIN_DATA5_0_VSC_N(slot
));
611 tu_cs_emit(cs
, pipe
* cmd
->vsc_draw_strm_pitch
);
612 tu_cs_emit(cs
, pipe
* 4);
613 tu_cs_emit(cs
, pipe
* cmd
->vsc_prim_strm_pitch
);
615 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
618 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
621 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
624 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
630 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
635 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
636 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
637 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
639 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.render_area
);
643 tu6_emit_sysmem_resolves(struct tu_cmd_buffer
*cmd
,
645 const struct tu_subpass
*subpass
)
647 if (subpass
->resolve_attachments
) {
648 /* From the documentation for vkCmdNextSubpass, section 7.4 "Render Pass
651 * End-of-subpass multisample resolves are treated as color
652 * attachment writes for the purposes of synchronization. That is,
653 * they are considered to execute in the
654 * VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage and
655 * their writes are synchronized with
656 * VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT. Synchronization between
657 * rendering within a subpass and any resolve operations at the end
658 * of the subpass occurs automatically, without need for explicit
659 * dependencies or pipeline barriers. However, if the resolve
660 * attachment is also used in a different subpass, an explicit
661 * dependency is needed.
663 * We use the CP_BLIT path for sysmem resolves, which is really a
664 * transfer command, so we have to manually flush similar to the gmem
665 * resolve case. However, a flush afterwards isn't needed because of the
666 * last sentence and the fact that we're in sysmem mode.
668 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
);
669 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
671 /* Wait for the flushes to land before using the 2D engine */
674 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
675 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
676 if (a
== VK_ATTACHMENT_UNUSED
)
679 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
680 subpass
->color_attachments
[i
].attachment
);
686 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
688 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
689 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
691 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
692 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
693 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
694 CP_SET_DRAW_STATE__0_GROUP_ID(0));
695 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
696 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
698 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
701 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
702 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
704 tu6_emit_blit_scissor(cmd
, cs
, true);
706 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
707 if (pass
->attachments
[a
].gmem_offset
>= 0)
708 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
711 if (subpass
->resolve_attachments
) {
712 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
713 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
714 if (a
!= VK_ATTACHMENT_UNUSED
)
715 tu_store_gmem_attachment(cmd
, cs
, a
,
716 subpass
->color_attachments
[i
].attachment
);
722 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
724 struct tu_device
*dev
= cmd
->device
;
725 const struct tu_physical_device
*phys_dev
= dev
->physical_device
;
727 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
729 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(
738 .gfx_shared_const
= true,
739 .cs_shared_const
= true,
740 .gfx_bindless
= 0x1f,
741 .cs_bindless
= 0x1f));
744 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
745 cmd
->state
.ccu_state
= TU_CMD_CCU_SYSMEM
;
746 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
747 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
748 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
749 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
750 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
751 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
752 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
753 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
755 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
756 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
757 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
758 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
759 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
760 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
761 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_SHARED_CONSTS
, 0);
762 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
763 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
764 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
765 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
766 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
767 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
769 /* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */
770 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
771 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
772 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
774 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
776 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
778 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
779 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
780 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
781 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
782 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
783 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
784 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
785 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
786 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
787 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
788 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
790 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
792 tu_cs_emit_regs(cs
, A6XX_VPC_POINT_COORD_INVERT(false));
793 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
795 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(true));
797 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
798 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
800 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
801 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
803 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
805 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
807 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
808 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
809 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
810 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
811 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
812 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
813 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
814 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
815 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
817 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
819 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
821 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
823 /* we don't use this yet.. probably best to disable.. */
824 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
825 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
826 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
827 CP_SET_DRAW_STATE__0_GROUP_ID(0));
828 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
829 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
832 A6XX_SP_HS_CTRL_REG0(0));
835 A6XX_SP_GS_CTRL_REG0(0));
838 A6XX_GRAS_LRZ_CNTL(0));
841 A6XX_RB_LRZ_CNTL(0));
844 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &dev
->global_bo
,
845 .bo_offset
= gb_offset(border_color
)));
847 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &dev
->global_bo
,
848 .bo_offset
= gb_offset(border_color
)));
851 * use vsc pitches from the largest values used so far with this device
852 * if there hasn't been overflow, there will already be a scratch bo
853 * allocated for these sizes
855 * if overflow is detected, the stream size is increased by 2x
857 mtx_lock(&dev
->vsc_pitch_mtx
);
859 struct tu6_global
*global
= dev
->global_bo
.map
;
861 uint32_t vsc_draw_overflow
= global
->vsc_draw_overflow
;
862 uint32_t vsc_prim_overflow
= global
->vsc_prim_overflow
;
864 if (vsc_draw_overflow
>= dev
->vsc_draw_strm_pitch
)
865 dev
->vsc_draw_strm_pitch
= (dev
->vsc_draw_strm_pitch
- VSC_PAD
) * 2 + VSC_PAD
;
867 if (vsc_prim_overflow
>= dev
->vsc_prim_strm_pitch
)
868 dev
->vsc_prim_strm_pitch
= (dev
->vsc_prim_strm_pitch
- VSC_PAD
) * 2 + VSC_PAD
;
870 cmd
->vsc_prim_strm_pitch
= dev
->vsc_prim_strm_pitch
;
871 cmd
->vsc_draw_strm_pitch
= dev
->vsc_draw_strm_pitch
;
873 mtx_unlock(&dev
->vsc_pitch_mtx
);
875 struct tu_bo
*vsc_bo
;
876 uint32_t size0
= cmd
->vsc_prim_strm_pitch
* MAX_VSC_PIPES
+
877 cmd
->vsc_draw_strm_pitch
* MAX_VSC_PIPES
;
879 tu_get_scratch_bo(dev
, size0
+ MAX_VSC_PIPES
* 4, &vsc_bo
);
882 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo
= vsc_bo
, .bo_offset
= size0
));
884 A6XX_VSC_PRIM_STRM_ADDRESS(.bo
= vsc_bo
));
886 A6XX_VSC_DRAW_STRM_ADDRESS(.bo
= vsc_bo
,
887 .bo_offset
= cmd
->vsc_prim_strm_pitch
* MAX_VSC_PIPES
));
889 tu_bo_list_add(&cmd
->bo_list
, vsc_bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
891 tu_cs_sanity_check(cs
);
895 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
897 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
900 A6XX_VSC_BIN_SIZE(.width
= fb
->tile0
.width
,
901 .height
= fb
->tile0
.height
));
904 A6XX_VSC_BIN_COUNT(.nx
= fb
->tile_count
.width
,
905 .ny
= fb
->tile_count
.height
));
907 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
908 tu_cs_emit_array(cs
, fb
->pipe_config
, 32);
911 A6XX_VSC_PRIM_STRM_PITCH(cmd
->vsc_prim_strm_pitch
),
912 A6XX_VSC_PRIM_STRM_LIMIT(cmd
->vsc_prim_strm_pitch
- VSC_PAD
));
915 A6XX_VSC_DRAW_STRM_PITCH(cmd
->vsc_draw_strm_pitch
),
916 A6XX_VSC_DRAW_STRM_LIMIT(cmd
->vsc_draw_strm_pitch
- VSC_PAD
));
920 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
922 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
923 const uint32_t used_pipe_count
=
924 fb
->pipe_count
.width
* fb
->pipe_count
.height
;
926 for (int i
= 0; i
< used_pipe_count
; i
++) {
927 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
928 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
929 CP_COND_WRITE5_0_WRITE_MEMORY
);
930 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i
)));
931 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
932 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_draw_strm_pitch
- VSC_PAD
));
933 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
934 tu_cs_emit_qw(cs
, global_iova(cmd
, vsc_draw_overflow
));
935 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(cmd
->vsc_draw_strm_pitch
));
937 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
938 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
939 CP_COND_WRITE5_0_WRITE_MEMORY
);
940 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i
)));
941 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
942 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_prim_strm_pitch
- VSC_PAD
));
943 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
944 tu_cs_emit_qw(cs
, global_iova(cmd
, vsc_prim_overflow
));
945 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(cmd
->vsc_prim_strm_pitch
));
948 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
952 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
954 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
955 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
957 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
959 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
960 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
962 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
965 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
971 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
973 update_vsc_pipe(cmd
, cs
);
976 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
979 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
981 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
982 tu_cs_emit(cs
, UNK_2C
);
985 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
988 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
990 /* emit IB to binning drawcmds: */
991 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
993 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
994 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
995 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
996 CP_SET_DRAW_STATE__0_GROUP_ID(0));
997 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
998 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1000 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1001 tu_cs_emit(cs
, UNK_2D
);
1003 /* This flush is probably required because the VSC, which produces the
1004 * visibility stream, is a client of UCHE, whereas the CP needs to read the
1005 * visibility stream (without caching) to do draw skipping. The
1006 * WFI+WAIT_FOR_ME combination guarantees that the binning commands
1007 * submitted are finished before reading the VSC regs (in
1008 * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
1011 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
);
1015 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1017 emit_vsc_overflow_test(cmd
, cs
);
1019 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1020 tu_cs_emit(cs
, 0x0);
1022 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1023 tu_cs_emit(cs
, 0x0);
1026 static struct tu_draw_state
1027 tu_emit_input_attachments(struct tu_cmd_buffer
*cmd
,
1028 const struct tu_subpass
*subpass
,
1031 /* note: we can probably emit input attachments just once for the whole
1032 * renderpass, this would avoid emitting both sysmem/gmem versions
1034 * emit two texture descriptors for each input, as a workaround for
1035 * d24s8, which can be sampled as both float (depth) and integer (stencil)
1036 * tu_shader lowers uint input attachment loads to use the 2nd descriptor
1038 * TODO: a smarter workaround
1041 if (!subpass
->input_count
)
1042 return (struct tu_draw_state
) {};
1044 struct tu_cs_memory texture
;
1045 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, subpass
->input_count
* 2,
1046 A6XX_TEX_CONST_DWORDS
, &texture
);
1047 assert(result
== VK_SUCCESS
);
1049 for (unsigned i
= 0; i
< subpass
->input_count
* 2; i
++) {
1050 uint32_t a
= subpass
->input_attachments
[i
/ 2].attachment
;
1051 if (a
== VK_ATTACHMENT_UNUSED
)
1054 struct tu_image_view
*iview
=
1055 cmd
->state
.framebuffer
->attachments
[a
].attachment
;
1056 const struct tu_render_pass_attachment
*att
=
1057 &cmd
->state
.pass
->attachments
[a
];
1058 uint32_t *dst
= &texture
.map
[A6XX_TEX_CONST_DWORDS
* i
];
1060 memcpy(dst
, iview
->descriptor
, A6XX_TEX_CONST_DWORDS
* 4);
1062 if (i
% 2 == 1 && att
->format
== VK_FORMAT_D24_UNORM_S8_UINT
) {
1063 /* note this works because spec says fb and input attachments
1064 * must use identity swizzle
1066 dst
[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK
|
1067 A6XX_TEX_CONST_0_SWIZ_X__MASK
| A6XX_TEX_CONST_0_SWIZ_Y__MASK
|
1068 A6XX_TEX_CONST_0_SWIZ_Z__MASK
| A6XX_TEX_CONST_0_SWIZ_W__MASK
);
1069 dst
[0] |= A6XX_TEX_CONST_0_FMT(FMT6_S8Z24_UINT
) |
1070 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_Y
) |
1071 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO
) |
1072 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO
) |
1073 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE
);
1079 /* patched for gmem */
1080 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
1081 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
1083 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
1084 A6XX_TEX_CONST_2_PITCH(cmd
->state
.framebuffer
->tile0
.width
* att
->cpp
);
1086 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ att
->gmem_offset
;
1087 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
1088 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
1093 struct tu_draw_state ds
= tu_cs_draw_state(&cmd
->sub_cs
, &cs
, 9);
1095 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_FRAG
, 3);
1096 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1097 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1098 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
1099 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_TEX
) |
1100 CP_LOAD_STATE6_0_NUM_UNIT(subpass
->input_count
* 2));
1101 tu_cs_emit_qw(&cs
, texture
.iova
);
1103 tu_cs_emit_pkt4(&cs
, REG_A6XX_SP_FS_TEX_CONST_LO
, 2);
1104 tu_cs_emit_qw(&cs
, texture
.iova
);
1106 tu_cs_emit_regs(&cs
, A6XX_SP_FS_TEX_COUNT(subpass
->input_count
* 2));
1108 assert(cs
.cur
== cs
.end
); /* validate draw state size */
1114 tu_set_input_attachments(struct tu_cmd_buffer
*cmd
, const struct tu_subpass
*subpass
)
1116 struct tu_cs
*cs
= &cmd
->draw_cs
;
1118 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 6);
1119 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
,
1120 tu_emit_input_attachments(cmd
, subpass
, true));
1121 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
,
1122 tu_emit_input_attachments(cmd
, subpass
, false));
1126 tu_emit_renderpass_begin(struct tu_cmd_buffer
*cmd
,
1127 const VkRenderPassBeginInfo
*info
)
1129 struct tu_cs
*cs
= &cmd
->draw_cs
;
1131 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1133 tu6_emit_blit_scissor(cmd
, cs
, true);
1135 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1136 tu_load_gmem_attachment(cmd
, cs
, i
, false);
1138 tu6_emit_blit_scissor(cmd
, cs
, false);
1140 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1141 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1143 tu_cond_exec_end(cs
);
1145 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1147 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1148 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1150 tu_cond_exec_end(cs
);
1154 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1156 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1158 assert(fb
->width
> 0 && fb
->height
> 0);
1159 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1160 tu6_emit_window_offset(cs
, 0, 0);
1162 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1164 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1166 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1167 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1169 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1170 tu_cs_emit(cs
, 0x0);
1172 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_SYSMEM
);
1174 /* enable stream-out, with sysmem there is only one pass: */
1175 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1177 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1178 tu_cs_emit(cs
, 0x1);
1180 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1181 tu_cs_emit(cs
, 0x0);
1183 tu_cs_sanity_check(cs
);
1187 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1189 /* Do any resolves of the last subpass. These are handled in the
1190 * tile_store_ib in the gmem path.
1192 tu6_emit_sysmem_resolves(cmd
, cs
, cmd
->state
.subpass
);
1194 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1196 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1197 tu_cs_emit(cs
, 0x0);
1199 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1201 tu_cs_sanity_check(cs
);
1205 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1207 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1209 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1213 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1214 tu_cs_emit(cs
, 0x0);
1216 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_GMEM
);
1218 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1219 if (use_hw_binning(cmd
)) {
1220 /* enable stream-out during binning pass: */
1221 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1223 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
,
1224 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1226 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1228 tu6_emit_binning_pass(cmd
, cs
);
1230 /* and disable stream-out for draw pass: */
1231 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(true));
1233 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
,
1234 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1237 A6XX_VFD_MODE_CNTL(0));
1239 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1241 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1243 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1244 tu_cs_emit(cs
, 0x1);
1246 /* no binning pass, so enable stream-out for draw pass:: */
1247 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1249 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
, 0x6000000);
1252 tu_cs_sanity_check(cs
);
1256 tu6_render_tile(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1258 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1260 if (use_hw_binning(cmd
)) {
1261 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1262 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1265 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1267 tu_cs_sanity_check(cs
);
1271 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1273 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1276 A6XX_GRAS_LRZ_CNTL(0));
1278 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1280 tu6_emit_event_write(cmd
, cs
, PC_CCU_RESOLVE_TS
);
1282 tu_cs_sanity_check(cs
);
1286 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1288 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1290 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1293 for (uint32_t py
= 0; py
< fb
->pipe_count
.height
; py
++) {
1294 for (uint32_t px
= 0; px
< fb
->pipe_count
.width
; px
++, pipe
++) {
1295 uint32_t tx1
= px
* fb
->pipe0
.width
;
1296 uint32_t ty1
= py
* fb
->pipe0
.height
;
1297 uint32_t tx2
= MIN2(tx1
+ fb
->pipe0
.width
, fb
->tile_count
.width
);
1298 uint32_t ty2
= MIN2(ty1
+ fb
->pipe0
.height
, fb
->tile_count
.height
);
1300 for (uint32_t ty
= ty1
; ty
< ty2
; ty
++) {
1301 for (uint32_t tx
= tx1
; tx
< tx2
; tx
++, slot
++) {
1302 tu6_emit_tile_select(cmd
, &cmd
->cs
, tx
, ty
, pipe
, slot
);
1303 tu6_render_tile(cmd
, &cmd
->cs
);
1309 tu6_tile_render_end(cmd
, &cmd
->cs
);
1313 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1315 tu6_sysmem_render_begin(cmd
, &cmd
->cs
);
1317 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1319 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1323 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1325 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1326 struct tu_cs sub_cs
;
1329 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1330 if (result
!= VK_SUCCESS
) {
1331 cmd
->record_result
= result
;
1335 /* emit to tile-store sub_cs */
1336 tu6_emit_tile_store(cmd
, &sub_cs
);
1338 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1342 tu_create_cmd_buffer(struct tu_device
*device
,
1343 struct tu_cmd_pool
*pool
,
1344 VkCommandBufferLevel level
,
1345 VkCommandBuffer
*pCommandBuffer
)
1347 struct tu_cmd_buffer
*cmd_buffer
;
1349 cmd_buffer
= vk_object_zalloc(&device
->vk
, NULL
, sizeof(*cmd_buffer
),
1350 VK_OBJECT_TYPE_COMMAND_BUFFER
);
1351 if (cmd_buffer
== NULL
)
1352 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1354 cmd_buffer
->device
= device
;
1355 cmd_buffer
->pool
= pool
;
1356 cmd_buffer
->level
= level
;
1359 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1360 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1363 /* Init the pool_link so we can safely call list_del when we destroy
1364 * the command buffer
1366 list_inithead(&cmd_buffer
->pool_link
);
1367 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1370 tu_bo_list_init(&cmd_buffer
->bo_list
);
1371 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1372 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1373 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1374 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1376 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1378 list_inithead(&cmd_buffer
->upload
.list
);
1384 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1386 list_del(&cmd_buffer
->pool_link
);
1388 tu_cs_finish(&cmd_buffer
->cs
);
1389 tu_cs_finish(&cmd_buffer
->draw_cs
);
1390 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1391 tu_cs_finish(&cmd_buffer
->sub_cs
);
1393 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1394 vk_object_free(&cmd_buffer
->device
->vk
, &cmd_buffer
->pool
->alloc
, cmd_buffer
);
1398 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1400 cmd_buffer
->record_result
= VK_SUCCESS
;
1402 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1403 tu_cs_reset(&cmd_buffer
->cs
);
1404 tu_cs_reset(&cmd_buffer
->draw_cs
);
1405 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1406 tu_cs_reset(&cmd_buffer
->sub_cs
);
1408 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++)
1409 memset(&cmd_buffer
->descriptors
[i
].sets
, 0, sizeof(cmd_buffer
->descriptors
[i
].sets
));
1411 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1413 return cmd_buffer
->record_result
;
1417 tu_AllocateCommandBuffers(VkDevice _device
,
1418 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1419 VkCommandBuffer
*pCommandBuffers
)
1421 TU_FROM_HANDLE(tu_device
, device
, _device
);
1422 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1424 VkResult result
= VK_SUCCESS
;
1427 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1429 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1430 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1431 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1433 list_del(&cmd_buffer
->pool_link
);
1434 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1436 result
= tu_reset_cmd_buffer(cmd_buffer
);
1437 cmd_buffer
->level
= pAllocateInfo
->level
;
1439 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1441 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1442 &pCommandBuffers
[i
]);
1444 if (result
!= VK_SUCCESS
)
1448 if (result
!= VK_SUCCESS
) {
1449 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1452 /* From the Vulkan 1.0.66 spec:
1454 * "vkAllocateCommandBuffers can be used to create multiple
1455 * command buffers. If the creation of any of those command
1456 * buffers fails, the implementation must destroy all
1457 * successfully created command buffer objects from this
1458 * command, set all entries of the pCommandBuffers array to
1459 * NULL and return the error."
1461 memset(pCommandBuffers
, 0,
1462 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1469 tu_FreeCommandBuffers(VkDevice device
,
1470 VkCommandPool commandPool
,
1471 uint32_t commandBufferCount
,
1472 const VkCommandBuffer
*pCommandBuffers
)
1474 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1475 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1478 if (cmd_buffer
->pool
) {
1479 list_del(&cmd_buffer
->pool_link
);
1480 list_addtail(&cmd_buffer
->pool_link
,
1481 &cmd_buffer
->pool
->free_cmd_buffers
);
1483 tu_cmd_buffer_destroy(cmd_buffer
);
1489 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1490 VkCommandBufferResetFlags flags
)
1492 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1493 return tu_reset_cmd_buffer(cmd_buffer
);
1496 /* Initialize the cache, assuming all necessary flushes have happened but *not*
1500 tu_cache_init(struct tu_cache_state
*cache
)
1502 cache
->flush_bits
= 0;
1503 cache
->pending_flush_bits
= TU_CMD_FLAG_ALL_INVALIDATE
;
1507 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1508 const VkCommandBufferBeginInfo
*pBeginInfo
)
1510 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1511 VkResult result
= VK_SUCCESS
;
1513 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1514 /* If the command buffer has already been resetted with
1515 * vkResetCommandBuffer, no need to do it again.
1517 result
= tu_reset_cmd_buffer(cmd_buffer
);
1518 if (result
!= VK_SUCCESS
)
1522 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1523 cmd_buffer
->state
.index_size
= 0xff; /* dirty restart index */
1525 tu_cache_init(&cmd_buffer
->state
.cache
);
1526 tu_cache_init(&cmd_buffer
->state
.renderpass_cache
);
1527 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1529 tu_cs_begin(&cmd_buffer
->cs
);
1530 tu_cs_begin(&cmd_buffer
->draw_cs
);
1531 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1533 /* setup initial configuration into command buffer */
1534 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1535 switch (cmd_buffer
->queue_family_index
) {
1536 case TU_QUEUE_GENERAL
:
1537 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1542 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1543 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1544 assert(pBeginInfo
->pInheritanceInfo
);
1545 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1546 cmd_buffer
->state
.subpass
=
1547 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1549 /* When executing in the middle of another command buffer, the CCU
1552 cmd_buffer
->state
.ccu_state
= TU_CMD_CCU_UNKNOWN
;
1556 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1561 /* Sets vertex buffers to HW binding points. We emit VBs in SDS (so that bin
1562 * rendering can skip over unused state), so we need to collect all the
1563 * bindings together into a single state emit at draw time.
1566 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1567 uint32_t firstBinding
,
1568 uint32_t bindingCount
,
1569 const VkBuffer
*pBuffers
,
1570 const VkDeviceSize
*pOffsets
)
1572 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1574 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1576 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1577 struct tu_buffer
*buf
= tu_buffer_from_handle(pBuffers
[i
]);
1579 cmd
->state
.vb
.buffers
[firstBinding
+ i
] = buf
;
1580 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1582 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1585 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1589 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1591 VkDeviceSize offset
,
1592 VkIndexType indexType
)
1594 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1595 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1599 uint32_t index_size
, index_shift
, restart_index
;
1601 switch (indexType
) {
1602 case VK_INDEX_TYPE_UINT16
:
1603 index_size
= INDEX4_SIZE_16_BIT
;
1605 restart_index
= 0xffff;
1607 case VK_INDEX_TYPE_UINT32
:
1608 index_size
= INDEX4_SIZE_32_BIT
;
1610 restart_index
= 0xffffffff;
1612 case VK_INDEX_TYPE_UINT8_EXT
:
1613 index_size
= INDEX4_SIZE_8_BIT
;
1615 restart_index
= 0xff;
1618 unreachable("invalid VkIndexType");
1621 /* initialize/update the restart index */
1622 if (cmd
->state
.index_size
!= index_size
)
1623 tu_cs_emit_regs(&cmd
->draw_cs
, A6XX_PC_RESTART_INDEX(restart_index
));
1625 assert(buf
->size
>= offset
);
1627 cmd
->state
.index_va
= buf
->bo
->iova
+ buf
->bo_offset
+ offset
;
1628 cmd
->state
.max_index_count
= (buf
->size
- offset
) >> index_shift
;
1629 cmd
->state
.index_size
= index_size
;
1631 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1635 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1636 VkPipelineBindPoint pipelineBindPoint
,
1637 VkPipelineLayout _layout
,
1639 uint32_t descriptorSetCount
,
1640 const VkDescriptorSet
*pDescriptorSets
,
1641 uint32_t dynamicOffsetCount
,
1642 const uint32_t *pDynamicOffsets
)
1644 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1645 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1646 unsigned dyn_idx
= 0;
1648 struct tu_descriptor_state
*descriptors_state
=
1649 tu_get_descriptors_state(cmd
, pipelineBindPoint
);
1651 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1652 unsigned idx
= i
+ firstSet
;
1653 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1655 descriptors_state
->sets
[idx
] = set
;
1657 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1658 /* update the contents of the dynamic descriptor set */
1659 unsigned src_idx
= j
;
1660 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1661 assert(dyn_idx
< dynamicOffsetCount
);
1664 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1666 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1667 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1669 /* Patch the storage/uniform descriptors right away. */
1670 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1671 /* Note: we can assume here that the addition won't roll over and
1672 * change the SIZE field.
1674 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1679 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1680 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1681 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1688 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
1689 if (set
->buffers
[j
]) {
1690 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
1691 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1695 if (set
->size
> 0) {
1696 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
1697 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1700 assert(dyn_idx
== dynamicOffsetCount
);
1702 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
, hlsq_invalidate_value
;
1703 uint64_t addr
[MAX_SETS
+ 1] = {};
1704 struct tu_cs
*cs
, state_cs
;
1706 for (uint32_t i
= 0; i
< MAX_SETS
; i
++) {
1707 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
1709 addr
[i
] = set
->va
| 3;
1712 if (layout
->dynamic_offset_count
) {
1713 /* allocate and fill out dynamic descriptor set */
1714 struct tu_cs_memory dynamic_desc_set
;
1715 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, layout
->dynamic_offset_count
,
1716 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
1717 assert(result
== VK_SUCCESS
);
1719 memcpy(dynamic_desc_set
.map
, descriptors_state
->dynamic_descriptors
,
1720 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
1721 addr
[MAX_SETS
] = dynamic_desc_set
.iova
| 3;
1724 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1725 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
1726 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
1727 hlsq_invalidate_value
= A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(0x1f);
1729 cmd
->state
.desc_sets
= tu_cs_draw_state(&cmd
->sub_cs
, &state_cs
, 24);
1730 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESC_SETS_LOAD
| TU_CMD_DIRTY_SHADER_CONSTS
;
1733 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1735 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
1736 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
1737 hlsq_invalidate_value
= A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(0x1f);
1739 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
1743 tu_cs_emit_pkt4(cs
, sp_bindless_base_reg
, 10);
1744 tu_cs_emit_array(cs
, (const uint32_t*) addr
, 10);
1745 tu_cs_emit_pkt4(cs
, hlsq_bindless_base_reg
, 10);
1746 tu_cs_emit_array(cs
, (const uint32_t*) addr
, 10);
1747 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(.dword
= hlsq_invalidate_value
));
1749 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1750 assert(cs
->cur
== cs
->end
); /* validate draw state size */
1751 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
1752 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets
);
1756 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
1757 uint32_t firstBinding
,
1758 uint32_t bindingCount
,
1759 const VkBuffer
*pBuffers
,
1760 const VkDeviceSize
*pOffsets
,
1761 const VkDeviceSize
*pSizes
)
1763 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1764 struct tu_cs
*cs
= &cmd
->draw_cs
;
1766 /* using COND_REG_EXEC for xfb commands matches the blob behavior
1767 * presumably there isn't any benefit using a draw state when the
1768 * condition is (SYSMEM | BINNING)
1770 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1771 CP_COND_REG_EXEC_0_SYSMEM
|
1772 CP_COND_REG_EXEC_0_BINNING
);
1774 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1775 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
1776 uint64_t iova
= buf
->bo
->iova
+ pOffsets
[i
];
1777 uint32_t size
= buf
->bo
->size
- pOffsets
[i
];
1778 uint32_t idx
= i
+ firstBinding
;
1780 if (pSizes
&& pSizes
[i
] != VK_WHOLE_SIZE
)
1783 /* BUFFER_BASE is 32-byte aligned, add remaining offset to BUFFER_OFFSET */
1784 uint32_t offset
= iova
& 0x1f;
1785 iova
&= ~(uint64_t) 0x1f;
1787 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_BASE(idx
), 3);
1788 tu_cs_emit_qw(cs
, iova
);
1789 tu_cs_emit(cs
, size
+ offset
);
1791 cmd
->state
.streamout_offset
[idx
] = offset
;
1793 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_WRITE
);
1796 tu_cond_exec_end(cs
);
1800 tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1801 uint32_t firstCounterBuffer
,
1802 uint32_t counterBufferCount
,
1803 const VkBuffer
*pCounterBuffers
,
1804 const VkDeviceSize
*pCounterBufferOffsets
)
1806 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1807 struct tu_cs
*cs
= &cmd
->draw_cs
;
1809 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1810 CP_COND_REG_EXEC_0_SYSMEM
|
1811 CP_COND_REG_EXEC_0_BINNING
);
1813 /* TODO: only update offset for active buffers */
1814 for (uint32_t i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++)
1815 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, cmd
->state
.streamout_offset
[i
]));
1817 for (uint32_t i
= 0; i
< counterBufferCount
; i
++) {
1818 uint32_t idx
= firstCounterBuffer
+ i
;
1819 uint32_t offset
= cmd
->state
.streamout_offset
[idx
];
1821 if (!pCounterBuffers
[i
])
1824 TU_FROM_HANDLE(tu_buffer
, buf
, pCounterBuffers
[i
]);
1826 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1828 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1829 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx
)) |
1830 CP_MEM_TO_REG_0_UNK31
|
1831 CP_MEM_TO_REG_0_CNT(1));
1832 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ pCounterBufferOffsets
[i
]);
1835 tu_cs_emit_pkt7(cs
, CP_REG_RMW
, 3);
1836 tu_cs_emit(cs
, CP_REG_RMW_0_DST_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx
)) |
1837 CP_REG_RMW_0_SRC1_ADD
);
1838 tu_cs_emit_qw(cs
, 0xffffffff);
1839 tu_cs_emit_qw(cs
, offset
);
1843 tu_cond_exec_end(cs
);
1846 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1847 uint32_t firstCounterBuffer
,
1848 uint32_t counterBufferCount
,
1849 const VkBuffer
*pCounterBuffers
,
1850 const VkDeviceSize
*pCounterBufferOffsets
)
1852 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1853 struct tu_cs
*cs
= &cmd
->draw_cs
;
1855 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1856 CP_COND_REG_EXEC_0_SYSMEM
|
1857 CP_COND_REG_EXEC_0_BINNING
);
1859 /* TODO: only flush buffers that need to be flushed */
1860 for (uint32_t i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
1861 /* note: FLUSH_BASE is always the same, so it could go in init_hw()? */
1862 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_FLUSH_BASE(i
), 2);
1863 tu_cs_emit_qw(cs
, global_iova(cmd
, flush_base
[i
]));
1864 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
);
1867 for (uint32_t i
= 0; i
< counterBufferCount
; i
++) {
1868 uint32_t idx
= firstCounterBuffer
+ i
;
1869 uint32_t offset
= cmd
->state
.streamout_offset
[idx
];
1871 if (!pCounterBuffers
[i
])
1874 TU_FROM_HANDLE(tu_buffer
, buf
, pCounterBuffers
[i
]);
1876 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_WRITE
);
1878 /* VPC_SO_FLUSH_BASE has dwords counter, but counter should be in bytes */
1879 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1880 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1881 CP_MEM_TO_REG_0_SHIFT_BY_2
|
1883 CP_MEM_TO_REG_0_UNK31
|
1884 CP_MEM_TO_REG_0_CNT(1));
1885 tu_cs_emit_qw(cs
, global_iova(cmd
, flush_base
[idx
]));
1888 tu_cs_emit_pkt7(cs
, CP_REG_RMW
, 3);
1889 tu_cs_emit(cs
, CP_REG_RMW_0_DST_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1890 CP_REG_RMW_0_SRC1_ADD
);
1891 tu_cs_emit_qw(cs
, 0xffffffff);
1892 tu_cs_emit_qw(cs
, -offset
);
1895 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
1896 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1897 CP_REG_TO_MEM_0_CNT(1));
1898 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ pCounterBufferOffsets
[i
]);
1901 tu_cond_exec_end(cs
);
1903 cmd
->state
.xfb_used
= true;
1907 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1908 VkPipelineLayout layout
,
1909 VkShaderStageFlags stageFlags
,
1912 const void *pValues
)
1914 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1915 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1916 cmd
->state
.dirty
|= TU_CMD_DIRTY_SHADER_CONSTS
;
1919 /* Flush everything which has been made available but we haven't actually
1923 tu_flush_all_pending(struct tu_cache_state
*cache
)
1925 cache
->flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
1926 cache
->pending_flush_bits
&= ~TU_CMD_FLAG_ALL_FLUSH
;
1930 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
1932 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1934 /* We currently flush CCU at the end of the command buffer, like
1935 * what the blob does. There's implicit synchronization around every
1936 * vkQueueSubmit, but the kernel only flushes the UCHE, and we don't
1937 * know yet if this command buffer will be the last in the submit so we
1938 * have to defensively flush everything else.
1940 * TODO: We could definitely do better than this, since these flushes
1941 * aren't required by Vulkan, but we'd need kernel support to do that.
1942 * Ideally, we'd like the kernel to flush everything afterwards, so that we
1943 * wouldn't have to do any flushes here, and when submitting multiple
1944 * command buffers there wouldn't be any unnecessary flushes in between.
1946 if (cmd_buffer
->state
.pass
) {
1947 tu_flush_all_pending(&cmd_buffer
->state
.renderpass_cache
);
1948 tu_emit_cache_flush_renderpass(cmd_buffer
, &cmd_buffer
->draw_cs
);
1950 tu_flush_all_pending(&cmd_buffer
->state
.cache
);
1951 cmd_buffer
->state
.cache
.flush_bits
|=
1952 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
1953 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
1954 tu_emit_cache_flush(cmd_buffer
, &cmd_buffer
->cs
);
1957 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->global_bo
,
1958 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1960 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
1961 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
1962 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1965 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
1966 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
1967 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1970 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
1971 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
1972 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1975 tu_cs_end(&cmd_buffer
->cs
);
1976 tu_cs_end(&cmd_buffer
->draw_cs
);
1977 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
1979 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
1981 return cmd_buffer
->record_result
;
1985 tu_cmd_dynamic_state(struct tu_cmd_buffer
*cmd
, uint32_t id
, uint32_t size
)
1989 assert(id
< ARRAY_SIZE(cmd
->state
.dynamic_state
));
1990 cmd
->state
.dynamic_state
[id
] = tu_cs_draw_state(&cmd
->sub_cs
, &cs
, size
);
1992 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
1993 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DYNAMIC
+ id
, cmd
->state
.dynamic_state
[id
]);
1999 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
2000 VkPipelineBindPoint pipelineBindPoint
,
2001 VkPipeline _pipeline
)
2003 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2004 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2006 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2007 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2008 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2011 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
) {
2012 cmd
->state
.compute_pipeline
= pipeline
;
2013 tu_cs_emit_state_ib(&cmd
->cs
, pipeline
->program
.state
);
2017 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
);
2019 cmd
->state
.pipeline
= pipeline
;
2020 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESC_SETS_LOAD
| TU_CMD_DIRTY_SHADER_CONSTS
;
2022 struct tu_cs
*cs
= &cmd
->draw_cs
;
2023 uint32_t mask
= ~pipeline
->dynamic_state_mask
& BITFIELD_MASK(TU_DYNAMIC_STATE_COUNT
);
2026 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (7 + util_bitcount(mask
)));
2027 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state
);
2028 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state
);
2029 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state
);
2030 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state
);
2031 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast_state
);
2032 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS
, pipeline
->ds_state
);
2033 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend_state
);
2034 for_each_bit(i
, mask
)
2035 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
, pipeline
->dynamic_state
[i
]);
2037 /* If the new pipeline requires more VBs than we had previously set up, we
2038 * need to re-emit them in SDS. If it requires the same set or fewer, we
2039 * can just re-use the old SDS.
2041 if (pipeline
->vi
.bindings_used
& ~cmd
->vertex_bindings_set
)
2042 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
2044 /* dynamic linewidth state depends pipeline state's gras_su_cntl
2045 * so the dynamic state ib must be updated when pipeline changes
2047 if (pipeline
->dynamic_state_mask
& BIT(VK_DYNAMIC_STATE_LINE_WIDTH
)) {
2048 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2050 cmd
->state
.dynamic_gras_su_cntl
&= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2051 cmd
->state
.dynamic_gras_su_cntl
|= pipeline
->gras_su_cntl
;
2053 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2058 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2059 uint32_t firstViewport
,
2060 uint32_t viewportCount
,
2061 const VkViewport
*pViewports
)
2063 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2064 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_VIEWPORT
, 18);
2066 assert(firstViewport
== 0 && viewportCount
== 1);
2068 tu6_emit_viewport(&cs
, pViewports
);
2072 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2073 uint32_t firstScissor
,
2074 uint32_t scissorCount
,
2075 const VkRect2D
*pScissors
)
2077 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2078 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_SCISSOR
, 3);
2080 assert(firstScissor
== 0 && scissorCount
== 1);
2082 tu6_emit_scissor(&cs
, pScissors
);
2086 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2088 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2089 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2091 cmd
->state
.dynamic_gras_su_cntl
&= ~A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2092 cmd
->state
.dynamic_gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(lineWidth
/ 2.0f
);
2094 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2098 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2099 float depthBiasConstantFactor
,
2100 float depthBiasClamp
,
2101 float depthBiasSlopeFactor
)
2103 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2104 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BIAS
, 4);
2106 tu6_emit_depth_bias(&cs
, depthBiasConstantFactor
, depthBiasClamp
, depthBiasSlopeFactor
);
2110 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2111 const float blendConstants
[4])
2113 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2114 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_BLEND_CONSTANTS
, 5);
2116 tu_cs_emit_pkt4(&cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2117 tu_cs_emit_array(&cs
, (const uint32_t *) blendConstants
, 4);
2121 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2122 float minDepthBounds
,
2123 float maxDepthBounds
)
2125 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2126 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BOUNDS
, 3);
2128 tu_cs_emit_regs(&cs
,
2129 A6XX_RB_Z_BOUNDS_MIN(minDepthBounds
),
2130 A6XX_RB_Z_BOUNDS_MAX(maxDepthBounds
));
2134 update_stencil_mask(uint32_t *value
, VkStencilFaceFlags face
, uint32_t mask
)
2136 if (face
& VK_STENCIL_FACE_FRONT_BIT
)
2137 *value
= (*value
& 0xff00) | (mask
& 0xff);
2138 if (face
& VK_STENCIL_FACE_BACK_BIT
)
2139 *value
= (*value
& 0xff) | (mask
& 0xff) << 8;
2143 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2144 VkStencilFaceFlags faceMask
,
2145 uint32_t compareMask
)
2147 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2148 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
, 2);
2150 update_stencil_mask(&cmd
->state
.dynamic_stencil_mask
, faceMask
, compareMask
);
2152 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILMASK(.dword
= cmd
->state
.dynamic_stencil_mask
));
2156 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2157 VkStencilFaceFlags faceMask
,
2160 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2161 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
, 2);
2163 update_stencil_mask(&cmd
->state
.dynamic_stencil_wrmask
, faceMask
, writeMask
);
2165 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILWRMASK(.dword
= cmd
->state
.dynamic_stencil_wrmask
));
2169 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2170 VkStencilFaceFlags faceMask
,
2173 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2174 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_REFERENCE
, 2);
2176 update_stencil_mask(&cmd
->state
.dynamic_stencil_ref
, faceMask
, reference
);
2178 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILREF(.dword
= cmd
->state
.dynamic_stencil_ref
));
2182 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer
,
2183 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
2185 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2186 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
, 9);
2188 assert(pSampleLocationsInfo
);
2190 tu6_emit_sample_locations(&cs
, pSampleLocationsInfo
);
2194 tu_flush_for_access(struct tu_cache_state
*cache
,
2195 enum tu_cmd_access_mask src_mask
,
2196 enum tu_cmd_access_mask dst_mask
)
2198 enum tu_cmd_flush_bits flush_bits
= 0;
2200 if (src_mask
& TU_ACCESS_HOST_WRITE
) {
2201 /* Host writes are always visible to CP, so only invalidate GPU caches */
2202 cache
->pending_flush_bits
|= TU_CMD_FLAG_GPU_INVALIDATE
;
2205 if (src_mask
& TU_ACCESS_SYSMEM_WRITE
) {
2206 /* Invalidate CP and 2D engine (make it do WFI + WFM if necessary) as
2209 cache
->pending_flush_bits
|= TU_CMD_FLAG_ALL_INVALIDATE
;
2212 if (src_mask
& TU_ACCESS_CP_WRITE
) {
2213 /* Flush the CP write queue. However a WFI shouldn't be necessary as
2214 * WAIT_MEM_WRITES should cover it.
2216 cache
->pending_flush_bits
|=
2217 TU_CMD_FLAG_WAIT_MEM_WRITES
|
2218 TU_CMD_FLAG_GPU_INVALIDATE
|
2219 TU_CMD_FLAG_WAIT_FOR_ME
;
2222 #define SRC_FLUSH(domain, flush, invalidate) \
2223 if (src_mask & TU_ACCESS_##domain##_WRITE) { \
2224 cache->pending_flush_bits |= TU_CMD_FLAG_##flush | \
2225 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2228 SRC_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2229 SRC_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2230 SRC_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2234 #define SRC_INCOHERENT_FLUSH(domain, flush, invalidate) \
2235 if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
2236 flush_bits |= TU_CMD_FLAG_##flush; \
2237 cache->pending_flush_bits |= \
2238 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2241 SRC_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2242 SRC_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2244 #undef SRC_INCOHERENT_FLUSH
2246 /* Treat host & sysmem write accesses the same, since the kernel implicitly
2247 * drains the queue before signalling completion to the host.
2249 if (dst_mask
& (TU_ACCESS_SYSMEM_READ
| TU_ACCESS_SYSMEM_WRITE
|
2250 TU_ACCESS_HOST_READ
| TU_ACCESS_HOST_WRITE
)) {
2251 flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
2254 #define DST_FLUSH(domain, flush, invalidate) \
2255 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2256 TU_ACCESS_##domain##_WRITE)) { \
2257 flush_bits |= cache->pending_flush_bits & \
2258 (TU_CMD_FLAG_##invalidate | \
2259 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2262 DST_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2263 DST_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2264 DST_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2268 #define DST_INCOHERENT_FLUSH(domain, flush, invalidate) \
2269 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2270 TU_ACCESS_##domain##_WRITE)) { \
2271 flush_bits |= TU_CMD_FLAG_##invalidate | \
2272 (cache->pending_flush_bits & \
2273 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2276 DST_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2277 DST_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2279 #undef DST_INCOHERENT_FLUSH
2281 if (dst_mask
& TU_ACCESS_WFI_READ
) {
2282 flush_bits
|= cache
->pending_flush_bits
&
2283 (TU_CMD_FLAG_ALL_FLUSH
| TU_CMD_FLAG_WAIT_FOR_IDLE
);
2286 if (dst_mask
& TU_ACCESS_WFM_READ
) {
2287 flush_bits
|= cache
->pending_flush_bits
&
2288 (TU_CMD_FLAG_ALL_FLUSH
| TU_CMD_FLAG_WAIT_FOR_ME
);
2291 cache
->flush_bits
|= flush_bits
;
2292 cache
->pending_flush_bits
&= ~flush_bits
;
2295 static enum tu_cmd_access_mask
2296 vk2tu_access(VkAccessFlags flags
, bool gmem
)
2298 enum tu_cmd_access_mask mask
= 0;
2300 /* If the GPU writes a buffer that is then read by an indirect draw
2301 * command, we theoretically need to emit a WFI to wait for any cache
2302 * flushes, and then a WAIT_FOR_ME to wait on the CP for the WFI to
2303 * complete. Waiting for the WFI to complete is performed as part of the
2304 * draw by the firmware, so we just need to execute the WFI.
2306 * Transform feedback counters are read via CP_MEM_TO_REG, which implicitly
2307 * does CP_WAIT_FOR_ME, but we still need a WFI if the GPU writes it.
2310 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
|
2311 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
|
2312 VK_ACCESS_MEMORY_READ_BIT
)) {
2313 mask
|= TU_ACCESS_WFI_READ
;
2317 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
| /* Read performed by CP */
2318 VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
| /* Read performed by CP */
2319 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
| /* Read performed by CP */
2320 VK_ACCESS_MEMORY_READ_BIT
)) {
2321 mask
|= TU_ACCESS_SYSMEM_READ
;
2325 (VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
|
2326 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2327 mask
|= TU_ACCESS_CP_WRITE
;
2331 (VK_ACCESS_HOST_READ_BIT
|
2332 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2333 mask
|= TU_ACCESS_HOST_READ
;
2337 (VK_ACCESS_HOST_WRITE_BIT
|
2338 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2339 mask
|= TU_ACCESS_HOST_WRITE
;
2343 (VK_ACCESS_INDEX_READ_BIT
| /* Read performed by PC, I think */
2344 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
| /* Read performed by VFD */
2345 VK_ACCESS_UNIFORM_READ_BIT
| /* Read performed by SP */
2346 /* TODO: Is there a no-cache bit for textures so that we can ignore
2349 VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
| /* Read performed by TP */
2350 VK_ACCESS_SHADER_READ_BIT
| /* Read perfomed by SP/TP */
2351 VK_ACCESS_MEMORY_READ_BIT
)) {
2352 mask
|= TU_ACCESS_UCHE_READ
;
2356 (VK_ACCESS_SHADER_WRITE_BIT
| /* Write performed by SP */
2357 VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
| /* Write performed by VPC */
2358 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2359 mask
|= TU_ACCESS_UCHE_WRITE
;
2362 /* When using GMEM, the CCU is always flushed automatically to GMEM, and
2363 * then GMEM is flushed to sysmem. Furthermore, we already had to flush any
2364 * previous writes in sysmem mode when transitioning to GMEM. Therefore we
2365 * can ignore CCU and pretend that color attachments and transfers use
2370 (VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
|
2371 VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT
|
2372 VK_ACCESS_MEMORY_READ_BIT
)) {
2374 mask
|= TU_ACCESS_SYSMEM_READ
;
2376 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_READ
;
2380 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
|
2381 VK_ACCESS_MEMORY_READ_BIT
)) {
2383 mask
|= TU_ACCESS_SYSMEM_READ
;
2385 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
;
2389 (VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
|
2390 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2392 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2394 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2399 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
|
2400 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2402 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2404 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2408 /* When the dst access is a transfer read/write, it seems we sometimes need
2409 * to insert a WFI after any flushes, to guarantee that the flushes finish
2410 * before the 2D engine starts. However the opposite (i.e. a WFI after
2411 * CP_BLIT and before any subsequent flush) does not seem to be needed, and
2412 * the blob doesn't emit such a WFI.
2416 (VK_ACCESS_TRANSFER_WRITE_BIT
|
2417 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2419 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2421 mask
|= TU_ACCESS_CCU_COLOR_WRITE
;
2423 mask
|= TU_ACCESS_WFI_READ
;
2427 (VK_ACCESS_TRANSFER_READ_BIT
| /* Access performed by TP */
2428 VK_ACCESS_MEMORY_READ_BIT
)) {
2429 mask
|= TU_ACCESS_UCHE_READ
| TU_ACCESS_WFI_READ
;
2437 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2438 uint32_t commandBufferCount
,
2439 const VkCommandBuffer
*pCmdBuffers
)
2441 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2444 assert(commandBufferCount
> 0);
2446 /* Emit any pending flushes. */
2447 if (cmd
->state
.pass
) {
2448 tu_flush_all_pending(&cmd
->state
.renderpass_cache
);
2449 tu_emit_cache_flush_renderpass(cmd
, &cmd
->draw_cs
);
2451 tu_flush_all_pending(&cmd
->state
.cache
);
2452 tu_emit_cache_flush(cmd
, &cmd
->cs
);
2455 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2456 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2458 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2459 if (result
!= VK_SUCCESS
) {
2460 cmd
->record_result
= result
;
2464 if (secondary
->usage_flags
&
2465 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2466 assert(tu_cs_is_empty(&secondary
->cs
));
2468 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2469 if (result
!= VK_SUCCESS
) {
2470 cmd
->record_result
= result
;
2474 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2475 &secondary
->draw_epilogue_cs
);
2476 if (result
!= VK_SUCCESS
) {
2477 cmd
->record_result
= result
;
2481 if (secondary
->has_tess
)
2482 cmd
->has_tess
= true;
2484 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2485 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2487 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2488 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2489 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2492 tu_cs_add_entries(&cmd
->cs
, &secondary
->cs
);
2495 cmd
->state
.index_size
= secondary
->state
.index_size
; /* for restart index update */
2497 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2499 /* After executing secondary command buffers, there may have been arbitrary
2500 * flushes executed, so when we encounter a pipeline barrier with a
2501 * srcMask, we have to assume that we need to invalidate. Therefore we need
2502 * to re-initialize the cache with all pending invalidate bits set.
2504 if (cmd
->state
.pass
) {
2505 tu_cache_init(&cmd
->state
.renderpass_cache
);
2507 tu_cache_init(&cmd
->state
.cache
);
2512 tu_CreateCommandPool(VkDevice _device
,
2513 const VkCommandPoolCreateInfo
*pCreateInfo
,
2514 const VkAllocationCallbacks
*pAllocator
,
2515 VkCommandPool
*pCmdPool
)
2517 TU_FROM_HANDLE(tu_device
, device
, _device
);
2518 struct tu_cmd_pool
*pool
;
2520 pool
= vk_object_alloc(&device
->vk
, pAllocator
, sizeof(*pool
),
2521 VK_OBJECT_TYPE_COMMAND_POOL
);
2523 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2526 pool
->alloc
= *pAllocator
;
2528 pool
->alloc
= device
->vk
.alloc
;
2530 list_inithead(&pool
->cmd_buffers
);
2531 list_inithead(&pool
->free_cmd_buffers
);
2533 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2535 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2541 tu_DestroyCommandPool(VkDevice _device
,
2542 VkCommandPool commandPool
,
2543 const VkAllocationCallbacks
*pAllocator
)
2545 TU_FROM_HANDLE(tu_device
, device
, _device
);
2546 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2551 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2552 &pool
->cmd_buffers
, pool_link
)
2554 tu_cmd_buffer_destroy(cmd_buffer
);
2557 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2558 &pool
->free_cmd_buffers
, pool_link
)
2560 tu_cmd_buffer_destroy(cmd_buffer
);
2563 vk_object_free(&device
->vk
, pAllocator
, pool
);
2567 tu_ResetCommandPool(VkDevice device
,
2568 VkCommandPool commandPool
,
2569 VkCommandPoolResetFlags flags
)
2571 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2574 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2577 result
= tu_reset_cmd_buffer(cmd_buffer
);
2578 if (result
!= VK_SUCCESS
)
2586 tu_TrimCommandPool(VkDevice device
,
2587 VkCommandPool commandPool
,
2588 VkCommandPoolTrimFlags flags
)
2590 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2595 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2596 &pool
->free_cmd_buffers
, pool_link
)
2598 tu_cmd_buffer_destroy(cmd_buffer
);
2603 tu_subpass_barrier(struct tu_cmd_buffer
*cmd_buffer
,
2604 const struct tu_subpass_barrier
*barrier
,
2607 /* Note: we don't know until the end of the subpass whether we'll use
2608 * sysmem, so assume sysmem here to be safe.
2610 struct tu_cache_state
*cache
=
2611 external
? &cmd_buffer
->state
.cache
: &cmd_buffer
->state
.renderpass_cache
;
2612 enum tu_cmd_access_mask src_flags
=
2613 vk2tu_access(barrier
->src_access_mask
, false);
2614 enum tu_cmd_access_mask dst_flags
=
2615 vk2tu_access(barrier
->dst_access_mask
, false);
2617 if (barrier
->incoherent_ccu_color
)
2618 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2619 if (barrier
->incoherent_ccu_depth
)
2620 src_flags
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2622 tu_flush_for_access(cache
, src_flags
, dst_flags
);
2626 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2627 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2628 VkSubpassContents contents
)
2630 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2631 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2632 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2634 cmd
->state
.pass
= pass
;
2635 cmd
->state
.subpass
= pass
->subpasses
;
2636 cmd
->state
.framebuffer
= fb
;
2637 cmd
->state
.render_area
= pRenderPassBegin
->renderArea
;
2639 tu_cmd_prepare_tile_store_ib(cmd
);
2641 /* Note: because this is external, any flushes will happen before draw_cs
2642 * gets called. However deferred flushes could have to happen later as part
2645 tu_subpass_barrier(cmd
, &pass
->subpasses
[0].start_barrier
, true);
2646 cmd
->state
.renderpass_cache
.pending_flush_bits
=
2647 cmd
->state
.cache
.pending_flush_bits
;
2648 cmd
->state
.renderpass_cache
.flush_bits
= 0;
2650 tu_emit_renderpass_begin(cmd
, pRenderPassBegin
);
2652 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2653 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2654 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2655 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2657 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2659 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2660 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2661 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2662 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2665 cmd
->state
.dirty
|= TU_CMD_DIRTY_DRAW_STATE
;
2669 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2670 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2671 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2673 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2674 pSubpassBeginInfo
->contents
);
2678 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2680 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2681 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2682 struct tu_cs
*cs
= &cmd
->draw_cs
;
2684 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2686 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2688 if (subpass
->resolve_attachments
) {
2689 tu6_emit_blit_scissor(cmd
, cs
, true);
2691 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2692 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2693 if (a
== VK_ATTACHMENT_UNUSED
)
2696 tu_store_gmem_attachment(cmd
, cs
, a
,
2697 subpass
->color_attachments
[i
].attachment
);
2699 if (pass
->attachments
[a
].gmem_offset
< 0)
2703 * check if the resolved attachment is needed by later subpasses,
2704 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2706 tu_finishme("missing GMEM->GMEM resolve path\n");
2707 tu_load_gmem_attachment(cmd
, cs
, a
, true);
2711 tu_cond_exec_end(cs
);
2713 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2715 tu6_emit_sysmem_resolves(cmd
, cs
, subpass
);
2717 tu_cond_exec_end(cs
);
2719 /* Handle dependencies for the next subpass */
2720 tu_subpass_barrier(cmd
, &cmd
->state
.subpass
->start_barrier
, false);
2722 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2723 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2724 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2725 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2726 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2728 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2732 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2733 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2734 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2736 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2740 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2741 struct tu_descriptor_state
*descriptors_state
,
2742 gl_shader_stage type
,
2743 uint32_t *push_constants
)
2745 const struct tu_program_descriptor_linkage
*link
=
2746 &pipeline
->program
.link
[type
];
2747 const struct ir3_ubo_analysis_state
*state
= &link
->const_state
.ubo_state
;
2749 if (link
->push_consts
.count
> 0) {
2750 unsigned num_units
= link
->push_consts
.count
;
2751 unsigned offset
= link
->push_consts
.lo
;
2752 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2753 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2754 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2755 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2756 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2757 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2760 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2761 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2764 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2765 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2766 uint32_t offset
= state
->range
[i
].start
;
2768 /* and even if the start of the const buffer is before
2769 * first_immediate, the end may not be:
2771 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2776 /* things should be aligned to vec4: */
2777 debug_assert((state
->range
[i
].offset
% 16) == 0);
2778 debug_assert((size
% 16) == 0);
2779 debug_assert((offset
% 16) == 0);
2781 /* Dig out the descriptor from the descriptor state and read the VA from
2784 assert(state
->range
[i
].ubo
.bindless
);
2785 uint32_t *base
= state
->range
[i
].ubo
.bindless_base
== MAX_SETS
?
2786 descriptors_state
->dynamic_descriptors
:
2787 descriptors_state
->sets
[state
->range
[i
].ubo
.bindless_base
]->mapped_ptr
;
2788 unsigned block
= state
->range
[i
].ubo
.block
;
2789 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2790 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2793 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2794 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2795 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2796 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2797 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2798 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2799 tu_cs_emit_qw(cs
, va
+ offset
);
2803 static struct tu_draw_state
2804 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2805 const struct tu_pipeline
*pipeline
,
2806 struct tu_descriptor_state
*descriptors_state
,
2807 gl_shader_stage type
)
2810 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2812 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2814 return tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2817 static struct tu_draw_state
2818 tu6_emit_vertex_buffers(struct tu_cmd_buffer
*cmd
,
2819 const struct tu_pipeline
*pipeline
)
2822 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 4 * MAX_VBS
, &cs
);
2825 for_each_bit(binding
, pipeline
->vi
.bindings_used
) {
2826 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2827 const VkDeviceSize offset
= buf
->bo_offset
+
2828 cmd
->state
.vb
.offsets
[binding
];
2830 tu_cs_emit_regs(&cs
,
2831 A6XX_VFD_FETCH_BASE(binding
, .bo
= buf
->bo
, .bo_offset
= offset
),
2832 A6XX_VFD_FETCH_SIZE(binding
, buf
->size
- offset
));
2836 cmd
->vertex_bindings_set
= pipeline
->vi
.bindings_used
;
2838 return tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2842 get_tess_param_bo_size(const struct tu_pipeline
*pipeline
,
2843 uint32_t draw_count
)
2845 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
2846 * Still not sure what to do here, so just allocate a reasonably large
2847 * BO and hope for the best for now. */
2851 /* the tess param BO is pipeline->tess.param_stride bytes per patch,
2852 * which includes both the per-vertex outputs and per-patch outputs
2853 * build_primitive_map in ir3 calculates this stride
2855 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
2856 uint32_t num_patches
= draw_count
/ verts_per_patch
;
2857 return num_patches
* pipeline
->tess
.param_stride
;
2861 get_tess_factor_bo_size(const struct tu_pipeline
*pipeline
,
2862 uint32_t draw_count
)
2864 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
2865 * Still not sure what to do here, so just allocate a reasonably large
2866 * BO and hope for the best for now. */
2870 /* Each distinct patch gets its own tess factor output. */
2871 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
2872 uint32_t num_patches
= draw_count
/ verts_per_patch
;
2873 uint32_t factor_stride
;
2874 switch (pipeline
->tess
.patch_type
) {
2875 case IR3_TESS_ISOLINES
:
2878 case IR3_TESS_TRIANGLES
:
2881 case IR3_TESS_QUADS
:
2885 unreachable("bad tessmode");
2887 return factor_stride
* num_patches
;
2891 tu6_emit_tess_consts(struct tu_cmd_buffer
*cmd
,
2892 uint32_t draw_count
,
2893 const struct tu_pipeline
*pipeline
,
2894 struct tu_draw_state
*state
)
2897 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 20, &cs
);
2898 if (result
!= VK_SUCCESS
)
2901 uint64_t tess_factor_size
= get_tess_factor_bo_size(pipeline
, draw_count
);
2902 uint64_t tess_param_size
= get_tess_param_bo_size(pipeline
, draw_count
);
2903 uint64_t tess_bo_size
= tess_factor_size
+ tess_param_size
;
2904 if (tess_bo_size
> 0) {
2905 struct tu_bo
*tess_bo
;
2906 result
= tu_get_scratch_bo(cmd
->device
, tess_bo_size
, &tess_bo
);
2907 if (result
!= VK_SUCCESS
)
2910 tu_bo_list_add(&cmd
->bo_list
, tess_bo
,
2911 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2912 uint64_t tess_factor_iova
= tess_bo
->iova
;
2913 uint64_t tess_param_iova
= tess_factor_iova
+ tess_factor_size
;
2915 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2916 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.hs_bo_regid
) |
2917 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2918 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2919 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_HS_SHADER
) |
2920 CP_LOAD_STATE6_0_NUM_UNIT(1));
2921 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2922 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2923 tu_cs_emit_qw(&cs
, tess_param_iova
);
2924 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2926 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2927 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.ds_bo_regid
) |
2928 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2929 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2930 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_DS_SHADER
) |
2931 CP_LOAD_STATE6_0_NUM_UNIT(1));
2932 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2933 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2934 tu_cs_emit_qw(&cs
, tess_param_iova
);
2935 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2937 tu_cs_emit_pkt4(&cs
, REG_A6XX_PC_TESSFACTOR_ADDR_LO
, 2);
2938 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2940 /* TODO: Without this WFI here, the hardware seems unable to read these
2941 * addresses we just emitted. Freedreno emits these consts as part of
2942 * IB1 instead of in a draw state which might make this WFI unnecessary,
2943 * but it requires a bit more indirection (SS6_INDIRECT for consts). */
2944 tu_cs_emit_wfi(&cs
);
2946 *state
= tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2951 tu6_draw_common(struct tu_cmd_buffer
*cmd
,
2954 /* note: draw_count is 0 for indirect */
2955 uint32_t draw_count
)
2957 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
2960 struct tu_descriptor_state
*descriptors_state
=
2961 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
2963 tu_emit_cache_flush_renderpass(cmd
, cs
);
2967 tu_cs_emit_regs(cs
, A6XX_PC_PRIMITIVE_CNTL_0(
2968 .primitive_restart
=
2969 pipeline
->ia
.primitive_restart
&& indexed
,
2970 .tess_upper_left_domain_origin
=
2971 pipeline
->tess
.upper_left_domain_origin
));
2973 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
2974 cmd
->state
.shader_const
[MESA_SHADER_VERTEX
] =
2975 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
);
2976 cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
] =
2977 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_CTRL
);
2978 cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
] =
2979 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_EVAL
);
2980 cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
] =
2981 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_GEOMETRY
);
2982 cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
] =
2983 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
);
2986 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
2987 cmd
->state
.vertex_buffers
= tu6_emit_vertex_buffers(cmd
, pipeline
);
2990 pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
2991 struct tu_draw_state tess_consts
= {};
2993 cmd
->has_tess
= true;
2994 result
= tu6_emit_tess_consts(cmd
, draw_count
, pipeline
, &tess_consts
);
2995 if (result
!= VK_SUCCESS
)
2999 /* for the first draw in a renderpass, re-emit all the draw states
3001 * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
3002 * used, then draw states must be re-emitted. note however this only happens
3003 * in the sysmem path, so this can be skipped this for the gmem path (TODO)
3005 * the two input attachment states are excluded because secondary command
3006 * buffer doesn't have a state ib to restore it, and not re-emitting them
3007 * is OK since CmdClearAttachments won't disable/overwrite them
3009 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DRAW_STATE
) {
3010 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (TU_DRAW_STATE_COUNT
- 2));
3012 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state
);
3013 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state
);
3014 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
3015 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state
);
3016 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state
);
3017 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast_state
);
3018 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS
, pipeline
->ds_state
);
3019 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend_state
);
3020 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_VERTEX
]);
3021 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
]);
3022 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
]);
3023 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
]);
3024 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
]);
3025 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets
);
3026 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, pipeline
->load_state
);
3027 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers
);
3028 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_PARAMS
, cmd
->state
.vs_params
);
3030 for (uint32_t i
= 0; i
< ARRAY_SIZE(cmd
->state
.dynamic_state
); i
++) {
3031 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
,
3032 ((pipeline
->dynamic_state_mask
& BIT(i
)) ?
3033 cmd
->state
.dynamic_state
[i
] :
3034 pipeline
->dynamic_state
[i
]));
3038 /* emit draw states that were just updated
3039 * note we eventually don't want to have to emit anything here
3041 uint32_t draw_state_count
=
3043 ((cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) ? 5 : 0) +
3044 ((cmd
->state
.dirty
& TU_CMD_DIRTY_DESC_SETS_LOAD
) ? 1 : 0) +
3045 ((cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) ? 1 : 0) +
3048 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_count
);
3050 /* We may need to re-emit tess consts if the current draw call is
3051 * sufficiently larger than the last draw call. */
3053 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
3054 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
3055 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_VERTEX
]);
3056 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
]);
3057 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
]);
3058 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
]);
3059 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
]);
3061 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESC_SETS_LOAD
)
3062 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, pipeline
->load_state
);
3063 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3064 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers
);
3065 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_PARAMS
, cmd
->state
.vs_params
);
3068 tu_cs_sanity_check(cs
);
3070 /* There are too many graphics dirty bits to list here, so just list the
3071 * bits to preserve instead. The only things not emitted here are
3072 * compute-related state.
3074 cmd
->state
.dirty
&= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
3079 tu_draw_initiator(struct tu_cmd_buffer
*cmd
, enum pc_di_src_sel src_sel
)
3081 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3082 uint32_t initiator
=
3083 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(pipeline
->ia
.primtype
) |
3084 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(src_sel
) |
3085 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(cmd
->state
.index_size
) |
3086 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
);
3088 if (pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
)
3089 initiator
|= CP_DRAW_INDX_OFFSET_0_GS_ENABLE
;
3091 switch (pipeline
->tess
.patch_type
) {
3092 case IR3_TESS_TRIANGLES
:
3093 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_TRIANGLES
) |
3094 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3096 case IR3_TESS_ISOLINES
:
3097 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_ISOLINES
) |
3098 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3101 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS
);
3103 case IR3_TESS_QUADS
:
3104 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS
) |
3105 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3113 vs_params_offset(struct tu_cmd_buffer
*cmd
)
3115 const struct tu_program_descriptor_linkage
*link
=
3116 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
3117 const struct ir3_const_state
*const_state
= &link
->const_state
;
3119 if (const_state
->offsets
.driver_param
>= link
->constlen
)
3122 /* this layout is required by CP_DRAW_INDIRECT_MULTI */
3123 STATIC_ASSERT(IR3_DP_DRAWID
== 0);
3124 STATIC_ASSERT(IR3_DP_VTXID_BASE
== 1);
3125 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
3127 /* 0 means disabled for CP_DRAW_INDIRECT_MULTI */
3128 assert(const_state
->offsets
.driver_param
!= 0);
3130 return const_state
->offsets
.driver_param
;
3133 static struct tu_draw_state
3134 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
3135 uint32_t vertex_offset
,
3136 uint32_t first_instance
)
3138 uint32_t offset
= vs_params_offset(cmd
);
3141 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 3 + (offset
? 8 : 0), &cs
);
3142 if (result
!= VK_SUCCESS
) {
3143 cmd
->record_result
= result
;
3144 return (struct tu_draw_state
) {};
3147 /* TODO: don't make a new draw state when it doesn't change */
3149 tu_cs_emit_regs(&cs
,
3150 A6XX_VFD_INDEX_OFFSET(vertex_offset
),
3151 A6XX_VFD_INSTANCE_START_OFFSET(first_instance
));
3154 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
3155 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3156 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3157 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3158 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
3159 CP_LOAD_STATE6_0_NUM_UNIT(1));
3164 tu_cs_emit(&cs
, vertex_offset
);
3165 tu_cs_emit(&cs
, first_instance
);
3169 struct tu_cs_entry entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
3170 return (struct tu_draw_state
) {entry
.bo
->iova
+ entry
.offset
, entry
.size
/ 4};
3174 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3175 uint32_t vertexCount
,
3176 uint32_t instanceCount
,
3177 uint32_t firstVertex
,
3178 uint32_t firstInstance
)
3180 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3181 struct tu_cs
*cs
= &cmd
->draw_cs
;
3183 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, firstVertex
, firstInstance
);
3185 tu6_draw_common(cmd
, cs
, false, vertexCount
);
3187 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3188 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3189 tu_cs_emit(cs
, instanceCount
);
3190 tu_cs_emit(cs
, vertexCount
);
3194 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3195 uint32_t indexCount
,
3196 uint32_t instanceCount
,
3197 uint32_t firstIndex
,
3198 int32_t vertexOffset
,
3199 uint32_t firstInstance
)
3201 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3202 struct tu_cs
*cs
= &cmd
->draw_cs
;
3204 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, vertexOffset
, firstInstance
);
3206 tu6_draw_common(cmd
, cs
, true, indexCount
);
3208 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3209 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3210 tu_cs_emit(cs
, instanceCount
);
3211 tu_cs_emit(cs
, indexCount
);
3212 tu_cs_emit(cs
, firstIndex
);
3213 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3214 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3217 /* Various firmware bugs/inconsistencies mean that some indirect draw opcodes
3218 * do not wait for WFI's to complete before executing. Add a WAIT_FOR_ME if
3219 * pending for these opcodes. This may result in a few extra WAIT_FOR_ME's
3220 * with these opcodes, but the alternative would add unnecessary WAIT_FOR_ME's
3221 * before draw opcodes that don't need it.
3224 draw_wfm(struct tu_cmd_buffer
*cmd
)
3226 cmd
->state
.renderpass_cache
.flush_bits
|=
3227 cmd
->state
.renderpass_cache
.pending_flush_bits
& TU_CMD_FLAG_WAIT_FOR_ME
;
3228 cmd
->state
.renderpass_cache
.pending_flush_bits
&= ~TU_CMD_FLAG_WAIT_FOR_ME
;
3232 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3234 VkDeviceSize offset
,
3238 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3239 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3240 struct tu_cs
*cs
= &cmd
->draw_cs
;
3242 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3244 /* The latest known a630_sqe.fw fails to wait for WFI before reading the
3245 * indirect buffer when using CP_DRAW_INDIRECT_MULTI, so we have to fall
3246 * back to CP_WAIT_FOR_ME except for a650 which has a fixed firmware.
3248 * TODO: There may be newer a630_sqe.fw released in the future which fixes
3249 * this, if so we should detect it and avoid this workaround.
3251 if (cmd
->device
->physical_device
->gpu_id
!= 650)
3254 tu6_draw_common(cmd
, cs
, false, 0);
3256 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 6);
3257 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3258 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_NORMAL
) |
3259 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3260 tu_cs_emit(cs
, drawCount
);
3261 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3262 tu_cs_emit(cs
, stride
);
3264 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3268 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3270 VkDeviceSize offset
,
3274 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3275 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3276 struct tu_cs
*cs
= &cmd
->draw_cs
;
3278 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3280 if (cmd
->device
->physical_device
->gpu_id
!= 650)
3283 tu6_draw_common(cmd
, cs
, true, 0);
3285 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 9);
3286 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3287 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDEXED
) |
3288 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3289 tu_cs_emit(cs
, drawCount
);
3290 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3291 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3292 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3293 tu_cs_emit(cs
, stride
);
3295 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3298 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3299 uint32_t instanceCount
,
3300 uint32_t firstInstance
,
3301 VkBuffer _counterBuffer
,
3302 VkDeviceSize counterBufferOffset
,
3303 uint32_t counterOffset
,
3304 uint32_t vertexStride
)
3306 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3307 TU_FROM_HANDLE(tu_buffer
, buf
, _counterBuffer
);
3308 struct tu_cs
*cs
= &cmd
->draw_cs
;
3310 /* All known firmware versions do not wait for WFI's with CP_DRAW_AUTO.
3311 * Plus, for the common case where the counter buffer is written by
3312 * vkCmdEndTransformFeedback, we need to wait for the CP_WAIT_MEM_WRITES to
3313 * complete which means we need a WAIT_FOR_ME anyway.
3317 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, 0, firstInstance
);
3319 tu6_draw_common(cmd
, cs
, false, 0);
3321 tu_cs_emit_pkt7(cs
, CP_DRAW_AUTO
, 6);
3322 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_XFB
));
3323 tu_cs_emit(cs
, instanceCount
);
3324 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ counterBufferOffset
);
3325 tu_cs_emit(cs
, counterOffset
);
3326 tu_cs_emit(cs
, vertexStride
);
3328 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3331 struct tu_dispatch_info
3334 * Determine the layout of the grid (in block units) to be used.
3339 * A starting offset for the grid. If unaligned is set, the offset
3340 * must still be aligned.
3342 uint32_t offsets
[3];
3344 * Whether it's an unaligned compute dispatch.
3349 * Indirect compute parameters resource.
3351 struct tu_buffer
*indirect
;
3352 uint64_t indirect_offset
;
3356 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3357 const struct tu_dispatch_info
*info
)
3359 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3360 const struct tu_program_descriptor_linkage
*link
=
3361 &pipeline
->program
.link
[type
];
3362 const struct ir3_const_state
*const_state
= &link
->const_state
;
3363 uint32_t offset
= const_state
->offsets
.driver_param
;
3365 if (link
->constlen
<= offset
)
3368 if (!info
->indirect
) {
3369 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3370 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3371 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3372 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3373 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3374 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3375 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3378 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3379 (link
->constlen
- offset
) * 4);
3380 /* push constants */
3381 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3382 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3383 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3384 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3385 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3386 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3390 for (i
= 0; i
< num_consts
; i
++)
3391 tu_cs_emit(cs
, driver_params
[i
]);
3393 tu_finishme("Indirect driver params");
3398 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3399 const struct tu_dispatch_info
*info
)
3401 struct tu_cs
*cs
= &cmd
->cs
;
3402 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3403 struct tu_descriptor_state
*descriptors_state
=
3404 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3406 /* TODO: We could probably flush less if we add a compute_flush_bits
3409 tu_emit_cache_flush(cmd
, cs
);
3411 /* note: no reason to have this in a separate IB */
3412 tu_cs_emit_state_ib(cs
,
3413 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
));
3415 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3417 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
)
3418 tu_cs_emit_state_ib(cs
, pipeline
->load_state
);
3420 cmd
->state
.dirty
&= ~TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
3422 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3423 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3425 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3426 const uint32_t *num_groups
= info
->blocks
;
3428 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3429 .localsizex
= local_size
[0] - 1,
3430 .localsizey
= local_size
[1] - 1,
3431 .localsizez
= local_size
[2] - 1),
3432 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3433 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3434 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3435 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3436 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3437 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3440 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3441 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3442 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3444 if (info
->indirect
) {
3445 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3447 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3448 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3450 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3451 tu_cs_emit(cs
, 0x00000000);
3452 tu_cs_emit_qw(cs
, iova
);
3454 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3455 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3456 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3458 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3459 tu_cs_emit(cs
, 0x00000000);
3460 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3461 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3462 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3469 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3477 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3478 struct tu_dispatch_info info
= {};
3484 info
.offsets
[0] = base_x
;
3485 info
.offsets
[1] = base_y
;
3486 info
.offsets
[2] = base_z
;
3487 tu_dispatch(cmd_buffer
, &info
);
3491 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3496 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3500 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3502 VkDeviceSize offset
)
3504 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3505 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3506 struct tu_dispatch_info info
= {};
3508 info
.indirect
= buffer
;
3509 info
.indirect_offset
= offset
;
3511 tu_dispatch(cmd_buffer
, &info
);
3515 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3517 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3519 tu_cs_end(&cmd_buffer
->draw_cs
);
3520 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3522 if (use_sysmem_rendering(cmd_buffer
))
3523 tu_cmd_render_sysmem(cmd_buffer
);
3525 tu_cmd_render_tiles(cmd_buffer
);
3527 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3529 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3530 tu_cs_begin(&cmd_buffer
->draw_cs
);
3531 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3532 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3534 cmd_buffer
->state
.cache
.pending_flush_bits
|=
3535 cmd_buffer
->state
.renderpass_cache
.pending_flush_bits
;
3536 tu_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
, true);
3538 cmd_buffer
->state
.pass
= NULL
;
3539 cmd_buffer
->state
.subpass
= NULL
;
3540 cmd_buffer
->state
.framebuffer
= NULL
;
3544 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3545 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3547 tu_CmdEndRenderPass(commandBuffer
);
3550 struct tu_barrier_info
3552 uint32_t eventCount
;
3553 const VkEvent
*pEvents
;
3554 VkPipelineStageFlags srcStageMask
;
3558 tu_barrier(struct tu_cmd_buffer
*cmd
,
3559 uint32_t memoryBarrierCount
,
3560 const VkMemoryBarrier
*pMemoryBarriers
,
3561 uint32_t bufferMemoryBarrierCount
,
3562 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3563 uint32_t imageMemoryBarrierCount
,
3564 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3565 const struct tu_barrier_info
*info
)
3567 struct tu_cs
*cs
= cmd
->state
.pass
? &cmd
->draw_cs
: &cmd
->cs
;
3568 VkAccessFlags srcAccessMask
= 0;
3569 VkAccessFlags dstAccessMask
= 0;
3571 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3572 srcAccessMask
|= pMemoryBarriers
[i
].srcAccessMask
;
3573 dstAccessMask
|= pMemoryBarriers
[i
].dstAccessMask
;
3576 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3577 srcAccessMask
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
3578 dstAccessMask
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
3581 enum tu_cmd_access_mask src_flags
= 0;
3582 enum tu_cmd_access_mask dst_flags
= 0;
3584 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3585 TU_FROM_HANDLE(tu_image
, image
, pImageMemoryBarriers
[i
].image
);
3586 VkImageLayout old_layout
= pImageMemoryBarriers
[i
].oldLayout
;
3587 /* For non-linear images, PREINITIALIZED is the same as UNDEFINED */
3588 if (old_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
3589 (image
->tiling
!= VK_IMAGE_TILING_LINEAR
&&
3590 old_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
)) {
3591 /* The underlying memory for this image may have been used earlier
3592 * within the same queue submission for a different image, which
3593 * means that there may be old, stale cache entries which are in the
3594 * "wrong" location, which could cause problems later after writing
3595 * to the image. We don't want these entries being flushed later and
3596 * overwriting the actual image, so we need to flush the CCU.
3598 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
3600 srcAccessMask
|= pImageMemoryBarriers
[i
].srcAccessMask
;
3601 dstAccessMask
|= pImageMemoryBarriers
[i
].dstAccessMask
;
3604 /* Inside a renderpass, we don't know yet whether we'll be using sysmem
3605 * so we have to use the sysmem flushes.
3607 bool gmem
= cmd
->state
.ccu_state
== TU_CMD_CCU_GMEM
&&
3609 src_flags
|= vk2tu_access(srcAccessMask
, gmem
);
3610 dst_flags
|= vk2tu_access(dstAccessMask
, gmem
);
3612 struct tu_cache_state
*cache
=
3613 cmd
->state
.pass
? &cmd
->state
.renderpass_cache
: &cmd
->state
.cache
;
3614 tu_flush_for_access(cache
, src_flags
, dst_flags
);
3616 for (uint32_t i
= 0; i
< info
->eventCount
; i
++) {
3617 TU_FROM_HANDLE(tu_event
, event
, info
->pEvents
[i
]);
3619 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3621 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3622 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3623 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3624 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3625 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3626 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3627 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3632 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3633 VkPipelineStageFlags srcStageMask
,
3634 VkPipelineStageFlags dstStageMask
,
3635 VkDependencyFlags dependencyFlags
,
3636 uint32_t memoryBarrierCount
,
3637 const VkMemoryBarrier
*pMemoryBarriers
,
3638 uint32_t bufferMemoryBarrierCount
,
3639 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3640 uint32_t imageMemoryBarrierCount
,
3641 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3643 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3644 struct tu_barrier_info info
;
3646 info
.eventCount
= 0;
3647 info
.pEvents
= NULL
;
3648 info
.srcStageMask
= srcStageMask
;
3650 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3651 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3652 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3656 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
,
3657 VkPipelineStageFlags stageMask
, unsigned value
)
3659 struct tu_cs
*cs
= &cmd
->cs
;
3661 /* vkCmdSetEvent/vkCmdResetEvent cannot be called inside a render pass */
3662 assert(!cmd
->state
.pass
);
3664 tu_emit_cache_flush(cmd
, cs
);
3666 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3668 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
3669 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
3671 VkPipelineStageFlags top_of_pipe_flags
=
3672 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
3673 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
;
3675 if (!(stageMask
& ~top_of_pipe_flags
)) {
3676 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3677 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3678 tu_cs_emit(cs
, value
);
3680 /* Use a RB_DONE_TS event to wait for everything to complete. */
3681 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 4);
3682 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS
));
3683 tu_cs_emit_qw(cs
, event
->bo
.iova
);
3684 tu_cs_emit(cs
, value
);
3689 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3691 VkPipelineStageFlags stageMask
)
3693 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3694 TU_FROM_HANDLE(tu_event
, event
, _event
);
3696 write_event(cmd
, event
, stageMask
, 1);
3700 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3702 VkPipelineStageFlags stageMask
)
3704 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3705 TU_FROM_HANDLE(tu_event
, event
, _event
);
3707 write_event(cmd
, event
, stageMask
, 0);
3711 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3712 uint32_t eventCount
,
3713 const VkEvent
*pEvents
,
3714 VkPipelineStageFlags srcStageMask
,
3715 VkPipelineStageFlags dstStageMask
,
3716 uint32_t memoryBarrierCount
,
3717 const VkMemoryBarrier
*pMemoryBarriers
,
3718 uint32_t bufferMemoryBarrierCount
,
3719 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3720 uint32_t imageMemoryBarrierCount
,
3721 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3723 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3724 struct tu_barrier_info info
;
3726 info
.eventCount
= eventCount
;
3727 info
.pEvents
= pEvents
;
3728 info
.srcStageMask
= 0;
3730 tu_barrier(cmd
, memoryBarrierCount
, pMemoryBarriers
,
3731 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3732 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3736 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)