src/freedreno/vulkan/tu_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 #include "tu_private.h"
  29
  30 #include "registers/adreno_pm4.xml.h"
  31 #include "registers/adreno_common.xml.h"
  32
  33 #include "vk_format.h"
  34
  35 #include "tu_cs.h"
  36
  37 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
  38
  39 void
  40 tu_bo_list_init(struct tu_bo_list *list)
  41 {
  42    list->count = list->capacity = 0;
  43    list->bo_infos = NULL;
  44 }
  45
  46 void
  47 tu_bo_list_destroy(struct tu_bo_list *list)
  48 {
  49    free(list->bo_infos);
  50 }
  51
  52 void
  53 tu_bo_list_reset(struct tu_bo_list *list)
  54 {
  55    list->count = 0;
  56 }
  57
  58 /**
  59  * \a flags consists of MSM_SUBMIT_BO_FLAGS.
  60  */
  61 static uint32_t
  62 tu_bo_list_add_info(struct tu_bo_list *list,
  63                     const struct drm_msm_gem_submit_bo *bo_info)
  64 {
  65    assert(bo_info->handle != 0);
  66
  67    for (uint32_t i = 0; i < list->count; ++i) {
  68       if (list->bo_infos[i].handle == bo_info->handle) {
  69          assert(list->bo_infos[i].presumed == bo_info->presumed);
  70          list->bo_infos[i].flags |= bo_info->flags;
  71          return i;
  72       }
  73    }
  74
  75    /* grow list->bo_infos if needed */
  76    if (list->count == list->capacity) {
  77       uint32_t new_capacity = MAX2(2 * list->count, 16);
  78       struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
  79          list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
  80       if (!new_bo_infos)
  81          return TU_BO_LIST_FAILED;
  82       list->bo_infos = new_bo_infos;
  83       list->capacity = new_capacity;
  84    }
  85
  86    list->bo_infos[list->count] = *bo_info;
  87    return list->count++;
  88 }
  89
  90 uint32_t
  91 tu_bo_list_add(struct tu_bo_list *list,
  92                const struct tu_bo *bo,
  93                uint32_t flags)
  94 {
  95    return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
  96                                        .flags = flags,
  97                                        .handle = bo->gem_handle,
  98                                        .presumed = bo->iova,
  99                                     });
 100 }
 101
 102 VkResult
 103 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
 104 {
 105    for (uint32_t i = 0; i < other->count; i++) {
 106       if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
 107          return VK_ERROR_OUT_OF_HOST_MEMORY;
 108    }
 109
 110    return VK_SUCCESS;
 111 }
 112
 113 static void
 114 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
 115                                     const struct tu_device *dev,
 116                                     uint32_t pixels)
 117 {
 118    const uint32_t tile_align_w = 64; /* note: 32 when no input attachments */
 119    const uint32_t tile_align_h = 16;
 120    const uint32_t max_tile_width = 1024;
 121
 122    /* note: don't offset the tiling config by render_area.offset,
 123     * because binning pass can't deal with it
 124     * this means we might end up with more tiles than necessary,
 125     * but load/store/etc are still scissored to the render_area
 126     */
 127    tiling->tile0.offset = (VkOffset2D) {};
 128
 129    const uint32_t ra_width =
 130       tiling->render_area.extent.width +
 131       (tiling->render_area.offset.x - tiling->tile0.offset.x);
 132    const uint32_t ra_height =
 133       tiling->render_area.extent.height +
 134       (tiling->render_area.offset.y - tiling->tile0.offset.y);
 135
 136    /* start from 1 tile */
 137    tiling->tile_count = (VkExtent2D) {
 138       .width = 1,
 139       .height = 1,
 140    };
 141    tiling->tile0.extent = (VkExtent2D) {
 142       .width = align(ra_width, tile_align_w),
 143       .height = align(ra_height, tile_align_h),
 144    };
 145
 146    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN)) {
 147       /* start with 2x2 tiles */
 148       tiling->tile_count.width = 2;
 149       tiling->tile_count.height = 2;
 150       tiling->tile0.extent.width = align(DIV_ROUND_UP(ra_width, 2), tile_align_w);
 151       tiling->tile0.extent.height = align(DIV_ROUND_UP(ra_height, 2), tile_align_h);
 152    }
 153
 154    /* do not exceed max tile width */
 155    while (tiling->tile0.extent.width > max_tile_width) {
 156       tiling->tile_count.width++;
 157       tiling->tile0.extent.width =
 158          align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 159    }
 160
 161    /* will force to sysmem, don't bother trying to have a valid tile config
 162     * TODO: just skip all GMEM stuff when sysmem is forced?
 163     */
 164    if (!pixels)
 165       return;
 166
 167    /* do not exceed gmem size */
 168    while (tiling->tile0.extent.width * tiling->tile0.extent.height > pixels) {
 169       if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
 170          tiling->tile_count.width++;
 171          tiling->tile0.extent.width =
 172             align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 173       } else {
 174          /* if this assert fails then layout is impossible.. */
 175          assert(tiling->tile0.extent.height > tile_align_h);
 176          tiling->tile_count.height++;
 177          tiling->tile0.extent.height =
 178             align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), tile_align_h);
 179       }
 180    }
 181 }
 182
 183 static void
 184 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
 185                                     const struct tu_device *dev)
 186 {
 187    const uint32_t max_pipe_count = 32; /* A6xx */
 188
 189    /* start from 1 tile per pipe */
 190    tiling->pipe0 = (VkExtent2D) {
 191       .width = 1,
 192       .height = 1,
 193    };
 194    tiling->pipe_count = tiling->tile_count;
 195
 196    while (tiling->pipe_count.width * tiling->pipe_count.height > max_pipe_count) {
 197       if (tiling->pipe0.width < tiling->pipe0.height) {
 198          tiling->pipe0.width += 1;
 199          tiling->pipe_count.width =
 200             DIV_ROUND_UP(tiling->tile_count.width, tiling->pipe0.width);
 201       } else {
 202          tiling->pipe0.height += 1;
 203          tiling->pipe_count.height =
 204             DIV_ROUND_UP(tiling->tile_count.height, tiling->pipe0.height);
 205       }
 206    }
 207 }
 208
 209 static void
 210 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
 211                               const struct tu_device *dev)
 212 {
 213    const uint32_t max_pipe_count = 32; /* A6xx */
 214    const uint32_t used_pipe_count =
 215       tiling->pipe_count.width * tiling->pipe_count.height;
 216    const VkExtent2D last_pipe = {
 217       .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
 218       .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
 219    };
 220
 221    assert(used_pipe_count <= max_pipe_count);
 222    assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
 223
 224    for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
 225       for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
 226          const uint32_t pipe_x = tiling->pipe0.width * x;
 227          const uint32_t pipe_y = tiling->pipe0.height * y;
 228          const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
 229                                     ? last_pipe.width
 230                                     : tiling->pipe0.width;
 231          const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
 232                                     ? last_pipe.height
 233                                     : tiling->pipe0.height;
 234          const uint32_t n = tiling->pipe_count.width * y + x;
 235
 236          tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
 237                                   A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
 238                                   A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
 239                                   A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
 240          tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
 241       }
 242    }
 243
 244    memset(tiling->pipe_config + used_pipe_count, 0,
 245           sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
 246 }
 247
 248 static void
 249 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
 250                           const struct tu_device *dev,
 251                           uint32_t tx,
 252                           uint32_t ty,
 253                           struct tu_tile *tile)
 254 {
 255    /* find the pipe and the slot for tile (tx, ty) */
 256    const uint32_t px = tx / tiling->pipe0.width;
 257    const uint32_t py = ty / tiling->pipe0.height;
 258    const uint32_t sx = tx - tiling->pipe0.width * px;
 259    const uint32_t sy = ty - tiling->pipe0.height * py;
 260    /* last pipe has different width */
 261    const uint32_t pipe_width =
 262       MIN2(tiling->pipe0.width,
 263            tiling->tile_count.width - px * tiling->pipe0.width);
 264
 265    assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
 266    assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
 267    assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
 268
 269    /* convert to 1D indices */
 270    tile->pipe = tiling->pipe_count.width * py + px;
 271    tile->slot = pipe_width * sy + sx;
 272
 273    /* get the blit area for the tile */
 274    tile->begin = (VkOffset2D) {
 275       .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
 276       .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
 277    };
 278    tile->end.x =
 279       (tx == tiling->tile_count.width - 1)
 280          ? tiling->render_area.offset.x + tiling->render_area.extent.width
 281          : tile->begin.x + tiling->tile0.extent.width;
 282    tile->end.y =
 283       (ty == tiling->tile_count.height - 1)
 284          ? tiling->render_area.offset.y + tiling->render_area.extent.height
 285          : tile->begin.y + tiling->tile0.extent.height;
 286 }
 287
 288 enum a3xx_msaa_samples
 289 tu_msaa_samples(uint32_t samples)
 290 {
 291    switch (samples) {
 292    case 1:
 293       return MSAA_ONE;
 294    case 2:
 295       return MSAA_TWO;
 296    case 4:
 297       return MSAA_FOUR;
 298    case 8:
 299       return MSAA_EIGHT;
 300    default:
 301       assert(!"invalid sample count");
 302       return MSAA_ONE;
 303    }
 304 }
 305
 306 static enum a4xx_index_size
 307 tu6_index_size(VkIndexType type)
 308 {
 309    switch (type) {
 310    case VK_INDEX_TYPE_UINT16:
 311       return INDEX4_SIZE_16_BIT;
 312    case VK_INDEX_TYPE_UINT32:
 313       return INDEX4_SIZE_32_BIT;
 314    default:
 315       unreachable("invalid VkIndexType");
 316       return INDEX4_SIZE_8_BIT;
 317    }
 318 }
 319
 320 unsigned
 321 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
 322                      struct tu_cs *cs,
 323                      enum vgt_event_type event,
 324                      bool need_seqno)
 325 {
 326    unsigned seqno = 0;
 327
 328    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
 329    tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
 330    if (need_seqno) {
 331       tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 332       seqno = ++cmd->scratch_seqno;
 333       tu_cs_emit(cs, seqno);
 334    }
 335
 336    return seqno;
 337 }
 338
 339 static void
 340 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 341 {
 342    tu6_emit_event_write(cmd, cs, 0x31, false);
 343 }
 344
 345 static void
 346 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 347 {
 348    tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
 349 }
 350
 351 static void
 352 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 353 {
 354    if (cmd->wait_for_idle) {
 355       tu_cs_emit_wfi(cs);
 356       cmd->wait_for_idle = false;
 357    }
 358 }
 359
 360 static void
 361 tu6_emit_zs(struct tu_cmd_buffer *cmd,
 362             const struct tu_subpass *subpass,
 363             struct tu_cs *cs)
 364 {
 365    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 366
 367    const uint32_t a = subpass->depth_stencil_attachment.attachment;
 368    if (a == VK_ATTACHMENT_UNUSED) {
 369       tu_cs_emit_regs(cs,
 370                       A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE),
 371                       A6XX_RB_DEPTH_BUFFER_PITCH(0),
 372                       A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
 373                       A6XX_RB_DEPTH_BUFFER_BASE(0),
 374                       A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
 375
 376       tu_cs_emit_regs(cs,
 377                       A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
 378
 379       tu_cs_emit_regs(cs,
 380                       A6XX_GRAS_LRZ_BUFFER_BASE(0),
 381                       A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 382                       A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 383
 384       tu_cs_emit_regs(cs, A6XX_RB_STENCIL_INFO(0));
 385
 386       return;
 387    }
 388
 389    const struct tu_image_view *iview = fb->attachments[a].attachment;
 390    const struct tu_render_pass_attachment *attachment =
 391       &cmd->state.pass->attachments[a];
 392    enum a6xx_depth_format fmt = tu6_pipe2depth(attachment->format);
 393
 394    tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
 395    tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt).value);
 396    tu_cs_image_ref(cs, iview, 0);
 397    tu_cs_emit(cs, attachment->gmem_offset);
 398
 399    tu_cs_emit_regs(cs,
 400                    A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
 401
 402    tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
 403    tu_cs_image_flag_ref(cs, iview, 0);
 404
 405    tu_cs_emit_regs(cs,
 406                    A6XX_GRAS_LRZ_BUFFER_BASE(0),
 407                    A6XX_GRAS_LRZ_BUFFER_PITCH(0),
 408                    A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
 409
 410    if (attachment->format == VK_FORMAT_S8_UINT) {
 411       tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 6);
 412       tu_cs_emit(cs, A6XX_RB_STENCIL_INFO(.separate_stencil = true).value);
 413       tu_cs_image_ref(cs, iview, 0);
 414       tu_cs_emit(cs, attachment->gmem_offset);
 415    } else {
 416       tu_cs_emit_regs(cs,
 417                      A6XX_RB_STENCIL_INFO(0));
 418    }
 419 }
 420
 421 static void
 422 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
 423              const struct tu_subpass *subpass,
 424              struct tu_cs *cs)
 425 {
 426    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 427
 428    for (uint32_t i = 0; i < subpass->color_count; ++i) {
 429       uint32_t a = subpass->color_attachments[i].attachment;
 430       if (a == VK_ATTACHMENT_UNUSED)
 431          continue;
 432
 433       const struct tu_image_view *iview = fb->attachments[a].attachment;
 434
 435       tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
 436       tu_cs_emit(cs, iview->RB_MRT_BUF_INFO);
 437       tu_cs_image_ref(cs, iview, 0);
 438       tu_cs_emit(cs, cmd->state.pass->attachments[a].gmem_offset);
 439
 440       tu_cs_emit_regs(cs,
 441                       A6XX_SP_FS_MRT_REG(i, .dword = iview->SP_FS_MRT_REG));
 442
 443       tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i), 3);
 444       tu_cs_image_flag_ref(cs, iview, 0);
 445    }
 446
 447    tu_cs_emit_regs(cs,
 448                    A6XX_RB_SRGB_CNTL(.dword = subpass->srgb_cntl));
 449    tu_cs_emit_regs(cs,
 450                    A6XX_SP_SRGB_CNTL(.dword = subpass->srgb_cntl));
 451
 452    tu_cs_emit_regs(cs,
 453                    A6XX_RB_RENDER_COMPONENTS(.dword = subpass->render_components));
 454    tu_cs_emit_regs(cs,
 455                    A6XX_SP_FS_RENDER_COMPONENTS(.dword = subpass->render_components));
 456
 457    tu_cs_emit_regs(cs, A6XX_GRAS_MAX_LAYER_INDEX(fb->layers - 1));
 458 }
 459
 460 void
 461 tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits vk_samples)
 462 {
 463    const enum a3xx_msaa_samples samples = tu_msaa_samples(vk_samples);
 464    bool msaa_disable = samples == MSAA_ONE;
 465
 466    tu_cs_emit_regs(cs,
 467                    A6XX_SP_TP_RAS_MSAA_CNTL(samples),
 468                    A6XX_SP_TP_DEST_MSAA_CNTL(.samples = samples,
 469                                              .msaa_disable = msaa_disable));
 470
 471    tu_cs_emit_regs(cs,
 472                    A6XX_GRAS_RAS_MSAA_CNTL(samples),
 473                    A6XX_GRAS_DEST_MSAA_CNTL(.samples = samples,
 474                                             .msaa_disable = msaa_disable));
 475
 476    tu_cs_emit_regs(cs,
 477                    A6XX_RB_RAS_MSAA_CNTL(samples),
 478                    A6XX_RB_DEST_MSAA_CNTL(.samples = samples,
 479                                           .msaa_disable = msaa_disable));
 480
 481    tu_cs_emit_regs(cs,
 482                    A6XX_RB_MSAA_CNTL(samples));
 483 }
 484
 485 static void
 486 tu6_emit_bin_size(struct tu_cs *cs,
 487                   uint32_t bin_w, uint32_t bin_h, uint32_t flags)
 488 {
 489    tu_cs_emit_regs(cs,
 490                    A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
 491                                          .binh = bin_h,
 492                                          .dword = flags));
 493
 494    tu_cs_emit_regs(cs,
 495                    A6XX_RB_BIN_CONTROL(.binw = bin_w,
 496                                        .binh = bin_h,
 497                                        .dword = flags));
 498
 499    /* no flag for RB_BIN_CONTROL2... */
 500    tu_cs_emit_regs(cs,
 501                    A6XX_RB_BIN_CONTROL2(.binw = bin_w,
 502                                         .binh = bin_h));
 503 }
 504
 505 static void
 506 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
 507                      const struct tu_subpass *subpass,
 508                      struct tu_cs *cs,
 509                      bool binning)
 510 {
 511    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 512    uint32_t cntl = 0;
 513    cntl |= A6XX_RB_RENDER_CNTL_UNK4;
 514    if (binning) {
 515       cntl |= A6XX_RB_RENDER_CNTL_BINNING;
 516    } else {
 517       uint32_t mrts_ubwc_enable = 0;
 518       for (uint32_t i = 0; i < subpass->color_count; ++i) {
 519          uint32_t a = subpass->color_attachments[i].attachment;
 520          if (a == VK_ATTACHMENT_UNUSED)
 521             continue;
 522
 523          const struct tu_image_view *iview = fb->attachments[a].attachment;
 524          if (iview->ubwc_enabled)
 525             mrts_ubwc_enable |= 1 << i;
 526       }
 527
 528       cntl |= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable);
 529
 530       const uint32_t a = subpass->depth_stencil_attachment.attachment;
 531       if (a != VK_ATTACHMENT_UNUSED) {
 532          const struct tu_image_view *iview = fb->attachments[a].attachment;
 533          if (iview->ubwc_enabled)
 534             cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH;
 535       }
 536
 537       /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
 538        * in order to set it correctly for the different subpasses. However,
 539        * that means the packets we're emitting also happen during binning. So
 540        * we need to guard the write on !BINNING at CP execution time.
 541        */
 542       tu_cs_reserve(cs, 3 + 4);
 543       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 544       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
 545                      CP_COND_REG_EXEC_0_GMEM | CP_COND_REG_EXEC_0_SYSMEM);
 546       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(4));
 547    }
 548
 549    tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
 550    tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
 551    tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
 552    tu_cs_emit(cs, cntl);
 553 }
 554
 555 static void
 556 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
 557 {
 558    const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
 559    uint32_t x1 = render_area->offset.x;
 560    uint32_t y1 = render_area->offset.y;
 561    uint32_t x2 = x1 + render_area->extent.width - 1;
 562    uint32_t y2 = y1 + render_area->extent.height - 1;
 563
 564    if (align) {
 565       x1 = x1 & ~(GMEM_ALIGN_W - 1);
 566       y1 = y1 & ~(GMEM_ALIGN_H - 1);
 567       x2 = ALIGN_POT(x2 + 1, GMEM_ALIGN_W) - 1;
 568       y2 = ALIGN_POT(y2 + 1, GMEM_ALIGN_H) - 1;
 569    }
 570
 571    tu_cs_emit_regs(cs,
 572                    A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
 573                    A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
 574 }
 575
 576 void
 577 tu6_emit_window_scissor(struct tu_cs *cs,
 578                         uint32_t x1,
 579                         uint32_t y1,
 580                         uint32_t x2,
 581                         uint32_t y2)
 582 {
 583    tu_cs_emit_regs(cs,
 584                    A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
 585                    A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
 586
 587    tu_cs_emit_regs(cs,
 588                    A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
 589                    A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
 590 }
 591
 592 void
 593 tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1)
 594 {
 595    tu_cs_emit_regs(cs,
 596                    A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
 597
 598    tu_cs_emit_regs(cs,
 599                    A6XX_RB_WINDOW_OFFSET2(.x = x1, .y = y1));
 600
 601    tu_cs_emit_regs(cs,
 602                    A6XX_SP_WINDOW_OFFSET(.x = x1, .y = y1));
 603
 604    tu_cs_emit_regs(cs,
 605                    A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
 606 }
 607
 608 static bool
 609 use_hw_binning(struct tu_cmd_buffer *cmd)
 610 {
 611    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 612
 613    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
 614       return false;
 615
 616    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN))
 617       return true;
 618
 619    return (tiling->tile_count.width * tiling->tile_count.height) > 2;
 620 }
 621
 622 static bool
 623 use_sysmem_rendering(struct tu_cmd_buffer *cmd)
 624 {
 625    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_SYSMEM))
 626       return true;
 627
 628    /* can't fit attachments into gmem */
 629    if (!cmd->state.pass->gmem_pixels)
 630       return true;
 631
 632    if (cmd->state.framebuffer->layers > 1)
 633       return true;
 634
 635    return cmd->state.tiling_config.force_sysmem;
 636 }
 637
 638 static void
 639 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
 640                      struct tu_cs *cs,
 641                      const struct tu_tile *tile)
 642 {
 643    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 644    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD));
 645
 646    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 647    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
 648
 649    const uint32_t x1 = tile->begin.x;
 650    const uint32_t y1 = tile->begin.y;
 651    const uint32_t x2 = tile->end.x - 1;
 652    const uint32_t y2 = tile->end.y - 1;
 653    tu6_emit_window_scissor(cs, x1, y1, x2, y2);
 654    tu6_emit_window_offset(cs, x1, y1);
 655
 656    tu_cs_emit_regs(cs,
 657                    A6XX_VPC_SO_OVERRIDE(.so_disable = false));
 658
 659    if (use_hw_binning(cmd)) {
 660       tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
 661
 662       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 663       tu_cs_emit(cs, 0x0);
 664
 665       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
 666       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
 667                      A6XX_CP_REG_TEST_0_BIT(0) |
 668                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
 669
 670       tu_cs_reserve(cs, 3 + 11);
 671       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 672       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
 673       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(11));
 674
 675       /* if (no overflow) */ {
 676          tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
 677          tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
 678                         CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
 679          tu_cs_emit_qw(cs, cmd->vsc_data.iova + tile->pipe * cmd->vsc_data_pitch);
 680          tu_cs_emit_qw(cs, cmd->vsc_data.iova + (tile->pipe * 4) + (32 * cmd->vsc_data_pitch));
 681          tu_cs_emit_qw(cs, cmd->vsc_data2.iova + (tile->pipe * cmd->vsc_data2_pitch));
 682
 683          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 684          tu_cs_emit(cs, 0x0);
 685
 686          /* use a NOP packet to skip over the 'else' side: */
 687          tu_cs_emit_pkt7(cs, CP_NOP, 2);
 688       } /* else */ {
 689          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 690          tu_cs_emit(cs, 0x1);
 691       }
 692
 693       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 694       tu_cs_emit(cs, 0x0);
 695    } else {
 696       tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 697       tu_cs_emit(cs, 0x1);
 698
 699       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 700       tu_cs_emit(cs, 0x0);
 701    }
 702 }
 703
 704 static void
 705 tu6_emit_sysmem_resolve(struct tu_cmd_buffer *cmd,
 706                         struct tu_cs *cs,
 707                         uint32_t a,
 708                         uint32_t gmem_a)
 709 {
 710    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 711    struct tu_image_view *dst = fb->attachments[a].attachment;
 712    struct tu_image_view *src = fb->attachments[gmem_a].attachment;
 713
 714    tu_resolve_sysmem(cmd, cs, src, dst, fb->layers, &cmd->state.tiling_config.render_area);
 715 }
 716
 717 static void
 718 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 719 {
 720    const struct tu_render_pass *pass = cmd->state.pass;
 721    const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
 722
 723    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
 724    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
 725                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
 726                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
 727    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
 728    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
 729
 730    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 731    tu_cs_emit(cs, 0x0);
 732
 733    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 734    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
 735
 736    tu6_emit_blit_scissor(cmd, cs, true);
 737
 738    for (uint32_t a = 0; a < pass->attachment_count; ++a) {
 739       if (pass->attachments[a].gmem_offset >= 0)
 740          tu_store_gmem_attachment(cmd, cs, a, a);
 741    }
 742
 743    if (subpass->resolve_attachments) {
 744       for (unsigned i = 0; i < subpass->color_count; i++) {
 745          uint32_t a = subpass->resolve_attachments[i].attachment;
 746          if (a != VK_ATTACHMENT_UNUSED)
 747             tu_store_gmem_attachment(cmd, cs, a,
 748                                      subpass->color_attachments[i].attachment);
 749       }
 750    }
 751 }
 752
 753 static void
 754 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
 755 {
 756    tu_cs_emit_regs(cs,
 757                    A6XX_PC_RESTART_INDEX(restart_index));
 758 }
 759
 760 static void
 761 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 762 {
 763    const struct tu_physical_device *phys_dev = cmd->device->physical_device;
 764
 765    tu6_emit_cache_flush(cmd, cs);
 766
 767    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
 768
 769    tu_cs_emit_regs(cs,
 770                    A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_bypass));
 771    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
 772    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
 773    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
 774    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
 775    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
 776    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
 777    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
 778    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
 779
 780    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
 781    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
 782    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
 783    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
 784    tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
 785    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
 786    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
 787    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
 788    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
 789    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
 790    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A982, 0);
 791    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
 792    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
 793    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_GS_SIV_CNTL, 0x0000ffff);
 794
 795    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
 796    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
 797    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
 798
 799    tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
 800
 801    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
 802
 803    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
 804    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
 805    tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
 806    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
 807    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
 808    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
 809    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
 810    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
 811    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
 812    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
 813    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
 814
 815    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
 816    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
 817
 818    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
 819    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
 820
 821    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
 822                         A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
 823
 824    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
 825    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
 826    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
 827    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
 828
 829    tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
 830    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
 831
 832    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
 833
 834    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
 835
 836    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
 837    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
 838    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
 839    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
 840    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
 841    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
 842    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
 843    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
 844    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
 845    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
 846    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
 847    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
 848    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
 849    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
 850
 851    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
 852
 853    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
 854
 855    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
 856
 857    /* we don't use this yet.. probably best to disable.. */
 858    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
 859    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
 860                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
 861                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
 862    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
 863    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
 864
 865    /* Set not to use streamout by default, */
 866    tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
 867    tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
 868    tu_cs_emit(cs, 0);
 869    tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
 870    tu_cs_emit(cs, 0);
 871
 872    tu_cs_emit_regs(cs,
 873                    A6XX_SP_HS_CTRL_REG0(0));
 874
 875    tu_cs_emit_regs(cs,
 876                    A6XX_SP_GS_CTRL_REG0(0));
 877
 878    tu_cs_emit_regs(cs,
 879                    A6XX_GRAS_LRZ_CNTL(0));
 880
 881    tu_cs_emit_regs(cs,
 882                    A6XX_RB_LRZ_CNTL(0));
 883
 884    tu_cs_emit_regs(cs,
 885                    A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo = &cmd->device->border_color));
 886    tu_cs_emit_regs(cs,
 887                    A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo = &cmd->device->border_color));
 888
 889    tu_cs_sanity_check(cs);
 890 }
 891
 892 static void
 893 tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 894 {
 895    unsigned seqno;
 896
 897    seqno = tu6_emit_event_write(cmd, cs, RB_DONE_TS, true);
 898
 899    tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
 900    tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
 901                   CP_WAIT_REG_MEM_0_POLL_MEMORY);
 902    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 903    tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(seqno));
 904    tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
 905    tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
 906
 907    seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
 908
 909    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4);
 910    tu_cs_emit(cs, CP_WAIT_MEM_GTE_0_RESERVED(0));
 911    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 912    tu_cs_emit(cs, CP_WAIT_MEM_GTE_3_REF(seqno));
 913 }
 914
 915 static void
 916 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 917 {
 918    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 919
 920    tu_cs_emit_regs(cs,
 921                    A6XX_VSC_BIN_SIZE(.width = tiling->tile0.extent.width,
 922                                      .height = tiling->tile0.extent.height),
 923                    A6XX_VSC_SIZE_ADDRESS(.bo = &cmd->vsc_data,
 924                                          .bo_offset = 32 * cmd->vsc_data_pitch));
 925
 926    tu_cs_emit_regs(cs,
 927                    A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
 928                                       .ny = tiling->tile_count.height));
 929
 930    tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
 931    for (unsigned i = 0; i < 32; i++)
 932       tu_cs_emit(cs, tiling->pipe_config[i]);
 933
 934    tu_cs_emit_regs(cs,
 935                    A6XX_VSC_PIPE_DATA2_ADDRESS(.bo = &cmd->vsc_data2),
 936                    A6XX_VSC_PIPE_DATA2_PITCH(cmd->vsc_data2_pitch),
 937                    A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd->vsc_data2.size));
 938
 939    tu_cs_emit_regs(cs,
 940                    A6XX_VSC_PIPE_DATA_ADDRESS(.bo = &cmd->vsc_data),
 941                    A6XX_VSC_PIPE_DATA_PITCH(cmd->vsc_data_pitch),
 942                    A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd->vsc_data.size));
 943 }
 944
 945 static void
 946 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 947 {
 948    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 949    const uint32_t used_pipe_count =
 950       tiling->pipe_count.width * tiling->pipe_count.height;
 951
 952    /* Clear vsc_scratch: */
 953    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
 954    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
 955    tu_cs_emit(cs, 0x0);
 956
 957    /* Check for overflow, write vsc_scratch if detected: */
 958    for (int i = 0; i < used_pipe_count; i++) {
 959       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
 960       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
 961             CP_COND_WRITE5_0_WRITE_MEMORY);
 962       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
 963       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
 964       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data_pitch));
 965       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
 966       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
 967       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_data_pitch));
 968
 969       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
 970       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
 971             CP_COND_WRITE5_0_WRITE_MEMORY);
 972       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
 973       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
 974       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data2_pitch));
 975       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
 976       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
 977       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_data2_pitch));
 978    }
 979
 980    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
 981
 982    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
 983
 984    tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
 985    tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
 986          CP_MEM_TO_REG_0_CNT(1 - 1));
 987    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
 988
 989    /*
 990     * This is a bit awkward, we really want a way to invert the
 991     * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
 992     * execute cmds to use hwbinning when a bit is *not* set.  This
 993     * dance is to invert OVERFLOW_FLAG_REG
 994     *
 995     * A CP_NOP packet is used to skip executing the 'else' clause
 996     * if (b0 set)..
 997     */
 998
 999    /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1000    tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1001    tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1002          A6XX_CP_REG_TEST_0_BIT(0) |
1003          A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1004
1005    tu_cs_reserve(cs, 3 + 7);
1006    tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1007    tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1008    tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(7));
1009
1010    /* if (b0 set) */ {
1011       /*
1012        * On overflow, mirror the value to control->vsc_overflow
1013        * which CPU is checking to detect overflow (see
1014        * check_vsc_overflow())
1015        */
1016       tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1017       tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
1018             CP_REG_TO_MEM_0_CNT(0));
1019       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_overflow));
1020
1021       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1022       tu_cs_emit(cs, 0x0);
1023
1024       tu_cs_emit_pkt7(cs, CP_NOP, 2);  /* skip 'else' when 'if' is taken */
1025    } /* else */ {
1026       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1027       tu_cs_emit(cs, 0x1);
1028    }
1029 }
1030
1031 static void
1032 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1033 {
1034    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1035    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1036
1037    uint32_t x1 = tiling->tile0.offset.x;
1038    uint32_t y1 = tiling->tile0.offset.y;
1039    uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
1040    uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
1041
1042    tu6_emit_window_scissor(cs, x1, y1, x2, y2);
1043
1044    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1045    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1046
1047    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1048    tu_cs_emit(cs, 0x1);
1049
1050    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1051    tu_cs_emit(cs, 0x1);
1052
1053    tu_cs_emit_wfi(cs);
1054
1055    tu_cs_emit_regs(cs,
1056                    A6XX_VFD_MODE_CNTL(.binning_pass = true));
1057
1058    update_vsc_pipe(cmd, cs);
1059
1060    tu_cs_emit_regs(cs,
1061                    A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1062
1063    tu_cs_emit_regs(cs,
1064                    A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1065
1066    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1067    tu_cs_emit(cs, UNK_2C);
1068
1069    tu_cs_emit_regs(cs,
1070                    A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
1071
1072    tu_cs_emit_regs(cs,
1073                    A6XX_SP_TP_WINDOW_OFFSET(.x = 0, .y = 0));
1074
1075    /* emit IB to binning drawcmds: */
1076    tu_cs_emit_call(cs, &cmd->draw_cs);
1077
1078    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1079    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1080                   CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1081                   CP_SET_DRAW_STATE__0_GROUP_ID(0));
1082    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1083    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1084
1085    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1086    tu_cs_emit(cs, UNK_2D);
1087
1088    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1089    tu6_cache_flush(cmd, cs);
1090
1091    tu_cs_emit_wfi(cs);
1092
1093    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1094
1095    emit_vsc_overflow_test(cmd, cs);
1096
1097    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1098    tu_cs_emit(cs, 0x0);
1099
1100    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1101    tu_cs_emit(cs, 0x0);
1102
1103    cmd->wait_for_idle = false;
1104 }
1105
1106 static void
1107 tu_emit_load_clear(struct tu_cmd_buffer *cmd,
1108                    const VkRenderPassBeginInfo *info)
1109 {
1110    struct tu_cs *cs = &cmd->draw_cs;
1111
1112    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
1113
1114    tu6_emit_blit_scissor(cmd, cs, true);
1115
1116    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1117       tu_load_gmem_attachment(cmd, cs, i, false);
1118
1119    tu6_emit_blit_scissor(cmd, cs, false);
1120
1121    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1122       tu_clear_gmem_attachment(cmd, cs, i, info);
1123
1124    tu_cond_exec_end(cs);
1125
1126    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
1127
1128    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1129       tu_clear_sysmem_attachment(cmd, cs, i, info);
1130
1131    tu_cond_exec_end(cs);
1132 }
1133
1134 static void
1135 tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1136                         const struct VkRect2D *renderArea)
1137 {
1138    const struct tu_physical_device *phys_dev = cmd->device->physical_device;
1139    const struct tu_framebuffer *fb = cmd->state.framebuffer;
1140
1141    assert(fb->width > 0 && fb->height > 0);
1142    tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
1143    tu6_emit_window_offset(cs, 0, 0);
1144
1145    tu6_emit_bin_size(cs, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1146
1147    tu6_emit_lrz_flush(cmd, cs);
1148
1149    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1150    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
1151
1152    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1153    tu_cs_emit(cs, 0x0);
1154
1155    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_COLOR, false);
1156    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH, false);
1157    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1158
1159    tu6_emit_wfi(cmd, cs);
1160    tu_cs_emit_regs(cs,
1161                    A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_bypass));
1162
1163    /* enable stream-out, with sysmem there is only one pass: */
1164    tu_cs_emit_regs(cs,
1165                    A6XX_VPC_SO_OVERRIDE(.so_disable = false));
1166
1167    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1168    tu_cs_emit(cs, 0x1);
1169
1170    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1171    tu_cs_emit(cs, 0x0);
1172
1173    tu_cs_sanity_check(cs);
1174 }
1175
1176 static void
1177 tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1178 {
1179    /* Do any resolves of the last subpass. These are handled in the
1180     * tile_store_ib in the gmem path.
1181     */
1182    const struct tu_subpass *subpass = cmd->state.subpass;
1183    if (subpass->resolve_attachments) {
1184       for (unsigned i = 0; i < subpass->color_count; i++) {
1185          uint32_t a = subpass->resolve_attachments[i].attachment;
1186          if (a != VK_ATTACHMENT_UNUSED)
1187             tu6_emit_sysmem_resolve(cmd, cs, a,
1188                                     subpass->color_attachments[i].attachment);
1189       }
1190    }
1191
1192    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1193
1194    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1195    tu_cs_emit(cs, 0x0);
1196
1197    tu6_emit_lrz_flush(cmd, cs);
1198
1199    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
1200    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
1201
1202    tu_cs_sanity_check(cs);
1203 }
1204
1205
1206 static void
1207 tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1208 {
1209    struct tu_physical_device *phys_dev = cmd->device->physical_device;
1210
1211    tu6_emit_lrz_flush(cmd, cs);
1212
1213    /* lrz clear? */
1214
1215    tu6_emit_cache_flush(cmd, cs);
1216
1217    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1218    tu_cs_emit(cs, 0x0);
1219
1220    /* TODO: flushing with barriers instead of blindly always flushing */
1221    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
1222    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
1223    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_COLOR, false);
1224    tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH, false);
1225
1226    tu_cs_emit_wfi(cs);
1227    tu_cs_emit_regs(cs,
1228                    A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_gmem, .gmem = 1));
1229
1230    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1231    if (use_hw_binning(cmd)) {
1232       /* enable stream-out during binning pass: */
1233       tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=false));
1234
1235       tu6_emit_bin_size(cs,
1236                         tiling->tile0.extent.width,
1237                         tiling->tile0.extent.height,
1238                         A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
1239
1240       tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true);
1241
1242       tu6_emit_binning_pass(cmd, cs);
1243
1244       /* and disable stream-out for draw pass: */
1245       tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=true));
1246
1247       tu6_emit_bin_size(cs,
1248                         tiling->tile0.extent.width,
1249                         tiling->tile0.extent.height,
1250                         A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
1251
1252       tu_cs_emit_regs(cs,
1253                       A6XX_VFD_MODE_CNTL(0));
1254
1255       tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
1256
1257       tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
1258
1259       tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1260       tu_cs_emit(cs, 0x1);
1261    } else {
1262       /* no binning pass, so enable stream-out for draw pass:: */
1263       tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=false));
1264
1265       tu6_emit_bin_size(cs,
1266                         tiling->tile0.extent.width,
1267                         tiling->tile0.extent.height,
1268                         0x6000000);
1269    }
1270
1271    tu_cs_sanity_check(cs);
1272 }
1273
1274 static void
1275 tu6_render_tile(struct tu_cmd_buffer *cmd,
1276                 struct tu_cs *cs,
1277                 const struct tu_tile *tile)
1278 {
1279    tu6_emit_tile_select(cmd, cs, tile);
1280
1281    tu_cs_emit_call(cs, &cmd->draw_cs);
1282    cmd->wait_for_idle = true;
1283
1284    if (use_hw_binning(cmd)) {
1285       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1286       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1287                      A6XX_CP_REG_TEST_0_BIT(0) |
1288                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1289
1290       tu_cs_reserve(cs, 3 + 2);
1291       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1292       tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
1293       tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(2));
1294
1295       /* if (no overflow) */ {
1296          tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1297          tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
1298       }
1299    }
1300
1301    tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1302
1303    tu_cs_sanity_check(cs);
1304 }
1305
1306 static void
1307 tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1308 {
1309    tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
1310
1311    tu_cs_emit_regs(cs,
1312                    A6XX_GRAS_LRZ_CNTL(0));
1313
1314    tu6_emit_lrz_flush(cmd, cs);
1315
1316    tu6_emit_event_write(cmd, cs, PC_CCU_RESOLVE_TS, true);
1317
1318    tu_cs_sanity_check(cs);
1319 }
1320
1321 static void
1322 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1323 {
1324    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1325
1326    tu6_tile_render_begin(cmd, &cmd->cs);
1327
1328    for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1329       for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1330          struct tu_tile tile;
1331          tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1332          tu6_render_tile(cmd, &cmd->cs, &tile);
1333       }
1334    }
1335
1336    tu6_tile_render_end(cmd, &cmd->cs);
1337 }
1338
1339 static void
1340 tu_cmd_render_sysmem(struct tu_cmd_buffer *cmd)
1341 {
1342    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1343
1344    tu6_sysmem_render_begin(cmd, &cmd->cs, &tiling->render_area);
1345
1346    tu_cs_emit_call(&cmd->cs, &cmd->draw_cs);
1347    cmd->wait_for_idle = true;
1348
1349    tu6_sysmem_render_end(cmd, &cmd->cs);
1350 }
1351
1352 static void
1353 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1354 {
1355    const uint32_t tile_store_space = 11 + (35 * 2) * cmd->state.pass->attachment_count;
1356    struct tu_cs sub_cs;
1357
1358    VkResult result =
1359       tu_cs_begin_sub_stream(&cmd->sub_cs, tile_store_space, &sub_cs);
1360    if (result != VK_SUCCESS) {
1361       cmd->record_result = result;
1362       return;
1363    }
1364
1365    /* emit to tile-store sub_cs */
1366    tu6_emit_tile_store(cmd, &sub_cs);
1367
1368    cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1369 }
1370
1371 static void
1372 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1373                             const VkRect2D *render_area)
1374 {
1375    const struct tu_device *dev = cmd->device;
1376    struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1377
1378    tiling->render_area = *render_area;
1379    tiling->force_sysmem = false;
1380
1381    tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass->gmem_pixels);
1382    tu_tiling_config_update_pipe_layout(tiling, dev);
1383    tu_tiling_config_update_pipes(tiling, dev);
1384 }
1385
1386 const struct tu_dynamic_state default_dynamic_state = {
1387    .viewport =
1388      {
1389        .count = 0,
1390      },
1391    .scissor =
1392      {
1393        .count = 0,
1394      },
1395    .line_width = 1.0f,
1396    .depth_bias =
1397      {
1398        .bias = 0.0f,
1399        .clamp = 0.0f,
1400        .slope = 0.0f,
1401      },
1402    .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1403    .depth_bounds =
1404      {
1405        .min = 0.0f,
1406        .max = 1.0f,
1407      },
1408    .stencil_compare_mask =
1409      {
1410        .front = ~0u,
1411        .back = ~0u,
1412      },
1413    .stencil_write_mask =
1414      {
1415        .front = ~0u,
1416        .back = ~0u,
1417      },
1418    .stencil_reference =
1419      {
1420        .front = 0u,
1421        .back = 0u,
1422      },
1423 };
1424
1425 static void UNUSED /* FINISHME */
1426 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1427                       const struct tu_dynamic_state *src)
1428 {
1429    struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1430    uint32_t copy_mask = src->mask;
1431    uint32_t dest_mask = 0;
1432
1433    tu_use_args(cmd_buffer); /* FINISHME */
1434
1435    /* Make sure to copy the number of viewports/scissors because they can
1436     * only be specified at pipeline creation time.
1437     */
1438    dest->viewport.count = src->viewport.count;
1439    dest->scissor.count = src->scissor.count;
1440    dest->discard_rectangle.count = src->discard_rectangle.count;
1441
1442    if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1443       if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1444                  src->viewport.count * sizeof(VkViewport))) {
1445          typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1446                       src->viewport.count);
1447          dest_mask |= TU_DYNAMIC_VIEWPORT;
1448       }
1449    }
1450
1451    if (copy_mask & TU_DYNAMIC_SCISSOR) {
1452       if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1453                  src->scissor.count * sizeof(VkRect2D))) {
1454          typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1455                       src->scissor.count);
1456          dest_mask |= TU_DYNAMIC_SCISSOR;
1457       }
1458    }
1459
1460    if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1461       if (dest->line_width != src->line_width) {
1462          dest->line_width = src->line_width;
1463          dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1464       }
1465    }
1466
1467    if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1468       if (memcmp(&dest->depth_bias, &src->depth_bias,
1469                  sizeof(src->depth_bias))) {
1470          dest->depth_bias = src->depth_bias;
1471          dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1472       }
1473    }
1474
1475    if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1476       if (memcmp(&dest->blend_constants, &src->blend_constants,
1477                  sizeof(src->blend_constants))) {
1478          typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1479          dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1480       }
1481    }
1482
1483    if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1484       if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1485                  sizeof(src->depth_bounds))) {
1486          dest->depth_bounds = src->depth_bounds;
1487          dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1488       }
1489    }
1490
1491    if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1492       if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1493                  sizeof(src->stencil_compare_mask))) {
1494          dest->stencil_compare_mask = src->stencil_compare_mask;
1495          dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1496       }
1497    }
1498
1499    if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1500       if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1501                  sizeof(src->stencil_write_mask))) {
1502          dest->stencil_write_mask = src->stencil_write_mask;
1503          dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1504       }
1505    }
1506
1507    if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1508       if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1509                  sizeof(src->stencil_reference))) {
1510          dest->stencil_reference = src->stencil_reference;
1511          dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1512       }
1513    }
1514
1515    if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1516       if (memcmp(&dest->discard_rectangle.rectangles,
1517                  &src->discard_rectangle.rectangles,
1518                  src->discard_rectangle.count * sizeof(VkRect2D))) {
1519          typed_memcpy(dest->discard_rectangle.rectangles,
1520                       src->discard_rectangle.rectangles,
1521                       src->discard_rectangle.count);
1522          dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1523       }
1524    }
1525 }
1526
1527 static VkResult
1528 tu_create_cmd_buffer(struct tu_device *device,
1529                      struct tu_cmd_pool *pool,
1530                      VkCommandBufferLevel level,
1531                      VkCommandBuffer *pCommandBuffer)
1532 {
1533    struct tu_cmd_buffer *cmd_buffer;
1534    cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1535                           VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1536    if (cmd_buffer == NULL)
1537       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1538
1539    cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1540    cmd_buffer->device = device;
1541    cmd_buffer->pool = pool;
1542    cmd_buffer->level = level;
1543
1544    if (pool) {
1545       list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1546       cmd_buffer->queue_family_index = pool->queue_family_index;
1547
1548    } else {
1549       /* Init the pool_link so we can safely call list_del when we destroy
1550        * the command buffer
1551        */
1552       list_inithead(&cmd_buffer->pool_link);
1553       cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1554    }
1555
1556    tu_bo_list_init(&cmd_buffer->bo_list);
1557    tu_cs_init(&cmd_buffer->cs, device, TU_CS_MODE_GROW, 4096);
1558    tu_cs_init(&cmd_buffer->draw_cs, device, TU_CS_MODE_GROW, 4096);
1559    tu_cs_init(&cmd_buffer->draw_epilogue_cs, device, TU_CS_MODE_GROW, 4096);
1560    tu_cs_init(&cmd_buffer->sub_cs, device, TU_CS_MODE_SUB_STREAM, 2048);
1561
1562    *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1563
1564    list_inithead(&cmd_buffer->upload.list);
1565
1566    VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1567    if (result != VK_SUCCESS)
1568       goto fail_scratch_bo;
1569
1570    /* TODO: resize on overflow */
1571    cmd_buffer->vsc_data_pitch = device->vsc_data_pitch;
1572    cmd_buffer->vsc_data2_pitch = device->vsc_data2_pitch;
1573    cmd_buffer->vsc_data = device->vsc_data;
1574    cmd_buffer->vsc_data2 = device->vsc_data2;
1575
1576    return VK_SUCCESS;
1577
1578 fail_scratch_bo:
1579    list_del(&cmd_buffer->pool_link);
1580    return result;
1581 }
1582
1583 static void
1584 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1585 {
1586    tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1587
1588    list_del(&cmd_buffer->pool_link);
1589
1590    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1591       free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1592
1593    tu_cs_finish(&cmd_buffer->cs);
1594    tu_cs_finish(&cmd_buffer->draw_cs);
1595    tu_cs_finish(&cmd_buffer->draw_epilogue_cs);
1596    tu_cs_finish(&cmd_buffer->sub_cs);
1597
1598    tu_bo_list_destroy(&cmd_buffer->bo_list);
1599    vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1600 }
1601
1602 static VkResult
1603 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1604 {
1605    cmd_buffer->wait_for_idle = true;
1606
1607    cmd_buffer->record_result = VK_SUCCESS;
1608
1609    tu_bo_list_reset(&cmd_buffer->bo_list);
1610    tu_cs_reset(&cmd_buffer->cs);
1611    tu_cs_reset(&cmd_buffer->draw_cs);
1612    tu_cs_reset(&cmd_buffer->draw_epilogue_cs);
1613    tu_cs_reset(&cmd_buffer->sub_cs);
1614
1615    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1616       cmd_buffer->descriptors[i].valid = 0;
1617       cmd_buffer->descriptors[i].push_dirty = false;
1618    }
1619
1620    cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1621
1622    return cmd_buffer->record_result;
1623 }
1624
1625 VkResult
1626 tu_AllocateCommandBuffers(VkDevice _device,
1627                           const VkCommandBufferAllocateInfo *pAllocateInfo,
1628                           VkCommandBuffer *pCommandBuffers)
1629 {
1630    TU_FROM_HANDLE(tu_device, device, _device);
1631    TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1632
1633    VkResult result = VK_SUCCESS;
1634    uint32_t i;
1635
1636    for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1637
1638       if (!list_is_empty(&pool->free_cmd_buffers)) {
1639          struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1640             &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1641
1642          list_del(&cmd_buffer->pool_link);
1643          list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1644
1645          result = tu_reset_cmd_buffer(cmd_buffer);
1646          cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1647          cmd_buffer->level = pAllocateInfo->level;
1648
1649          pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1650       } else {
1651          result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1652                                        &pCommandBuffers[i]);
1653       }
1654       if (result != VK_SUCCESS)
1655          break;
1656    }
1657
1658    if (result != VK_SUCCESS) {
1659       tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1660                             pCommandBuffers);
1661
1662       /* From the Vulkan 1.0.66 spec:
1663        *
1664        * "vkAllocateCommandBuffers can be used to create multiple
1665        *  command buffers. If the creation of any of those command
1666        *  buffers fails, the implementation must destroy all
1667        *  successfully created command buffer objects from this
1668        *  command, set all entries of the pCommandBuffers array to
1669        *  NULL and return the error."
1670        */
1671       memset(pCommandBuffers, 0,
1672              sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1673    }
1674
1675    return result;
1676 }
1677
1678 void
1679 tu_FreeCommandBuffers(VkDevice device,
1680                       VkCommandPool commandPool,
1681                       uint32_t commandBufferCount,
1682                       const VkCommandBuffer *pCommandBuffers)
1683 {
1684    for (uint32_t i = 0; i < commandBufferCount; i++) {
1685       TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1686
1687       if (cmd_buffer) {
1688          if (cmd_buffer->pool) {
1689             list_del(&cmd_buffer->pool_link);
1690             list_addtail(&cmd_buffer->pool_link,
1691                          &cmd_buffer->pool->free_cmd_buffers);
1692          } else
1693             tu_cmd_buffer_destroy(cmd_buffer);
1694       }
1695    }
1696 }
1697
1698 VkResult
1699 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1700                       VkCommandBufferResetFlags flags)
1701 {
1702    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1703    return tu_reset_cmd_buffer(cmd_buffer);
1704 }
1705
1706 VkResult
1707 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1708                       const VkCommandBufferBeginInfo *pBeginInfo)
1709 {
1710    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1711    VkResult result = VK_SUCCESS;
1712
1713    if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1714       /* If the command buffer has already been resetted with
1715        * vkResetCommandBuffer, no need to do it again.
1716        */
1717       result = tu_reset_cmd_buffer(cmd_buffer);
1718       if (result != VK_SUCCESS)
1719          return result;
1720    }
1721
1722    memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1723    cmd_buffer->usage_flags = pBeginInfo->flags;
1724
1725    tu_cs_begin(&cmd_buffer->cs);
1726    tu_cs_begin(&cmd_buffer->draw_cs);
1727    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
1728
1729    cmd_buffer->scratch_seqno = 0;
1730
1731    /* setup initial configuration into command buffer */
1732    if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1733       switch (cmd_buffer->queue_family_index) {
1734       case TU_QUEUE_GENERAL:
1735          tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1736          break;
1737       default:
1738          break;
1739       }
1740    } else if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
1741               (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
1742       assert(pBeginInfo->pInheritanceInfo);
1743       cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1744       cmd_buffer->state.subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1745    }
1746
1747    cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1748
1749    return VK_SUCCESS;
1750 }
1751
1752 void
1753 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1754                         uint32_t firstBinding,
1755                         uint32_t bindingCount,
1756                         const VkBuffer *pBuffers,
1757                         const VkDeviceSize *pOffsets)
1758 {
1759    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1760
1761    assert(firstBinding + bindingCount <= MAX_VBS);
1762
1763    for (uint32_t i = 0; i < bindingCount; i++) {
1764       cmd->state.vb.buffers[firstBinding + i] =
1765          tu_buffer_from_handle(pBuffers[i]);
1766       cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1767    }
1768
1769    /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1770    cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1771 }
1772
1773 void
1774 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1775                       VkBuffer buffer,
1776                       VkDeviceSize offset,
1777                       VkIndexType indexType)
1778 {
1779    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1780    TU_FROM_HANDLE(tu_buffer, buf, buffer);
1781
1782    /* initialize/update the restart index */
1783    if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1784       struct tu_cs *draw_cs = &cmd->draw_cs;
1785
1786       tu6_emit_restart_index(
1787          draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1788
1789       tu_cs_sanity_check(draw_cs);
1790    }
1791
1792    /* track the BO */
1793    if (cmd->state.index_buffer != buf)
1794       tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1795
1796    cmd->state.index_buffer = buf;
1797    cmd->state.index_offset = offset;
1798    cmd->state.index_type = indexType;
1799 }
1800
1801 void
1802 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1803                          VkPipelineBindPoint pipelineBindPoint,
1804                          VkPipelineLayout _layout,
1805                          uint32_t firstSet,
1806                          uint32_t descriptorSetCount,
1807                          const VkDescriptorSet *pDescriptorSets,
1808                          uint32_t dynamicOffsetCount,
1809                          const uint32_t *pDynamicOffsets)
1810 {
1811    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1812    TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1813    unsigned dyn_idx = 0;
1814
1815    struct tu_descriptor_state *descriptors_state =
1816       tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1817
1818    for (unsigned i = 0; i < descriptorSetCount; ++i) {
1819       unsigned idx = i + firstSet;
1820       TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1821
1822       descriptors_state->sets[idx] = set;
1823       descriptors_state->valid |= (1u << idx);
1824
1825       /* Note: the actual input attachment indices come from the shader
1826        * itself, so we can't generate the patched versions of these until
1827        * draw time when both the pipeline and descriptors are bound and
1828        * we're inside the render pass.
1829        */
1830       unsigned dst_idx = layout->set[idx].input_attachment_start;
1831       memcpy(&descriptors_state->input_attachments[dst_idx * A6XX_TEX_CONST_DWORDS],
1832              set->dynamic_descriptors,
1833              set->layout->input_attachment_count * A6XX_TEX_CONST_DWORDS * 4);
1834
1835       for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1836          /* Dynamic buffers come after input attachments in the descriptor set
1837           * itself, but due to how the Vulkan descriptor set binding works, we
1838           * have to put input attachments and dynamic buffers in separate
1839           * buffers in the descriptor_state and then combine them at draw
1840           * time. Binding a descriptor set only invalidates the descriptor
1841           * sets after it, but if we try to tightly pack the descriptors after
1842           * the input attachments then we could corrupt dynamic buffers in the
1843           * descriptor set before it, or we'd have to move all the dynamic
1844           * buffers over. We just put them into separate buffers to make
1845           * binding as well as the later patching of input attachments easy.
1846           */
1847          unsigned src_idx = j + set->layout->input_attachment_count;
1848          unsigned dst_idx = j + layout->set[idx].dynamic_offset_start;
1849          assert(dyn_idx < dynamicOffsetCount);
1850
1851          uint32_t *dst =
1852             &descriptors_state->dynamic_descriptors[dst_idx * A6XX_TEX_CONST_DWORDS];
1853          uint32_t *src =
1854             &set->dynamic_descriptors[src_idx * A6XX_TEX_CONST_DWORDS];
1855          uint32_t offset = pDynamicOffsets[dyn_idx];
1856
1857          /* Patch the storage/uniform descriptors right away. */
1858          if (layout->set[idx].layout->dynamic_ubo & (1 << j)) {
1859             /* Note: we can assume here that the addition won't roll over and
1860              * change the SIZE field.
1861              */
1862             uint64_t va = src[0] | ((uint64_t)src[1] << 32);
1863             va += offset;
1864             dst[0] = va;
1865             dst[1] = va >> 32;
1866          } else {
1867             memcpy(dst, src, A6XX_TEX_CONST_DWORDS * 4);
1868             /* Note: A6XX_IBO_5_DEPTH is always 0 */
1869             uint64_t va = dst[4] | ((uint64_t)dst[5] << 32);
1870             va += offset;
1871             dst[4] = va;
1872             dst[5] = va >> 32;
1873          }
1874       }
1875    }
1876
1877    if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE)
1878       cmd_buffer->state.dirty |= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS;
1879    else
1880       cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
1881 }
1882
1883 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,
1884                                            uint32_t firstBinding,
1885                                            uint32_t bindingCount,
1886                                            const VkBuffer *pBuffers,
1887                                            const VkDeviceSize *pOffsets,
1888                                            const VkDeviceSize *pSizes)
1889 {
1890    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1891    assert(firstBinding + bindingCount <= IR3_MAX_SO_BUFFERS);
1892
1893    for (uint32_t i = 0; i < bindingCount; i++) {
1894       uint32_t idx = firstBinding + i;
1895       TU_FROM_HANDLE(tu_buffer, buf, pBuffers[i]);
1896
1897       if (pOffsets[i] != 0)
1898          cmd->state.streamout_reset |= 1 << idx;
1899
1900       cmd->state.streamout_buf.buffers[idx] = buf;
1901       cmd->state.streamout_buf.offsets[idx] = pOffsets[i];
1902       cmd->state.streamout_buf.sizes[idx] = pSizes[i];
1903
1904       cmd->state.streamout_enabled |= 1 << idx;
1905    }
1906
1907    cmd->state.dirty |= TU_CMD_DIRTY_STREAMOUT_BUFFERS;
1908 }
1909
1910 void tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,
1911                                        uint32_t firstCounterBuffer,
1912                                        uint32_t counterBufferCount,
1913                                        const VkBuffer *pCounterBuffers,
1914                                        const VkDeviceSize *pCounterBufferOffsets)
1915 {
1916    assert(firstCounterBuffer + counterBufferCount <= IR3_MAX_SO_BUFFERS);
1917    /* TODO do something with counter buffer? */
1918 }
1919
1920 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,
1921                                        uint32_t firstCounterBuffer,
1922                                        uint32_t counterBufferCount,
1923                                        const VkBuffer *pCounterBuffers,
1924                                        const VkDeviceSize *pCounterBufferOffsets)
1925 {
1926    assert(firstCounterBuffer + counterBufferCount <= IR3_MAX_SO_BUFFERS);
1927    /* TODO do something with counter buffer? */
1928
1929    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1930    cmd->state.streamout_enabled = 0;
1931 }
1932
1933 void
1934 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
1935                     VkPipelineLayout layout,
1936                     VkShaderStageFlags stageFlags,
1937                     uint32_t offset,
1938                     uint32_t size,
1939                     const void *pValues)
1940 {
1941    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1942    memcpy((void*) cmd->push_constants + offset, pValues, size);
1943    cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
1944 }
1945
1946 VkResult
1947 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
1948 {
1949    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1950
1951    if (cmd_buffer->scratch_seqno) {
1952       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
1953                      MSM_SUBMIT_BO_WRITE);
1954    }
1955
1956    if (cmd_buffer->use_vsc_data) {
1957       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data,
1958                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1959       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data2,
1960                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
1961    }
1962
1963    tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->device->border_color,
1964                   MSM_SUBMIT_BO_READ);
1965
1966    for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
1967       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
1968                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1969    }
1970
1971    for (uint32_t i = 0; i < cmd_buffer->draw_epilogue_cs.bo_count; i++) {
1972       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_epilogue_cs.bos[i],
1973                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1974    }
1975
1976    for (uint32_t i = 0; i < cmd_buffer->sub_cs.bo_count; i++) {
1977       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->sub_cs.bos[i],
1978                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
1979    }
1980
1981    tu_cs_end(&cmd_buffer->cs);
1982    tu_cs_end(&cmd_buffer->draw_cs);
1983    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
1984
1985    cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
1986
1987    return cmd_buffer->record_result;
1988 }
1989
1990 void
1991 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
1992                    VkPipelineBindPoint pipelineBindPoint,
1993                    VkPipeline _pipeline)
1994 {
1995    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1996    TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1997
1998    switch (pipelineBindPoint) {
1999    case VK_PIPELINE_BIND_POINT_GRAPHICS:
2000       cmd->state.pipeline = pipeline;
2001       cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
2002       break;
2003    case VK_PIPELINE_BIND_POINT_COMPUTE:
2004       cmd->state.compute_pipeline = pipeline;
2005       cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
2006       break;
2007    default:
2008       unreachable("unrecognized pipeline bind point");
2009       break;
2010    }
2011
2012    tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2013                   MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2014    for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2015       tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2016                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2017    }
2018 }
2019
2020 void
2021 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2022                   uint32_t firstViewport,
2023                   uint32_t viewportCount,
2024                   const VkViewport *pViewports)
2025 {
2026    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2027
2028    assert(firstViewport == 0 && viewportCount == 1);
2029    cmd->state.dynamic.viewport.viewports[0] = pViewports[0];
2030    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_VIEWPORT;
2031 }
2032
2033 void
2034 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2035                  uint32_t firstScissor,
2036                  uint32_t scissorCount,
2037                  const VkRect2D *pScissors)
2038 {
2039    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2040
2041    assert(firstScissor == 0 && scissorCount == 1);
2042    cmd->state.dynamic.scissor.scissors[0] = pScissors[0];
2043    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_SCISSOR;
2044 }
2045
2046 void
2047 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2048 {
2049    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2050
2051    cmd->state.dynamic.line_width = lineWidth;
2052
2053    /* line width depends on VkPipelineRasterizationStateCreateInfo */
2054    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2055 }
2056
2057 void
2058 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2059                    float depthBiasConstantFactor,
2060                    float depthBiasClamp,
2061                    float depthBiasSlopeFactor)
2062 {
2063    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2064    struct tu_cs *draw_cs = &cmd->draw_cs;
2065
2066    tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
2067                        depthBiasSlopeFactor);
2068
2069    tu_cs_sanity_check(draw_cs);
2070 }
2071
2072 void
2073 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2074                         const float blendConstants[4])
2075 {
2076    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2077    struct tu_cs *draw_cs = &cmd->draw_cs;
2078
2079    tu6_emit_blend_constants(draw_cs, blendConstants);
2080
2081    tu_cs_sanity_check(draw_cs);
2082 }
2083
2084 void
2085 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2086                      float minDepthBounds,
2087                      float maxDepthBounds)
2088 {
2089 }
2090
2091 void
2092 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2093                             VkStencilFaceFlags faceMask,
2094                             uint32_t compareMask)
2095 {
2096    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2097
2098    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2099       cmd->state.dynamic.stencil_compare_mask.front = compareMask;
2100    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2101       cmd->state.dynamic.stencil_compare_mask.back = compareMask;
2102
2103    /* the front/back compare masks must be updated together */
2104    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2105 }
2106
2107 void
2108 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2109                           VkStencilFaceFlags faceMask,
2110                           uint32_t writeMask)
2111 {
2112    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2113
2114    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2115       cmd->state.dynamic.stencil_write_mask.front = writeMask;
2116    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2117       cmd->state.dynamic.stencil_write_mask.back = writeMask;
2118
2119    /* the front/back write masks must be updated together */
2120    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2121 }
2122
2123 void
2124 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2125                           VkStencilFaceFlags faceMask,
2126                           uint32_t reference)
2127 {
2128    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2129
2130    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2131       cmd->state.dynamic.stencil_reference.front = reference;
2132    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2133       cmd->state.dynamic.stencil_reference.back = reference;
2134
2135    /* the front/back references must be updated together */
2136    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2137 }
2138
2139 void
2140 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer,
2141                             const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
2142 {
2143    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2144
2145    tu6_emit_sample_locations(&cmd->draw_cs, pSampleLocationsInfo);
2146 }
2147
2148 void
2149 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2150                       uint32_t commandBufferCount,
2151                       const VkCommandBuffer *pCmdBuffers)
2152 {
2153    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2154    VkResult result;
2155
2156    assert(commandBufferCount > 0);
2157
2158    for (uint32_t i = 0; i < commandBufferCount; i++) {
2159       TU_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
2160
2161       result = tu_bo_list_merge(&cmd->bo_list, &secondary->bo_list);
2162       if (result != VK_SUCCESS) {
2163          cmd->record_result = result;
2164          break;
2165       }
2166
2167       if (secondary->usage_flags &
2168           VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2169          assert(tu_cs_is_empty(&secondary->cs));
2170
2171          result = tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
2172          if (result != VK_SUCCESS) {
2173             cmd->record_result = result;
2174             break;
2175          }
2176
2177          result = tu_cs_add_entries(&cmd->draw_epilogue_cs,
2178                &secondary->draw_epilogue_cs);
2179          if (result != VK_SUCCESS) {
2180             cmd->record_result = result;
2181             break;
2182          }
2183       } else {
2184          assert(tu_cs_is_empty(&secondary->draw_cs));
2185          assert(tu_cs_is_empty(&secondary->draw_epilogue_cs));
2186
2187          for (uint32_t j = 0; j < secondary->cs.bo_count; j++) {
2188             tu_bo_list_add(&cmd->bo_list, secondary->cs.bos[j],
2189                            MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2190          }
2191
2192          tu_cs_add_entries(&cmd->cs, &secondary->cs);
2193       }
2194    }
2195    cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
2196 }
2197
2198 VkResult
2199 tu_CreateCommandPool(VkDevice _device,
2200                      const VkCommandPoolCreateInfo *pCreateInfo,
2201                      const VkAllocationCallbacks *pAllocator,
2202                      VkCommandPool *pCmdPool)
2203 {
2204    TU_FROM_HANDLE(tu_device, device, _device);
2205    struct tu_cmd_pool *pool;
2206
2207    pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2208                     VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2209    if (pool == NULL)
2210       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2211
2212    if (pAllocator)
2213       pool->alloc = *pAllocator;
2214    else
2215       pool->alloc = device->alloc;
2216
2217    list_inithead(&pool->cmd_buffers);
2218    list_inithead(&pool->free_cmd_buffers);
2219
2220    pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2221
2222    *pCmdPool = tu_cmd_pool_to_handle(pool);
2223
2224    return VK_SUCCESS;
2225 }
2226
2227 void
2228 tu_DestroyCommandPool(VkDevice _device,
2229                       VkCommandPool commandPool,
2230                       const VkAllocationCallbacks *pAllocator)
2231 {
2232    TU_FROM_HANDLE(tu_device, device, _device);
2233    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2234
2235    if (!pool)
2236       return;
2237
2238    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2239                             &pool->cmd_buffers, pool_link)
2240    {
2241       tu_cmd_buffer_destroy(cmd_buffer);
2242    }
2243
2244    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2245                             &pool->free_cmd_buffers, pool_link)
2246    {
2247       tu_cmd_buffer_destroy(cmd_buffer);
2248    }
2249
2250    vk_free2(&device->alloc, pAllocator, pool);
2251 }
2252
2253 VkResult
2254 tu_ResetCommandPool(VkDevice device,
2255                     VkCommandPool commandPool,
2256                     VkCommandPoolResetFlags flags)
2257 {
2258    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2259    VkResult result;
2260
2261    list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2262                        pool_link)
2263    {
2264       result = tu_reset_cmd_buffer(cmd_buffer);
2265       if (result != VK_SUCCESS)
2266          return result;
2267    }
2268
2269    return VK_SUCCESS;
2270 }
2271
2272 void
2273 tu_TrimCommandPool(VkDevice device,
2274                    VkCommandPool commandPool,
2275                    VkCommandPoolTrimFlags flags)
2276 {
2277    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2278
2279    if (!pool)
2280       return;
2281
2282    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2283                             &pool->free_cmd_buffers, pool_link)
2284    {
2285       tu_cmd_buffer_destroy(cmd_buffer);
2286    }
2287 }
2288
2289 void
2290 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2291                       const VkRenderPassBeginInfo *pRenderPassBegin,
2292                       VkSubpassContents contents)
2293 {
2294    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2295    TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2296    TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
2297
2298    cmd->state.pass = pass;
2299    cmd->state.subpass = pass->subpasses;
2300    cmd->state.framebuffer = fb;
2301
2302    tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
2303    tu_cmd_prepare_tile_store_ib(cmd);
2304
2305    tu_emit_load_clear(cmd, pRenderPassBegin);
2306
2307    tu6_emit_zs(cmd, cmd->state.subpass, &cmd->draw_cs);
2308    tu6_emit_mrt(cmd, cmd->state.subpass, &cmd->draw_cs);
2309    tu6_emit_msaa(&cmd->draw_cs, cmd->state.subpass->samples);
2310    tu6_emit_render_cntl(cmd, cmd->state.subpass, &cmd->draw_cs, false);
2311
2312    /* note: use_hw_binning only checks tiling config */
2313    if (use_hw_binning(cmd))
2314       cmd->use_vsc_data = true;
2315
2316    for (uint32_t i = 0; i < fb->attachment_count; ++i) {
2317       const struct tu_image_view *iview = fb->attachments[i].attachment;
2318       tu_bo_list_add(&cmd->bo_list, iview->image->bo,
2319                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2320    }
2321
2322    /* Flag input attachment descriptors for re-emission if necessary */
2323    cmd->state.dirty |= TU_CMD_DIRTY_INPUT_ATTACHMENTS;
2324 }
2325
2326 void
2327 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
2328                        const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2329                        const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2330 {
2331    tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2332                          pSubpassBeginInfo->contents);
2333 }
2334
2335 void
2336 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2337 {
2338    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2339    const struct tu_render_pass *pass = cmd->state.pass;
2340    struct tu_cs *cs = &cmd->draw_cs;
2341
2342    const struct tu_subpass *subpass = cmd->state.subpass++;
2343
2344    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
2345
2346    if (subpass->resolve_attachments) {
2347       tu6_emit_blit_scissor(cmd, cs, true);
2348
2349       for (unsigned i = 0; i < subpass->color_count; i++) {
2350          uint32_t a = subpass->resolve_attachments[i].attachment;
2351          if (a == VK_ATTACHMENT_UNUSED)
2352             continue;
2353
2354          tu_store_gmem_attachment(cmd, cs, a,
2355                                   subpass->color_attachments[i].attachment);
2356
2357          if (pass->attachments[a].gmem_offset < 0)
2358             continue;
2359
2360          /* TODO:
2361           * check if the resolved attachment is needed by later subpasses,
2362           * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2363           */
2364          tu_finishme("missing GMEM->GMEM resolve path\n");
2365          tu_load_gmem_attachment(cmd, cs, a, true);
2366       }
2367    }
2368
2369    tu_cond_exec_end(cs);
2370
2371    tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
2372
2373    /* Emit flushes so that input attachments will read the correct value.
2374     * TODO: use subpass dependencies to flush or not
2375     */
2376    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
2377    tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
2378
2379    if (subpass->resolve_attachments) {
2380       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2381
2382       for (unsigned i = 0; i < subpass->color_count; i++) {
2383          uint32_t a = subpass->resolve_attachments[i].attachment;
2384          if (a == VK_ATTACHMENT_UNUSED)
2385             continue;
2386
2387          tu6_emit_sysmem_resolve(cmd, cs, a,
2388                                  subpass->color_attachments[i].attachment);
2389       }
2390
2391       tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
2392    }
2393
2394    tu_cond_exec_end(cs);
2395
2396    /* subpass->input_count > 0 then texture cache invalidate is likely to be needed */
2397    if (cmd->state.subpass->input_count)
2398       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2399
2400    /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2401    tu6_emit_zs(cmd, cmd->state.subpass, cs);
2402    tu6_emit_mrt(cmd, cmd->state.subpass, cs);
2403    tu6_emit_msaa(cs, cmd->state.subpass->samples);
2404    tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, false);
2405
2406    /* Flag input attachment descriptors for re-emission if necessary */
2407    cmd->state.dirty |= TU_CMD_DIRTY_INPUT_ATTACHMENTS;
2408 }
2409
2410 void
2411 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
2412                    const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2413                    const VkSubpassEndInfoKHR *pSubpassEndInfo)
2414 {
2415    tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2416 }
2417
2418 struct tu_draw_info
2419 {
2420    /**
2421     * Number of vertices.
2422     */
2423    uint32_t count;
2424
2425    /**
2426     * Index of the first vertex.
2427     */
2428    int32_t vertex_offset;
2429
2430    /**
2431     * First instance id.
2432     */
2433    uint32_t first_instance;
2434
2435    /**
2436     * Number of instances.
2437     */
2438    uint32_t instance_count;
2439
2440    /**
2441     * First index (indexed draws only).
2442     */
2443    uint32_t first_index;
2444
2445    /**
2446     * Whether it's an indexed draw.
2447     */
2448    bool indexed;
2449
2450    /**
2451     * Indirect draw parameters resource.
2452     */
2453    struct tu_buffer *indirect;
2454    uint64_t indirect_offset;
2455    uint32_t stride;
2456
2457    /**
2458     * Draw count parameters resource.
2459     */
2460    struct tu_buffer *count_buffer;
2461    uint64_t count_buffer_offset;
2462
2463    /**
2464     * Stream output parameters resource.
2465     */
2466    struct tu_buffer *streamout_buffer;
2467    uint64_t streamout_buffer_offset;
2468 };
2469
2470 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2471 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2472 #define ENABLE_NON_GMEM (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_SYSMEM)
2473
2474 enum tu_draw_state_group_id
2475 {
2476    TU_DRAW_STATE_PROGRAM,
2477    TU_DRAW_STATE_PROGRAM_BINNING,
2478    TU_DRAW_STATE_VI,
2479    TU_DRAW_STATE_VI_BINNING,
2480    TU_DRAW_STATE_VP,
2481    TU_DRAW_STATE_RAST,
2482    TU_DRAW_STATE_DS,
2483    TU_DRAW_STATE_BLEND,
2484    TU_DRAW_STATE_VS_CONST,
2485    TU_DRAW_STATE_GS_CONST,
2486    TU_DRAW_STATE_FS_CONST,
2487    TU_DRAW_STATE_DESC_SETS,
2488    TU_DRAW_STATE_DESC_SETS_GMEM,
2489    TU_DRAW_STATE_DESC_SETS_LOAD,
2490    TU_DRAW_STATE_VS_PARAMS,
2491
2492    TU_DRAW_STATE_COUNT,
2493 };
2494
2495 struct tu_draw_state_group
2496 {
2497    enum tu_draw_state_group_id id;
2498    uint32_t enable_mask;
2499    struct tu_cs_entry ib;
2500 };
2501
2502 static inline uint32_t
2503 tu6_stage2opcode(gl_shader_stage type)
2504 {
2505    switch (type) {
2506    case MESA_SHADER_VERTEX:
2507    case MESA_SHADER_TESS_CTRL:
2508    case MESA_SHADER_TESS_EVAL:
2509    case MESA_SHADER_GEOMETRY:
2510       return CP_LOAD_STATE6_GEOM;
2511    case MESA_SHADER_FRAGMENT:
2512    case MESA_SHADER_COMPUTE:
2513    case MESA_SHADER_KERNEL:
2514       return CP_LOAD_STATE6_FRAG;
2515    default:
2516       unreachable("bad shader type");
2517    }
2518 }
2519
2520 static inline enum a6xx_state_block
2521 tu6_stage2shadersb(gl_shader_stage type)
2522 {
2523    switch (type) {
2524    case MESA_SHADER_VERTEX:
2525       return SB6_VS_SHADER;
2526    case MESA_SHADER_GEOMETRY:
2527       return SB6_GS_SHADER;
2528    case MESA_SHADER_FRAGMENT:
2529       return SB6_FS_SHADER;
2530    case MESA_SHADER_COMPUTE:
2531    case MESA_SHADER_KERNEL:
2532       return SB6_CS_SHADER;
2533    default:
2534       unreachable("bad shader type");
2535       return ~0;
2536    }
2537 }
2538
2539 static void
2540 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2541                      struct tu_descriptor_state *descriptors_state,
2542                      gl_shader_stage type,
2543                      uint32_t *push_constants)
2544 {
2545    const struct tu_program_descriptor_linkage *link =
2546       &pipeline->program.link[type];
2547    const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2548
2549    if (link->push_consts.count > 0) {
2550       unsigned num_units = link->push_consts.count;
2551       unsigned offset = link->push_consts.lo;
2552       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_units * 4);
2553       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
2554             CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2555             CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2556             CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2557             CP_LOAD_STATE6_0_NUM_UNIT(num_units));
2558       tu_cs_emit(cs, 0);
2559       tu_cs_emit(cs, 0);
2560       for (unsigned i = 0; i < num_units * 4; i++)
2561          tu_cs_emit(cs, push_constants[i + offset * 4]);
2562    }
2563
2564    for (uint32_t i = 0; i < state->num_enabled; i++) {
2565       uint32_t size = state->range[i].end - state->range[i].start;
2566       uint32_t offset = state->range[i].start;
2567
2568       /* and even if the start of the const buffer is before
2569        * first_immediate, the end may not be:
2570        */
2571       size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2572
2573       if (size == 0)
2574          continue;
2575
2576       /* things should be aligned to vec4: */
2577       debug_assert((state->range[i].offset % 16) == 0);
2578       debug_assert((size % 16) == 0);
2579       debug_assert((offset % 16) == 0);
2580
2581       /* Dig out the descriptor from the descriptor state and read the VA from
2582        * it.
2583        */
2584       assert(state->range[i].bindless);
2585       uint32_t *base = state->range[i].bindless_base == MAX_SETS ?
2586          descriptors_state->dynamic_descriptors :
2587          descriptors_state->sets[state->range[i].bindless_base]->mapped_ptr;
2588       unsigned block = state->range[i].block;
2589       /* If the block in the shader here is in the dynamic descriptor set, it
2590        * is an index into the dynamic descriptor set which is combined from
2591        * dynamic descriptors and input attachments on-the-fly, and we don't
2592        * have access to it here. Instead we work backwards to get the index
2593        * into dynamic_descriptors.
2594        */
2595       if (state->range[i].bindless_base == MAX_SETS)
2596          block -= pipeline->layout->input_attachment_count;
2597       uint32_t *desc = base + block * A6XX_TEX_CONST_DWORDS;
2598       uint64_t va = desc[0] | ((uint64_t)(desc[1] & A6XX_UBO_1_BASE_HI__MASK) << 32);
2599       assert(va);
2600
2601       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2602       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2603             CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2604             CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2605             CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2606             CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2607       tu_cs_emit_qw(cs, va + offset);
2608    }
2609 }
2610
2611 static struct tu_cs_entry
2612 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2613                 const struct tu_pipeline *pipeline,
2614                 struct tu_descriptor_state *descriptors_state,
2615                 gl_shader_stage type)
2616 {
2617    struct tu_cs cs;
2618    tu_cs_begin_sub_stream(&cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
2619
2620    tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2621
2622    return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2623 }
2624
2625 static VkResult
2626 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
2627                    const struct tu_draw_info *draw,
2628                    struct tu_cs_entry *entry)
2629 {
2630    /* TODO: fill out more than just base instance */
2631    const struct tu_program_descriptor_linkage *link =
2632       &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
2633    const struct ir3_const_state *const_state = &link->const_state;
2634    struct tu_cs cs;
2635
2636    if (const_state->offsets.driver_param >= link->constlen) {
2637       *entry = (struct tu_cs_entry) {};
2638       return VK_SUCCESS;
2639    }
2640
2641    VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 8, &cs);
2642    if (result != VK_SUCCESS)
2643       return result;
2644
2645    tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
2646    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(const_state->offsets.driver_param) |
2647          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2648          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2649          CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
2650          CP_LOAD_STATE6_0_NUM_UNIT(1));
2651    tu_cs_emit(&cs, 0);
2652    tu_cs_emit(&cs, 0);
2653
2654    STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
2655
2656    tu_cs_emit(&cs, 0);
2657    tu_cs_emit(&cs, 0);
2658    tu_cs_emit(&cs, draw->first_instance);
2659    tu_cs_emit(&cs, 0);
2660
2661    *entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2662    return VK_SUCCESS;
2663 }
2664
2665 static VkResult
2666 tu6_emit_descriptor_sets(struct tu_cmd_buffer *cmd,
2667                          const struct tu_pipeline *pipeline,
2668                          VkPipelineBindPoint bind_point,
2669                          struct tu_cs_entry *entry,
2670                          bool gmem)
2671 {
2672    struct tu_cs *draw_state = &cmd->sub_cs;
2673    struct tu_pipeline_layout *layout = pipeline->layout;
2674    struct tu_descriptor_state *descriptors_state =
2675       tu_get_descriptors_state(cmd, bind_point);
2676    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2677    const uint32_t *input_attachment_idx =
2678       pipeline->program.input_attachment_idx;
2679    uint32_t num_dynamic_descs = layout->dynamic_offset_count +
2680       layout->input_attachment_count;
2681    struct ts_cs_memory dynamic_desc_set;
2682    VkResult result;
2683
2684    if (num_dynamic_descs > 0) {
2685       /* allocate and fill out dynamic descriptor set */
2686       result = tu_cs_alloc(draw_state, num_dynamic_descs,
2687                            A6XX_TEX_CONST_DWORDS, &dynamic_desc_set);
2688       if (result != VK_SUCCESS)
2689          return result;
2690
2691       memcpy(dynamic_desc_set.map, descriptors_state->input_attachments,
2692              layout->input_attachment_count * A6XX_TEX_CONST_DWORDS * 4);
2693
2694       if (gmem) {
2695          /* Patch input attachments to refer to GMEM instead */
2696          for (unsigned i = 0; i < layout->input_attachment_count; i++) {
2697             uint32_t *dst =
2698                &dynamic_desc_set.map[A6XX_TEX_CONST_DWORDS * i];
2699
2700             /* The compiler has already laid out input_attachment_idx in the
2701              * final order of input attachments, so there's no need to go
2702              * through the pipeline layout finding input attachments.
2703              */
2704             unsigned attachment_idx = input_attachment_idx[i];
2705
2706             /* It's possible for the pipeline layout to include an input
2707              * attachment which doesn't actually exist for the current
2708              * subpass. Of course, this is only valid so long as the pipeline
2709              * doesn't try to actually load that attachment. Just skip
2710              * patching in that scenario to avoid out-of-bounds accesses.
2711              */
2712             if (attachment_idx >= cmd->state.subpass->input_count)
2713                continue;
2714
2715             uint32_t a = cmd->state.subpass->input_attachments[attachment_idx].attachment;
2716             const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
2717
2718             assert(att->gmem_offset >= 0);
2719
2720             dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
2721             dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
2722             dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
2723             dst[2] |=
2724                A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
2725                A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
2726             dst[3] = 0;
2727             dst[4] = cmd->device->physical_device->gmem_base + att->gmem_offset;
2728             dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
2729             for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2730                dst[i] = 0;
2731
2732             if (cmd->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
2733                tu_finishme("patch input attachment pitch for secondary cmd buffer");
2734          }
2735       }
2736
2737       memcpy(dynamic_desc_set.map + layout->input_attachment_count * A6XX_TEX_CONST_DWORDS,
2738              descriptors_state->dynamic_descriptors,
2739              layout->dynamic_offset_count * A6XX_TEX_CONST_DWORDS * 4);
2740    }
2741
2742    uint32_t sp_bindless_base_reg, hlsq_bindless_base_reg;
2743    uint32_t hlsq_update_value;
2744    switch (bind_point) {
2745    case VK_PIPELINE_BIND_POINT_GRAPHICS:
2746       sp_bindless_base_reg = REG_A6XX_SP_BINDLESS_BASE(0);
2747       hlsq_bindless_base_reg = REG_A6XX_HLSQ_BINDLESS_BASE(0);
2748       hlsq_update_value = 0x7c000;
2749       break;
2750    case VK_PIPELINE_BIND_POINT_COMPUTE:
2751       sp_bindless_base_reg = REG_A6XX_SP_CS_BINDLESS_BASE(0);
2752       hlsq_bindless_base_reg = REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
2753       hlsq_update_value = 0x3e00;
2754       break;
2755    default:
2756       unreachable("bad bind point");
2757    }
2758
2759    /* Be careful here to *not* refer to the pipeline, so that if only the
2760     * pipeline changes we don't have to emit this again (except if there are
2761     * dynamic descriptors in the pipeline layout). This means always emitting
2762     * all the valid descriptors, which means that we always have to put the
2763     * dynamic descriptor in the driver-only slot at the end
2764     */
2765    uint32_t num_user_sets = util_last_bit(descriptors_state->valid);
2766    uint32_t num_sets = num_user_sets;
2767    if (num_dynamic_descs > 0) {
2768       num_user_sets = MAX_SETS;
2769       num_sets = num_user_sets + 1;
2770    }
2771
2772    unsigned regs[2] = { sp_bindless_base_reg, hlsq_bindless_base_reg };
2773
2774    struct tu_cs cs;
2775    result = tu_cs_begin_sub_stream(draw_state, ARRAY_SIZE(regs) * (1 + num_sets * 2) + 2, &cs);
2776    if (result != VK_SUCCESS)
2777       return result;
2778
2779    if (num_sets > 0) {
2780       for (unsigned i = 0; i < ARRAY_SIZE(regs); i++) {
2781          tu_cs_emit_pkt4(&cs, regs[i], num_sets * 2);
2782          for (unsigned j = 0; j < num_user_sets; j++) {
2783             if (descriptors_state->valid & (1 << j)) {
2784                /* magic | 3 copied from the blob */
2785                tu_cs_emit_qw(&cs, descriptors_state->sets[j]->va | 3);
2786             } else {
2787                tu_cs_emit_qw(&cs, 0 | 3);
2788             }
2789          }
2790          if (num_dynamic_descs > 0) {
2791             tu_cs_emit_qw(&cs, dynamic_desc_set.iova | 3);
2792          }
2793       }
2794
2795       tu_cs_emit_regs(&cs, A6XX_HLSQ_UPDATE_CNTL(hlsq_update_value));
2796    }
2797
2798    *entry = tu_cs_end_sub_stream(draw_state, &cs);
2799    return VK_SUCCESS;
2800 }
2801
2802 static void
2803 tu6_emit_streamout(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
2804 {
2805    struct tu_streamout_state *tf = &cmd->state.pipeline->streamout;
2806
2807    for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2808       struct tu_buffer *buf = cmd->state.streamout_buf.buffers[i];
2809       if (!buf)
2810          continue;
2811
2812       uint32_t offset;
2813       offset = cmd->state.streamout_buf.offsets[i];
2814
2815       tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_BASE(i, .bo = buf->bo,
2816                                                      .bo_offset = buf->bo_offset));
2817       tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_SIZE(i, buf->size));
2818
2819       if (cmd->state.streamout_reset & (1 << i)) {
2820          tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_OFFSET(i, offset));
2821          cmd->state.streamout_reset &= ~(1  << i);
2822       } else {
2823          tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
2824          tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i)) |
2825                         CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
2826                         CP_MEM_TO_REG_0_CNT(0));
2827          tu_cs_emit_qw(cs, cmd->scratch_bo.iova +
2828                            ctrl_offset(flush_base[i].offset));
2829       }
2830
2831       tu_cs_emit_regs(cs, A6XX_VPC_SO_FLUSH_BASE(i, .bo = &cmd->scratch_bo,
2832                                                     .bo_offset =
2833                                                        ctrl_offset(flush_base[i])));
2834    }
2835
2836    if (cmd->state.streamout_enabled) {
2837       tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
2838       tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
2839       tu_cs_emit(cs, tf->vpc_so_buf_cntl);
2840       tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(0));
2841       tu_cs_emit(cs, tf->ncomp[0]);
2842       tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(1));
2843       tu_cs_emit(cs, tf->ncomp[1]);
2844       tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(2));
2845       tu_cs_emit(cs, tf->ncomp[2]);
2846       tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(3));
2847       tu_cs_emit(cs, tf->ncomp[3]);
2848       tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
2849       tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
2850       for (unsigned i = 0; i < tf->prog_count; i++) {
2851          tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
2852          tu_cs_emit(cs, tf->prog[i]);
2853       }
2854    } else {
2855       tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
2856       tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
2857       tu_cs_emit(cs, 0);
2858       tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
2859       tu_cs_emit(cs, 0);
2860    }
2861 }
2862
2863 static VkResult
2864 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
2865                      struct tu_cs *cs,
2866                      const struct tu_draw_info *draw)
2867 {
2868    const struct tu_pipeline *pipeline = cmd->state.pipeline;
2869    const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
2870    struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
2871    uint32_t draw_state_group_count = 0;
2872    VkResult result;
2873
2874    struct tu_descriptor_state *descriptors_state =
2875       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
2876
2877    /* TODO lrz */
2878
2879    tu_cs_emit_regs(cs,
2880                    A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart =
2881                                             pipeline->ia.primitive_restart && draw->indexed));
2882
2883    if (cmd->state.dirty &
2884           (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
2885        (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
2886       tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
2887                             dynamic->line_width);
2888    }
2889
2890    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
2891        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2892       tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
2893                                     dynamic->stencil_compare_mask.back);
2894    }
2895
2896    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
2897        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2898       tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
2899                                   dynamic->stencil_write_mask.back);
2900    }
2901
2902    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
2903        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2904       tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
2905                                  dynamic->stencil_reference.back);
2906    }
2907
2908    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
2909        (pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
2910       tu6_emit_viewport(cs, &cmd->state.dynamic.viewport.viewports[0]);
2911    }
2912
2913    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_SCISSOR) &&
2914        (pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
2915       tu6_emit_scissor(cs, &cmd->state.dynamic.scissor.scissors[0]);
2916    }
2917
2918    if (cmd->state.dirty &
2919        (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
2920       for (uint32_t i = 0; i < pipeline->vi.count; i++) {
2921          const uint32_t binding = pipeline->vi.bindings[i];
2922          const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
2923          const VkDeviceSize offset = buf->bo_offset +
2924                                      cmd->state.vb.offsets[binding];
2925          const VkDeviceSize size =
2926             offset < buf->size ? buf->size - offset : 0;
2927
2928          tu_cs_emit_regs(cs,
2929                          A6XX_VFD_FETCH_BASE(i, .bo = buf->bo, .bo_offset = offset),
2930                          A6XX_VFD_FETCH_SIZE(i, size));
2931       }
2932    }
2933
2934    if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
2935       draw_state_groups[draw_state_group_count++] =
2936          (struct tu_draw_state_group) {
2937             .id = TU_DRAW_STATE_PROGRAM,
2938             .enable_mask = ENABLE_DRAW,
2939             .ib = pipeline->program.state_ib,
2940          };
2941       draw_state_groups[draw_state_group_count++] =
2942          (struct tu_draw_state_group) {
2943             .id = TU_DRAW_STATE_PROGRAM_BINNING,
2944             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
2945             .ib = pipeline->program.binning_state_ib,
2946          };
2947       draw_state_groups[draw_state_group_count++] =
2948          (struct tu_draw_state_group) {
2949             .id = TU_DRAW_STATE_VI,
2950             .enable_mask = ENABLE_DRAW,
2951             .ib = pipeline->vi.state_ib,
2952          };
2953       draw_state_groups[draw_state_group_count++] =
2954          (struct tu_draw_state_group) {
2955             .id = TU_DRAW_STATE_VI_BINNING,
2956             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
2957             .ib = pipeline->vi.binning_state_ib,
2958          };
2959       draw_state_groups[draw_state_group_count++] =
2960          (struct tu_draw_state_group) {
2961             .id = TU_DRAW_STATE_VP,
2962             .enable_mask = ENABLE_ALL,
2963             .ib = pipeline->vp.state_ib,
2964          };
2965       draw_state_groups[draw_state_group_count++] =
2966          (struct tu_draw_state_group) {
2967             .id = TU_DRAW_STATE_RAST,
2968             .enable_mask = ENABLE_ALL,
2969             .ib = pipeline->rast.state_ib,
2970          };
2971       draw_state_groups[draw_state_group_count++] =
2972          (struct tu_draw_state_group) {
2973             .id = TU_DRAW_STATE_DS,
2974             .enable_mask = ENABLE_ALL,
2975             .ib = pipeline->ds.state_ib,
2976          };
2977       draw_state_groups[draw_state_group_count++] =
2978          (struct tu_draw_state_group) {
2979             .id = TU_DRAW_STATE_BLEND,
2980             .enable_mask = ENABLE_ALL,
2981             .ib = pipeline->blend.state_ib,
2982          };
2983    }
2984
2985    if (cmd->state.dirty &
2986          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_PUSH_CONSTANTS)) {
2987       draw_state_groups[draw_state_group_count++] =
2988          (struct tu_draw_state_group) {
2989             .id = TU_DRAW_STATE_VS_CONST,
2990             .enable_mask = ENABLE_ALL,
2991             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
2992          };
2993       draw_state_groups[draw_state_group_count++] =
2994          (struct tu_draw_state_group) {
2995             .id = TU_DRAW_STATE_GS_CONST,
2996             .enable_mask = ENABLE_ALL,
2997             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_GEOMETRY)
2998          };
2999       draw_state_groups[draw_state_group_count++] =
3000          (struct tu_draw_state_group) {
3001             .id = TU_DRAW_STATE_FS_CONST,
3002             .enable_mask = ENABLE_DRAW,
3003             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
3004          };
3005    }
3006
3007    if (cmd->state.dirty & TU_CMD_DIRTY_STREAMOUT_BUFFERS)
3008       tu6_emit_streamout(cmd, cs);
3009
3010    /* If there are any any dynamic descriptors, then we may need to re-emit
3011     * them after every pipeline change in case the number of input attachments
3012     * changes. We also always need to re-emit after a pipeline change if there
3013     * are any input attachments, because the input attachment index comes from
3014     * the pipeline. Finally, it can also happen that the subpass changes
3015     * without the pipeline changing, in which case the GMEM descriptors need
3016     * to be patched differently.
3017     *
3018     * TODO: We could probably be clever and avoid re-emitting state on
3019     * pipeline changes if the number of input attachments is always 0. We
3020     * could also only re-emit dynamic state.
3021     */
3022    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS ||
3023        ((pipeline->layout->dynamic_offset_count +
3024          pipeline->layout->input_attachment_count > 0) &&
3025         cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) ||
3026        (pipeline->layout->input_attachment_count > 0 &&
3027         cmd->state.dirty & TU_CMD_DIRTY_INPUT_ATTACHMENTS)) {
3028       struct tu_cs_entry desc_sets, desc_sets_gmem;
3029       bool need_gmem_desc_set = pipeline->layout->input_attachment_count > 0;
3030
3031       result = tu6_emit_descriptor_sets(cmd, pipeline,
3032                                         VK_PIPELINE_BIND_POINT_GRAPHICS,
3033                                         &desc_sets, false);
3034       if (result != VK_SUCCESS)
3035          return result;
3036
3037       draw_state_groups[draw_state_group_count++] =
3038          (struct tu_draw_state_group) {
3039             .id = TU_DRAW_STATE_DESC_SETS,
3040             .enable_mask = need_gmem_desc_set ? ENABLE_NON_GMEM : ENABLE_ALL,
3041             .ib = desc_sets,
3042          };
3043
3044       if (need_gmem_desc_set) {
3045          result = tu6_emit_descriptor_sets(cmd, pipeline,
3046                                            VK_PIPELINE_BIND_POINT_GRAPHICS,
3047                                            &desc_sets_gmem, true);
3048          if (result != VK_SUCCESS)
3049             return result;
3050
3051          draw_state_groups[draw_state_group_count++] =
3052             (struct tu_draw_state_group) {
3053                .id = TU_DRAW_STATE_DESC_SETS_GMEM,
3054                .enable_mask = CP_SET_DRAW_STATE__0_GMEM,
3055                .ib = desc_sets_gmem,
3056             };
3057       }
3058
3059       /* We need to reload the descriptors every time the descriptor sets
3060        * change. However, the commands we send only depend on the pipeline
3061        * because the whole point is to cache descriptors which are used by the
3062        * pipeline. There's a problem here, in that the firmware has an
3063        * "optimization" which skips executing groups that are set to the same
3064        * value as the last draw. This means that if the descriptor sets change
3065        * but not the pipeline, we'd try to re-execute the same buffer which
3066        * the firmware would ignore and we wouldn't pre-load the new
3067        * descriptors. The blob seems to re-emit the LOAD_STATE group whenever
3068        * the descriptor sets change, which we emulate here by copying the
3069        * pre-prepared buffer.
3070        */
3071       const struct tu_cs_entry *load_entry = &pipeline->load_state.state_ib;
3072       if (load_entry->size > 0) {
3073          struct tu_cs load_cs;
3074          result = tu_cs_begin_sub_stream(&cmd->sub_cs, load_entry->size, &load_cs);
3075          if (result != VK_SUCCESS)
3076             return result;
3077          tu_cs_emit_array(&load_cs,
3078                           (uint32_t *)((char  *)load_entry->bo->map + load_entry->offset),
3079                           load_entry->size / 4);
3080          struct tu_cs_entry load_copy = tu_cs_end_sub_stream(&cmd->sub_cs, &load_cs);
3081
3082          draw_state_groups[draw_state_group_count++] =
3083             (struct tu_draw_state_group) {
3084                .id = TU_DRAW_STATE_DESC_SETS_LOAD,
3085                /* The blob seems to not enable this for binning, even when
3086                 * resources would actually be used in the binning shader.
3087                 * Presumably the overhead of prefetching the resources isn't
3088                 * worth it.
3089                 */
3090                .enable_mask = ENABLE_DRAW,
3091                .ib = load_copy,
3092             };
3093       }
3094    }
3095
3096    struct tu_cs_entry vs_params;
3097    result = tu6_emit_vs_params(cmd, draw, &vs_params);
3098    if (result != VK_SUCCESS)
3099       return result;
3100
3101    draw_state_groups[draw_state_group_count++] =
3102       (struct tu_draw_state_group) {
3103          .id = TU_DRAW_STATE_VS_PARAMS,
3104          .enable_mask = ENABLE_ALL,
3105          .ib = vs_params,
3106       };
3107
3108    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
3109    for (uint32_t i = 0; i < draw_state_group_count; i++) {
3110       const struct tu_draw_state_group *group = &draw_state_groups[i];
3111       debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
3112       uint32_t cp_set_draw_state =
3113          CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
3114          group->enable_mask |
3115          CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
3116       uint64_t iova;
3117       if (group->ib.size) {
3118          iova = group->ib.bo->iova + group->ib.offset;
3119       } else {
3120          cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
3121          iova = 0;
3122       }
3123
3124       tu_cs_emit(cs, cp_set_draw_state);
3125       tu_cs_emit_qw(cs, iova);
3126    }
3127
3128    tu_cs_sanity_check(cs);
3129
3130    /* track BOs */
3131    if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
3132       for (uint32_t i = 0; i < MAX_VBS; i++) {
3133          const struct tu_buffer *buf = cmd->state.vb.buffers[i];
3134          if (buf)
3135             tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
3136       }
3137    }
3138    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3139       unsigned i;
3140       for_each_bit(i, descriptors_state->valid) {
3141          struct tu_descriptor_set *set = descriptors_state->sets[i];
3142          for (unsigned j = 0; j < set->layout->buffer_count; ++j) {
3143             if (set->buffers[j]) {
3144                tu_bo_list_add(&cmd->bo_list, set->buffers[j],
3145                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3146             }
3147          }
3148          if (set->size > 0) {
3149             tu_bo_list_add(&cmd->bo_list, &set->pool->bo,
3150                            MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
3151          }
3152       }
3153    }
3154    if (cmd->state.dirty & TU_CMD_DIRTY_STREAMOUT_BUFFERS) {
3155       for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
3156          const struct tu_buffer *buf = cmd->state.streamout_buf.buffers[i];
3157          if (buf) {
3158             tu_bo_list_add(&cmd->bo_list, buf->bo,
3159                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3160          }
3161       }
3162    }
3163
3164    /* There are too many graphics dirty bits to list here, so just list the
3165     * bits to preserve instead. The only things not emitted here are
3166     * compute-related state.
3167     */
3168    cmd->state.dirty &= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS;
3169
3170    /* Fragment shader state overwrites compute shader state, so flag the
3171     * compute pipeline for re-emit.
3172     */
3173    cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
3174    return VK_SUCCESS;
3175 }
3176
3177 static void
3178 tu6_emit_draw_indirect(struct tu_cmd_buffer *cmd,
3179                      struct tu_cs *cs,
3180                      const struct tu_draw_info *draw)
3181 {
3182    const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3183    bool has_gs = cmd->state.pipeline->active_stages &
3184                  VK_SHADER_STAGE_GEOMETRY_BIT;
3185
3186    tu_cs_emit_regs(cs,
3187                    A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
3188                    A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
3189
3190    if (draw->indexed) {
3191       const enum a4xx_index_size index_size =
3192          tu6_index_size(cmd->state.index_type);
3193       const uint32_t index_bytes =
3194          (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3195       const struct tu_buffer *index_buf = cmd->state.index_buffer;
3196       unsigned max_indicies =
3197          (index_buf->size - cmd->state.index_offset) / index_bytes;
3198
3199       const uint32_t cp_draw_indx =
3200          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3201          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3202          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3203          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
3204          COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
3205
3206       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_INDIRECT, 6);
3207       tu_cs_emit(cs, cp_draw_indx);
3208       tu_cs_emit_qw(cs, index_buf->bo->iova + cmd->state.index_offset);
3209       tu_cs_emit(cs, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
3210       tu_cs_emit_qw(cs, draw->indirect->bo->iova + draw->indirect_offset);
3211    } else {
3212       const uint32_t cp_draw_indx =
3213          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3214          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3215          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
3216          COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
3217
3218       tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT, 3);
3219       tu_cs_emit(cs, cp_draw_indx);
3220       tu_cs_emit_qw(cs, draw->indirect->bo->iova + draw->indirect_offset);
3221    }
3222
3223    tu_bo_list_add(&cmd->bo_list, draw->indirect->bo, MSM_SUBMIT_BO_READ);
3224 }
3225
3226 static void
3227 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
3228                      struct tu_cs *cs,
3229                      const struct tu_draw_info *draw)
3230 {
3231
3232    const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3233    bool has_gs = cmd->state.pipeline->active_stages &
3234                  VK_SHADER_STAGE_GEOMETRY_BIT;
3235
3236    tu_cs_emit_regs(cs,
3237                    A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
3238                    A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
3239
3240    /* TODO hw binning */
3241    if (draw->indexed) {
3242       const enum a4xx_index_size index_size =
3243          tu6_index_size(cmd->state.index_type);
3244       const uint32_t index_bytes =
3245          (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3246       const struct tu_buffer *buf = cmd->state.index_buffer;
3247       const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
3248                                   index_bytes * draw->first_index;
3249       const uint32_t size = index_bytes * draw->count;
3250
3251       const uint32_t cp_draw_indx =
3252          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3253          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3254          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3255          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
3256          COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
3257
3258       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
3259       tu_cs_emit(cs, cp_draw_indx);
3260       tu_cs_emit(cs, draw->instance_count);
3261       tu_cs_emit(cs, draw->count);
3262       tu_cs_emit(cs, 0x0); /* XXX */
3263       tu_cs_emit_qw(cs, buf->bo->iova + offset);
3264       tu_cs_emit(cs, size);
3265    } else {
3266       const uint32_t cp_draw_indx =
3267          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3268          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3269          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
3270          COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
3271
3272       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
3273       tu_cs_emit(cs, cp_draw_indx);
3274       tu_cs_emit(cs, draw->instance_count);
3275       tu_cs_emit(cs, draw->count);
3276    }
3277 }
3278
3279 static void
3280 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
3281 {
3282    struct tu_cs *cs = &cmd->draw_cs;
3283    VkResult result;
3284
3285    result = tu6_bind_draw_states(cmd, cs, draw);
3286    if (result != VK_SUCCESS) {
3287       cmd->record_result = result;
3288       return;
3289    }
3290
3291    if (draw->indirect)
3292       tu6_emit_draw_indirect(cmd, cs, draw);
3293    else
3294       tu6_emit_draw_direct(cmd, cs, draw);
3295
3296    if (cmd->state.streamout_enabled) {
3297       for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
3298          if (cmd->state.streamout_enabled & (1 << i))
3299             tu6_emit_event_write(cmd, cs, FLUSH_SO_0 + i, false);
3300       }
3301    }
3302
3303    cmd->wait_for_idle = true;
3304
3305    tu_cs_sanity_check(cs);
3306 }
3307
3308 void
3309 tu_CmdDraw(VkCommandBuffer commandBuffer,
3310            uint32_t vertexCount,
3311            uint32_t instanceCount,
3312            uint32_t firstVertex,
3313            uint32_t firstInstance)
3314 {
3315    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3316    struct tu_draw_info info = {};
3317
3318    info.count = vertexCount;
3319    info.instance_count = instanceCount;
3320    info.first_instance = firstInstance;
3321    info.vertex_offset = firstVertex;
3322
3323    tu_draw(cmd_buffer, &info);
3324 }
3325
3326 void
3327 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3328                   uint32_t indexCount,
3329                   uint32_t instanceCount,
3330                   uint32_t firstIndex,
3331                   int32_t vertexOffset,
3332                   uint32_t firstInstance)
3333 {
3334    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3335    struct tu_draw_info info = {};
3336
3337    info.indexed = true;
3338    info.count = indexCount;
3339    info.instance_count = instanceCount;
3340    info.first_index = firstIndex;
3341    info.vertex_offset = vertexOffset;
3342    info.first_instance = firstInstance;
3343
3344    tu_draw(cmd_buffer, &info);
3345 }
3346
3347 void
3348 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3349                    VkBuffer _buffer,
3350                    VkDeviceSize offset,
3351                    uint32_t drawCount,
3352                    uint32_t stride)
3353 {
3354    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3355    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3356    struct tu_draw_info info = {};
3357
3358    info.count = drawCount;
3359    info.indirect = buffer;
3360    info.indirect_offset = offset;
3361    info.stride = stride;
3362
3363    tu_draw(cmd_buffer, &info);
3364 }
3365
3366 void
3367 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3368                           VkBuffer _buffer,
3369                           VkDeviceSize offset,
3370                           uint32_t drawCount,
3371                           uint32_t stride)
3372 {
3373    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3374    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3375    struct tu_draw_info info = {};
3376
3377    info.indexed = true;
3378    info.count = drawCount;
3379    info.indirect = buffer;
3380    info.indirect_offset = offset;
3381    info.stride = stride;
3382
3383    tu_draw(cmd_buffer, &info);
3384 }
3385
3386 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer,
3387                                     uint32_t instanceCount,
3388                                     uint32_t firstInstance,
3389                                     VkBuffer _counterBuffer,
3390                                     VkDeviceSize counterBufferOffset,
3391                                     uint32_t counterOffset,
3392                                     uint32_t vertexStride)
3393 {
3394    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3395    TU_FROM_HANDLE(tu_buffer, buffer, _counterBuffer);
3396
3397    struct tu_draw_info info = {};
3398
3399    info.instance_count = instanceCount;
3400    info.first_instance = firstInstance;
3401    info.streamout_buffer = buffer;
3402    info.streamout_buffer_offset = counterBufferOffset;
3403    info.stride = vertexStride;
3404
3405    tu_draw(cmd_buffer, &info);
3406 }
3407
3408 struct tu_dispatch_info
3409 {
3410    /**
3411     * Determine the layout of the grid (in block units) to be used.
3412     */
3413    uint32_t blocks[3];
3414
3415    /**
3416     * A starting offset for the grid. If unaligned is set, the offset
3417     * must still be aligned.
3418     */
3419    uint32_t offsets[3];
3420    /**
3421     * Whether it's an unaligned compute dispatch.
3422     */
3423    bool unaligned;
3424
3425    /**
3426     * Indirect compute parameters resource.
3427     */
3428    struct tu_buffer *indirect;
3429    uint64_t indirect_offset;
3430 };
3431
3432 static void
3433 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3434                               const struct tu_dispatch_info *info)
3435 {
3436    gl_shader_stage type = MESA_SHADER_COMPUTE;
3437    const struct tu_program_descriptor_linkage *link =
3438       &pipeline->program.link[type];
3439    const struct ir3_const_state *const_state = &link->const_state;
3440    uint32_t offset = const_state->offsets.driver_param;
3441
3442    if (link->constlen <= offset)
3443       return;
3444
3445    if (!info->indirect) {
3446       uint32_t driver_params[IR3_DP_CS_COUNT] = {
3447          [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
3448          [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
3449          [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
3450          [IR3_DP_LOCAL_GROUP_SIZE_X] = pipeline->compute.local_size[0],
3451          [IR3_DP_LOCAL_GROUP_SIZE_Y] = pipeline->compute.local_size[1],
3452          [IR3_DP_LOCAL_GROUP_SIZE_Z] = pipeline->compute.local_size[2],
3453       };
3454
3455       uint32_t num_consts = MIN2(const_state->num_driver_params,
3456                                  (link->constlen - offset) * 4);
3457       /* push constants */
3458       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
3459       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
3460                  CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3461                  CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3462                  CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3463                  CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
3464       tu_cs_emit(cs, 0);
3465       tu_cs_emit(cs, 0);
3466       uint32_t i;
3467       for (i = 0; i < num_consts; i++)
3468          tu_cs_emit(cs, driver_params[i]);
3469    } else {
3470       tu_finishme("Indirect driver params");
3471    }
3472 }
3473
3474 static void
3475 tu_dispatch(struct tu_cmd_buffer *cmd,
3476             const struct tu_dispatch_info *info)
3477 {
3478    struct tu_cs *cs = &cmd->cs;
3479    struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3480    struct tu_descriptor_state *descriptors_state =
3481       &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3482    VkResult result;
3483
3484    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3485       tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3486
3487    struct tu_cs_entry ib;
3488
3489    ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3490    if (ib.size)
3491       tu_cs_emit_ib(cs, &ib);
3492
3493    tu_emit_compute_driver_params(cs, pipeline, info);
3494
3495    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS) {
3496       result = tu6_emit_descriptor_sets(cmd, pipeline,
3497                                         VK_PIPELINE_BIND_POINT_COMPUTE, &ib,
3498                                         false);
3499       if (result != VK_SUCCESS) {
3500          cmd->record_result = result;
3501          return;
3502       }
3503
3504       /* track BOs */
3505       unsigned i;
3506       for_each_bit(i, descriptors_state->valid) {
3507          struct tu_descriptor_set *set = descriptors_state->sets[i];
3508          for (unsigned j = 0; j < set->layout->buffer_count; ++j) {
3509             if (set->buffers[j]) {
3510                tu_bo_list_add(&cmd->bo_list, set->buffers[j],
3511                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3512             }
3513          }
3514
3515          if (set->size > 0) {
3516             tu_bo_list_add(&cmd->bo_list, &set->pool->bo,
3517                            MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
3518          }
3519       }
3520    }
3521
3522    if (ib.size)
3523       tu_cs_emit_ib(cs, &ib);
3524
3525    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS)
3526       tu_cs_emit_ib(cs, &pipeline->load_state.state_ib);
3527
3528    cmd->state.dirty &=
3529       ~(TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS | TU_CMD_DIRTY_COMPUTE_PIPELINE);
3530
3531    /* Compute shader state overwrites fragment shader state, so we flag the
3532     * graphics pipeline for re-emit.
3533     */
3534    cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
3535
3536    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3537    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
3538
3539    const uint32_t *local_size = pipeline->compute.local_size;
3540    const uint32_t *num_groups = info->blocks;
3541    tu_cs_emit_regs(cs,
3542                    A6XX_HLSQ_CS_NDRANGE_0(.kerneldim = 3,
3543                                           .localsizex = local_size[0] - 1,
3544                                           .localsizey = local_size[1] - 1,
3545                                           .localsizez = local_size[2] - 1),
3546                    A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x = local_size[0] * num_groups[0]),
3547                    A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x = 0),
3548                    A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y = local_size[1] * num_groups[1]),
3549                    A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y = 0),
3550                    A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z = local_size[2] * num_groups[2]),
3551                    A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z = 0));
3552
3553    tu_cs_emit_regs(cs,
3554                    A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3555                    A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3556                    A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3557
3558    if (info->indirect) {
3559       uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3560
3561       tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3562                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3563
3564       tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3565       tu_cs_emit(cs, 0x00000000);
3566       tu_cs_emit_qw(cs, iova);
3567       tu_cs_emit(cs,
3568                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3569                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3570                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3571    } else {
3572       tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3573       tu_cs_emit(cs, 0x00000000);
3574       tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3575       tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3576       tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3577    }
3578
3579    tu_cs_emit_wfi(cs);
3580
3581    tu6_emit_cache_flush(cmd, cs);
3582 }
3583
3584 void
3585 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
3586                    uint32_t base_x,
3587                    uint32_t base_y,
3588                    uint32_t base_z,
3589                    uint32_t x,
3590                    uint32_t y,
3591                    uint32_t z)
3592 {
3593    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3594    struct tu_dispatch_info info = {};
3595
3596    info.blocks[0] = x;
3597    info.blocks[1] = y;
3598    info.blocks[2] = z;
3599
3600    info.offsets[0] = base_x;
3601    info.offsets[1] = base_y;
3602    info.offsets[2] = base_z;
3603    tu_dispatch(cmd_buffer, &info);
3604 }
3605
3606 void
3607 tu_CmdDispatch(VkCommandBuffer commandBuffer,
3608                uint32_t x,
3609                uint32_t y,
3610                uint32_t z)
3611 {
3612    tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3613 }
3614
3615 void
3616 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
3617                        VkBuffer _buffer,
3618                        VkDeviceSize offset)
3619 {
3620    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3621    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3622    struct tu_dispatch_info info = {};
3623
3624    info.indirect = buffer;
3625    info.indirect_offset = offset;
3626
3627    tu_dispatch(cmd_buffer, &info);
3628 }
3629
3630 void
3631 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3632 {
3633    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3634
3635    tu_cs_end(&cmd_buffer->draw_cs);
3636    tu_cs_end(&cmd_buffer->draw_epilogue_cs);
3637
3638    if (use_sysmem_rendering(cmd_buffer))
3639       tu_cmd_render_sysmem(cmd_buffer);
3640    else
3641       tu_cmd_render_tiles(cmd_buffer);
3642
3643    /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3644       rendered */
3645    tu_cs_discard_entries(&cmd_buffer->draw_cs);
3646    tu_cs_begin(&cmd_buffer->draw_cs);
3647    tu_cs_discard_entries(&cmd_buffer->draw_epilogue_cs);
3648    tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
3649
3650    cmd_buffer->state.pass = NULL;
3651    cmd_buffer->state.subpass = NULL;
3652    cmd_buffer->state.framebuffer = NULL;
3653 }
3654
3655 void
3656 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
3657                      const VkSubpassEndInfoKHR *pSubpassEndInfo)
3658 {
3659    tu_CmdEndRenderPass(commandBuffer);
3660 }
3661
3662 struct tu_barrier_info
3663 {
3664    uint32_t eventCount;
3665    const VkEvent *pEvents;
3666    VkPipelineStageFlags srcStageMask;
3667 };
3668
3669 static void
3670 tu_barrier(struct tu_cmd_buffer *cmd,
3671            uint32_t memoryBarrierCount,
3672            const VkMemoryBarrier *pMemoryBarriers,
3673            uint32_t bufferMemoryBarrierCount,
3674            const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3675            uint32_t imageMemoryBarrierCount,
3676            const VkImageMemoryBarrier *pImageMemoryBarriers,
3677            const struct tu_barrier_info *info)
3678 {
3679    /* renderpass case is only for subpass self-dependencies
3680     * which means syncing the render output with texture cache
3681     * note: only the CACHE_INVALIDATE is needed in GMEM mode
3682     * and in sysmem mode we might not need either color/depth flush
3683     */
3684    if (cmd->state.pass) {
3685       tu6_emit_event_write(cmd, &cmd->draw_cs, PC_CCU_FLUSH_COLOR_TS, true);
3686       tu6_emit_event_write(cmd, &cmd->draw_cs, PC_CCU_FLUSH_DEPTH_TS, true);
3687       tu6_emit_event_write(cmd, &cmd->draw_cs, CACHE_INVALIDATE, false);
3688       return;
3689    }
3690 }
3691
3692 void
3693 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3694                       VkPipelineStageFlags srcStageMask,
3695                       VkPipelineStageFlags dstStageMask,
3696                       VkDependencyFlags dependencyFlags,
3697                       uint32_t memoryBarrierCount,
3698                       const VkMemoryBarrier *pMemoryBarriers,
3699                       uint32_t bufferMemoryBarrierCount,
3700                       const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3701                       uint32_t imageMemoryBarrierCount,
3702                       const VkImageMemoryBarrier *pImageMemoryBarriers)
3703 {
3704    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3705    struct tu_barrier_info info;
3706
3707    info.eventCount = 0;
3708    info.pEvents = NULL;
3709    info.srcStageMask = srcStageMask;
3710
3711    tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3712               bufferMemoryBarrierCount, pBufferMemoryBarriers,
3713               imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3714 }
3715
3716 static void
3717 write_event(struct tu_cmd_buffer *cmd, struct tu_event *event, unsigned value)
3718 {
3719    struct tu_cs *cs = &cmd->cs;
3720
3721    tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_WRITE);
3722
3723    /* TODO: any flush required before/after ? */
3724
3725    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
3726    tu_cs_emit_qw(cs, event->bo.iova); /* ADDR_LO/HI */
3727    tu_cs_emit(cs, value);
3728 }
3729
3730 void
3731 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3732                VkEvent _event,
3733                VkPipelineStageFlags stageMask)
3734 {
3735    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3736    TU_FROM_HANDLE(tu_event, event, _event);
3737
3738    write_event(cmd, event, 1);
3739 }
3740
3741 void
3742 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3743                  VkEvent _event,
3744                  VkPipelineStageFlags stageMask)
3745 {
3746    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3747    TU_FROM_HANDLE(tu_event, event, _event);
3748
3749    write_event(cmd, event, 0);
3750 }
3751
3752 void
3753 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3754                  uint32_t eventCount,
3755                  const VkEvent *pEvents,
3756                  VkPipelineStageFlags srcStageMask,
3757                  VkPipelineStageFlags dstStageMask,
3758                  uint32_t memoryBarrierCount,
3759                  const VkMemoryBarrier *pMemoryBarriers,
3760                  uint32_t bufferMemoryBarrierCount,
3761                  const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3762                  uint32_t imageMemoryBarrierCount,
3763                  const VkImageMemoryBarrier *pImageMemoryBarriers)
3764 {
3765    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3766    struct tu_cs *cs = &cmd->cs;
3767
3768    /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
3769
3770    for (uint32_t i = 0; i < eventCount; i++) {
3771       TU_FROM_HANDLE(tu_event, event, pEvents[i]);
3772
3773       tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_READ);
3774
3775       tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
3776       tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
3777                      CP_WAIT_REG_MEM_0_POLL_MEMORY);
3778       tu_cs_emit_qw(cs, event->bo.iova); /* POLL_ADDR_LO/HI */
3779       tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1));
3780       tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u));
3781       tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3782    }
3783 }
3784
3785 void
3786 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3787 {
3788    /* No-op */
3789 }