2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
33 #include "vk_format.h"
38 tu_bo_list_init(struct tu_bo_list
*list
)
40 list
->count
= list
->capacity
= 0;
41 list
->bo_infos
= NULL
;
45 tu_bo_list_destroy(struct tu_bo_list
*list
)
51 tu_bo_list_reset(struct tu_bo_list
*list
)
57 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 tu_bo_list_add_info(struct tu_bo_list
*list
,
61 const struct drm_msm_gem_submit_bo
*bo_info
)
63 assert(bo_info
->handle
!= 0);
65 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
66 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
67 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
68 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
73 /* grow list->bo_infos if needed */
74 if (list
->count
== list
->capacity
) {
75 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
76 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
77 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
79 return TU_BO_LIST_FAILED
;
80 list
->bo_infos
= new_bo_infos
;
81 list
->capacity
= new_capacity
;
84 list
->bo_infos
[list
->count
] = *bo_info
;
89 tu_bo_list_add(struct tu_bo_list
*list
,
90 const struct tu_bo
*bo
,
93 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
95 .handle
= bo
->gem_handle
,
101 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
103 for (uint32_t i
= 0; i
< other
->count
; i
++) {
104 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
105 return VK_ERROR_OUT_OF_HOST_MEMORY
;
112 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
114 enum vgt_event_type event
)
116 bool need_seqno
= false;
121 case PC_CCU_FLUSH_DEPTH_TS
:
122 case PC_CCU_FLUSH_COLOR_TS
:
123 case PC_CCU_RESOLVE_TS
:
130 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
131 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
133 tu_cs_emit_qw(cs
, global_iova(cmd
, seqno_dummy
));
139 tu6_emit_flushes(struct tu_cmd_buffer
*cmd_buffer
,
141 enum tu_cmd_flush_bits flushes
)
143 /* Experiments show that invalidating CCU while it still has data in it
144 * doesn't work, so make sure to always flush before invalidating in case
145 * any data remains that hasn't yet been made available through a barrier.
146 * However it does seem to work for UCHE.
148 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_COLOR
|
149 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
))
150 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_COLOR_TS
);
151 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
152 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
))
153 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_DEPTH_TS
);
154 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_COLOR
)
155 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_COLOR
);
156 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
)
157 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_DEPTH
);
158 if (flushes
& TU_CMD_FLAG_CACHE_FLUSH
)
159 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_FLUSH_TS
);
160 if (flushes
& TU_CMD_FLAG_CACHE_INVALIDATE
)
161 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_INVALIDATE
);
162 if (flushes
& TU_CMD_FLAG_WAIT_MEM_WRITES
)
163 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
164 if (flushes
& TU_CMD_FLAG_WAIT_FOR_IDLE
)
166 if (flushes
& TU_CMD_FLAG_WAIT_FOR_ME
)
167 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
170 /* "Normal" cache flushes, that don't require any special handling */
173 tu_emit_cache_flush(struct tu_cmd_buffer
*cmd_buffer
,
176 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.cache
.flush_bits
);
177 cmd_buffer
->state
.cache
.flush_bits
= 0;
180 /* Renderpass cache flushes */
183 tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
186 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.renderpass_cache
.flush_bits
);
187 cmd_buffer
->state
.renderpass_cache
.flush_bits
= 0;
190 /* Cache flushes for things that use the color/depth read/write path (i.e.
191 * blits and draws). This deals with changing CCU state as well as the usual
196 tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
198 enum tu_cmd_ccu_state ccu_state
)
200 enum tu_cmd_flush_bits flushes
= cmd_buffer
->state
.cache
.flush_bits
;
202 assert(ccu_state
!= TU_CMD_CCU_UNKNOWN
);
204 /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
205 * the CCU may also contain data that we haven't flushed out yet, so we
206 * also need to flush. Also, in order to program RB_CCU_CNTL, we need to
207 * emit a WFI as it isn't pipelined.
209 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
210 if (cmd_buffer
->state
.ccu_state
!= TU_CMD_CCU_GMEM
) {
212 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
213 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
214 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
215 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
216 TU_CMD_FLAG_CCU_FLUSH_DEPTH
);
219 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
220 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
221 TU_CMD_FLAG_WAIT_FOR_IDLE
;
222 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
223 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
224 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
225 TU_CMD_FLAG_WAIT_FOR_IDLE
);
228 tu6_emit_flushes(cmd_buffer
, cs
, flushes
);
229 cmd_buffer
->state
.cache
.flush_bits
= 0;
231 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
232 struct tu_physical_device
*phys_dev
= cmd_buffer
->device
->physical_device
;
234 A6XX_RB_CCU_CNTL(.offset
=
235 ccu_state
== TU_CMD_CCU_GMEM
?
236 phys_dev
->ccu_offset_gmem
:
237 phys_dev
->ccu_offset_bypass
,
238 .gmem
= ccu_state
== TU_CMD_CCU_GMEM
));
239 cmd_buffer
->state
.ccu_state
= ccu_state
;
244 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
245 const struct tu_subpass
*subpass
,
248 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
250 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
251 if (a
== VK_ATTACHMENT_UNUSED
) {
253 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
254 A6XX_RB_DEPTH_BUFFER_PITCH(0),
255 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
256 A6XX_RB_DEPTH_BUFFER_BASE(0),
257 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
260 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
263 A6XX_GRAS_LRZ_BUFFER_BASE(0),
264 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
265 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
267 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
272 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
273 const struct tu_render_pass_attachment
*attachment
=
274 &cmd
->state
.pass
->attachments
[a
];
275 enum a6xx_depth_format fmt
= tu6_pipe2depth(attachment
->format
);
277 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
278 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
).value
);
279 tu_cs_image_ref(cs
, iview
, 0);
280 tu_cs_emit(cs
, attachment
->gmem_offset
);
283 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
285 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
286 tu_cs_image_flag_ref(cs
, iview
, 0);
289 A6XX_GRAS_LRZ_BUFFER_BASE(0),
290 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
291 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
293 if (attachment
->format
== VK_FORMAT_S8_UINT
) {
294 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 6);
295 tu_cs_emit(cs
, A6XX_RB_STENCIL_INFO(.separate_stencil
= true).value
);
296 tu_cs_image_ref(cs
, iview
, 0);
297 tu_cs_emit(cs
, attachment
->gmem_offset
);
300 A6XX_RB_STENCIL_INFO(0));
305 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
306 const struct tu_subpass
*subpass
,
309 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
311 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
312 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
313 if (a
== VK_ATTACHMENT_UNUSED
)
316 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
318 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
319 tu_cs_emit(cs
, iview
->RB_MRT_BUF_INFO
);
320 tu_cs_image_ref(cs
, iview
, 0);
321 tu_cs_emit(cs
, cmd
->state
.pass
->attachments
[a
].gmem_offset
);
324 A6XX_SP_FS_MRT_REG(i
, .dword
= iview
->SP_FS_MRT_REG
));
326 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i
), 3);
327 tu_cs_image_flag_ref(cs
, iview
, 0);
331 A6XX_RB_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
333 A6XX_SP_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
335 tu_cs_emit_regs(cs
, A6XX_GRAS_MAX_LAYER_INDEX(fb
->layers
- 1));
339 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
341 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
342 bool msaa_disable
= samples
== MSAA_ONE
;
345 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
346 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
347 .msaa_disable
= msaa_disable
));
350 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
351 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
352 .msaa_disable
= msaa_disable
));
355 A6XX_RB_RAS_MSAA_CNTL(samples
),
356 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
357 .msaa_disable
= msaa_disable
));
360 A6XX_RB_MSAA_CNTL(samples
));
364 tu6_emit_bin_size(struct tu_cs
*cs
,
365 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
368 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
373 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
377 /* no flag for RB_BIN_CONTROL2... */
379 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
384 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
385 const struct tu_subpass
*subpass
,
389 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
391 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
393 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
395 uint32_t mrts_ubwc_enable
= 0;
396 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
397 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
398 if (a
== VK_ATTACHMENT_UNUSED
)
401 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
402 if (iview
->ubwc_enabled
)
403 mrts_ubwc_enable
|= 1 << i
;
406 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
408 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
409 if (a
!= VK_ATTACHMENT_UNUSED
) {
410 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
411 if (iview
->ubwc_enabled
)
412 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
415 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
416 * in order to set it correctly for the different subpasses. However,
417 * that means the packets we're emitting also happen during binning. So
418 * we need to guard the write on !BINNING at CP execution time.
420 tu_cs_reserve(cs
, 3 + 4);
421 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
422 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
423 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
424 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
427 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
428 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
429 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
430 tu_cs_emit(cs
, cntl
);
434 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
437 const VkRect2D
*render_area
= &cmd
->state
.render_area
;
439 /* Avoid assertion fails with an empty render area at (0, 0) where the
440 * subtraction below wraps around. Empty render areas should be forced to
441 * the sysmem path by use_sysmem_rendering(). It's not even clear whether
442 * an empty scissor here works, and the blob seems to force sysmem too as
443 * it sets something wrong (non-empty) for the scissor.
445 if (render_area
->extent
.width
== 0 ||
446 render_area
->extent
.height
== 0)
449 uint32_t x1
= render_area
->offset
.x
;
450 uint32_t y1
= render_area
->offset
.y
;
451 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
452 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
455 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
456 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
457 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
458 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
462 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
463 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
467 tu6_emit_window_scissor(struct tu_cs
*cs
,
474 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
475 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
478 A6XX_GRAS_2D_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
479 A6XX_GRAS_2D_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
483 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
486 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
489 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
492 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
495 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
499 tu_cs_emit_draw_state(struct tu_cs
*cs
, uint32_t id
, struct tu_draw_state state
)
501 uint32_t enable_mask
;
503 case TU_DRAW_STATE_PROGRAM
:
504 case TU_DRAW_STATE_VI
:
505 case TU_DRAW_STATE_FS_CONST
:
506 /* The blob seems to not enable this (DESC_SETS_LOAD) for binning, even
507 * when resources would actually be used in the binning shader.
508 * Presumably the overhead of prefetching the resources isn't
511 case TU_DRAW_STATE_DESC_SETS_LOAD
:
512 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
513 CP_SET_DRAW_STATE__0_SYSMEM
;
515 case TU_DRAW_STATE_PROGRAM_BINNING
:
516 case TU_DRAW_STATE_VI_BINNING
:
517 enable_mask
= CP_SET_DRAW_STATE__0_BINNING
;
519 case TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
:
520 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
;
522 case TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
:
523 enable_mask
= CP_SET_DRAW_STATE__0_SYSMEM
;
526 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
527 CP_SET_DRAW_STATE__0_SYSMEM
|
528 CP_SET_DRAW_STATE__0_BINNING
;
532 /* We need to reload the descriptors every time the descriptor sets
533 * change. However, the commands we send only depend on the pipeline
534 * because the whole point is to cache descriptors which are used by the
535 * pipeline. There's a problem here, in that the firmware has an
536 * "optimization" which skips executing groups that are set to the same
537 * value as the last draw. This means that if the descriptor sets change
538 * but not the pipeline, we'd try to re-execute the same buffer which
539 * the firmware would ignore and we wouldn't pre-load the new
540 * descriptors. Set the DIRTY bit to avoid this optimization
542 if (id
== TU_DRAW_STATE_DESC_SETS_LOAD
)
543 enable_mask
|= CP_SET_DRAW_STATE__0_DIRTY
;
545 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(state
.size
) |
547 CP_SET_DRAW_STATE__0_GROUP_ID(id
) |
548 COND(!state
.size
, CP_SET_DRAW_STATE__0_DISABLE
));
549 tu_cs_emit_qw(cs
, state
.iova
);
553 use_hw_binning(struct tu_cmd_buffer
*cmd
)
555 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
557 /* XFB commands are emitted for BINNING || SYSMEM, which makes it incompatible
558 * with non-hw binning GMEM rendering. this is required because some of the
559 * XFB commands need to only be executed once
561 if (cmd
->state
.xfb_used
)
564 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
567 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
570 return (fb
->tile_count
.width
* fb
->tile_count
.height
) > 2;
574 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
576 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
579 /* can't fit attachments into gmem */
580 if (!cmd
->state
.pass
->gmem_pixels
)
583 if (cmd
->state
.framebuffer
->layers
> 1)
586 /* Use sysmem for empty render areas */
587 if (cmd
->state
.render_area
.extent
.width
== 0 ||
588 cmd
->state
.render_area
.extent
.height
== 0)
598 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
600 uint32_t tx
, uint32_t ty
, uint32_t pipe
, uint32_t slot
)
602 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
604 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
605 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
607 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
608 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
610 const uint32_t x1
= fb
->tile0
.width
* tx
;
611 const uint32_t y1
= fb
->tile0
.height
* ty
;
612 const uint32_t x2
= x1
+ fb
->tile0
.width
- 1;
613 const uint32_t y2
= y1
+ fb
->tile0
.height
- 1;
614 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
615 tu6_emit_window_offset(cs
, x1
, y1
);
617 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
619 if (use_hw_binning(cmd
)) {
620 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
622 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
625 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5_OFFSET
, 4);
626 tu_cs_emit(cs
, fb
->pipe_sizes
[pipe
] |
627 CP_SET_BIN_DATA5_0_VSC_N(slot
));
628 tu_cs_emit(cs
, pipe
* cmd
->vsc_draw_strm_pitch
);
629 tu_cs_emit(cs
, pipe
* 4);
630 tu_cs_emit(cs
, pipe
* cmd
->vsc_prim_strm_pitch
);
632 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
635 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
638 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
641 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
647 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
652 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
653 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
654 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
656 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.render_area
);
660 tu6_emit_sysmem_resolves(struct tu_cmd_buffer
*cmd
,
662 const struct tu_subpass
*subpass
)
664 if (subpass
->resolve_attachments
) {
665 /* From the documentation for vkCmdNextSubpass, section 7.4 "Render Pass
668 * End-of-subpass multisample resolves are treated as color
669 * attachment writes for the purposes of synchronization. That is,
670 * they are considered to execute in the
671 * VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage and
672 * their writes are synchronized with
673 * VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT. Synchronization between
674 * rendering within a subpass and any resolve operations at the end
675 * of the subpass occurs automatically, without need for explicit
676 * dependencies or pipeline barriers. However, if the resolve
677 * attachment is also used in a different subpass, an explicit
678 * dependency is needed.
680 * We use the CP_BLIT path for sysmem resolves, which is really a
681 * transfer command, so we have to manually flush similar to the gmem
682 * resolve case. However, a flush afterwards isn't needed because of the
683 * last sentence and the fact that we're in sysmem mode.
685 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
);
686 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
688 /* Wait for the flushes to land before using the 2D engine */
691 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
692 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
693 if (a
== VK_ATTACHMENT_UNUSED
)
696 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
697 subpass
->color_attachments
[i
].attachment
);
703 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
705 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
706 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
708 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
709 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
710 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
711 CP_SET_DRAW_STATE__0_GROUP_ID(0));
712 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
713 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
715 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
718 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
719 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
721 tu6_emit_blit_scissor(cmd
, cs
, true);
723 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
724 if (pass
->attachments
[a
].gmem_offset
>= 0)
725 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
728 if (subpass
->resolve_attachments
) {
729 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
730 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
731 if (a
!= VK_ATTACHMENT_UNUSED
)
732 tu_store_gmem_attachment(cmd
, cs
, a
,
733 subpass
->color_attachments
[i
].attachment
);
739 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
741 struct tu_device
*dev
= cmd
->device
;
742 const struct tu_physical_device
*phys_dev
= dev
->physical_device
;
744 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
746 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(
755 .gfx_shared_const
= true,
756 .cs_shared_const
= true,
757 .gfx_bindless
= 0x1f,
758 .cs_bindless
= 0x1f));
762 cmd
->state
.cache
.pending_flush_bits
&=
763 ~(TU_CMD_FLAG_WAIT_FOR_IDLE
| TU_CMD_FLAG_CACHE_INVALIDATE
);
766 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
767 cmd
->state
.ccu_state
= TU_CMD_CCU_SYSMEM
;
768 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
769 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
770 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
771 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
772 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
773 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
774 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
775 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
777 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
778 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
779 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
780 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
781 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
782 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
783 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_SHARED_CONSTS
, 0);
784 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
785 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
786 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
787 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
788 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
789 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
791 /* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */
792 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
793 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
794 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
796 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
798 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
800 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
801 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
802 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
803 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
804 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
805 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
806 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
807 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
808 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
809 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
810 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
812 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
814 tu_cs_emit_regs(cs
, A6XX_VPC_POINT_COORD_INVERT(false));
815 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
817 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(true));
819 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
820 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
822 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
823 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
825 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
827 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
829 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
830 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
831 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
832 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
833 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
834 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
835 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
836 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
837 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
839 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
841 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
843 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
845 /* we don't use this yet.. probably best to disable.. */
846 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
847 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
848 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
849 CP_SET_DRAW_STATE__0_GROUP_ID(0));
850 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
851 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
854 A6XX_SP_HS_CTRL_REG0(0));
857 A6XX_SP_GS_CTRL_REG0(0));
860 A6XX_GRAS_LRZ_CNTL(0));
863 A6XX_RB_LRZ_CNTL(0));
866 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &dev
->global_bo
,
867 .bo_offset
= gb_offset(border_color
)));
869 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &dev
->global_bo
,
870 .bo_offset
= gb_offset(border_color
)));
873 * use vsc pitches from the largest values used so far with this device
874 * if there hasn't been overflow, there will already be a scratch bo
875 * allocated for these sizes
877 * if overflow is detected, the stream size is increased by 2x
879 mtx_lock(&dev
->vsc_pitch_mtx
);
881 struct tu6_global
*global
= dev
->global_bo
.map
;
883 uint32_t vsc_draw_overflow
= global
->vsc_draw_overflow
;
884 uint32_t vsc_prim_overflow
= global
->vsc_prim_overflow
;
886 if (vsc_draw_overflow
>= dev
->vsc_draw_strm_pitch
)
887 dev
->vsc_draw_strm_pitch
= (dev
->vsc_draw_strm_pitch
- VSC_PAD
) * 2 + VSC_PAD
;
889 if (vsc_prim_overflow
>= dev
->vsc_prim_strm_pitch
)
890 dev
->vsc_prim_strm_pitch
= (dev
->vsc_prim_strm_pitch
- VSC_PAD
) * 2 + VSC_PAD
;
892 cmd
->vsc_prim_strm_pitch
= dev
->vsc_prim_strm_pitch
;
893 cmd
->vsc_draw_strm_pitch
= dev
->vsc_draw_strm_pitch
;
895 mtx_unlock(&dev
->vsc_pitch_mtx
);
897 struct tu_bo
*vsc_bo
;
898 uint32_t size0
= cmd
->vsc_prim_strm_pitch
* MAX_VSC_PIPES
+
899 cmd
->vsc_draw_strm_pitch
* MAX_VSC_PIPES
;
901 tu_get_scratch_bo(dev
, size0
+ MAX_VSC_PIPES
* 4, &vsc_bo
);
904 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo
= vsc_bo
, .bo_offset
= size0
));
906 A6XX_VSC_PRIM_STRM_ADDRESS(.bo
= vsc_bo
));
908 A6XX_VSC_DRAW_STRM_ADDRESS(.bo
= vsc_bo
,
909 .bo_offset
= cmd
->vsc_prim_strm_pitch
* MAX_VSC_PIPES
));
911 tu_bo_list_add(&cmd
->bo_list
, vsc_bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
913 tu_cs_sanity_check(cs
);
917 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
919 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
922 A6XX_VSC_BIN_SIZE(.width
= fb
->tile0
.width
,
923 .height
= fb
->tile0
.height
));
926 A6XX_VSC_BIN_COUNT(.nx
= fb
->tile_count
.width
,
927 .ny
= fb
->tile_count
.height
));
929 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
930 tu_cs_emit_array(cs
, fb
->pipe_config
, 32);
933 A6XX_VSC_PRIM_STRM_PITCH(cmd
->vsc_prim_strm_pitch
),
934 A6XX_VSC_PRIM_STRM_LIMIT(cmd
->vsc_prim_strm_pitch
- VSC_PAD
));
937 A6XX_VSC_DRAW_STRM_PITCH(cmd
->vsc_draw_strm_pitch
),
938 A6XX_VSC_DRAW_STRM_LIMIT(cmd
->vsc_draw_strm_pitch
- VSC_PAD
));
942 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
944 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
945 const uint32_t used_pipe_count
=
946 fb
->pipe_count
.width
* fb
->pipe_count
.height
;
948 for (int i
= 0; i
< used_pipe_count
; i
++) {
949 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
950 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
951 CP_COND_WRITE5_0_WRITE_MEMORY
);
952 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i
)));
953 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
954 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_draw_strm_pitch
- VSC_PAD
));
955 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
956 tu_cs_emit_qw(cs
, global_iova(cmd
, vsc_draw_overflow
));
957 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(cmd
->vsc_draw_strm_pitch
));
959 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
960 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
961 CP_COND_WRITE5_0_WRITE_MEMORY
);
962 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i
)));
963 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
964 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_prim_strm_pitch
- VSC_PAD
));
965 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
966 tu_cs_emit_qw(cs
, global_iova(cmd
, vsc_prim_overflow
));
967 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(cmd
->vsc_prim_strm_pitch
));
970 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
974 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
976 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
977 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
979 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
981 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
982 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
984 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
987 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
993 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
995 update_vsc_pipe(cmd
, cs
);
998 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1001 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1003 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1004 tu_cs_emit(cs
, UNK_2C
);
1007 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
1010 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
1012 /* emit IB to binning drawcmds: */
1013 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1015 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1016 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1017 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1018 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1019 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1020 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1022 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1023 tu_cs_emit(cs
, UNK_2D
);
1025 /* This flush is probably required because the VSC, which produces the
1026 * visibility stream, is a client of UCHE, whereas the CP needs to read the
1027 * visibility stream (without caching) to do draw skipping. The
1028 * WFI+WAIT_FOR_ME combination guarantees that the binning commands
1029 * submitted are finished before reading the VSC regs (in
1030 * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
1033 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
);
1037 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1039 emit_vsc_overflow_test(cmd
, cs
);
1041 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1042 tu_cs_emit(cs
, 0x0);
1044 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1045 tu_cs_emit(cs
, 0x0);
1048 static struct tu_draw_state
1049 tu_emit_input_attachments(struct tu_cmd_buffer
*cmd
,
1050 const struct tu_subpass
*subpass
,
1053 /* note: we can probably emit input attachments just once for the whole
1054 * renderpass, this would avoid emitting both sysmem/gmem versions
1056 * emit two texture descriptors for each input, as a workaround for
1057 * d24s8, which can be sampled as both float (depth) and integer (stencil)
1058 * tu_shader lowers uint input attachment loads to use the 2nd descriptor
1060 * TODO: a smarter workaround
1063 if (!subpass
->input_count
)
1064 return (struct tu_draw_state
) {};
1066 struct tu_cs_memory texture
;
1067 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, subpass
->input_count
* 2,
1068 A6XX_TEX_CONST_DWORDS
, &texture
);
1069 assert(result
== VK_SUCCESS
);
1071 for (unsigned i
= 0; i
< subpass
->input_count
* 2; i
++) {
1072 uint32_t a
= subpass
->input_attachments
[i
/ 2].attachment
;
1073 if (a
== VK_ATTACHMENT_UNUSED
)
1076 struct tu_image_view
*iview
=
1077 cmd
->state
.framebuffer
->attachments
[a
].attachment
;
1078 const struct tu_render_pass_attachment
*att
=
1079 &cmd
->state
.pass
->attachments
[a
];
1080 uint32_t *dst
= &texture
.map
[A6XX_TEX_CONST_DWORDS
* i
];
1082 memcpy(dst
, iview
->descriptor
, A6XX_TEX_CONST_DWORDS
* 4);
1084 if (i
% 2 == 1 && att
->format
== VK_FORMAT_D24_UNORM_S8_UINT
) {
1085 /* note this works because spec says fb and input attachments
1086 * must use identity swizzle
1088 dst
[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK
|
1089 A6XX_TEX_CONST_0_SWIZ_X__MASK
| A6XX_TEX_CONST_0_SWIZ_Y__MASK
|
1090 A6XX_TEX_CONST_0_SWIZ_Z__MASK
| A6XX_TEX_CONST_0_SWIZ_W__MASK
);
1091 dst
[0] |= A6XX_TEX_CONST_0_FMT(FMT6_S8Z24_UINT
) |
1092 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_Y
) |
1093 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO
) |
1094 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO
) |
1095 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE
);
1101 /* patched for gmem */
1102 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
1103 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
1105 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
1106 A6XX_TEX_CONST_2_PITCH(cmd
->state
.framebuffer
->tile0
.width
* att
->cpp
);
1108 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ att
->gmem_offset
;
1109 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
1110 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
1115 struct tu_draw_state ds
= tu_cs_draw_state(&cmd
->sub_cs
, &cs
, 9);
1117 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_FRAG
, 3);
1118 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1119 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1120 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
1121 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_TEX
) |
1122 CP_LOAD_STATE6_0_NUM_UNIT(subpass
->input_count
* 2));
1123 tu_cs_emit_qw(&cs
, texture
.iova
);
1125 tu_cs_emit_pkt4(&cs
, REG_A6XX_SP_FS_TEX_CONST_LO
, 2);
1126 tu_cs_emit_qw(&cs
, texture
.iova
);
1128 tu_cs_emit_regs(&cs
, A6XX_SP_FS_TEX_COUNT(subpass
->input_count
* 2));
1130 assert(cs
.cur
== cs
.end
); /* validate draw state size */
1136 tu_set_input_attachments(struct tu_cmd_buffer
*cmd
, const struct tu_subpass
*subpass
)
1138 struct tu_cs
*cs
= &cmd
->draw_cs
;
1140 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 6);
1141 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
,
1142 tu_emit_input_attachments(cmd
, subpass
, true));
1143 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
,
1144 tu_emit_input_attachments(cmd
, subpass
, false));
1148 tu_emit_renderpass_begin(struct tu_cmd_buffer
*cmd
,
1149 const VkRenderPassBeginInfo
*info
)
1151 struct tu_cs
*cs
= &cmd
->draw_cs
;
1153 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1155 tu6_emit_blit_scissor(cmd
, cs
, true);
1157 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1158 tu_load_gmem_attachment(cmd
, cs
, i
, false);
1160 tu6_emit_blit_scissor(cmd
, cs
, false);
1162 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1163 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1165 tu_cond_exec_end(cs
);
1167 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1169 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1170 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1172 tu_cond_exec_end(cs
);
1176 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1178 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1180 assert(fb
->width
> 0 && fb
->height
> 0);
1181 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1182 tu6_emit_window_offset(cs
, 0, 0);
1184 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1186 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1188 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1189 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1191 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1192 tu_cs_emit(cs
, 0x0);
1194 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_SYSMEM
);
1196 /* enable stream-out, with sysmem there is only one pass: */
1197 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1199 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1200 tu_cs_emit(cs
, 0x1);
1202 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1203 tu_cs_emit(cs
, 0x0);
1205 tu_cs_sanity_check(cs
);
1209 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1211 /* Do any resolves of the last subpass. These are handled in the
1212 * tile_store_ib in the gmem path.
1214 tu6_emit_sysmem_resolves(cmd
, cs
, cmd
->state
.subpass
);
1216 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1218 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1219 tu_cs_emit(cs
, 0x0);
1221 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1223 tu_cs_sanity_check(cs
);
1227 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1229 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1231 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1235 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1236 tu_cs_emit(cs
, 0x0);
1238 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_GMEM
);
1240 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1241 if (use_hw_binning(cmd
)) {
1242 /* enable stream-out during binning pass: */
1243 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1245 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
,
1246 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1248 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1250 tu6_emit_binning_pass(cmd
, cs
);
1252 /* and disable stream-out for draw pass: */
1253 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(true));
1255 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
,
1256 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1259 A6XX_VFD_MODE_CNTL(0));
1261 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1263 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1265 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1266 tu_cs_emit(cs
, 0x1);
1268 /* no binning pass, so enable stream-out for draw pass:: */
1269 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1271 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
, 0x6000000);
1274 tu_cs_sanity_check(cs
);
1278 tu6_render_tile(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1280 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1282 if (use_hw_binning(cmd
)) {
1283 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1284 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1287 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1289 tu_cs_sanity_check(cs
);
1293 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1295 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1298 A6XX_GRAS_LRZ_CNTL(0));
1300 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1302 tu6_emit_event_write(cmd
, cs
, PC_CCU_RESOLVE_TS
);
1304 tu_cs_sanity_check(cs
);
1308 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1310 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1312 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1315 for (uint32_t py
= 0; py
< fb
->pipe_count
.height
; py
++) {
1316 for (uint32_t px
= 0; px
< fb
->pipe_count
.width
; px
++, pipe
++) {
1317 uint32_t tx1
= px
* fb
->pipe0
.width
;
1318 uint32_t ty1
= py
* fb
->pipe0
.height
;
1319 uint32_t tx2
= MIN2(tx1
+ fb
->pipe0
.width
, fb
->tile_count
.width
);
1320 uint32_t ty2
= MIN2(ty1
+ fb
->pipe0
.height
, fb
->tile_count
.height
);
1322 for (uint32_t ty
= ty1
; ty
< ty2
; ty
++) {
1323 for (uint32_t tx
= tx1
; tx
< tx2
; tx
++, slot
++) {
1324 tu6_emit_tile_select(cmd
, &cmd
->cs
, tx
, ty
, pipe
, slot
);
1325 tu6_render_tile(cmd
, &cmd
->cs
);
1331 tu6_tile_render_end(cmd
, &cmd
->cs
);
1335 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1337 tu6_sysmem_render_begin(cmd
, &cmd
->cs
);
1339 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1341 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1345 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1347 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1348 struct tu_cs sub_cs
;
1351 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1352 if (result
!= VK_SUCCESS
) {
1353 cmd
->record_result
= result
;
1357 /* emit to tile-store sub_cs */
1358 tu6_emit_tile_store(cmd
, &sub_cs
);
1360 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1364 tu_create_cmd_buffer(struct tu_device
*device
,
1365 struct tu_cmd_pool
*pool
,
1366 VkCommandBufferLevel level
,
1367 VkCommandBuffer
*pCommandBuffer
)
1369 struct tu_cmd_buffer
*cmd_buffer
;
1371 cmd_buffer
= vk_object_zalloc(&device
->vk
, NULL
, sizeof(*cmd_buffer
),
1372 VK_OBJECT_TYPE_COMMAND_BUFFER
);
1373 if (cmd_buffer
== NULL
)
1374 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1376 cmd_buffer
->device
= device
;
1377 cmd_buffer
->pool
= pool
;
1378 cmd_buffer
->level
= level
;
1381 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1382 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1385 /* Init the pool_link so we can safely call list_del when we destroy
1386 * the command buffer
1388 list_inithead(&cmd_buffer
->pool_link
);
1389 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1392 tu_bo_list_init(&cmd_buffer
->bo_list
);
1393 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1394 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1395 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1396 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1398 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1400 list_inithead(&cmd_buffer
->upload
.list
);
1406 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1408 list_del(&cmd_buffer
->pool_link
);
1410 tu_cs_finish(&cmd_buffer
->cs
);
1411 tu_cs_finish(&cmd_buffer
->draw_cs
);
1412 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1413 tu_cs_finish(&cmd_buffer
->sub_cs
);
1415 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1416 vk_object_free(&cmd_buffer
->device
->vk
, &cmd_buffer
->pool
->alloc
, cmd_buffer
);
1420 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1422 cmd_buffer
->record_result
= VK_SUCCESS
;
1424 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1425 tu_cs_reset(&cmd_buffer
->cs
);
1426 tu_cs_reset(&cmd_buffer
->draw_cs
);
1427 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1428 tu_cs_reset(&cmd_buffer
->sub_cs
);
1430 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++)
1431 memset(&cmd_buffer
->descriptors
[i
].sets
, 0, sizeof(cmd_buffer
->descriptors
[i
].sets
));
1433 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1435 return cmd_buffer
->record_result
;
1439 tu_AllocateCommandBuffers(VkDevice _device
,
1440 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1441 VkCommandBuffer
*pCommandBuffers
)
1443 TU_FROM_HANDLE(tu_device
, device
, _device
);
1444 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1446 VkResult result
= VK_SUCCESS
;
1449 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1451 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1452 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1453 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1455 list_del(&cmd_buffer
->pool_link
);
1456 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1458 result
= tu_reset_cmd_buffer(cmd_buffer
);
1459 cmd_buffer
->level
= pAllocateInfo
->level
;
1461 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1463 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1464 &pCommandBuffers
[i
]);
1466 if (result
!= VK_SUCCESS
)
1470 if (result
!= VK_SUCCESS
) {
1471 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1474 /* From the Vulkan 1.0.66 spec:
1476 * "vkAllocateCommandBuffers can be used to create multiple
1477 * command buffers. If the creation of any of those command
1478 * buffers fails, the implementation must destroy all
1479 * successfully created command buffer objects from this
1480 * command, set all entries of the pCommandBuffers array to
1481 * NULL and return the error."
1483 memset(pCommandBuffers
, 0,
1484 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1491 tu_FreeCommandBuffers(VkDevice device
,
1492 VkCommandPool commandPool
,
1493 uint32_t commandBufferCount
,
1494 const VkCommandBuffer
*pCommandBuffers
)
1496 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1497 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1500 if (cmd_buffer
->pool
) {
1501 list_del(&cmd_buffer
->pool_link
);
1502 list_addtail(&cmd_buffer
->pool_link
,
1503 &cmd_buffer
->pool
->free_cmd_buffers
);
1505 tu_cmd_buffer_destroy(cmd_buffer
);
1511 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1512 VkCommandBufferResetFlags flags
)
1514 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1515 return tu_reset_cmd_buffer(cmd_buffer
);
1518 /* Initialize the cache, assuming all necessary flushes have happened but *not*
1522 tu_cache_init(struct tu_cache_state
*cache
)
1524 cache
->flush_bits
= 0;
1525 cache
->pending_flush_bits
= TU_CMD_FLAG_ALL_INVALIDATE
;
1529 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1530 const VkCommandBufferBeginInfo
*pBeginInfo
)
1532 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1533 VkResult result
= VK_SUCCESS
;
1535 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1536 /* If the command buffer has already been resetted with
1537 * vkResetCommandBuffer, no need to do it again.
1539 result
= tu_reset_cmd_buffer(cmd_buffer
);
1540 if (result
!= VK_SUCCESS
)
1544 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1545 cmd_buffer
->state
.index_size
= 0xff; /* dirty restart index */
1547 tu_cache_init(&cmd_buffer
->state
.cache
);
1548 tu_cache_init(&cmd_buffer
->state
.renderpass_cache
);
1549 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1551 tu_cs_begin(&cmd_buffer
->cs
);
1552 tu_cs_begin(&cmd_buffer
->draw_cs
);
1553 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1555 /* setup initial configuration into command buffer */
1556 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1557 switch (cmd_buffer
->queue_family_index
) {
1558 case TU_QUEUE_GENERAL
:
1559 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1564 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1565 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1566 assert(pBeginInfo
->pInheritanceInfo
);
1567 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1568 cmd_buffer
->state
.subpass
=
1569 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1571 /* When executing in the middle of another command buffer, the CCU
1574 cmd_buffer
->state
.ccu_state
= TU_CMD_CCU_UNKNOWN
;
1578 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1583 /* Sets vertex buffers to HW binding points. We emit VBs in SDS (so that bin
1584 * rendering can skip over unused state), so we need to collect all the
1585 * bindings together into a single state emit at draw time.
1588 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1589 uint32_t firstBinding
,
1590 uint32_t bindingCount
,
1591 const VkBuffer
*pBuffers
,
1592 const VkDeviceSize
*pOffsets
)
1594 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1596 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1598 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1599 struct tu_buffer
*buf
= tu_buffer_from_handle(pBuffers
[i
]);
1601 cmd
->state
.vb
.buffers
[firstBinding
+ i
] = buf
;
1602 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1604 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1607 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1611 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1613 VkDeviceSize offset
,
1614 VkIndexType indexType
)
1616 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1617 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1621 uint32_t index_size
, index_shift
, restart_index
;
1623 switch (indexType
) {
1624 case VK_INDEX_TYPE_UINT16
:
1625 index_size
= INDEX4_SIZE_16_BIT
;
1627 restart_index
= 0xffff;
1629 case VK_INDEX_TYPE_UINT32
:
1630 index_size
= INDEX4_SIZE_32_BIT
;
1632 restart_index
= 0xffffffff;
1634 case VK_INDEX_TYPE_UINT8_EXT
:
1635 index_size
= INDEX4_SIZE_8_BIT
;
1637 restart_index
= 0xff;
1640 unreachable("invalid VkIndexType");
1643 /* initialize/update the restart index */
1644 if (cmd
->state
.index_size
!= index_size
)
1645 tu_cs_emit_regs(&cmd
->draw_cs
, A6XX_PC_RESTART_INDEX(restart_index
));
1647 assert(buf
->size
>= offset
);
1649 cmd
->state
.index_va
= buf
->bo
->iova
+ buf
->bo_offset
+ offset
;
1650 cmd
->state
.max_index_count
= (buf
->size
- offset
) >> index_shift
;
1651 cmd
->state
.index_size
= index_size
;
1653 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1657 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1658 VkPipelineBindPoint pipelineBindPoint
,
1659 VkPipelineLayout _layout
,
1661 uint32_t descriptorSetCount
,
1662 const VkDescriptorSet
*pDescriptorSets
,
1663 uint32_t dynamicOffsetCount
,
1664 const uint32_t *pDynamicOffsets
)
1666 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1667 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1668 unsigned dyn_idx
= 0;
1670 struct tu_descriptor_state
*descriptors_state
=
1671 tu_get_descriptors_state(cmd
, pipelineBindPoint
);
1673 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1674 unsigned idx
= i
+ firstSet
;
1675 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1677 descriptors_state
->sets
[idx
] = set
;
1679 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1680 /* update the contents of the dynamic descriptor set */
1681 unsigned src_idx
= j
;
1682 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1683 assert(dyn_idx
< dynamicOffsetCount
);
1686 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1688 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1689 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1691 /* Patch the storage/uniform descriptors right away. */
1692 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1693 /* Note: we can assume here that the addition won't roll over and
1694 * change the SIZE field.
1696 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1701 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1702 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1703 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1710 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
1711 if (set
->buffers
[j
]) {
1712 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
1713 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1717 if (set
->size
> 0) {
1718 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
1719 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1722 assert(dyn_idx
== dynamicOffsetCount
);
1724 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
, hlsq_invalidate_value
;
1725 uint64_t addr
[MAX_SETS
+ 1] = {};
1726 struct tu_cs
*cs
, state_cs
;
1728 for (uint32_t i
= 0; i
< MAX_SETS
; i
++) {
1729 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
1731 addr
[i
] = set
->va
| 3;
1734 if (layout
->dynamic_offset_count
) {
1735 /* allocate and fill out dynamic descriptor set */
1736 struct tu_cs_memory dynamic_desc_set
;
1737 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, layout
->dynamic_offset_count
,
1738 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
1739 assert(result
== VK_SUCCESS
);
1741 memcpy(dynamic_desc_set
.map
, descriptors_state
->dynamic_descriptors
,
1742 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
1743 addr
[MAX_SETS
] = dynamic_desc_set
.iova
| 3;
1746 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1747 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
1748 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
1749 hlsq_invalidate_value
= A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(0x1f);
1751 cmd
->state
.desc_sets
= tu_cs_draw_state(&cmd
->sub_cs
, &state_cs
, 24);
1752 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESC_SETS_LOAD
| TU_CMD_DIRTY_SHADER_CONSTS
;
1755 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1757 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
1758 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
1759 hlsq_invalidate_value
= A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(0x1f);
1761 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
1765 tu_cs_emit_pkt4(cs
, sp_bindless_base_reg
, 10);
1766 tu_cs_emit_array(cs
, (const uint32_t*) addr
, 10);
1767 tu_cs_emit_pkt4(cs
, hlsq_bindless_base_reg
, 10);
1768 tu_cs_emit_array(cs
, (const uint32_t*) addr
, 10);
1769 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(.dword
= hlsq_invalidate_value
));
1771 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1772 assert(cs
->cur
== cs
->end
); /* validate draw state size */
1773 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
1774 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets
);
1778 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
1779 uint32_t firstBinding
,
1780 uint32_t bindingCount
,
1781 const VkBuffer
*pBuffers
,
1782 const VkDeviceSize
*pOffsets
,
1783 const VkDeviceSize
*pSizes
)
1785 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1786 struct tu_cs
*cs
= &cmd
->draw_cs
;
1788 /* using COND_REG_EXEC for xfb commands matches the blob behavior
1789 * presumably there isn't any benefit using a draw state when the
1790 * condition is (SYSMEM | BINNING)
1792 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1793 CP_COND_REG_EXEC_0_SYSMEM
|
1794 CP_COND_REG_EXEC_0_BINNING
);
1796 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1797 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
1798 uint64_t iova
= buf
->bo
->iova
+ pOffsets
[i
];
1799 uint32_t size
= buf
->bo
->size
- pOffsets
[i
];
1800 uint32_t idx
= i
+ firstBinding
;
1802 if (pSizes
&& pSizes
[i
] != VK_WHOLE_SIZE
)
1805 /* BUFFER_BASE is 32-byte aligned, add remaining offset to BUFFER_OFFSET */
1806 uint32_t offset
= iova
& 0x1f;
1807 iova
&= ~(uint64_t) 0x1f;
1809 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_BASE(idx
), 3);
1810 tu_cs_emit_qw(cs
, iova
);
1811 tu_cs_emit(cs
, size
+ offset
);
1813 cmd
->state
.streamout_offset
[idx
] = offset
;
1815 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_WRITE
);
1818 tu_cond_exec_end(cs
);
1822 tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1823 uint32_t firstCounterBuffer
,
1824 uint32_t counterBufferCount
,
1825 const VkBuffer
*pCounterBuffers
,
1826 const VkDeviceSize
*pCounterBufferOffsets
)
1828 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1829 struct tu_cs
*cs
= &cmd
->draw_cs
;
1831 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1832 CP_COND_REG_EXEC_0_SYSMEM
|
1833 CP_COND_REG_EXEC_0_BINNING
);
1835 /* TODO: only update offset for active buffers */
1836 for (uint32_t i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++)
1837 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, cmd
->state
.streamout_offset
[i
]));
1839 for (uint32_t i
= 0; i
< counterBufferCount
; i
++) {
1840 uint32_t idx
= firstCounterBuffer
+ i
;
1841 uint32_t offset
= cmd
->state
.streamout_offset
[idx
];
1843 if (!pCounterBuffers
[i
])
1846 TU_FROM_HANDLE(tu_buffer
, buf
, pCounterBuffers
[i
]);
1848 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1850 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1851 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx
)) |
1852 CP_MEM_TO_REG_0_UNK31
|
1853 CP_MEM_TO_REG_0_CNT(1));
1854 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ pCounterBufferOffsets
[i
]);
1857 tu_cs_emit_pkt7(cs
, CP_REG_RMW
, 3);
1858 tu_cs_emit(cs
, CP_REG_RMW_0_DST_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx
)) |
1859 CP_REG_RMW_0_SRC1_ADD
);
1860 tu_cs_emit_qw(cs
, 0xffffffff);
1861 tu_cs_emit_qw(cs
, offset
);
1865 tu_cond_exec_end(cs
);
1868 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1869 uint32_t firstCounterBuffer
,
1870 uint32_t counterBufferCount
,
1871 const VkBuffer
*pCounterBuffers
,
1872 const VkDeviceSize
*pCounterBufferOffsets
)
1874 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1875 struct tu_cs
*cs
= &cmd
->draw_cs
;
1877 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1878 CP_COND_REG_EXEC_0_SYSMEM
|
1879 CP_COND_REG_EXEC_0_BINNING
);
1881 /* TODO: only flush buffers that need to be flushed */
1882 for (uint32_t i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
1883 /* note: FLUSH_BASE is always the same, so it could go in init_hw()? */
1884 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_FLUSH_BASE(i
), 2);
1885 tu_cs_emit_qw(cs
, global_iova(cmd
, flush_base
[i
]));
1886 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
);
1889 for (uint32_t i
= 0; i
< counterBufferCount
; i
++) {
1890 uint32_t idx
= firstCounterBuffer
+ i
;
1891 uint32_t offset
= cmd
->state
.streamout_offset
[idx
];
1893 if (!pCounterBuffers
[i
])
1896 TU_FROM_HANDLE(tu_buffer
, buf
, pCounterBuffers
[i
]);
1898 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_WRITE
);
1900 /* VPC_SO_FLUSH_BASE has dwords counter, but counter should be in bytes */
1901 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1902 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1903 CP_MEM_TO_REG_0_SHIFT_BY_2
|
1905 CP_MEM_TO_REG_0_UNK31
|
1906 CP_MEM_TO_REG_0_CNT(1));
1907 tu_cs_emit_qw(cs
, global_iova(cmd
, flush_base
[idx
]));
1910 tu_cs_emit_pkt7(cs
, CP_REG_RMW
, 3);
1911 tu_cs_emit(cs
, CP_REG_RMW_0_DST_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1912 CP_REG_RMW_0_SRC1_ADD
);
1913 tu_cs_emit_qw(cs
, 0xffffffff);
1914 tu_cs_emit_qw(cs
, -offset
);
1917 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
1918 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1919 CP_REG_TO_MEM_0_CNT(1));
1920 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ pCounterBufferOffsets
[i
]);
1923 tu_cond_exec_end(cs
);
1925 cmd
->state
.xfb_used
= true;
1929 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1930 VkPipelineLayout layout
,
1931 VkShaderStageFlags stageFlags
,
1934 const void *pValues
)
1936 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1937 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1938 cmd
->state
.dirty
|= TU_CMD_DIRTY_SHADER_CONSTS
;
1941 /* Flush everything which has been made available but we haven't actually
1945 tu_flush_all_pending(struct tu_cache_state
*cache
)
1947 cache
->flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
1948 cache
->pending_flush_bits
&= ~TU_CMD_FLAG_ALL_FLUSH
;
1952 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
1954 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1956 /* We currently flush CCU at the end of the command buffer, like
1957 * what the blob does. There's implicit synchronization around every
1958 * vkQueueSubmit, but the kernel only flushes the UCHE, and we don't
1959 * know yet if this command buffer will be the last in the submit so we
1960 * have to defensively flush everything else.
1962 * TODO: We could definitely do better than this, since these flushes
1963 * aren't required by Vulkan, but we'd need kernel support to do that.
1964 * Ideally, we'd like the kernel to flush everything afterwards, so that we
1965 * wouldn't have to do any flushes here, and when submitting multiple
1966 * command buffers there wouldn't be any unnecessary flushes in between.
1968 if (cmd_buffer
->state
.pass
) {
1969 tu_flush_all_pending(&cmd_buffer
->state
.renderpass_cache
);
1970 tu_emit_cache_flush_renderpass(cmd_buffer
, &cmd_buffer
->draw_cs
);
1972 tu_flush_all_pending(&cmd_buffer
->state
.cache
);
1973 cmd_buffer
->state
.cache
.flush_bits
|=
1974 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
1975 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
1976 tu_emit_cache_flush(cmd_buffer
, &cmd_buffer
->cs
);
1979 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->global_bo
,
1980 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1982 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
1983 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
1984 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1987 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
1988 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
1989 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1992 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
1993 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
1994 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1997 tu_cs_end(&cmd_buffer
->cs
);
1998 tu_cs_end(&cmd_buffer
->draw_cs
);
1999 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
2001 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
2003 return cmd_buffer
->record_result
;
2007 tu_cmd_dynamic_state(struct tu_cmd_buffer
*cmd
, uint32_t id
, uint32_t size
)
2011 assert(id
< ARRAY_SIZE(cmd
->state
.dynamic_state
));
2012 cmd
->state
.dynamic_state
[id
] = tu_cs_draw_state(&cmd
->sub_cs
, &cs
, size
);
2014 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
2015 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DYNAMIC
+ id
, cmd
->state
.dynamic_state
[id
]);
2021 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
2022 VkPipelineBindPoint pipelineBindPoint
,
2023 VkPipeline _pipeline
)
2025 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2026 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2028 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2029 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2030 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2033 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
) {
2034 cmd
->state
.compute_pipeline
= pipeline
;
2035 tu_cs_emit_state_ib(&cmd
->cs
, pipeline
->program
.state
);
2039 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
);
2041 cmd
->state
.pipeline
= pipeline
;
2042 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESC_SETS_LOAD
| TU_CMD_DIRTY_SHADER_CONSTS
;
2044 struct tu_cs
*cs
= &cmd
->draw_cs
;
2045 uint32_t mask
= ~pipeline
->dynamic_state_mask
& BITFIELD_MASK(TU_DYNAMIC_STATE_COUNT
);
2048 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (7 + util_bitcount(mask
)));
2049 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state
);
2050 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state
);
2051 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state
);
2052 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state
);
2053 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast_state
);
2054 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS
, pipeline
->ds_state
);
2055 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend_state
);
2056 for_each_bit(i
, mask
)
2057 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
, pipeline
->dynamic_state
[i
]);
2059 /* If the new pipeline requires more VBs than we had previously set up, we
2060 * need to re-emit them in SDS. If it requires the same set or fewer, we
2061 * can just re-use the old SDS.
2063 if (pipeline
->vi
.bindings_used
& ~cmd
->vertex_bindings_set
)
2064 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
2066 /* dynamic linewidth state depends pipeline state's gras_su_cntl
2067 * so the dynamic state ib must be updated when pipeline changes
2069 if (pipeline
->dynamic_state_mask
& BIT(VK_DYNAMIC_STATE_LINE_WIDTH
)) {
2070 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2072 cmd
->state
.dynamic_gras_su_cntl
&= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2073 cmd
->state
.dynamic_gras_su_cntl
|= pipeline
->gras_su_cntl
;
2075 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2080 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2081 uint32_t firstViewport
,
2082 uint32_t viewportCount
,
2083 const VkViewport
*pViewports
)
2085 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2086 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_VIEWPORT
, 18);
2088 assert(firstViewport
== 0 && viewportCount
== 1);
2090 tu6_emit_viewport(&cs
, pViewports
);
2094 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2095 uint32_t firstScissor
,
2096 uint32_t scissorCount
,
2097 const VkRect2D
*pScissors
)
2099 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2100 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_SCISSOR
, 3);
2102 assert(firstScissor
== 0 && scissorCount
== 1);
2104 tu6_emit_scissor(&cs
, pScissors
);
2108 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2110 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2111 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2113 cmd
->state
.dynamic_gras_su_cntl
&= ~A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2114 cmd
->state
.dynamic_gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(lineWidth
/ 2.0f
);
2116 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2120 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2121 float depthBiasConstantFactor
,
2122 float depthBiasClamp
,
2123 float depthBiasSlopeFactor
)
2125 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2126 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BIAS
, 4);
2128 tu6_emit_depth_bias(&cs
, depthBiasConstantFactor
, depthBiasClamp
, depthBiasSlopeFactor
);
2132 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2133 const float blendConstants
[4])
2135 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2136 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_BLEND_CONSTANTS
, 5);
2138 tu_cs_emit_pkt4(&cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2139 tu_cs_emit_array(&cs
, (const uint32_t *) blendConstants
, 4);
2143 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2144 float minDepthBounds
,
2145 float maxDepthBounds
)
2147 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2148 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BOUNDS
, 3);
2150 tu_cs_emit_regs(&cs
,
2151 A6XX_RB_Z_BOUNDS_MIN(minDepthBounds
),
2152 A6XX_RB_Z_BOUNDS_MAX(maxDepthBounds
));
2156 update_stencil_mask(uint32_t *value
, VkStencilFaceFlags face
, uint32_t mask
)
2158 if (face
& VK_STENCIL_FACE_FRONT_BIT
)
2159 *value
= (*value
& 0xff00) | (mask
& 0xff);
2160 if (face
& VK_STENCIL_FACE_BACK_BIT
)
2161 *value
= (*value
& 0xff) | (mask
& 0xff) << 8;
2165 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2166 VkStencilFaceFlags faceMask
,
2167 uint32_t compareMask
)
2169 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2170 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
, 2);
2172 update_stencil_mask(&cmd
->state
.dynamic_stencil_mask
, faceMask
, compareMask
);
2174 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILMASK(.dword
= cmd
->state
.dynamic_stencil_mask
));
2178 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2179 VkStencilFaceFlags faceMask
,
2182 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2183 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
, 2);
2185 update_stencil_mask(&cmd
->state
.dynamic_stencil_wrmask
, faceMask
, writeMask
);
2187 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILWRMASK(.dword
= cmd
->state
.dynamic_stencil_wrmask
));
2191 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2192 VkStencilFaceFlags faceMask
,
2195 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2196 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_REFERENCE
, 2);
2198 update_stencil_mask(&cmd
->state
.dynamic_stencil_ref
, faceMask
, reference
);
2200 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILREF(.dword
= cmd
->state
.dynamic_stencil_ref
));
2204 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer
,
2205 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
2207 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2208 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
, 9);
2210 assert(pSampleLocationsInfo
);
2212 tu6_emit_sample_locations(&cs
, pSampleLocationsInfo
);
2216 tu_flush_for_access(struct tu_cache_state
*cache
,
2217 enum tu_cmd_access_mask src_mask
,
2218 enum tu_cmd_access_mask dst_mask
)
2220 enum tu_cmd_flush_bits flush_bits
= 0;
2222 if (src_mask
& TU_ACCESS_HOST_WRITE
) {
2223 /* Host writes are always visible to CP, so only invalidate GPU caches */
2224 cache
->pending_flush_bits
|= TU_CMD_FLAG_GPU_INVALIDATE
;
2227 if (src_mask
& TU_ACCESS_SYSMEM_WRITE
) {
2228 /* Invalidate CP and 2D engine (make it do WFI + WFM if necessary) as
2231 cache
->pending_flush_bits
|= TU_CMD_FLAG_ALL_INVALIDATE
;
2234 if (src_mask
& TU_ACCESS_CP_WRITE
) {
2235 /* Flush the CP write queue. However a WFI shouldn't be necessary as
2236 * WAIT_MEM_WRITES should cover it.
2238 cache
->pending_flush_bits
|=
2239 TU_CMD_FLAG_WAIT_MEM_WRITES
|
2240 TU_CMD_FLAG_GPU_INVALIDATE
|
2241 TU_CMD_FLAG_WAIT_FOR_ME
;
2244 #define SRC_FLUSH(domain, flush, invalidate) \
2245 if (src_mask & TU_ACCESS_##domain##_WRITE) { \
2246 cache->pending_flush_bits |= TU_CMD_FLAG_##flush | \
2247 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2250 SRC_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2251 SRC_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2252 SRC_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2256 #define SRC_INCOHERENT_FLUSH(domain, flush, invalidate) \
2257 if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
2258 flush_bits |= TU_CMD_FLAG_##flush; \
2259 cache->pending_flush_bits |= \
2260 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2263 SRC_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2264 SRC_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2266 #undef SRC_INCOHERENT_FLUSH
2268 /* Treat host & sysmem write accesses the same, since the kernel implicitly
2269 * drains the queue before signalling completion to the host.
2271 if (dst_mask
& (TU_ACCESS_SYSMEM_READ
| TU_ACCESS_SYSMEM_WRITE
|
2272 TU_ACCESS_HOST_READ
| TU_ACCESS_HOST_WRITE
)) {
2273 flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
2276 #define DST_FLUSH(domain, flush, invalidate) \
2277 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2278 TU_ACCESS_##domain##_WRITE)) { \
2279 flush_bits |= cache->pending_flush_bits & \
2280 (TU_CMD_FLAG_##invalidate | \
2281 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2284 DST_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2285 DST_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2286 DST_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2290 #define DST_INCOHERENT_FLUSH(domain, flush, invalidate) \
2291 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2292 TU_ACCESS_##domain##_WRITE)) { \
2293 flush_bits |= TU_CMD_FLAG_##invalidate | \
2294 (cache->pending_flush_bits & \
2295 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2298 DST_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2299 DST_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2301 #undef DST_INCOHERENT_FLUSH
2303 if (dst_mask
& TU_ACCESS_WFI_READ
) {
2304 flush_bits
|= cache
->pending_flush_bits
&
2305 (TU_CMD_FLAG_ALL_FLUSH
| TU_CMD_FLAG_WAIT_FOR_IDLE
);
2308 if (dst_mask
& TU_ACCESS_WFM_READ
) {
2309 flush_bits
|= cache
->pending_flush_bits
&
2310 (TU_CMD_FLAG_ALL_FLUSH
| TU_CMD_FLAG_WAIT_FOR_ME
);
2313 cache
->flush_bits
|= flush_bits
;
2314 cache
->pending_flush_bits
&= ~flush_bits
;
2317 static enum tu_cmd_access_mask
2318 vk2tu_access(VkAccessFlags flags
, bool gmem
)
2320 enum tu_cmd_access_mask mask
= 0;
2322 /* If the GPU writes a buffer that is then read by an indirect draw
2323 * command, we theoretically need to emit a WFI to wait for any cache
2324 * flushes, and then a WAIT_FOR_ME to wait on the CP for the WFI to
2325 * complete. Waiting for the WFI to complete is performed as part of the
2326 * draw by the firmware, so we just need to execute the WFI.
2328 * Transform feedback counters are read via CP_MEM_TO_REG, which implicitly
2329 * does CP_WAIT_FOR_ME, but we still need a WFI if the GPU writes it.
2332 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
|
2333 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
|
2334 VK_ACCESS_MEMORY_READ_BIT
)) {
2335 mask
|= TU_ACCESS_WFI_READ
;
2339 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
| /* Read performed by CP */
2340 VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
| /* Read performed by CP */
2341 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
| /* Read performed by CP */
2342 VK_ACCESS_MEMORY_READ_BIT
)) {
2343 mask
|= TU_ACCESS_SYSMEM_READ
;
2347 (VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
|
2348 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2349 mask
|= TU_ACCESS_CP_WRITE
;
2353 (VK_ACCESS_HOST_READ_BIT
|
2354 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2355 mask
|= TU_ACCESS_HOST_READ
;
2359 (VK_ACCESS_HOST_WRITE_BIT
|
2360 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2361 mask
|= TU_ACCESS_HOST_WRITE
;
2365 (VK_ACCESS_INDEX_READ_BIT
| /* Read performed by PC, I think */
2366 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
| /* Read performed by VFD */
2367 VK_ACCESS_UNIFORM_READ_BIT
| /* Read performed by SP */
2368 /* TODO: Is there a no-cache bit for textures so that we can ignore
2371 VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
| /* Read performed by TP */
2372 VK_ACCESS_SHADER_READ_BIT
| /* Read perfomed by SP/TP */
2373 VK_ACCESS_MEMORY_READ_BIT
)) {
2374 mask
|= TU_ACCESS_UCHE_READ
;
2378 (VK_ACCESS_SHADER_WRITE_BIT
| /* Write performed by SP */
2379 VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
| /* Write performed by VPC */
2380 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2381 mask
|= TU_ACCESS_UCHE_WRITE
;
2384 /* When using GMEM, the CCU is always flushed automatically to GMEM, and
2385 * then GMEM is flushed to sysmem. Furthermore, we already had to flush any
2386 * previous writes in sysmem mode when transitioning to GMEM. Therefore we
2387 * can ignore CCU and pretend that color attachments and transfers use
2392 (VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
|
2393 VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT
|
2394 VK_ACCESS_MEMORY_READ_BIT
)) {
2396 mask
|= TU_ACCESS_SYSMEM_READ
;
2398 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_READ
;
2402 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
|
2403 VK_ACCESS_MEMORY_READ_BIT
)) {
2405 mask
|= TU_ACCESS_SYSMEM_READ
;
2407 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
;
2411 (VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
|
2412 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2414 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2416 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2421 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
|
2422 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2424 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2426 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2430 /* When the dst access is a transfer read/write, it seems we sometimes need
2431 * to insert a WFI after any flushes, to guarantee that the flushes finish
2432 * before the 2D engine starts. However the opposite (i.e. a WFI after
2433 * CP_BLIT and before any subsequent flush) does not seem to be needed, and
2434 * the blob doesn't emit such a WFI.
2438 (VK_ACCESS_TRANSFER_WRITE_BIT
|
2439 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2441 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2443 mask
|= TU_ACCESS_CCU_COLOR_WRITE
;
2445 mask
|= TU_ACCESS_WFI_READ
;
2449 (VK_ACCESS_TRANSFER_READ_BIT
| /* Access performed by TP */
2450 VK_ACCESS_MEMORY_READ_BIT
)) {
2451 mask
|= TU_ACCESS_UCHE_READ
| TU_ACCESS_WFI_READ
;
2459 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2460 uint32_t commandBufferCount
,
2461 const VkCommandBuffer
*pCmdBuffers
)
2463 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2466 assert(commandBufferCount
> 0);
2468 /* Emit any pending flushes. */
2469 if (cmd
->state
.pass
) {
2470 tu_flush_all_pending(&cmd
->state
.renderpass_cache
);
2471 tu_emit_cache_flush_renderpass(cmd
, &cmd
->draw_cs
);
2473 tu_flush_all_pending(&cmd
->state
.cache
);
2474 tu_emit_cache_flush(cmd
, &cmd
->cs
);
2477 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2478 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2480 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2481 if (result
!= VK_SUCCESS
) {
2482 cmd
->record_result
= result
;
2486 if (secondary
->usage_flags
&
2487 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2488 assert(tu_cs_is_empty(&secondary
->cs
));
2490 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2491 if (result
!= VK_SUCCESS
) {
2492 cmd
->record_result
= result
;
2496 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2497 &secondary
->draw_epilogue_cs
);
2498 if (result
!= VK_SUCCESS
) {
2499 cmd
->record_result
= result
;
2503 if (secondary
->has_tess
)
2504 cmd
->has_tess
= true;
2506 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2507 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2509 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2510 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2511 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2514 tu_cs_add_entries(&cmd
->cs
, &secondary
->cs
);
2517 cmd
->state
.index_size
= secondary
->state
.index_size
; /* for restart index update */
2519 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2521 /* After executing secondary command buffers, there may have been arbitrary
2522 * flushes executed, so when we encounter a pipeline barrier with a
2523 * srcMask, we have to assume that we need to invalidate. Therefore we need
2524 * to re-initialize the cache with all pending invalidate bits set.
2526 if (cmd
->state
.pass
) {
2527 tu_cache_init(&cmd
->state
.renderpass_cache
);
2529 tu_cache_init(&cmd
->state
.cache
);
2534 tu_CreateCommandPool(VkDevice _device
,
2535 const VkCommandPoolCreateInfo
*pCreateInfo
,
2536 const VkAllocationCallbacks
*pAllocator
,
2537 VkCommandPool
*pCmdPool
)
2539 TU_FROM_HANDLE(tu_device
, device
, _device
);
2540 struct tu_cmd_pool
*pool
;
2542 pool
= vk_object_alloc(&device
->vk
, pAllocator
, sizeof(*pool
),
2543 VK_OBJECT_TYPE_COMMAND_POOL
);
2545 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2548 pool
->alloc
= *pAllocator
;
2550 pool
->alloc
= device
->vk
.alloc
;
2552 list_inithead(&pool
->cmd_buffers
);
2553 list_inithead(&pool
->free_cmd_buffers
);
2555 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2557 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2563 tu_DestroyCommandPool(VkDevice _device
,
2564 VkCommandPool commandPool
,
2565 const VkAllocationCallbacks
*pAllocator
)
2567 TU_FROM_HANDLE(tu_device
, device
, _device
);
2568 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2573 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2574 &pool
->cmd_buffers
, pool_link
)
2576 tu_cmd_buffer_destroy(cmd_buffer
);
2579 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2580 &pool
->free_cmd_buffers
, pool_link
)
2582 tu_cmd_buffer_destroy(cmd_buffer
);
2585 vk_object_free(&device
->vk
, pAllocator
, pool
);
2589 tu_ResetCommandPool(VkDevice device
,
2590 VkCommandPool commandPool
,
2591 VkCommandPoolResetFlags flags
)
2593 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2596 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2599 result
= tu_reset_cmd_buffer(cmd_buffer
);
2600 if (result
!= VK_SUCCESS
)
2608 tu_TrimCommandPool(VkDevice device
,
2609 VkCommandPool commandPool
,
2610 VkCommandPoolTrimFlags flags
)
2612 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2617 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2618 &pool
->free_cmd_buffers
, pool_link
)
2620 tu_cmd_buffer_destroy(cmd_buffer
);
2625 tu_subpass_barrier(struct tu_cmd_buffer
*cmd_buffer
,
2626 const struct tu_subpass_barrier
*barrier
,
2629 /* Note: we don't know until the end of the subpass whether we'll use
2630 * sysmem, so assume sysmem here to be safe.
2632 struct tu_cache_state
*cache
=
2633 external
? &cmd_buffer
->state
.cache
: &cmd_buffer
->state
.renderpass_cache
;
2634 enum tu_cmd_access_mask src_flags
=
2635 vk2tu_access(barrier
->src_access_mask
, false);
2636 enum tu_cmd_access_mask dst_flags
=
2637 vk2tu_access(barrier
->dst_access_mask
, false);
2639 if (barrier
->incoherent_ccu_color
)
2640 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2641 if (barrier
->incoherent_ccu_depth
)
2642 src_flags
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2644 tu_flush_for_access(cache
, src_flags
, dst_flags
);
2648 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2649 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2650 VkSubpassContents contents
)
2652 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2653 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2654 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2656 cmd
->state
.pass
= pass
;
2657 cmd
->state
.subpass
= pass
->subpasses
;
2658 cmd
->state
.framebuffer
= fb
;
2659 cmd
->state
.render_area
= pRenderPassBegin
->renderArea
;
2661 tu_cmd_prepare_tile_store_ib(cmd
);
2663 /* Note: because this is external, any flushes will happen before draw_cs
2664 * gets called. However deferred flushes could have to happen later as part
2667 tu_subpass_barrier(cmd
, &pass
->subpasses
[0].start_barrier
, true);
2668 cmd
->state
.renderpass_cache
.pending_flush_bits
=
2669 cmd
->state
.cache
.pending_flush_bits
;
2670 cmd
->state
.renderpass_cache
.flush_bits
= 0;
2672 tu_emit_renderpass_begin(cmd
, pRenderPassBegin
);
2674 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2675 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2676 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2677 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2679 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2681 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2682 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2683 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2684 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2687 cmd
->state
.dirty
|= TU_CMD_DIRTY_DRAW_STATE
;
2691 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2692 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2693 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2695 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2696 pSubpassBeginInfo
->contents
);
2700 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2702 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2703 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2704 struct tu_cs
*cs
= &cmd
->draw_cs
;
2706 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2708 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2710 if (subpass
->resolve_attachments
) {
2711 tu6_emit_blit_scissor(cmd
, cs
, true);
2713 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2714 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2715 if (a
== VK_ATTACHMENT_UNUSED
)
2718 tu_store_gmem_attachment(cmd
, cs
, a
,
2719 subpass
->color_attachments
[i
].attachment
);
2721 if (pass
->attachments
[a
].gmem_offset
< 0)
2725 * check if the resolved attachment is needed by later subpasses,
2726 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2728 tu_finishme("missing GMEM->GMEM resolve path\n");
2729 tu_load_gmem_attachment(cmd
, cs
, a
, true);
2733 tu_cond_exec_end(cs
);
2735 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2737 tu6_emit_sysmem_resolves(cmd
, cs
, subpass
);
2739 tu_cond_exec_end(cs
);
2741 /* Handle dependencies for the next subpass */
2742 tu_subpass_barrier(cmd
, &cmd
->state
.subpass
->start_barrier
, false);
2744 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2745 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2746 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2747 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2748 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2750 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2754 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2755 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2756 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2758 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2762 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2763 struct tu_descriptor_state
*descriptors_state
,
2764 gl_shader_stage type
,
2765 uint32_t *push_constants
)
2767 const struct tu_program_descriptor_linkage
*link
=
2768 &pipeline
->program
.link
[type
];
2769 const struct ir3_ubo_analysis_state
*state
= &link
->const_state
.ubo_state
;
2771 if (link
->push_consts
.count
> 0) {
2772 unsigned num_units
= link
->push_consts
.count
;
2773 unsigned offset
= link
->push_consts
.lo
;
2774 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2775 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2776 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2777 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2778 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2779 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2782 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2783 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2786 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2787 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2788 uint32_t offset
= state
->range
[i
].start
;
2790 /* and even if the start of the const buffer is before
2791 * first_immediate, the end may not be:
2793 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2798 /* things should be aligned to vec4: */
2799 debug_assert((state
->range
[i
].offset
% 16) == 0);
2800 debug_assert((size
% 16) == 0);
2801 debug_assert((offset
% 16) == 0);
2803 /* Dig out the descriptor from the descriptor state and read the VA from
2806 assert(state
->range
[i
].ubo
.bindless
);
2807 uint32_t *base
= state
->range
[i
].ubo
.bindless_base
== MAX_SETS
?
2808 descriptors_state
->dynamic_descriptors
:
2809 descriptors_state
->sets
[state
->range
[i
].ubo
.bindless_base
]->mapped_ptr
;
2810 unsigned block
= state
->range
[i
].ubo
.block
;
2811 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2812 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2815 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2816 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2817 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2818 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2819 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2820 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2821 tu_cs_emit_qw(cs
, va
+ offset
);
2825 static struct tu_draw_state
2826 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2827 const struct tu_pipeline
*pipeline
,
2828 struct tu_descriptor_state
*descriptors_state
,
2829 gl_shader_stage type
)
2832 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2834 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2836 return tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2839 static struct tu_draw_state
2840 tu6_emit_vertex_buffers(struct tu_cmd_buffer
*cmd
,
2841 const struct tu_pipeline
*pipeline
)
2844 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 4 * MAX_VBS
, &cs
);
2847 for_each_bit(binding
, pipeline
->vi
.bindings_used
) {
2848 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2849 const VkDeviceSize offset
= buf
->bo_offset
+
2850 cmd
->state
.vb
.offsets
[binding
];
2852 tu_cs_emit_regs(&cs
,
2853 A6XX_VFD_FETCH_BASE(binding
, .bo
= buf
->bo
, .bo_offset
= offset
),
2854 A6XX_VFD_FETCH_SIZE(binding
, buf
->size
- offset
));
2858 cmd
->vertex_bindings_set
= pipeline
->vi
.bindings_used
;
2860 return tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2864 get_tess_param_bo_size(const struct tu_pipeline
*pipeline
,
2865 uint32_t draw_count
)
2867 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
2868 * Still not sure what to do here, so just allocate a reasonably large
2869 * BO and hope for the best for now. */
2873 /* the tess param BO is pipeline->tess.param_stride bytes per patch,
2874 * which includes both the per-vertex outputs and per-patch outputs
2875 * build_primitive_map in ir3 calculates this stride
2877 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
2878 uint32_t num_patches
= draw_count
/ verts_per_patch
;
2879 return num_patches
* pipeline
->tess
.param_stride
;
2883 get_tess_factor_bo_size(const struct tu_pipeline
*pipeline
,
2884 uint32_t draw_count
)
2886 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
2887 * Still not sure what to do here, so just allocate a reasonably large
2888 * BO and hope for the best for now. */
2892 /* Each distinct patch gets its own tess factor output. */
2893 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
2894 uint32_t num_patches
= draw_count
/ verts_per_patch
;
2895 uint32_t factor_stride
;
2896 switch (pipeline
->tess
.patch_type
) {
2897 case IR3_TESS_ISOLINES
:
2900 case IR3_TESS_TRIANGLES
:
2903 case IR3_TESS_QUADS
:
2907 unreachable("bad tessmode");
2909 return factor_stride
* num_patches
;
2913 tu6_emit_tess_consts(struct tu_cmd_buffer
*cmd
,
2914 uint32_t draw_count
,
2915 const struct tu_pipeline
*pipeline
,
2916 struct tu_draw_state
*state
,
2917 uint64_t *factor_iova
)
2920 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 16, &cs
);
2921 if (result
!= VK_SUCCESS
)
2924 uint64_t tess_factor_size
= get_tess_factor_bo_size(pipeline
, draw_count
);
2925 uint64_t tess_param_size
= get_tess_param_bo_size(pipeline
, draw_count
);
2926 uint64_t tess_bo_size
= tess_factor_size
+ tess_param_size
;
2927 if (tess_bo_size
> 0) {
2928 struct tu_bo
*tess_bo
;
2929 result
= tu_get_scratch_bo(cmd
->device
, tess_bo_size
, &tess_bo
);
2930 if (result
!= VK_SUCCESS
)
2933 tu_bo_list_add(&cmd
->bo_list
, tess_bo
,
2934 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2935 uint64_t tess_factor_iova
= tess_bo
->iova
;
2936 uint64_t tess_param_iova
= tess_factor_iova
+ tess_factor_size
;
2938 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2939 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.hs_bo_regid
) |
2940 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2941 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2942 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_HS_SHADER
) |
2943 CP_LOAD_STATE6_0_NUM_UNIT(1));
2944 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2945 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2946 tu_cs_emit_qw(&cs
, tess_param_iova
);
2947 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2949 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2950 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.ds_bo_regid
) |
2951 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2952 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2953 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_DS_SHADER
) |
2954 CP_LOAD_STATE6_0_NUM_UNIT(1));
2955 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2956 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2957 tu_cs_emit_qw(&cs
, tess_param_iova
);
2958 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2960 *factor_iova
= tess_factor_iova
;
2962 *state
= tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2967 tu6_draw_common(struct tu_cmd_buffer
*cmd
,
2970 /* note: draw_count is 0 for indirect */
2971 uint32_t draw_count
)
2973 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
2976 struct tu_descriptor_state
*descriptors_state
=
2977 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
2979 tu_emit_cache_flush_renderpass(cmd
, cs
);
2983 tu_cs_emit_regs(cs
, A6XX_PC_PRIMITIVE_CNTL_0(
2984 .primitive_restart
=
2985 pipeline
->ia
.primitive_restart
&& indexed
,
2986 .tess_upper_left_domain_origin
=
2987 pipeline
->tess
.upper_left_domain_origin
));
2989 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
2990 cmd
->state
.shader_const
[MESA_SHADER_VERTEX
] =
2991 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
);
2992 cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
] =
2993 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_CTRL
);
2994 cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
] =
2995 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_EVAL
);
2996 cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
] =
2997 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_GEOMETRY
);
2998 cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
] =
2999 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
);
3002 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3003 cmd
->state
.vertex_buffers
= tu6_emit_vertex_buffers(cmd
, pipeline
);
3006 pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
3007 struct tu_draw_state tess_consts
= {};
3009 uint64_t tess_factor_iova
= 0;
3011 cmd
->has_tess
= true;
3012 result
= tu6_emit_tess_consts(cmd
, draw_count
, pipeline
, &tess_consts
, &tess_factor_iova
);
3013 if (result
!= VK_SUCCESS
)
3016 /* this sequence matches what the blob does before every tess draw
3017 * PC_TESSFACTOR_ADDR_LO is a non-context register and needs a wfi
3018 * before writing to it
3022 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_TESSFACTOR_ADDR_LO
, 2);
3023 tu_cs_emit_qw(cs
, tess_factor_iova
);
3025 tu_cs_emit_pkt7(cs
, CP_SET_SUBDRAW_SIZE
, 1);
3026 tu_cs_emit(cs
, draw_count
);
3029 /* for the first draw in a renderpass, re-emit all the draw states
3031 * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
3032 * used, then draw states must be re-emitted. note however this only happens
3033 * in the sysmem path, so this can be skipped this for the gmem path (TODO)
3035 * the two input attachment states are excluded because secondary command
3036 * buffer doesn't have a state ib to restore it, and not re-emitting them
3037 * is OK since CmdClearAttachments won't disable/overwrite them
3039 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DRAW_STATE
) {
3040 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (TU_DRAW_STATE_COUNT
- 2));
3042 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state
);
3043 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state
);
3044 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
3045 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state
);
3046 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state
);
3047 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast_state
);
3048 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS
, pipeline
->ds_state
);
3049 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend_state
);
3050 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_VERTEX
]);
3051 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
]);
3052 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
]);
3053 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
]);
3054 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
]);
3055 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets
);
3056 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, pipeline
->load_state
);
3057 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers
);
3058 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_PARAMS
, cmd
->state
.vs_params
);
3060 for (uint32_t i
= 0; i
< ARRAY_SIZE(cmd
->state
.dynamic_state
); i
++) {
3061 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
,
3062 ((pipeline
->dynamic_state_mask
& BIT(i
)) ?
3063 cmd
->state
.dynamic_state
[i
] :
3064 pipeline
->dynamic_state
[i
]));
3068 /* emit draw states that were just updated
3069 * note we eventually don't want to have to emit anything here
3071 uint32_t draw_state_count
=
3073 ((cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) ? 5 : 0) +
3074 ((cmd
->state
.dirty
& TU_CMD_DIRTY_DESC_SETS_LOAD
) ? 1 : 0) +
3075 ((cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) ? 1 : 0) +
3078 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_count
);
3080 /* We may need to re-emit tess consts if the current draw call is
3081 * sufficiently larger than the last draw call. */
3083 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
3084 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
3085 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_VERTEX
]);
3086 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
]);
3087 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
]);
3088 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
]);
3089 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
]);
3091 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESC_SETS_LOAD
)
3092 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, pipeline
->load_state
);
3093 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3094 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers
);
3095 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_PARAMS
, cmd
->state
.vs_params
);
3098 tu_cs_sanity_check(cs
);
3100 /* There are too many graphics dirty bits to list here, so just list the
3101 * bits to preserve instead. The only things not emitted here are
3102 * compute-related state.
3104 cmd
->state
.dirty
&= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
3109 tu_draw_initiator(struct tu_cmd_buffer
*cmd
, enum pc_di_src_sel src_sel
)
3111 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3112 uint32_t initiator
=
3113 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(pipeline
->ia
.primtype
) |
3114 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(src_sel
) |
3115 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(cmd
->state
.index_size
) |
3116 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
);
3118 if (pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
)
3119 initiator
|= CP_DRAW_INDX_OFFSET_0_GS_ENABLE
;
3121 switch (pipeline
->tess
.patch_type
) {
3122 case IR3_TESS_TRIANGLES
:
3123 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_TRIANGLES
) |
3124 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3126 case IR3_TESS_ISOLINES
:
3127 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_ISOLINES
) |
3128 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3131 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS
);
3133 case IR3_TESS_QUADS
:
3134 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS
) |
3135 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3143 vs_params_offset(struct tu_cmd_buffer
*cmd
)
3145 const struct tu_program_descriptor_linkage
*link
=
3146 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
3147 const struct ir3_const_state
*const_state
= &link
->const_state
;
3149 if (const_state
->offsets
.driver_param
>= link
->constlen
)
3152 /* this layout is required by CP_DRAW_INDIRECT_MULTI */
3153 STATIC_ASSERT(IR3_DP_DRAWID
== 0);
3154 STATIC_ASSERT(IR3_DP_VTXID_BASE
== 1);
3155 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
3157 /* 0 means disabled for CP_DRAW_INDIRECT_MULTI */
3158 assert(const_state
->offsets
.driver_param
!= 0);
3160 return const_state
->offsets
.driver_param
;
3163 static struct tu_draw_state
3164 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
3165 uint32_t vertex_offset
,
3166 uint32_t first_instance
)
3168 uint32_t offset
= vs_params_offset(cmd
);
3171 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 3 + (offset
? 8 : 0), &cs
);
3172 if (result
!= VK_SUCCESS
) {
3173 cmd
->record_result
= result
;
3174 return (struct tu_draw_state
) {};
3177 /* TODO: don't make a new draw state when it doesn't change */
3179 tu_cs_emit_regs(&cs
,
3180 A6XX_VFD_INDEX_OFFSET(vertex_offset
),
3181 A6XX_VFD_INSTANCE_START_OFFSET(first_instance
));
3184 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
3185 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3186 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3187 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3188 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
3189 CP_LOAD_STATE6_0_NUM_UNIT(1));
3194 tu_cs_emit(&cs
, vertex_offset
);
3195 tu_cs_emit(&cs
, first_instance
);
3199 struct tu_cs_entry entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
3200 return (struct tu_draw_state
) {entry
.bo
->iova
+ entry
.offset
, entry
.size
/ 4};
3204 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3205 uint32_t vertexCount
,
3206 uint32_t instanceCount
,
3207 uint32_t firstVertex
,
3208 uint32_t firstInstance
)
3210 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3211 struct tu_cs
*cs
= &cmd
->draw_cs
;
3213 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, firstVertex
, firstInstance
);
3215 tu6_draw_common(cmd
, cs
, false, vertexCount
);
3217 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3218 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3219 tu_cs_emit(cs
, instanceCount
);
3220 tu_cs_emit(cs
, vertexCount
);
3224 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3225 uint32_t indexCount
,
3226 uint32_t instanceCount
,
3227 uint32_t firstIndex
,
3228 int32_t vertexOffset
,
3229 uint32_t firstInstance
)
3231 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3232 struct tu_cs
*cs
= &cmd
->draw_cs
;
3234 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, vertexOffset
, firstInstance
);
3236 tu6_draw_common(cmd
, cs
, true, indexCount
);
3238 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3239 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3240 tu_cs_emit(cs
, instanceCount
);
3241 tu_cs_emit(cs
, indexCount
);
3242 tu_cs_emit(cs
, firstIndex
);
3243 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3244 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3247 /* Various firmware bugs/inconsistencies mean that some indirect draw opcodes
3248 * do not wait for WFI's to complete before executing. Add a WAIT_FOR_ME if
3249 * pending for these opcodes. This may result in a few extra WAIT_FOR_ME's
3250 * with these opcodes, but the alternative would add unnecessary WAIT_FOR_ME's
3251 * before draw opcodes that don't need it.
3254 draw_wfm(struct tu_cmd_buffer
*cmd
)
3256 cmd
->state
.renderpass_cache
.flush_bits
|=
3257 cmd
->state
.renderpass_cache
.pending_flush_bits
& TU_CMD_FLAG_WAIT_FOR_ME
;
3258 cmd
->state
.renderpass_cache
.pending_flush_bits
&= ~TU_CMD_FLAG_WAIT_FOR_ME
;
3262 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3264 VkDeviceSize offset
,
3268 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3269 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3270 struct tu_cs
*cs
= &cmd
->draw_cs
;
3272 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3274 /* The latest known a630_sqe.fw fails to wait for WFI before reading the
3275 * indirect buffer when using CP_DRAW_INDIRECT_MULTI, so we have to fall
3276 * back to CP_WAIT_FOR_ME except for a650 which has a fixed firmware.
3278 * TODO: There may be newer a630_sqe.fw released in the future which fixes
3279 * this, if so we should detect it and avoid this workaround.
3281 if (cmd
->device
->physical_device
->gpu_id
!= 650)
3284 tu6_draw_common(cmd
, cs
, false, 0);
3286 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 6);
3287 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3288 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_NORMAL
) |
3289 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3290 tu_cs_emit(cs
, drawCount
);
3291 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3292 tu_cs_emit(cs
, stride
);
3294 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3298 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3300 VkDeviceSize offset
,
3304 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3305 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3306 struct tu_cs
*cs
= &cmd
->draw_cs
;
3308 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3310 if (cmd
->device
->physical_device
->gpu_id
!= 650)
3313 tu6_draw_common(cmd
, cs
, true, 0);
3315 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 9);
3316 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3317 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDEXED
) |
3318 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3319 tu_cs_emit(cs
, drawCount
);
3320 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3321 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3322 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3323 tu_cs_emit(cs
, stride
);
3325 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3329 tu_CmdDrawIndirectCount(VkCommandBuffer commandBuffer
,
3331 VkDeviceSize offset
,
3332 VkBuffer countBuffer
,
3333 VkDeviceSize countBufferOffset
,
3337 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3338 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3339 TU_FROM_HANDLE(tu_buffer
, count_buf
, countBuffer
);
3340 struct tu_cs
*cs
= &cmd
->draw_cs
;
3342 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3344 /* It turns out that the firmware we have for a650 only partially fixed the
3345 * problem with CP_DRAW_INDIRECT_MULTI not waiting for WFI's to complete
3346 * before reading indirect parameters. It waits for WFI's before reading
3347 * the draw parameters, but after reading the indirect count :(.
3351 tu6_draw_common(cmd
, cs
, false, 0);
3353 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 8);
3354 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3355 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT
) |
3356 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3357 tu_cs_emit(cs
, drawCount
);
3358 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3359 tu_cs_emit_qw(cs
, count_buf
->bo
->iova
+ count_buf
->bo_offset
+ countBufferOffset
);
3360 tu_cs_emit(cs
, stride
);
3362 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3363 tu_bo_list_add(&cmd
->bo_list
, count_buf
->bo
, MSM_SUBMIT_BO_READ
);
3367 tu_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer
,
3369 VkDeviceSize offset
,
3370 VkBuffer countBuffer
,
3371 VkDeviceSize countBufferOffset
,
3375 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3376 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3377 TU_FROM_HANDLE(tu_buffer
, count_buf
, countBuffer
);
3378 struct tu_cs
*cs
= &cmd
->draw_cs
;
3380 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3384 tu6_draw_common(cmd
, cs
, true, 0);
3386 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 11);
3387 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3388 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT_INDEXED
) |
3389 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3390 tu_cs_emit(cs
, drawCount
);
3391 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3392 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3393 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3394 tu_cs_emit_qw(cs
, count_buf
->bo
->iova
+ count_buf
->bo_offset
+ countBufferOffset
);
3395 tu_cs_emit(cs
, stride
);
3397 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3398 tu_bo_list_add(&cmd
->bo_list
, count_buf
->bo
, MSM_SUBMIT_BO_READ
);
3401 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3402 uint32_t instanceCount
,
3403 uint32_t firstInstance
,
3404 VkBuffer _counterBuffer
,
3405 VkDeviceSize counterBufferOffset
,
3406 uint32_t counterOffset
,
3407 uint32_t vertexStride
)
3409 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3410 TU_FROM_HANDLE(tu_buffer
, buf
, _counterBuffer
);
3411 struct tu_cs
*cs
= &cmd
->draw_cs
;
3413 /* All known firmware versions do not wait for WFI's with CP_DRAW_AUTO.
3414 * Plus, for the common case where the counter buffer is written by
3415 * vkCmdEndTransformFeedback, we need to wait for the CP_WAIT_MEM_WRITES to
3416 * complete which means we need a WAIT_FOR_ME anyway.
3420 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, 0, firstInstance
);
3422 tu6_draw_common(cmd
, cs
, false, 0);
3424 tu_cs_emit_pkt7(cs
, CP_DRAW_AUTO
, 6);
3425 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_XFB
));
3426 tu_cs_emit(cs
, instanceCount
);
3427 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ counterBufferOffset
);
3428 tu_cs_emit(cs
, counterOffset
);
3429 tu_cs_emit(cs
, vertexStride
);
3431 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3434 struct tu_dispatch_info
3437 * Determine the layout of the grid (in block units) to be used.
3442 * A starting offset for the grid. If unaligned is set, the offset
3443 * must still be aligned.
3445 uint32_t offsets
[3];
3447 * Whether it's an unaligned compute dispatch.
3452 * Indirect compute parameters resource.
3454 struct tu_buffer
*indirect
;
3455 uint64_t indirect_offset
;
3459 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3460 const struct tu_dispatch_info
*info
)
3462 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3463 const struct tu_program_descriptor_linkage
*link
=
3464 &pipeline
->program
.link
[type
];
3465 const struct ir3_const_state
*const_state
= &link
->const_state
;
3466 uint32_t offset
= const_state
->offsets
.driver_param
;
3468 if (link
->constlen
<= offset
)
3471 if (!info
->indirect
) {
3472 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3473 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3474 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3475 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3476 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3477 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3478 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3481 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3482 (link
->constlen
- offset
) * 4);
3483 /* push constants */
3484 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3485 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3486 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3487 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3488 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3489 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3493 for (i
= 0; i
< num_consts
; i
++)
3494 tu_cs_emit(cs
, driver_params
[i
]);
3496 tu_finishme("Indirect driver params");
3501 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3502 const struct tu_dispatch_info
*info
)
3504 struct tu_cs
*cs
= &cmd
->cs
;
3505 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3506 struct tu_descriptor_state
*descriptors_state
=
3507 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3509 /* TODO: We could probably flush less if we add a compute_flush_bits
3512 tu_emit_cache_flush(cmd
, cs
);
3514 /* note: no reason to have this in a separate IB */
3515 tu_cs_emit_state_ib(cs
,
3516 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
));
3518 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3520 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
)
3521 tu_cs_emit_state_ib(cs
, pipeline
->load_state
);
3523 cmd
->state
.dirty
&= ~TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
3525 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3526 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3528 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3529 const uint32_t *num_groups
= info
->blocks
;
3531 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3532 .localsizex
= local_size
[0] - 1,
3533 .localsizey
= local_size
[1] - 1,
3534 .localsizez
= local_size
[2] - 1),
3535 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3536 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3537 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3538 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3539 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3540 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3543 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3544 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3545 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3547 if (info
->indirect
) {
3548 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3550 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3551 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3553 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3554 tu_cs_emit(cs
, 0x00000000);
3555 tu_cs_emit_qw(cs
, iova
);
3557 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3558 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3559 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3561 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3562 tu_cs_emit(cs
, 0x00000000);
3563 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3564 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3565 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3572 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3580 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3581 struct tu_dispatch_info info
= {};
3587 info
.offsets
[0] = base_x
;
3588 info
.offsets
[1] = base_y
;
3589 info
.offsets
[2] = base_z
;
3590 tu_dispatch(cmd_buffer
, &info
);
3594 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3599 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3603 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3605 VkDeviceSize offset
)
3607 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3608 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3609 struct tu_dispatch_info info
= {};
3611 info
.indirect
= buffer
;
3612 info
.indirect_offset
= offset
;
3614 tu_dispatch(cmd_buffer
, &info
);
3618 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3620 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3622 tu_cs_end(&cmd_buffer
->draw_cs
);
3623 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3625 if (use_sysmem_rendering(cmd_buffer
))
3626 tu_cmd_render_sysmem(cmd_buffer
);
3628 tu_cmd_render_tiles(cmd_buffer
);
3630 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3632 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3633 tu_cs_begin(&cmd_buffer
->draw_cs
);
3634 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3635 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3637 cmd_buffer
->state
.cache
.pending_flush_bits
|=
3638 cmd_buffer
->state
.renderpass_cache
.pending_flush_bits
;
3639 tu_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
, true);
3641 cmd_buffer
->state
.pass
= NULL
;
3642 cmd_buffer
->state
.subpass
= NULL
;
3643 cmd_buffer
->state
.framebuffer
= NULL
;
3647 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3648 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3650 tu_CmdEndRenderPass(commandBuffer
);
3653 struct tu_barrier_info
3655 uint32_t eventCount
;
3656 const VkEvent
*pEvents
;
3657 VkPipelineStageFlags srcStageMask
;
3661 tu_barrier(struct tu_cmd_buffer
*cmd
,
3662 uint32_t memoryBarrierCount
,
3663 const VkMemoryBarrier
*pMemoryBarriers
,
3664 uint32_t bufferMemoryBarrierCount
,
3665 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3666 uint32_t imageMemoryBarrierCount
,
3667 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3668 const struct tu_barrier_info
*info
)
3670 struct tu_cs
*cs
= cmd
->state
.pass
? &cmd
->draw_cs
: &cmd
->cs
;
3671 VkAccessFlags srcAccessMask
= 0;
3672 VkAccessFlags dstAccessMask
= 0;
3674 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3675 srcAccessMask
|= pMemoryBarriers
[i
].srcAccessMask
;
3676 dstAccessMask
|= pMemoryBarriers
[i
].dstAccessMask
;
3679 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3680 srcAccessMask
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
3681 dstAccessMask
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
3684 enum tu_cmd_access_mask src_flags
= 0;
3685 enum tu_cmd_access_mask dst_flags
= 0;
3687 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3688 TU_FROM_HANDLE(tu_image
, image
, pImageMemoryBarriers
[i
].image
);
3689 VkImageLayout old_layout
= pImageMemoryBarriers
[i
].oldLayout
;
3690 /* For non-linear images, PREINITIALIZED is the same as UNDEFINED */
3691 if (old_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
3692 (image
->tiling
!= VK_IMAGE_TILING_LINEAR
&&
3693 old_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
)) {
3694 /* The underlying memory for this image may have been used earlier
3695 * within the same queue submission for a different image, which
3696 * means that there may be old, stale cache entries which are in the
3697 * "wrong" location, which could cause problems later after writing
3698 * to the image. We don't want these entries being flushed later and
3699 * overwriting the actual image, so we need to flush the CCU.
3701 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
3703 srcAccessMask
|= pImageMemoryBarriers
[i
].srcAccessMask
;
3704 dstAccessMask
|= pImageMemoryBarriers
[i
].dstAccessMask
;
3707 /* Inside a renderpass, we don't know yet whether we'll be using sysmem
3708 * so we have to use the sysmem flushes.
3710 bool gmem
= cmd
->state
.ccu_state
== TU_CMD_CCU_GMEM
&&
3712 src_flags
|= vk2tu_access(srcAccessMask
, gmem
);
3713 dst_flags
|= vk2tu_access(dstAccessMask
, gmem
);
3715 struct tu_cache_state
*cache
=
3716 cmd
->state
.pass
? &cmd
->state
.renderpass_cache
: &cmd
->state
.cache
;
3717 tu_flush_for_access(cache
, src_flags
, dst_flags
);
3719 for (uint32_t i
= 0; i
< info
->eventCount
; i
++) {
3720 TU_FROM_HANDLE(tu_event
, event
, info
->pEvents
[i
]);
3722 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3724 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3725 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3726 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3727 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3728 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3729 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3730 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3735 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3736 VkPipelineStageFlags srcStageMask
,
3737 VkPipelineStageFlags dstStageMask
,
3738 VkDependencyFlags dependencyFlags
,
3739 uint32_t memoryBarrierCount
,
3740 const VkMemoryBarrier
*pMemoryBarriers
,
3741 uint32_t bufferMemoryBarrierCount
,
3742 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3743 uint32_t imageMemoryBarrierCount
,
3744 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3746 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3747 struct tu_barrier_info info
;
3749 info
.eventCount
= 0;
3750 info
.pEvents
= NULL
;
3751 info
.srcStageMask
= srcStageMask
;
3753 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3754 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3755 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3759 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
,
3760 VkPipelineStageFlags stageMask
, unsigned value
)
3762 struct tu_cs
*cs
= &cmd
->cs
;
3764 /* vkCmdSetEvent/vkCmdResetEvent cannot be called inside a render pass */
3765 assert(!cmd
->state
.pass
);
3767 tu_emit_cache_flush(cmd
, cs
);
3769 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3771 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
3772 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
3774 VkPipelineStageFlags top_of_pipe_flags
=
3775 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
3776 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
;
3778 if (!(stageMask
& ~top_of_pipe_flags
)) {
3779 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3780 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3781 tu_cs_emit(cs
, value
);
3783 /* Use a RB_DONE_TS event to wait for everything to complete. */
3784 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 4);
3785 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS
));
3786 tu_cs_emit_qw(cs
, event
->bo
.iova
);
3787 tu_cs_emit(cs
, value
);
3792 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3794 VkPipelineStageFlags stageMask
)
3796 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3797 TU_FROM_HANDLE(tu_event
, event
, _event
);
3799 write_event(cmd
, event
, stageMask
, 1);
3803 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3805 VkPipelineStageFlags stageMask
)
3807 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3808 TU_FROM_HANDLE(tu_event
, event
, _event
);
3810 write_event(cmd
, event
, stageMask
, 0);
3814 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3815 uint32_t eventCount
,
3816 const VkEvent
*pEvents
,
3817 VkPipelineStageFlags srcStageMask
,
3818 VkPipelineStageFlags dstStageMask
,
3819 uint32_t memoryBarrierCount
,
3820 const VkMemoryBarrier
*pMemoryBarriers
,
3821 uint32_t bufferMemoryBarrierCount
,
3822 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3823 uint32_t imageMemoryBarrierCount
,
3824 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3826 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3827 struct tu_barrier_info info
;
3829 info
.eventCount
= eventCount
;
3830 info
.pEvents
= pEvents
;
3831 info
.srcStageMask
= 0;
3833 tu_barrier(cmd
, memoryBarrierCount
, pMemoryBarriers
,
3834 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3835 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3839 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)