2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
33 #include "vk_format.h"
37 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
40 tu_bo_list_init(struct tu_bo_list
*list
)
42 list
->count
= list
->capacity
= 0;
43 list
->bo_infos
= NULL
;
47 tu_bo_list_destroy(struct tu_bo_list
*list
)
53 tu_bo_list_reset(struct tu_bo_list
*list
)
59 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
62 tu_bo_list_add_info(struct tu_bo_list
*list
,
63 const struct drm_msm_gem_submit_bo
*bo_info
)
65 assert(bo_info
->handle
!= 0);
67 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
68 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
69 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
70 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
75 /* grow list->bo_infos if needed */
76 if (list
->count
== list
->capacity
) {
77 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
78 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
79 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
81 return TU_BO_LIST_FAILED
;
82 list
->bo_infos
= new_bo_infos
;
83 list
->capacity
= new_capacity
;
86 list
->bo_infos
[list
->count
] = *bo_info
;
91 tu_bo_list_add(struct tu_bo_list
*list
,
92 const struct tu_bo
*bo
,
95 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
97 .handle
= bo
->gem_handle
,
103 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
105 for (uint32_t i
= 0; i
< other
->count
; i
++) {
106 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
107 return VK_ERROR_OUT_OF_HOST_MEMORY
;
114 tu_tiling_config_update_tile_layout(struct tu_tiling_config
*tiling
,
115 const struct tu_device
*dev
,
116 const struct tu_render_pass
*pass
)
118 const uint32_t tile_align_w
= pass
->tile_align_w
;
119 const uint32_t max_tile_width
= 1024;
121 /* note: don't offset the tiling config by render_area.offset,
122 * because binning pass can't deal with it
123 * this means we might end up with more tiles than necessary,
124 * but load/store/etc are still scissored to the render_area
126 tiling
->tile0
.offset
= (VkOffset2D
) {};
128 const uint32_t ra_width
=
129 tiling
->render_area
.extent
.width
+
130 (tiling
->render_area
.offset
.x
- tiling
->tile0
.offset
.x
);
131 const uint32_t ra_height
=
132 tiling
->render_area
.extent
.height
+
133 (tiling
->render_area
.offset
.y
- tiling
->tile0
.offset
.y
);
135 /* start from 1 tile */
136 tiling
->tile_count
= (VkExtent2D
) {
140 tiling
->tile0
.extent
= (VkExtent2D
) {
141 .width
= util_align_npot(ra_width
, tile_align_w
),
142 .height
= align(ra_height
, TILE_ALIGN_H
),
145 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
)) {
146 /* start with 2x2 tiles */
147 tiling
->tile_count
.width
= 2;
148 tiling
->tile_count
.height
= 2;
149 tiling
->tile0
.extent
.width
= util_align_npot(DIV_ROUND_UP(ra_width
, 2), tile_align_w
);
150 tiling
->tile0
.extent
.height
= align(DIV_ROUND_UP(ra_height
, 2), TILE_ALIGN_H
);
153 /* do not exceed max tile width */
154 while (tiling
->tile0
.extent
.width
> max_tile_width
) {
155 tiling
->tile_count
.width
++;
156 tiling
->tile0
.extent
.width
=
157 util_align_npot(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
160 /* will force to sysmem, don't bother trying to have a valid tile config
161 * TODO: just skip all GMEM stuff when sysmem is forced?
163 if (!pass
->gmem_pixels
)
166 /* do not exceed gmem size */
167 while (tiling
->tile0
.extent
.width
* tiling
->tile0
.extent
.height
> pass
->gmem_pixels
) {
168 if (tiling
->tile0
.extent
.width
> MAX2(tile_align_w
, tiling
->tile0
.extent
.height
)) {
169 tiling
->tile_count
.width
++;
170 tiling
->tile0
.extent
.width
=
171 util_align_npot(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
173 /* if this assert fails then layout is impossible.. */
174 assert(tiling
->tile0
.extent
.height
> TILE_ALIGN_H
);
175 tiling
->tile_count
.height
++;
176 tiling
->tile0
.extent
.height
=
177 align(DIV_ROUND_UP(ra_height
, tiling
->tile_count
.height
), TILE_ALIGN_H
);
183 tu_tiling_config_update_pipe_layout(struct tu_tiling_config
*tiling
,
184 const struct tu_device
*dev
)
186 const uint32_t max_pipe_count
= 32; /* A6xx */
188 /* start from 1 tile per pipe */
189 tiling
->pipe0
= (VkExtent2D
) {
193 tiling
->pipe_count
= tiling
->tile_count
;
195 while (tiling
->pipe_count
.width
* tiling
->pipe_count
.height
> max_pipe_count
) {
196 if (tiling
->pipe0
.width
< tiling
->pipe0
.height
) {
197 tiling
->pipe0
.width
+= 1;
198 tiling
->pipe_count
.width
=
199 DIV_ROUND_UP(tiling
->tile_count
.width
, tiling
->pipe0
.width
);
201 tiling
->pipe0
.height
+= 1;
202 tiling
->pipe_count
.height
=
203 DIV_ROUND_UP(tiling
->tile_count
.height
, tiling
->pipe0
.height
);
209 tu_tiling_config_update_pipes(struct tu_tiling_config
*tiling
,
210 const struct tu_device
*dev
)
212 const uint32_t max_pipe_count
= 32; /* A6xx */
213 const uint32_t used_pipe_count
=
214 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
215 const VkExtent2D last_pipe
= {
216 .width
= (tiling
->tile_count
.width
- 1) % tiling
->pipe0
.width
+ 1,
217 .height
= (tiling
->tile_count
.height
- 1) % tiling
->pipe0
.height
+ 1,
220 assert(used_pipe_count
<= max_pipe_count
);
221 assert(max_pipe_count
<= ARRAY_SIZE(tiling
->pipe_config
));
223 for (uint32_t y
= 0; y
< tiling
->pipe_count
.height
; y
++) {
224 for (uint32_t x
= 0; x
< tiling
->pipe_count
.width
; x
++) {
225 const uint32_t pipe_x
= tiling
->pipe0
.width
* x
;
226 const uint32_t pipe_y
= tiling
->pipe0
.height
* y
;
227 const uint32_t pipe_w
= (x
== tiling
->pipe_count
.width
- 1)
229 : tiling
->pipe0
.width
;
230 const uint32_t pipe_h
= (y
== tiling
->pipe_count
.height
- 1)
232 : tiling
->pipe0
.height
;
233 const uint32_t n
= tiling
->pipe_count
.width
* y
+ x
;
235 tiling
->pipe_config
[n
] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x
) |
236 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y
) |
237 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w
) |
238 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h
);
239 tiling
->pipe_sizes
[n
] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w
* pipe_h
);
243 memset(tiling
->pipe_config
+ used_pipe_count
, 0,
244 sizeof(uint32_t) * (max_pipe_count
- used_pipe_count
));
248 tu_tiling_config_get_tile(const struct tu_tiling_config
*tiling
,
249 const struct tu_device
*dev
,
252 struct tu_tile
*tile
)
254 /* find the pipe and the slot for tile (tx, ty) */
255 const uint32_t px
= tx
/ tiling
->pipe0
.width
;
256 const uint32_t py
= ty
/ tiling
->pipe0
.height
;
257 const uint32_t sx
= tx
- tiling
->pipe0
.width
* px
;
258 const uint32_t sy
= ty
- tiling
->pipe0
.height
* py
;
259 /* last pipe has different width */
260 const uint32_t pipe_width
=
261 MIN2(tiling
->pipe0
.width
,
262 tiling
->tile_count
.width
- px
* tiling
->pipe0
.width
);
264 assert(tx
< tiling
->tile_count
.width
&& ty
< tiling
->tile_count
.height
);
265 assert(px
< tiling
->pipe_count
.width
&& py
< tiling
->pipe_count
.height
);
266 assert(sx
< tiling
->pipe0
.width
&& sy
< tiling
->pipe0
.height
);
268 /* convert to 1D indices */
269 tile
->pipe
= tiling
->pipe_count
.width
* py
+ px
;
270 tile
->slot
= pipe_width
* sy
+ sx
;
272 /* get the blit area for the tile */
273 tile
->begin
= (VkOffset2D
) {
274 .x
= tiling
->tile0
.offset
.x
+ tiling
->tile0
.extent
.width
* tx
,
275 .y
= tiling
->tile0
.offset
.y
+ tiling
->tile0
.extent
.height
* ty
,
278 (tx
== tiling
->tile_count
.width
- 1)
279 ? tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
280 : tile
->begin
.x
+ tiling
->tile0
.extent
.width
;
282 (ty
== tiling
->tile_count
.height
- 1)
283 ? tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
284 : tile
->begin
.y
+ tiling
->tile0
.extent
.height
;
287 enum a3xx_msaa_samples
288 tu_msaa_samples(uint32_t samples
)
300 assert(!"invalid sample count");
305 static enum a4xx_index_size
306 tu6_index_size(VkIndexType type
)
309 case VK_INDEX_TYPE_UINT16
:
310 return INDEX4_SIZE_16_BIT
;
311 case VK_INDEX_TYPE_UINT32
:
312 return INDEX4_SIZE_32_BIT
;
314 unreachable("invalid VkIndexType");
315 return INDEX4_SIZE_8_BIT
;
320 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
322 enum vgt_event_type event
)
324 bool need_seqno
= false;
329 case PC_CCU_FLUSH_DEPTH_TS
:
330 case PC_CCU_FLUSH_COLOR_TS
:
331 case PC_CCU_RESOLVE_TS
:
338 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
339 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
341 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
347 tu6_emit_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
349 tu6_emit_event_write(cmd
, cs
, 0x31);
353 tu6_emit_lrz_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
355 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
359 tu6_emit_wfi(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
361 if (cmd
->wait_for_idle
) {
363 cmd
->wait_for_idle
= false;
368 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
369 const struct tu_subpass
*subpass
,
372 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
374 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
375 if (a
== VK_ATTACHMENT_UNUSED
) {
377 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
378 A6XX_RB_DEPTH_BUFFER_PITCH(0),
379 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
380 A6XX_RB_DEPTH_BUFFER_BASE(0),
381 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
384 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
387 A6XX_GRAS_LRZ_BUFFER_BASE(0),
388 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
389 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
391 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
396 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
397 const struct tu_render_pass_attachment
*attachment
=
398 &cmd
->state
.pass
->attachments
[a
];
399 enum a6xx_depth_format fmt
= tu6_pipe2depth(attachment
->format
);
401 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
402 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
).value
);
403 tu_cs_image_ref(cs
, iview
, 0);
404 tu_cs_emit(cs
, attachment
->gmem_offset
);
407 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
409 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
410 tu_cs_image_flag_ref(cs
, iview
, 0);
413 A6XX_GRAS_LRZ_BUFFER_BASE(0),
414 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
415 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
417 if (attachment
->format
== VK_FORMAT_S8_UINT
) {
418 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 6);
419 tu_cs_emit(cs
, A6XX_RB_STENCIL_INFO(.separate_stencil
= true).value
);
420 tu_cs_image_ref(cs
, iview
, 0);
421 tu_cs_emit(cs
, attachment
->gmem_offset
);
424 A6XX_RB_STENCIL_INFO(0));
429 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
430 const struct tu_subpass
*subpass
,
433 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
435 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
436 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
437 if (a
== VK_ATTACHMENT_UNUSED
)
440 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
442 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
443 tu_cs_emit(cs
, iview
->RB_MRT_BUF_INFO
);
444 tu_cs_image_ref(cs
, iview
, 0);
445 tu_cs_emit(cs
, cmd
->state
.pass
->attachments
[a
].gmem_offset
);
448 A6XX_SP_FS_MRT_REG(i
, .dword
= iview
->SP_FS_MRT_REG
));
450 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i
), 3);
451 tu_cs_image_flag_ref(cs
, iview
, 0);
455 A6XX_RB_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
457 A6XX_SP_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
459 tu_cs_emit_regs(cs
, A6XX_GRAS_MAX_LAYER_INDEX(fb
->layers
- 1));
463 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
465 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
466 bool msaa_disable
= samples
== MSAA_ONE
;
469 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
470 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
471 .msaa_disable
= msaa_disable
));
474 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
475 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
476 .msaa_disable
= msaa_disable
));
479 A6XX_RB_RAS_MSAA_CNTL(samples
),
480 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
481 .msaa_disable
= msaa_disable
));
484 A6XX_RB_MSAA_CNTL(samples
));
488 tu6_emit_bin_size(struct tu_cs
*cs
,
489 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
492 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
497 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
501 /* no flag for RB_BIN_CONTROL2... */
503 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
508 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
509 const struct tu_subpass
*subpass
,
513 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
515 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
517 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
519 uint32_t mrts_ubwc_enable
= 0;
520 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
521 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
522 if (a
== VK_ATTACHMENT_UNUSED
)
525 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
526 if (iview
->ubwc_enabled
)
527 mrts_ubwc_enable
|= 1 << i
;
530 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
532 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
533 if (a
!= VK_ATTACHMENT_UNUSED
) {
534 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
535 if (iview
->ubwc_enabled
)
536 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
539 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
540 * in order to set it correctly for the different subpasses. However,
541 * that means the packets we're emitting also happen during binning. So
542 * we need to guard the write on !BINNING at CP execution time.
544 tu_cs_reserve(cs
, 3 + 4);
545 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
546 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
547 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
548 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
551 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
552 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
553 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
554 tu_cs_emit(cs
, cntl
);
558 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
560 const VkRect2D
*render_area
= &cmd
->state
.tiling_config
.render_area
;
561 uint32_t x1
= render_area
->offset
.x
;
562 uint32_t y1
= render_area
->offset
.y
;
563 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
564 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
567 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
568 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
569 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
570 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
574 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
575 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
579 tu6_emit_window_scissor(struct tu_cs
*cs
,
586 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
587 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
590 A6XX_GRAS_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
591 A6XX_GRAS_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
595 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
598 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
601 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
604 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
607 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
611 use_hw_binning(struct tu_cmd_buffer
*cmd
)
613 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
615 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
618 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
621 return (tiling
->tile_count
.width
* tiling
->tile_count
.height
) > 2;
625 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
627 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
630 /* can't fit attachments into gmem */
631 if (!cmd
->state
.pass
->gmem_pixels
)
634 if (cmd
->state
.framebuffer
->layers
> 1)
637 return cmd
->state
.tiling_config
.force_sysmem
;
641 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
643 const struct tu_tile
*tile
)
645 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
646 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
648 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
649 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
651 const uint32_t x1
= tile
->begin
.x
;
652 const uint32_t y1
= tile
->begin
.y
;
653 const uint32_t x2
= tile
->end
.x
- 1;
654 const uint32_t y2
= tile
->end
.y
- 1;
655 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
656 tu6_emit_window_offset(cs
, x1
, y1
);
659 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
661 if (use_hw_binning(cmd
)) {
662 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
664 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
667 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
668 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
669 A6XX_CP_REG_TEST_0_BIT(0) |
670 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
672 tu_cs_reserve(cs
, 3 + 11);
673 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
674 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
675 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(11));
677 /* if (no overflow) */ {
678 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5
, 7);
679 tu_cs_emit(cs
, cmd
->state
.tiling_config
.pipe_sizes
[tile
->pipe
] |
680 CP_SET_BIN_DATA5_0_VSC_N(tile
->slot
));
681 tu_cs_emit_qw(cs
, cmd
->vsc_draw_strm
.iova
+ tile
->pipe
* cmd
->vsc_draw_strm_pitch
);
682 tu_cs_emit_qw(cs
, cmd
->vsc_draw_strm
.iova
+ (tile
->pipe
* 4) + (32 * cmd
->vsc_draw_strm_pitch
));
683 tu_cs_emit_qw(cs
, cmd
->vsc_prim_strm
.iova
+ (tile
->pipe
* cmd
->vsc_prim_strm_pitch
));
685 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
688 /* use a NOP packet to skip over the 'else' side: */
689 tu_cs_emit_pkt7(cs
, CP_NOP
, 2);
691 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
695 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
698 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
701 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
707 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
712 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
713 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
714 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
716 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.tiling_config
.render_area
);
720 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
722 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
723 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
725 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
726 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
727 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
728 CP_SET_DRAW_STATE__0_GROUP_ID(0));
729 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
730 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
732 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
735 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
736 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
738 tu6_emit_blit_scissor(cmd
, cs
, true);
740 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
741 if (pass
->attachments
[a
].gmem_offset
>= 0)
742 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
745 if (subpass
->resolve_attachments
) {
746 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
747 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
748 if (a
!= VK_ATTACHMENT_UNUSED
)
749 tu_store_gmem_attachment(cmd
, cs
, a
,
750 subpass
->color_attachments
[i
].attachment
);
756 tu6_emit_restart_index(struct tu_cs
*cs
, uint32_t restart_index
)
759 A6XX_PC_RESTART_INDEX(restart_index
));
763 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
765 const struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
767 tu6_emit_cache_flush(cmd
, cs
);
769 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 0xfffff);
772 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
773 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
774 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
775 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
776 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
777 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
778 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
779 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
780 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
782 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
783 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
784 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
785 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
786 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
787 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
788 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BB11
, 0);
789 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
790 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
791 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
792 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
793 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
794 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
795 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_GS_SIV_CNTL
, 0x0000ffff);
797 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
798 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
799 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
801 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
803 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
805 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
806 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
807 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
808 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
809 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
810 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
811 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
812 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
813 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
814 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
815 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
817 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9101
, 0xffff00);
818 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
820 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9236
,
821 A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
822 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
824 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_SO_OVERRIDE
,
825 A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
827 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
828 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
829 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9990
, 0);
831 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
832 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
834 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
836 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
838 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
839 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_809B
, 0);
840 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
841 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
842 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
843 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
844 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
845 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9981
, 0x3);
846 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
847 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9108
, 0x3);
848 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
849 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8878
, 0);
850 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8879
, 0);
851 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
853 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
855 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
857 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
859 /* we don't use this yet.. probably best to disable.. */
860 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
861 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
862 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
863 CP_SET_DRAW_STATE__0_GROUP_ID(0));
864 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
865 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
867 /* Set not to use streamout by default, */
868 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
869 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
871 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
875 A6XX_SP_HS_CTRL_REG0(0));
878 A6XX_SP_GS_CTRL_REG0(0));
881 A6XX_GRAS_LRZ_CNTL(0));
884 A6XX_RB_LRZ_CNTL(0));
887 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
889 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
891 tu_cs_sanity_check(cs
);
895 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
897 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
900 A6XX_VSC_BIN_SIZE(.width
= tiling
->tile0
.extent
.width
,
901 .height
= tiling
->tile0
.extent
.height
),
902 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo
= &cmd
->vsc_draw_strm
,
903 .bo_offset
= 32 * cmd
->vsc_draw_strm_pitch
));
906 A6XX_VSC_BIN_COUNT(.nx
= tiling
->tile_count
.width
,
907 .ny
= tiling
->tile_count
.height
));
909 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
910 for (unsigned i
= 0; i
< 32; i
++)
911 tu_cs_emit(cs
, tiling
->pipe_config
[i
]);
914 A6XX_VSC_PRIM_STRM_ADDRESS(.bo
= &cmd
->vsc_prim_strm
),
915 A6XX_VSC_PRIM_STRM_PITCH(cmd
->vsc_prim_strm_pitch
),
916 A6XX_VSC_PRIM_STRM_ARRAY_PITCH(cmd
->vsc_prim_strm
.size
));
919 A6XX_VSC_DRAW_STRM_ADDRESS(.bo
= &cmd
->vsc_draw_strm
),
920 A6XX_VSC_DRAW_STRM_PITCH(cmd
->vsc_draw_strm_pitch
),
921 A6XX_VSC_DRAW_STRM_ARRAY_PITCH(cmd
->vsc_draw_strm
.size
));
925 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
927 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
928 const uint32_t used_pipe_count
=
929 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
931 /* Clear vsc_scratch: */
932 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
933 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
936 /* Check for overflow, write vsc_scratch if detected: */
937 for (int i
= 0; i
< used_pipe_count
; i
++) {
938 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
939 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
940 CP_COND_WRITE5_0_WRITE_MEMORY
);
941 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i
)));
942 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
943 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_draw_strm_pitch
));
944 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
945 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
946 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd
->vsc_draw_strm_pitch
));
948 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
949 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
950 CP_COND_WRITE5_0_WRITE_MEMORY
);
951 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i
)));
952 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
953 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_prim_strm_pitch
));
954 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
955 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
956 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd
->vsc_prim_strm_pitch
));
959 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
961 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
963 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
964 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG
) |
965 CP_MEM_TO_REG_0_CNT(1 - 1));
966 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
969 * This is a bit awkward, we really want a way to invert the
970 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
971 * execute cmds to use hwbinning when a bit is *not* set. This
972 * dance is to invert OVERFLOW_FLAG_REG
974 * A CP_NOP packet is used to skip executing the 'else' clause
978 /* b0 will be set if VSC_DRAW_STRM or VSC_PRIM_STRM overflow: */
979 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
980 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
981 A6XX_CP_REG_TEST_0_BIT(0) |
982 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
984 tu_cs_reserve(cs
, 3 + 7);
985 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
986 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
987 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(7));
991 * On overflow, mirror the value to control->vsc_overflow
992 * which CPU is checking to detect overflow (see
993 * check_vsc_overflow())
995 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
996 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG
) |
997 CP_REG_TO_MEM_0_CNT(0));
998 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_overflow
));
1000 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1001 tu_cs_emit(cs
, 0x0);
1003 tu_cs_emit_pkt7(cs
, CP_NOP
, 2); /* skip 'else' when 'if' is taken */
1005 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1006 tu_cs_emit(cs
, 0x1);
1011 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1013 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1014 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1016 uint32_t x1
= tiling
->tile0
.offset
.x
;
1017 uint32_t y1
= tiling
->tile0
.offset
.y
;
1018 uint32_t x2
= tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
- 1;
1019 uint32_t y2
= tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
- 1;
1021 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
1023 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1024 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
1026 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1027 tu_cs_emit(cs
, 0x1);
1029 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1030 tu_cs_emit(cs
, 0x1);
1035 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
1037 update_vsc_pipe(cmd
, cs
);
1040 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1043 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1045 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1046 tu_cs_emit(cs
, UNK_2C
);
1049 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
1052 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
1054 /* emit IB to binning drawcmds: */
1055 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1057 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1058 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1059 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1060 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1061 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1062 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1064 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1065 tu_cs_emit(cs
, UNK_2D
);
1067 /* This flush is probably required because the VSC, which produces the
1068 * visibility stream, is a client of UCHE, whereas the CP needs to read the
1069 * visibility stream (without caching) to do draw skipping. The
1070 * WFI+WAIT_FOR_ME combination guarantees that the binning commands
1071 * submitted are finished before reading the VSC regs (in
1072 * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
1075 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
);
1079 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1081 emit_vsc_overflow_test(cmd
, cs
);
1083 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1084 tu_cs_emit(cs
, 0x0);
1086 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1087 tu_cs_emit(cs
, 0x0);
1089 cmd
->wait_for_idle
= false;
1093 tu_emit_load_clear(struct tu_cmd_buffer
*cmd
,
1094 const VkRenderPassBeginInfo
*info
)
1096 struct tu_cs
*cs
= &cmd
->draw_cs
;
1098 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1100 tu6_emit_blit_scissor(cmd
, cs
, true);
1102 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1103 tu_load_gmem_attachment(cmd
, cs
, i
, false);
1105 tu6_emit_blit_scissor(cmd
, cs
, false);
1107 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1108 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1110 tu_cond_exec_end(cs
);
1112 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1114 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1115 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1117 tu_cond_exec_end(cs
);
1121 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
,
1122 const struct VkRect2D
*renderArea
)
1124 const struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1125 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1127 assert(fb
->width
> 0 && fb
->height
> 0);
1128 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1129 tu6_emit_window_offset(cs
, 0, 0);
1131 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1133 tu6_emit_lrz_flush(cmd
, cs
);
1135 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1136 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1138 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1139 tu_cs_emit(cs
, 0x0);
1141 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_COLOR
);
1142 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_DEPTH
);
1143 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
1145 tu6_emit_wfi(cmd
, cs
);
1147 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
1149 /* enable stream-out, with sysmem there is only one pass: */
1151 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
1153 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1154 tu_cs_emit(cs
, 0x1);
1156 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1157 tu_cs_emit(cs
, 0x0);
1159 tu_cs_sanity_check(cs
);
1163 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1165 /* Do any resolves of the last subpass. These are handled in the
1166 * tile_store_ib in the gmem path.
1168 const struct tu_subpass
*subpass
= cmd
->state
.subpass
;
1169 if (subpass
->resolve_attachments
) {
1170 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
1171 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
1172 if (a
!= VK_ATTACHMENT_UNUSED
)
1173 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
1174 subpass
->color_attachments
[i
].attachment
);
1178 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1180 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1181 tu_cs_emit(cs
, 0x0);
1183 tu6_emit_lrz_flush(cmd
, cs
);
1185 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
);
1186 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
);
1188 tu_cs_sanity_check(cs
);
1193 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1195 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1197 tu6_emit_lrz_flush(cmd
, cs
);
1201 tu6_emit_cache_flush(cmd
, cs
);
1203 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1204 tu_cs_emit(cs
, 0x0);
1206 /* TODO: flushing with barriers instead of blindly always flushing */
1207 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
);
1208 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
);
1209 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_COLOR
);
1210 tu6_emit_event_write(cmd
, cs
, PC_CCU_INVALIDATE_DEPTH
);
1214 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_gmem
, .gmem
= 1));
1216 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1217 if (use_hw_binning(cmd
)) {
1218 /* enable stream-out during binning pass: */
1219 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1221 tu6_emit_bin_size(cs
,
1222 tiling
->tile0
.extent
.width
,
1223 tiling
->tile0
.extent
.height
,
1224 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1226 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1228 tu6_emit_binning_pass(cmd
, cs
);
1230 /* and disable stream-out for draw pass: */
1231 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=true));
1233 tu6_emit_bin_size(cs
,
1234 tiling
->tile0
.extent
.width
,
1235 tiling
->tile0
.extent
.height
,
1236 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1239 A6XX_VFD_MODE_CNTL(0));
1241 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1243 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1245 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1246 tu_cs_emit(cs
, 0x1);
1248 /* no binning pass, so enable stream-out for draw pass:: */
1249 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1251 tu6_emit_bin_size(cs
,
1252 tiling
->tile0
.extent
.width
,
1253 tiling
->tile0
.extent
.height
,
1257 tu_cs_sanity_check(cs
);
1261 tu6_render_tile(struct tu_cmd_buffer
*cmd
,
1263 const struct tu_tile
*tile
)
1265 tu6_emit_tile_select(cmd
, cs
, tile
);
1267 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1268 cmd
->wait_for_idle
= true;
1270 if (use_hw_binning(cmd
)) {
1271 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1272 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1273 A6XX_CP_REG_TEST_0_BIT(0) |
1274 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1276 tu_cs_reserve(cs
, 3 + 2);
1277 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1278 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
1279 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(2));
1281 /* if (no overflow) */ {
1282 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1283 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1287 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1289 tu_cs_sanity_check(cs
);
1293 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1295 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1298 A6XX_GRAS_LRZ_CNTL(0));
1300 tu6_emit_lrz_flush(cmd
, cs
);
1302 tu6_emit_event_write(cmd
, cs
, PC_CCU_RESOLVE_TS
);
1304 tu_cs_sanity_check(cs
);
1308 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1310 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1312 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1314 for (uint32_t y
= 0; y
< tiling
->tile_count
.height
; y
++) {
1315 for (uint32_t x
= 0; x
< tiling
->tile_count
.width
; x
++) {
1316 struct tu_tile tile
;
1317 tu_tiling_config_get_tile(tiling
, cmd
->device
, x
, y
, &tile
);
1318 tu6_render_tile(cmd
, &cmd
->cs
, &tile
);
1322 tu6_tile_render_end(cmd
, &cmd
->cs
);
1326 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1328 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1330 tu6_sysmem_render_begin(cmd
, &cmd
->cs
, &tiling
->render_area
);
1332 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1333 cmd
->wait_for_idle
= true;
1335 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1339 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1341 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1342 struct tu_cs sub_cs
;
1345 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1346 if (result
!= VK_SUCCESS
) {
1347 cmd
->record_result
= result
;
1351 /* emit to tile-store sub_cs */
1352 tu6_emit_tile_store(cmd
, &sub_cs
);
1354 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1358 tu_cmd_update_tiling_config(struct tu_cmd_buffer
*cmd
,
1359 const VkRect2D
*render_area
)
1361 const struct tu_device
*dev
= cmd
->device
;
1362 struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1364 tiling
->render_area
= *render_area
;
1365 tiling
->force_sysmem
= false;
1367 tu_tiling_config_update_tile_layout(tiling
, dev
, cmd
->state
.pass
);
1368 tu_tiling_config_update_pipe_layout(tiling
, dev
);
1369 tu_tiling_config_update_pipes(tiling
, dev
);
1372 const struct tu_dynamic_state default_dynamic_state
= {
1388 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
1394 .stencil_compare_mask
=
1399 .stencil_write_mask
=
1404 .stencil_reference
=
1411 static void UNUSED
/* FINISHME */
1412 tu_bind_dynamic_state(struct tu_cmd_buffer
*cmd_buffer
,
1413 const struct tu_dynamic_state
*src
)
1415 struct tu_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
1416 uint32_t copy_mask
= src
->mask
;
1417 uint32_t dest_mask
= 0;
1419 tu_use_args(cmd_buffer
); /* FINISHME */
1421 /* Make sure to copy the number of viewports/scissors because they can
1422 * only be specified at pipeline creation time.
1424 dest
->viewport
.count
= src
->viewport
.count
;
1425 dest
->scissor
.count
= src
->scissor
.count
;
1426 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
1428 if (copy_mask
& TU_DYNAMIC_VIEWPORT
) {
1429 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
1430 src
->viewport
.count
* sizeof(VkViewport
))) {
1431 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
1432 src
->viewport
.count
);
1433 dest_mask
|= TU_DYNAMIC_VIEWPORT
;
1437 if (copy_mask
& TU_DYNAMIC_SCISSOR
) {
1438 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
1439 src
->scissor
.count
* sizeof(VkRect2D
))) {
1440 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
1441 src
->scissor
.count
);
1442 dest_mask
|= TU_DYNAMIC_SCISSOR
;
1446 if (copy_mask
& TU_DYNAMIC_LINE_WIDTH
) {
1447 if (dest
->line_width
!= src
->line_width
) {
1448 dest
->line_width
= src
->line_width
;
1449 dest_mask
|= TU_DYNAMIC_LINE_WIDTH
;
1453 if (copy_mask
& TU_DYNAMIC_DEPTH_BIAS
) {
1454 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
1455 sizeof(src
->depth_bias
))) {
1456 dest
->depth_bias
= src
->depth_bias
;
1457 dest_mask
|= TU_DYNAMIC_DEPTH_BIAS
;
1461 if (copy_mask
& TU_DYNAMIC_BLEND_CONSTANTS
) {
1462 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
1463 sizeof(src
->blend_constants
))) {
1464 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
1465 dest_mask
|= TU_DYNAMIC_BLEND_CONSTANTS
;
1469 if (copy_mask
& TU_DYNAMIC_DEPTH_BOUNDS
) {
1470 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
1471 sizeof(src
->depth_bounds
))) {
1472 dest
->depth_bounds
= src
->depth_bounds
;
1473 dest_mask
|= TU_DYNAMIC_DEPTH_BOUNDS
;
1477 if (copy_mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
) {
1478 if (memcmp(&dest
->stencil_compare_mask
, &src
->stencil_compare_mask
,
1479 sizeof(src
->stencil_compare_mask
))) {
1480 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
1481 dest_mask
|= TU_DYNAMIC_STENCIL_COMPARE_MASK
;
1485 if (copy_mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
) {
1486 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
1487 sizeof(src
->stencil_write_mask
))) {
1488 dest
->stencil_write_mask
= src
->stencil_write_mask
;
1489 dest_mask
|= TU_DYNAMIC_STENCIL_WRITE_MASK
;
1493 if (copy_mask
& TU_DYNAMIC_STENCIL_REFERENCE
) {
1494 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
1495 sizeof(src
->stencil_reference
))) {
1496 dest
->stencil_reference
= src
->stencil_reference
;
1497 dest_mask
|= TU_DYNAMIC_STENCIL_REFERENCE
;
1501 if (copy_mask
& TU_DYNAMIC_DISCARD_RECTANGLE
) {
1502 if (memcmp(&dest
->discard_rectangle
.rectangles
,
1503 &src
->discard_rectangle
.rectangles
,
1504 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
1505 typed_memcpy(dest
->discard_rectangle
.rectangles
,
1506 src
->discard_rectangle
.rectangles
,
1507 src
->discard_rectangle
.count
);
1508 dest_mask
|= TU_DYNAMIC_DISCARD_RECTANGLE
;
1514 tu_create_cmd_buffer(struct tu_device
*device
,
1515 struct tu_cmd_pool
*pool
,
1516 VkCommandBufferLevel level
,
1517 VkCommandBuffer
*pCommandBuffer
)
1519 struct tu_cmd_buffer
*cmd_buffer
;
1520 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
1521 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1522 if (cmd_buffer
== NULL
)
1523 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1525 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1526 cmd_buffer
->device
= device
;
1527 cmd_buffer
->pool
= pool
;
1528 cmd_buffer
->level
= level
;
1531 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1532 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1535 /* Init the pool_link so we can safely call list_del when we destroy
1536 * the command buffer
1538 list_inithead(&cmd_buffer
->pool_link
);
1539 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1542 tu_bo_list_init(&cmd_buffer
->bo_list
);
1543 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1544 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1545 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1546 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1548 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1550 list_inithead(&cmd_buffer
->upload
.list
);
1552 VkResult result
= tu_bo_init_new(device
, &cmd_buffer
->scratch_bo
, 0x1000);
1553 if (result
!= VK_SUCCESS
)
1554 goto fail_scratch_bo
;
1556 /* TODO: resize on overflow */
1557 cmd_buffer
->vsc_draw_strm_pitch
= device
->vsc_draw_strm_pitch
;
1558 cmd_buffer
->vsc_prim_strm_pitch
= device
->vsc_prim_strm_pitch
;
1559 cmd_buffer
->vsc_draw_strm
= device
->vsc_draw_strm
;
1560 cmd_buffer
->vsc_prim_strm
= device
->vsc_prim_strm
;
1565 list_del(&cmd_buffer
->pool_link
);
1570 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1572 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->scratch_bo
);
1574 list_del(&cmd_buffer
->pool_link
);
1576 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++)
1577 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
1579 tu_cs_finish(&cmd_buffer
->cs
);
1580 tu_cs_finish(&cmd_buffer
->draw_cs
);
1581 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1582 tu_cs_finish(&cmd_buffer
->sub_cs
);
1584 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1585 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
1589 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1591 cmd_buffer
->wait_for_idle
= true;
1593 cmd_buffer
->record_result
= VK_SUCCESS
;
1595 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1596 tu_cs_reset(&cmd_buffer
->cs
);
1597 tu_cs_reset(&cmd_buffer
->draw_cs
);
1598 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1599 tu_cs_reset(&cmd_buffer
->sub_cs
);
1601 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++) {
1602 cmd_buffer
->descriptors
[i
].valid
= 0;
1603 cmd_buffer
->descriptors
[i
].push_dirty
= false;
1606 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1608 return cmd_buffer
->record_result
;
1612 tu_AllocateCommandBuffers(VkDevice _device
,
1613 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1614 VkCommandBuffer
*pCommandBuffers
)
1616 TU_FROM_HANDLE(tu_device
, device
, _device
);
1617 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1619 VkResult result
= VK_SUCCESS
;
1622 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1624 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1625 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1626 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1628 list_del(&cmd_buffer
->pool_link
);
1629 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1631 result
= tu_reset_cmd_buffer(cmd_buffer
);
1632 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1633 cmd_buffer
->level
= pAllocateInfo
->level
;
1635 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1637 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1638 &pCommandBuffers
[i
]);
1640 if (result
!= VK_SUCCESS
)
1644 if (result
!= VK_SUCCESS
) {
1645 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1648 /* From the Vulkan 1.0.66 spec:
1650 * "vkAllocateCommandBuffers can be used to create multiple
1651 * command buffers. If the creation of any of those command
1652 * buffers fails, the implementation must destroy all
1653 * successfully created command buffer objects from this
1654 * command, set all entries of the pCommandBuffers array to
1655 * NULL and return the error."
1657 memset(pCommandBuffers
, 0,
1658 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1665 tu_FreeCommandBuffers(VkDevice device
,
1666 VkCommandPool commandPool
,
1667 uint32_t commandBufferCount
,
1668 const VkCommandBuffer
*pCommandBuffers
)
1670 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1671 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1674 if (cmd_buffer
->pool
) {
1675 list_del(&cmd_buffer
->pool_link
);
1676 list_addtail(&cmd_buffer
->pool_link
,
1677 &cmd_buffer
->pool
->free_cmd_buffers
);
1679 tu_cmd_buffer_destroy(cmd_buffer
);
1685 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1686 VkCommandBufferResetFlags flags
)
1688 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1689 return tu_reset_cmd_buffer(cmd_buffer
);
1693 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1694 const VkCommandBufferBeginInfo
*pBeginInfo
)
1696 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1697 VkResult result
= VK_SUCCESS
;
1699 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1700 /* If the command buffer has already been resetted with
1701 * vkResetCommandBuffer, no need to do it again.
1703 result
= tu_reset_cmd_buffer(cmd_buffer
);
1704 if (result
!= VK_SUCCESS
)
1708 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1709 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1711 tu_cs_begin(&cmd_buffer
->cs
);
1712 tu_cs_begin(&cmd_buffer
->draw_cs
);
1713 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1715 /* setup initial configuration into command buffer */
1716 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1717 switch (cmd_buffer
->queue_family_index
) {
1718 case TU_QUEUE_GENERAL
:
1719 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1724 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
1725 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
1726 assert(pBeginInfo
->pInheritanceInfo
);
1727 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1728 cmd_buffer
->state
.subpass
= &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1731 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1736 /* Sets vertex buffers to HW binding points. We emit VBs in SDS (so that bin
1737 * rendering can skip over unused state), so we need to collect all the
1738 * bindings together into a single state emit at draw time.
1741 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1742 uint32_t firstBinding
,
1743 uint32_t bindingCount
,
1744 const VkBuffer
*pBuffers
,
1745 const VkDeviceSize
*pOffsets
)
1747 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1749 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1751 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1752 struct tu_buffer
*buf
= tu_buffer_from_handle(pBuffers
[i
]);
1754 cmd
->state
.vb
.buffers
[firstBinding
+ i
] = buf
;
1755 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1757 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1760 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1764 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1766 VkDeviceSize offset
,
1767 VkIndexType indexType
)
1769 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1770 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1772 /* initialize/update the restart index */
1773 if (!cmd
->state
.index_buffer
|| cmd
->state
.index_type
!= indexType
) {
1774 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1776 tu6_emit_restart_index(
1777 draw_cs
, indexType
== VK_INDEX_TYPE_UINT32
? 0xffffffff : 0xffff);
1779 tu_cs_sanity_check(draw_cs
);
1783 if (cmd
->state
.index_buffer
!= buf
)
1784 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1786 cmd
->state
.index_buffer
= buf
;
1787 cmd
->state
.index_offset
= offset
;
1788 cmd
->state
.index_type
= indexType
;
1792 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1793 VkPipelineBindPoint pipelineBindPoint
,
1794 VkPipelineLayout _layout
,
1796 uint32_t descriptorSetCount
,
1797 const VkDescriptorSet
*pDescriptorSets
,
1798 uint32_t dynamicOffsetCount
,
1799 const uint32_t *pDynamicOffsets
)
1801 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1802 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1803 unsigned dyn_idx
= 0;
1805 struct tu_descriptor_state
*descriptors_state
=
1806 tu_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
1808 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1809 unsigned idx
= i
+ firstSet
;
1810 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1812 descriptors_state
->sets
[idx
] = set
;
1813 descriptors_state
->valid
|= (1u << idx
);
1815 /* Note: the actual input attachment indices come from the shader
1816 * itself, so we can't generate the patched versions of these until
1817 * draw time when both the pipeline and descriptors are bound and
1818 * we're inside the render pass.
1820 unsigned dst_idx
= layout
->set
[idx
].input_attachment_start
;
1821 memcpy(&descriptors_state
->input_attachments
[dst_idx
* A6XX_TEX_CONST_DWORDS
],
1822 set
->dynamic_descriptors
,
1823 set
->layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
* 4);
1825 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1826 /* Dynamic buffers come after input attachments in the descriptor set
1827 * itself, but due to how the Vulkan descriptor set binding works, we
1828 * have to put input attachments and dynamic buffers in separate
1829 * buffers in the descriptor_state and then combine them at draw
1830 * time. Binding a descriptor set only invalidates the descriptor
1831 * sets after it, but if we try to tightly pack the descriptors after
1832 * the input attachments then we could corrupt dynamic buffers in the
1833 * descriptor set before it, or we'd have to move all the dynamic
1834 * buffers over. We just put them into separate buffers to make
1835 * binding as well as the later patching of input attachments easy.
1837 unsigned src_idx
= j
+ set
->layout
->input_attachment_count
;
1838 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1839 assert(dyn_idx
< dynamicOffsetCount
);
1842 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1844 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1845 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1847 /* Patch the storage/uniform descriptors right away. */
1848 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1849 /* Note: we can assume here that the addition won't roll over and
1850 * change the SIZE field.
1852 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1857 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1858 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1859 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1867 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
)
1868 cmd_buffer
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
;
1870 cmd_buffer
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
;
1873 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
1874 uint32_t firstBinding
,
1875 uint32_t bindingCount
,
1876 const VkBuffer
*pBuffers
,
1877 const VkDeviceSize
*pOffsets
,
1878 const VkDeviceSize
*pSizes
)
1880 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1881 assert(firstBinding
+ bindingCount
<= IR3_MAX_SO_BUFFERS
);
1883 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1884 uint32_t idx
= firstBinding
+ i
;
1885 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
1887 if (pOffsets
[i
] != 0)
1888 cmd
->state
.streamout_reset
|= 1 << idx
;
1890 cmd
->state
.streamout_buf
.buffers
[idx
] = buf
;
1891 cmd
->state
.streamout_buf
.offsets
[idx
] = pOffsets
[i
];
1892 cmd
->state
.streamout_buf
.sizes
[idx
] = pSizes
[i
];
1894 cmd
->state
.streamout_enabled
|= 1 << idx
;
1897 cmd
->state
.dirty
|= TU_CMD_DIRTY_STREAMOUT_BUFFERS
;
1900 void tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1901 uint32_t firstCounterBuffer
,
1902 uint32_t counterBufferCount
,
1903 const VkBuffer
*pCounterBuffers
,
1904 const VkDeviceSize
*pCounterBufferOffsets
)
1906 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1907 /* TODO do something with counter buffer? */
1910 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1911 uint32_t firstCounterBuffer
,
1912 uint32_t counterBufferCount
,
1913 const VkBuffer
*pCounterBuffers
,
1914 const VkDeviceSize
*pCounterBufferOffsets
)
1916 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
1917 /* TODO do something with counter buffer? */
1919 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1920 cmd
->state
.streamout_enabled
= 0;
1924 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1925 VkPipelineLayout layout
,
1926 VkShaderStageFlags stageFlags
,
1929 const void *pValues
)
1931 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1932 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1933 cmd
->state
.dirty
|= TU_CMD_DIRTY_PUSH_CONSTANTS
;
1937 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
1939 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1941 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->scratch_bo
,
1942 MSM_SUBMIT_BO_WRITE
);
1944 if (cmd_buffer
->use_vsc_data
) {
1945 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_draw_strm
,
1946 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1947 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_prim_strm
,
1948 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1951 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->border_color
,
1952 MSM_SUBMIT_BO_READ
);
1954 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
1955 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
1956 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1959 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
1960 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
1961 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1964 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
1965 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
1966 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1969 tu_cs_end(&cmd_buffer
->cs
);
1970 tu_cs_end(&cmd_buffer
->draw_cs
);
1971 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
1973 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
1975 return cmd_buffer
->record_result
;
1979 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
1980 VkPipelineBindPoint pipelineBindPoint
,
1981 VkPipeline _pipeline
)
1983 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1984 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
1986 switch (pipelineBindPoint
) {
1987 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
1988 cmd
->state
.pipeline
= pipeline
;
1989 cmd
->state
.dirty
|= TU_CMD_DIRTY_PIPELINE
;
1991 case VK_PIPELINE_BIND_POINT_COMPUTE
:
1992 cmd
->state
.compute_pipeline
= pipeline
;
1993 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
1996 unreachable("unrecognized pipeline bind point");
2000 /* If the new pipeline requires more VBs than we had previously set up, we
2001 * need to re-emit them in SDS. If it requires the same set or fewer, we
2002 * can just re-use the old SDS.
2004 if (pipeline
->vi
.bindings_used
& ~cmd
->vertex_bindings_set
)
2005 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
2007 tu_bo_list_add(&cmd
->bo_list
, &pipeline
->program
.binary_bo
,
2008 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2009 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2010 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2011 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2016 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2017 uint32_t firstViewport
,
2018 uint32_t viewportCount
,
2019 const VkViewport
*pViewports
)
2021 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2023 assert(firstViewport
== 0 && viewportCount
== 1);
2024 cmd
->state
.dynamic
.viewport
.viewports
[0] = pViewports
[0];
2025 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2029 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2030 uint32_t firstScissor
,
2031 uint32_t scissorCount
,
2032 const VkRect2D
*pScissors
)
2034 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2036 assert(firstScissor
== 0 && scissorCount
== 1);
2037 cmd
->state
.dynamic
.scissor
.scissors
[0] = pScissors
[0];
2038 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_SCISSOR
;
2042 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2044 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2046 cmd
->state
.dynamic
.line_width
= lineWidth
;
2048 /* line width depends on VkPipelineRasterizationStateCreateInfo */
2049 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2053 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2054 float depthBiasConstantFactor
,
2055 float depthBiasClamp
,
2056 float depthBiasSlopeFactor
)
2058 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2059 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2061 tu6_emit_depth_bias(draw_cs
, depthBiasConstantFactor
, depthBiasClamp
,
2062 depthBiasSlopeFactor
);
2064 tu_cs_sanity_check(draw_cs
);
2068 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2069 const float blendConstants
[4])
2071 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2072 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
2074 tu6_emit_blend_constants(draw_cs
, blendConstants
);
2076 tu_cs_sanity_check(draw_cs
);
2080 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2081 float minDepthBounds
,
2082 float maxDepthBounds
)
2087 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2088 VkStencilFaceFlags faceMask
,
2089 uint32_t compareMask
)
2091 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2093 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2094 cmd
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
2095 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2096 cmd
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
2098 /* the front/back compare masks must be updated together */
2099 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2103 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2104 VkStencilFaceFlags faceMask
,
2107 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2109 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2110 cmd
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
2111 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2112 cmd
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
2114 /* the front/back write masks must be updated together */
2115 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2119 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2120 VkStencilFaceFlags faceMask
,
2123 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2125 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
2126 cmd
->state
.dynamic
.stencil_reference
.front
= reference
;
2127 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
2128 cmd
->state
.dynamic
.stencil_reference
.back
= reference
;
2130 /* the front/back references must be updated together */
2131 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2135 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer
,
2136 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
2138 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2140 tu6_emit_sample_locations(&cmd
->draw_cs
, pSampleLocationsInfo
);
2144 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2145 uint32_t commandBufferCount
,
2146 const VkCommandBuffer
*pCmdBuffers
)
2148 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2151 assert(commandBufferCount
> 0);
2153 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2154 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2156 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2157 if (result
!= VK_SUCCESS
) {
2158 cmd
->record_result
= result
;
2162 if (secondary
->usage_flags
&
2163 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2164 assert(tu_cs_is_empty(&secondary
->cs
));
2166 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2167 if (result
!= VK_SUCCESS
) {
2168 cmd
->record_result
= result
;
2172 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2173 &secondary
->draw_epilogue_cs
);
2174 if (result
!= VK_SUCCESS
) {
2175 cmd
->record_result
= result
;
2179 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2180 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2182 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2183 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2184 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2187 tu_cs_add_entries(&cmd
->cs
, &secondary
->cs
);
2190 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2194 tu_CreateCommandPool(VkDevice _device
,
2195 const VkCommandPoolCreateInfo
*pCreateInfo
,
2196 const VkAllocationCallbacks
*pAllocator
,
2197 VkCommandPool
*pCmdPool
)
2199 TU_FROM_HANDLE(tu_device
, device
, _device
);
2200 struct tu_cmd_pool
*pool
;
2202 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2203 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2205 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2208 pool
->alloc
= *pAllocator
;
2210 pool
->alloc
= device
->alloc
;
2212 list_inithead(&pool
->cmd_buffers
);
2213 list_inithead(&pool
->free_cmd_buffers
);
2215 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2217 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2223 tu_DestroyCommandPool(VkDevice _device
,
2224 VkCommandPool commandPool
,
2225 const VkAllocationCallbacks
*pAllocator
)
2227 TU_FROM_HANDLE(tu_device
, device
, _device
);
2228 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2233 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2234 &pool
->cmd_buffers
, pool_link
)
2236 tu_cmd_buffer_destroy(cmd_buffer
);
2239 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2240 &pool
->free_cmd_buffers
, pool_link
)
2242 tu_cmd_buffer_destroy(cmd_buffer
);
2245 vk_free2(&device
->alloc
, pAllocator
, pool
);
2249 tu_ResetCommandPool(VkDevice device
,
2250 VkCommandPool commandPool
,
2251 VkCommandPoolResetFlags flags
)
2253 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2256 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2259 result
= tu_reset_cmd_buffer(cmd_buffer
);
2260 if (result
!= VK_SUCCESS
)
2268 tu_TrimCommandPool(VkDevice device
,
2269 VkCommandPool commandPool
,
2270 VkCommandPoolTrimFlags flags
)
2272 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2277 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2278 &pool
->free_cmd_buffers
, pool_link
)
2280 tu_cmd_buffer_destroy(cmd_buffer
);
2285 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2286 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2287 VkSubpassContents contents
)
2289 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2290 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2291 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2293 cmd
->state
.pass
= pass
;
2294 cmd
->state
.subpass
= pass
->subpasses
;
2295 cmd
->state
.framebuffer
= fb
;
2297 tu_cmd_update_tiling_config(cmd
, &pRenderPassBegin
->renderArea
);
2298 tu_cmd_prepare_tile_store_ib(cmd
);
2300 tu_emit_load_clear(cmd
, pRenderPassBegin
);
2302 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2303 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2304 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2305 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2307 /* note: use_hw_binning only checks tiling config */
2308 if (use_hw_binning(cmd
))
2309 cmd
->use_vsc_data
= true;
2311 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2312 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2313 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2314 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2317 /* Flag input attachment descriptors for re-emission if necessary */
2318 cmd
->state
.dirty
|= TU_CMD_DIRTY_INPUT_ATTACHMENTS
;
2322 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2323 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2324 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2326 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2327 pSubpassBeginInfo
->contents
);
2331 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2333 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2334 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2335 struct tu_cs
*cs
= &cmd
->draw_cs
;
2337 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2339 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2341 if (subpass
->resolve_attachments
) {
2342 tu6_emit_blit_scissor(cmd
, cs
, true);
2344 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2345 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2346 if (a
== VK_ATTACHMENT_UNUSED
)
2349 tu_store_gmem_attachment(cmd
, cs
, a
,
2350 subpass
->color_attachments
[i
].attachment
);
2352 if (pass
->attachments
[a
].gmem_offset
< 0)
2356 * check if the resolved attachment is needed by later subpasses,
2357 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2359 tu_finishme("missing GMEM->GMEM resolve path\n");
2360 tu_load_gmem_attachment(cmd
, cs
, a
, true);
2364 tu_cond_exec_end(cs
);
2366 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2368 /* Emit flushes so that input attachments will read the correct value.
2369 * TODO: use subpass dependencies to flush or not
2371 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
);
2372 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_DEPTH_TS
);
2374 if (subpass
->resolve_attachments
) {
2375 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
2377 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2378 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2379 if (a
== VK_ATTACHMENT_UNUSED
)
2382 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
2383 subpass
->color_attachments
[i
].attachment
);
2386 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
);
2389 tu_cond_exec_end(cs
);
2391 /* subpass->input_count > 0 then texture cache invalidate is likely to be needed */
2392 if (cmd
->state
.subpass
->input_count
)
2393 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
2395 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2396 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2397 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2398 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2399 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2401 /* Flag input attachment descriptors for re-emission if necessary */
2402 cmd
->state
.dirty
|= TU_CMD_DIRTY_INPUT_ATTACHMENTS
;
2406 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2407 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2408 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2410 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2416 * Number of vertices.
2421 * Index of the first vertex.
2423 int32_t vertex_offset
;
2426 * First instance id.
2428 uint32_t first_instance
;
2431 * Number of instances.
2433 uint32_t instance_count
;
2436 * First index (indexed draws only).
2438 uint32_t first_index
;
2441 * Whether it's an indexed draw.
2446 * Indirect draw parameters resource.
2448 struct tu_buffer
*indirect
;
2449 uint64_t indirect_offset
;
2453 * Draw count parameters resource.
2455 struct tu_buffer
*count_buffer
;
2456 uint64_t count_buffer_offset
;
2459 * Stream output parameters resource.
2461 struct tu_buffer
*streamout_buffer
;
2462 uint64_t streamout_buffer_offset
;
2465 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2466 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2467 #define ENABLE_NON_GMEM (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_SYSMEM)
2469 enum tu_draw_state_group_id
2471 TU_DRAW_STATE_PROGRAM
,
2472 TU_DRAW_STATE_PROGRAM_BINNING
,
2475 TU_DRAW_STATE_VI_BINNING
,
2479 TU_DRAW_STATE_BLEND
,
2480 TU_DRAW_STATE_VS_CONST
,
2481 TU_DRAW_STATE_GS_CONST
,
2482 TU_DRAW_STATE_FS_CONST
,
2483 TU_DRAW_STATE_DESC_SETS
,
2484 TU_DRAW_STATE_DESC_SETS_GMEM
,
2485 TU_DRAW_STATE_DESC_SETS_LOAD
,
2486 TU_DRAW_STATE_VS_PARAMS
,
2488 TU_DRAW_STATE_COUNT
,
2491 struct tu_draw_state_group
2493 enum tu_draw_state_group_id id
;
2494 uint32_t enable_mask
;
2495 struct tu_cs_entry ib
;
2498 static inline uint32_t
2499 tu6_stage2opcode(gl_shader_stage type
)
2502 case MESA_SHADER_VERTEX
:
2503 case MESA_SHADER_TESS_CTRL
:
2504 case MESA_SHADER_TESS_EVAL
:
2505 case MESA_SHADER_GEOMETRY
:
2506 return CP_LOAD_STATE6_GEOM
;
2507 case MESA_SHADER_FRAGMENT
:
2508 case MESA_SHADER_COMPUTE
:
2509 case MESA_SHADER_KERNEL
:
2510 return CP_LOAD_STATE6_FRAG
;
2512 unreachable("bad shader type");
2516 static inline enum a6xx_state_block
2517 tu6_stage2shadersb(gl_shader_stage type
)
2520 case MESA_SHADER_VERTEX
:
2521 return SB6_VS_SHADER
;
2522 case MESA_SHADER_GEOMETRY
:
2523 return SB6_GS_SHADER
;
2524 case MESA_SHADER_FRAGMENT
:
2525 return SB6_FS_SHADER
;
2526 case MESA_SHADER_COMPUTE
:
2527 case MESA_SHADER_KERNEL
:
2528 return SB6_CS_SHADER
;
2530 unreachable("bad shader type");
2536 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2537 struct tu_descriptor_state
*descriptors_state
,
2538 gl_shader_stage type
,
2539 uint32_t *push_constants
)
2541 const struct tu_program_descriptor_linkage
*link
=
2542 &pipeline
->program
.link
[type
];
2543 const struct ir3_ubo_analysis_state
*state
= &link
->ubo_state
;
2545 if (link
->push_consts
.count
> 0) {
2546 unsigned num_units
= link
->push_consts
.count
;
2547 unsigned offset
= link
->push_consts
.lo
;
2548 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2549 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2550 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2551 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2552 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2553 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2556 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2557 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2560 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2561 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2562 uint32_t offset
= state
->range
[i
].start
;
2564 /* and even if the start of the const buffer is before
2565 * first_immediate, the end may not be:
2567 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2572 /* things should be aligned to vec4: */
2573 debug_assert((state
->range
[i
].offset
% 16) == 0);
2574 debug_assert((size
% 16) == 0);
2575 debug_assert((offset
% 16) == 0);
2577 /* Dig out the descriptor from the descriptor state and read the VA from
2580 assert(state
->range
[i
].bindless
);
2581 uint32_t *base
= state
->range
[i
].bindless_base
== MAX_SETS
?
2582 descriptors_state
->dynamic_descriptors
:
2583 descriptors_state
->sets
[state
->range
[i
].bindless_base
]->mapped_ptr
;
2584 unsigned block
= state
->range
[i
].block
;
2585 /* If the block in the shader here is in the dynamic descriptor set, it
2586 * is an index into the dynamic descriptor set which is combined from
2587 * dynamic descriptors and input attachments on-the-fly, and we don't
2588 * have access to it here. Instead we work backwards to get the index
2589 * into dynamic_descriptors.
2591 if (state
->range
[i
].bindless_base
== MAX_SETS
)
2592 block
-= pipeline
->layout
->input_attachment_count
;
2593 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2594 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2597 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2598 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2599 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2600 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2601 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2602 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2603 tu_cs_emit_qw(cs
, va
+ offset
);
2607 static struct tu_cs_entry
2608 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2609 const struct tu_pipeline
*pipeline
,
2610 struct tu_descriptor_state
*descriptors_state
,
2611 gl_shader_stage type
)
2614 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2616 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2618 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2622 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
2623 const struct tu_draw_info
*draw
,
2624 struct tu_cs_entry
*entry
)
2626 /* TODO: fill out more than just base instance */
2627 const struct tu_program_descriptor_linkage
*link
=
2628 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
2629 const struct ir3_const_state
*const_state
= &link
->const_state
;
2632 if (const_state
->offsets
.driver_param
>= link
->constlen
) {
2633 *entry
= (struct tu_cs_entry
) {};
2637 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 8, &cs
);
2638 if (result
!= VK_SUCCESS
)
2641 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2642 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(const_state
->offsets
.driver_param
) |
2643 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2644 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2645 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
2646 CP_LOAD_STATE6_0_NUM_UNIT(1));
2650 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
2654 tu_cs_emit(&cs
, draw
->first_instance
);
2657 *entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2661 static struct tu_cs_entry
2662 tu6_emit_vertex_buffers(struct tu_cmd_buffer
*cmd
,
2663 const struct tu_pipeline
*pipeline
)
2666 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 4 * MAX_VBS
, &cs
);
2669 for_each_bit(binding
, pipeline
->vi
.bindings_used
) {
2670 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2671 const VkDeviceSize offset
= buf
->bo_offset
+
2672 cmd
->state
.vb
.offsets
[binding
];
2674 tu_cs_emit_regs(&cs
,
2675 A6XX_VFD_FETCH_BASE(binding
, .bo
= buf
->bo
, .bo_offset
= offset
),
2676 A6XX_VFD_FETCH_SIZE(binding
, buf
->size
- offset
));
2680 cmd
->vertex_bindings_set
= pipeline
->vi
.bindings_used
;
2682 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2686 tu6_emit_descriptor_sets(struct tu_cmd_buffer
*cmd
,
2687 const struct tu_pipeline
*pipeline
,
2688 VkPipelineBindPoint bind_point
,
2689 struct tu_cs_entry
*entry
,
2692 struct tu_cs
*draw_state
= &cmd
->sub_cs
;
2693 struct tu_pipeline_layout
*layout
= pipeline
->layout
;
2694 struct tu_descriptor_state
*descriptors_state
=
2695 tu_get_descriptors_state(cmd
, bind_point
);
2696 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
2697 const uint32_t *input_attachment_idx
=
2698 pipeline
->program
.input_attachment_idx
;
2699 uint32_t num_dynamic_descs
= layout
->dynamic_offset_count
+
2700 layout
->input_attachment_count
;
2701 struct ts_cs_memory dynamic_desc_set
;
2704 if (num_dynamic_descs
> 0) {
2705 /* allocate and fill out dynamic descriptor set */
2706 result
= tu_cs_alloc(draw_state
, num_dynamic_descs
,
2707 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
2708 if (result
!= VK_SUCCESS
)
2711 memcpy(dynamic_desc_set
.map
, descriptors_state
->input_attachments
,
2712 layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
* 4);
2715 /* Patch input attachments to refer to GMEM instead */
2716 for (unsigned i
= 0; i
< layout
->input_attachment_count
; i
++) {
2718 &dynamic_desc_set
.map
[A6XX_TEX_CONST_DWORDS
* i
];
2720 /* The compiler has already laid out input_attachment_idx in the
2721 * final order of input attachments, so there's no need to go
2722 * through the pipeline layout finding input attachments.
2724 unsigned attachment_idx
= input_attachment_idx
[i
];
2726 /* It's possible for the pipeline layout to include an input
2727 * attachment which doesn't actually exist for the current
2728 * subpass. Of course, this is only valid so long as the pipeline
2729 * doesn't try to actually load that attachment. Just skip
2730 * patching in that scenario to avoid out-of-bounds accesses.
2732 if (attachment_idx
>= cmd
->state
.subpass
->input_count
)
2735 uint32_t a
= cmd
->state
.subpass
->input_attachments
[attachment_idx
].attachment
;
2736 const struct tu_render_pass_attachment
*att
= &cmd
->state
.pass
->attachments
[a
];
2738 assert(att
->gmem_offset
>= 0);
2740 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
2741 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
2742 dst
[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK
| A6XX_TEX_CONST_2_PITCH__MASK
);
2744 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
2745 A6XX_TEX_CONST_2_PITCH(tiling
->tile0
.extent
.width
* att
->cpp
);
2747 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ att
->gmem_offset
;
2748 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
2749 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
2752 if (cmd
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
2753 tu_finishme("patch input attachment pitch for secondary cmd buffer");
2757 memcpy(dynamic_desc_set
.map
+ layout
->input_attachment_count
* A6XX_TEX_CONST_DWORDS
,
2758 descriptors_state
->dynamic_descriptors
,
2759 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
2762 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
;
2763 uint32_t hlsq_update_value
;
2764 switch (bind_point
) {
2765 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
2766 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
2767 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
2768 hlsq_update_value
= 0x7c000;
2770 case VK_PIPELINE_BIND_POINT_COMPUTE
:
2771 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
2772 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
2773 hlsq_update_value
= 0x3e00;
2776 unreachable("bad bind point");
2779 /* Be careful here to *not* refer to the pipeline, so that if only the
2780 * pipeline changes we don't have to emit this again (except if there are
2781 * dynamic descriptors in the pipeline layout). This means always emitting
2782 * all the valid descriptors, which means that we always have to put the
2783 * dynamic descriptor in the driver-only slot at the end
2785 uint32_t num_user_sets
= util_last_bit(descriptors_state
->valid
);
2786 uint32_t num_sets
= num_user_sets
;
2787 if (num_dynamic_descs
> 0) {
2788 num_user_sets
= MAX_SETS
;
2789 num_sets
= num_user_sets
+ 1;
2792 unsigned regs
[2] = { sp_bindless_base_reg
, hlsq_bindless_base_reg
};
2795 result
= tu_cs_begin_sub_stream(draw_state
, ARRAY_SIZE(regs
) * (1 + num_sets
* 2) + 2, &cs
);
2796 if (result
!= VK_SUCCESS
)
2800 for (unsigned i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
2801 tu_cs_emit_pkt4(&cs
, regs
[i
], num_sets
* 2);
2802 for (unsigned j
= 0; j
< num_user_sets
; j
++) {
2803 if (descriptors_state
->valid
& (1 << j
)) {
2804 /* magic | 3 copied from the blob */
2805 tu_cs_emit_qw(&cs
, descriptors_state
->sets
[j
]->va
| 3);
2807 tu_cs_emit_qw(&cs
, 0 | 3);
2810 if (num_dynamic_descs
> 0) {
2811 tu_cs_emit_qw(&cs
, dynamic_desc_set
.iova
| 3);
2815 tu_cs_emit_regs(&cs
, A6XX_HLSQ_UPDATE_CNTL(hlsq_update_value
));
2818 *entry
= tu_cs_end_sub_stream(draw_state
, &cs
);
2823 tu6_emit_streamout(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
2825 struct tu_streamout_state
*tf
= &cmd
->state
.pipeline
->streamout
;
2827 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2828 struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
2833 offset
= cmd
->state
.streamout_buf
.offsets
[i
];
2835 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_BASE(i
, .bo
= buf
->bo
,
2836 .bo_offset
= buf
->bo_offset
));
2837 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_SIZE(i
, buf
->size
));
2839 if (cmd
->state
.streamout_reset
& (1 << i
)) {
2840 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, offset
));
2841 cmd
->state
.streamout_reset
&= ~(1 << i
);
2843 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
2844 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i
)) |
2845 CP_MEM_TO_REG_0_SHIFT_BY_2
| CP_MEM_TO_REG_0_UNK31
|
2846 CP_MEM_TO_REG_0_CNT(0));
2847 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+
2848 ctrl_offset(flush_base
[i
].offset
));
2851 tu_cs_emit_regs(cs
, A6XX_VPC_SO_FLUSH_BASE(i
, .bo
= &cmd
->scratch_bo
,
2853 ctrl_offset(flush_base
[i
])));
2856 if (cmd
->state
.streamout_enabled
) {
2857 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * tf
->prog_count
));
2858 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
2859 tu_cs_emit(cs
, tf
->vpc_so_buf_cntl
);
2860 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(0));
2861 tu_cs_emit(cs
, tf
->ncomp
[0]);
2862 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(1));
2863 tu_cs_emit(cs
, tf
->ncomp
[1]);
2864 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(2));
2865 tu_cs_emit(cs
, tf
->ncomp
[2]);
2866 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(3));
2867 tu_cs_emit(cs
, tf
->ncomp
[3]);
2868 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
2869 tu_cs_emit(cs
, A6XX_VPC_SO_CNTL_ENABLE
);
2870 for (unsigned i
= 0; i
< tf
->prog_count
; i
++) {
2871 tu_cs_emit(cs
, REG_A6XX_VPC_SO_PROG
);
2872 tu_cs_emit(cs
, tf
->prog
[i
]);
2875 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
2876 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
2878 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
2884 tu6_bind_draw_states(struct tu_cmd_buffer
*cmd
,
2886 const struct tu_draw_info
*draw
)
2888 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
2889 const struct tu_dynamic_state
*dynamic
= &cmd
->state
.dynamic
;
2890 struct tu_draw_state_group draw_state_groups
[TU_DRAW_STATE_COUNT
];
2891 uint32_t draw_state_group_count
= 0;
2894 struct tu_descriptor_state
*descriptors_state
=
2895 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
2900 A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart
=
2901 pipeline
->ia
.primitive_restart
&& draw
->indexed
));
2903 if (cmd
->state
.dirty
&
2904 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) &&
2905 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
)) {
2906 tu6_emit_gras_su_cntl(cs
, pipeline
->rast
.gras_su_cntl
,
2907 dynamic
->line_width
);
2910 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) &&
2911 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
2912 tu6_emit_stencil_compare_mask(cs
, dynamic
->stencil_compare_mask
.front
,
2913 dynamic
->stencil_compare_mask
.back
);
2916 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) &&
2917 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
2918 tu6_emit_stencil_write_mask(cs
, dynamic
->stencil_write_mask
.front
,
2919 dynamic
->stencil_write_mask
.back
);
2922 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) &&
2923 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
2924 tu6_emit_stencil_reference(cs
, dynamic
->stencil_reference
.front
,
2925 dynamic
->stencil_reference
.back
);
2928 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2929 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_VIEWPORT
)) {
2930 tu6_emit_viewport(cs
, &cmd
->state
.dynamic
.viewport
.viewports
[0]);
2933 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_SCISSOR
) &&
2934 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SCISSOR
)) {
2935 tu6_emit_scissor(cs
, &cmd
->state
.dynamic
.scissor
.scissors
[0]);
2938 if (cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) {
2939 draw_state_groups
[draw_state_group_count
++] =
2940 (struct tu_draw_state_group
) {
2941 .id
= TU_DRAW_STATE_PROGRAM
,
2942 .enable_mask
= ENABLE_DRAW
,
2943 .ib
= pipeline
->program
.state_ib
,
2945 draw_state_groups
[draw_state_group_count
++] =
2946 (struct tu_draw_state_group
) {
2947 .id
= TU_DRAW_STATE_PROGRAM_BINNING
,
2948 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
2949 .ib
= pipeline
->program
.binning_state_ib
,
2951 draw_state_groups
[draw_state_group_count
++] =
2952 (struct tu_draw_state_group
) {
2953 .id
= TU_DRAW_STATE_VI
,
2954 .enable_mask
= ENABLE_DRAW
,
2955 .ib
= pipeline
->vi
.state_ib
,
2957 draw_state_groups
[draw_state_group_count
++] =
2958 (struct tu_draw_state_group
) {
2959 .id
= TU_DRAW_STATE_VI_BINNING
,
2960 .enable_mask
= CP_SET_DRAW_STATE__0_BINNING
,
2961 .ib
= pipeline
->vi
.binning_state_ib
,
2963 draw_state_groups
[draw_state_group_count
++] =
2964 (struct tu_draw_state_group
) {
2965 .id
= TU_DRAW_STATE_VP
,
2966 .enable_mask
= ENABLE_ALL
,
2967 .ib
= pipeline
->vp
.state_ib
,
2969 draw_state_groups
[draw_state_group_count
++] =
2970 (struct tu_draw_state_group
) {
2971 .id
= TU_DRAW_STATE_RAST
,
2972 .enable_mask
= ENABLE_ALL
,
2973 .ib
= pipeline
->rast
.state_ib
,
2975 draw_state_groups
[draw_state_group_count
++] =
2976 (struct tu_draw_state_group
) {
2977 .id
= TU_DRAW_STATE_DS
,
2978 .enable_mask
= ENABLE_ALL
,
2979 .ib
= pipeline
->ds
.state_ib
,
2981 draw_state_groups
[draw_state_group_count
++] =
2982 (struct tu_draw_state_group
) {
2983 .id
= TU_DRAW_STATE_BLEND
,
2984 .enable_mask
= ENABLE_ALL
,
2985 .ib
= pipeline
->blend
.state_ib
,
2989 if (cmd
->state
.dirty
&
2990 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DESCRIPTOR_SETS
| TU_CMD_DIRTY_PUSH_CONSTANTS
)) {
2991 draw_state_groups
[draw_state_group_count
++] =
2992 (struct tu_draw_state_group
) {
2993 .id
= TU_DRAW_STATE_VS_CONST
,
2994 .enable_mask
= ENABLE_ALL
,
2995 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
)
2997 draw_state_groups
[draw_state_group_count
++] =
2998 (struct tu_draw_state_group
) {
2999 .id
= TU_DRAW_STATE_GS_CONST
,
3000 .enable_mask
= ENABLE_ALL
,
3001 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_GEOMETRY
)
3003 draw_state_groups
[draw_state_group_count
++] =
3004 (struct tu_draw_state_group
) {
3005 .id
= TU_DRAW_STATE_FS_CONST
,
3006 .enable_mask
= ENABLE_DRAW
,
3007 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
)
3011 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) {
3012 draw_state_groups
[draw_state_group_count
++] =
3013 (struct tu_draw_state_group
) {
3014 .id
= TU_DRAW_STATE_VB
,
3015 .enable_mask
= ENABLE_ALL
,
3016 .ib
= tu6_emit_vertex_buffers(cmd
, pipeline
)
3020 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
)
3021 tu6_emit_streamout(cmd
, cs
);
3023 /* If there are any any dynamic descriptors, then we may need to re-emit
3024 * them after every pipeline change in case the number of input attachments
3025 * changes. We also always need to re-emit after a pipeline change if there
3026 * are any input attachments, because the input attachment index comes from
3027 * the pipeline. Finally, it can also happen that the subpass changes
3028 * without the pipeline changing, in which case the GMEM descriptors need
3029 * to be patched differently.
3031 * TODO: We could probably be clever and avoid re-emitting state on
3032 * pipeline changes if the number of input attachments is always 0. We
3033 * could also only re-emit dynamic state.
3035 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
||
3036 ((pipeline
->layout
->dynamic_offset_count
+
3037 pipeline
->layout
->input_attachment_count
> 0) &&
3038 cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) ||
3039 (pipeline
->layout
->input_attachment_count
> 0 &&
3040 cmd
->state
.dirty
& TU_CMD_DIRTY_INPUT_ATTACHMENTS
)) {
3041 struct tu_cs_entry desc_sets
, desc_sets_gmem
;
3042 bool need_gmem_desc_set
= pipeline
->layout
->input_attachment_count
> 0;
3044 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3045 VK_PIPELINE_BIND_POINT_GRAPHICS
,
3047 if (result
!= VK_SUCCESS
)
3050 draw_state_groups
[draw_state_group_count
++] =
3051 (struct tu_draw_state_group
) {
3052 .id
= TU_DRAW_STATE_DESC_SETS
,
3053 .enable_mask
= need_gmem_desc_set
? ENABLE_NON_GMEM
: ENABLE_ALL
,
3057 if (need_gmem_desc_set
) {
3058 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3059 VK_PIPELINE_BIND_POINT_GRAPHICS
,
3060 &desc_sets_gmem
, true);
3061 if (result
!= VK_SUCCESS
)
3064 draw_state_groups
[draw_state_group_count
++] =
3065 (struct tu_draw_state_group
) {
3066 .id
= TU_DRAW_STATE_DESC_SETS_GMEM
,
3067 .enable_mask
= CP_SET_DRAW_STATE__0_GMEM
,
3068 .ib
= desc_sets_gmem
,
3072 /* We need to reload the descriptors every time the descriptor sets
3073 * change. However, the commands we send only depend on the pipeline
3074 * because the whole point is to cache descriptors which are used by the
3075 * pipeline. There's a problem here, in that the firmware has an
3076 * "optimization" which skips executing groups that are set to the same
3077 * value as the last draw. This means that if the descriptor sets change
3078 * but not the pipeline, we'd try to re-execute the same buffer which
3079 * the firmware would ignore and we wouldn't pre-load the new
3080 * descriptors. The blob seems to re-emit the LOAD_STATE group whenever
3081 * the descriptor sets change, which we emulate here by copying the
3082 * pre-prepared buffer.
3084 const struct tu_cs_entry
*load_entry
= &pipeline
->load_state
.state_ib
;
3085 if (load_entry
->size
> 0) {
3086 struct tu_cs load_cs
;
3087 result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, load_entry
->size
, &load_cs
);
3088 if (result
!= VK_SUCCESS
)
3090 tu_cs_emit_array(&load_cs
,
3091 (uint32_t *)((char *)load_entry
->bo
->map
+ load_entry
->offset
),
3092 load_entry
->size
/ 4);
3093 struct tu_cs_entry load_copy
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &load_cs
);
3095 draw_state_groups
[draw_state_group_count
++] =
3096 (struct tu_draw_state_group
) {
3097 .id
= TU_DRAW_STATE_DESC_SETS_LOAD
,
3098 /* The blob seems to not enable this for binning, even when
3099 * resources would actually be used in the binning shader.
3100 * Presumably the overhead of prefetching the resources isn't
3103 .enable_mask
= ENABLE_DRAW
,
3109 struct tu_cs_entry vs_params
;
3110 result
= tu6_emit_vs_params(cmd
, draw
, &vs_params
);
3111 if (result
!= VK_SUCCESS
)
3114 draw_state_groups
[draw_state_group_count
++] =
3115 (struct tu_draw_state_group
) {
3116 .id
= TU_DRAW_STATE_VS_PARAMS
,
3117 .enable_mask
= ENABLE_ALL
,
3121 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_group_count
);
3122 for (uint32_t i
= 0; i
< draw_state_group_count
; i
++) {
3123 const struct tu_draw_state_group
*group
= &draw_state_groups
[i
];
3124 debug_assert((group
->enable_mask
& ~ENABLE_ALL
) == 0);
3125 uint32_t cp_set_draw_state
=
3126 CP_SET_DRAW_STATE__0_COUNT(group
->ib
.size
/ 4) |
3127 group
->enable_mask
|
3128 CP_SET_DRAW_STATE__0_GROUP_ID(group
->id
);
3130 if (group
->ib
.size
) {
3131 iova
= group
->ib
.bo
->iova
+ group
->ib
.offset
;
3133 cp_set_draw_state
|= CP_SET_DRAW_STATE__0_DISABLE
;
3137 tu_cs_emit(cs
, cp_set_draw_state
);
3138 tu_cs_emit_qw(cs
, iova
);
3141 tu_cs_sanity_check(cs
);
3144 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) {
3146 for_each_bit(i
, descriptors_state
->valid
) {
3147 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3148 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
3149 if (set
->buffers
[j
]) {
3150 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
3151 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3154 if (set
->size
> 0) {
3155 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
3156 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3160 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
) {
3161 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3162 const struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
3164 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
,
3165 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3170 /* There are too many graphics dirty bits to list here, so just list the
3171 * bits to preserve instead. The only things not emitted here are
3172 * compute-related state.
3174 cmd
->state
.dirty
&= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
;
3176 /* Fragment shader state overwrites compute shader state, so flag the
3177 * compute pipeline for re-emit.
3179 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
3184 tu6_emit_draw_indirect(struct tu_cmd_buffer
*cmd
,
3186 const struct tu_draw_info
*draw
)
3188 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3189 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3190 VK_SHADER_STAGE_GEOMETRY_BIT
;
3193 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3194 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3196 if (draw
->indexed
) {
3197 const enum a4xx_index_size index_size
=
3198 tu6_index_size(cmd
->state
.index_type
);
3199 const uint32_t index_bytes
=
3200 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3201 const struct tu_buffer
*index_buf
= cmd
->state
.index_buffer
;
3202 unsigned max_indicies
=
3203 (index_buf
->size
- cmd
->state
.index_offset
) / index_bytes
;
3205 const uint32_t cp_draw_indx
=
3206 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3207 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3208 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3209 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3210 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3212 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_INDIRECT
, 6);
3213 tu_cs_emit(cs
, cp_draw_indx
);
3214 tu_cs_emit_qw(cs
, index_buf
->bo
->iova
+ cmd
->state
.index_offset
);
3215 tu_cs_emit(cs
, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies
));
3216 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3218 const uint32_t cp_draw_indx
=
3219 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3220 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3221 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3222 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3224 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT
, 3);
3225 tu_cs_emit(cs
, cp_draw_indx
);
3226 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3229 tu_bo_list_add(&cmd
->bo_list
, draw
->indirect
->bo
, MSM_SUBMIT_BO_READ
);
3233 tu6_emit_draw_direct(struct tu_cmd_buffer
*cmd
,
3235 const struct tu_draw_info
*draw
)
3238 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3239 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3240 VK_SHADER_STAGE_GEOMETRY_BIT
;
3243 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3244 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3246 /* TODO hw binning */
3247 if (draw
->indexed
) {
3248 const enum a4xx_index_size index_size
=
3249 tu6_index_size(cmd
->state
.index_type
);
3250 const uint32_t index_bytes
=
3251 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3252 const struct tu_buffer
*buf
= cmd
->state
.index_buffer
;
3253 const VkDeviceSize offset
= buf
->bo_offset
+ cmd
->state
.index_offset
+
3254 index_bytes
* draw
->first_index
;
3255 const uint32_t size
= index_bytes
* draw
->count
;
3257 const uint32_t cp_draw_indx
=
3258 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3259 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3260 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3261 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3262 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3264 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3265 tu_cs_emit(cs
, cp_draw_indx
);
3266 tu_cs_emit(cs
, draw
->instance_count
);
3267 tu_cs_emit(cs
, draw
->count
);
3268 tu_cs_emit(cs
, 0x0); /* XXX */
3269 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ offset
);
3270 tu_cs_emit(cs
, size
);
3272 const uint32_t cp_draw_indx
=
3273 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3274 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3275 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3276 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3278 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3279 tu_cs_emit(cs
, cp_draw_indx
);
3280 tu_cs_emit(cs
, draw
->instance_count
);
3281 tu_cs_emit(cs
, draw
->count
);
3286 tu_draw(struct tu_cmd_buffer
*cmd
, const struct tu_draw_info
*draw
)
3288 struct tu_cs
*cs
= &cmd
->draw_cs
;
3291 result
= tu6_bind_draw_states(cmd
, cs
, draw
);
3292 if (result
!= VK_SUCCESS
) {
3293 cmd
->record_result
= result
;
3298 tu6_emit_draw_indirect(cmd
, cs
, draw
);
3300 tu6_emit_draw_direct(cmd
, cs
, draw
);
3302 if (cmd
->state
.streamout_enabled
) {
3303 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3304 if (cmd
->state
.streamout_enabled
& (1 << i
))
3305 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
);
3309 cmd
->wait_for_idle
= true;
3311 tu_cs_sanity_check(cs
);
3315 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3316 uint32_t vertexCount
,
3317 uint32_t instanceCount
,
3318 uint32_t firstVertex
,
3319 uint32_t firstInstance
)
3321 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3322 struct tu_draw_info info
= {};
3324 info
.count
= vertexCount
;
3325 info
.instance_count
= instanceCount
;
3326 info
.first_instance
= firstInstance
;
3327 info
.vertex_offset
= firstVertex
;
3329 tu_draw(cmd_buffer
, &info
);
3333 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3334 uint32_t indexCount
,
3335 uint32_t instanceCount
,
3336 uint32_t firstIndex
,
3337 int32_t vertexOffset
,
3338 uint32_t firstInstance
)
3340 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3341 struct tu_draw_info info
= {};
3343 info
.indexed
= true;
3344 info
.count
= indexCount
;
3345 info
.instance_count
= instanceCount
;
3346 info
.first_index
= firstIndex
;
3347 info
.vertex_offset
= vertexOffset
;
3348 info
.first_instance
= firstInstance
;
3350 tu_draw(cmd_buffer
, &info
);
3354 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3356 VkDeviceSize offset
,
3360 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3361 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3362 struct tu_draw_info info
= {};
3364 info
.count
= drawCount
;
3365 info
.indirect
= buffer
;
3366 info
.indirect_offset
= offset
;
3367 info
.stride
= stride
;
3369 tu_draw(cmd_buffer
, &info
);
3373 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3375 VkDeviceSize offset
,
3379 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3380 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3381 struct tu_draw_info info
= {};
3383 info
.indexed
= true;
3384 info
.count
= drawCount
;
3385 info
.indirect
= buffer
;
3386 info
.indirect_offset
= offset
;
3387 info
.stride
= stride
;
3389 tu_draw(cmd_buffer
, &info
);
3392 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3393 uint32_t instanceCount
,
3394 uint32_t firstInstance
,
3395 VkBuffer _counterBuffer
,
3396 VkDeviceSize counterBufferOffset
,
3397 uint32_t counterOffset
,
3398 uint32_t vertexStride
)
3400 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3401 TU_FROM_HANDLE(tu_buffer
, buffer
, _counterBuffer
);
3403 struct tu_draw_info info
= {};
3405 info
.instance_count
= instanceCount
;
3406 info
.first_instance
= firstInstance
;
3407 info
.streamout_buffer
= buffer
;
3408 info
.streamout_buffer_offset
= counterBufferOffset
;
3409 info
.stride
= vertexStride
;
3411 tu_draw(cmd_buffer
, &info
);
3414 struct tu_dispatch_info
3417 * Determine the layout of the grid (in block units) to be used.
3422 * A starting offset for the grid. If unaligned is set, the offset
3423 * must still be aligned.
3425 uint32_t offsets
[3];
3427 * Whether it's an unaligned compute dispatch.
3432 * Indirect compute parameters resource.
3434 struct tu_buffer
*indirect
;
3435 uint64_t indirect_offset
;
3439 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3440 const struct tu_dispatch_info
*info
)
3442 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3443 const struct tu_program_descriptor_linkage
*link
=
3444 &pipeline
->program
.link
[type
];
3445 const struct ir3_const_state
*const_state
= &link
->const_state
;
3446 uint32_t offset
= const_state
->offsets
.driver_param
;
3448 if (link
->constlen
<= offset
)
3451 if (!info
->indirect
) {
3452 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3453 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3454 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3455 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3456 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3457 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3458 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3461 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3462 (link
->constlen
- offset
) * 4);
3463 /* push constants */
3464 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3465 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3466 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3467 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3468 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3469 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3473 for (i
= 0; i
< num_consts
; i
++)
3474 tu_cs_emit(cs
, driver_params
[i
]);
3476 tu_finishme("Indirect driver params");
3481 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3482 const struct tu_dispatch_info
*info
)
3484 struct tu_cs
*cs
= &cmd
->cs
;
3485 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3486 struct tu_descriptor_state
*descriptors_state
=
3487 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3490 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_PIPELINE
)
3491 tu_cs_emit_ib(cs
, &pipeline
->program
.state_ib
);
3493 struct tu_cs_entry ib
;
3495 ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
);
3497 tu_cs_emit_ib(cs
, &ib
);
3499 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3501 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
) {
3502 result
= tu6_emit_descriptor_sets(cmd
, pipeline
,
3503 VK_PIPELINE_BIND_POINT_COMPUTE
, &ib
,
3505 if (result
!= VK_SUCCESS
) {
3506 cmd
->record_result
= result
;
3512 for_each_bit(i
, descriptors_state
->valid
) {
3513 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
3514 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
3515 if (set
->buffers
[j
]) {
3516 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
3517 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3521 if (set
->size
> 0) {
3522 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
3523 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3529 tu_cs_emit_ib(cs
, &ib
);
3531 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
)
3532 tu_cs_emit_ib(cs
, &pipeline
->load_state
.state_ib
);
3535 ~(TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
| TU_CMD_DIRTY_COMPUTE_PIPELINE
);
3537 /* Compute shader state overwrites fragment shader state, so we flag the
3538 * graphics pipeline for re-emit.
3540 cmd
->state
.dirty
|= TU_CMD_DIRTY_PIPELINE
;
3542 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3543 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3545 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3546 const uint32_t *num_groups
= info
->blocks
;
3548 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3549 .localsizex
= local_size
[0] - 1,
3550 .localsizey
= local_size
[1] - 1,
3551 .localsizez
= local_size
[2] - 1),
3552 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3553 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3554 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3555 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3556 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3557 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3560 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3561 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3562 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3564 if (info
->indirect
) {
3565 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3567 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3568 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3570 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3571 tu_cs_emit(cs
, 0x00000000);
3572 tu_cs_emit_qw(cs
, iova
);
3574 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3575 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3576 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3578 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3579 tu_cs_emit(cs
, 0x00000000);
3580 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3581 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3582 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3587 tu6_emit_cache_flush(cmd
, cs
);
3591 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3599 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3600 struct tu_dispatch_info info
= {};
3606 info
.offsets
[0] = base_x
;
3607 info
.offsets
[1] = base_y
;
3608 info
.offsets
[2] = base_z
;
3609 tu_dispatch(cmd_buffer
, &info
);
3613 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3618 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3622 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3624 VkDeviceSize offset
)
3626 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3627 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3628 struct tu_dispatch_info info
= {};
3630 info
.indirect
= buffer
;
3631 info
.indirect_offset
= offset
;
3633 tu_dispatch(cmd_buffer
, &info
);
3637 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3639 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3641 tu_cs_end(&cmd_buffer
->draw_cs
);
3642 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3644 if (use_sysmem_rendering(cmd_buffer
))
3645 tu_cmd_render_sysmem(cmd_buffer
);
3647 tu_cmd_render_tiles(cmd_buffer
);
3649 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3651 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3652 tu_cs_begin(&cmd_buffer
->draw_cs
);
3653 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3654 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3656 cmd_buffer
->state
.pass
= NULL
;
3657 cmd_buffer
->state
.subpass
= NULL
;
3658 cmd_buffer
->state
.framebuffer
= NULL
;
3662 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3663 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3665 tu_CmdEndRenderPass(commandBuffer
);
3668 struct tu_barrier_info
3670 uint32_t eventCount
;
3671 const VkEvent
*pEvents
;
3672 VkPipelineStageFlags srcStageMask
;
3676 tu_barrier(struct tu_cmd_buffer
*cmd
,
3677 uint32_t memoryBarrierCount
,
3678 const VkMemoryBarrier
*pMemoryBarriers
,
3679 uint32_t bufferMemoryBarrierCount
,
3680 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3681 uint32_t imageMemoryBarrierCount
,
3682 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3683 const struct tu_barrier_info
*info
)
3685 /* renderpass case is only for subpass self-dependencies
3686 * which means syncing the render output with texture cache
3687 * note: only the CACHE_INVALIDATE is needed in GMEM mode
3688 * and in sysmem mode we might not need either color/depth flush
3690 if (cmd
->state
.pass
) {
3691 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, PC_CCU_FLUSH_COLOR_TS
);
3692 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, PC_CCU_FLUSH_DEPTH_TS
);
3693 tu6_emit_event_write(cmd
, &cmd
->draw_cs
, CACHE_INVALIDATE
);
3699 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3700 VkPipelineStageFlags srcStageMask
,
3701 VkPipelineStageFlags dstStageMask
,
3702 VkDependencyFlags dependencyFlags
,
3703 uint32_t memoryBarrierCount
,
3704 const VkMemoryBarrier
*pMemoryBarriers
,
3705 uint32_t bufferMemoryBarrierCount
,
3706 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3707 uint32_t imageMemoryBarrierCount
,
3708 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3710 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3711 struct tu_barrier_info info
;
3713 info
.eventCount
= 0;
3714 info
.pEvents
= NULL
;
3715 info
.srcStageMask
= srcStageMask
;
3717 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3718 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3719 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3723 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
, unsigned value
)
3725 struct tu_cs
*cs
= &cmd
->cs
;
3727 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3729 /* TODO: any flush required before/after ? */
3731 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3732 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3733 tu_cs_emit(cs
, value
);
3737 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3739 VkPipelineStageFlags stageMask
)
3741 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3742 TU_FROM_HANDLE(tu_event
, event
, _event
);
3744 write_event(cmd
, event
, 1);
3748 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3750 VkPipelineStageFlags stageMask
)
3752 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3753 TU_FROM_HANDLE(tu_event
, event
, _event
);
3755 write_event(cmd
, event
, 0);
3759 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3760 uint32_t eventCount
,
3761 const VkEvent
*pEvents
,
3762 VkPipelineStageFlags srcStageMask
,
3763 VkPipelineStageFlags dstStageMask
,
3764 uint32_t memoryBarrierCount
,
3765 const VkMemoryBarrier
*pMemoryBarriers
,
3766 uint32_t bufferMemoryBarrierCount
,
3767 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3768 uint32_t imageMemoryBarrierCount
,
3769 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3771 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3772 struct tu_cs
*cs
= &cmd
->cs
;
3774 /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
3776 for (uint32_t i
= 0; i
< eventCount
; i
++) {
3777 TU_FROM_HANDLE(tu_event
, event
, pEvents
[i
]);
3779 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3781 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3782 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3783 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3784 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3785 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3786 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3787 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3792 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)