2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
33 #include "vk_format.h"
37 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
40 tu_bo_list_init(struct tu_bo_list
*list
)
42 list
->count
= list
->capacity
= 0;
43 list
->bo_infos
= NULL
;
47 tu_bo_list_destroy(struct tu_bo_list
*list
)
53 tu_bo_list_reset(struct tu_bo_list
*list
)
59 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
62 tu_bo_list_add_info(struct tu_bo_list
*list
,
63 const struct drm_msm_gem_submit_bo
*bo_info
)
65 assert(bo_info
->handle
!= 0);
67 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
68 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
69 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
70 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
75 /* grow list->bo_infos if needed */
76 if (list
->count
== list
->capacity
) {
77 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
78 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
79 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
81 return TU_BO_LIST_FAILED
;
82 list
->bo_infos
= new_bo_infos
;
83 list
->capacity
= new_capacity
;
86 list
->bo_infos
[list
->count
] = *bo_info
;
91 tu_bo_list_add(struct tu_bo_list
*list
,
92 const struct tu_bo
*bo
,
95 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
97 .handle
= bo
->gem_handle
,
103 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
105 for (uint32_t i
= 0; i
< other
->count
; i
++) {
106 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
107 return VK_ERROR_OUT_OF_HOST_MEMORY
;
114 tu_tiling_config_update_tile_layout(struct tu_tiling_config
*tiling
,
115 const struct tu_device
*dev
,
116 const struct tu_render_pass
*pass
)
118 const uint32_t tile_align_w
= pass
->tile_align_w
;
119 const uint32_t max_tile_width
= 1024;
121 /* note: don't offset the tiling config by render_area.offset,
122 * because binning pass can't deal with it
123 * this means we might end up with more tiles than necessary,
124 * but load/store/etc are still scissored to the render_area
126 tiling
->tile0
.offset
= (VkOffset2D
) {};
128 const uint32_t ra_width
=
129 tiling
->render_area
.extent
.width
+
130 (tiling
->render_area
.offset
.x
- tiling
->tile0
.offset
.x
);
131 const uint32_t ra_height
=
132 tiling
->render_area
.extent
.height
+
133 (tiling
->render_area
.offset
.y
- tiling
->tile0
.offset
.y
);
135 /* start from 1 tile */
136 tiling
->tile_count
= (VkExtent2D
) {
140 tiling
->tile0
.extent
= (VkExtent2D
) {
141 .width
= util_align_npot(ra_width
, tile_align_w
),
142 .height
= align(ra_height
, TILE_ALIGN_H
),
145 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
)) {
146 /* start with 2x2 tiles */
147 tiling
->tile_count
.width
= 2;
148 tiling
->tile_count
.height
= 2;
149 tiling
->tile0
.extent
.width
= util_align_npot(DIV_ROUND_UP(ra_width
, 2), tile_align_w
);
150 tiling
->tile0
.extent
.height
= align(DIV_ROUND_UP(ra_height
, 2), TILE_ALIGN_H
);
153 /* do not exceed max tile width */
154 while (tiling
->tile0
.extent
.width
> max_tile_width
) {
155 tiling
->tile_count
.width
++;
156 tiling
->tile0
.extent
.width
=
157 util_align_npot(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
160 /* will force to sysmem, don't bother trying to have a valid tile config
161 * TODO: just skip all GMEM stuff when sysmem is forced?
163 if (!pass
->gmem_pixels
)
166 /* do not exceed gmem size */
167 while (tiling
->tile0
.extent
.width
* tiling
->tile0
.extent
.height
> pass
->gmem_pixels
) {
168 if (tiling
->tile0
.extent
.width
> MAX2(tile_align_w
, tiling
->tile0
.extent
.height
)) {
169 tiling
->tile_count
.width
++;
170 tiling
->tile0
.extent
.width
=
171 util_align_npot(DIV_ROUND_UP(ra_width
, tiling
->tile_count
.width
), tile_align_w
);
173 /* if this assert fails then layout is impossible.. */
174 assert(tiling
->tile0
.extent
.height
> TILE_ALIGN_H
);
175 tiling
->tile_count
.height
++;
176 tiling
->tile0
.extent
.height
=
177 align(DIV_ROUND_UP(ra_height
, tiling
->tile_count
.height
), TILE_ALIGN_H
);
183 tu_tiling_config_update_pipe_layout(struct tu_tiling_config
*tiling
,
184 const struct tu_device
*dev
)
186 const uint32_t max_pipe_count
= 32; /* A6xx */
188 /* start from 1 tile per pipe */
189 tiling
->pipe0
= (VkExtent2D
) {
193 tiling
->pipe_count
= tiling
->tile_count
;
195 while (tiling
->pipe_count
.width
* tiling
->pipe_count
.height
> max_pipe_count
) {
196 if (tiling
->pipe0
.width
< tiling
->pipe0
.height
) {
197 tiling
->pipe0
.width
+= 1;
198 tiling
->pipe_count
.width
=
199 DIV_ROUND_UP(tiling
->tile_count
.width
, tiling
->pipe0
.width
);
201 tiling
->pipe0
.height
+= 1;
202 tiling
->pipe_count
.height
=
203 DIV_ROUND_UP(tiling
->tile_count
.height
, tiling
->pipe0
.height
);
209 tu_tiling_config_update_pipes(struct tu_tiling_config
*tiling
,
210 const struct tu_device
*dev
)
212 const uint32_t max_pipe_count
= 32; /* A6xx */
213 const uint32_t used_pipe_count
=
214 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
215 const VkExtent2D last_pipe
= {
216 .width
= (tiling
->tile_count
.width
- 1) % tiling
->pipe0
.width
+ 1,
217 .height
= (tiling
->tile_count
.height
- 1) % tiling
->pipe0
.height
+ 1,
220 assert(used_pipe_count
<= max_pipe_count
);
221 assert(max_pipe_count
<= ARRAY_SIZE(tiling
->pipe_config
));
223 for (uint32_t y
= 0; y
< tiling
->pipe_count
.height
; y
++) {
224 for (uint32_t x
= 0; x
< tiling
->pipe_count
.width
; x
++) {
225 const uint32_t pipe_x
= tiling
->pipe0
.width
* x
;
226 const uint32_t pipe_y
= tiling
->pipe0
.height
* y
;
227 const uint32_t pipe_w
= (x
== tiling
->pipe_count
.width
- 1)
229 : tiling
->pipe0
.width
;
230 const uint32_t pipe_h
= (y
== tiling
->pipe_count
.height
- 1)
232 : tiling
->pipe0
.height
;
233 const uint32_t n
= tiling
->pipe_count
.width
* y
+ x
;
235 tiling
->pipe_config
[n
] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x
) |
236 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y
) |
237 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w
) |
238 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h
);
239 tiling
->pipe_sizes
[n
] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w
* pipe_h
);
243 memset(tiling
->pipe_config
+ used_pipe_count
, 0,
244 sizeof(uint32_t) * (max_pipe_count
- used_pipe_count
));
248 tu_tiling_config_get_tile(const struct tu_tiling_config
*tiling
,
249 const struct tu_device
*dev
,
252 struct tu_tile
*tile
)
254 /* find the pipe and the slot for tile (tx, ty) */
255 const uint32_t px
= tx
/ tiling
->pipe0
.width
;
256 const uint32_t py
= ty
/ tiling
->pipe0
.height
;
257 const uint32_t sx
= tx
- tiling
->pipe0
.width
* px
;
258 const uint32_t sy
= ty
- tiling
->pipe0
.height
* py
;
259 /* last pipe has different width */
260 const uint32_t pipe_width
=
261 MIN2(tiling
->pipe0
.width
,
262 tiling
->tile_count
.width
- px
* tiling
->pipe0
.width
);
264 assert(tx
< tiling
->tile_count
.width
&& ty
< tiling
->tile_count
.height
);
265 assert(px
< tiling
->pipe_count
.width
&& py
< tiling
->pipe_count
.height
);
266 assert(sx
< tiling
->pipe0
.width
&& sy
< tiling
->pipe0
.height
);
268 /* convert to 1D indices */
269 tile
->pipe
= tiling
->pipe_count
.width
* py
+ px
;
270 tile
->slot
= pipe_width
* sy
+ sx
;
272 /* get the blit area for the tile */
273 tile
->begin
= (VkOffset2D
) {
274 .x
= tiling
->tile0
.offset
.x
+ tiling
->tile0
.extent
.width
* tx
,
275 .y
= tiling
->tile0
.offset
.y
+ tiling
->tile0
.extent
.height
* ty
,
278 (tx
== tiling
->tile_count
.width
- 1)
279 ? tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
280 : tile
->begin
.x
+ tiling
->tile0
.extent
.width
;
282 (ty
== tiling
->tile_count
.height
- 1)
283 ? tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
284 : tile
->begin
.y
+ tiling
->tile0
.extent
.height
;
287 enum a3xx_msaa_samples
288 tu_msaa_samples(uint32_t samples
)
300 assert(!"invalid sample count");
305 static enum a4xx_index_size
306 tu6_index_size(VkIndexType type
)
309 case VK_INDEX_TYPE_UINT16
:
310 return INDEX4_SIZE_16_BIT
;
311 case VK_INDEX_TYPE_UINT32
:
312 return INDEX4_SIZE_32_BIT
;
314 unreachable("invalid VkIndexType");
315 return INDEX4_SIZE_8_BIT
;
320 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
322 enum vgt_event_type event
)
324 bool need_seqno
= false;
329 case PC_CCU_FLUSH_DEPTH_TS
:
330 case PC_CCU_FLUSH_COLOR_TS
:
331 case PC_CCU_RESOLVE_TS
:
338 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
339 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
341 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
347 tu6_emit_flushes(struct tu_cmd_buffer
*cmd_buffer
,
349 enum tu_cmd_flush_bits flushes
)
351 /* Experiments show that invalidating CCU while it still has data in it
352 * doesn't work, so make sure to always flush before invalidating in case
353 * any data remains that hasn't yet been made available through a barrier.
354 * However it does seem to work for UCHE.
356 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_COLOR
|
357 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
))
358 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_COLOR_TS
);
359 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
360 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
))
361 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_DEPTH_TS
);
362 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_COLOR
)
363 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_COLOR
);
364 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
)
365 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_DEPTH
);
366 if (flushes
& TU_CMD_FLAG_CACHE_FLUSH
)
367 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_FLUSH_TS
);
368 if (flushes
& TU_CMD_FLAG_CACHE_INVALIDATE
)
369 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_INVALIDATE
);
370 if (flushes
& TU_CMD_FLAG_WFI
)
374 /* "Normal" cache flushes, that don't require any special handling */
377 tu_emit_cache_flush(struct tu_cmd_buffer
*cmd_buffer
,
380 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.cache
.flush_bits
);
381 cmd_buffer
->state
.cache
.flush_bits
= 0;
384 /* Renderpass cache flushes */
387 tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
390 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.renderpass_cache
.flush_bits
);
391 cmd_buffer
->state
.renderpass_cache
.flush_bits
= 0;
394 /* Cache flushes for things that use the color/depth read/write path (i.e.
395 * blits and draws). This deals with changing CCU state as well as the usual
400 tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
402 enum tu_cmd_ccu_state ccu_state
)
404 enum tu_cmd_flush_bits flushes
= cmd_buffer
->state
.cache
.flush_bits
;
406 assert(ccu_state
!= TU_CMD_CCU_UNKNOWN
);
408 /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
409 * the CCU may also contain data that we haven't flushed out yet, so we
410 * also need to flush. Also, in order to program RB_CCU_CNTL, we need to
411 * emit a WFI as it isn't pipelined.
413 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
414 if (cmd_buffer
->state
.ccu_state
!= TU_CMD_CCU_GMEM
) {
416 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
417 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
418 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
419 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
420 TU_CMD_FLAG_CCU_FLUSH_DEPTH
);
423 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
424 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
426 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
427 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
428 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
);
431 tu6_emit_flushes(cmd_buffer
, cs
, flushes
);
432 cmd_buffer
->state
.cache
.flush_bits
= 0;
434 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
435 struct tu_physical_device
*phys_dev
= cmd_buffer
->device
->physical_device
;
437 A6XX_RB_CCU_CNTL(.offset
=
438 ccu_state
== TU_CMD_CCU_GMEM
?
439 phys_dev
->ccu_offset_gmem
:
440 phys_dev
->ccu_offset_bypass
,
441 .gmem
= ccu_state
== TU_CMD_CCU_GMEM
));
442 cmd_buffer
->state
.ccu_state
= ccu_state
;
447 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
448 const struct tu_subpass
*subpass
,
451 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
453 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
454 if (a
== VK_ATTACHMENT_UNUSED
) {
456 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
457 A6XX_RB_DEPTH_BUFFER_PITCH(0),
458 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
459 A6XX_RB_DEPTH_BUFFER_BASE(0),
460 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
463 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
466 A6XX_GRAS_LRZ_BUFFER_BASE(0),
467 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
468 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
470 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
475 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
476 const struct tu_render_pass_attachment
*attachment
=
477 &cmd
->state
.pass
->attachments
[a
];
478 enum a6xx_depth_format fmt
= tu6_pipe2depth(attachment
->format
);
480 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
481 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
).value
);
482 tu_cs_image_ref(cs
, iview
, 0);
483 tu_cs_emit(cs
, attachment
->gmem_offset
);
486 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
488 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
489 tu_cs_image_flag_ref(cs
, iview
, 0);
492 A6XX_GRAS_LRZ_BUFFER_BASE(0),
493 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
494 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
496 if (attachment
->format
== VK_FORMAT_S8_UINT
) {
497 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 6);
498 tu_cs_emit(cs
, A6XX_RB_STENCIL_INFO(.separate_stencil
= true).value
);
499 tu_cs_image_ref(cs
, iview
, 0);
500 tu_cs_emit(cs
, attachment
->gmem_offset
);
503 A6XX_RB_STENCIL_INFO(0));
508 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
509 const struct tu_subpass
*subpass
,
512 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
514 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
515 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
516 if (a
== VK_ATTACHMENT_UNUSED
)
519 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
521 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
522 tu_cs_emit(cs
, iview
->RB_MRT_BUF_INFO
);
523 tu_cs_image_ref(cs
, iview
, 0);
524 tu_cs_emit(cs
, cmd
->state
.pass
->attachments
[a
].gmem_offset
);
527 A6XX_SP_FS_MRT_REG(i
, .dword
= iview
->SP_FS_MRT_REG
));
529 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i
), 3);
530 tu_cs_image_flag_ref(cs
, iview
, 0);
534 A6XX_RB_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
536 A6XX_SP_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
538 tu_cs_emit_regs(cs
, A6XX_GRAS_MAX_LAYER_INDEX(fb
->layers
- 1));
542 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
544 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
545 bool msaa_disable
= samples
== MSAA_ONE
;
548 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
549 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
550 .msaa_disable
= msaa_disable
));
553 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
554 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
555 .msaa_disable
= msaa_disable
));
558 A6XX_RB_RAS_MSAA_CNTL(samples
),
559 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
560 .msaa_disable
= msaa_disable
));
563 A6XX_RB_MSAA_CNTL(samples
));
567 tu6_emit_bin_size(struct tu_cs
*cs
,
568 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
571 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
576 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
580 /* no flag for RB_BIN_CONTROL2... */
582 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
587 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
588 const struct tu_subpass
*subpass
,
592 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
594 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
596 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
598 uint32_t mrts_ubwc_enable
= 0;
599 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
600 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
601 if (a
== VK_ATTACHMENT_UNUSED
)
604 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
605 if (iview
->ubwc_enabled
)
606 mrts_ubwc_enable
|= 1 << i
;
609 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
611 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
612 if (a
!= VK_ATTACHMENT_UNUSED
) {
613 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
614 if (iview
->ubwc_enabled
)
615 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
618 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
619 * in order to set it correctly for the different subpasses. However,
620 * that means the packets we're emitting also happen during binning. So
621 * we need to guard the write on !BINNING at CP execution time.
623 tu_cs_reserve(cs
, 3 + 4);
624 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
625 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
626 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
627 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
630 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
631 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
632 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
633 tu_cs_emit(cs
, cntl
);
637 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
639 const VkRect2D
*render_area
= &cmd
->state
.tiling_config
.render_area
;
640 uint32_t x1
= render_area
->offset
.x
;
641 uint32_t y1
= render_area
->offset
.y
;
642 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
643 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
646 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
647 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
648 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
649 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
653 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
654 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
658 tu6_emit_window_scissor(struct tu_cs
*cs
,
665 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
666 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
669 A6XX_GRAS_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
670 A6XX_GRAS_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
674 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
677 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
680 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
683 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
686 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
690 tu_cs_emit_draw_state(struct tu_cs
*cs
, uint32_t id
, struct tu_draw_state state
)
692 uint32_t enable_mask
;
694 case TU_DRAW_STATE_PROGRAM
:
695 case TU_DRAW_STATE_VI
:
696 case TU_DRAW_STATE_FS_CONST
:
697 /* The blob seems to not enable this (DESC_SETS_LOAD) for binning, even
698 * when resources would actually be used in the binning shader.
699 * Presumably the overhead of prefetching the resources isn't
702 case TU_DRAW_STATE_DESC_SETS_LOAD
:
703 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
704 CP_SET_DRAW_STATE__0_SYSMEM
;
706 case TU_DRAW_STATE_PROGRAM_BINNING
:
707 case TU_DRAW_STATE_VI_BINNING
:
708 enable_mask
= CP_SET_DRAW_STATE__0_BINNING
;
710 case TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
:
711 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
;
713 case TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
:
714 enable_mask
= CP_SET_DRAW_STATE__0_SYSMEM
;
717 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
718 CP_SET_DRAW_STATE__0_SYSMEM
|
719 CP_SET_DRAW_STATE__0_BINNING
;
723 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(state
.size
) |
725 CP_SET_DRAW_STATE__0_GROUP_ID(id
) |
726 COND(!state
.size
, CP_SET_DRAW_STATE__0_DISABLE
));
727 tu_cs_emit_qw(cs
, state
.iova
);
730 /* note: get rid of this eventually */
732 tu_cs_emit_sds_ib(struct tu_cs
*cs
, uint32_t id
, struct tu_cs_entry entry
)
734 tu_cs_emit_draw_state(cs
, id
, (struct tu_draw_state
) {
735 .iova
= entry
.size
? entry
.bo
->iova
+ entry
.offset
: 0,
736 .size
= entry
.size
/ 4,
741 use_hw_binning(struct tu_cmd_buffer
*cmd
)
743 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
745 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
748 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
751 return (tiling
->tile_count
.width
* tiling
->tile_count
.height
) > 2;
755 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
757 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
760 /* can't fit attachments into gmem */
761 if (!cmd
->state
.pass
->gmem_pixels
)
764 if (cmd
->state
.framebuffer
->layers
> 1)
767 return cmd
->state
.tiling_config
.force_sysmem
;
771 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
773 const struct tu_tile
*tile
)
775 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
776 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
778 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
779 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
781 const uint32_t x1
= tile
->begin
.x
;
782 const uint32_t y1
= tile
->begin
.y
;
783 const uint32_t x2
= tile
->end
.x
- 1;
784 const uint32_t y2
= tile
->end
.y
- 1;
785 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
786 tu6_emit_window_offset(cs
, x1
, y1
);
789 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
791 if (use_hw_binning(cmd
)) {
792 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
794 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
797 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
798 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
799 A6XX_CP_REG_TEST_0_BIT(0) |
800 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
802 tu_cs_reserve(cs
, 3 + 11);
803 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
804 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
805 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(11));
807 /* if (no overflow) */ {
808 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5
, 7);
809 tu_cs_emit(cs
, cmd
->state
.tiling_config
.pipe_sizes
[tile
->pipe
] |
810 CP_SET_BIN_DATA5_0_VSC_N(tile
->slot
));
811 tu_cs_emit_qw(cs
, cmd
->vsc_draw_strm
.iova
+ tile
->pipe
* cmd
->vsc_draw_strm_pitch
);
812 tu_cs_emit_qw(cs
, cmd
->vsc_draw_strm
.iova
+ (tile
->pipe
* 4) + (32 * cmd
->vsc_draw_strm_pitch
));
813 tu_cs_emit_qw(cs
, cmd
->vsc_prim_strm
.iova
+ (tile
->pipe
* cmd
->vsc_prim_strm_pitch
));
815 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
818 /* use a NOP packet to skip over the 'else' side: */
819 tu_cs_emit_pkt7(cs
, CP_NOP
, 2);
821 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
825 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
828 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
831 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
837 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
842 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
843 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
844 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
846 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.tiling_config
.render_area
);
850 tu6_emit_sysmem_resolves(struct tu_cmd_buffer
*cmd
,
852 const struct tu_subpass
*subpass
)
854 if (subpass
->resolve_attachments
) {
855 /* From the documentation for vkCmdNextSubpass, section 7.4 "Render Pass
858 * End-of-subpass multisample resolves are treated as color
859 * attachment writes for the purposes of synchronization. That is,
860 * they are considered to execute in the
861 * VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage and
862 * their writes are synchronized with
863 * VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT. Synchronization between
864 * rendering within a subpass and any resolve operations at the end
865 * of the subpass occurs automatically, without need for explicit
866 * dependencies or pipeline barriers. However, if the resolve
867 * attachment is also used in a different subpass, an explicit
868 * dependency is needed.
870 * We use the CP_BLIT path for sysmem resolves, which is really a
871 * transfer command, so we have to manually flush similar to the gmem
872 * resolve case. However, a flush afterwards isn't needed because of the
873 * last sentence and the fact that we're in sysmem mode.
875 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
);
876 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
878 /* Wait for the flushes to land before using the 2D engine */
881 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
882 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
883 if (a
== VK_ATTACHMENT_UNUSED
)
886 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
887 subpass
->color_attachments
[i
].attachment
);
893 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
895 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
896 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
898 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
899 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
900 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
901 CP_SET_DRAW_STATE__0_GROUP_ID(0));
902 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
903 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
905 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
908 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
909 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
911 tu6_emit_blit_scissor(cmd
, cs
, true);
913 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
914 if (pass
->attachments
[a
].gmem_offset
>= 0)
915 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
918 if (subpass
->resolve_attachments
) {
919 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
920 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
921 if (a
!= VK_ATTACHMENT_UNUSED
)
922 tu_store_gmem_attachment(cmd
, cs
, a
,
923 subpass
->color_attachments
[i
].attachment
);
929 tu6_emit_restart_index(struct tu_cs
*cs
, uint32_t restart_index
)
932 A6XX_PC_RESTART_INDEX(restart_index
));
936 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
938 const struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
940 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
942 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 0xfffff);
945 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
946 cmd
->state
.ccu_state
= TU_CMD_CCU_SYSMEM
;
947 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
948 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
949 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
950 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
951 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
952 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
953 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
954 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
956 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
957 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
958 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
959 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
960 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
961 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
962 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BB11
, 0);
963 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
964 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
965 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
966 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
967 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
968 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
969 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_GS_SIV_CNTL
, 0x0000ffff);
971 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
972 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
973 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
975 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
977 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
979 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
980 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
981 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
982 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
983 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
984 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
985 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
986 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
987 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
988 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
989 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
991 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9101
, 0xffff00);
992 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
994 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9236
,
995 A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
996 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
998 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_SO_OVERRIDE
,
999 A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
1001 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
1002 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
1003 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9990
, 0);
1005 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
1006 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
1008 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
1010 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
1012 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
1013 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_809B
, 0);
1014 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
1015 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
1016 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
1017 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
1018 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
1019 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9981
, 0x3);
1020 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
1021 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9108
, 0x3);
1022 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
1023 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8878
, 0);
1024 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8879
, 0);
1025 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
1027 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
1029 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
1031 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
1033 /* we don't use this yet.. probably best to disable.. */
1034 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1035 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1036 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1037 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1038 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1039 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1041 /* Set not to use streamout by default, */
1042 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
1043 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
1045 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
1049 A6XX_SP_HS_CTRL_REG0(0));
1052 A6XX_SP_GS_CTRL_REG0(0));
1055 A6XX_GRAS_LRZ_CNTL(0));
1058 A6XX_RB_LRZ_CNTL(0));
1061 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
1063 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &cmd
->device
->border_color
));
1065 tu_cs_sanity_check(cs
);
1069 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1071 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1074 A6XX_VSC_BIN_SIZE(.width
= tiling
->tile0
.extent
.width
,
1075 .height
= tiling
->tile0
.extent
.height
),
1076 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo
= &cmd
->vsc_draw_strm
,
1077 .bo_offset
= 32 * cmd
->vsc_draw_strm_pitch
));
1080 A6XX_VSC_BIN_COUNT(.nx
= tiling
->tile_count
.width
,
1081 .ny
= tiling
->tile_count
.height
));
1083 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1084 for (unsigned i
= 0; i
< 32; i
++)
1085 tu_cs_emit(cs
, tiling
->pipe_config
[i
]);
1088 A6XX_VSC_PRIM_STRM_ADDRESS(.bo
= &cmd
->vsc_prim_strm
),
1089 A6XX_VSC_PRIM_STRM_PITCH(cmd
->vsc_prim_strm_pitch
),
1090 A6XX_VSC_PRIM_STRM_ARRAY_PITCH(cmd
->vsc_prim_strm
.size
));
1093 A6XX_VSC_DRAW_STRM_ADDRESS(.bo
= &cmd
->vsc_draw_strm
),
1094 A6XX_VSC_DRAW_STRM_PITCH(cmd
->vsc_draw_strm_pitch
),
1095 A6XX_VSC_DRAW_STRM_ARRAY_PITCH(cmd
->vsc_draw_strm
.size
));
1099 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1101 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1102 const uint32_t used_pipe_count
=
1103 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
1105 /* Clear vsc_scratch: */
1106 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
1107 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1108 tu_cs_emit(cs
, 0x0);
1110 /* Check for overflow, write vsc_scratch if detected: */
1111 for (int i
= 0; i
< used_pipe_count
; i
++) {
1112 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1113 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1114 CP_COND_WRITE5_0_WRITE_MEMORY
);
1115 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i
)));
1116 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1117 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_draw_strm_pitch
));
1118 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1119 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1120 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd
->vsc_draw_strm_pitch
));
1122 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
1123 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
1124 CP_COND_WRITE5_0_WRITE_MEMORY
);
1125 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i
)));
1126 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1127 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_prim_strm_pitch
));
1128 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
1129 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1130 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd
->vsc_prim_strm_pitch
));
1133 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
1135 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1137 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1138 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG
) |
1139 CP_MEM_TO_REG_0_CNT(1 - 1));
1140 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_scratch
));
1143 * This is a bit awkward, we really want a way to invert the
1144 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1145 * execute cmds to use hwbinning when a bit is *not* set. This
1146 * dance is to invert OVERFLOW_FLAG_REG
1148 * A CP_NOP packet is used to skip executing the 'else' clause
1152 /* b0 will be set if VSC_DRAW_STRM or VSC_PRIM_STRM overflow: */
1153 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1154 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1155 A6XX_CP_REG_TEST_0_BIT(0) |
1156 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1158 tu_cs_reserve(cs
, 3 + 7);
1159 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1160 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
1161 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(7));
1165 * On overflow, mirror the value to control->vsc_overflow
1166 * which CPU is checking to detect overflow (see
1167 * check_vsc_overflow())
1169 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
1170 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG
) |
1171 CP_REG_TO_MEM_0_CNT(0));
1172 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+ ctrl_offset(vsc_overflow
));
1174 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1175 tu_cs_emit(cs
, 0x0);
1177 tu_cs_emit_pkt7(cs
, CP_NOP
, 2); /* skip 'else' when 'if' is taken */
1179 tu_cs_emit_pkt4(cs
, OVERFLOW_FLAG_REG
, 1);
1180 tu_cs_emit(cs
, 0x1);
1185 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1187 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1188 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1190 uint32_t x1
= tiling
->tile0
.offset
.x
;
1191 uint32_t y1
= tiling
->tile0
.offset
.y
;
1192 uint32_t x2
= tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
- 1;
1193 uint32_t y2
= tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
- 1;
1195 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
1197 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1198 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
1200 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1201 tu_cs_emit(cs
, 0x1);
1203 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1204 tu_cs_emit(cs
, 0x1);
1209 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
1211 update_vsc_pipe(cmd
, cs
);
1214 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1217 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1219 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1220 tu_cs_emit(cs
, UNK_2C
);
1223 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
1226 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
1228 /* emit IB to binning drawcmds: */
1229 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1231 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1232 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1233 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1234 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1235 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1236 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1238 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1239 tu_cs_emit(cs
, UNK_2D
);
1241 /* This flush is probably required because the VSC, which produces the
1242 * visibility stream, is a client of UCHE, whereas the CP needs to read the
1243 * visibility stream (without caching) to do draw skipping. The
1244 * WFI+WAIT_FOR_ME combination guarantees that the binning commands
1245 * submitted are finished before reading the VSC regs (in
1246 * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
1249 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
);
1253 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1255 emit_vsc_overflow_test(cmd
, cs
);
1257 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1258 tu_cs_emit(cs
, 0x0);
1260 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1261 tu_cs_emit(cs
, 0x0);
1265 tu_emit_input_attachments(struct tu_cmd_buffer
*cmd
,
1266 const struct tu_subpass
*subpass
,
1267 struct tu_cs_entry
*ib
,
1270 /* note: we can probably emit input attachments just once for the whole
1271 * renderpass, this would avoid emitting both sysmem/gmem versions
1273 * emit two texture descriptors for each input, as a workaround for
1274 * d24s8, which can be sampled as both float (depth) and integer (stencil)
1275 * tu_shader lowers uint input attachment loads to use the 2nd descriptor
1277 * TODO: a smarter workaround
1280 if (!subpass
->input_count
)
1283 struct ts_cs_memory texture
;
1284 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, subpass
->input_count
* 2,
1285 A6XX_TEX_CONST_DWORDS
, &texture
);
1286 assert(result
== VK_SUCCESS
);
1288 for (unsigned i
= 0; i
< subpass
->input_count
* 2; i
++) {
1289 uint32_t a
= subpass
->input_attachments
[i
/ 2].attachment
;
1290 if (a
== VK_ATTACHMENT_UNUSED
)
1293 struct tu_image_view
*iview
=
1294 cmd
->state
.framebuffer
->attachments
[a
].attachment
;
1295 const struct tu_render_pass_attachment
*att
=
1296 &cmd
->state
.pass
->attachments
[a
];
1297 uint32_t *dst
= &texture
.map
[A6XX_TEX_CONST_DWORDS
* i
];
1299 memcpy(dst
, iview
->descriptor
, A6XX_TEX_CONST_DWORDS
* 4);
1301 if (i
% 2 == 1 && att
->format
== VK_FORMAT_D24_UNORM_S8_UINT
) {
1302 /* note this works because spec says fb and input attachments
1303 * must use identity swizzle
1305 dst
[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK
|
1306 A6XX_TEX_CONST_0_SWIZ_X__MASK
| A6XX_TEX_CONST_0_SWIZ_Y__MASK
|
1307 A6XX_TEX_CONST_0_SWIZ_Z__MASK
| A6XX_TEX_CONST_0_SWIZ_W__MASK
);
1308 dst
[0] |= A6XX_TEX_CONST_0_FMT(FMT6_S8Z24_UINT
) |
1309 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_Y
) |
1310 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO
) |
1311 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO
) |
1312 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE
);
1318 /* patched for gmem */
1319 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
1320 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
1321 dst
[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK
| A6XX_TEX_CONST_2_PITCH__MASK
);
1323 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
1324 A6XX_TEX_CONST_2_PITCH(cmd
->state
.tiling_config
.tile0
.extent
.width
* att
->cpp
);
1326 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ att
->gmem_offset
;
1327 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
1328 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
1333 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 9, &cs
);
1335 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_FRAG
, 3);
1336 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1337 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1338 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
1339 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_TEX
) |
1340 CP_LOAD_STATE6_0_NUM_UNIT(subpass
->input_count
* 2));
1341 tu_cs_emit_qw(&cs
, texture
.iova
);
1343 tu_cs_emit_pkt4(&cs
, REG_A6XX_SP_FS_TEX_CONST_LO
, 2);
1344 tu_cs_emit_qw(&cs
, texture
.iova
);
1346 tu_cs_emit_regs(&cs
, A6XX_SP_FS_TEX_COUNT(subpass
->input_count
* 2));
1348 *ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
1352 tu_set_input_attachments(struct tu_cmd_buffer
*cmd
, const struct tu_subpass
*subpass
)
1354 struct tu_cs
*cs
= &cmd
->draw_cs
;
1356 tu_emit_input_attachments(cmd
, subpass
, &cmd
->state
.ia_gmem_ib
, true);
1357 tu_emit_input_attachments(cmd
, subpass
, &cmd
->state
.ia_sysmem_ib
, false);
1359 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 6);
1360 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
, cmd
->state
.ia_gmem_ib
);
1361 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
, cmd
->state
.ia_sysmem_ib
);
1365 tu_emit_renderpass_begin(struct tu_cmd_buffer
*cmd
,
1366 const VkRenderPassBeginInfo
*info
)
1368 struct tu_cs
*cs
= &cmd
->draw_cs
;
1370 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1372 tu6_emit_blit_scissor(cmd
, cs
, true);
1374 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1375 tu_load_gmem_attachment(cmd
, cs
, i
, false);
1377 tu6_emit_blit_scissor(cmd
, cs
, false);
1379 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1380 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1382 tu_cond_exec_end(cs
);
1384 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1386 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1387 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1389 tu_cond_exec_end(cs
);
1393 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
,
1394 const struct VkRect2D
*renderArea
)
1396 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1398 assert(fb
->width
> 0 && fb
->height
> 0);
1399 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1400 tu6_emit_window_offset(cs
, 0, 0);
1402 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1404 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1406 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1407 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1409 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1410 tu_cs_emit(cs
, 0x0);
1412 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_SYSMEM
);
1414 /* enable stream-out, with sysmem there is only one pass: */
1416 A6XX_VPC_SO_OVERRIDE(.so_disable
= false));
1418 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1419 tu_cs_emit(cs
, 0x1);
1421 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1422 tu_cs_emit(cs
, 0x0);
1424 tu_cs_sanity_check(cs
);
1428 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1430 /* Do any resolves of the last subpass. These are handled in the
1431 * tile_store_ib in the gmem path.
1433 tu6_emit_sysmem_resolves(cmd
, cs
, cmd
->state
.subpass
);
1435 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1437 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1438 tu_cs_emit(cs
, 0x0);
1440 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1442 tu_cs_sanity_check(cs
);
1446 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1448 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1450 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1454 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1455 tu_cs_emit(cs
, 0x0);
1457 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_GMEM
);
1459 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1460 if (use_hw_binning(cmd
)) {
1461 /* enable stream-out during binning pass: */
1462 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1464 tu6_emit_bin_size(cs
,
1465 tiling
->tile0
.extent
.width
,
1466 tiling
->tile0
.extent
.height
,
1467 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1469 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1471 tu6_emit_binning_pass(cmd
, cs
);
1473 /* and disable stream-out for draw pass: */
1474 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=true));
1476 tu6_emit_bin_size(cs
,
1477 tiling
->tile0
.extent
.width
,
1478 tiling
->tile0
.extent
.height
,
1479 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1482 A6XX_VFD_MODE_CNTL(0));
1484 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1486 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1488 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1489 tu_cs_emit(cs
, 0x1);
1491 /* no binning pass, so enable stream-out for draw pass:: */
1492 tu_cs_emit_regs(cs
, A6XX_VPC_SO_OVERRIDE(.so_disable
=false));
1494 tu6_emit_bin_size(cs
,
1495 tiling
->tile0
.extent
.width
,
1496 tiling
->tile0
.extent
.height
,
1500 tu_cs_sanity_check(cs
);
1504 tu6_render_tile(struct tu_cmd_buffer
*cmd
,
1506 const struct tu_tile
*tile
)
1508 tu6_emit_tile_select(cmd
, cs
, tile
);
1510 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1512 if (use_hw_binning(cmd
)) {
1513 tu_cs_emit_pkt7(cs
, CP_REG_TEST
, 1);
1514 tu_cs_emit(cs
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1515 A6XX_CP_REG_TEST_0_BIT(0) |
1516 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1518 tu_cs_reserve(cs
, 3 + 2);
1519 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
1520 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
1521 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(2));
1523 /* if (no overflow) */ {
1524 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1525 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1529 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1531 tu_cs_sanity_check(cs
);
1535 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1537 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1540 A6XX_GRAS_LRZ_CNTL(0));
1542 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1544 tu6_emit_event_write(cmd
, cs
, PC_CCU_RESOLVE_TS
);
1546 tu_cs_sanity_check(cs
);
1550 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1552 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1554 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1556 for (uint32_t y
= 0; y
< tiling
->tile_count
.height
; y
++) {
1557 for (uint32_t x
= 0; x
< tiling
->tile_count
.width
; x
++) {
1558 struct tu_tile tile
;
1559 tu_tiling_config_get_tile(tiling
, cmd
->device
, x
, y
, &tile
);
1560 tu6_render_tile(cmd
, &cmd
->cs
, &tile
);
1564 tu6_tile_render_end(cmd
, &cmd
->cs
);
1568 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1570 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1572 tu6_sysmem_render_begin(cmd
, &cmd
->cs
, &tiling
->render_area
);
1574 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1576 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1580 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1582 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1583 struct tu_cs sub_cs
;
1586 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1587 if (result
!= VK_SUCCESS
) {
1588 cmd
->record_result
= result
;
1592 /* emit to tile-store sub_cs */
1593 tu6_emit_tile_store(cmd
, &sub_cs
);
1595 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1599 tu_cmd_update_tiling_config(struct tu_cmd_buffer
*cmd
,
1600 const VkRect2D
*render_area
)
1602 const struct tu_device
*dev
= cmd
->device
;
1603 struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1605 tiling
->render_area
= *render_area
;
1606 tiling
->force_sysmem
= false;
1608 tu_tiling_config_update_tile_layout(tiling
, dev
, cmd
->state
.pass
);
1609 tu_tiling_config_update_pipe_layout(tiling
, dev
);
1610 tu_tiling_config_update_pipes(tiling
, dev
);
1614 tu_create_cmd_buffer(struct tu_device
*device
,
1615 struct tu_cmd_pool
*pool
,
1616 VkCommandBufferLevel level
,
1617 VkCommandBuffer
*pCommandBuffer
)
1619 struct tu_cmd_buffer
*cmd_buffer
;
1620 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
1621 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1622 if (cmd_buffer
== NULL
)
1623 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1625 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1626 cmd_buffer
->device
= device
;
1627 cmd_buffer
->pool
= pool
;
1628 cmd_buffer
->level
= level
;
1631 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1632 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1635 /* Init the pool_link so we can safely call list_del when we destroy
1636 * the command buffer
1638 list_inithead(&cmd_buffer
->pool_link
);
1639 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1642 tu_bo_list_init(&cmd_buffer
->bo_list
);
1643 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1644 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1645 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1646 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1648 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1650 list_inithead(&cmd_buffer
->upload
.list
);
1652 VkResult result
= tu_bo_init_new(device
, &cmd_buffer
->scratch_bo
, 0x1000);
1653 if (result
!= VK_SUCCESS
)
1654 goto fail_scratch_bo
;
1656 /* TODO: resize on overflow */
1657 cmd_buffer
->vsc_draw_strm_pitch
= device
->vsc_draw_strm_pitch
;
1658 cmd_buffer
->vsc_prim_strm_pitch
= device
->vsc_prim_strm_pitch
;
1659 cmd_buffer
->vsc_draw_strm
= device
->vsc_draw_strm
;
1660 cmd_buffer
->vsc_prim_strm
= device
->vsc_prim_strm
;
1665 list_del(&cmd_buffer
->pool_link
);
1670 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1672 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->scratch_bo
);
1674 list_del(&cmd_buffer
->pool_link
);
1676 tu_cs_finish(&cmd_buffer
->cs
);
1677 tu_cs_finish(&cmd_buffer
->draw_cs
);
1678 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1679 tu_cs_finish(&cmd_buffer
->sub_cs
);
1681 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1682 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
1686 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1688 cmd_buffer
->record_result
= VK_SUCCESS
;
1690 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1691 tu_cs_reset(&cmd_buffer
->cs
);
1692 tu_cs_reset(&cmd_buffer
->draw_cs
);
1693 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1694 tu_cs_reset(&cmd_buffer
->sub_cs
);
1696 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++)
1697 memset(&cmd_buffer
->descriptors
[i
].sets
, 0, sizeof(cmd_buffer
->descriptors
[i
].sets
));
1699 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1701 return cmd_buffer
->record_result
;
1705 tu_AllocateCommandBuffers(VkDevice _device
,
1706 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1707 VkCommandBuffer
*pCommandBuffers
)
1709 TU_FROM_HANDLE(tu_device
, device
, _device
);
1710 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1712 VkResult result
= VK_SUCCESS
;
1715 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1717 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1718 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1719 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1721 list_del(&cmd_buffer
->pool_link
);
1722 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1724 result
= tu_reset_cmd_buffer(cmd_buffer
);
1725 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1726 cmd_buffer
->level
= pAllocateInfo
->level
;
1728 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1730 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1731 &pCommandBuffers
[i
]);
1733 if (result
!= VK_SUCCESS
)
1737 if (result
!= VK_SUCCESS
) {
1738 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1741 /* From the Vulkan 1.0.66 spec:
1743 * "vkAllocateCommandBuffers can be used to create multiple
1744 * command buffers. If the creation of any of those command
1745 * buffers fails, the implementation must destroy all
1746 * successfully created command buffer objects from this
1747 * command, set all entries of the pCommandBuffers array to
1748 * NULL and return the error."
1750 memset(pCommandBuffers
, 0,
1751 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1758 tu_FreeCommandBuffers(VkDevice device
,
1759 VkCommandPool commandPool
,
1760 uint32_t commandBufferCount
,
1761 const VkCommandBuffer
*pCommandBuffers
)
1763 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1764 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1767 if (cmd_buffer
->pool
) {
1768 list_del(&cmd_buffer
->pool_link
);
1769 list_addtail(&cmd_buffer
->pool_link
,
1770 &cmd_buffer
->pool
->free_cmd_buffers
);
1772 tu_cmd_buffer_destroy(cmd_buffer
);
1778 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1779 VkCommandBufferResetFlags flags
)
1781 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1782 return tu_reset_cmd_buffer(cmd_buffer
);
1785 /* Initialize the cache, assuming all necessary flushes have happened but *not*
1789 tu_cache_init(struct tu_cache_state
*cache
)
1791 cache
->flush_bits
= 0;
1792 cache
->pending_flush_bits
= TU_CMD_FLAG_ALL_INVALIDATE
;
1796 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1797 const VkCommandBufferBeginInfo
*pBeginInfo
)
1799 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1800 VkResult result
= VK_SUCCESS
;
1802 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1803 /* If the command buffer has already been resetted with
1804 * vkResetCommandBuffer, no need to do it again.
1806 result
= tu_reset_cmd_buffer(cmd_buffer
);
1807 if (result
!= VK_SUCCESS
)
1811 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1812 tu_cache_init(&cmd_buffer
->state
.cache
);
1813 tu_cache_init(&cmd_buffer
->state
.renderpass_cache
);
1814 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1816 tu_cs_begin(&cmd_buffer
->cs
);
1817 tu_cs_begin(&cmd_buffer
->draw_cs
);
1818 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1820 /* setup initial configuration into command buffer */
1821 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1822 switch (cmd_buffer
->queue_family_index
) {
1823 case TU_QUEUE_GENERAL
:
1824 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1829 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1830 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1831 assert(pBeginInfo
->pInheritanceInfo
);
1832 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1833 cmd_buffer
->state
.subpass
=
1834 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1836 /* When executing in the middle of another command buffer, the CCU
1839 cmd_buffer
->state
.ccu_state
= TU_CMD_CCU_UNKNOWN
;
1843 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1848 /* Sets vertex buffers to HW binding points. We emit VBs in SDS (so that bin
1849 * rendering can skip over unused state), so we need to collect all the
1850 * bindings together into a single state emit at draw time.
1853 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1854 uint32_t firstBinding
,
1855 uint32_t bindingCount
,
1856 const VkBuffer
*pBuffers
,
1857 const VkDeviceSize
*pOffsets
)
1859 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1861 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1863 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1864 struct tu_buffer
*buf
= tu_buffer_from_handle(pBuffers
[i
]);
1866 cmd
->state
.vb
.buffers
[firstBinding
+ i
] = buf
;
1867 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1869 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1872 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1876 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1878 VkDeviceSize offset
,
1879 VkIndexType indexType
)
1881 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1882 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1884 /* initialize/update the restart index */
1885 if (!cmd
->state
.index_buffer
|| cmd
->state
.index_type
!= indexType
) {
1886 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1888 tu6_emit_restart_index(
1889 draw_cs
, indexType
== VK_INDEX_TYPE_UINT32
? 0xffffffff : 0xffff);
1891 tu_cs_sanity_check(draw_cs
);
1895 if (cmd
->state
.index_buffer
!= buf
)
1896 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1898 cmd
->state
.index_buffer
= buf
;
1899 cmd
->state
.index_offset
= offset
;
1900 cmd
->state
.index_type
= indexType
;
1904 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1905 VkPipelineBindPoint pipelineBindPoint
,
1906 VkPipelineLayout _layout
,
1908 uint32_t descriptorSetCount
,
1909 const VkDescriptorSet
*pDescriptorSets
,
1910 uint32_t dynamicOffsetCount
,
1911 const uint32_t *pDynamicOffsets
)
1913 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1914 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1915 unsigned dyn_idx
= 0;
1917 struct tu_descriptor_state
*descriptors_state
=
1918 tu_get_descriptors_state(cmd
, pipelineBindPoint
);
1920 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1921 unsigned idx
= i
+ firstSet
;
1922 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1924 descriptors_state
->sets
[idx
] = set
;
1926 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1927 /* update the contents of the dynamic descriptor set */
1928 unsigned src_idx
= j
;
1929 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1930 assert(dyn_idx
< dynamicOffsetCount
);
1933 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1935 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1936 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1938 /* Patch the storage/uniform descriptors right away. */
1939 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1940 /* Note: we can assume here that the addition won't roll over and
1941 * change the SIZE field.
1943 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1948 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1949 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1950 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1957 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
1958 if (set
->buffers
[j
]) {
1959 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
1960 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1964 if (set
->size
> 0) {
1965 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
1966 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1969 assert(dyn_idx
== dynamicOffsetCount
);
1971 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
, hlsq_update_value
;
1972 uint64_t addr
[MAX_SETS
+ 1] = {};
1975 for (uint32_t i
= 0; i
< MAX_SETS
; i
++) {
1976 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
1978 addr
[i
] = set
->va
| 3;
1981 if (layout
->dynamic_offset_count
) {
1982 /* allocate and fill out dynamic descriptor set */
1983 struct ts_cs_memory dynamic_desc_set
;
1984 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, layout
->dynamic_offset_count
,
1985 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
1986 assert(result
== VK_SUCCESS
);
1988 memcpy(dynamic_desc_set
.map
, descriptors_state
->dynamic_descriptors
,
1989 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
1990 addr
[MAX_SETS
] = dynamic_desc_set
.iova
| 3;
1993 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1994 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
1995 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
1996 hlsq_update_value
= 0x7c000;
1998 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
| TU_CMD_DIRTY_SHADER_CONSTS
;
2000 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
);
2002 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
2003 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
2004 hlsq_update_value
= 0x3e00;
2006 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
;
2009 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 24, &cs
);
2011 tu_cs_emit_pkt4(&cs
, sp_bindless_base_reg
, 10);
2012 tu_cs_emit_array(&cs
, (const uint32_t*) addr
, 10);
2013 tu_cs_emit_pkt4(&cs
, hlsq_bindless_base_reg
, 10);
2014 tu_cs_emit_array(&cs
, (const uint32_t*) addr
, 10);
2015 tu_cs_emit_regs(&cs
, A6XX_HLSQ_UPDATE_CNTL(.dword
= hlsq_update_value
));
2017 struct tu_cs_entry ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
2018 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
2019 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
2020 tu_cs_emit_sds_ib(&cmd
->draw_cs
, TU_DRAW_STATE_DESC_SETS
, ib
);
2021 cmd
->state
.desc_sets_ib
= ib
;
2023 /* note: for compute we could emit directly, instead of a CP_INDIRECT
2024 * however, the blob uses draw states for compute
2026 tu_cs_emit_ib(&cmd
->cs
, &ib
);
2030 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
2031 uint32_t firstBinding
,
2032 uint32_t bindingCount
,
2033 const VkBuffer
*pBuffers
,
2034 const VkDeviceSize
*pOffsets
,
2035 const VkDeviceSize
*pSizes
)
2037 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2038 assert(firstBinding
+ bindingCount
<= IR3_MAX_SO_BUFFERS
);
2040 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
2041 uint32_t idx
= firstBinding
+ i
;
2042 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
2044 if (pOffsets
[i
] != 0)
2045 cmd
->state
.streamout_reset
|= 1 << idx
;
2047 cmd
->state
.streamout_buf
.buffers
[idx
] = buf
;
2048 cmd
->state
.streamout_buf
.offsets
[idx
] = pOffsets
[i
];
2049 cmd
->state
.streamout_buf
.sizes
[idx
] = pSizes
[i
];
2051 cmd
->state
.streamout_enabled
|= 1 << idx
;
2054 cmd
->state
.dirty
|= TU_CMD_DIRTY_STREAMOUT_BUFFERS
;
2057 void tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
2058 uint32_t firstCounterBuffer
,
2059 uint32_t counterBufferCount
,
2060 const VkBuffer
*pCounterBuffers
,
2061 const VkDeviceSize
*pCounterBufferOffsets
)
2063 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
2064 /* TODO do something with counter buffer? */
2067 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
2068 uint32_t firstCounterBuffer
,
2069 uint32_t counterBufferCount
,
2070 const VkBuffer
*pCounterBuffers
,
2071 const VkDeviceSize
*pCounterBufferOffsets
)
2073 assert(firstCounterBuffer
+ counterBufferCount
<= IR3_MAX_SO_BUFFERS
);
2074 /* TODO do something with counter buffer? */
2076 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2077 cmd
->state
.streamout_enabled
= 0;
2081 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
2082 VkPipelineLayout layout
,
2083 VkShaderStageFlags stageFlags
,
2086 const void *pValues
)
2088 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2089 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
2090 cmd
->state
.dirty
|= TU_CMD_DIRTY_SHADER_CONSTS
;
2093 /* Flush everything which has been made available but we haven't actually
2097 tu_flush_all_pending(struct tu_cache_state
*cache
)
2099 cache
->flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
2100 cache
->pending_flush_bits
&= ~TU_CMD_FLAG_ALL_FLUSH
;
2104 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
2106 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
2108 /* We currently flush CCU at the end of the command buffer, like
2109 * what the blob does. There's implicit synchronization around every
2110 * vkQueueSubmit, but the kernel only flushes the UCHE, and we don't
2111 * know yet if this command buffer will be the last in the submit so we
2112 * have to defensively flush everything else.
2114 * TODO: We could definitely do better than this, since these flushes
2115 * aren't required by Vulkan, but we'd need kernel support to do that.
2116 * Ideally, we'd like the kernel to flush everything afterwards, so that we
2117 * wouldn't have to do any flushes here, and when submitting multiple
2118 * command buffers there wouldn't be any unnecessary flushes in between.
2120 if (cmd_buffer
->state
.pass
) {
2121 tu_flush_all_pending(&cmd_buffer
->state
.renderpass_cache
);
2122 tu_emit_cache_flush_renderpass(cmd_buffer
, &cmd_buffer
->draw_cs
);
2124 tu_flush_all_pending(&cmd_buffer
->state
.cache
);
2125 cmd_buffer
->state
.cache
.flush_bits
|=
2126 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
2127 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
2128 tu_emit_cache_flush(cmd_buffer
, &cmd_buffer
->cs
);
2131 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->scratch_bo
,
2132 MSM_SUBMIT_BO_WRITE
);
2134 if (cmd_buffer
->use_vsc_data
) {
2135 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_draw_strm
,
2136 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2137 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->vsc_prim_strm
,
2138 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2141 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->border_color
,
2142 MSM_SUBMIT_BO_READ
);
2144 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
2145 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
2146 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2149 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
2150 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
2151 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2154 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
2155 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
2156 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2159 tu_cs_end(&cmd_buffer
->cs
);
2160 tu_cs_end(&cmd_buffer
->draw_cs
);
2161 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
2163 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
2165 return cmd_buffer
->record_result
;
2169 tu_cmd_dynamic_state(struct tu_cmd_buffer
*cmd
, uint32_t id
, uint32_t size
)
2171 struct ts_cs_memory memory
;
2174 /* TODO: share this logic with tu_pipeline_static_state */
2175 tu_cs_alloc(&cmd
->sub_cs
, size
, 1, &memory
);
2176 tu_cs_init_external(&cs
, memory
.map
, memory
.map
+ size
);
2178 tu_cs_reserve_space(&cs
, size
);
2180 assert(id
< ARRAY_SIZE(cmd
->state
.dynamic_state
));
2181 cmd
->state
.dynamic_state
[id
].iova
= memory
.iova
;
2182 cmd
->state
.dynamic_state
[id
].size
= size
;
2184 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
2185 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DYNAMIC
+ id
, cmd
->state
.dynamic_state
[id
]);
2191 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
2192 VkPipelineBindPoint pipelineBindPoint
,
2193 VkPipeline _pipeline
)
2195 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2196 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2198 tu_bo_list_add(&cmd
->bo_list
, &pipeline
->program
.binary_bo
,
2199 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2200 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2201 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2202 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2205 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
) {
2206 cmd
->state
.compute_pipeline
= pipeline
;
2207 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_PIPELINE
;
2211 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
);
2213 cmd
->state
.pipeline
= pipeline
;
2214 cmd
->state
.dirty
|= TU_CMD_DIRTY_SHADER_CONSTS
;
2216 struct tu_cs
*cs
= &cmd
->draw_cs
;
2217 uint32_t mask
= ~pipeline
->dynamic_state_mask
& BITFIELD_MASK(TU_DYNAMIC_STATE_COUNT
);
2220 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (7 + util_bitcount(mask
)));
2221 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state_ib
);
2222 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state_ib
);
2223 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state_ib
);
2224 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state_ib
);
2225 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast
.state_ib
);
2226 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DS
, pipeline
->ds
.state_ib
);
2227 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend
.state_ib
);
2229 for_each_bit(i
, mask
)
2230 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
, pipeline
->dynamic_state
[i
]);
2232 /* If the new pipeline requires more VBs than we had previously set up, we
2233 * need to re-emit them in SDS. If it requires the same set or fewer, we
2234 * can just re-use the old SDS.
2236 if (pipeline
->vi
.bindings_used
& ~cmd
->vertex_bindings_set
)
2237 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
2239 /* If the pipeline needs a dynamic descriptor, re-emit descriptor sets */
2240 if (pipeline
->layout
->dynamic_offset_count
)
2241 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
;
2243 /* dynamic linewidth state depends pipeline state's gras_su_cntl
2244 * so the dynamic state ib must be updated when pipeline changes
2246 if (pipeline
->dynamic_state_mask
& BIT(VK_DYNAMIC_STATE_LINE_WIDTH
)) {
2247 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2249 cmd
->state
.dynamic_gras_su_cntl
&= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2250 cmd
->state
.dynamic_gras_su_cntl
|= pipeline
->gras_su_cntl
;
2252 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2257 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2258 uint32_t firstViewport
,
2259 uint32_t viewportCount
,
2260 const VkViewport
*pViewports
)
2262 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2263 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_VIEWPORT
, 18);
2265 assert(firstViewport
== 0 && viewportCount
== 1);
2267 tu6_emit_viewport(&cs
, pViewports
);
2271 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2272 uint32_t firstScissor
,
2273 uint32_t scissorCount
,
2274 const VkRect2D
*pScissors
)
2276 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2277 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_SCISSOR
, 3);
2279 assert(firstScissor
== 0 && scissorCount
== 1);
2281 tu6_emit_scissor(&cs
, pScissors
);
2285 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2287 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2288 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2290 cmd
->state
.dynamic_gras_su_cntl
&= ~A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2291 cmd
->state
.dynamic_gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(lineWidth
/ 2.0f
);
2293 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2297 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2298 float depthBiasConstantFactor
,
2299 float depthBiasClamp
,
2300 float depthBiasSlopeFactor
)
2302 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2303 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BIAS
, 4);
2305 tu6_emit_depth_bias(&cs
, depthBiasConstantFactor
, depthBiasClamp
, depthBiasSlopeFactor
);
2309 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2310 const float blendConstants
[4])
2312 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2313 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_BLEND_CONSTANTS
, 5);
2315 tu_cs_emit_pkt4(&cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2316 tu_cs_emit_array(&cs
, (const uint32_t *) blendConstants
, 4);
2320 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2321 float minDepthBounds
,
2322 float maxDepthBounds
)
2327 update_stencil_mask(uint32_t *value
, VkStencilFaceFlags face
, uint32_t mask
)
2329 if (face
& VK_STENCIL_FACE_FRONT_BIT
)
2330 *value
|= A6XX_RB_STENCILMASK_MASK(mask
);
2331 if (face
& VK_STENCIL_FACE_BACK_BIT
)
2332 *value
|= A6XX_RB_STENCILMASK_BFMASK(mask
);
2336 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2337 VkStencilFaceFlags faceMask
,
2338 uint32_t compareMask
)
2340 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2341 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
, 2);
2343 update_stencil_mask(&cmd
->state
.dynamic_stencil_mask
, faceMask
, compareMask
);
2345 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILMASK(.dword
= cmd
->state
.dynamic_stencil_mask
));
2349 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2350 VkStencilFaceFlags faceMask
,
2353 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2354 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
, 2);
2356 update_stencil_mask(&cmd
->state
.dynamic_stencil_wrmask
, faceMask
, writeMask
);
2358 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILWRMASK(.dword
= cmd
->state
.dynamic_stencil_wrmask
));
2362 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2363 VkStencilFaceFlags faceMask
,
2366 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2367 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_REFERENCE
, 2);
2369 update_stencil_mask(&cmd
->state
.dynamic_stencil_ref
, faceMask
, reference
);
2371 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILREF(.dword
= cmd
->state
.dynamic_stencil_ref
));
2375 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer
,
2376 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
2378 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2379 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
, 9);
2381 assert(pSampleLocationsInfo
);
2383 tu6_emit_sample_locations(&cs
, pSampleLocationsInfo
);
2387 tu_flush_for_access(struct tu_cache_state
*cache
,
2388 enum tu_cmd_access_mask src_mask
,
2389 enum tu_cmd_access_mask dst_mask
)
2391 enum tu_cmd_flush_bits flush_bits
= 0;
2393 if (src_mask
& TU_ACCESS_SYSMEM_WRITE
) {
2394 cache
->pending_flush_bits
|= TU_CMD_FLAG_ALL_INVALIDATE
;
2397 #define SRC_FLUSH(domain, flush, invalidate) \
2398 if (src_mask & TU_ACCESS_##domain##_WRITE) { \
2399 cache->pending_flush_bits |= TU_CMD_FLAG_##flush | \
2400 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2403 SRC_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2404 SRC_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2405 SRC_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2409 #define SRC_INCOHERENT_FLUSH(domain, flush, invalidate) \
2410 if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
2411 flush_bits |= TU_CMD_FLAG_##flush; \
2412 cache->pending_flush_bits |= \
2413 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2416 SRC_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2417 SRC_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2419 #undef SRC_INCOHERENT_FLUSH
2421 if (dst_mask
& (TU_ACCESS_SYSMEM_READ
| TU_ACCESS_SYSMEM_WRITE
)) {
2422 flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
2425 #define DST_FLUSH(domain, flush, invalidate) \
2426 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2427 TU_ACCESS_##domain##_WRITE)) { \
2428 flush_bits |= cache->pending_flush_bits & \
2429 (TU_CMD_FLAG_##invalidate | \
2430 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2433 DST_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2434 DST_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2435 DST_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2439 #define DST_INCOHERENT_FLUSH(domain, flush, invalidate) \
2440 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2441 TU_ACCESS_##domain##_WRITE)) { \
2442 flush_bits |= TU_CMD_FLAG_##invalidate | \
2443 (cache->pending_flush_bits & \
2444 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2447 DST_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2448 DST_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2450 #undef DST_INCOHERENT_FLUSH
2452 if (dst_mask
& TU_ACCESS_WFI_READ
) {
2453 flush_bits
|= TU_CMD_FLAG_WFI
;
2456 cache
->flush_bits
|= flush_bits
;
2457 cache
->pending_flush_bits
&= ~flush_bits
;
2460 static enum tu_cmd_access_mask
2461 vk2tu_access(VkAccessFlags flags
, bool gmem
)
2463 enum tu_cmd_access_mask mask
= 0;
2465 /* If the GPU writes a buffer that is then read by an indirect draw
2466 * command, we theoretically need a WFI + WAIT_FOR_ME combination to
2467 * wait for the writes to complete. The WAIT_FOR_ME is performed as part
2468 * of the draw by the firmware, so we just need to execute a WFI.
2471 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
|
2472 VK_ACCESS_MEMORY_READ_BIT
)) {
2473 mask
|= TU_ACCESS_WFI_READ
;
2477 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
| /* Read performed by CP */
2478 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
| /* Read performed by CP, I think */
2479 VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
| /* Read performed by CP */
2480 VK_ACCESS_HOST_READ_BIT
| /* sysmem by definition */
2481 VK_ACCESS_MEMORY_READ_BIT
)) {
2482 mask
|= TU_ACCESS_SYSMEM_READ
;
2486 (VK_ACCESS_HOST_WRITE_BIT
|
2487 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
| /* Write performed by CP, I think */
2488 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2489 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2493 (VK_ACCESS_INDEX_READ_BIT
| /* Read performed by PC, I think */
2494 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
| /* Read performed by VFD */
2495 VK_ACCESS_UNIFORM_READ_BIT
| /* Read performed by SP */
2496 /* TODO: Is there a no-cache bit for textures so that we can ignore
2499 VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
| /* Read performed by TP */
2500 VK_ACCESS_SHADER_READ_BIT
| /* Read perfomed by SP/TP */
2501 VK_ACCESS_MEMORY_READ_BIT
)) {
2502 mask
|= TU_ACCESS_UCHE_READ
;
2506 (VK_ACCESS_SHADER_WRITE_BIT
| /* Write performed by SP */
2507 VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
| /* Write performed by VPC */
2508 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2509 mask
|= TU_ACCESS_UCHE_WRITE
;
2512 /* When using GMEM, the CCU is always flushed automatically to GMEM, and
2513 * then GMEM is flushed to sysmem. Furthermore, we already had to flush any
2514 * previous writes in sysmem mode when transitioning to GMEM. Therefore we
2515 * can ignore CCU and pretend that color attachments and transfers use
2520 (VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
|
2521 VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT
|
2522 VK_ACCESS_MEMORY_READ_BIT
)) {
2524 mask
|= TU_ACCESS_SYSMEM_READ
;
2526 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_READ
;
2530 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
|
2531 VK_ACCESS_MEMORY_READ_BIT
)) {
2533 mask
|= TU_ACCESS_SYSMEM_READ
;
2535 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
;
2539 (VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
|
2540 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2542 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2544 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2549 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
|
2550 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2552 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2554 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2558 /* When the dst access is a transfer read/write, it seems we sometimes need
2559 * to insert a WFI after any flushes, to guarantee that the flushes finish
2560 * before the 2D engine starts. However the opposite (i.e. a WFI after
2561 * CP_BLIT and before any subsequent flush) does not seem to be needed, and
2562 * the blob doesn't emit such a WFI.
2566 (VK_ACCESS_TRANSFER_WRITE_BIT
|
2567 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2569 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2571 mask
|= TU_ACCESS_CCU_COLOR_WRITE
;
2573 mask
|= TU_ACCESS_WFI_READ
;
2577 (VK_ACCESS_TRANSFER_READ_BIT
| /* Access performed by TP */
2578 VK_ACCESS_MEMORY_READ_BIT
)) {
2579 mask
|= TU_ACCESS_UCHE_READ
| TU_ACCESS_WFI_READ
;
2587 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2588 uint32_t commandBufferCount
,
2589 const VkCommandBuffer
*pCmdBuffers
)
2591 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2594 assert(commandBufferCount
> 0);
2596 /* Emit any pending flushes. */
2597 if (cmd
->state
.pass
) {
2598 tu_flush_all_pending(&cmd
->state
.renderpass_cache
);
2599 tu_emit_cache_flush_renderpass(cmd
, &cmd
->draw_cs
);
2601 tu_flush_all_pending(&cmd
->state
.cache
);
2602 tu_emit_cache_flush(cmd
, &cmd
->cs
);
2605 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2606 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2608 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2609 if (result
!= VK_SUCCESS
) {
2610 cmd
->record_result
= result
;
2614 if (secondary
->usage_flags
&
2615 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2616 assert(tu_cs_is_empty(&secondary
->cs
));
2618 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2619 if (result
!= VK_SUCCESS
) {
2620 cmd
->record_result
= result
;
2624 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2625 &secondary
->draw_epilogue_cs
);
2626 if (result
!= VK_SUCCESS
) {
2627 cmd
->record_result
= result
;
2631 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2632 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2634 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2635 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2636 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2639 tu_cs_add_entries(&cmd
->cs
, &secondary
->cs
);
2642 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2644 /* After executing secondary command buffers, there may have been arbitrary
2645 * flushes executed, so when we encounter a pipeline barrier with a
2646 * srcMask, we have to assume that we need to invalidate. Therefore we need
2647 * to re-initialize the cache with all pending invalidate bits set.
2649 if (cmd
->state
.pass
) {
2650 tu_cache_init(&cmd
->state
.renderpass_cache
);
2652 tu_cache_init(&cmd
->state
.cache
);
2657 tu_CreateCommandPool(VkDevice _device
,
2658 const VkCommandPoolCreateInfo
*pCreateInfo
,
2659 const VkAllocationCallbacks
*pAllocator
,
2660 VkCommandPool
*pCmdPool
)
2662 TU_FROM_HANDLE(tu_device
, device
, _device
);
2663 struct tu_cmd_pool
*pool
;
2665 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2666 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2668 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2671 pool
->alloc
= *pAllocator
;
2673 pool
->alloc
= device
->alloc
;
2675 list_inithead(&pool
->cmd_buffers
);
2676 list_inithead(&pool
->free_cmd_buffers
);
2678 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2680 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2686 tu_DestroyCommandPool(VkDevice _device
,
2687 VkCommandPool commandPool
,
2688 const VkAllocationCallbacks
*pAllocator
)
2690 TU_FROM_HANDLE(tu_device
, device
, _device
);
2691 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2696 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2697 &pool
->cmd_buffers
, pool_link
)
2699 tu_cmd_buffer_destroy(cmd_buffer
);
2702 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2703 &pool
->free_cmd_buffers
, pool_link
)
2705 tu_cmd_buffer_destroy(cmd_buffer
);
2708 vk_free2(&device
->alloc
, pAllocator
, pool
);
2712 tu_ResetCommandPool(VkDevice device
,
2713 VkCommandPool commandPool
,
2714 VkCommandPoolResetFlags flags
)
2716 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2719 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2722 result
= tu_reset_cmd_buffer(cmd_buffer
);
2723 if (result
!= VK_SUCCESS
)
2731 tu_TrimCommandPool(VkDevice device
,
2732 VkCommandPool commandPool
,
2733 VkCommandPoolTrimFlags flags
)
2735 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2740 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2741 &pool
->free_cmd_buffers
, pool_link
)
2743 tu_cmd_buffer_destroy(cmd_buffer
);
2748 tu_subpass_barrier(struct tu_cmd_buffer
*cmd_buffer
,
2749 const struct tu_subpass_barrier
*barrier
,
2752 /* Note: we don't know until the end of the subpass whether we'll use
2753 * sysmem, so assume sysmem here to be safe.
2755 struct tu_cache_state
*cache
=
2756 external
? &cmd_buffer
->state
.cache
: &cmd_buffer
->state
.renderpass_cache
;
2757 enum tu_cmd_access_mask src_flags
=
2758 vk2tu_access(barrier
->src_access_mask
, false);
2759 enum tu_cmd_access_mask dst_flags
=
2760 vk2tu_access(barrier
->dst_access_mask
, false);
2762 if (barrier
->incoherent_ccu_color
)
2763 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2764 if (barrier
->incoherent_ccu_depth
)
2765 src_flags
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2767 tu_flush_for_access(cache
, src_flags
, dst_flags
);
2771 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2772 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2773 VkSubpassContents contents
)
2775 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2776 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2777 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2779 cmd
->state
.pass
= pass
;
2780 cmd
->state
.subpass
= pass
->subpasses
;
2781 cmd
->state
.framebuffer
= fb
;
2783 tu_cmd_update_tiling_config(cmd
, &pRenderPassBegin
->renderArea
);
2784 tu_cmd_prepare_tile_store_ib(cmd
);
2786 /* Note: because this is external, any flushes will happen before draw_cs
2787 * gets called. However deferred flushes could have to happen later as part
2790 tu_subpass_barrier(cmd
, &pass
->subpasses
[0].start_barrier
, true);
2791 cmd
->state
.renderpass_cache
.pending_flush_bits
=
2792 cmd
->state
.cache
.pending_flush_bits
;
2793 cmd
->state
.renderpass_cache
.flush_bits
= 0;
2795 tu_emit_renderpass_begin(cmd
, pRenderPassBegin
);
2797 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2798 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2799 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2800 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2802 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2804 /* note: use_hw_binning only checks tiling config */
2805 if (use_hw_binning(cmd
))
2806 cmd
->use_vsc_data
= true;
2808 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2809 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2810 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2811 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2814 cmd
->state
.dirty
|= TU_CMD_DIRTY_DRAW_STATE
;
2818 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2819 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2820 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2822 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2823 pSubpassBeginInfo
->contents
);
2827 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2829 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2830 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2831 struct tu_cs
*cs
= &cmd
->draw_cs
;
2833 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2835 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2837 if (subpass
->resolve_attachments
) {
2838 tu6_emit_blit_scissor(cmd
, cs
, true);
2840 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2841 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2842 if (a
== VK_ATTACHMENT_UNUSED
)
2845 tu_store_gmem_attachment(cmd
, cs
, a
,
2846 subpass
->color_attachments
[i
].attachment
);
2848 if (pass
->attachments
[a
].gmem_offset
< 0)
2852 * check if the resolved attachment is needed by later subpasses,
2853 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2855 tu_finishme("missing GMEM->GMEM resolve path\n");
2856 tu_load_gmem_attachment(cmd
, cs
, a
, true);
2860 tu_cond_exec_end(cs
);
2862 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2864 tu6_emit_sysmem_resolves(cmd
, cs
, subpass
);
2866 tu_cond_exec_end(cs
);
2868 /* Handle dependencies for the next subpass */
2869 tu_subpass_barrier(cmd
, &cmd
->state
.subpass
->start_barrier
, false);
2871 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2872 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2873 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2874 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2875 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2877 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2881 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2882 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2883 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2885 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2891 * Number of vertices.
2896 * Index of the first vertex.
2898 int32_t vertex_offset
;
2901 * First instance id.
2903 uint32_t first_instance
;
2906 * Number of instances.
2908 uint32_t instance_count
;
2911 * First index (indexed draws only).
2913 uint32_t first_index
;
2916 * Whether it's an indexed draw.
2921 * Indirect draw parameters resource.
2923 struct tu_buffer
*indirect
;
2924 uint64_t indirect_offset
;
2928 * Draw count parameters resource.
2930 struct tu_buffer
*count_buffer
;
2931 uint64_t count_buffer_offset
;
2934 * Stream output parameters resource.
2936 struct tu_buffer
*streamout_buffer
;
2937 uint64_t streamout_buffer_offset
;
2941 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2942 struct tu_descriptor_state
*descriptors_state
,
2943 gl_shader_stage type
,
2944 uint32_t *push_constants
)
2946 const struct tu_program_descriptor_linkage
*link
=
2947 &pipeline
->program
.link
[type
];
2948 const struct ir3_ubo_analysis_state
*state
= &link
->ubo_state
;
2950 if (link
->push_consts
.count
> 0) {
2951 unsigned num_units
= link
->push_consts
.count
;
2952 unsigned offset
= link
->push_consts
.lo
;
2953 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2954 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2955 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2956 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2957 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2958 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2961 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2962 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2965 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2966 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2967 uint32_t offset
= state
->range
[i
].start
;
2969 /* and even if the start of the const buffer is before
2970 * first_immediate, the end may not be:
2972 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2977 /* things should be aligned to vec4: */
2978 debug_assert((state
->range
[i
].offset
% 16) == 0);
2979 debug_assert((size
% 16) == 0);
2980 debug_assert((offset
% 16) == 0);
2982 /* Dig out the descriptor from the descriptor state and read the VA from
2985 assert(state
->range
[i
].bindless
);
2986 uint32_t *base
= state
->range
[i
].bindless_base
== MAX_SETS
?
2987 descriptors_state
->dynamic_descriptors
:
2988 descriptors_state
->sets
[state
->range
[i
].bindless_base
]->mapped_ptr
;
2989 unsigned block
= state
->range
[i
].block
;
2990 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2991 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2994 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2995 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2996 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2997 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2998 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2999 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
3000 tu_cs_emit_qw(cs
, va
+ offset
);
3004 static struct tu_cs_entry
3005 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
3006 const struct tu_pipeline
*pipeline
,
3007 struct tu_descriptor_state
*descriptors_state
,
3008 gl_shader_stage type
)
3011 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
3013 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
3015 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
3019 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
3020 const struct tu_draw_info
*draw
,
3021 struct tu_cs_entry
*entry
)
3023 /* TODO: fill out more than just base instance */
3024 const struct tu_program_descriptor_linkage
*link
=
3025 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
3026 const struct ir3_const_state
*const_state
= &link
->const_state
;
3029 if (const_state
->offsets
.driver_param
>= link
->constlen
) {
3030 *entry
= (struct tu_cs_entry
) {};
3034 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 8, &cs
);
3035 if (result
!= VK_SUCCESS
)
3038 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
3039 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(const_state
->offsets
.driver_param
) |
3040 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3041 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3042 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
3043 CP_LOAD_STATE6_0_NUM_UNIT(1));
3047 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
3051 tu_cs_emit(&cs
, draw
->first_instance
);
3054 *entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
3058 static struct tu_cs_entry
3059 tu6_emit_vertex_buffers(struct tu_cmd_buffer
*cmd
,
3060 const struct tu_pipeline
*pipeline
)
3063 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 4 * MAX_VBS
, &cs
);
3066 for_each_bit(binding
, pipeline
->vi
.bindings_used
) {
3067 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
3068 const VkDeviceSize offset
= buf
->bo_offset
+
3069 cmd
->state
.vb
.offsets
[binding
];
3071 tu_cs_emit_regs(&cs
,
3072 A6XX_VFD_FETCH_BASE(binding
, .bo
= buf
->bo
, .bo_offset
= offset
),
3073 A6XX_VFD_FETCH_SIZE(binding
, buf
->size
- offset
));
3077 cmd
->vertex_bindings_set
= pipeline
->vi
.bindings_used
;
3079 return tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
3083 tu6_emit_streamout(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
3085 struct tu_streamout_state
*tf
= &cmd
->state
.pipeline
->streamout
;
3087 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3088 struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
3093 offset
= cmd
->state
.streamout_buf
.offsets
[i
];
3095 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_BASE(i
, .bo
= buf
->bo
,
3096 .bo_offset
= buf
->bo_offset
));
3097 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_SIZE(i
, buf
->size
));
3099 if (cmd
->state
.streamout_reset
& (1 << i
)) {
3100 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, offset
));
3101 cmd
->state
.streamout_reset
&= ~(1 << i
);
3103 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
3104 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i
)) |
3105 CP_MEM_TO_REG_0_SHIFT_BY_2
| CP_MEM_TO_REG_0_UNK31
|
3106 CP_MEM_TO_REG_0_CNT(0));
3107 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
+
3108 ctrl_offset(flush_base
[i
].offset
));
3111 tu_cs_emit_regs(cs
, A6XX_VPC_SO_FLUSH_BASE(i
, .bo
= &cmd
->scratch_bo
,
3113 ctrl_offset(flush_base
[i
])));
3116 if (cmd
->state
.streamout_enabled
) {
3117 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * tf
->prog_count
));
3118 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
3119 tu_cs_emit(cs
, tf
->vpc_so_buf_cntl
);
3120 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(0));
3121 tu_cs_emit(cs
, tf
->ncomp
[0]);
3122 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(1));
3123 tu_cs_emit(cs
, tf
->ncomp
[1]);
3124 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(2));
3125 tu_cs_emit(cs
, tf
->ncomp
[2]);
3126 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(3));
3127 tu_cs_emit(cs
, tf
->ncomp
[3]);
3128 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
3129 tu_cs_emit(cs
, A6XX_VPC_SO_CNTL_ENABLE
);
3130 for (unsigned i
= 0; i
< tf
->prog_count
; i
++) {
3131 tu_cs_emit(cs
, REG_A6XX_VPC_SO_PROG
);
3132 tu_cs_emit(cs
, tf
->prog
[i
]);
3135 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
3136 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
3138 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
3144 tu6_bind_draw_states(struct tu_cmd_buffer
*cmd
,
3146 const struct tu_draw_info
*draw
)
3148 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3151 struct tu_descriptor_state
*descriptors_state
=
3152 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
3157 A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart
=
3158 pipeline
->ia
.primitive_restart
&& draw
->indexed
));
3160 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
3161 cmd
->state
.shader_const_ib
[MESA_SHADER_VERTEX
] =
3162 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
);
3163 cmd
->state
.shader_const_ib
[MESA_SHADER_GEOMETRY
] =
3164 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_GEOMETRY
);
3165 cmd
->state
.shader_const_ib
[MESA_SHADER_FRAGMENT
] =
3166 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
);
3169 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
)
3170 tu6_emit_streamout(cmd
, cs
);
3172 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) {
3173 /* We need to reload the descriptors every time the descriptor sets
3174 * change. However, the commands we send only depend on the pipeline
3175 * because the whole point is to cache descriptors which are used by the
3176 * pipeline. There's a problem here, in that the firmware has an
3177 * "optimization" which skips executing groups that are set to the same
3178 * value as the last draw. This means that if the descriptor sets change
3179 * but not the pipeline, we'd try to re-execute the same buffer which
3180 * the firmware would ignore and we wouldn't pre-load the new
3181 * descriptors. The blob seems to re-emit the LOAD_STATE group whenever
3182 * the descriptor sets change, which we emulate here by copying the
3183 * pre-prepared buffer.
3185 const struct tu_cs_entry
*load_entry
= &pipeline
->load_state
.state_ib
;
3186 if (load_entry
->size
> 0) {
3187 struct tu_cs load_cs
;
3188 result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, load_entry
->size
, &load_cs
);
3189 if (result
!= VK_SUCCESS
)
3191 tu_cs_emit_array(&load_cs
,
3192 (uint32_t *)((char *)load_entry
->bo
->map
+ load_entry
->offset
),
3193 load_entry
->size
/ 4);
3194 cmd
->state
.desc_sets_load_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &load_cs
);
3196 cmd
->state
.desc_sets_load_ib
.size
= 0;
3200 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3201 cmd
->state
.vertex_buffers_ib
= tu6_emit_vertex_buffers(cmd
, pipeline
);
3203 struct tu_cs_entry vs_params
;
3204 result
= tu6_emit_vs_params(cmd
, draw
, &vs_params
);
3205 if (result
!= VK_SUCCESS
)
3208 /* for the first draw in a renderpass, re-emit all the draw states
3210 * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
3211 * used, then draw states must be re-emitted. note however this only happens
3212 * in the sysmem path, so this can be skipped this for the gmem path (TODO)
3214 * the two input attachment states are excluded because secondary command
3215 * buffer doesn't have a state ib to restore it, and not re-emitting them
3216 * is OK since CmdClearAttachments won't disable/overwrite them
3218 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DRAW_STATE
) {
3219 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (TU_DRAW_STATE_COUNT
- 2));
3221 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state_ib
);
3222 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state_ib
);
3223 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state_ib
);
3224 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state_ib
);
3225 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast
.state_ib
);
3226 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DS
, pipeline
->ds
.state_ib
);
3227 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend
.state_ib
);
3228 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_VERTEX
]);
3229 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_GEOMETRY
]);
3230 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_FRAGMENT
]);
3231 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets_ib
);
3232 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, cmd
->state
.desc_sets_load_ib
);
3233 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers_ib
);
3234 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VS_PARAMS
, vs_params
);
3236 for (uint32_t i
= 0; i
< ARRAY_SIZE(cmd
->state
.dynamic_state
); i
++) {
3237 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
,
3238 ((pipeline
->dynamic_state_mask
& BIT(i
)) ?
3239 cmd
->state
.dynamic_state
[i
] :
3240 pipeline
->dynamic_state
[i
]));
3244 /* emit draw states that were just updated
3245 * note we eventually don't want to have to emit anything here
3247 uint32_t draw_state_count
=
3248 ((cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) ? 3 : 0) +
3249 ((cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) ? 1 : 0) +
3250 ((cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) ? 1 : 0) +
3253 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_count
);
3255 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
3256 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_VERTEX
]);
3257 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_GEOMETRY
]);
3258 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const_ib
[MESA_SHADER_FRAGMENT
]);
3260 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
)
3261 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, cmd
->state
.desc_sets_load_ib
);
3262 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3263 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers_ib
);
3264 tu_cs_emit_sds_ib(cs
, TU_DRAW_STATE_VS_PARAMS
, vs_params
);
3267 tu_cs_sanity_check(cs
);
3270 if (cmd
->state
.dirty
& TU_CMD_DIRTY_STREAMOUT_BUFFERS
) {
3271 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3272 const struct tu_buffer
*buf
= cmd
->state
.streamout_buf
.buffers
[i
];
3274 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
,
3275 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3280 /* There are too many graphics dirty bits to list here, so just list the
3281 * bits to preserve instead. The only things not emitted here are
3282 * compute-related state.
3284 cmd
->state
.dirty
&= (TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
| TU_CMD_DIRTY_COMPUTE_PIPELINE
);
3289 tu6_emit_draw_indirect(struct tu_cmd_buffer
*cmd
,
3291 const struct tu_draw_info
*draw
)
3293 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3294 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3295 VK_SHADER_STAGE_GEOMETRY_BIT
;
3298 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3299 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3301 if (draw
->indexed
) {
3302 const enum a4xx_index_size index_size
=
3303 tu6_index_size(cmd
->state
.index_type
);
3304 const uint32_t index_bytes
=
3305 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3306 const struct tu_buffer
*index_buf
= cmd
->state
.index_buffer
;
3307 unsigned max_indicies
=
3308 (index_buf
->size
- cmd
->state
.index_offset
) / index_bytes
;
3310 const uint32_t cp_draw_indx
=
3311 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3312 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3313 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3314 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3315 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3317 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_INDIRECT
, 6);
3318 tu_cs_emit(cs
, cp_draw_indx
);
3319 tu_cs_emit_qw(cs
, index_buf
->bo
->iova
+ cmd
->state
.index_offset
);
3320 tu_cs_emit(cs
, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies
));
3321 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3323 const uint32_t cp_draw_indx
=
3324 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3325 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3326 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3327 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3329 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT
, 3);
3330 tu_cs_emit(cs
, cp_draw_indx
);
3331 tu_cs_emit_qw(cs
, draw
->indirect
->bo
->iova
+ draw
->indirect_offset
);
3334 tu_bo_list_add(&cmd
->bo_list
, draw
->indirect
->bo
, MSM_SUBMIT_BO_READ
);
3338 tu6_emit_draw_direct(struct tu_cmd_buffer
*cmd
,
3340 const struct tu_draw_info
*draw
)
3343 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
3344 bool has_gs
= cmd
->state
.pipeline
->active_stages
&
3345 VK_SHADER_STAGE_GEOMETRY_BIT
;
3348 A6XX_VFD_INDEX_OFFSET(draw
->vertex_offset
),
3349 A6XX_VFD_INSTANCE_START_OFFSET(draw
->first_instance
));
3351 /* TODO hw binning */
3352 if (draw
->indexed
) {
3353 const enum a4xx_index_size index_size
=
3354 tu6_index_size(cmd
->state
.index_type
);
3355 const uint32_t index_bytes
=
3356 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
3357 const struct tu_buffer
*buf
= cmd
->state
.index_buffer
;
3358 const VkDeviceSize offset
= buf
->bo_offset
+ cmd
->state
.index_offset
+
3359 index_bytes
* draw
->first_index
;
3360 const uint32_t size
= index_bytes
* draw
->count
;
3362 const uint32_t cp_draw_indx
=
3363 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3364 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
3365 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
3366 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3367 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3369 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3370 tu_cs_emit(cs
, cp_draw_indx
);
3371 tu_cs_emit(cs
, draw
->instance_count
);
3372 tu_cs_emit(cs
, draw
->count
);
3373 tu_cs_emit(cs
, 0x0); /* XXX */
3374 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ offset
);
3375 tu_cs_emit(cs
, size
);
3377 const uint32_t cp_draw_indx
=
3378 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
3379 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
3380 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
) |
3381 COND(has_gs
, CP_DRAW_INDX_OFFSET_0_GS_ENABLE
) | 0x2000;
3383 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3384 tu_cs_emit(cs
, cp_draw_indx
);
3385 tu_cs_emit(cs
, draw
->instance_count
);
3386 tu_cs_emit(cs
, draw
->count
);
3391 tu_draw(struct tu_cmd_buffer
*cmd
, const struct tu_draw_info
*draw
)
3393 struct tu_cs
*cs
= &cmd
->draw_cs
;
3396 tu_emit_cache_flush_renderpass(cmd
, cs
);
3398 result
= tu6_bind_draw_states(cmd
, cs
, draw
);
3399 if (result
!= VK_SUCCESS
) {
3400 cmd
->record_result
= result
;
3405 tu6_emit_draw_indirect(cmd
, cs
, draw
);
3407 tu6_emit_draw_direct(cmd
, cs
, draw
);
3409 if (cmd
->state
.streamout_enabled
) {
3410 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
3411 if (cmd
->state
.streamout_enabled
& (1 << i
))
3412 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
);
3416 tu_cs_sanity_check(cs
);
3420 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3421 uint32_t vertexCount
,
3422 uint32_t instanceCount
,
3423 uint32_t firstVertex
,
3424 uint32_t firstInstance
)
3426 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3427 struct tu_draw_info info
= {};
3429 info
.count
= vertexCount
;
3430 info
.instance_count
= instanceCount
;
3431 info
.first_instance
= firstInstance
;
3432 info
.vertex_offset
= firstVertex
;
3434 tu_draw(cmd_buffer
, &info
);
3438 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3439 uint32_t indexCount
,
3440 uint32_t instanceCount
,
3441 uint32_t firstIndex
,
3442 int32_t vertexOffset
,
3443 uint32_t firstInstance
)
3445 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3446 struct tu_draw_info info
= {};
3448 info
.indexed
= true;
3449 info
.count
= indexCount
;
3450 info
.instance_count
= instanceCount
;
3451 info
.first_index
= firstIndex
;
3452 info
.vertex_offset
= vertexOffset
;
3453 info
.first_instance
= firstInstance
;
3455 tu_draw(cmd_buffer
, &info
);
3459 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3461 VkDeviceSize offset
,
3465 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3466 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3467 struct tu_draw_info info
= {};
3469 info
.count
= drawCount
;
3470 info
.indirect
= buffer
;
3471 info
.indirect_offset
= offset
;
3472 info
.stride
= stride
;
3474 tu_draw(cmd_buffer
, &info
);
3478 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3480 VkDeviceSize offset
,
3484 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3485 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3486 struct tu_draw_info info
= {};
3488 info
.indexed
= true;
3489 info
.count
= drawCount
;
3490 info
.indirect
= buffer
;
3491 info
.indirect_offset
= offset
;
3492 info
.stride
= stride
;
3494 tu_draw(cmd_buffer
, &info
);
3497 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3498 uint32_t instanceCount
,
3499 uint32_t firstInstance
,
3500 VkBuffer _counterBuffer
,
3501 VkDeviceSize counterBufferOffset
,
3502 uint32_t counterOffset
,
3503 uint32_t vertexStride
)
3505 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3506 TU_FROM_HANDLE(tu_buffer
, buffer
, _counterBuffer
);
3508 struct tu_draw_info info
= {};
3510 info
.instance_count
= instanceCount
;
3511 info
.first_instance
= firstInstance
;
3512 info
.streamout_buffer
= buffer
;
3513 info
.streamout_buffer_offset
= counterBufferOffset
;
3514 info
.stride
= vertexStride
;
3516 tu_draw(cmd_buffer
, &info
);
3519 struct tu_dispatch_info
3522 * Determine the layout of the grid (in block units) to be used.
3527 * A starting offset for the grid. If unaligned is set, the offset
3528 * must still be aligned.
3530 uint32_t offsets
[3];
3532 * Whether it's an unaligned compute dispatch.
3537 * Indirect compute parameters resource.
3539 struct tu_buffer
*indirect
;
3540 uint64_t indirect_offset
;
3544 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3545 const struct tu_dispatch_info
*info
)
3547 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3548 const struct tu_program_descriptor_linkage
*link
=
3549 &pipeline
->program
.link
[type
];
3550 const struct ir3_const_state
*const_state
= &link
->const_state
;
3551 uint32_t offset
= const_state
->offsets
.driver_param
;
3553 if (link
->constlen
<= offset
)
3556 if (!info
->indirect
) {
3557 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3558 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3559 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3560 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3561 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3562 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3563 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3566 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3567 (link
->constlen
- offset
) * 4);
3568 /* push constants */
3569 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3570 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3571 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3572 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3573 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3574 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3578 for (i
= 0; i
< num_consts
; i
++)
3579 tu_cs_emit(cs
, driver_params
[i
]);
3581 tu_finishme("Indirect driver params");
3586 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3587 const struct tu_dispatch_info
*info
)
3589 struct tu_cs
*cs
= &cmd
->cs
;
3590 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3591 struct tu_descriptor_state
*descriptors_state
=
3592 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3594 /* TODO: We could probably flush less if we add a compute_flush_bits
3597 tu_emit_cache_flush(cmd
, cs
);
3599 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_PIPELINE
)
3600 tu_cs_emit_ib(cs
, &pipeline
->program
.state_ib
);
3602 struct tu_cs_entry ib
;
3604 ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
);
3606 tu_cs_emit_ib(cs
, &ib
);
3608 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3610 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
) &&
3611 pipeline
->load_state
.state_ib
.size
> 0) {
3612 tu_cs_emit_ib(cs
, &pipeline
->load_state
.state_ib
);
3616 ~(TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
| TU_CMD_DIRTY_COMPUTE_PIPELINE
);
3618 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3619 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3621 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3622 const uint32_t *num_groups
= info
->blocks
;
3624 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3625 .localsizex
= local_size
[0] - 1,
3626 .localsizey
= local_size
[1] - 1,
3627 .localsizez
= local_size
[2] - 1),
3628 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3629 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3630 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3631 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3632 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3633 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3636 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3637 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3638 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3640 if (info
->indirect
) {
3641 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3643 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3644 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3646 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3647 tu_cs_emit(cs
, 0x00000000);
3648 tu_cs_emit_qw(cs
, iova
);
3650 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3651 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3652 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3654 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3655 tu_cs_emit(cs
, 0x00000000);
3656 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3657 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3658 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3665 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3673 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3674 struct tu_dispatch_info info
= {};
3680 info
.offsets
[0] = base_x
;
3681 info
.offsets
[1] = base_y
;
3682 info
.offsets
[2] = base_z
;
3683 tu_dispatch(cmd_buffer
, &info
);
3687 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3692 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3696 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3698 VkDeviceSize offset
)
3700 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3701 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3702 struct tu_dispatch_info info
= {};
3704 info
.indirect
= buffer
;
3705 info
.indirect_offset
= offset
;
3707 tu_dispatch(cmd_buffer
, &info
);
3711 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3713 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3715 tu_cs_end(&cmd_buffer
->draw_cs
);
3716 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3718 if (use_sysmem_rendering(cmd_buffer
))
3719 tu_cmd_render_sysmem(cmd_buffer
);
3721 tu_cmd_render_tiles(cmd_buffer
);
3723 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3725 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3726 tu_cs_begin(&cmd_buffer
->draw_cs
);
3727 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3728 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3730 cmd_buffer
->state
.cache
.pending_flush_bits
|=
3731 cmd_buffer
->state
.renderpass_cache
.pending_flush_bits
;
3732 tu_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
, true);
3734 cmd_buffer
->state
.pass
= NULL
;
3735 cmd_buffer
->state
.subpass
= NULL
;
3736 cmd_buffer
->state
.framebuffer
= NULL
;
3740 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3741 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3743 tu_CmdEndRenderPass(commandBuffer
);
3746 struct tu_barrier_info
3748 uint32_t eventCount
;
3749 const VkEvent
*pEvents
;
3750 VkPipelineStageFlags srcStageMask
;
3754 tu_barrier(struct tu_cmd_buffer
*cmd
,
3755 uint32_t memoryBarrierCount
,
3756 const VkMemoryBarrier
*pMemoryBarriers
,
3757 uint32_t bufferMemoryBarrierCount
,
3758 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3759 uint32_t imageMemoryBarrierCount
,
3760 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3761 const struct tu_barrier_info
*info
)
3763 struct tu_cs
*cs
= cmd
->state
.pass
? &cmd
->draw_cs
: &cmd
->cs
;
3764 VkAccessFlags srcAccessMask
= 0;
3765 VkAccessFlags dstAccessMask
= 0;
3767 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3768 srcAccessMask
|= pMemoryBarriers
[i
].srcAccessMask
;
3769 dstAccessMask
|= pMemoryBarriers
[i
].dstAccessMask
;
3772 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3773 srcAccessMask
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
3774 dstAccessMask
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
3777 enum tu_cmd_access_mask src_flags
= 0;
3778 enum tu_cmd_access_mask dst_flags
= 0;
3780 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3781 TU_FROM_HANDLE(tu_image
, image
, pImageMemoryBarriers
[i
].image
);
3782 VkImageLayout old_layout
= pImageMemoryBarriers
[i
].oldLayout
;
3783 /* For non-linear images, PREINITIALIZED is the same as UNDEFINED */
3784 if (old_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
3785 (image
->tiling
!= VK_IMAGE_TILING_LINEAR
&&
3786 old_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
)) {
3787 /* The underlying memory for this image may have been used earlier
3788 * within the same queue submission for a different image, which
3789 * means that there may be old, stale cache entries which are in the
3790 * "wrong" location, which could cause problems later after writing
3791 * to the image. We don't want these entries being flushed later and
3792 * overwriting the actual image, so we need to flush the CCU.
3794 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
3796 srcAccessMask
|= pImageMemoryBarriers
[i
].srcAccessMask
;
3797 dstAccessMask
|= pImageMemoryBarriers
[i
].dstAccessMask
;
3800 /* Inside a renderpass, we don't know yet whether we'll be using sysmem
3801 * so we have to use the sysmem flushes.
3803 bool gmem
= cmd
->state
.ccu_state
== TU_CMD_CCU_GMEM
&&
3805 src_flags
|= vk2tu_access(srcAccessMask
, gmem
);
3806 dst_flags
|= vk2tu_access(dstAccessMask
, gmem
);
3808 struct tu_cache_state
*cache
=
3809 cmd
->state
.pass
? &cmd
->state
.renderpass_cache
: &cmd
->state
.cache
;
3810 tu_flush_for_access(cache
, src_flags
, dst_flags
);
3812 for (uint32_t i
= 0; i
< info
->eventCount
; i
++) {
3813 TU_FROM_HANDLE(tu_event
, event
, info
->pEvents
[i
]);
3815 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3817 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3818 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3819 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3820 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3821 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3822 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3823 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3828 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3829 VkPipelineStageFlags srcStageMask
,
3830 VkPipelineStageFlags dstStageMask
,
3831 VkDependencyFlags dependencyFlags
,
3832 uint32_t memoryBarrierCount
,
3833 const VkMemoryBarrier
*pMemoryBarriers
,
3834 uint32_t bufferMemoryBarrierCount
,
3835 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3836 uint32_t imageMemoryBarrierCount
,
3837 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3839 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3840 struct tu_barrier_info info
;
3842 info
.eventCount
= 0;
3843 info
.pEvents
= NULL
;
3844 info
.srcStageMask
= srcStageMask
;
3846 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3847 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3848 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3852 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
,
3853 VkPipelineStageFlags stageMask
, unsigned value
)
3855 struct tu_cs
*cs
= &cmd
->cs
;
3857 /* vkCmdSetEvent/vkCmdResetEvent cannot be called inside a render pass */
3858 assert(!cmd
->state
.pass
);
3860 tu_emit_cache_flush(cmd
, cs
);
3862 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3864 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
3865 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
3867 VkPipelineStageFlags top_of_pipe_flags
=
3868 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
3869 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
;
3871 if (!(stageMask
& ~top_of_pipe_flags
)) {
3872 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3873 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3874 tu_cs_emit(cs
, value
);
3876 /* Use a RB_DONE_TS event to wait for everything to complete. */
3877 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 4);
3878 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS
));
3879 tu_cs_emit_qw(cs
, event
->bo
.iova
);
3880 tu_cs_emit(cs
, value
);
3885 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3887 VkPipelineStageFlags stageMask
)
3889 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3890 TU_FROM_HANDLE(tu_event
, event
, _event
);
3892 write_event(cmd
, event
, stageMask
, 1);
3896 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3898 VkPipelineStageFlags stageMask
)
3900 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3901 TU_FROM_HANDLE(tu_event
, event
, _event
);
3903 write_event(cmd
, event
, stageMask
, 0);
3907 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3908 uint32_t eventCount
,
3909 const VkEvent
*pEvents
,
3910 VkPipelineStageFlags srcStageMask
,
3911 VkPipelineStageFlags dstStageMask
,
3912 uint32_t memoryBarrierCount
,
3913 const VkMemoryBarrier
*pMemoryBarriers
,
3914 uint32_t bufferMemoryBarrierCount
,
3915 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3916 uint32_t imageMemoryBarrierCount
,
3917 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3919 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3920 struct tu_barrier_info info
;
3922 info
.eventCount
= eventCount
;
3923 info
.pEvents
= pEvents
;
3924 info
.srcStageMask
= 0;
3926 tu_barrier(cmd
, memoryBarrierCount
, pMemoryBarriers
,
3927 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3928 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3932 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)