src/freedreno/vulkan/tu_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 #include "tu_private.h"
  29
  30 #include "registers/adreno_pm4.xml.h"
  31 #include "registers/adreno_common.xml.h"
  32 #include "registers/a6xx.xml.h"
  33
  34 #include "vk_format.h"
  35
  36 #include "tu_cs.h"
  37 #include "tu_blit.h"
  38
  39 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
  40
  41 void
  42 tu_bo_list_init(struct tu_bo_list *list)
  43 {
  44    list->count = list->capacity = 0;
  45    list->bo_infos = NULL;
  46 }
  47
  48 void
  49 tu_bo_list_destroy(struct tu_bo_list *list)
  50 {
  51    free(list->bo_infos);
  52 }
  53
  54 void
  55 tu_bo_list_reset(struct tu_bo_list *list)
  56 {
  57    list->count = 0;
  58 }
  59
  60 /**
  61  * \a flags consists of MSM_SUBMIT_BO_FLAGS.
  62  */
  63 static uint32_t
  64 tu_bo_list_add_info(struct tu_bo_list *list,
  65                     const struct drm_msm_gem_submit_bo *bo_info)
  66 {
  67    assert(bo_info->handle != 0);
  68
  69    for (uint32_t i = 0; i < list->count; ++i) {
  70       if (list->bo_infos[i].handle == bo_info->handle) {
  71          assert(list->bo_infos[i].presumed == bo_info->presumed);
  72          list->bo_infos[i].flags |= bo_info->flags;
  73          return i;
  74       }
  75    }
  76
  77    /* grow list->bo_infos if needed */
  78    if (list->count == list->capacity) {
  79       uint32_t new_capacity = MAX2(2 * list->count, 16);
  80       struct drm_msm_gem_submit_bo *new_bo_infos = realloc(
  81          list->bo_infos, new_capacity * sizeof(struct drm_msm_gem_submit_bo));
  82       if (!new_bo_infos)
  83          return TU_BO_LIST_FAILED;
  84       list->bo_infos = new_bo_infos;
  85       list->capacity = new_capacity;
  86    }
  87
  88    list->bo_infos[list->count] = *bo_info;
  89    return list->count++;
  90 }
  91
  92 uint32_t
  93 tu_bo_list_add(struct tu_bo_list *list,
  94                const struct tu_bo *bo,
  95                uint32_t flags)
  96 {
  97    return tu_bo_list_add_info(list, &(struct drm_msm_gem_submit_bo) {
  98                                        .flags = flags,
  99                                        .handle = bo->gem_handle,
 100                                        .presumed = bo->iova,
 101                                     });
 102 }
 103
 104 VkResult
 105 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other)
 106 {
 107    for (uint32_t i = 0; i < other->count; i++) {
 108       if (tu_bo_list_add_info(list, other->bo_infos + i) == TU_BO_LIST_FAILED)
 109          return VK_ERROR_OUT_OF_HOST_MEMORY;
 110    }
 111
 112    return VK_SUCCESS;
 113 }
 114
 115 static VkResult
 116 tu_tiling_config_update_gmem_layout(struct tu_tiling_config *tiling,
 117                                     const struct tu_device *dev)
 118 {
 119    const uint32_t gmem_size = dev->physical_device->gmem_size;
 120    uint32_t offset = 0;
 121
 122    for (uint32_t i = 0; i < tiling->buffer_count; i++) {
 123       /* 16KB-aligned */
 124       offset = align(offset, 0x4000);
 125
 126       tiling->gmem_offsets[i] = offset;
 127       offset += tiling->tile0.extent.width * tiling->tile0.extent.height *
 128                 tiling->buffer_cpp[i];
 129    }
 130
 131    return offset <= gmem_size ? VK_SUCCESS : VK_ERROR_OUT_OF_DEVICE_MEMORY;
 132 }
 133
 134 static void
 135 tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
 136                                     const struct tu_device *dev)
 137 {
 138    const uint32_t tile_align_w = dev->physical_device->tile_align_w;
 139    const uint32_t tile_align_h = dev->physical_device->tile_align_h;
 140    const uint32_t max_tile_width = 1024; /* A6xx */
 141
 142    tiling->tile0.offset = (VkOffset2D) {
 143       .x = tiling->render_area.offset.x & ~(tile_align_w - 1),
 144       .y = tiling->render_area.offset.y & ~(tile_align_h - 1),
 145    };
 146
 147    const uint32_t ra_width =
 148       tiling->render_area.extent.width +
 149       (tiling->render_area.offset.x - tiling->tile0.offset.x);
 150    const uint32_t ra_height =
 151       tiling->render_area.extent.height +
 152       (tiling->render_area.offset.y - tiling->tile0.offset.y);
 153
 154    /* start from 1 tile */
 155    tiling->tile_count = (VkExtent2D) {
 156       .width = 1,
 157       .height = 1,
 158    };
 159    tiling->tile0.extent = (VkExtent2D) {
 160       .width = align(ra_width, tile_align_w),
 161       .height = align(ra_height, tile_align_h),
 162    };
 163
 164    /* do not exceed max tile width */
 165    while (tiling->tile0.extent.width > max_tile_width) {
 166       tiling->tile_count.width++;
 167       tiling->tile0.extent.width =
 168          align(ra_width / tiling->tile_count.width, tile_align_w);
 169    }
 170
 171    /* do not exceed gmem size */
 172    while (tu_tiling_config_update_gmem_layout(tiling, dev) != VK_SUCCESS) {
 173       if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
 174          tiling->tile_count.width++;
 175          tiling->tile0.extent.width =
 176             align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
 177       } else {
 178          /* if this assert fails then layout is impossible.. */
 179          assert(tiling->tile0.extent.height > tile_align_h);
 180          tiling->tile_count.height++;
 181          tiling->tile0.extent.height =
 182             align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), tile_align_h);
 183       }
 184    }
 185 }
 186
 187 static void
 188 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
 189                                     const struct tu_device *dev)
 190 {
 191    const uint32_t max_pipe_count = 32; /* A6xx */
 192
 193    /* start from 1 tile per pipe */
 194    tiling->pipe0 = (VkExtent2D) {
 195       .width = 1,
 196       .height = 1,
 197    };
 198    tiling->pipe_count = tiling->tile_count;
 199
 200    /* do not exceed max pipe count vertically */
 201    while (tiling->pipe_count.height > max_pipe_count) {
 202       tiling->pipe0.height += 2;
 203       tiling->pipe_count.height =
 204          (tiling->tile_count.height + tiling->pipe0.height - 1) /
 205          tiling->pipe0.height;
 206    }
 207
 208    /* do not exceed max pipe count */
 209    while (tiling->pipe_count.width * tiling->pipe_count.height >
 210           max_pipe_count) {
 211       tiling->pipe0.width += 1;
 212       tiling->pipe_count.width =
 213          (tiling->tile_count.width + tiling->pipe0.width - 1) /
 214          tiling->pipe0.width;
 215    }
 216 }
 217
 218 static void
 219 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
 220                               const struct tu_device *dev)
 221 {
 222    const uint32_t max_pipe_count = 32; /* A6xx */
 223    const uint32_t used_pipe_count =
 224       tiling->pipe_count.width * tiling->pipe_count.height;
 225    const VkExtent2D last_pipe = {
 226       .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
 227       .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
 228    };
 229
 230    assert(used_pipe_count <= max_pipe_count);
 231    assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
 232
 233    for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
 234       for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
 235          const uint32_t pipe_x = tiling->pipe0.width * x;
 236          const uint32_t pipe_y = tiling->pipe0.height * y;
 237          const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
 238                                     ? last_pipe.width
 239                                     : tiling->pipe0.width;
 240          const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
 241                                     ? last_pipe.height
 242                                     : tiling->pipe0.height;
 243          const uint32_t n = tiling->pipe_count.width * y + x;
 244
 245          tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
 246                                   A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
 247                                   A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
 248                                   A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
 249          tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
 250       }
 251    }
 252
 253    memset(tiling->pipe_config + used_pipe_count, 0,
 254           sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
 255 }
 256
 257 static void
 258 tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
 259                           const struct tu_device *dev,
 260                           uint32_t tx,
 261                           uint32_t ty,
 262                           struct tu_tile *tile)
 263 {
 264    /* find the pipe and the slot for tile (tx, ty) */
 265    const uint32_t px = tx / tiling->pipe0.width;
 266    const uint32_t py = ty / tiling->pipe0.height;
 267    const uint32_t sx = tx - tiling->pipe0.width * px;
 268    const uint32_t sy = ty - tiling->pipe0.height * py;
 269
 270    assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
 271    assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
 272    assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
 273
 274    /* convert to 1D indices */
 275    tile->pipe = tiling->pipe_count.width * py + px;
 276    tile->slot = tiling->pipe0.width * sy + sx;
 277
 278    /* get the blit area for the tile */
 279    tile->begin = (VkOffset2D) {
 280       .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
 281       .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
 282    };
 283    tile->end.x =
 284       (tx == tiling->tile_count.width - 1)
 285          ? tiling->render_area.offset.x + tiling->render_area.extent.width
 286          : tile->begin.x + tiling->tile0.extent.width;
 287    tile->end.y =
 288       (ty == tiling->tile_count.height - 1)
 289          ? tiling->render_area.offset.y + tiling->render_area.extent.height
 290          : tile->begin.y + tiling->tile0.extent.height;
 291 }
 292
 293 enum a3xx_msaa_samples
 294 tu_msaa_samples(uint32_t samples)
 295 {
 296    switch (samples) {
 297    case 1:
 298       return MSAA_ONE;
 299    case 2:
 300       return MSAA_TWO;
 301    case 4:
 302       return MSAA_FOUR;
 303    case 8:
 304       return MSAA_EIGHT;
 305    default:
 306       assert(!"invalid sample count");
 307       return MSAA_ONE;
 308    }
 309 }
 310
 311 static enum a4xx_index_size
 312 tu6_index_size(VkIndexType type)
 313 {
 314    switch (type) {
 315    case VK_INDEX_TYPE_UINT16:
 316       return INDEX4_SIZE_16_BIT;
 317    case VK_INDEX_TYPE_UINT32:
 318       return INDEX4_SIZE_32_BIT;
 319    default:
 320       unreachable("invalid VkIndexType");
 321       return INDEX4_SIZE_8_BIT;
 322    }
 323 }
 324
 325 static void
 326 tu6_emit_marker(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 327 {
 328    tu_cs_emit_write_reg(cs, cmd->marker_reg, ++cmd->marker_seqno);
 329 }
 330
 331 unsigned
 332 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
 333                      struct tu_cs *cs,
 334                      enum vgt_event_type event,
 335                      bool need_seqno)
 336 {
 337    unsigned seqno = 0;
 338
 339    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
 340    tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
 341    if (need_seqno) {
 342       tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
 343       seqno = ++cmd->scratch_seqno;
 344       tu_cs_emit(cs, seqno);
 345    }
 346
 347    return seqno;
 348 }
 349
 350 static void
 351 tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 352 {
 353    tu6_emit_event_write(cmd, cs, 0x31, false);
 354 }
 355
 356 static void
 357 tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 358 {
 359    tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
 360 }
 361
 362 static void
 363 tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 364 {
 365    if (cmd->wait_for_idle) {
 366       tu_cs_emit_wfi(cs);
 367       cmd->wait_for_idle = false;
 368    }
 369 }
 370
 371 static void
 372 tu6_emit_flag_buffer(struct tu_cs *cs, const struct tu_image_view *iview)
 373 {
 374    uint64_t va = tu_image_ubwc_base(iview->image, iview->base_mip, iview->base_layer);
 375    uint32_t pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip);
 376    uint32_t size = tu_image_ubwc_size(iview->image, iview->base_mip);
 377    if (iview->image->layout.ubwc_size) {
 378       tu_cs_emit_qw(cs, va);
 379       tu_cs_emit(cs, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(pitch) |
 380                      A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(size >> 2));
 381    } else {
 382       tu_cs_emit_qw(cs, 0);
 383       tu_cs_emit(cs, 0);
 384    }
 385 }
 386
 387 static void
 388 tu6_emit_zs(struct tu_cmd_buffer *cmd,
 389             const struct tu_subpass *subpass,
 390             struct tu_cs *cs)
 391 {
 392    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 393    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 394
 395    const uint32_t a = subpass->depth_stencil_attachment.attachment;
 396    if (a == VK_ATTACHMENT_UNUSED) {
 397       tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
 398       tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
 399       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
 400       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
 401       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
 402       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
 403       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
 404
 405       tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
 406       tu_cs_emit(cs,
 407                  A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
 408
 409       tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
 410       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
 411       tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
 412       tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
 413       tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
 414       tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
 415
 416       tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
 417       tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
 418
 419       return;
 420    }
 421
 422    const struct tu_image_view *iview = fb->attachments[a].attachment;
 423    enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
 424
 425    tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
 426    tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
 427    tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)));
 428    tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layout.layer_size));
 429    tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
 430    tu_cs_emit(cs, tiling->gmem_offsets[a]);
 431
 432    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
 433    tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
 434
 435    tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
 436    tu6_emit_flag_buffer(cs, iview);
 437
 438    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
 439    tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
 440    tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
 441    tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
 442    tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
 443    tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
 444
 445    tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
 446    tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
 447
 448    /* enable zs? */
 449 }
 450
 451 static void
 452 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
 453              const struct tu_subpass *subpass,
 454              struct tu_cs *cs)
 455 {
 456    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 457    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 458    unsigned char mrt_comp[MAX_RTS] = { 0 };
 459    unsigned srgb_cntl = 0;
 460
 461    for (uint32_t i = 0; i < subpass->color_count; ++i) {
 462       uint32_t a = subpass->color_attachments[i].attachment;
 463       if (a == VK_ATTACHMENT_UNUSED)
 464          continue;
 465
 466       const struct tu_image_view *iview = fb->attachments[a].attachment;
 467       const enum a6xx_tile_mode tile_mode =
 468          tu6_get_image_tile_mode(iview->image, iview->base_mip);
 469
 470       mrt_comp[i] = 0xf;
 471
 472       if (vk_format_is_srgb(iview->vk_format))
 473          srgb_cntl |= (1 << i);
 474
 475       const struct tu_native_format *format =
 476          tu6_get_native_format(iview->vk_format);
 477       assert(format && format->rb >= 0);
 478
 479       tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
 480       tu_cs_emit(cs, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format->rb) |
 481                         A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
 482                         A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format->swap));
 483       tu_cs_emit(cs, A6XX_RB_MRT_PITCH(tu_image_stride(iview->image, iview->base_mip)));
 484       tu_cs_emit(cs, A6XX_RB_MRT_ARRAY_PITCH(iview->image->layout.layer_size));
 485       tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
 486       tu_cs_emit(
 487          cs, tiling->gmem_offsets[a]); /* RB_MRT[i].BASE_GMEM */
 488
 489       tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_MRT_REG(i), 1);
 490       tu_cs_emit(cs, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format->rb) |
 491                      COND(vk_format_is_sint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_SINT) |
 492                      COND(vk_format_is_uint(iview->vk_format), A6XX_SP_FS_MRT_REG_COLOR_UINT));
 493
 494       tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
 495       tu6_emit_flag_buffer(cs, iview);
 496    }
 497
 498    tu_cs_emit_pkt4(cs, REG_A6XX_RB_SRGB_CNTL, 1);
 499    tu_cs_emit(cs, srgb_cntl);
 500
 501    tu_cs_emit_pkt4(cs, REG_A6XX_SP_SRGB_CNTL, 1);
 502    tu_cs_emit(cs, srgb_cntl);
 503
 504    tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_COMPONENTS, 1);
 505    tu_cs_emit(cs, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
 506                      A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
 507                      A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
 508                      A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
 509                      A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
 510                      A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
 511                      A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
 512                      A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
 513
 514    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
 515    tu_cs_emit(cs, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
 516                      A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
 517                      A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
 518                      A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
 519                      A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
 520                      A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
 521                      A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
 522                      A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
 523 }
 524
 525 static void
 526 tu6_emit_msaa(struct tu_cmd_buffer *cmd,
 527               const struct tu_subpass *subpass,
 528               struct tu_cs *cs)
 529 {
 530    const enum a3xx_msaa_samples samples = tu_msaa_samples(subpass->samples);
 531
 532    tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
 533    tu_cs_emit(cs, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
 534    tu_cs_emit(cs, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
 535               COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
 536
 537    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
 538    tu_cs_emit(cs, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
 539    tu_cs_emit(cs, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
 540               COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
 541
 542    tu_cs_emit_pkt4(cs, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
 543    tu_cs_emit(cs, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
 544    tu_cs_emit(cs, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
 545               COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
 546
 547    tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_CNTL, 1);
 548    tu_cs_emit(cs, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
 549 }
 550
 551 static void
 552 tu6_emit_bin_size(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t flags)
 553 {
 554    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 555    const uint32_t bin_w = tiling->tile0.extent.width;
 556    const uint32_t bin_h = tiling->tile0.extent.height;
 557
 558    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_BIN_CONTROL, 1);
 559    tu_cs_emit(cs, A6XX_GRAS_BIN_CONTROL_BINW(bin_w) |
 560                      A6XX_GRAS_BIN_CONTROL_BINH(bin_h) | flags);
 561
 562    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL, 1);
 563    tu_cs_emit(cs, A6XX_RB_BIN_CONTROL_BINW(bin_w) |
 564                      A6XX_RB_BIN_CONTROL_BINH(bin_h) | flags);
 565
 566    /* no flag for RB_BIN_CONTROL2... */
 567    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BIN_CONTROL2, 1);
 568    tu_cs_emit(cs, A6XX_RB_BIN_CONTROL2_BINW(bin_w) |
 569                      A6XX_RB_BIN_CONTROL2_BINH(bin_h));
 570 }
 571
 572 static void
 573 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
 574                      struct tu_cs *cs,
 575                      bool binning)
 576 {
 577    uint32_t cntl = 0;
 578    cntl |= A6XX_RB_RENDER_CNTL_UNK4;
 579    if (binning)
 580       cntl |= A6XX_RB_RENDER_CNTL_BINNING;
 581
 582    tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
 583    tu_cs_emit(cs, 0x2);
 584    tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
 585    tu_cs_emit(cs, cntl);
 586 }
 587
 588 static void
 589 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
 590 {
 591    const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
 592    uint32_t x1 = render_area->offset.x;
 593    uint32_t y1 = render_area->offset.y;
 594    uint32_t x2 = x1 + render_area->extent.width - 1;
 595    uint32_t y2 = y1 + render_area->extent.height - 1;
 596
 597    /* TODO: alignment requirement seems to be less than tile_align_w/h */
 598    if (align) {
 599       x1 = x1 & ~cmd->device->physical_device->tile_align_w;
 600       y1 = y1 & ~cmd->device->physical_device->tile_align_h;
 601       x2 = ALIGN_POT(x2 + 1, cmd->device->physical_device->tile_align_w) - 1;
 602       y2 = ALIGN_POT(y2 + 1, cmd->device->physical_device->tile_align_h) - 1;
 603    }
 604
 605    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
 606    tu_cs_emit(cs,
 607               A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
 608    tu_cs_emit(cs,
 609               A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
 610 }
 611
 612 static void
 613 tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
 614                    struct tu_cs *cs,
 615                    const struct tu_image_view *iview,
 616                    uint32_t gmem_offset,
 617                    bool resolve)
 618 {
 619    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
 620    tu_cs_emit(cs, resolve ? 0 : (A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM));
 621
 622    const struct tu_native_format *format =
 623       tu6_get_native_format(iview->vk_format);
 624    assert(format && format->rb >= 0);
 625
 626    enum a6xx_tile_mode tile_mode =
 627       tu6_get_image_tile_mode(iview->image, iview->base_mip);
 628    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 5);
 629    tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
 630                      A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview->image->samples)) |
 631                      A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb) |
 632                      A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format->swap) |
 633                      COND(iview->image->layout.ubwc_size,
 634                           A6XX_RB_BLIT_DST_INFO_FLAGS));
 635    tu_cs_emit_qw(cs, tu_image_base(iview->image, iview->base_mip, iview->base_layer));
 636    tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)));
 637    tu_cs_emit(cs, A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layout.layer_size));
 638
 639    if (iview->image->layout.ubwc_size) {
 640       tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
 641       tu6_emit_flag_buffer(cs, iview);
 642    }
 643
 644    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 645    tu_cs_emit(cs, gmem_offset);
 646 }
 647
 648 static void
 649 tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 650 {
 651    tu6_emit_marker(cmd, cs);
 652    tu6_emit_event_write(cmd, cs, BLIT, false);
 653    tu6_emit_marker(cmd, cs);
 654 }
 655
 656 static void
 657 tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
 658                         struct tu_cs *cs,
 659                         uint32_t x1,
 660                         uint32_t y1,
 661                         uint32_t x2,
 662                         uint32_t y2)
 663 {
 664    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 665    tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
 666                      A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
 667    tu_cs_emit(cs, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
 668                      A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
 669
 670    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
 671    tu_cs_emit(
 672       cs, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
 673    tu_cs_emit(
 674       cs, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
 675 }
 676
 677 static void
 678 tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
 679                        struct tu_cs *cs,
 680                        uint32_t x1,
 681                        uint32_t y1)
 682 {
 683    tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
 684    tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
 685
 686    tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET2, 1);
 687    tu_cs_emit(cs,
 688               A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
 689
 690    tu_cs_emit_pkt4(cs, REG_A6XX_SP_WINDOW_OFFSET, 1);
 691    tu_cs_emit(cs, A6XX_SP_WINDOW_OFFSET_X(x1) | A6XX_SP_WINDOW_OFFSET_Y(y1));
 692
 693    tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
 694    tu_cs_emit(
 695       cs, A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
 696 }
 697
 698 static bool
 699 use_hw_binning(struct tu_cmd_buffer *cmd)
 700 {
 701    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 702
 703    if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
 704       return false;
 705
 706    return (tiling->tile_count.width * tiling->tile_count.height) > 2;
 707 }
 708
 709 static void
 710 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
 711                      struct tu_cs *cs,
 712                      const struct tu_tile *tile)
 713 {
 714    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 715    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
 716
 717    tu6_emit_marker(cmd, cs);
 718    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 719    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
 720    tu6_emit_marker(cmd, cs);
 721
 722    const uint32_t x1 = tile->begin.x;
 723    const uint32_t y1 = tile->begin.y;
 724    const uint32_t x2 = tile->end.x - 1;
 725    const uint32_t y2 = tile->end.y - 1;
 726    tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
 727    tu6_emit_window_offset(cmd, cs, x1, y1);
 728
 729    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_OVERRIDE, 1);
 730    tu_cs_emit(cs, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
 731
 732    if (use_hw_binning(cmd)) {
 733       tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
 734
 735       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 736       tu_cs_emit(cs, 0x0);
 737
 738       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
 739       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
 740                      A6XX_CP_REG_TEST_0_BIT(0) |
 741                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
 742
 743       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
 744       tu_cs_emit(cs, 0x10000000);
 745       tu_cs_emit(cs, 11); /* conditionally execute next 11 dwords */
 746
 747       /* if (no overflow) */ {
 748          tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
 749          tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
 750                         CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
 751          tu_cs_emit_qw(cs, cmd->vsc_data.iova + tile->pipe * cmd->vsc_data_pitch);
 752          tu_cs_emit_qw(cs, cmd->vsc_data.iova + (tile->pipe * 4) + (32 * cmd->vsc_data_pitch));
 753          tu_cs_emit_qw(cs, cmd->vsc_data2.iova + (tile->pipe * cmd->vsc_data2_pitch));
 754
 755          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 756          tu_cs_emit(cs, 0x0);
 757
 758          /* use a NOP packet to skip over the 'else' side: */
 759          tu_cs_emit_pkt7(cs, CP_NOP, 2);
 760       } /* else */ {
 761          tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 762          tu_cs_emit(cs, 0x1);
 763       }
 764
 765       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 766       tu_cs_emit(cs, 0x0);
 767
 768       tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_8804, 1);
 769       tu_cs_emit(cs, 0x0);
 770
 771       tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 1);
 772       tu_cs_emit(cs, 0x0);
 773
 774       tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 1);
 775       tu_cs_emit(cs, 0x0);
 776    } else {
 777       tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
 778       tu_cs_emit(cs, 0x1);
 779
 780       tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
 781       tu_cs_emit(cs, 0x0);
 782    }
 783 }
 784
 785 static void
 786 tu6_emit_load_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a)
 787 {
 788    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 789    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 790    const struct tu_image_view *iview = fb->attachments[a].attachment;
 791    const struct tu_render_pass_attachment *attachment =
 792       &cmd->state.pass->attachments[a];
 793
 794    if (!attachment->needs_gmem)
 795       return;
 796
 797    const uint32_t x1 = tiling->render_area.offset.x;
 798    const uint32_t y1 = tiling->render_area.offset.y;
 799    const uint32_t x2 = x1 + tiling->render_area.extent.width;
 800    const uint32_t y2 = y1 + tiling->render_area.extent.height;
 801    const uint32_t tile_x2 =
 802       tiling->tile0.offset.x + tiling->tile0.extent.width * tiling->tile_count.width;
 803    const uint32_t tile_y2 =
 804       tiling->tile0.offset.y + tiling->tile0.extent.height * tiling->tile_count.height;
 805    bool need_load =
 806       x1 != tiling->tile0.offset.x || x2 != MIN2(fb->width, tile_x2) ||
 807       y1 != tiling->tile0.offset.y || y2 != MIN2(fb->height, tile_y2);
 808
 809    if (need_load)
 810       tu_finishme("improve handling of unaligned render area");
 811
 812    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
 813       need_load = true;
 814
 815    if (vk_format_has_stencil(iview->vk_format) &&
 816        attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
 817       need_load = true;
 818
 819    if (need_load) {
 820       tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[a], false);
 821       tu6_emit_blit(cmd, cs);
 822    }
 823 }
 824
 825 static void
 826 tu6_emit_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
 827                           uint32_t a,
 828                           const VkRenderPassBeginInfo *info)
 829 {
 830    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
 831    const struct tu_framebuffer *fb = cmd->state.framebuffer;
 832    const struct tu_image_view *iview = fb->attachments[a].attachment;
 833    const struct tu_render_pass_attachment *attachment =
 834       &cmd->state.pass->attachments[a];
 835    unsigned clear_mask = 0;
 836
 837    /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
 838    if (!attachment->needs_gmem)
 839       return;
 840
 841    if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
 842       clear_mask = 0xf;
 843
 844    if (vk_format_has_stencil(iview->vk_format)) {
 845       clear_mask &= 0x1;
 846       if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
 847          clear_mask |= 0x2;
 848    }
 849    if (!clear_mask)
 850       return;
 851
 852    const struct tu_native_format *format =
 853       tu6_get_native_format(iview->vk_format);
 854    assert(format && format->rb >= 0);
 855
 856    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
 857    tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format->rb));
 858
 859    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_INFO, 1);
 860    tu_cs_emit(cs, A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(clear_mask));
 861
 862    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 863    tu_cs_emit(cs, tiling->gmem_offsets[a]);
 864
 865    tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
 866    tu_cs_emit(cs, 0);
 867
 868    uint32_t clear_vals[4] = { 0 };
 869    tu_pack_clear_value(&info->pClearValues[a], iview->vk_format, clear_vals);
 870
 871    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
 872    tu_cs_emit(cs, clear_vals[0]);
 873    tu_cs_emit(cs, clear_vals[1]);
 874    tu_cs_emit(cs, clear_vals[2]);
 875    tu_cs_emit(cs, clear_vals[3]);
 876
 877    tu6_emit_blit(cmd, cs);
 878 }
 879
 880 static void
 881 tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
 882                           struct tu_cs *cs,
 883                           uint32_t a,
 884                           uint32_t gmem_a)
 885 {
 886    if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
 887       return;
 888
 889    tu6_emit_blit_info(cmd, cs,
 890                       cmd->state.framebuffer->attachments[a].attachment,
 891                       cmd->state.tiling_config.gmem_offsets[gmem_a], true);
 892    tu6_emit_blit(cmd, cs);
 893 }
 894
 895 static void
 896 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 897 {
 898    const struct tu_render_pass *pass = cmd->state.pass;
 899    const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
 900
 901    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
 902    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
 903                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
 904                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
 905    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
 906    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
 907
 908    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 909    tu_cs_emit(cs, 0x0);
 910
 911    tu6_emit_marker(cmd, cs);
 912    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
 913    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
 914    tu6_emit_marker(cmd, cs);
 915
 916    tu6_emit_blit_scissor(cmd, cs, true);
 917
 918    for (uint32_t a = 0; a < pass->attachment_count; ++a) {
 919       if (pass->attachments[a].needs_gmem)
 920          tu6_emit_store_attachment(cmd, cs, a, a);
 921    }
 922
 923    if (subpass->resolve_attachments) {
 924       for (unsigned i = 0; i < subpass->color_count; i++) {
 925          uint32_t a = subpass->resolve_attachments[i].attachment;
 926          if (a != VK_ATTACHMENT_UNUSED)
 927             tu6_emit_store_attachment(cmd, cs, a,
 928                                       subpass->color_attachments[i].attachment);
 929       }
 930    }
 931 }
 932
 933 static void
 934 tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
 935 {
 936    tu_cs_emit_pkt4(cs, REG_A6XX_PC_RESTART_INDEX, 1);
 937    tu_cs_emit(cs, restart_index);
 938 }
 939
 940 static void
 941 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 942 {
 943    VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
 944    if (result != VK_SUCCESS) {
 945       cmd->record_result = result;
 946       return;
 947    }
 948
 949    tu6_emit_cache_flush(cmd, cs);
 950
 951    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
 952
 953    tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
 954    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
 955    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
 956    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
 957    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
 958    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B605, 0x44);
 959    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B600, 0x100000);
 960    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
 961    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
 962
 963    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
 964    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
 965    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
 966    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
 967    tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
 968    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
 969    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
 970    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
 971    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
 972    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
 973    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
 974    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
 975    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
 976    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
 977
 978    tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
 979
 980    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
 981    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
 982    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
 983
 984    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
 985    tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
 986    tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
 987    tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
 988    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
 989    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
 990    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
 991    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
 992    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
 993    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
 994    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
 995    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
 996
 997    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
 998    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
 999
1000    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
1001    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
1002
1003    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
1004                         A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
1005
1006    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
1007    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
1008    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
1009
1010    tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
1011    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
1012
1013    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
1014
1015    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
1016
1017    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
1018    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
1019    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1020    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1021    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
1022    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
1023    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
1024    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
1025    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
1026    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
1027    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
1028    tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
1029    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
1030    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
1031    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
1032    tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
1033    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
1034    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
1035    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
1036    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
1037    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1038
1039    tu6_emit_marker(cmd, cs);
1040
1041    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
1042
1043    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
1044
1045    tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f);
1046
1047    /* we don't use this yet.. probably best to disable.. */
1048    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1049    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1050                      CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1051                      CP_SET_DRAW_STATE__0_GROUP_ID(0));
1052    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1053    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1054
1055    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1056    tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1057    tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1058    tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1059
1060    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1061    tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1062    tu_cs_emit(cs, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1063
1064    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1065    tu_cs_emit(cs, 0x00000000); /* VPC_SO_BUF_CNTL */
1066
1067    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1068    tu_cs_emit(cs, 0x00000000); /* UNKNOWN_E2AB */
1069
1070    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1071    tu_cs_emit(cs, 0x00000000);
1072    tu_cs_emit(cs, 0x00000000);
1073    tu_cs_emit(cs, 0x00000000);
1074
1075    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1076    tu_cs_emit(cs, 0x00000000);
1077    tu_cs_emit(cs, 0x00000000);
1078    tu_cs_emit(cs, 0x00000000);
1079    tu_cs_emit(cs, 0x00000000);
1080    tu_cs_emit(cs, 0x00000000);
1081    tu_cs_emit(cs, 0x00000000);
1082
1083    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1084    tu_cs_emit(cs, 0x00000000);
1085    tu_cs_emit(cs, 0x00000000);
1086    tu_cs_emit(cs, 0x00000000);
1087    tu_cs_emit(cs, 0x00000000);
1088    tu_cs_emit(cs, 0x00000000);
1089    tu_cs_emit(cs, 0x00000000);
1090
1091    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1092    tu_cs_emit(cs, 0x00000000);
1093    tu_cs_emit(cs, 0x00000000);
1094    tu_cs_emit(cs, 0x00000000);
1095
1096    tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CTRL_REG0, 1);
1097    tu_cs_emit(cs, 0x00000000);
1098
1099    tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1100    tu_cs_emit(cs, 0x00000000);
1101
1102    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1103    tu_cs_emit(cs, 0x00000000);
1104
1105    tu_cs_emit_pkt4(cs, REG_A6XX_RB_LRZ_CNTL, 1);
1106    tu_cs_emit(cs, 0x00000000);
1107
1108    tu_cs_sanity_check(cs);
1109 }
1110
1111 static void
1112 tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1113 {
1114    unsigned seqno;
1115
1116    seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_AND_INV_EVENT, true);
1117
1118    tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
1119    tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1120                   CP_WAIT_REG_MEM_0_POLL_MEMORY);
1121    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1122    tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(seqno));
1123    tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
1124    tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1125
1126    seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1127
1128    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4);
1129    tu_cs_emit(cs, CP_WAIT_MEM_GTE_0_RESERVED(0));
1130    tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
1131    tu_cs_emit(cs, CP_WAIT_MEM_GTE_3_REF(seqno));
1132 }
1133
1134 static void
1135 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1136 {
1137    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1138
1139    tu_cs_emit_pkt4(cs, REG_A6XX_VSC_BIN_SIZE, 3);
1140    tu_cs_emit(cs, A6XX_VSC_BIN_SIZE_WIDTH(tiling->tile0.extent.width) |
1141                   A6XX_VSC_BIN_SIZE_HEIGHT(tiling->tile0.extent.height));
1142    tu_cs_emit_qw(cs, cmd->vsc_data.iova + 32 * cmd->vsc_data_pitch); /* VSC_SIZE_ADDRESS_LO/HI */
1143
1144    tu_cs_emit_pkt4(cs, REG_A6XX_VSC_BIN_COUNT, 1);
1145    tu_cs_emit(cs, A6XX_VSC_BIN_COUNT_NX(tiling->tile_count.width) |
1146                   A6XX_VSC_BIN_COUNT_NY(tiling->tile_count.height));
1147
1148    tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
1149    for (unsigned i = 0; i < 32; i++)
1150       tu_cs_emit(cs, tiling->pipe_config[i]);
1151
1152    tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO, 4);
1153    tu_cs_emit_qw(cs, cmd->vsc_data2.iova);
1154    tu_cs_emit(cs, cmd->vsc_data2_pitch);
1155    tu_cs_emit(cs, cmd->vsc_data2.size);
1156
1157    tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO, 4);
1158    tu_cs_emit_qw(cs, cmd->vsc_data.iova);
1159    tu_cs_emit(cs, cmd->vsc_data_pitch);
1160    tu_cs_emit(cs, cmd->vsc_data.size);
1161 }
1162
1163 static void
1164 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1165 {
1166    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1167    const uint32_t used_pipe_count =
1168       tiling->pipe_count.width * tiling->pipe_count.height;
1169
1170    /* Clear vsc_scratch: */
1171    tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
1172    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1173    tu_cs_emit(cs, 0x0);
1174
1175    /* Check for overflow, write vsc_scratch if detected: */
1176    for (int i = 0; i < used_pipe_count; i++) {
1177       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1178       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1179             CP_COND_WRITE5_0_WRITE_MEMORY);
1180       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
1181       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1182       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data_pitch));
1183       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1184       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1185       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_data_pitch));
1186
1187       tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1188       tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1189             CP_COND_WRITE5_0_WRITE_MEMORY);
1190       tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
1191       tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1192       tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data2_pitch));
1193       tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1194       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1195       tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_data2_pitch));
1196    }
1197
1198    tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1199
1200    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1201
1202    tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
1203    tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
1204          CP_MEM_TO_REG_0_CNT(1 - 1));
1205    tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_SCRATCH);
1206
1207    /*
1208     * This is a bit awkward, we really want a way to invert the
1209     * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
1210     * execute cmds to use hwbinning when a bit is *not* set.  This
1211     * dance is to invert OVERFLOW_FLAG_REG
1212     *
1213     * A CP_NOP packet is used to skip executing the 'else' clause
1214     * if (b0 set)..
1215     */
1216
1217    /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
1218    tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1219    tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1220          A6XX_CP_REG_TEST_0_BIT(0) |
1221          A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1222
1223    tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1224    tu_cs_emit(cs, 0x10000000);
1225    tu_cs_emit(cs, 7);  /* conditionally execute next 7 dwords */
1226
1227    /* if (b0 set) */ {
1228       /*
1229        * On overflow, mirror the value to control->vsc_overflow
1230        * which CPU is checking to detect overflow (see
1231        * check_vsc_overflow())
1232        */
1233       tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
1234       tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
1235             CP_REG_TO_MEM_0_CNT(0));
1236       tu_cs_emit_qw(cs, cmd->scratch_bo.iova + VSC_OVERFLOW);
1237
1238       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1239       tu_cs_emit(cs, 0x0);
1240
1241       tu_cs_emit_pkt7(cs, CP_NOP, 2);  /* skip 'else' when 'if' is taken */
1242    } /* else */ {
1243       tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
1244       tu_cs_emit(cs, 0x1);
1245    }
1246 }
1247
1248 static void
1249 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1250 {
1251    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1252
1253    uint32_t x1 = tiling->tile0.offset.x;
1254    uint32_t y1 = tiling->tile0.offset.y;
1255    uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
1256    uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
1257
1258    tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
1259
1260    tu6_emit_marker(cmd, cs);
1261    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1262    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
1263    tu6_emit_marker(cmd, cs);
1264
1265    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1266    tu_cs_emit(cs, 0x1);
1267
1268    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1269    tu_cs_emit(cs, 0x1);
1270
1271    tu_cs_emit_wfi(cs);
1272
1273    tu_cs_emit_pkt4(cs, REG_A6XX_VFD_MODE_CNTL, 1);
1274    tu_cs_emit(cs, A6XX_VFD_MODE_CNTL_BINNING_PASS);
1275
1276    update_vsc_pipe(cmd, cs);
1277
1278    tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9805, 1);
1279    tu_cs_emit(cs, 0x1);
1280
1281    tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A0F8, 1);
1282    tu_cs_emit(cs, 0x1);
1283
1284    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1285    tu_cs_emit(cs, UNK_2C);
1286
1287    tu_cs_emit_pkt4(cs, REG_A6XX_RB_WINDOW_OFFSET, 1);
1288    tu_cs_emit(cs, A6XX_RB_WINDOW_OFFSET_X(0) |
1289                   A6XX_RB_WINDOW_OFFSET_Y(0));
1290
1291    tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
1292    tu_cs_emit(cs, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
1293                   A6XX_SP_TP_WINDOW_OFFSET_Y(0));
1294
1295    /* emit IB to binning drawcmds: */
1296    tu_cs_emit_call(cs, &cmd->draw_cs);
1297
1298    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1299    tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1300                   CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1301                   CP_SET_DRAW_STATE__0_GROUP_ID(0));
1302    tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1303    tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1304
1305    tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1306    tu_cs_emit(cs, UNK_2D);
1307
1308    tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
1309    tu6_cache_flush(cmd, cs);
1310
1311    tu_cs_emit_wfi(cs);
1312
1313    tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1314
1315    emit_vsc_overflow_test(cmd, cs);
1316
1317    tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1318    tu_cs_emit(cs, 0x0);
1319
1320    tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1321    tu_cs_emit(cs, 0x0);
1322
1323    tu_cs_emit_wfi(cs);
1324
1325    tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1326    tu_cs_emit(cs, 0x7c400004);
1327
1328    cmd->wait_for_idle = false;
1329 }
1330
1331 static void
1332 tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1333 {
1334    VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
1335    if (result != VK_SUCCESS) {
1336       cmd->record_result = result;
1337       return;
1338    }
1339
1340    tu6_emit_lrz_flush(cmd, cs);
1341
1342    /* lrz clear? */
1343
1344    tu6_emit_cache_flush(cmd, cs);
1345
1346    tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1347    tu_cs_emit(cs, 0x0);
1348
1349    /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1350    tu6_emit_wfi(cmd, cs);
1351    tu_cs_emit_pkt4(cs, REG_A6XX_RB_CCU_CNTL, 1);
1352    tu_cs_emit(cs, 0x7c400004); /* RB_CCU_CNTL */
1353
1354    if (use_hw_binning(cmd)) {
1355       tu6_emit_bin_size(cmd, cs, A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
1356
1357       tu6_emit_render_cntl(cmd, cs, true);
1358
1359       tu6_emit_binning_pass(cmd, cs);
1360
1361       tu6_emit_bin_size(cmd, cs, A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
1362
1363       tu_cs_emit_pkt4(cs, REG_A6XX_VFD_MODE_CNTL, 1);
1364       tu_cs_emit(cs, 0x0);
1365
1366       tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9805, 1);
1367       tu_cs_emit(cs, 0x1);
1368
1369       tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A0F8, 1);
1370       tu_cs_emit(cs, 0x1);
1371
1372       tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1373       tu_cs_emit(cs, 0x1);
1374    } else {
1375       tu6_emit_bin_size(cmd, cs, 0x6000000);
1376    }
1377
1378    tu6_emit_render_cntl(cmd, cs, false);
1379
1380    tu_cs_sanity_check(cs);
1381 }
1382
1383 static void
1384 tu6_render_tile(struct tu_cmd_buffer *cmd,
1385                 struct tu_cs *cs,
1386                 const struct tu_tile *tile)
1387 {
1388    const uint32_t render_tile_space = 256 + tu_cs_get_call_size(&cmd->draw_cs);
1389    VkResult result = tu_cs_reserve_space(cmd->device, cs, render_tile_space);
1390    if (result != VK_SUCCESS) {
1391       cmd->record_result = result;
1392       return;
1393    }
1394
1395    tu6_emit_tile_select(cmd, cs, tile);
1396    tu_cs_emit_ib(cs, &cmd->state.tile_load_ib);
1397
1398    tu_cs_emit_call(cs, &cmd->draw_cs);
1399    cmd->wait_for_idle = true;
1400
1401    if (use_hw_binning(cmd)) {
1402       tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1403       tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1404                      A6XX_CP_REG_TEST_0_BIT(0) |
1405                      A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1406
1407       tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1408       tu_cs_emit(cs, 0x10000000);
1409       tu_cs_emit(cs, 2);  /* conditionally execute next 2 dwords */
1410
1411       /* if (no overflow) */ {
1412          tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1413          tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1414       }
1415    }
1416
1417    tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
1418
1419    tu_cs_sanity_check(cs);
1420 }
1421
1422 static void
1423 tu6_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1424 {
1425    VkResult result = tu_cs_reserve_space(cmd->device, cs, 16);
1426    if (result != VK_SUCCESS) {
1427       cmd->record_result = result;
1428       return;
1429    }
1430
1431    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_CNTL, 1);
1432    tu_cs_emit(cs, 0);
1433
1434    tu6_emit_lrz_flush(cmd, cs);
1435
1436    tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
1437
1438    tu_cs_sanity_check(cs);
1439 }
1440
1441 static void
1442 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
1443 {
1444    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1445
1446    tu6_render_begin(cmd, &cmd->cs);
1447
1448    for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
1449       for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
1450          struct tu_tile tile;
1451          tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
1452          tu6_render_tile(cmd, &cmd->cs, &tile);
1453       }
1454    }
1455
1456    tu6_render_end(cmd, &cmd->cs);
1457 }
1458
1459 static void
1460 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer *cmd,
1461                             const VkRenderPassBeginInfo *info)
1462 {
1463    const uint32_t tile_load_space =
1464       8 + (23+19) * cmd->state.pass->attachment_count +
1465       21 + (13 * cmd->state.subpass->color_count + 8) + 11;
1466
1467    struct tu_cs sub_cs;
1468
1469    VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs,
1470                                             tile_load_space, &sub_cs);
1471    if (result != VK_SUCCESS) {
1472       cmd->record_result = result;
1473       return;
1474    }
1475
1476    tu6_emit_blit_scissor(cmd, &sub_cs, true);
1477
1478    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1479       tu6_emit_load_attachment(cmd, &sub_cs, i);
1480
1481    tu6_emit_blit_scissor(cmd, &sub_cs, false);
1482
1483    for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1484       tu6_emit_clear_attachment(cmd, &sub_cs, i, info);
1485
1486    /* invalidate because reading input attachments will cache GMEM and
1487     * the cache isn''t updated when GMEM is written
1488     * TODO: is there a no-cache bit for textures?
1489     */
1490    if (cmd->state.subpass->input_count)
1491       tu6_emit_event_write(cmd, &sub_cs, CACHE_INVALIDATE, false);
1492
1493    tu6_emit_zs(cmd, cmd->state.subpass, &sub_cs);
1494    tu6_emit_mrt(cmd, cmd->state.subpass, &sub_cs);
1495    tu6_emit_msaa(cmd, cmd->state.subpass, &sub_cs);
1496
1497    cmd->state.tile_load_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1498 }
1499
1500 static void
1501 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
1502 {
1503    const uint32_t tile_store_space = 32 + 23 * cmd->state.pass->attachment_count;
1504    struct tu_cs sub_cs;
1505
1506    VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs,
1507                                             tile_store_space, &sub_cs);
1508    if (result != VK_SUCCESS) {
1509       cmd->record_result = result;
1510       return;
1511    }
1512
1513    /* emit to tile-store sub_cs */
1514    tu6_emit_tile_store(cmd, &sub_cs);
1515
1516    cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
1517 }
1518
1519 static void
1520 tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
1521                             const VkRect2D *render_area)
1522 {
1523    const struct tu_device *dev = cmd->device;
1524    const struct tu_render_pass *pass = cmd->state.pass;
1525    struct tu_tiling_config *tiling = &cmd->state.tiling_config;
1526
1527    tiling->render_area = *render_area;
1528    for (uint32_t a = 0; a < pass->attachment_count; a++) {
1529       if (pass->attachments[a].needs_gmem)
1530          tiling->buffer_cpp[a] = pass->attachments[a].cpp;
1531       else
1532          tiling->buffer_cpp[a] = 0;
1533    }
1534    tiling->buffer_count = pass->attachment_count;
1535
1536    tu_tiling_config_update_tile_layout(tiling, dev);
1537    tu_tiling_config_update_pipe_layout(tiling, dev);
1538    tu_tiling_config_update_pipes(tiling, dev);
1539 }
1540
1541 const struct tu_dynamic_state default_dynamic_state = {
1542    .viewport =
1543      {
1544        .count = 0,
1545      },
1546    .scissor =
1547      {
1548        .count = 0,
1549      },
1550    .line_width = 1.0f,
1551    .depth_bias =
1552      {
1553        .bias = 0.0f,
1554        .clamp = 0.0f,
1555        .slope = 0.0f,
1556      },
1557    .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
1558    .depth_bounds =
1559      {
1560        .min = 0.0f,
1561        .max = 1.0f,
1562      },
1563    .stencil_compare_mask =
1564      {
1565        .front = ~0u,
1566        .back = ~0u,
1567      },
1568    .stencil_write_mask =
1569      {
1570        .front = ~0u,
1571        .back = ~0u,
1572      },
1573    .stencil_reference =
1574      {
1575        .front = 0u,
1576        .back = 0u,
1577      },
1578 };
1579
1580 static void UNUSED /* FINISHME */
1581 tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
1582                       const struct tu_dynamic_state *src)
1583 {
1584    struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
1585    uint32_t copy_mask = src->mask;
1586    uint32_t dest_mask = 0;
1587
1588    tu_use_args(cmd_buffer); /* FINISHME */
1589
1590    /* Make sure to copy the number of viewports/scissors because they can
1591     * only be specified at pipeline creation time.
1592     */
1593    dest->viewport.count = src->viewport.count;
1594    dest->scissor.count = src->scissor.count;
1595    dest->discard_rectangle.count = src->discard_rectangle.count;
1596
1597    if (copy_mask & TU_DYNAMIC_VIEWPORT) {
1598       if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
1599                  src->viewport.count * sizeof(VkViewport))) {
1600          typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
1601                       src->viewport.count);
1602          dest_mask |= TU_DYNAMIC_VIEWPORT;
1603       }
1604    }
1605
1606    if (copy_mask & TU_DYNAMIC_SCISSOR) {
1607       if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
1608                  src->scissor.count * sizeof(VkRect2D))) {
1609          typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
1610                       src->scissor.count);
1611          dest_mask |= TU_DYNAMIC_SCISSOR;
1612       }
1613    }
1614
1615    if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
1616       if (dest->line_width != src->line_width) {
1617          dest->line_width = src->line_width;
1618          dest_mask |= TU_DYNAMIC_LINE_WIDTH;
1619       }
1620    }
1621
1622    if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
1623       if (memcmp(&dest->depth_bias, &src->depth_bias,
1624                  sizeof(src->depth_bias))) {
1625          dest->depth_bias = src->depth_bias;
1626          dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
1627       }
1628    }
1629
1630    if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
1631       if (memcmp(&dest->blend_constants, &src->blend_constants,
1632                  sizeof(src->blend_constants))) {
1633          typed_memcpy(dest->blend_constants, src->blend_constants, 4);
1634          dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
1635       }
1636    }
1637
1638    if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
1639       if (memcmp(&dest->depth_bounds, &src->depth_bounds,
1640                  sizeof(src->depth_bounds))) {
1641          dest->depth_bounds = src->depth_bounds;
1642          dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
1643       }
1644    }
1645
1646    if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
1647       if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
1648                  sizeof(src->stencil_compare_mask))) {
1649          dest->stencil_compare_mask = src->stencil_compare_mask;
1650          dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
1651       }
1652    }
1653
1654    if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
1655       if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
1656                  sizeof(src->stencil_write_mask))) {
1657          dest->stencil_write_mask = src->stencil_write_mask;
1658          dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
1659       }
1660    }
1661
1662    if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
1663       if (memcmp(&dest->stencil_reference, &src->stencil_reference,
1664                  sizeof(src->stencil_reference))) {
1665          dest->stencil_reference = src->stencil_reference;
1666          dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
1667       }
1668    }
1669
1670    if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
1671       if (memcmp(&dest->discard_rectangle.rectangles,
1672                  &src->discard_rectangle.rectangles,
1673                  src->discard_rectangle.count * sizeof(VkRect2D))) {
1674          typed_memcpy(dest->discard_rectangle.rectangles,
1675                       src->discard_rectangle.rectangles,
1676                       src->discard_rectangle.count);
1677          dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
1678       }
1679    }
1680 }
1681
1682 static VkResult
1683 tu_create_cmd_buffer(struct tu_device *device,
1684                      struct tu_cmd_pool *pool,
1685                      VkCommandBufferLevel level,
1686                      VkCommandBuffer *pCommandBuffer)
1687 {
1688    struct tu_cmd_buffer *cmd_buffer;
1689    cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
1690                           VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1691    if (cmd_buffer == NULL)
1692       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1693
1694    cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1695    cmd_buffer->device = device;
1696    cmd_buffer->pool = pool;
1697    cmd_buffer->level = level;
1698
1699    if (pool) {
1700       list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1701       cmd_buffer->queue_family_index = pool->queue_family_index;
1702
1703    } else {
1704       /* Init the pool_link so we can safely call list_del when we destroy
1705        * the command buffer
1706        */
1707       list_inithead(&cmd_buffer->pool_link);
1708       cmd_buffer->queue_family_index = TU_QUEUE_GENERAL;
1709    }
1710
1711    tu_bo_list_init(&cmd_buffer->bo_list);
1712    tu_cs_init(&cmd_buffer->cs, TU_CS_MODE_GROW, 4096);
1713    tu_cs_init(&cmd_buffer->draw_cs, TU_CS_MODE_GROW, 4096);
1714    tu_cs_init(&cmd_buffer->sub_cs, TU_CS_MODE_SUB_STREAM, 2048);
1715
1716    *pCommandBuffer = tu_cmd_buffer_to_handle(cmd_buffer);
1717
1718    list_inithead(&cmd_buffer->upload.list);
1719
1720    cmd_buffer->marker_reg = REG_A6XX_CP_SCRATCH_REG(
1721       cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY ? 7 : 6);
1722
1723    VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
1724    if (result != VK_SUCCESS)
1725       return result;
1726
1727 #define VSC_DATA_SIZE(pitch)  ((pitch) * 32 + 0x100)  /* extra size to store VSC_SIZE */
1728 #define VSC_DATA2_SIZE(pitch) ((pitch) * 32)
1729
1730    /* TODO: resize on overflow or compute a max size from # of vertices in renderpass?? */
1731    cmd_buffer->vsc_data_pitch = 0x440 * 4;
1732    cmd_buffer->vsc_data2_pitch = 0x1040 * 4;
1733
1734    result = tu_bo_init_new(device, &cmd_buffer->vsc_data, VSC_DATA_SIZE(cmd_buffer->vsc_data_pitch));
1735    if (result != VK_SUCCESS)
1736       goto fail_vsc_data;
1737
1738    result = tu_bo_init_new(device, &cmd_buffer->vsc_data2, VSC_DATA2_SIZE(cmd_buffer->vsc_data2_pitch));
1739    if (result != VK_SUCCESS)
1740       goto fail_vsc_data2;
1741
1742    return VK_SUCCESS;
1743
1744 fail_vsc_data2:
1745    tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data);
1746 fail_vsc_data:
1747    tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1748    return result;
1749 }
1750
1751 static void
1752 tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
1753 {
1754    tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
1755    tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data);
1756    tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data2);
1757
1758    list_del(&cmd_buffer->pool_link);
1759
1760    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
1761       free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
1762
1763    tu_cs_finish(cmd_buffer->device, &cmd_buffer->cs);
1764    tu_cs_finish(cmd_buffer->device, &cmd_buffer->draw_cs);
1765    tu_cs_finish(cmd_buffer->device, &cmd_buffer->sub_cs);
1766
1767    tu_bo_list_destroy(&cmd_buffer->bo_list);
1768    vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
1769 }
1770
1771 static VkResult
1772 tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
1773 {
1774    cmd_buffer->wait_for_idle = true;
1775
1776    cmd_buffer->record_result = VK_SUCCESS;
1777
1778    tu_bo_list_reset(&cmd_buffer->bo_list);
1779    tu_cs_reset(cmd_buffer->device, &cmd_buffer->cs);
1780    tu_cs_reset(cmd_buffer->device, &cmd_buffer->draw_cs);
1781    tu_cs_reset(cmd_buffer->device, &cmd_buffer->sub_cs);
1782
1783    for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
1784       cmd_buffer->descriptors[i].dirty = 0;
1785       cmd_buffer->descriptors[i].valid = 0;
1786       cmd_buffer->descriptors[i].push_dirty = false;
1787    }
1788
1789    cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
1790
1791    return cmd_buffer->record_result;
1792 }
1793
1794 VkResult
1795 tu_AllocateCommandBuffers(VkDevice _device,
1796                           const VkCommandBufferAllocateInfo *pAllocateInfo,
1797                           VkCommandBuffer *pCommandBuffers)
1798 {
1799    TU_FROM_HANDLE(tu_device, device, _device);
1800    TU_FROM_HANDLE(tu_cmd_pool, pool, pAllocateInfo->commandPool);
1801
1802    VkResult result = VK_SUCCESS;
1803    uint32_t i;
1804
1805    for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1806
1807       if (!list_is_empty(&pool->free_cmd_buffers)) {
1808          struct tu_cmd_buffer *cmd_buffer = list_first_entry(
1809             &pool->free_cmd_buffers, struct tu_cmd_buffer, pool_link);
1810
1811          list_del(&cmd_buffer->pool_link);
1812          list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1813
1814          result = tu_reset_cmd_buffer(cmd_buffer);
1815          cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1816          cmd_buffer->level = pAllocateInfo->level;
1817
1818          pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
1819       } else {
1820          result = tu_create_cmd_buffer(device, pool, pAllocateInfo->level,
1821                                        &pCommandBuffers[i]);
1822       }
1823       if (result != VK_SUCCESS)
1824          break;
1825    }
1826
1827    if (result != VK_SUCCESS) {
1828       tu_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i,
1829                             pCommandBuffers);
1830
1831       /* From the Vulkan 1.0.66 spec:
1832        *
1833        * "vkAllocateCommandBuffers can be used to create multiple
1834        *  command buffers. If the creation of any of those command
1835        *  buffers fails, the implementation must destroy all
1836        *  successfully created command buffer objects from this
1837        *  command, set all entries of the pCommandBuffers array to
1838        *  NULL and return the error."
1839        */
1840       memset(pCommandBuffers, 0,
1841              sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1842    }
1843
1844    return result;
1845 }
1846
1847 void
1848 tu_FreeCommandBuffers(VkDevice device,
1849                       VkCommandPool commandPool,
1850                       uint32_t commandBufferCount,
1851                       const VkCommandBuffer *pCommandBuffers)
1852 {
1853    for (uint32_t i = 0; i < commandBufferCount; i++) {
1854       TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1855
1856       if (cmd_buffer) {
1857          if (cmd_buffer->pool) {
1858             list_del(&cmd_buffer->pool_link);
1859             list_addtail(&cmd_buffer->pool_link,
1860                          &cmd_buffer->pool->free_cmd_buffers);
1861          } else
1862             tu_cmd_buffer_destroy(cmd_buffer);
1863       }
1864    }
1865 }
1866
1867 VkResult
1868 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer,
1869                       VkCommandBufferResetFlags flags)
1870 {
1871    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1872    return tu_reset_cmd_buffer(cmd_buffer);
1873 }
1874
1875 VkResult
1876 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
1877                       const VkCommandBufferBeginInfo *pBeginInfo)
1878 {
1879    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1880    VkResult result = VK_SUCCESS;
1881
1882    if (cmd_buffer->status != TU_CMD_BUFFER_STATUS_INITIAL) {
1883       /* If the command buffer has already been resetted with
1884        * vkResetCommandBuffer, no need to do it again.
1885        */
1886       result = tu_reset_cmd_buffer(cmd_buffer);
1887       if (result != VK_SUCCESS)
1888          return result;
1889    }
1890
1891    memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1892    cmd_buffer->usage_flags = pBeginInfo->flags;
1893
1894    tu_cs_begin(&cmd_buffer->cs);
1895    tu_cs_begin(&cmd_buffer->draw_cs);
1896
1897    cmd_buffer->marker_seqno = 0;
1898    cmd_buffer->scratch_seqno = 0;
1899
1900    /* setup initial configuration into command buffer */
1901    if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1902       switch (cmd_buffer->queue_family_index) {
1903       case TU_QUEUE_GENERAL:
1904          tu6_init_hw(cmd_buffer, &cmd_buffer->cs);
1905          break;
1906       default:
1907          break;
1908       }
1909    }
1910
1911    cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
1912
1913    return VK_SUCCESS;
1914 }
1915
1916 void
1917 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
1918                         uint32_t firstBinding,
1919                         uint32_t bindingCount,
1920                         const VkBuffer *pBuffers,
1921                         const VkDeviceSize *pOffsets)
1922 {
1923    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1924
1925    assert(firstBinding + bindingCount <= MAX_VBS);
1926
1927    for (uint32_t i = 0; i < bindingCount; i++) {
1928       cmd->state.vb.buffers[firstBinding + i] =
1929          tu_buffer_from_handle(pBuffers[i]);
1930       cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
1931    }
1932
1933    /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1934    cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1935 }
1936
1937 void
1938 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer,
1939                       VkBuffer buffer,
1940                       VkDeviceSize offset,
1941                       VkIndexType indexType)
1942 {
1943    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
1944    TU_FROM_HANDLE(tu_buffer, buf, buffer);
1945
1946    /* initialize/update the restart index */
1947    if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
1948       struct tu_cs *draw_cs = &cmd->draw_cs;
1949       VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 2);
1950       if (result != VK_SUCCESS) {
1951          cmd->record_result = result;
1952          return;
1953       }
1954
1955       tu6_emit_restart_index(
1956          draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
1957
1958       tu_cs_sanity_check(draw_cs);
1959    }
1960
1961    /* track the BO */
1962    if (cmd->state.index_buffer != buf)
1963       tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
1964
1965    cmd->state.index_buffer = buf;
1966    cmd->state.index_offset = offset;
1967    cmd->state.index_type = indexType;
1968 }
1969
1970 void
1971 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
1972                          VkPipelineBindPoint pipelineBindPoint,
1973                          VkPipelineLayout _layout,
1974                          uint32_t firstSet,
1975                          uint32_t descriptorSetCount,
1976                          const VkDescriptorSet *pDescriptorSets,
1977                          uint32_t dynamicOffsetCount,
1978                          const uint32_t *pDynamicOffsets)
1979 {
1980    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
1981    TU_FROM_HANDLE(tu_pipeline_layout, layout, _layout);
1982    unsigned dyn_idx = 0;
1983
1984    struct tu_descriptor_state *descriptors_state =
1985       tu_get_descriptors_state(cmd_buffer, pipelineBindPoint);
1986
1987    for (unsigned i = 0; i < descriptorSetCount; ++i) {
1988       unsigned idx = i + firstSet;
1989       TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
1990
1991       descriptors_state->sets[idx] = set;
1992       descriptors_state->valid |= (1u << idx);
1993
1994       for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
1995          unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
1996          assert(dyn_idx < dynamicOffsetCount);
1997
1998          descriptors_state->dynamic_buffers[idx] =
1999          set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
2000       }
2001    }
2002
2003    cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
2004 }
2005
2006 void
2007 tu_CmdPushConstants(VkCommandBuffer commandBuffer,
2008                     VkPipelineLayout layout,
2009                     VkShaderStageFlags stageFlags,
2010                     uint32_t offset,
2011                     uint32_t size,
2012                     const void *pValues)
2013 {
2014    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2015    memcpy((void*) cmd->push_constants + offset, pValues, size);
2016    cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
2017 }
2018
2019 VkResult
2020 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
2021 {
2022    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2023
2024    if (cmd_buffer->scratch_seqno) {
2025       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
2026                      MSM_SUBMIT_BO_WRITE);
2027    }
2028
2029    if (cmd_buffer->use_vsc_data) {
2030       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data,
2031                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2032       tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data2,
2033                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2034    }
2035
2036    for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
2037       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
2038                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2039    }
2040
2041    for (uint32_t i = 0; i < cmd_buffer->sub_cs.bo_count; i++) {
2042       tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->sub_cs.bos[i],
2043                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2044    }
2045
2046    tu_cs_end(&cmd_buffer->cs);
2047    tu_cs_end(&cmd_buffer->draw_cs);
2048
2049    cmd_buffer->status = TU_CMD_BUFFER_STATUS_EXECUTABLE;
2050
2051    return cmd_buffer->record_result;
2052 }
2053
2054 void
2055 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
2056                    VkPipelineBindPoint pipelineBindPoint,
2057                    VkPipeline _pipeline)
2058 {
2059    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2060    TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2061
2062    switch (pipelineBindPoint) {
2063    case VK_PIPELINE_BIND_POINT_GRAPHICS:
2064       cmd->state.pipeline = pipeline;
2065       cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
2066       break;
2067    case VK_PIPELINE_BIND_POINT_COMPUTE:
2068       cmd->state.compute_pipeline = pipeline;
2069       cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
2070       break;
2071    default:
2072       unreachable("unrecognized pipeline bind point");
2073       break;
2074    }
2075
2076    tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
2077                   MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2078    for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
2079       tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
2080                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
2081    }
2082 }
2083
2084 void
2085 tu_CmdSetViewport(VkCommandBuffer commandBuffer,
2086                   uint32_t firstViewport,
2087                   uint32_t viewportCount,
2088                   const VkViewport *pViewports)
2089 {
2090    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2091    struct tu_cs *draw_cs = &cmd->draw_cs;
2092
2093    VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 12);
2094    if (result != VK_SUCCESS) {
2095       cmd->record_result = result;
2096       return;
2097    }
2098
2099    assert(firstViewport == 0 && viewportCount == 1);
2100    tu6_emit_viewport(draw_cs, pViewports);
2101
2102    tu_cs_sanity_check(draw_cs);
2103 }
2104
2105 void
2106 tu_CmdSetScissor(VkCommandBuffer commandBuffer,
2107                  uint32_t firstScissor,
2108                  uint32_t scissorCount,
2109                  const VkRect2D *pScissors)
2110 {
2111    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2112    struct tu_cs *draw_cs = &cmd->draw_cs;
2113
2114    VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 3);
2115    if (result != VK_SUCCESS) {
2116       cmd->record_result = result;
2117       return;
2118    }
2119
2120    assert(firstScissor == 0 && scissorCount == 1);
2121    tu6_emit_scissor(draw_cs, pScissors);
2122
2123    tu_cs_sanity_check(draw_cs);
2124 }
2125
2126 void
2127 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
2128 {
2129    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2130
2131    cmd->state.dynamic.line_width = lineWidth;
2132
2133    /* line width depends on VkPipelineRasterizationStateCreateInfo */
2134    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2135 }
2136
2137 void
2138 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer,
2139                    float depthBiasConstantFactor,
2140                    float depthBiasClamp,
2141                    float depthBiasSlopeFactor)
2142 {
2143    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2144    struct tu_cs *draw_cs = &cmd->draw_cs;
2145
2146    VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 4);
2147    if (result != VK_SUCCESS) {
2148       cmd->record_result = result;
2149       return;
2150    }
2151
2152    tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
2153                        depthBiasSlopeFactor);
2154
2155    tu_cs_sanity_check(draw_cs);
2156 }
2157
2158 void
2159 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer,
2160                         const float blendConstants[4])
2161 {
2162    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2163    struct tu_cs *draw_cs = &cmd->draw_cs;
2164
2165    VkResult result = tu_cs_reserve_space(cmd->device, draw_cs, 5);
2166    if (result != VK_SUCCESS) {
2167       cmd->record_result = result;
2168       return;
2169    }
2170
2171    tu6_emit_blend_constants(draw_cs, blendConstants);
2172
2173    tu_cs_sanity_check(draw_cs);
2174 }
2175
2176 void
2177 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer,
2178                      float minDepthBounds,
2179                      float maxDepthBounds)
2180 {
2181 }
2182
2183 void
2184 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer,
2185                             VkStencilFaceFlags faceMask,
2186                             uint32_t compareMask)
2187 {
2188    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2189
2190    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2191       cmd->state.dynamic.stencil_compare_mask.front = compareMask;
2192    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2193       cmd->state.dynamic.stencil_compare_mask.back = compareMask;
2194
2195    /* the front/back compare masks must be updated together */
2196    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2197 }
2198
2199 void
2200 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer,
2201                           VkStencilFaceFlags faceMask,
2202                           uint32_t writeMask)
2203 {
2204    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2205
2206    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2207       cmd->state.dynamic.stencil_write_mask.front = writeMask;
2208    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2209       cmd->state.dynamic.stencil_write_mask.back = writeMask;
2210
2211    /* the front/back write masks must be updated together */
2212    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2213 }
2214
2215 void
2216 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer,
2217                           VkStencilFaceFlags faceMask,
2218                           uint32_t reference)
2219 {
2220    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2221
2222    if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2223       cmd->state.dynamic.stencil_reference.front = reference;
2224    if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2225       cmd->state.dynamic.stencil_reference.back = reference;
2226
2227    /* the front/back references must be updated together */
2228    cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2229 }
2230
2231 void
2232 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
2233                       uint32_t commandBufferCount,
2234                       const VkCommandBuffer *pCmdBuffers)
2235 {
2236 }
2237
2238 VkResult
2239 tu_CreateCommandPool(VkDevice _device,
2240                      const VkCommandPoolCreateInfo *pCreateInfo,
2241                      const VkAllocationCallbacks *pAllocator,
2242                      VkCommandPool *pCmdPool)
2243 {
2244    TU_FROM_HANDLE(tu_device, device, _device);
2245    struct tu_cmd_pool *pool;
2246
2247    pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2248                     VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2249    if (pool == NULL)
2250       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2251
2252    if (pAllocator)
2253       pool->alloc = *pAllocator;
2254    else
2255       pool->alloc = device->alloc;
2256
2257    list_inithead(&pool->cmd_buffers);
2258    list_inithead(&pool->free_cmd_buffers);
2259
2260    pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2261
2262    *pCmdPool = tu_cmd_pool_to_handle(pool);
2263
2264    return VK_SUCCESS;
2265 }
2266
2267 void
2268 tu_DestroyCommandPool(VkDevice _device,
2269                       VkCommandPool commandPool,
2270                       const VkAllocationCallbacks *pAllocator)
2271 {
2272    TU_FROM_HANDLE(tu_device, device, _device);
2273    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2274
2275    if (!pool)
2276       return;
2277
2278    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2279                             &pool->cmd_buffers, pool_link)
2280    {
2281       tu_cmd_buffer_destroy(cmd_buffer);
2282    }
2283
2284    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2285                             &pool->free_cmd_buffers, pool_link)
2286    {
2287       tu_cmd_buffer_destroy(cmd_buffer);
2288    }
2289
2290    vk_free2(&device->alloc, pAllocator, pool);
2291 }
2292
2293 VkResult
2294 tu_ResetCommandPool(VkDevice device,
2295                     VkCommandPool commandPool,
2296                     VkCommandPoolResetFlags flags)
2297 {
2298    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2299    VkResult result;
2300
2301    list_for_each_entry(struct tu_cmd_buffer, cmd_buffer, &pool->cmd_buffers,
2302                        pool_link)
2303    {
2304       result = tu_reset_cmd_buffer(cmd_buffer);
2305       if (result != VK_SUCCESS)
2306          return result;
2307    }
2308
2309    return VK_SUCCESS;
2310 }
2311
2312 void
2313 tu_TrimCommandPool(VkDevice device,
2314                    VkCommandPool commandPool,
2315                    VkCommandPoolTrimFlags flags)
2316 {
2317    TU_FROM_HANDLE(tu_cmd_pool, pool, commandPool);
2318
2319    if (!pool)
2320       return;
2321
2322    list_for_each_entry_safe(struct tu_cmd_buffer, cmd_buffer,
2323                             &pool->free_cmd_buffers, pool_link)
2324    {
2325       tu_cmd_buffer_destroy(cmd_buffer);
2326    }
2327 }
2328
2329 void
2330 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
2331                       const VkRenderPassBeginInfo *pRenderPassBegin,
2332                       VkSubpassContents contents)
2333 {
2334    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2335    TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
2336    TU_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
2337
2338    cmd->state.pass = pass;
2339    cmd->state.subpass = pass->subpasses;
2340    cmd->state.framebuffer = fb;
2341
2342    tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
2343    tu_cmd_prepare_tile_load_ib(cmd, pRenderPassBegin);
2344    tu_cmd_prepare_tile_store_ib(cmd);
2345
2346    /* note: use_hw_binning only checks tiling config */
2347    if (use_hw_binning(cmd))
2348       cmd->use_vsc_data = true;
2349
2350    for (uint32_t i = 0; i < fb->attachment_count; ++i) {
2351       const struct tu_image_view *iview = fb->attachments[i].attachment;
2352       tu_bo_list_add(&cmd->bo_list, iview->image->bo,
2353                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
2354    }
2355 }
2356
2357 void
2358 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer,
2359                           const VkRenderPassBeginInfo *pRenderPassBeginInfo,
2360                           const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
2361 {
2362    tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
2363                          pSubpassBeginInfo->contents);
2364 }
2365
2366 void
2367 tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
2368 {
2369    TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2370    const struct tu_render_pass *pass = cmd->state.pass;
2371    const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2372    struct tu_cs *cs = &cmd->draw_cs;
2373
2374    VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
2375    if (result != VK_SUCCESS) {
2376       cmd->record_result = result;
2377       return;
2378    }
2379
2380    const struct tu_subpass *subpass = cmd->state.subpass++;
2381    /* TODO:
2382     * if msaa samples change between subpasses,
2383     * attachment store is broken for some attachments
2384     */
2385    if (subpass->resolve_attachments) {
2386       tu6_emit_blit_scissor(cmd, cs, true);
2387       for (unsigned i = 0; i < subpass->color_count; i++) {
2388          uint32_t a = subpass->resolve_attachments[i].attachment;
2389          if (a != VK_ATTACHMENT_UNUSED) {
2390                tu6_emit_store_attachment(cmd, cs, a,
2391                                          subpass->color_attachments[i].attachment);
2392          }
2393       }
2394    }
2395
2396    /* invalidate because reading input attachments will cache GMEM and
2397     * the cache isn''t updated when GMEM is written
2398     * TODO: is there a no-cache bit for textures?
2399     */
2400    if (cmd->state.subpass->input_count)
2401       tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
2402
2403    /* emit mrt/zs/msaa state for the subpass that is starting */
2404    tu6_emit_zs(cmd, cmd->state.subpass, cs);
2405    tu6_emit_mrt(cmd, cmd->state.subpass, cs);
2406    tu6_emit_msaa(cmd, cmd->state.subpass, cs);
2407
2408    /* TODO:
2409     * since we don't know how to do GMEM->GMEM resolve,
2410     * resolve attachments are resolved to memory then loaded to GMEM again if needed
2411     */
2412    if (subpass->resolve_attachments) {
2413       for (unsigned i = 0; i < subpass->color_count; i++) {
2414          uint32_t a = subpass->resolve_attachments[i].attachment;
2415          const struct tu_image_view *iview =
2416             cmd->state.framebuffer->attachments[a].attachment;
2417          if (a != VK_ATTACHMENT_UNUSED && pass->attachments[a].needs_gmem) {
2418                tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
2419                tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[a], false);
2420                tu6_emit_blit(cmd, cs);
2421          }
2422       }
2423    }
2424 }
2425
2426 void
2427 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer,
2428                       const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
2429                       const VkSubpassEndInfoKHR *pSubpassEndInfo)
2430 {
2431    tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
2432 }
2433
2434 struct tu_draw_info
2435 {
2436    /**
2437     * Number of vertices.
2438     */
2439    uint32_t count;
2440
2441    /**
2442     * Index of the first vertex.
2443     */
2444    int32_t vertex_offset;
2445
2446    /**
2447     * First instance id.
2448     */
2449    uint32_t first_instance;
2450
2451    /**
2452     * Number of instances.
2453     */
2454    uint32_t instance_count;
2455
2456    /**
2457     * First index (indexed draws only).
2458     */
2459    uint32_t first_index;
2460
2461    /**
2462     * Whether it's an indexed draw.
2463     */
2464    bool indexed;
2465
2466    /**
2467     * Indirect draw parameters resource.
2468     */
2469    struct tu_buffer *indirect;
2470    uint64_t indirect_offset;
2471    uint32_t stride;
2472
2473    /**
2474     * Draw count parameters resource.
2475     */
2476    struct tu_buffer *count_buffer;
2477    uint64_t count_buffer_offset;
2478 };
2479
2480 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2481 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
2482
2483 enum tu_draw_state_group_id
2484 {
2485    TU_DRAW_STATE_PROGRAM,
2486    TU_DRAW_STATE_PROGRAM_BINNING,
2487    TU_DRAW_STATE_VI,
2488    TU_DRAW_STATE_VI_BINNING,
2489    TU_DRAW_STATE_VP,
2490    TU_DRAW_STATE_RAST,
2491    TU_DRAW_STATE_DS,
2492    TU_DRAW_STATE_BLEND,
2493    TU_DRAW_STATE_VS_CONST,
2494    TU_DRAW_STATE_FS_CONST,
2495    TU_DRAW_STATE_VS_TEX,
2496    TU_DRAW_STATE_FS_TEX,
2497    TU_DRAW_STATE_FS_IBO,
2498    TU_DRAW_STATE_VS_PARAMS,
2499
2500    TU_DRAW_STATE_COUNT,
2501 };
2502
2503 struct tu_draw_state_group
2504 {
2505    enum tu_draw_state_group_id id;
2506    uint32_t enable_mask;
2507    struct tu_cs_entry ib;
2508 };
2509
2510 const static struct tu_sampler*
2511 sampler_ptr(struct tu_descriptor_state *descriptors_state,
2512             const struct tu_descriptor_map *map, unsigned i,
2513             unsigned array_index)
2514 {
2515    assert(descriptors_state->valid & (1 << map->set[i]));
2516
2517    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2518    assert(map->binding[i] < set->layout->binding_count);
2519
2520    const struct tu_descriptor_set_binding_layout *layout =
2521       &set->layout->binding[map->binding[i]];
2522
2523    if (layout->immutable_samplers_offset) {
2524       const struct tu_sampler *immutable_samplers =
2525          tu_immutable_samplers(set->layout, layout);
2526
2527       return &immutable_samplers[array_index];
2528    }
2529
2530    switch (layout->type) {
2531    case VK_DESCRIPTOR_TYPE_SAMPLER:
2532       return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4];
2533    case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2534       return (struct tu_sampler*) &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS +
2535                                                    array_index *
2536                                                    (A6XX_TEX_CONST_DWORDS +
2537                                                     sizeof(struct tu_sampler) / 4)];
2538    default:
2539       unreachable("unimplemented descriptor type");
2540       break;
2541    }
2542 }
2543
2544 static void
2545 write_tex_const(struct tu_cmd_buffer *cmd,
2546                 uint32_t *dst,
2547                 struct tu_descriptor_state *descriptors_state,
2548                 const struct tu_descriptor_map *map,
2549                 unsigned i, unsigned array_index)
2550 {
2551    assert(descriptors_state->valid & (1 << map->set[i]));
2552
2553    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2554    assert(map->binding[i] < set->layout->binding_count);
2555
2556    const struct tu_descriptor_set_binding_layout *layout =
2557       &set->layout->binding[map->binding[i]];
2558
2559    switch (layout->type) {
2560    case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
2561    case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2562    case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2563    case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
2564       memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2565                                    array_index * A6XX_TEX_CONST_DWORDS],
2566              A6XX_TEX_CONST_DWORDS * 4);
2567       break;
2568    case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2569       memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
2570                                    array_index *
2571                                    (A6XX_TEX_CONST_DWORDS +
2572                                     sizeof(struct tu_sampler) / 4)],
2573              A6XX_TEX_CONST_DWORDS * 4);
2574       break;
2575    default:
2576       unreachable("unimplemented descriptor type");
2577       break;
2578    }
2579
2580    if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
2581       const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
2582       uint32_t a = cmd->state.subpass->input_attachments[map->value[i] +
2583                                                          array_index].attachment;
2584
2585       assert(cmd->state.pass->attachments[a].needs_gmem);
2586       dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
2587       dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
2588       dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
2589       dst[2] |=
2590          A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
2591          A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * tiling->buffer_cpp[a]);
2592       dst[3] = 0;
2593       dst[4] = 0x100000 + tiling->gmem_offsets[a];
2594       dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
2595       for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2596          dst[i] = 0;
2597    }
2598 }
2599
2600 static uint64_t
2601 buffer_ptr(struct tu_descriptor_state *descriptors_state,
2602            const struct tu_descriptor_map *map,
2603            unsigned i, unsigned array_index)
2604 {
2605    assert(descriptors_state->valid & (1 << map->set[i]));
2606
2607    struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
2608    assert(map->binding[i] < set->layout->binding_count);
2609
2610    const struct tu_descriptor_set_binding_layout *layout =
2611       &set->layout->binding[map->binding[i]];
2612
2613    switch (layout->type) {
2614    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2615    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
2616       return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset +
2617                                                 array_index];
2618    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2619    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2620       return (uint64_t) set->mapped_ptr[layout->offset / 4 + array_index * 2 + 1] << 32 |
2621                         set->mapped_ptr[layout->offset / 4 + array_index * 2];
2622    default:
2623       unreachable("unimplemented descriptor type");
2624       break;
2625    }
2626 }
2627
2628 static inline uint32_t
2629 tu6_stage2opcode(gl_shader_stage type)
2630 {
2631    switch (type) {
2632    case MESA_SHADER_VERTEX:
2633    case MESA_SHADER_TESS_CTRL:
2634    case MESA_SHADER_TESS_EVAL:
2635    case MESA_SHADER_GEOMETRY:
2636       return CP_LOAD_STATE6_GEOM;
2637    case MESA_SHADER_FRAGMENT:
2638    case MESA_SHADER_COMPUTE:
2639    case MESA_SHADER_KERNEL:
2640       return CP_LOAD_STATE6_FRAG;
2641    default:
2642       unreachable("bad shader type");
2643    }
2644 }
2645
2646 static inline enum a6xx_state_block
2647 tu6_stage2shadersb(gl_shader_stage type)
2648 {
2649    switch (type) {
2650    case MESA_SHADER_VERTEX:
2651       return SB6_VS_SHADER;
2652    case MESA_SHADER_FRAGMENT:
2653       return SB6_FS_SHADER;
2654    case MESA_SHADER_COMPUTE:
2655    case MESA_SHADER_KERNEL:
2656       return SB6_CS_SHADER;
2657    default:
2658       unreachable("bad shader type");
2659       return ~0;
2660    }
2661 }
2662
2663 static void
2664 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2665                      struct tu_descriptor_state *descriptors_state,
2666                      gl_shader_stage type,
2667                      uint32_t *push_constants)
2668 {
2669    const struct tu_program_descriptor_linkage *link =
2670       &pipeline->program.link[type];
2671    const struct ir3_ubo_analysis_state *state = &link->ubo_state;
2672
2673    for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
2674       if (state->range[i].start < state->range[i].end) {
2675          uint32_t size = state->range[i].end - state->range[i].start;
2676          uint32_t offset = state->range[i].start;
2677
2678          /* and even if the start of the const buffer is before
2679           * first_immediate, the end may not be:
2680           */
2681          size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
2682
2683          if (size == 0)
2684             continue;
2685
2686          /* things should be aligned to vec4: */
2687          debug_assert((state->range[i].offset % 16) == 0);
2688          debug_assert((size % 16) == 0);
2689          debug_assert((offset % 16) == 0);
2690
2691          if (i == 0) {
2692             /* push constants */
2693             tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
2694             tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2695                   CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2696                   CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2697                   CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2698                   CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2699             tu_cs_emit(cs, 0);
2700             tu_cs_emit(cs, 0);
2701             for (unsigned i = 0; i < size / 4; i++)
2702                tu_cs_emit(cs, push_constants[i + offset / 4]);
2703             continue;
2704          }
2705
2706          /* Look through the UBO map to find our UBO index, and get the VA for
2707           * that UBO.
2708           */
2709          uint64_t va = 0;
2710          uint32_t ubo_idx = i - 1;
2711          uint32_t ubo_map_base = 0;
2712          for (int j = 0; j < link->ubo_map.num; j++) {
2713             if (ubo_idx >= ubo_map_base &&
2714                 ubo_idx < ubo_map_base + link->ubo_map.array_size[j]) {
2715                va = buffer_ptr(descriptors_state, &link->ubo_map, j,
2716                                ubo_idx - ubo_map_base);
2717                break;
2718             }
2719             ubo_map_base += link->ubo_map.array_size[j];
2720          }
2721          assert(va);
2722
2723          tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
2724          tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
2725                CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2726                CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2727                CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2728                CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
2729          tu_cs_emit_qw(cs, va + offset);
2730       }
2731    }
2732 }
2733
2734 static void
2735 tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
2736               struct tu_descriptor_state *descriptors_state,
2737               gl_shader_stage type)
2738 {
2739    const struct tu_program_descriptor_linkage *link =
2740       &pipeline->program.link[type];
2741
2742    uint32_t num = MIN2(link->ubo_map.num_desc, link->const_state.num_ubos);
2743    uint32_t anum = align(num, 2);
2744
2745    if (!num)
2746       return;
2747
2748    tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
2749    tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
2750          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2751          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2752          CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
2753          CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
2754    tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2755    tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2756
2757    unsigned emitted = 0;
2758    for (unsigned i = 0; emitted < num && i < link->ubo_map.num; i++) {
2759       for (unsigned j = 0; emitted < num && j < link->ubo_map.array_size[i]; j++) {
2760          tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i, j));
2761          emitted++;
2762       }
2763    }
2764
2765    for (; emitted < anum; emitted++) {
2766       tu_cs_emit(cs, 0xffffffff);
2767       tu_cs_emit(cs, 0xffffffff);
2768    }
2769 }
2770
2771 static struct tu_cs_entry
2772 tu6_emit_consts(struct tu_cmd_buffer *cmd,
2773                 const struct tu_pipeline *pipeline,
2774                 struct tu_descriptor_state *descriptors_state,
2775                 gl_shader_stage type)
2776 {
2777    struct tu_cs cs;
2778    tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
2779
2780    tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
2781    tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
2782
2783    return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2784 }
2785
2786 static VkResult
2787 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
2788                    const struct tu_draw_info *draw,
2789                    struct tu_cs_entry *entry)
2790 {
2791    /* TODO: fill out more than just base instance */
2792    const struct tu_program_descriptor_linkage *link =
2793       &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
2794    const struct ir3_const_state *const_state = &link->const_state;
2795    struct tu_cs cs;
2796
2797    if (const_state->offsets.driver_param >= link->constlen) {
2798       *entry = (struct tu_cs_entry) {};
2799       return VK_SUCCESS;
2800    }
2801
2802    VkResult result = tu_cs_begin_sub_stream(cmd->device, &cmd->sub_cs, 8, &cs);
2803    if (result != VK_SUCCESS)
2804       return result;
2805
2806    tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
2807    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(const_state->offsets.driver_param) |
2808          CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2809          CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
2810          CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
2811          CP_LOAD_STATE6_0_NUM_UNIT(1));
2812    tu_cs_emit(&cs, 0);
2813    tu_cs_emit(&cs, 0);
2814
2815    STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
2816
2817    tu_cs_emit(&cs, 0);
2818    tu_cs_emit(&cs, 0);
2819    tu_cs_emit(&cs, draw->first_instance);
2820    tu_cs_emit(&cs, 0);
2821
2822    *entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
2823    return VK_SUCCESS;
2824 }
2825
2826 static VkResult
2827 tu6_emit_textures(struct tu_cmd_buffer *cmd,
2828                   const struct tu_pipeline *pipeline,
2829                   struct tu_descriptor_state *descriptors_state,
2830                   gl_shader_stage type,
2831                   struct tu_cs_entry *entry,
2832                   bool *needs_border)
2833 {
2834    struct tu_device *device = cmd->device;
2835    struct tu_cs *draw_state = &cmd->sub_cs;
2836    const struct tu_program_descriptor_linkage *link =
2837       &pipeline->program.link[type];
2838    VkResult result;
2839
2840    if (link->texture_map.num_desc == 0 && link->sampler_map.num_desc == 0) {
2841       *entry = (struct tu_cs_entry) {};
2842       return VK_SUCCESS;
2843    }
2844
2845    /* allocate and fill texture state */
2846    struct ts_cs_memory tex_const;
2847    result = tu_cs_alloc(device, draw_state, link->texture_map.num_desc,
2848                         A6XX_TEX_CONST_DWORDS, &tex_const);
2849    if (result != VK_SUCCESS)
2850       return result;
2851
2852    int tex_index = 0;
2853    for (unsigned i = 0; i < link->texture_map.num; i++) {
2854       for (int j = 0; j < link->texture_map.array_size[i]; j++) {
2855          write_tex_const(cmd,
2856                          &tex_const.map[A6XX_TEX_CONST_DWORDS * tex_index++],
2857                          descriptors_state, &link->texture_map, i, j);
2858       }
2859    }
2860
2861    /* allocate and fill sampler state */
2862    struct ts_cs_memory tex_samp = { 0 };
2863    if (link->sampler_map.num_desc) {
2864       result = tu_cs_alloc(device, draw_state, link->sampler_map.num_desc,
2865                            A6XX_TEX_SAMP_DWORDS, &tex_samp);
2866       if (result != VK_SUCCESS)
2867          return result;
2868
2869       int sampler_index = 0;
2870       for (unsigned i = 0; i < link->sampler_map.num; i++) {
2871          for (int j = 0; j < link->sampler_map.array_size[i]; j++) {
2872             const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
2873                                                            &link->sampler_map,
2874                                                            i, j);
2875             memcpy(&tex_samp.map[A6XX_TEX_SAMP_DWORDS * sampler_index++],
2876                    sampler->state, sizeof(sampler->state));
2877             *needs_border |= sampler->needs_border;
2878          }
2879       }
2880    }
2881
2882    unsigned tex_samp_reg, tex_const_reg, tex_count_reg;
2883    enum a6xx_state_block sb;
2884
2885    switch (type) {
2886    case MESA_SHADER_VERTEX:
2887       sb = SB6_VS_TEX;
2888       tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
2889       tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
2890       tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
2891       break;
2892    case MESA_SHADER_FRAGMENT:
2893       sb = SB6_FS_TEX;
2894       tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
2895       tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
2896       tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
2897       break;
2898    case MESA_SHADER_COMPUTE:
2899       sb = SB6_CS_TEX;
2900       tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
2901       tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
2902       tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
2903       break;
2904    default:
2905       unreachable("bad state block");
2906    }
2907
2908    struct tu_cs cs;
2909    result = tu_cs_begin_sub_stream(device, draw_state, 16, &cs);
2910    if (result != VK_SUCCESS)
2911       return result;
2912
2913    if (link->sampler_map.num_desc) {
2914       /* output sampler state: */
2915       tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2916       tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2917                  CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
2918                  CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2919                  CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2920                  CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num_desc));
2921       tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2922
2923       tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
2924       tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
2925    }
2926
2927    /* emit texture state: */
2928    tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
2929    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
2930       CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
2931       CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
2932       CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
2933       CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num_desc));
2934    tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2935
2936    tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
2937    tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
2938
2939    tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
2940    tu_cs_emit(&cs, link->texture_map.num_desc);
2941
2942    *entry = tu_cs_end_sub_stream(draw_state, &cs);
2943    return VK_SUCCESS;
2944 }
2945
2946 static VkResult
2947 tu6_emit_ibo(struct tu_cmd_buffer *cmd,
2948              const struct tu_pipeline *pipeline,
2949              struct tu_descriptor_state *descriptors_state,
2950              gl_shader_stage type,
2951              struct tu_cs_entry *entry)
2952 {
2953    struct tu_device *device = cmd->device;
2954    struct tu_cs *draw_state = &cmd->sub_cs;
2955    const struct tu_program_descriptor_linkage *link =
2956       &pipeline->program.link[type];
2957    VkResult result;
2958
2959    if (link->image_mapping.num_ibo == 0) {
2960       *entry = (struct tu_cs_entry) {};
2961       return VK_SUCCESS;
2962    }
2963
2964    struct ts_cs_memory ibo_const;
2965    result = tu_cs_alloc(device, draw_state, link->image_mapping.num_ibo,
2966                         A6XX_TEX_CONST_DWORDS, &ibo_const);
2967    if (result != VK_SUCCESS)
2968       return result;
2969
2970    for (unsigned i = 0; i < link->image_mapping.num_ibo; i++) {
2971       unsigned idx = link->image_mapping.ibo_to_image[i];
2972       uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * i];
2973
2974       if (idx & IBO_SSBO) {
2975          idx &= ~IBO_SSBO;
2976
2977          uint64_t va = buffer_ptr(descriptors_state, &link->ssbo_map, idx,
2978                                   0 /* XXX */);
2979          /* We don't expose robustBufferAccess, so leave the size unlimited. */
2980          uint32_t sz = MAX_STORAGE_BUFFER_RANGE / 4;
2981
2982          dst[0] = A6XX_IBO_0_FMT(TFMT6_32_UINT);
2983          dst[1] = A6XX_IBO_1_WIDTH(sz & MASK(15)) |
2984                   A6XX_IBO_1_HEIGHT(sz >> 15);
2985          dst[2] = A6XX_IBO_2_UNK4 |
2986                   A6XX_IBO_2_UNK31 |
2987                   A6XX_IBO_2_TYPE(A6XX_TEX_1D);
2988          dst[3] = 0;
2989          dst[4] = va;
2990          dst[5] = va >> 32;
2991          for (int i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
2992             dst[i] = 0;
2993       } else {
2994          tu_finishme("Emit images");
2995       }
2996    }
2997
2998    struct tu_cs cs;
2999    result = tu_cs_begin_sub_stream(device, draw_state, 7, &cs);
3000    if (result != VK_SUCCESS)
3001       return result;
3002
3003    uint32_t opcode, ibo_addr_reg;
3004    enum a6xx_state_block sb;
3005    enum a6xx_state_type st;
3006
3007    switch (type) {
3008    case MESA_SHADER_FRAGMENT:
3009       opcode = CP_LOAD_STATE6;
3010       st = ST6_SHADER;
3011       sb = SB6_IBO;
3012       ibo_addr_reg = REG_A6XX_SP_IBO_LO;
3013       break;
3014    case MESA_SHADER_COMPUTE:
3015       opcode = CP_LOAD_STATE6_FRAG;
3016       st = ST6_IBO;
3017       sb = SB6_CS_SHADER;
3018       ibo_addr_reg = REG_A6XX_SP_CS_IBO_LO;
3019       break;
3020    default:
3021       unreachable("unsupported stage for ibos");
3022    }
3023
3024    /* emit texture state: */
3025    tu_cs_emit_pkt7(&cs, opcode, 3);
3026    tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
3027               CP_LOAD_STATE6_0_STATE_TYPE(st) |
3028               CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
3029               CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
3030               CP_LOAD_STATE6_0_NUM_UNIT(link->image_mapping.num_ibo));
3031    tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3032
3033    tu_cs_emit_pkt4(&cs, ibo_addr_reg, 2);
3034    tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
3035
3036    *entry = tu_cs_end_sub_stream(draw_state, &cs);
3037    return VK_SUCCESS;
3038 }
3039
3040 struct PACKED bcolor_entry {
3041    uint32_t fp32[4];
3042    uint16_t ui16[4];
3043    int16_t  si16[4];
3044    uint16_t fp16[4];
3045    uint16_t rgb565;
3046    uint16_t rgb5a1;
3047    uint16_t rgba4;
3048    uint8_t __pad0[2];
3049    uint8_t  ui8[4];
3050    int8_t   si8[4];
3051    uint32_t rgb10a2;
3052    uint32_t z24; /* also s8? */
3053    uint16_t srgb[4];      /* appears to duplicate fp16[], but clamped, used for srgb */
3054    uint8_t  __pad1[56];
3055 } border_color[] = {
3056    [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] = {},
3057    [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK] = {},
3058    [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] = {
3059       .fp32[3] = 0x3f800000,
3060       .ui16[3] = 0xffff,
3061       .si16[3] = 0x7fff,
3062       .fp16[3] = 0x3c00,
3063       .rgb5a1 = 0x8000,
3064       .rgba4 = 0xf000,
3065       .ui8[3] = 0xff,
3066       .si8[3] = 0x7f,
3067       .rgb10a2 = 0xc0000000,
3068       .srgb[3] = 0x3c00,
3069    },
3070    [VK_BORDER_COLOR_INT_OPAQUE_BLACK] = {
3071       .fp32[3] = 1,
3072       .fp16[3] = 1,
3073    },
3074    [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE] = {
3075       .fp32[0 ... 3] = 0x3f800000,
3076       .ui16[0 ... 3] = 0xffff,
3077       .si16[0 ... 3] = 0x7fff,
3078       .fp16[0 ... 3] = 0x3c00,
3079       .rgb565 = 0xffff,
3080       .rgb5a1 = 0xffff,
3081       .rgba4 = 0xffff,
3082       .ui8[0 ... 3] = 0xff,
3083       .si8[0 ... 3] = 0x7f,
3084       .rgb10a2 = 0xffffffff,
3085       .z24 = 0xffffff,
3086       .srgb[0 ... 3] = 0x3c00,
3087    },
3088    [VK_BORDER_COLOR_INT_OPAQUE_WHITE] = {
3089       .fp32[0 ... 3] = 1,
3090       .fp16[0 ... 3] = 1,
3091    },
3092 };
3093
3094 static VkResult
3095 tu6_emit_border_color(struct tu_cmd_buffer *cmd,
3096                       struct tu_cs *cs)
3097 {
3098    STATIC_ASSERT(sizeof(struct bcolor_entry) == 128);
3099
3100    const struct tu_pipeline *pipeline = cmd->state.pipeline;
3101    struct tu_descriptor_state *descriptors_state =
3102       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3103    const struct tu_descriptor_map *vs_sampler =
3104       &pipeline->program.link[MESA_SHADER_VERTEX].sampler_map;
3105    const struct tu_descriptor_map *fs_sampler =
3106       &pipeline->program.link[MESA_SHADER_FRAGMENT].sampler_map;
3107    struct ts_cs_memory ptr;
3108
3109    VkResult result = tu_cs_alloc(cmd->device, &cmd->sub_cs,
3110                                  vs_sampler->num_desc + fs_sampler->num_desc,
3111                                  128 / 4,
3112                                  &ptr);
3113    if (result != VK_SUCCESS)
3114       return result;
3115
3116    for (unsigned i = 0; i < vs_sampler->num; i++) {
3117       for (unsigned j = 0; j < vs_sampler->array_size[i]; j++) {
3118          const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3119                                                         vs_sampler, i, j);
3120          memcpy(ptr.map, &border_color[sampler->border], 128);
3121          ptr.map += 128 / 4;
3122       }
3123    }
3124
3125    for (unsigned i = 0; i < fs_sampler->num; i++) {
3126       for (unsigned j = 0; j < fs_sampler->array_size[i]; j++) {
3127          const struct tu_sampler *sampler = sampler_ptr(descriptors_state,
3128                                                         fs_sampler, i, j);
3129          memcpy(ptr.map, &border_color[sampler->border], 128);
3130          ptr.map += 128 / 4;
3131       }
3132    }
3133
3134    tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
3135    tu_cs_emit_qw(cs, ptr.iova);
3136    return VK_SUCCESS;
3137 }
3138
3139 static VkResult
3140 tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
3141                      struct tu_cs *cs,
3142                      const struct tu_draw_info *draw)
3143 {
3144    const struct tu_pipeline *pipeline = cmd->state.pipeline;
3145    const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
3146    struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
3147    uint32_t draw_state_group_count = 0;
3148
3149    struct tu_descriptor_state *descriptors_state =
3150       &cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
3151
3152    VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
3153    if (result != VK_SUCCESS)
3154       return result;
3155
3156    /* TODO lrz */
3157
3158    uint32_t pc_primitive_cntl = 0;
3159    if (pipeline->ia.primitive_restart && draw->indexed)
3160       pc_primitive_cntl |= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART;
3161
3162    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
3163    tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
3164    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_UNKNOWN_A008, 0);
3165
3166    tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
3167    tu_cs_emit(cs, pc_primitive_cntl);
3168
3169    if (cmd->state.dirty &
3170           (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
3171        (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
3172       tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
3173                             dynamic->line_width);
3174    }
3175
3176    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
3177        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
3178       tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
3179                                     dynamic->stencil_compare_mask.back);
3180    }
3181
3182    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
3183        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
3184       tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
3185                                   dynamic->stencil_write_mask.back);
3186    }
3187
3188    if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
3189        (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
3190       tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
3191                                  dynamic->stencil_reference.back);
3192    }
3193
3194    if (cmd->state.dirty &
3195        (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
3196       for (uint32_t i = 0; i < pipeline->vi.count; i++) {
3197          const uint32_t binding = pipeline->vi.bindings[i];
3198          const uint32_t stride = pipeline->vi.strides[i];
3199          const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
3200          const VkDeviceSize offset = buf->bo_offset +
3201                                      cmd->state.vb.offsets[binding] +
3202                                      pipeline->vi.offsets[i];
3203          const VkDeviceSize size =
3204             offset < buf->bo->size ? buf->bo->size - offset : 0;
3205
3206          tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH(i), 4);
3207          tu_cs_emit_qw(cs, buf->bo->iova + offset);
3208          tu_cs_emit(cs, size);
3209          tu_cs_emit(cs, stride);
3210       }
3211    }
3212
3213    if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
3214       draw_state_groups[draw_state_group_count++] =
3215          (struct tu_draw_state_group) {
3216             .id = TU_DRAW_STATE_PROGRAM,
3217             .enable_mask = ENABLE_DRAW,
3218             .ib = pipeline->program.state_ib,
3219          };
3220       draw_state_groups[draw_state_group_count++] =
3221          (struct tu_draw_state_group) {
3222             .id = TU_DRAW_STATE_PROGRAM_BINNING,
3223             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3224             .ib = pipeline->program.binning_state_ib,
3225          };
3226       draw_state_groups[draw_state_group_count++] =
3227          (struct tu_draw_state_group) {
3228             .id = TU_DRAW_STATE_VI,
3229             .enable_mask = ENABLE_DRAW,
3230             .ib = pipeline->vi.state_ib,
3231          };
3232       draw_state_groups[draw_state_group_count++] =
3233          (struct tu_draw_state_group) {
3234             .id = TU_DRAW_STATE_VI_BINNING,
3235             .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
3236             .ib = pipeline->vi.binning_state_ib,
3237          };
3238       draw_state_groups[draw_state_group_count++] =
3239          (struct tu_draw_state_group) {
3240             .id = TU_DRAW_STATE_VP,
3241             .enable_mask = ENABLE_ALL,
3242             .ib = pipeline->vp.state_ib,
3243          };
3244       draw_state_groups[draw_state_group_count++] =
3245          (struct tu_draw_state_group) {
3246             .id = TU_DRAW_STATE_RAST,
3247             .enable_mask = ENABLE_ALL,
3248             .ib = pipeline->rast.state_ib,
3249          };
3250       draw_state_groups[draw_state_group_count++] =
3251          (struct tu_draw_state_group) {
3252             .id = TU_DRAW_STATE_DS,
3253             .enable_mask = ENABLE_ALL,
3254             .ib = pipeline->ds.state_ib,
3255          };
3256       draw_state_groups[draw_state_group_count++] =
3257          (struct tu_draw_state_group) {
3258             .id = TU_DRAW_STATE_BLEND,
3259             .enable_mask = ENABLE_ALL,
3260             .ib = pipeline->blend.state_ib,
3261          };
3262    }
3263
3264    if (cmd->state.dirty &
3265          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_PUSH_CONSTANTS)) {
3266       draw_state_groups[draw_state_group_count++] =
3267          (struct tu_draw_state_group) {
3268             .id = TU_DRAW_STATE_VS_CONST,
3269             .enable_mask = ENABLE_ALL,
3270             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
3271          };
3272       draw_state_groups[draw_state_group_count++] =
3273          (struct tu_draw_state_group) {
3274             .id = TU_DRAW_STATE_FS_CONST,
3275             .enable_mask = ENABLE_DRAW,
3276             .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
3277          };
3278    }
3279
3280    if (cmd->state.dirty &
3281          (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
3282       bool needs_border = false;
3283       struct tu_cs_entry vs_tex, fs_tex, fs_ibo;
3284
3285       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3286                                  MESA_SHADER_VERTEX, &vs_tex, &needs_border);
3287       if (result != VK_SUCCESS)
3288          return result;
3289
3290       result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3291                                  MESA_SHADER_FRAGMENT, &fs_tex, &needs_border);
3292       if (result != VK_SUCCESS)
3293          return result;
3294
3295       result = tu6_emit_ibo(cmd, pipeline, descriptors_state,
3296                             MESA_SHADER_FRAGMENT, &fs_ibo);
3297       if (result != VK_SUCCESS)
3298          return result;
3299
3300       draw_state_groups[draw_state_group_count++] =
3301          (struct tu_draw_state_group) {
3302             .id = TU_DRAW_STATE_VS_TEX,
3303             .enable_mask = ENABLE_ALL,
3304             .ib = vs_tex,
3305          };
3306       draw_state_groups[draw_state_group_count++] =
3307          (struct tu_draw_state_group) {
3308             .id = TU_DRAW_STATE_FS_TEX,
3309             .enable_mask = ENABLE_DRAW,
3310             .ib = fs_tex,
3311          };
3312       draw_state_groups[draw_state_group_count++] =
3313          (struct tu_draw_state_group) {
3314             .id = TU_DRAW_STATE_FS_IBO,
3315             .enable_mask = ENABLE_DRAW,
3316             .ib = fs_ibo,
3317          };
3318
3319       if (needs_border) {
3320          result = tu6_emit_border_color(cmd, cs);
3321          if (result != VK_SUCCESS)
3322             return result;
3323       }
3324    }
3325
3326    struct tu_cs_entry vs_params;
3327    result = tu6_emit_vs_params(cmd, draw, &vs_params);
3328    if (result != VK_SUCCESS)
3329       return result;
3330
3331    draw_state_groups[draw_state_group_count++] =
3332       (struct tu_draw_state_group) {
3333          .id = TU_DRAW_STATE_VS_PARAMS,
3334          .enable_mask = ENABLE_ALL,
3335          .ib = vs_params,
3336       };
3337
3338    tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
3339    for (uint32_t i = 0; i < draw_state_group_count; i++) {
3340       const struct tu_draw_state_group *group = &draw_state_groups[i];
3341       debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
3342       uint32_t cp_set_draw_state =
3343          CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
3344          group->enable_mask |
3345          CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
3346       uint64_t iova;
3347       if (group->ib.size) {
3348          iova = group->ib.bo->iova + group->ib.offset;
3349       } else {
3350          cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
3351          iova = 0;
3352       }
3353
3354       tu_cs_emit(cs, cp_set_draw_state);
3355       tu_cs_emit_qw(cs, iova);
3356    }
3357
3358    tu_cs_sanity_check(cs);
3359
3360    /* track BOs */
3361    if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
3362       for (uint32_t i = 0; i < MAX_VBS; i++) {
3363          const struct tu_buffer *buf = cmd->state.vb.buffers[i];
3364          if (buf)
3365             tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
3366       }
3367    }
3368    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3369       unsigned i;
3370       for_each_bit(i, descriptors_state->valid) {
3371          struct tu_descriptor_set *set = descriptors_state->sets[i];
3372          for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3373             if (set->descriptors[j]) {
3374                tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3375                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3376             }
3377       }
3378    }
3379
3380    /* Fragment shader state overwrites compute shader state, so flag the
3381     * compute pipeline for re-emit.
3382     */
3383    cmd->state.dirty = TU_CMD_DIRTY_COMPUTE_PIPELINE;
3384    return VK_SUCCESS;
3385 }
3386
3387 static void
3388 tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
3389                      struct tu_cs *cs,
3390                      const struct tu_draw_info *draw)
3391 {
3392
3393    const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
3394
3395    tu_cs_emit_pkt4(cs, REG_A6XX_VFD_INDEX_OFFSET, 2);
3396    tu_cs_emit(cs, draw->vertex_offset);
3397    tu_cs_emit(cs, draw->first_instance);
3398
3399    /* TODO hw binning */
3400    if (draw->indexed) {
3401       const enum a4xx_index_size index_size =
3402          tu6_index_size(cmd->state.index_type);
3403       const uint32_t index_bytes =
3404          (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
3405       const struct tu_buffer *buf = cmd->state.index_buffer;
3406       const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
3407                                   index_bytes * draw->first_index;
3408       const uint32_t size = index_bytes * draw->count;
3409
3410       const uint32_t cp_draw_indx =
3411          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3412          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
3413          CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
3414          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3415
3416       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
3417       tu_cs_emit(cs, cp_draw_indx);
3418       tu_cs_emit(cs, draw->instance_count);
3419       tu_cs_emit(cs, draw->count);
3420       tu_cs_emit(cs, 0x0); /* XXX */
3421       tu_cs_emit_qw(cs, buf->bo->iova + offset);
3422       tu_cs_emit(cs, size);
3423    } else {
3424       const uint32_t cp_draw_indx =
3425          CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
3426          CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
3427          CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) | 0x2000;
3428
3429       tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
3430       tu_cs_emit(cs, cp_draw_indx);
3431       tu_cs_emit(cs, draw->instance_count);
3432       tu_cs_emit(cs, draw->count);
3433    }
3434 }
3435
3436 static void
3437 tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
3438 {
3439    struct tu_cs *cs = &cmd->draw_cs;
3440    VkResult result;
3441
3442    result = tu6_bind_draw_states(cmd, cs, draw);
3443    if (result != VK_SUCCESS) {
3444       cmd->record_result = result;
3445       return;
3446    }
3447
3448    result = tu_cs_reserve_space(cmd->device, cs, 32);
3449    if (result != VK_SUCCESS) {
3450       cmd->record_result = result;
3451       return;
3452    }
3453
3454    if (draw->indirect) {
3455       tu_finishme("indirect draw");
3456       return;
3457    }
3458
3459    /* TODO tu6_emit_marker should pick different regs depending on cs */
3460
3461    tu6_emit_marker(cmd, cs);
3462    tu6_emit_draw_direct(cmd, cs, draw);
3463    tu6_emit_marker(cmd, cs);
3464
3465    cmd->wait_for_idle = true;
3466
3467    tu_cs_sanity_check(cs);
3468 }
3469
3470 void
3471 tu_CmdDraw(VkCommandBuffer commandBuffer,
3472            uint32_t vertexCount,
3473            uint32_t instanceCount,
3474            uint32_t firstVertex,
3475            uint32_t firstInstance)
3476 {
3477    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3478    struct tu_draw_info info = {};
3479
3480    info.count = vertexCount;
3481    info.instance_count = instanceCount;
3482    info.first_instance = firstInstance;
3483    info.vertex_offset = firstVertex;
3484
3485    tu_draw(cmd_buffer, &info);
3486 }
3487
3488 void
3489 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
3490                   uint32_t indexCount,
3491                   uint32_t instanceCount,
3492                   uint32_t firstIndex,
3493                   int32_t vertexOffset,
3494                   uint32_t firstInstance)
3495 {
3496    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3497    struct tu_draw_info info = {};
3498
3499    info.indexed = true;
3500    info.count = indexCount;
3501    info.instance_count = instanceCount;
3502    info.first_index = firstIndex;
3503    info.vertex_offset = vertexOffset;
3504    info.first_instance = firstInstance;
3505
3506    tu_draw(cmd_buffer, &info);
3507 }
3508
3509 void
3510 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
3511                    VkBuffer _buffer,
3512                    VkDeviceSize offset,
3513                    uint32_t drawCount,
3514                    uint32_t stride)
3515 {
3516    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3517    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3518    struct tu_draw_info info = {};
3519
3520    info.count = drawCount;
3521    info.indirect = buffer;
3522    info.indirect_offset = offset;
3523    info.stride = stride;
3524
3525    tu_draw(cmd_buffer, &info);
3526 }
3527
3528 void
3529 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
3530                           VkBuffer _buffer,
3531                           VkDeviceSize offset,
3532                           uint32_t drawCount,
3533                           uint32_t stride)
3534 {
3535    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3536    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3537    struct tu_draw_info info = {};
3538
3539    info.indexed = true;
3540    info.count = drawCount;
3541    info.indirect = buffer;
3542    info.indirect_offset = offset;
3543    info.stride = stride;
3544
3545    tu_draw(cmd_buffer, &info);
3546 }
3547
3548 struct tu_dispatch_info
3549 {
3550    /**
3551     * Determine the layout of the grid (in block units) to be used.
3552     */
3553    uint32_t blocks[3];
3554
3555    /**
3556     * A starting offset for the grid. If unaligned is set, the offset
3557     * must still be aligned.
3558     */
3559    uint32_t offsets[3];
3560    /**
3561     * Whether it's an unaligned compute dispatch.
3562     */
3563    bool unaligned;
3564
3565    /**
3566     * Indirect compute parameters resource.
3567     */
3568    struct tu_buffer *indirect;
3569    uint64_t indirect_offset;
3570 };
3571
3572 static void
3573 tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline,
3574                               const struct tu_dispatch_info *info)
3575 {
3576    gl_shader_stage type = MESA_SHADER_COMPUTE;
3577    const struct tu_program_descriptor_linkage *link =
3578       &pipeline->program.link[type];
3579    const struct ir3_const_state *const_state = &link->const_state;
3580    uint32_t offset = const_state->offsets.driver_param;
3581
3582    if (link->constlen <= offset)
3583       return;
3584
3585    if (!info->indirect) {
3586       uint32_t driver_params[IR3_DP_CS_COUNT] = {
3587          [IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0],
3588          [IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1],
3589          [IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2],
3590          [IR3_DP_LOCAL_GROUP_SIZE_X] = pipeline->compute.local_size[0],
3591          [IR3_DP_LOCAL_GROUP_SIZE_Y] = pipeline->compute.local_size[1],
3592          [IR3_DP_LOCAL_GROUP_SIZE_Z] = pipeline->compute.local_size[2],
3593       };
3594
3595       uint32_t num_consts = MIN2(const_state->num_driver_params,
3596                                  (link->constlen - offset) * 4);
3597       /* push constants */
3598       tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
3599       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
3600                  CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
3601                  CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
3602                  CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
3603                  CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
3604       tu_cs_emit(cs, 0);
3605       tu_cs_emit(cs, 0);
3606       uint32_t i;
3607       for (i = 0; i < num_consts; i++)
3608          tu_cs_emit(cs, driver_params[i]);
3609    } else {
3610       tu_finishme("Indirect driver params");
3611    }
3612 }
3613
3614 static void
3615 tu_dispatch(struct tu_cmd_buffer *cmd,
3616             const struct tu_dispatch_info *info)
3617 {
3618    struct tu_cs *cs = &cmd->cs;
3619    struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
3620    struct tu_descriptor_state *descriptors_state =
3621       &cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
3622
3623    VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
3624    if (result != VK_SUCCESS) {
3625       cmd->record_result = result;
3626       return;
3627    }
3628
3629    if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
3630       tu_cs_emit_ib(cs, &pipeline->program.state_ib);
3631
3632    struct tu_cs_entry ib;
3633
3634    ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
3635    if (ib.size)
3636       tu_cs_emit_ib(cs, &ib);
3637
3638    tu_emit_compute_driver_params(cs, pipeline, info);
3639
3640    bool needs_border;
3641    result = tu6_emit_textures(cmd, pipeline, descriptors_state,
3642                               MESA_SHADER_COMPUTE, &ib, &needs_border);
3643    if (result != VK_SUCCESS) {
3644       cmd->record_result = result;
3645       return;
3646    }
3647
3648    if (ib.size)
3649       tu_cs_emit_ib(cs, &ib);
3650
3651    if (needs_border)
3652       tu_finishme("compute border color");
3653
3654    result = tu6_emit_ibo(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE, &ib);
3655    if (result != VK_SUCCESS) {
3656       cmd->record_result = result;
3657       return;
3658    }
3659
3660    if (ib.size)
3661       tu_cs_emit_ib(cs, &ib);
3662
3663    /* track BOs */
3664    if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
3665       unsigned i;
3666       for_each_bit(i, descriptors_state->valid) {
3667          struct tu_descriptor_set *set = descriptors_state->sets[i];
3668          for (unsigned j = 0; j < set->layout->buffer_count; ++j)
3669             if (set->descriptors[j]) {
3670                tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
3671                               MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3672             }
3673       }
3674    }
3675
3676    /* Compute shader state overwrites fragment shader state, so we flag the
3677     * graphics pipeline for re-emit.
3678     */
3679    cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
3680
3681    tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
3682    tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x8));
3683
3684    const uint32_t *local_size = pipeline->compute.local_size;
3685    const uint32_t *num_groups = info->blocks;
3686    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_NDRANGE_0, 7);
3687    tu_cs_emit(cs,
3688               A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(3) |
3689               A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
3690               A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
3691               A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
3692    tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size[0] * num_groups[0]));
3693    tu_cs_emit(cs, 0);            /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
3694    tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size[1] * num_groups[1]));
3695    tu_cs_emit(cs, 0);            /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
3696    tu_cs_emit(cs, A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size[2] * num_groups[2]));
3697    tu_cs_emit(cs, 0);            /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
3698
3699    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X, 3);
3700    tu_cs_emit(cs, 1);            /* HLSQ_CS_KERNEL_GROUP_X */
3701    tu_cs_emit(cs, 1);            /* HLSQ_CS_KERNEL_GROUP_Y */
3702    tu_cs_emit(cs, 1);            /* HLSQ_CS_KERNEL_GROUP_Z */
3703
3704    if (info->indirect) {
3705       uint64_t iova = tu_buffer_iova(info->indirect) + info->indirect_offset;
3706
3707       tu_bo_list_add(&cmd->bo_list, info->indirect->bo,
3708                      MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
3709
3710       tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
3711       tu_cs_emit(cs, 0x00000000);
3712       tu_cs_emit_qw(cs, iova);
3713       tu_cs_emit(cs,
3714                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
3715                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
3716                  A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
3717    } else {
3718       tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
3719       tu_cs_emit(cs, 0x00000000);
3720       tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
3721       tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
3722       tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
3723    }
3724
3725    tu_cs_emit_wfi(cs);
3726
3727    tu6_emit_cache_flush(cmd, cs);
3728 }
3729
3730 void
3731 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
3732                    uint32_t base_x,
3733                    uint32_t base_y,
3734                    uint32_t base_z,
3735                    uint32_t x,
3736                    uint32_t y,
3737                    uint32_t z)
3738 {
3739    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3740    struct tu_dispatch_info info = {};
3741
3742    info.blocks[0] = x;
3743    info.blocks[1] = y;
3744    info.blocks[2] = z;
3745
3746    info.offsets[0] = base_x;
3747    info.offsets[1] = base_y;
3748    info.offsets[2] = base_z;
3749    tu_dispatch(cmd_buffer, &info);
3750 }
3751
3752 void
3753 tu_CmdDispatch(VkCommandBuffer commandBuffer,
3754                uint32_t x,
3755                uint32_t y,
3756                uint32_t z)
3757 {
3758    tu_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3759 }
3760
3761 void
3762 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
3763                        VkBuffer _buffer,
3764                        VkDeviceSize offset)
3765 {
3766    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3767    TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
3768    struct tu_dispatch_info info = {};
3769
3770    info.indirect = buffer;
3771    info.indirect_offset = offset;
3772
3773    tu_dispatch(cmd_buffer, &info);
3774 }
3775
3776 void
3777 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
3778 {
3779    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3780
3781    tu_cs_end(&cmd_buffer->draw_cs);
3782
3783    tu_cmd_render_tiles(cmd_buffer);
3784
3785    /* discard draw_cs entries now that the tiles are rendered */
3786    tu_cs_discard_entries(&cmd_buffer->draw_cs);
3787    tu_cs_begin(&cmd_buffer->draw_cs);
3788
3789    cmd_buffer->state.pass = NULL;
3790    cmd_buffer->state.subpass = NULL;
3791    cmd_buffer->state.framebuffer = NULL;
3792 }
3793
3794 void
3795 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer,
3796                         const VkSubpassEndInfoKHR *pSubpassEndInfo)
3797 {
3798    tu_CmdEndRenderPass(commandBuffer);
3799 }
3800
3801 struct tu_barrier_info
3802 {
3803    uint32_t eventCount;
3804    const VkEvent *pEvents;
3805    VkPipelineStageFlags srcStageMask;
3806 };
3807
3808 static void
3809 tu_barrier(struct tu_cmd_buffer *cmd_buffer,
3810            uint32_t memoryBarrierCount,
3811            const VkMemoryBarrier *pMemoryBarriers,
3812            uint32_t bufferMemoryBarrierCount,
3813            const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3814            uint32_t imageMemoryBarrierCount,
3815            const VkImageMemoryBarrier *pImageMemoryBarriers,
3816            const struct tu_barrier_info *info)
3817 {
3818 }
3819
3820 void
3821 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
3822                       VkPipelineStageFlags srcStageMask,
3823                       VkPipelineStageFlags destStageMask,
3824                       VkBool32 byRegion,
3825                       uint32_t memoryBarrierCount,
3826                       const VkMemoryBarrier *pMemoryBarriers,
3827                       uint32_t bufferMemoryBarrierCount,
3828                       const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3829                       uint32_t imageMemoryBarrierCount,
3830                       const VkImageMemoryBarrier *pImageMemoryBarriers)
3831 {
3832    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3833    struct tu_barrier_info info;
3834
3835    info.eventCount = 0;
3836    info.pEvents = NULL;
3837    info.srcStageMask = srcStageMask;
3838
3839    tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3840               bufferMemoryBarrierCount, pBufferMemoryBarriers,
3841               imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3842 }
3843
3844 static void
3845 write_event(struct tu_cmd_buffer *cmd_buffer,
3846             struct tu_event *event,
3847             VkPipelineStageFlags stageMask,
3848             unsigned value)
3849 {
3850 }
3851
3852 void
3853 tu_CmdSetEvent(VkCommandBuffer commandBuffer,
3854                VkEvent _event,
3855                VkPipelineStageFlags stageMask)
3856 {
3857    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3858    TU_FROM_HANDLE(tu_event, event, _event);
3859
3860    write_event(cmd_buffer, event, stageMask, 1);
3861 }
3862
3863 void
3864 tu_CmdResetEvent(VkCommandBuffer commandBuffer,
3865                  VkEvent _event,
3866                  VkPipelineStageFlags stageMask)
3867 {
3868    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3869    TU_FROM_HANDLE(tu_event, event, _event);
3870
3871    write_event(cmd_buffer, event, stageMask, 0);
3872 }
3873
3874 void
3875 tu_CmdWaitEvents(VkCommandBuffer commandBuffer,
3876                  uint32_t eventCount,
3877                  const VkEvent *pEvents,
3878                  VkPipelineStageFlags srcStageMask,
3879                  VkPipelineStageFlags dstStageMask,
3880                  uint32_t memoryBarrierCount,
3881                  const VkMemoryBarrier *pMemoryBarriers,
3882                  uint32_t bufferMemoryBarrierCount,
3883                  const VkBufferMemoryBarrier *pBufferMemoryBarriers,
3884                  uint32_t imageMemoryBarrierCount,
3885                  const VkImageMemoryBarrier *pImageMemoryBarriers)
3886 {
3887    TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3888    struct tu_barrier_info info;
3889
3890    info.eventCount = eventCount;
3891    info.pEvents = pEvents;
3892    info.srcStageMask = 0;
3893
3894    tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
3895               bufferMemoryBarrierCount, pBufferMemoryBarriers,
3896               imageMemoryBarrierCount, pImageMemoryBarriers, &info);
3897 }
3898
3899 void
3900 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask)
3901 {
3902    /* No-op */
3903 }