2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "util/debug.h"
31 #include "util/u_atomic.h"
32 #include "util/format/u_format.h"
33 #include "vk_format.h"
35 #include "drm-uapi/drm_fourcc.h"
40 tu_image_create(VkDevice _device
,
41 const VkImageCreateInfo
*pCreateInfo
,
42 const VkAllocationCallbacks
*alloc
,
46 TU_FROM_HANDLE(tu_device
, device
, _device
);
47 struct tu_image
*image
= NULL
;
48 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
50 tu_assert(pCreateInfo
->mipLevels
> 0);
51 tu_assert(pCreateInfo
->arrayLayers
> 0);
52 tu_assert(pCreateInfo
->samples
> 0);
53 tu_assert(pCreateInfo
->extent
.width
> 0);
54 tu_assert(pCreateInfo
->extent
.height
> 0);
55 tu_assert(pCreateInfo
->extent
.depth
> 0);
57 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
58 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
60 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
62 image
->type
= pCreateInfo
->imageType
;
64 image
->vk_format
= pCreateInfo
->format
;
65 image
->tiling
= pCreateInfo
->tiling
;
66 image
->usage
= pCreateInfo
->usage
;
67 image
->flags
= pCreateInfo
->flags
;
68 image
->extent
= pCreateInfo
->extent
;
69 image
->level_count
= pCreateInfo
->mipLevels
;
70 image
->layer_count
= pCreateInfo
->arrayLayers
;
71 image
->samples
= pCreateInfo
->samples
;
73 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
74 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
75 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
76 if (pCreateInfo
->pQueueFamilyIndices
[i
] ==
77 VK_QUEUE_FAMILY_EXTERNAL
)
78 image
->queue_family_mask
|= (1u << TU_MAX_QUEUE_FAMILIES
) - 1u;
80 image
->queue_family_mask
|=
81 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
85 vk_find_struct_const(pCreateInfo
->pNext
,
86 EXTERNAL_MEMORY_IMAGE_CREATE_INFO
) != NULL
;
88 image
->layout
.tile_mode
= TILE6_3
;
89 bool ubwc_enabled
= true;
91 /* disable tiling when linear is requested and for compressed formats */
92 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
||
93 modifier
== DRM_FORMAT_MOD_LINEAR
||
94 vk_format_is_compressed(image
->vk_format
)) {
95 image
->layout
.tile_mode
= TILE6_LINEAR
;
99 /* UBWC can't be used with E5B9G9R9 */
100 if (image
->vk_format
== VK_FORMAT_E5B9G9R9_UFLOAT_PACK32
)
101 ubwc_enabled
= false;
103 /* separate stencil doesn't have a UBWC enable bit */
104 if (image
->vk_format
== VK_FORMAT_S8_UINT
)
105 ubwc_enabled
= false;
107 if (image
->extent
.depth
> 1) {
108 tu_finishme("UBWC with 3D textures");
109 ubwc_enabled
= false;
112 /* Disable UBWC for storage images.
114 * The closed GL driver skips UBWC for storage images (and additionally
115 * uses linear for writeonly images). We seem to have image tiling working
116 * in freedreno in general, so turnip matches that. freedreno also enables
117 * UBWC on images, but it's not really tested due to the lack of
118 * UBWC-enabled mipmaps in freedreno currently. Just match the closed GL
119 * behavior of no UBWC.
121 if (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)
122 ubwc_enabled
= false;
124 uint32_t ubwc_blockwidth
, ubwc_blockheight
;
125 fdl6_get_ubwc_blockwidth(&image
->layout
,
126 &ubwc_blockwidth
, &ubwc_blockheight
);
127 if (!ubwc_blockwidth
) {
128 tu_finishme("UBWC for cpp=%d", image
->layout
.cpp
);
129 ubwc_enabled
= false;
132 /* expect UBWC enabled if we asked for it */
133 assert(modifier
!= DRM_FORMAT_MOD_QCOM_COMPRESSED
|| ubwc_enabled
);
135 image
->layout
.ubwc
= ubwc_enabled
;
137 fdl6_layout(&image
->layout
, vk_format_to_pipe_format(image
->vk_format
),
139 pCreateInfo
->extent
.width
,
140 pCreateInfo
->extent
.height
,
141 pCreateInfo
->extent
.depth
,
142 pCreateInfo
->mipLevels
,
143 pCreateInfo
->arrayLayers
,
144 pCreateInfo
->imageType
== VK_IMAGE_TYPE_3D
);
146 *pImage
= tu_image_to_handle(image
);
151 enum a6xx_tex_fetchsize
152 tu6_fetchsize(VkFormat format
)
154 if (vk_format_description(format
)->layout
== UTIL_FORMAT_LAYOUT_ASTC
)
155 return TFETCH6_16_BYTE
;
157 switch (vk_format_get_blocksize(format
) / vk_format_get_blockwidth(format
)) {
158 case 1: return TFETCH6_1_BYTE
;
159 case 2: return TFETCH6_2_BYTE
;
160 case 4: return TFETCH6_4_BYTE
;
161 case 8: return TFETCH6_8_BYTE
;
162 case 16: return TFETCH6_16_BYTE
;
164 unreachable("bad block size");
169 tu6_texswiz(const VkComponentMapping
*comps
,
171 VkImageAspectFlagBits aspect_mask
)
173 unsigned char swiz
[4] = {comps
->r
, comps
->g
, comps
->b
, comps
->a
};
174 unsigned char vk_swizzle
[] = {
175 [VK_COMPONENT_SWIZZLE_ZERO
] = A6XX_TEX_ZERO
,
176 [VK_COMPONENT_SWIZZLE_ONE
] = A6XX_TEX_ONE
,
177 [VK_COMPONENT_SWIZZLE_R
] = A6XX_TEX_X
,
178 [VK_COMPONENT_SWIZZLE_G
] = A6XX_TEX_Y
,
179 [VK_COMPONENT_SWIZZLE_B
] = A6XX_TEX_Z
,
180 [VK_COMPONENT_SWIZZLE_A
] = A6XX_TEX_W
,
182 const unsigned char *fmt_swiz
= vk_format_description(format
)->swizzle
;
184 for (unsigned i
= 0; i
< 4; i
++) {
185 swiz
[i
] = (swiz
[i
] == VK_COMPONENT_SWIZZLE_IDENTITY
) ? i
: vk_swizzle
[swiz
[i
]];
186 /* if format has 0/1 in channel, use that (needed for bc1_rgb) */
188 if (aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
&&
189 format
== VK_FORMAT_D24_UNORM_S8_UINT
)
190 swiz
[i
] = A6XX_TEX_Y
;
191 switch (fmt_swiz
[swiz
[i
]]) {
192 case PIPE_SWIZZLE_0
: swiz
[i
] = A6XX_TEX_ZERO
; break;
193 case PIPE_SWIZZLE_1
: swiz
[i
] = A6XX_TEX_ONE
; break;
198 return A6XX_TEX_CONST_0_SWIZ_X(swiz
[0]) |
199 A6XX_TEX_CONST_0_SWIZ_Y(swiz
[1]) |
200 A6XX_TEX_CONST_0_SWIZ_Z(swiz
[2]) |
201 A6XX_TEX_CONST_0_SWIZ_W(swiz
[3]);
204 static enum a6xx_tex_type
205 tu6_tex_type(VkImageViewType type
)
209 case VK_IMAGE_VIEW_TYPE_1D
:
210 case VK_IMAGE_VIEW_TYPE_1D_ARRAY
:
212 case VK_IMAGE_VIEW_TYPE_2D
:
213 case VK_IMAGE_VIEW_TYPE_2D_ARRAY
:
215 case VK_IMAGE_VIEW_TYPE_3D
:
217 case VK_IMAGE_VIEW_TYPE_CUBE
:
218 case VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
:
219 return A6XX_TEX_CUBE
;
224 tu_cs_image_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
)
226 tu_cs_emit(cs
, iview
->PITCH
);
227 tu_cs_emit(cs
, iview
->layer_size
>> 6);
228 tu_cs_emit_qw(cs
, iview
->base_addr
+ iview
->layer_size
* layer
);
232 tu_cs_image_ref_2d(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
, bool src
)
234 tu_cs_emit_qw(cs
, iview
->base_addr
+ iview
->layer_size
* layer
);
235 /* SP_PS_2D_SRC_PITCH has shifted pitch field */
236 tu_cs_emit(cs
, iview
->PITCH
<< (src
? 9 : 0));
240 tu_cs_image_flag_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
)
242 tu_cs_emit_qw(cs
, iview
->ubwc_addr
+ iview
->ubwc_layer_size
* layer
);
243 tu_cs_emit(cs
, iview
->FLAG_BUFFER_PITCH
);
247 tu_image_view_init(struct tu_image_view
*iview
,
248 const VkImageViewCreateInfo
*pCreateInfo
)
250 TU_FROM_HANDLE(tu_image
, image
, pCreateInfo
->image
);
251 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
252 VkFormat format
= pCreateInfo
->format
;
253 VkImageAspectFlagBits aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
255 switch (image
->type
) {
256 case VK_IMAGE_TYPE_1D
:
257 case VK_IMAGE_TYPE_2D
:
258 assert(range
->baseArrayLayer
+ tu_get_layerCount(image
, range
) <=
261 case VK_IMAGE_TYPE_3D
:
262 assert(range
->baseArrayLayer
+ tu_get_layerCount(image
, range
) <=
263 tu_minify(image
->extent
.depth
, range
->baseMipLevel
));
266 unreachable("bad VkImageType");
269 iview
->image
= image
;
271 memset(iview
->descriptor
, 0, sizeof(iview
->descriptor
));
273 struct fdl_layout
*layout
= &image
->layout
;
275 uint32_t width
= u_minify(image
->extent
.width
, range
->baseMipLevel
);
276 uint32_t height
= u_minify(image
->extent
.height
, range
->baseMipLevel
);
277 uint32_t depth
= pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
?
278 u_minify(image
->extent
.depth
, range
->baseMipLevel
) : tu_get_layerCount(image
, range
);
280 uint64_t base_addr
= image
->bo
->iova
+ image
->bo_offset
+
281 fdl_surface_offset(layout
, range
->baseMipLevel
, range
->baseArrayLayer
);
282 uint64_t ubwc_addr
= image
->bo
->iova
+ image
->bo_offset
+
283 fdl_ubwc_offset(layout
, range
->baseMipLevel
, range
->baseArrayLayer
);
285 uint32_t pitch
= layout
->slices
[range
->baseMipLevel
].pitch
* layout
->cpp
/
286 util_format_get_blockwidth(layout
->format
);
287 uint32_t ubwc_pitch
= layout
->ubwc_slices
[range
->baseMipLevel
].pitch
;
288 uint32_t layer_size
= fdl_layer_stride(layout
, range
->baseMipLevel
);
290 struct tu_native_format fmt
= tu6_format_texture(format
, layout
->tile_mode
);
291 /* note: freedreno layout assumes no TILE_ALL bit for non-UBWC
292 * this means smaller mipmap levels have a linear tile mode
294 fmt
.tile_mode
= fdl_tile_mode(layout
, range
->baseMipLevel
);
296 bool ubwc_enabled
= fdl_ubwc_enabled(layout
, range
->baseMipLevel
);
298 unsigned fmt_tex
= fmt
.fmt
;
299 if (fmt_tex
== FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8
) {
300 if (aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
)
301 fmt_tex
= FMT6_Z24_UNORM_S8_UINT
;
302 if (aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
)
303 fmt_tex
= FMT6_S8Z24_UINT
;
304 /* TODO: also use this format with storage descriptor ? */
307 iview
->descriptor
[0] =
308 A6XX_TEX_CONST_0_TILE_MODE(fmt
.tile_mode
) |
309 COND(vk_format_is_srgb(format
), A6XX_TEX_CONST_0_SRGB
) |
310 A6XX_TEX_CONST_0_FMT(fmt_tex
) |
311 A6XX_TEX_CONST_0_SAMPLES(tu_msaa_samples(image
->samples
)) |
312 A6XX_TEX_CONST_0_SWAP(fmt
.swap
) |
313 tu6_texswiz(&pCreateInfo
->components
, format
, aspect_mask
) |
314 A6XX_TEX_CONST_0_MIPLVLS(tu_get_levelCount(image
, range
) - 1);
315 iview
->descriptor
[1] = A6XX_TEX_CONST_1_WIDTH(width
) | A6XX_TEX_CONST_1_HEIGHT(height
);
316 iview
->descriptor
[2] =
317 A6XX_TEX_CONST_2_FETCHSIZE(tu6_fetchsize(format
)) |
318 A6XX_TEX_CONST_2_PITCH(pitch
) |
319 A6XX_TEX_CONST_2_TYPE(tu6_tex_type(pCreateInfo
->viewType
));
320 iview
->descriptor
[3] = A6XX_TEX_CONST_3_ARRAY_PITCH(layer_size
);
321 iview
->descriptor
[4] = base_addr
;
322 iview
->descriptor
[5] = (base_addr
>> 32) | A6XX_TEX_CONST_5_DEPTH(depth
);
325 uint32_t block_width
, block_height
;
326 fdl6_get_ubwc_blockwidth(&image
->layout
,
327 &block_width
, &block_height
);
329 iview
->descriptor
[3] |= A6XX_TEX_CONST_3_FLAG
| A6XX_TEX_CONST_3_TILE_ALL
;
330 iview
->descriptor
[7] = ubwc_addr
;
331 iview
->descriptor
[8] = ubwc_addr
>> 32;
332 iview
->descriptor
[9] |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(layout
->ubwc_layer_size
>> 2);
333 iview
->descriptor
[10] |=
334 A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(ubwc_pitch
) |
335 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(util_logbase2_ceil(DIV_ROUND_UP(width
, block_width
))) |
336 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(util_logbase2_ceil(DIV_ROUND_UP(height
, block_height
)));
339 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
340 iview
->descriptor
[3] |=
341 A6XX_TEX_CONST_3_MIN_LAYERSZ(image
->layout
.slices
[image
->level_count
- 1].size0
);
344 /* only texture descriptor is valid for TEXTURE-only formats */
345 if (!(fmt
.supported
& FMT_COLOR
))
348 struct tu_native_format cfmt
= tu6_format_color(format
, layout
->tile_mode
);
349 cfmt
.tile_mode
= fmt
.tile_mode
;
351 if (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
352 memset(iview
->storage_descriptor
, 0, sizeof(iview
->storage_descriptor
));
354 iview
->storage_descriptor
[0] =
355 A6XX_IBO_0_FMT(fmt
.fmt
) |
356 A6XX_IBO_0_TILE_MODE(fmt
.tile_mode
);
357 iview
->storage_descriptor
[1] =
358 A6XX_IBO_1_WIDTH(width
) |
359 A6XX_IBO_1_HEIGHT(height
);
360 iview
->storage_descriptor
[2] =
361 A6XX_IBO_2_PITCH(pitch
) |
362 A6XX_IBO_2_TYPE(tu6_tex_type(pCreateInfo
->viewType
));
363 iview
->storage_descriptor
[3] = A6XX_IBO_3_ARRAY_PITCH(layer_size
);
365 iview
->storage_descriptor
[4] = base_addr
;
366 iview
->storage_descriptor
[5] = (base_addr
>> 32) | A6XX_IBO_5_DEPTH(depth
);
369 iview
->storage_descriptor
[3] |= A6XX_IBO_3_FLAG
| A6XX_IBO_3_UNK27
;
370 iview
->storage_descriptor
[7] |= ubwc_addr
;
371 iview
->storage_descriptor
[8] |= ubwc_addr
>> 32;
372 iview
->storage_descriptor
[9] = A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(layout
->ubwc_layer_size
>> 2);
373 iview
->storage_descriptor
[10] =
374 A6XX_IBO_10_FLAG_BUFFER_PITCH(ubwc_pitch
);
378 iview
->base_addr
= base_addr
;
379 iview
->ubwc_addr
= ubwc_addr
;
380 iview
->layer_size
= layer_size
;
381 iview
->ubwc_layer_size
= layout
->ubwc_layer_size
;
383 iview
->extent
.width
= width
;
384 iview
->extent
.height
= height
;
385 iview
->need_y2_align
=
386 (fmt
.tile_mode
== TILE6_LINEAR
&& range
->baseMipLevel
!= image
->level_count
- 1);
388 iview
->ubwc_enabled
= ubwc_enabled
;
390 /* note: these have same encoding for MRT and 2D (except 2D PITCH src) */
391 iview
->PITCH
= A6XX_RB_DEPTH_BUFFER_PITCH(pitch
).value
;
392 iview
->FLAG_BUFFER_PITCH
= A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(
393 .pitch
= ubwc_pitch
, .array_pitch
= layout
->ubwc_layer_size
>> 2).value
;
395 iview
->RB_MRT_BUF_INFO
= A6XX_RB_MRT_BUF_INFO(0,
396 .color_tile_mode
= cfmt
.tile_mode
,
397 .color_format
= cfmt
.fmt
,
398 .color_swap
= cfmt
.swap
).value
;
399 iview
->SP_FS_MRT_REG
= A6XX_SP_FS_MRT_REG(0,
400 .color_format
= cfmt
.fmt
,
401 .color_sint
= vk_format_is_sint(format
),
402 .color_uint
= vk_format_is_uint(format
)).value
;
404 iview
->SP_PS_2D_SRC_INFO
= A6XX_SP_PS_2D_SRC_INFO(
405 .color_format
= fmt
.fmt
,
406 .tile_mode
= fmt
.tile_mode
,
407 .color_swap
= fmt
.swap
,
408 .flags
= ubwc_enabled
,
409 .srgb
= vk_format_is_srgb(format
),
410 .samples
= tu_msaa_samples(image
->samples
),
411 .samples_average
= image
->samples
> 1 &&
412 !vk_format_is_int(format
) &&
413 !vk_format_is_depth_or_stencil(format
),
416 iview
->SP_PS_2D_SRC_SIZE
=
417 A6XX_SP_PS_2D_SRC_SIZE(.width
= width
, .height
= height
).value
;
419 iview
->RB_2D_DST_INFO
= A6XX_RB_2D_DST_INFO(
420 .color_format
= cfmt
.fmt
,
421 .tile_mode
= cfmt
.tile_mode
,
422 .color_swap
= cfmt
.swap
,
423 .flags
= ubwc_enabled
,
424 .srgb
= vk_format_is_srgb(format
)).value
;
426 iview
->RB_BLIT_DST_INFO
= A6XX_RB_BLIT_DST_INFO(
427 .tile_mode
= cfmt
.tile_mode
,
428 .samples
= tu_msaa_samples(iview
->image
->samples
),
429 .color_format
= cfmt
.fmt
,
430 .color_swap
= cfmt
.swap
,
431 .flags
= ubwc_enabled
).value
;
435 tu_image_queue_family_mask(const struct tu_image
*image
,
437 uint32_t queue_family
)
439 if (!image
->exclusive
)
440 return image
->queue_family_mask
;
441 if (family
== VK_QUEUE_FAMILY_EXTERNAL
)
442 return (1u << TU_MAX_QUEUE_FAMILIES
) - 1u;
443 if (family
== VK_QUEUE_FAMILY_IGNORED
)
444 return 1u << queue_family
;
449 tu_CreateImage(VkDevice device
,
450 const VkImageCreateInfo
*pCreateInfo
,
451 const VkAllocationCallbacks
*pAllocator
,
455 const VkNativeBufferANDROID
*gralloc_info
=
456 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
459 return tu_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
463 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
464 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT
) {
465 const VkImageDrmFormatModifierListCreateInfoEXT
*mod_info
=
466 vk_find_struct_const(pCreateInfo
->pNext
,
467 IMAGE_DRM_FORMAT_MODIFIER_LIST_CREATE_INFO_EXT
);
469 modifier
= DRM_FORMAT_MOD_LINEAR
;
470 for (unsigned i
= 0; i
< mod_info
->drmFormatModifierCount
; i
++) {
471 if (mod_info
->pDrmFormatModifiers
[i
] == DRM_FORMAT_MOD_QCOM_COMPRESSED
)
472 modifier
= DRM_FORMAT_MOD_QCOM_COMPRESSED
;
475 const struct wsi_image_create_info
*wsi_info
=
476 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
477 if (wsi_info
&& wsi_info
->scanout
)
478 modifier
= DRM_FORMAT_MOD_LINEAR
;
481 return tu_image_create(device
, pCreateInfo
, pAllocator
, pImage
, modifier
);
485 tu_DestroyImage(VkDevice _device
,
487 const VkAllocationCallbacks
*pAllocator
)
489 TU_FROM_HANDLE(tu_device
, device
, _device
);
490 TU_FROM_HANDLE(tu_image
, image
, _image
);
495 if (image
->owned_memory
!= VK_NULL_HANDLE
)
496 tu_FreeMemory(_device
, image
->owned_memory
, pAllocator
);
498 vk_free2(&device
->alloc
, pAllocator
, image
);
502 tu_GetImageSubresourceLayout(VkDevice _device
,
504 const VkImageSubresource
*pSubresource
,
505 VkSubresourceLayout
*pLayout
)
507 TU_FROM_HANDLE(tu_image
, image
, _image
);
509 const struct fdl_slice
*slice
= image
->layout
.slices
+ pSubresource
->mipLevel
;
511 pLayout
->offset
= fdl_surface_offset(&image
->layout
,
512 pSubresource
->mipLevel
,
513 pSubresource
->arrayLayer
);
514 pLayout
->size
= slice
->size0
;
516 slice
->pitch
* vk_format_get_blocksize(image
->vk_format
);
517 pLayout
->arrayPitch
= image
->layout
.layer_size
;
518 pLayout
->depthPitch
= slice
->size0
;
520 if (image
->layout
.ubwc_layer_size
) {
521 /* UBWC starts at offset 0 */
523 /* UBWC scanout won't match what the kernel wants if we have levels/layers */
524 assert(image
->level_count
== 1 && image
->layer_count
== 1);
528 VkResult
tu_GetImageDrmFormatModifierPropertiesEXT(
531 VkImageDrmFormatModifierPropertiesEXT
* pProperties
)
533 TU_FROM_HANDLE(tu_image
, image
, _image
);
535 assert(pProperties
->sType
==
536 VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_PROPERTIES_EXT
);
538 /* TODO invent a modifier for tiled but not UBWC buffers */
540 if (!image
->layout
.tile_mode
)
541 pProperties
->drmFormatModifier
= DRM_FORMAT_MOD_LINEAR
;
542 else if (image
->layout
.ubwc_layer_size
)
543 pProperties
->drmFormatModifier
= DRM_FORMAT_MOD_QCOM_COMPRESSED
;
545 pProperties
->drmFormatModifier
= DRM_FORMAT_MOD_INVALID
;
552 tu_CreateImageView(VkDevice _device
,
553 const VkImageViewCreateInfo
*pCreateInfo
,
554 const VkAllocationCallbacks
*pAllocator
,
557 TU_FROM_HANDLE(tu_device
, device
, _device
);
558 struct tu_image_view
*view
;
560 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
561 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
563 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
565 tu_image_view_init(view
, pCreateInfo
);
567 *pView
= tu_image_view_to_handle(view
);
573 tu_DestroyImageView(VkDevice _device
,
575 const VkAllocationCallbacks
*pAllocator
)
577 TU_FROM_HANDLE(tu_device
, device
, _device
);
578 TU_FROM_HANDLE(tu_image_view
, iview
, _iview
);
582 vk_free2(&device
->alloc
, pAllocator
, iview
);
586 tu_buffer_view_init(struct tu_buffer_view
*view
,
587 struct tu_device
*device
,
588 const VkBufferViewCreateInfo
*pCreateInfo
)
590 TU_FROM_HANDLE(tu_buffer
, buffer
, pCreateInfo
->buffer
);
592 view
->buffer
= buffer
;
594 enum VkFormat vfmt
= pCreateInfo
->format
;
595 enum pipe_format pfmt
= vk_format_to_pipe_format(vfmt
);
596 const struct tu_native_format fmt
= tu6_format_texture(vfmt
, TILE6_LINEAR
);
599 if (pCreateInfo
->range
== VK_WHOLE_SIZE
)
600 range
= buffer
->size
- pCreateInfo
->offset
;
602 range
= pCreateInfo
->range
;
603 uint32_t elements
= range
/ util_format_get_blocksize(pfmt
);
605 static const VkComponentMapping components
= {
606 .r
= VK_COMPONENT_SWIZZLE_R
,
607 .g
= VK_COMPONENT_SWIZZLE_G
,
608 .b
= VK_COMPONENT_SWIZZLE_B
,
609 .a
= VK_COMPONENT_SWIZZLE_A
,
612 uint64_t iova
= tu_buffer_iova(buffer
) + pCreateInfo
->offset
;
614 memset(&view
->descriptor
, 0, sizeof(view
->descriptor
));
616 view
->descriptor
[0] =
617 A6XX_TEX_CONST_0_TILE_MODE(TILE6_LINEAR
) |
618 A6XX_TEX_CONST_0_SWAP(fmt
.swap
) |
619 A6XX_TEX_CONST_0_FMT(fmt
.fmt
) |
620 A6XX_TEX_CONST_0_MIPLVLS(0) |
621 tu6_texswiz(&components
, vfmt
, VK_IMAGE_ASPECT_COLOR_BIT
);
622 COND(vk_format_is_srgb(vfmt
), A6XX_TEX_CONST_0_SRGB
);
623 view
->descriptor
[1] =
624 A6XX_TEX_CONST_1_WIDTH(elements
& MASK(15)) |
625 A6XX_TEX_CONST_1_HEIGHT(elements
>> 15);
626 view
->descriptor
[2] =
627 A6XX_TEX_CONST_2_UNK4
|
628 A6XX_TEX_CONST_2_UNK31
;
629 view
->descriptor
[4] = iova
;
630 view
->descriptor
[5] = iova
>> 32;
634 tu_CreateBufferView(VkDevice _device
,
635 const VkBufferViewCreateInfo
*pCreateInfo
,
636 const VkAllocationCallbacks
*pAllocator
,
639 TU_FROM_HANDLE(tu_device
, device
, _device
);
640 struct tu_buffer_view
*view
;
642 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
643 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
645 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
647 tu_buffer_view_init(view
, device
, pCreateInfo
);
649 *pView
= tu_buffer_view_to_handle(view
);
655 tu_DestroyBufferView(VkDevice _device
,
656 VkBufferView bufferView
,
657 const VkAllocationCallbacks
*pAllocator
)
659 TU_FROM_HANDLE(tu_device
, device
, _device
);
660 TU_FROM_HANDLE(tu_buffer_view
, view
, bufferView
);
665 vk_free2(&device
->alloc
, pAllocator
, view
);