2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "util/debug.h"
31 #include "util/u_atomic.h"
32 #include "util/format/u_format.h"
33 #include "vk_format.h"
35 #include "drm-uapi/drm_fourcc.h"
40 tu_image_create(VkDevice _device
,
41 const VkImageCreateInfo
*pCreateInfo
,
42 const VkAllocationCallbacks
*alloc
,
46 TU_FROM_HANDLE(tu_device
, device
, _device
);
47 struct tu_image
*image
= NULL
;
48 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
50 tu_assert(pCreateInfo
->mipLevels
> 0);
51 tu_assert(pCreateInfo
->arrayLayers
> 0);
52 tu_assert(pCreateInfo
->samples
> 0);
53 tu_assert(pCreateInfo
->extent
.width
> 0);
54 tu_assert(pCreateInfo
->extent
.height
> 0);
55 tu_assert(pCreateInfo
->extent
.depth
> 0);
57 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
58 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
60 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
62 image
->type
= pCreateInfo
->imageType
;
64 image
->vk_format
= pCreateInfo
->format
;
65 image
->tiling
= pCreateInfo
->tiling
;
66 image
->usage
= pCreateInfo
->usage
;
67 image
->flags
= pCreateInfo
->flags
;
68 image
->extent
= pCreateInfo
->extent
;
69 image
->level_count
= pCreateInfo
->mipLevels
;
70 image
->layer_count
= pCreateInfo
->arrayLayers
;
71 image
->samples
= pCreateInfo
->samples
;
73 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
74 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
75 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
76 if (pCreateInfo
->pQueueFamilyIndices
[i
] ==
77 VK_QUEUE_FAMILY_EXTERNAL
)
78 image
->queue_family_mask
|= (1u << TU_MAX_QUEUE_FAMILIES
) - 1u;
80 image
->queue_family_mask
|=
81 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
85 vk_find_struct_const(pCreateInfo
->pNext
,
86 EXTERNAL_MEMORY_IMAGE_CREATE_INFO
) != NULL
;
88 image
->layout
.tile_mode
= TILE6_3
;
90 !(device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOUBWC
);
92 /* disable tiling when linear is requested and for compressed formats */
93 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
||
94 modifier
== DRM_FORMAT_MOD_LINEAR
) {
95 image
->layout
.tile_mode
= TILE6_LINEAR
;
99 /* don't use UBWC with compressed formats */
100 if (vk_format_is_compressed(image
->vk_format
))
101 ubwc_enabled
= false;
103 /* UBWC can't be used with E5B9G9R9 */
104 if (image
->vk_format
== VK_FORMAT_E5B9G9R9_UFLOAT_PACK32
)
105 ubwc_enabled
= false;
107 /* separate stencil doesn't have a UBWC enable bit */
108 if (image
->vk_format
== VK_FORMAT_S8_UINT
)
109 ubwc_enabled
= false;
111 if (image
->extent
.depth
> 1) {
112 tu_finishme("UBWC with 3D textures");
113 ubwc_enabled
= false;
116 /* Disable UBWC for storage images.
118 * The closed GL driver skips UBWC for storage images (and additionally
119 * uses linear for writeonly images). We seem to have image tiling working
120 * in freedreno in general, so turnip matches that. freedreno also enables
121 * UBWC on images, but it's not really tested due to the lack of
122 * UBWC-enabled mipmaps in freedreno currently. Just match the closed GL
123 * behavior of no UBWC.
125 if (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)
126 ubwc_enabled
= false;
128 uint32_t ubwc_blockwidth
, ubwc_blockheight
;
129 fdl6_get_ubwc_blockwidth(&image
->layout
,
130 &ubwc_blockwidth
, &ubwc_blockheight
);
131 if (!ubwc_blockwidth
) {
132 tu_finishme("UBWC for cpp=%d", image
->layout
.cpp
);
133 ubwc_enabled
= false;
136 /* expect UBWC enabled if we asked for it */
137 assert(modifier
!= DRM_FORMAT_MOD_QCOM_COMPRESSED
|| ubwc_enabled
);
139 image
->layout
.ubwc
= ubwc_enabled
;
141 fdl6_layout(&image
->layout
, vk_format_to_pipe_format(image
->vk_format
),
143 pCreateInfo
->extent
.width
,
144 pCreateInfo
->extent
.height
,
145 pCreateInfo
->extent
.depth
,
146 pCreateInfo
->mipLevels
,
147 pCreateInfo
->arrayLayers
,
148 pCreateInfo
->imageType
== VK_IMAGE_TYPE_3D
);
150 *pImage
= tu_image_to_handle(image
);
155 enum a6xx_tex_fetchsize
156 tu6_fetchsize(VkFormat format
)
158 switch (vk_format_get_blocksize(format
)) {
159 case 1: return TFETCH6_1_BYTE
;
160 case 2: return TFETCH6_2_BYTE
;
161 case 4: return TFETCH6_4_BYTE
;
162 case 8: return TFETCH6_8_BYTE
;
163 case 16: return TFETCH6_16_BYTE
;
165 unreachable("bad block size");
170 tu6_texswiz(const VkComponentMapping
*comps
,
172 VkImageAspectFlagBits aspect_mask
)
174 unsigned char swiz
[4] = {comps
->r
, comps
->g
, comps
->b
, comps
->a
};
175 unsigned char vk_swizzle
[] = {
176 [VK_COMPONENT_SWIZZLE_ZERO
] = A6XX_TEX_ZERO
,
177 [VK_COMPONENT_SWIZZLE_ONE
] = A6XX_TEX_ONE
,
178 [VK_COMPONENT_SWIZZLE_R
] = A6XX_TEX_X
,
179 [VK_COMPONENT_SWIZZLE_G
] = A6XX_TEX_Y
,
180 [VK_COMPONENT_SWIZZLE_B
] = A6XX_TEX_Z
,
181 [VK_COMPONENT_SWIZZLE_A
] = A6XX_TEX_W
,
183 const unsigned char *fmt_swiz
= vk_format_description(format
)->swizzle
;
185 for (unsigned i
= 0; i
< 4; i
++) {
186 swiz
[i
] = (swiz
[i
] == VK_COMPONENT_SWIZZLE_IDENTITY
) ? i
: vk_swizzle
[swiz
[i
]];
187 /* if format has 0/1 in channel, use that (needed for bc1_rgb) */
189 if (aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
&&
190 format
== VK_FORMAT_D24_UNORM_S8_UINT
)
191 swiz
[i
] = A6XX_TEX_Y
;
192 switch (fmt_swiz
[swiz
[i
]]) {
193 case PIPE_SWIZZLE_0
: swiz
[i
] = A6XX_TEX_ZERO
; break;
194 case PIPE_SWIZZLE_1
: swiz
[i
] = A6XX_TEX_ONE
; break;
199 return A6XX_TEX_CONST_0_SWIZ_X(swiz
[0]) |
200 A6XX_TEX_CONST_0_SWIZ_Y(swiz
[1]) |
201 A6XX_TEX_CONST_0_SWIZ_Z(swiz
[2]) |
202 A6XX_TEX_CONST_0_SWIZ_W(swiz
[3]);
205 static enum a6xx_tex_type
206 tu6_tex_type(VkImageViewType type
)
210 case VK_IMAGE_VIEW_TYPE_1D
:
211 case VK_IMAGE_VIEW_TYPE_1D_ARRAY
:
213 case VK_IMAGE_VIEW_TYPE_2D
:
214 case VK_IMAGE_VIEW_TYPE_2D_ARRAY
:
216 case VK_IMAGE_VIEW_TYPE_3D
:
218 case VK_IMAGE_VIEW_TYPE_CUBE
:
219 case VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
:
220 return A6XX_TEX_CUBE
;
225 tu_cs_image_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
)
227 tu_cs_emit(cs
, iview
->PITCH
);
228 tu_cs_emit(cs
, iview
->layer_size
>> 6);
229 tu_cs_emit_qw(cs
, iview
->base_addr
+ iview
->layer_size
* layer
);
233 tu_cs_image_ref_2d(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
, bool src
)
235 tu_cs_emit_qw(cs
, iview
->base_addr
+ iview
->layer_size
* layer
);
236 /* SP_PS_2D_SRC_PITCH has shifted pitch field */
237 tu_cs_emit(cs
, iview
->PITCH
<< (src
? 9 : 0));
241 tu_cs_image_flag_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
)
243 tu_cs_emit_qw(cs
, iview
->ubwc_addr
+ iview
->ubwc_layer_size
* layer
);
244 tu_cs_emit(cs
, iview
->FLAG_BUFFER_PITCH
);
248 tu_image_view_init(struct tu_image_view
*iview
,
249 const VkImageViewCreateInfo
*pCreateInfo
)
251 TU_FROM_HANDLE(tu_image
, image
, pCreateInfo
->image
);
252 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
253 VkFormat format
= pCreateInfo
->format
;
254 VkImageAspectFlagBits aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
256 switch (image
->type
) {
257 case VK_IMAGE_TYPE_1D
:
258 case VK_IMAGE_TYPE_2D
:
259 assert(range
->baseArrayLayer
+ tu_get_layerCount(image
, range
) <=
262 case VK_IMAGE_TYPE_3D
:
263 assert(range
->baseArrayLayer
+ tu_get_layerCount(image
, range
) <=
264 tu_minify(image
->extent
.depth
, range
->baseMipLevel
));
267 unreachable("bad VkImageType");
270 iview
->image
= image
;
272 memset(iview
->descriptor
, 0, sizeof(iview
->descriptor
));
274 struct fdl_layout
*layout
= &image
->layout
;
276 uint32_t width
= u_minify(image
->extent
.width
, range
->baseMipLevel
);
277 uint32_t height
= u_minify(image
->extent
.height
, range
->baseMipLevel
);
278 uint32_t depth
= tu_get_layerCount(image
, range
);
279 switch (pCreateInfo
->viewType
) {
280 case VK_IMAGE_VIEW_TYPE_3D
:
281 depth
= u_minify(image
->extent
.depth
, range
->baseMipLevel
);
283 case VK_IMAGE_VIEW_TYPE_CUBE
:
284 case VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
:
291 uint64_t base_addr
= image
->bo
->iova
+ image
->bo_offset
+
292 fdl_surface_offset(layout
, range
->baseMipLevel
, range
->baseArrayLayer
);
293 uint64_t ubwc_addr
= image
->bo
->iova
+ image
->bo_offset
+
294 fdl_ubwc_offset(layout
, range
->baseMipLevel
, range
->baseArrayLayer
);
296 uint32_t pitch
= layout
->slices
[range
->baseMipLevel
].pitch
;
297 uint32_t ubwc_pitch
= layout
->ubwc_slices
[range
->baseMipLevel
].pitch
;
298 uint32_t layer_size
= fdl_layer_stride(layout
, range
->baseMipLevel
);
300 struct tu_native_format fmt
= tu6_format_texture(format
, layout
->tile_mode
);
301 /* note: freedreno layout assumes no TILE_ALL bit for non-UBWC
302 * this means smaller mipmap levels have a linear tile mode
304 fmt
.tile_mode
= fdl_tile_mode(layout
, range
->baseMipLevel
);
306 bool ubwc_enabled
= fdl_ubwc_enabled(layout
, range
->baseMipLevel
);
308 unsigned fmt_tex
= fmt
.fmt
;
309 if (fmt_tex
== FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8
) {
310 if (aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
)
311 fmt_tex
= FMT6_Z24_UNORM_S8_UINT
;
312 if (aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
)
313 fmt_tex
= FMT6_S8Z24_UINT
;
314 /* TODO: also use this format with storage descriptor ? */
317 iview
->descriptor
[0] =
318 A6XX_TEX_CONST_0_TILE_MODE(fmt
.tile_mode
) |
319 COND(vk_format_is_srgb(format
), A6XX_TEX_CONST_0_SRGB
) |
320 A6XX_TEX_CONST_0_FMT(fmt_tex
) |
321 A6XX_TEX_CONST_0_SAMPLES(tu_msaa_samples(image
->samples
)) |
322 A6XX_TEX_CONST_0_SWAP(fmt
.swap
) |
323 tu6_texswiz(&pCreateInfo
->components
, format
, aspect_mask
) |
324 A6XX_TEX_CONST_0_MIPLVLS(tu_get_levelCount(image
, range
) - 1);
325 iview
->descriptor
[1] = A6XX_TEX_CONST_1_WIDTH(width
) | A6XX_TEX_CONST_1_HEIGHT(height
);
326 iview
->descriptor
[2] =
327 A6XX_TEX_CONST_2_FETCHSIZE(tu6_fetchsize(format
)) |
328 A6XX_TEX_CONST_2_PITCH(pitch
) |
329 A6XX_TEX_CONST_2_TYPE(tu6_tex_type(pCreateInfo
->viewType
));
330 iview
->descriptor
[3] = A6XX_TEX_CONST_3_ARRAY_PITCH(layer_size
);
331 iview
->descriptor
[4] = base_addr
;
332 iview
->descriptor
[5] = (base_addr
>> 32) | A6XX_TEX_CONST_5_DEPTH(depth
);
335 uint32_t block_width
, block_height
;
336 fdl6_get_ubwc_blockwidth(&image
->layout
,
337 &block_width
, &block_height
);
339 iview
->descriptor
[3] |= A6XX_TEX_CONST_3_FLAG
| A6XX_TEX_CONST_3_TILE_ALL
;
340 iview
->descriptor
[7] = ubwc_addr
;
341 iview
->descriptor
[8] = ubwc_addr
>> 32;
342 iview
->descriptor
[9] |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(layout
->ubwc_layer_size
>> 2);
343 iview
->descriptor
[10] |=
344 A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(ubwc_pitch
) |
345 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(util_logbase2_ceil(DIV_ROUND_UP(width
, block_width
))) |
346 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(util_logbase2_ceil(DIV_ROUND_UP(height
, block_height
)));
349 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
350 iview
->descriptor
[3] |=
351 A6XX_TEX_CONST_3_MIN_LAYERSZ(image
->layout
.slices
[image
->level_count
- 1].size0
);
354 /* only texture descriptor is valid for TEXTURE-only formats */
355 if (!(fmt
.supported
& FMT_COLOR
))
358 struct tu_native_format cfmt
= tu6_format_color(format
, layout
->tile_mode
);
359 cfmt
.tile_mode
= fmt
.tile_mode
;
361 if (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
362 memset(iview
->storage_descriptor
, 0, sizeof(iview
->storage_descriptor
));
364 iview
->storage_descriptor
[0] =
365 A6XX_IBO_0_FMT(fmt
.fmt
) |
366 A6XX_IBO_0_TILE_MODE(fmt
.tile_mode
);
367 iview
->storage_descriptor
[1] =
368 A6XX_IBO_1_WIDTH(width
) |
369 A6XX_IBO_1_HEIGHT(height
);
370 iview
->storage_descriptor
[2] =
371 A6XX_IBO_2_PITCH(pitch
) |
372 A6XX_IBO_2_TYPE(tu6_tex_type(pCreateInfo
->viewType
));
373 iview
->storage_descriptor
[3] = A6XX_IBO_3_ARRAY_PITCH(layer_size
);
375 iview
->storage_descriptor
[4] = base_addr
;
376 iview
->storage_descriptor
[5] = (base_addr
>> 32) | A6XX_IBO_5_DEPTH(depth
);
379 iview
->storage_descriptor
[3] |= A6XX_IBO_3_FLAG
| A6XX_IBO_3_UNK27
;
380 iview
->storage_descriptor
[7] |= ubwc_addr
;
381 iview
->storage_descriptor
[8] |= ubwc_addr
>> 32;
382 iview
->storage_descriptor
[9] = A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(layout
->ubwc_layer_size
>> 2);
383 iview
->storage_descriptor
[10] =
384 A6XX_IBO_10_FLAG_BUFFER_PITCH(ubwc_pitch
);
388 iview
->base_addr
= base_addr
;
389 iview
->ubwc_addr
= ubwc_addr
;
390 iview
->layer_size
= layer_size
;
391 iview
->ubwc_layer_size
= layout
->ubwc_layer_size
;
393 iview
->extent
.width
= width
;
394 iview
->extent
.height
= height
;
395 iview
->need_y2_align
=
396 (fmt
.tile_mode
== TILE6_LINEAR
&& range
->baseMipLevel
!= image
->level_count
- 1);
398 iview
->ubwc_enabled
= ubwc_enabled
;
400 /* note: these have same encoding for MRT and 2D (except 2D PITCH src) */
401 iview
->PITCH
= A6XX_RB_DEPTH_BUFFER_PITCH(pitch
).value
;
402 iview
->FLAG_BUFFER_PITCH
= A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(
403 .pitch
= ubwc_pitch
, .array_pitch
= layout
->ubwc_layer_size
>> 2).value
;
405 iview
->RB_MRT_BUF_INFO
= A6XX_RB_MRT_BUF_INFO(0,
406 .color_tile_mode
= cfmt
.tile_mode
,
407 .color_format
= cfmt
.fmt
,
408 .color_swap
= cfmt
.swap
).value
;
409 iview
->SP_FS_MRT_REG
= A6XX_SP_FS_MRT_REG(0,
410 .color_format
= cfmt
.fmt
,
411 .color_sint
= vk_format_is_sint(format
),
412 .color_uint
= vk_format_is_uint(format
)).value
;
414 iview
->SP_PS_2D_SRC_INFO
= A6XX_SP_PS_2D_SRC_INFO(
415 .color_format
= fmt
.fmt
,
416 .tile_mode
= fmt
.tile_mode
,
417 .color_swap
= fmt
.swap
,
418 .flags
= ubwc_enabled
,
419 .srgb
= vk_format_is_srgb(format
),
420 .samples
= tu_msaa_samples(image
->samples
),
421 .samples_average
= image
->samples
> 1 &&
422 !vk_format_is_int(format
) &&
423 !vk_format_is_depth_or_stencil(format
),
426 iview
->SP_PS_2D_SRC_SIZE
=
427 A6XX_SP_PS_2D_SRC_SIZE(.width
= width
, .height
= height
).value
;
429 iview
->RB_2D_DST_INFO
= A6XX_RB_2D_DST_INFO(
430 .color_format
= cfmt
.fmt
,
431 .tile_mode
= cfmt
.tile_mode
,
432 .color_swap
= cfmt
.swap
,
433 .flags
= ubwc_enabled
,
434 .srgb
= vk_format_is_srgb(format
)).value
;
436 iview
->RB_BLIT_DST_INFO
= A6XX_RB_BLIT_DST_INFO(
437 .tile_mode
= cfmt
.tile_mode
,
438 .samples
= tu_msaa_samples(iview
->image
->samples
),
439 .color_format
= cfmt
.fmt
,
440 .color_swap
= cfmt
.swap
,
441 .flags
= ubwc_enabled
).value
;
445 tu_image_queue_family_mask(const struct tu_image
*image
,
447 uint32_t queue_family
)
449 if (!image
->exclusive
)
450 return image
->queue_family_mask
;
451 if (family
== VK_QUEUE_FAMILY_EXTERNAL
)
452 return (1u << TU_MAX_QUEUE_FAMILIES
) - 1u;
453 if (family
== VK_QUEUE_FAMILY_IGNORED
)
454 return 1u << queue_family
;
459 tu_CreateImage(VkDevice device
,
460 const VkImageCreateInfo
*pCreateInfo
,
461 const VkAllocationCallbacks
*pAllocator
,
465 const VkNativeBufferANDROID
*gralloc_info
=
466 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
469 return tu_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
473 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
474 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT
) {
475 const VkImageDrmFormatModifierListCreateInfoEXT
*mod_info
=
476 vk_find_struct_const(pCreateInfo
->pNext
,
477 IMAGE_DRM_FORMAT_MODIFIER_LIST_CREATE_INFO_EXT
);
479 modifier
= DRM_FORMAT_MOD_LINEAR
;
480 for (unsigned i
= 0; i
< mod_info
->drmFormatModifierCount
; i
++) {
481 if (mod_info
->pDrmFormatModifiers
[i
] == DRM_FORMAT_MOD_QCOM_COMPRESSED
)
482 modifier
= DRM_FORMAT_MOD_QCOM_COMPRESSED
;
485 const struct wsi_image_create_info
*wsi_info
=
486 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
487 if (wsi_info
&& wsi_info
->scanout
)
488 modifier
= DRM_FORMAT_MOD_LINEAR
;
491 return tu_image_create(device
, pCreateInfo
, pAllocator
, pImage
, modifier
);
495 tu_DestroyImage(VkDevice _device
,
497 const VkAllocationCallbacks
*pAllocator
)
499 TU_FROM_HANDLE(tu_device
, device
, _device
);
500 TU_FROM_HANDLE(tu_image
, image
, _image
);
505 if (image
->owned_memory
!= VK_NULL_HANDLE
)
506 tu_FreeMemory(_device
, image
->owned_memory
, pAllocator
);
508 vk_free2(&device
->alloc
, pAllocator
, image
);
512 tu_GetImageSubresourceLayout(VkDevice _device
,
514 const VkImageSubresource
*pSubresource
,
515 VkSubresourceLayout
*pLayout
)
517 TU_FROM_HANDLE(tu_image
, image
, _image
);
519 const struct fdl_slice
*slice
= image
->layout
.slices
+ pSubresource
->mipLevel
;
521 pLayout
->offset
= fdl_surface_offset(&image
->layout
,
522 pSubresource
->mipLevel
,
523 pSubresource
->arrayLayer
);
524 pLayout
->size
= slice
->size0
;
526 slice
->pitch
* vk_format_get_blockheight(image
->vk_format
);
527 pLayout
->arrayPitch
= image
->layout
.layer_size
;
528 pLayout
->depthPitch
= slice
->size0
;
530 if (image
->layout
.ubwc_layer_size
) {
531 /* UBWC starts at offset 0 */
533 /* UBWC scanout won't match what the kernel wants if we have levels/layers */
534 assert(image
->level_count
== 1 && image
->layer_count
== 1);
538 VkResult
tu_GetImageDrmFormatModifierPropertiesEXT(
541 VkImageDrmFormatModifierPropertiesEXT
* pProperties
)
543 TU_FROM_HANDLE(tu_image
, image
, _image
);
545 assert(pProperties
->sType
==
546 VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_PROPERTIES_EXT
);
548 /* TODO invent a modifier for tiled but not UBWC buffers */
550 if (!image
->layout
.tile_mode
)
551 pProperties
->drmFormatModifier
= DRM_FORMAT_MOD_LINEAR
;
552 else if (image
->layout
.ubwc_layer_size
)
553 pProperties
->drmFormatModifier
= DRM_FORMAT_MOD_QCOM_COMPRESSED
;
555 pProperties
->drmFormatModifier
= DRM_FORMAT_MOD_INVALID
;
562 tu_CreateImageView(VkDevice _device
,
563 const VkImageViewCreateInfo
*pCreateInfo
,
564 const VkAllocationCallbacks
*pAllocator
,
567 TU_FROM_HANDLE(tu_device
, device
, _device
);
568 struct tu_image_view
*view
;
570 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
571 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
573 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
575 tu_image_view_init(view
, pCreateInfo
);
577 *pView
= tu_image_view_to_handle(view
);
583 tu_DestroyImageView(VkDevice _device
,
585 const VkAllocationCallbacks
*pAllocator
)
587 TU_FROM_HANDLE(tu_device
, device
, _device
);
588 TU_FROM_HANDLE(tu_image_view
, iview
, _iview
);
592 vk_free2(&device
->alloc
, pAllocator
, iview
);
596 tu_buffer_view_init(struct tu_buffer_view
*view
,
597 struct tu_device
*device
,
598 const VkBufferViewCreateInfo
*pCreateInfo
)
600 TU_FROM_HANDLE(tu_buffer
, buffer
, pCreateInfo
->buffer
);
602 view
->buffer
= buffer
;
604 enum VkFormat vfmt
= pCreateInfo
->format
;
605 enum pipe_format pfmt
= vk_format_to_pipe_format(vfmt
);
606 const struct tu_native_format fmt
= tu6_format_texture(vfmt
, TILE6_LINEAR
);
609 if (pCreateInfo
->range
== VK_WHOLE_SIZE
)
610 range
= buffer
->size
- pCreateInfo
->offset
;
612 range
= pCreateInfo
->range
;
613 uint32_t elements
= range
/ util_format_get_blocksize(pfmt
);
615 static const VkComponentMapping components
= {
616 .r
= VK_COMPONENT_SWIZZLE_R
,
617 .g
= VK_COMPONENT_SWIZZLE_G
,
618 .b
= VK_COMPONENT_SWIZZLE_B
,
619 .a
= VK_COMPONENT_SWIZZLE_A
,
622 uint64_t iova
= tu_buffer_iova(buffer
) + pCreateInfo
->offset
;
624 memset(&view
->descriptor
, 0, sizeof(view
->descriptor
));
626 view
->descriptor
[0] =
627 A6XX_TEX_CONST_0_TILE_MODE(TILE6_LINEAR
) |
628 A6XX_TEX_CONST_0_SWAP(fmt
.swap
) |
629 A6XX_TEX_CONST_0_FMT(fmt
.fmt
) |
630 A6XX_TEX_CONST_0_MIPLVLS(0) |
631 tu6_texswiz(&components
, vfmt
, VK_IMAGE_ASPECT_COLOR_BIT
);
632 COND(vk_format_is_srgb(vfmt
), A6XX_TEX_CONST_0_SRGB
);
633 view
->descriptor
[1] =
634 A6XX_TEX_CONST_1_WIDTH(elements
& MASK(15)) |
635 A6XX_TEX_CONST_1_HEIGHT(elements
>> 15);
636 view
->descriptor
[2] =
637 A6XX_TEX_CONST_2_UNK4
|
638 A6XX_TEX_CONST_2_UNK31
;
639 view
->descriptor
[4] = iova
;
640 view
->descriptor
[5] = iova
>> 32;
644 tu_CreateBufferView(VkDevice _device
,
645 const VkBufferViewCreateInfo
*pCreateInfo
,
646 const VkAllocationCallbacks
*pAllocator
,
649 TU_FROM_HANDLE(tu_device
, device
, _device
);
650 struct tu_buffer_view
*view
;
652 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
653 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
655 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
657 tu_buffer_view_init(view
, device
, pCreateInfo
);
659 *pView
= tu_buffer_view_to_handle(view
);
665 tu_DestroyBufferView(VkDevice _device
,
666 VkBufferView bufferView
,
667 const VkAllocationCallbacks
*pAllocator
)
669 TU_FROM_HANDLE(tu_device
, device
, _device
);
670 TU_FROM_HANDLE(tu_buffer_view
, view
, bufferView
);
675 vk_free2(&device
->alloc
, pAllocator
, view
);