turnip: implement VK_KHR_sampler_ycbcr_conversion
[mesa.git] / src / freedreno / vulkan / tu_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "util/debug.h"
31 #include "util/u_atomic.h"
32 #include "util/format/u_format.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "drm-uapi/drm_fourcc.h"
36
37 #include "tu_cs.h"
38
39 VkResult
40 tu_image_create(VkDevice _device,
41 const VkImageCreateInfo *pCreateInfo,
42 const VkAllocationCallbacks *alloc,
43 VkImage *pImage,
44 uint64_t modifier)
45 {
46 TU_FROM_HANDLE(tu_device, device, _device);
47 struct tu_image *image = NULL;
48 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
49
50 tu_assert(pCreateInfo->mipLevels > 0);
51 tu_assert(pCreateInfo->arrayLayers > 0);
52 tu_assert(pCreateInfo->samples > 0);
53 tu_assert(pCreateInfo->extent.width > 0);
54 tu_assert(pCreateInfo->extent.height > 0);
55 tu_assert(pCreateInfo->extent.depth > 0);
56
57 image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
58 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
59 if (!image)
60 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
61
62 image->type = pCreateInfo->imageType;
63
64 image->vk_format = pCreateInfo->format;
65 image->tiling = pCreateInfo->tiling;
66 image->usage = pCreateInfo->usage;
67 image->flags = pCreateInfo->flags;
68 image->extent = pCreateInfo->extent;
69 image->level_count = pCreateInfo->mipLevels;
70 image->layer_count = pCreateInfo->arrayLayers;
71 image->samples = pCreateInfo->samples;
72
73 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
74 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
75 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
76 if (pCreateInfo->pQueueFamilyIndices[i] ==
77 VK_QUEUE_FAMILY_EXTERNAL)
78 image->queue_family_mask |= (1u << TU_MAX_QUEUE_FAMILIES) - 1u;
79 else
80 image->queue_family_mask |=
81 1u << pCreateInfo->pQueueFamilyIndices[i];
82 }
83
84 image->shareable =
85 vk_find_struct_const(pCreateInfo->pNext,
86 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
87
88 image->layout.tile_mode = TILE6_3;
89 bool ubwc_enabled =
90 !(device->physical_device->instance->debug_flags & TU_DEBUG_NOUBWC);
91
92 /* disable tiling when linear is requested and for compressed formats */
93 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR ||
94 modifier == DRM_FORMAT_MOD_LINEAR) {
95 image->layout.tile_mode = TILE6_LINEAR;
96 ubwc_enabled = false;
97 }
98
99 /* don't use UBWC with compressed formats */
100 if (vk_format_is_compressed(image->vk_format))
101 ubwc_enabled = false;
102
103 /* UBWC can't be used with E5B9G9R9 */
104 if (image->vk_format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32)
105 ubwc_enabled = false;
106
107 /* separate stencil doesn't have a UBWC enable bit */
108 if (image->vk_format == VK_FORMAT_S8_UINT)
109 ubwc_enabled = false;
110
111 if (image->extent.depth > 1) {
112 tu_finishme("UBWC with 3D textures");
113 ubwc_enabled = false;
114 }
115
116 /* Disable UBWC for storage images.
117 *
118 * The closed GL driver skips UBWC for storage images (and additionally
119 * uses linear for writeonly images). We seem to have image tiling working
120 * in freedreno in general, so turnip matches that. freedreno also enables
121 * UBWC on images, but it's not really tested due to the lack of
122 * UBWC-enabled mipmaps in freedreno currently. Just match the closed GL
123 * behavior of no UBWC.
124 */
125 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
126 ubwc_enabled = false;
127
128 uint32_t ubwc_blockwidth, ubwc_blockheight;
129 fdl6_get_ubwc_blockwidth(&image->layout,
130 &ubwc_blockwidth, &ubwc_blockheight);
131 if (!ubwc_blockwidth) {
132 tu_finishme("UBWC for cpp=%d", image->layout.cpp);
133 ubwc_enabled = false;
134 }
135
136 /* expect UBWC enabled if we asked for it */
137 assert(modifier != DRM_FORMAT_MOD_QCOM_COMPRESSED || ubwc_enabled);
138
139 image->layout.ubwc = ubwc_enabled;
140
141 fdl6_layout(&image->layout, vk_format_to_pipe_format(image->vk_format),
142 image->samples,
143 pCreateInfo->extent.width,
144 pCreateInfo->extent.height,
145 pCreateInfo->extent.depth,
146 pCreateInfo->mipLevels,
147 pCreateInfo->arrayLayers,
148 pCreateInfo->imageType == VK_IMAGE_TYPE_3D);
149
150 *pImage = tu_image_to_handle(image);
151
152 return VK_SUCCESS;
153 }
154
155 enum a6xx_tex_fetchsize
156 tu6_fetchsize(VkFormat format)
157 {
158 switch (vk_format_get_blocksize(format)) {
159 case 1: return TFETCH6_1_BYTE;
160 case 2: return TFETCH6_2_BYTE;
161 case 4: return TFETCH6_4_BYTE;
162 case 8: return TFETCH6_8_BYTE;
163 case 16: return TFETCH6_16_BYTE;
164 default:
165 unreachable("bad block size");
166 }
167 }
168
169 static void
170 compose_swizzle(unsigned char *swiz, const VkComponentMapping *mapping)
171 {
172 unsigned char src_swiz[4] = { swiz[0], swiz[1], swiz[2], swiz[3] };
173 VkComponentSwizzle vk_swiz[4] = {
174 mapping->r, mapping->g, mapping->b, mapping->a
175 };
176 for (int i = 0; i < 4; i++) {
177 switch (vk_swiz[i]) {
178 case VK_COMPONENT_SWIZZLE_IDENTITY:
179 swiz[i] = src_swiz[i];
180 break;
181 case VK_COMPONENT_SWIZZLE_R...VK_COMPONENT_SWIZZLE_A:
182 swiz[i] = src_swiz[vk_swiz[i] - VK_COMPONENT_SWIZZLE_R];
183 break;
184 case VK_COMPONENT_SWIZZLE_ZERO:
185 swiz[i] = A6XX_TEX_ZERO;
186 break;
187 case VK_COMPONENT_SWIZZLE_ONE:
188 swiz[i] = A6XX_TEX_ONE;
189 break;
190 default:
191 unreachable("unexpected swizzle");
192 }
193 }
194 }
195
196 static uint32_t
197 tu6_texswiz(const VkComponentMapping *comps,
198 const struct tu_sampler_ycbcr_conversion *conversion,
199 VkFormat format,
200 VkImageAspectFlagBits aspect_mask)
201 {
202 unsigned char swiz[4] = {
203 A6XX_TEX_X, A6XX_TEX_Y, A6XX_TEX_Z, A6XX_TEX_W,
204 };
205
206 switch (format) {
207 case VK_FORMAT_BC1_RGB_UNORM_BLOCK:
208 case VK_FORMAT_BC1_RGB_SRGB_BLOCK:
209 /* same hardware format is used for BC1_RGB / BC1_RGBA */
210 swiz[3] = A6XX_TEX_ONE;
211 break;
212 case VK_FORMAT_D24_UNORM_S8_UINT:
213 /* for D24S8, stencil is in the 2nd channel of the hardware format */
214 if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
215 swiz[0] = A6XX_TEX_Y;
216 swiz[1] = A6XX_TEX_ZERO;
217 }
218 default:
219 break;
220 }
221
222 compose_swizzle(swiz, comps);
223 if (conversion)
224 compose_swizzle(swiz, &conversion->components);
225
226 return A6XX_TEX_CONST_0_SWIZ_X(swiz[0]) |
227 A6XX_TEX_CONST_0_SWIZ_Y(swiz[1]) |
228 A6XX_TEX_CONST_0_SWIZ_Z(swiz[2]) |
229 A6XX_TEX_CONST_0_SWIZ_W(swiz[3]);
230 }
231
232 static enum a6xx_tex_type
233 tu6_tex_type(VkImageViewType type)
234 {
235 switch (type) {
236 default:
237 case VK_IMAGE_VIEW_TYPE_1D:
238 case VK_IMAGE_VIEW_TYPE_1D_ARRAY:
239 return A6XX_TEX_1D;
240 case VK_IMAGE_VIEW_TYPE_2D:
241 case VK_IMAGE_VIEW_TYPE_2D_ARRAY:
242 return A6XX_TEX_2D;
243 case VK_IMAGE_VIEW_TYPE_3D:
244 return A6XX_TEX_3D;
245 case VK_IMAGE_VIEW_TYPE_CUBE:
246 case VK_IMAGE_VIEW_TYPE_CUBE_ARRAY:
247 return A6XX_TEX_CUBE;
248 }
249 }
250
251 void
252 tu_cs_image_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
253 {
254 tu_cs_emit(cs, iview->PITCH);
255 tu_cs_emit(cs, iview->layer_size >> 6);
256 tu_cs_emit_qw(cs, iview->base_addr + iview->layer_size * layer);
257 }
258
259 void
260 tu_cs_image_ref_2d(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer, bool src)
261 {
262 tu_cs_emit_qw(cs, iview->base_addr + iview->layer_size * layer);
263 /* SP_PS_2D_SRC_PITCH has shifted pitch field */
264 tu_cs_emit(cs, iview->PITCH << (src ? 9 : 0));
265 }
266
267 void
268 tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
269 {
270 tu_cs_emit_qw(cs, iview->ubwc_addr + iview->ubwc_layer_size * layer);
271 tu_cs_emit(cs, iview->FLAG_BUFFER_PITCH);
272 }
273
274 void
275 tu_image_view_init(struct tu_image_view *iview,
276 const VkImageViewCreateInfo *pCreateInfo)
277 {
278 TU_FROM_HANDLE(tu_image, image, pCreateInfo->image);
279 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
280 VkFormat format = pCreateInfo->format;
281 VkImageAspectFlagBits aspect_mask = pCreateInfo->subresourceRange.aspectMask;
282
283 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
284 vk_find_struct_const(pCreateInfo->pNext, SAMPLER_YCBCR_CONVERSION_INFO);
285 const struct tu_sampler_ycbcr_conversion *conversion = ycbcr_conversion ?
286 tu_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion) : NULL;
287
288 switch (image->type) {
289 case VK_IMAGE_TYPE_1D:
290 case VK_IMAGE_TYPE_2D:
291 assert(range->baseArrayLayer + tu_get_layerCount(image, range) <=
292 image->layer_count);
293 break;
294 case VK_IMAGE_TYPE_3D:
295 assert(range->baseArrayLayer + tu_get_layerCount(image, range) <=
296 tu_minify(image->extent.depth, range->baseMipLevel));
297 break;
298 default:
299 unreachable("bad VkImageType");
300 }
301
302 iview->image = image;
303
304 memset(iview->descriptor, 0, sizeof(iview->descriptor));
305
306 struct fdl_layout *layout = &image->layout;
307
308 uint32_t width = u_minify(image->extent.width, range->baseMipLevel);
309 uint32_t height = u_minify(image->extent.height, range->baseMipLevel);
310 uint32_t depth = tu_get_layerCount(image, range);
311 switch (pCreateInfo->viewType) {
312 case VK_IMAGE_VIEW_TYPE_3D:
313 depth = u_minify(image->extent.depth, range->baseMipLevel);
314 break;
315 case VK_IMAGE_VIEW_TYPE_CUBE:
316 case VK_IMAGE_VIEW_TYPE_CUBE_ARRAY:
317 depth /= 6;
318 break;
319 default:
320 break;
321 }
322
323 uint64_t base_addr = image->bo->iova + image->bo_offset +
324 fdl_surface_offset(layout, range->baseMipLevel, range->baseArrayLayer);
325 uint64_t ubwc_addr = image->bo->iova + image->bo_offset +
326 fdl_ubwc_offset(layout, range->baseMipLevel, range->baseArrayLayer);
327
328 uint32_t pitch = layout->slices[range->baseMipLevel].pitch;
329 uint32_t ubwc_pitch = layout->ubwc_slices[range->baseMipLevel].pitch;
330 uint32_t layer_size = fdl_layer_stride(layout, range->baseMipLevel);
331
332 struct tu_native_format fmt = tu6_format_texture(format, layout->tile_mode);
333 /* note: freedreno layout assumes no TILE_ALL bit for non-UBWC
334 * this means smaller mipmap levels have a linear tile mode
335 */
336 fmt.tile_mode = fdl_tile_mode(layout, range->baseMipLevel);
337
338 bool ubwc_enabled = fdl_ubwc_enabled(layout, range->baseMipLevel);
339
340 unsigned fmt_tex = fmt.fmt;
341 if (fmt_tex == FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8) {
342 if (aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT)
343 fmt_tex = FMT6_Z24_UNORM_S8_UINT;
344 if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
345 fmt_tex = FMT6_S8Z24_UINT;
346 /* TODO: also use this format with storage descriptor ? */
347 }
348
349 iview->descriptor[0] =
350 A6XX_TEX_CONST_0_TILE_MODE(fmt.tile_mode) |
351 COND(vk_format_is_srgb(format), A6XX_TEX_CONST_0_SRGB) |
352 A6XX_TEX_CONST_0_FMT(fmt_tex) |
353 A6XX_TEX_CONST_0_SAMPLES(tu_msaa_samples(image->samples)) |
354 A6XX_TEX_CONST_0_SWAP(fmt.swap) |
355 tu6_texswiz(&pCreateInfo->components, conversion, format, aspect_mask) |
356 A6XX_TEX_CONST_0_MIPLVLS(tu_get_levelCount(image, range) - 1);
357 iview->descriptor[1] = A6XX_TEX_CONST_1_WIDTH(width) | A6XX_TEX_CONST_1_HEIGHT(height);
358 iview->descriptor[2] =
359 A6XX_TEX_CONST_2_FETCHSIZE(tu6_fetchsize(format)) |
360 A6XX_TEX_CONST_2_PITCH(pitch) |
361 A6XX_TEX_CONST_2_TYPE(tu6_tex_type(pCreateInfo->viewType));
362 iview->descriptor[3] = A6XX_TEX_CONST_3_ARRAY_PITCH(layer_size);
363 iview->descriptor[4] = base_addr;
364 iview->descriptor[5] = (base_addr >> 32) | A6XX_TEX_CONST_5_DEPTH(depth);
365
366 if (ubwc_enabled) {
367 uint32_t block_width, block_height;
368 fdl6_get_ubwc_blockwidth(&image->layout,
369 &block_width, &block_height);
370
371 iview->descriptor[3] |= A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_TILE_ALL;
372 iview->descriptor[7] = ubwc_addr;
373 iview->descriptor[8] = ubwc_addr >> 32;
374 iview->descriptor[9] |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(layout->ubwc_layer_size >> 2);
375 iview->descriptor[10] |=
376 A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(ubwc_pitch) |
377 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(util_logbase2_ceil(DIV_ROUND_UP(width, block_width))) |
378 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(util_logbase2_ceil(DIV_ROUND_UP(height, block_height)));
379 }
380
381 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
382 iview->descriptor[3] |=
383 A6XX_TEX_CONST_3_MIN_LAYERSZ(image->layout.slices[image->level_count - 1].size0);
384 }
385
386 iview->SP_PS_2D_SRC_INFO = A6XX_SP_PS_2D_SRC_INFO(
387 .color_format = fmt.fmt,
388 .tile_mode = fmt.tile_mode,
389 .color_swap = fmt.swap,
390 .flags = ubwc_enabled,
391 .srgb = vk_format_is_srgb(format),
392 .samples = tu_msaa_samples(image->samples),
393 .samples_average = image->samples > 1 &&
394 !vk_format_is_int(format) &&
395 !vk_format_is_depth_or_stencil(format),
396 .unk20 = 1,
397 .unk22 = 1).value;
398 iview->SP_PS_2D_SRC_SIZE =
399 A6XX_SP_PS_2D_SRC_SIZE(.width = width, .height = height).value;
400
401 /* note: these have same encoding for MRT and 2D (except 2D PITCH src) */
402 iview->PITCH = A6XX_RB_DEPTH_BUFFER_PITCH(pitch).value;
403 iview->FLAG_BUFFER_PITCH = A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(
404 .pitch = ubwc_pitch, .array_pitch = layout->ubwc_layer_size >> 2).value;
405
406 iview->base_addr = base_addr;
407 iview->ubwc_addr = ubwc_addr;
408 iview->layer_size = layer_size;
409 iview->ubwc_layer_size = layout->ubwc_layer_size;
410
411 /* Don't set fields that are only used for attachments/blit dest if COLOR
412 * is unsupported.
413 */
414 if (!(fmt.supported & FMT_COLOR))
415 return;
416
417 struct tu_native_format cfmt = tu6_format_color(format, layout->tile_mode);
418 cfmt.tile_mode = fmt.tile_mode;
419
420 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT) {
421 memset(iview->storage_descriptor, 0, sizeof(iview->storage_descriptor));
422
423 iview->storage_descriptor[0] =
424 A6XX_IBO_0_FMT(fmt.fmt) |
425 A6XX_IBO_0_TILE_MODE(fmt.tile_mode);
426 iview->storage_descriptor[1] =
427 A6XX_IBO_1_WIDTH(width) |
428 A6XX_IBO_1_HEIGHT(height);
429 iview->storage_descriptor[2] =
430 A6XX_IBO_2_PITCH(pitch) |
431 A6XX_IBO_2_TYPE(tu6_tex_type(pCreateInfo->viewType));
432 iview->storage_descriptor[3] = A6XX_IBO_3_ARRAY_PITCH(layer_size);
433
434 iview->storage_descriptor[4] = base_addr;
435 iview->storage_descriptor[5] = (base_addr >> 32) | A6XX_IBO_5_DEPTH(depth);
436
437 if (ubwc_enabled) {
438 iview->storage_descriptor[3] |= A6XX_IBO_3_FLAG | A6XX_IBO_3_UNK27;
439 iview->storage_descriptor[7] |= ubwc_addr;
440 iview->storage_descriptor[8] |= ubwc_addr >> 32;
441 iview->storage_descriptor[9] = A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(layout->ubwc_layer_size >> 2);
442 iview->storage_descriptor[10] =
443 A6XX_IBO_10_FLAG_BUFFER_PITCH(ubwc_pitch);
444 }
445 }
446
447 iview->extent.width = width;
448 iview->extent.height = height;
449 iview->need_y2_align =
450 (fmt.tile_mode == TILE6_LINEAR && range->baseMipLevel != image->level_count - 1);
451
452 iview->ubwc_enabled = ubwc_enabled;
453
454 iview->RB_MRT_BUF_INFO = A6XX_RB_MRT_BUF_INFO(0,
455 .color_tile_mode = cfmt.tile_mode,
456 .color_format = cfmt.fmt,
457 .color_swap = cfmt.swap).value;
458 iview->SP_FS_MRT_REG = A6XX_SP_FS_MRT_REG(0,
459 .color_format = cfmt.fmt,
460 .color_sint = vk_format_is_sint(format),
461 .color_uint = vk_format_is_uint(format)).value;
462
463 iview->RB_2D_DST_INFO = A6XX_RB_2D_DST_INFO(
464 .color_format = cfmt.fmt,
465 .tile_mode = cfmt.tile_mode,
466 .color_swap = cfmt.swap,
467 .flags = ubwc_enabled,
468 .srgb = vk_format_is_srgb(format)).value;
469
470 iview->RB_BLIT_DST_INFO = A6XX_RB_BLIT_DST_INFO(
471 .tile_mode = cfmt.tile_mode,
472 .samples = tu_msaa_samples(iview->image->samples),
473 .color_format = cfmt.fmt,
474 .color_swap = cfmt.swap,
475 .flags = ubwc_enabled).value;
476 }
477
478 unsigned
479 tu_image_queue_family_mask(const struct tu_image *image,
480 uint32_t family,
481 uint32_t queue_family)
482 {
483 if (!image->exclusive)
484 return image->queue_family_mask;
485 if (family == VK_QUEUE_FAMILY_EXTERNAL)
486 return (1u << TU_MAX_QUEUE_FAMILIES) - 1u;
487 if (family == VK_QUEUE_FAMILY_IGNORED)
488 return 1u << queue_family;
489 return 1u << family;
490 }
491
492 VkResult
493 tu_CreateImage(VkDevice device,
494 const VkImageCreateInfo *pCreateInfo,
495 const VkAllocationCallbacks *pAllocator,
496 VkImage *pImage)
497 {
498 #ifdef ANDROID
499 const VkNativeBufferANDROID *gralloc_info =
500 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
501
502 if (gralloc_info)
503 return tu_image_from_gralloc(device, pCreateInfo, gralloc_info,
504 pAllocator, pImage);
505 #endif
506
507 uint64_t modifier = DRM_FORMAT_MOD_INVALID;
508 if (pCreateInfo->tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) {
509 const VkImageDrmFormatModifierListCreateInfoEXT *mod_info =
510 vk_find_struct_const(pCreateInfo->pNext,
511 IMAGE_DRM_FORMAT_MODIFIER_LIST_CREATE_INFO_EXT);
512
513 modifier = DRM_FORMAT_MOD_LINEAR;
514 for (unsigned i = 0; i < mod_info->drmFormatModifierCount; i++) {
515 if (mod_info->pDrmFormatModifiers[i] == DRM_FORMAT_MOD_QCOM_COMPRESSED)
516 modifier = DRM_FORMAT_MOD_QCOM_COMPRESSED;
517 }
518 } else {
519 const struct wsi_image_create_info *wsi_info =
520 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
521 if (wsi_info && wsi_info->scanout)
522 modifier = DRM_FORMAT_MOD_LINEAR;
523 }
524
525 return tu_image_create(device, pCreateInfo, pAllocator, pImage, modifier);
526 }
527
528 void
529 tu_DestroyImage(VkDevice _device,
530 VkImage _image,
531 const VkAllocationCallbacks *pAllocator)
532 {
533 TU_FROM_HANDLE(tu_device, device, _device);
534 TU_FROM_HANDLE(tu_image, image, _image);
535
536 if (!image)
537 return;
538
539 if (image->owned_memory != VK_NULL_HANDLE)
540 tu_FreeMemory(_device, image->owned_memory, pAllocator);
541
542 vk_free2(&device->alloc, pAllocator, image);
543 }
544
545 void
546 tu_GetImageSubresourceLayout(VkDevice _device,
547 VkImage _image,
548 const VkImageSubresource *pSubresource,
549 VkSubresourceLayout *pLayout)
550 {
551 TU_FROM_HANDLE(tu_image, image, _image);
552
553 const struct fdl_slice *slice = image->layout.slices + pSubresource->mipLevel;
554
555 pLayout->offset = fdl_surface_offset(&image->layout,
556 pSubresource->mipLevel,
557 pSubresource->arrayLayer);
558 pLayout->size = slice->size0;
559 pLayout->rowPitch =
560 slice->pitch * vk_format_get_blockheight(image->vk_format);
561 pLayout->arrayPitch = image->layout.layer_size;
562 pLayout->depthPitch = slice->size0;
563
564 if (image->layout.ubwc_layer_size) {
565 /* UBWC starts at offset 0 */
566 pLayout->offset = 0;
567 /* UBWC scanout won't match what the kernel wants if we have levels/layers */
568 assert(image->level_count == 1 && image->layer_count == 1);
569 }
570 }
571
572 VkResult tu_GetImageDrmFormatModifierPropertiesEXT(
573 VkDevice device,
574 VkImage _image,
575 VkImageDrmFormatModifierPropertiesEXT* pProperties)
576 {
577 TU_FROM_HANDLE(tu_image, image, _image);
578
579 assert(pProperties->sType ==
580 VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_PROPERTIES_EXT);
581
582 /* TODO invent a modifier for tiled but not UBWC buffers */
583
584 if (!image->layout.tile_mode)
585 pProperties->drmFormatModifier = DRM_FORMAT_MOD_LINEAR;
586 else if (image->layout.ubwc_layer_size)
587 pProperties->drmFormatModifier = DRM_FORMAT_MOD_QCOM_COMPRESSED;
588 else
589 pProperties->drmFormatModifier = DRM_FORMAT_MOD_INVALID;
590
591 return VK_SUCCESS;
592 }
593
594
595 VkResult
596 tu_CreateImageView(VkDevice _device,
597 const VkImageViewCreateInfo *pCreateInfo,
598 const VkAllocationCallbacks *pAllocator,
599 VkImageView *pView)
600 {
601 TU_FROM_HANDLE(tu_device, device, _device);
602 struct tu_image_view *view;
603
604 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
605 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
606 if (view == NULL)
607 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
608
609 tu_image_view_init(view, pCreateInfo);
610
611 *pView = tu_image_view_to_handle(view);
612
613 return VK_SUCCESS;
614 }
615
616 void
617 tu_DestroyImageView(VkDevice _device,
618 VkImageView _iview,
619 const VkAllocationCallbacks *pAllocator)
620 {
621 TU_FROM_HANDLE(tu_device, device, _device);
622 TU_FROM_HANDLE(tu_image_view, iview, _iview);
623
624 if (!iview)
625 return;
626 vk_free2(&device->alloc, pAllocator, iview);
627 }
628
629 void
630 tu_buffer_view_init(struct tu_buffer_view *view,
631 struct tu_device *device,
632 const VkBufferViewCreateInfo *pCreateInfo)
633 {
634 TU_FROM_HANDLE(tu_buffer, buffer, pCreateInfo->buffer);
635
636 view->buffer = buffer;
637
638 enum VkFormat vfmt = pCreateInfo->format;
639 enum pipe_format pfmt = vk_format_to_pipe_format(vfmt);
640 const struct tu_native_format fmt = tu6_format_texture(vfmt, TILE6_LINEAR);
641
642 uint32_t range;
643 if (pCreateInfo->range == VK_WHOLE_SIZE)
644 range = buffer->size - pCreateInfo->offset;
645 else
646 range = pCreateInfo->range;
647 uint32_t elements = range / util_format_get_blocksize(pfmt);
648
649 static const VkComponentMapping components = {
650 .r = VK_COMPONENT_SWIZZLE_R,
651 .g = VK_COMPONENT_SWIZZLE_G,
652 .b = VK_COMPONENT_SWIZZLE_B,
653 .a = VK_COMPONENT_SWIZZLE_A,
654 };
655
656 uint64_t iova = tu_buffer_iova(buffer) + pCreateInfo->offset;
657
658 memset(&view->descriptor, 0, sizeof(view->descriptor));
659
660 view->descriptor[0] =
661 A6XX_TEX_CONST_0_TILE_MODE(TILE6_LINEAR) |
662 A6XX_TEX_CONST_0_SWAP(fmt.swap) |
663 A6XX_TEX_CONST_0_FMT(fmt.fmt) |
664 A6XX_TEX_CONST_0_MIPLVLS(0) |
665 tu6_texswiz(&components, NULL, vfmt, VK_IMAGE_ASPECT_COLOR_BIT);
666 COND(vk_format_is_srgb(vfmt), A6XX_TEX_CONST_0_SRGB);
667 view->descriptor[1] =
668 A6XX_TEX_CONST_1_WIDTH(elements & MASK(15)) |
669 A6XX_TEX_CONST_1_HEIGHT(elements >> 15);
670 view->descriptor[2] =
671 A6XX_TEX_CONST_2_UNK4 |
672 A6XX_TEX_CONST_2_UNK31;
673 view->descriptor[4] = iova;
674 view->descriptor[5] = iova >> 32;
675 }
676
677 VkResult
678 tu_CreateBufferView(VkDevice _device,
679 const VkBufferViewCreateInfo *pCreateInfo,
680 const VkAllocationCallbacks *pAllocator,
681 VkBufferView *pView)
682 {
683 TU_FROM_HANDLE(tu_device, device, _device);
684 struct tu_buffer_view *view;
685
686 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
687 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
688 if (!view)
689 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
690
691 tu_buffer_view_init(view, device, pCreateInfo);
692
693 *pView = tu_buffer_view_to_handle(view);
694
695 return VK_SUCCESS;
696 }
697
698 void
699 tu_DestroyBufferView(VkDevice _device,
700 VkBufferView bufferView,
701 const VkAllocationCallbacks *pAllocator)
702 {
703 TU_FROM_HANDLE(tu_device, device, _device);
704 TU_FROM_HANDLE(tu_buffer_view, view, bufferView);
705
706 if (!view)
707 return;
708
709 vk_free2(&device->alloc, pAllocator, view);
710 }