freedreno/layout: add explicit offset/pitch argument to fdl6_layout
[mesa.git] / src / freedreno / vulkan / tu_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "util/debug.h"
31 #include "util/u_atomic.h"
32 #include "util/format/u_format.h"
33 #include "vk_format.h"
34 #include "vk_util.h"
35 #include "drm-uapi/drm_fourcc.h"
36
37 #include "tu_cs.h"
38
39 VkResult
40 tu_image_create(VkDevice _device,
41 const VkImageCreateInfo *pCreateInfo,
42 const VkAllocationCallbacks *alloc,
43 VkImage *pImage,
44 uint64_t modifier)
45 {
46 TU_FROM_HANDLE(tu_device, device, _device);
47 struct tu_image *image = NULL;
48 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
49
50 tu_assert(pCreateInfo->mipLevels > 0);
51 tu_assert(pCreateInfo->arrayLayers > 0);
52 tu_assert(pCreateInfo->samples > 0);
53 tu_assert(pCreateInfo->extent.width > 0);
54 tu_assert(pCreateInfo->extent.height > 0);
55 tu_assert(pCreateInfo->extent.depth > 0);
56
57 image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
58 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
59 if (!image)
60 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
61
62 image->type = pCreateInfo->imageType;
63
64 image->vk_format = pCreateInfo->format;
65 image->tiling = pCreateInfo->tiling;
66 image->usage = pCreateInfo->usage;
67 image->flags = pCreateInfo->flags;
68 image->extent = pCreateInfo->extent;
69 image->level_count = pCreateInfo->mipLevels;
70 image->layer_count = pCreateInfo->arrayLayers;
71 image->samples = pCreateInfo->samples;
72
73 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
74 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
75 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
76 if (pCreateInfo->pQueueFamilyIndices[i] ==
77 VK_QUEUE_FAMILY_EXTERNAL)
78 image->queue_family_mask |= (1u << TU_MAX_QUEUE_FAMILIES) - 1u;
79 else
80 image->queue_family_mask |=
81 1u << pCreateInfo->pQueueFamilyIndices[i];
82 }
83
84 image->shareable =
85 vk_find_struct_const(pCreateInfo->pNext,
86 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
87
88 image->layout.tile_mode = TILE6_3;
89 bool ubwc_enabled =
90 !(device->physical_device->instance->debug_flags & TU_DEBUG_NOUBWC);
91
92 /* disable tiling when linear is requested, for YUYV/UYVY, and for mutable
93 * images. Mutable images can be reinterpreted as any other compatible
94 * format, including swapped formats which aren't supported with tiling.
95 * This means that we have to fall back to linear almost always. However
96 * depth and stencil formats cannot be reintepreted as another format, and
97 * cannot be linear with sysmem rendering, so don't fall back for those.
98 *
99 * TODO: Be smarter and use usage bits and VK_KHR_image_format_list to
100 * enable tiling and/or UBWC when possible.
101 */
102 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR ||
103 modifier == DRM_FORMAT_MOD_LINEAR ||
104 vk_format_description(image->vk_format)->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED ||
105 (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT &&
106 !vk_format_is_depth_or_stencil(image->vk_format))) {
107 image->layout.tile_mode = TILE6_LINEAR;
108 ubwc_enabled = false;
109 }
110
111 /* don't use UBWC with compressed formats */
112 if (vk_format_is_compressed(image->vk_format))
113 ubwc_enabled = false;
114
115 /* UBWC can't be used with E5B9G9R9 */
116 if (image->vk_format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32)
117 ubwc_enabled = false;
118
119 /* separate stencil doesn't have a UBWC enable bit */
120 if (image->vk_format == VK_FORMAT_S8_UINT)
121 ubwc_enabled = false;
122
123 if (image->extent.depth > 1) {
124 tu_finishme("UBWC with 3D textures");
125 ubwc_enabled = false;
126 }
127
128 /* Disable UBWC for storage images.
129 *
130 * The closed GL driver skips UBWC for storage images (and additionally
131 * uses linear for writeonly images). We seem to have image tiling working
132 * in freedreno in general, so turnip matches that. freedreno also enables
133 * UBWC on images, but it's not really tested due to the lack of
134 * UBWC-enabled mipmaps in freedreno currently. Just match the closed GL
135 * behavior of no UBWC.
136 */
137 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
138 ubwc_enabled = false;
139
140 uint32_t ubwc_blockwidth, ubwc_blockheight;
141 fdl6_get_ubwc_blockwidth(&image->layout,
142 &ubwc_blockwidth, &ubwc_blockheight);
143 if (!ubwc_blockwidth) {
144 tu_finishme("UBWC for cpp=%d", image->layout.cpp);
145 ubwc_enabled = false;
146 }
147
148 /* expect UBWC enabled if we asked for it */
149 assert(modifier != DRM_FORMAT_MOD_QCOM_COMPRESSED || ubwc_enabled);
150
151 image->layout.ubwc = ubwc_enabled;
152
153 fdl6_layout(&image->layout, vk_format_to_pipe_format(image->vk_format),
154 image->samples,
155 pCreateInfo->extent.width,
156 pCreateInfo->extent.height,
157 pCreateInfo->extent.depth,
158 pCreateInfo->mipLevels,
159 pCreateInfo->arrayLayers,
160 pCreateInfo->imageType == VK_IMAGE_TYPE_3D,
161 NULL);
162
163 *pImage = tu_image_to_handle(image);
164
165 return VK_SUCCESS;
166 }
167
168 enum a6xx_tex_fetchsize
169 tu6_fetchsize(VkFormat format)
170 {
171 switch (vk_format_get_blocksize(format)) {
172 case 1: return TFETCH6_1_BYTE;
173 case 2: return TFETCH6_2_BYTE;
174 case 4: return TFETCH6_4_BYTE;
175 case 8: return TFETCH6_8_BYTE;
176 case 16: return TFETCH6_16_BYTE;
177 default:
178 unreachable("bad block size");
179 }
180 }
181
182 static void
183 compose_swizzle(unsigned char *swiz, const VkComponentMapping *mapping)
184 {
185 unsigned char src_swiz[4] = { swiz[0], swiz[1], swiz[2], swiz[3] };
186 VkComponentSwizzle vk_swiz[4] = {
187 mapping->r, mapping->g, mapping->b, mapping->a
188 };
189 for (int i = 0; i < 4; i++) {
190 switch (vk_swiz[i]) {
191 case VK_COMPONENT_SWIZZLE_IDENTITY:
192 swiz[i] = src_swiz[i];
193 break;
194 case VK_COMPONENT_SWIZZLE_R...VK_COMPONENT_SWIZZLE_A:
195 swiz[i] = src_swiz[vk_swiz[i] - VK_COMPONENT_SWIZZLE_R];
196 break;
197 case VK_COMPONENT_SWIZZLE_ZERO:
198 swiz[i] = A6XX_TEX_ZERO;
199 break;
200 case VK_COMPONENT_SWIZZLE_ONE:
201 swiz[i] = A6XX_TEX_ONE;
202 break;
203 default:
204 unreachable("unexpected swizzle");
205 }
206 }
207 }
208
209 static uint32_t
210 tu6_texswiz(const VkComponentMapping *comps,
211 const struct tu_sampler_ycbcr_conversion *conversion,
212 VkFormat format,
213 VkImageAspectFlagBits aspect_mask)
214 {
215 unsigned char swiz[4] = {
216 A6XX_TEX_X, A6XX_TEX_Y, A6XX_TEX_Z, A6XX_TEX_W,
217 };
218
219 switch (format) {
220 case VK_FORMAT_G8B8G8R8_422_UNORM:
221 case VK_FORMAT_B8G8R8G8_422_UNORM:
222 swiz[0] = A6XX_TEX_Z;
223 swiz[1] = A6XX_TEX_X;
224 swiz[2] = A6XX_TEX_Y;
225 break;
226 case VK_FORMAT_BC1_RGB_UNORM_BLOCK:
227 case VK_FORMAT_BC1_RGB_SRGB_BLOCK:
228 /* same hardware format is used for BC1_RGB / BC1_RGBA */
229 swiz[3] = A6XX_TEX_ONE;
230 break;
231 case VK_FORMAT_D24_UNORM_S8_UINT:
232 /* for D24S8, stencil is in the 2nd channel of the hardware format */
233 if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
234 swiz[0] = A6XX_TEX_Y;
235 swiz[1] = A6XX_TEX_ZERO;
236 }
237 default:
238 break;
239 }
240
241 compose_swizzle(swiz, comps);
242 if (conversion)
243 compose_swizzle(swiz, &conversion->components);
244
245 return A6XX_TEX_CONST_0_SWIZ_X(swiz[0]) |
246 A6XX_TEX_CONST_0_SWIZ_Y(swiz[1]) |
247 A6XX_TEX_CONST_0_SWIZ_Z(swiz[2]) |
248 A6XX_TEX_CONST_0_SWIZ_W(swiz[3]);
249 }
250
251 static enum a6xx_tex_type
252 tu6_tex_type(VkImageViewType type, bool storage)
253 {
254 switch (type) {
255 default:
256 case VK_IMAGE_VIEW_TYPE_1D:
257 case VK_IMAGE_VIEW_TYPE_1D_ARRAY:
258 return A6XX_TEX_1D;
259 case VK_IMAGE_VIEW_TYPE_2D:
260 case VK_IMAGE_VIEW_TYPE_2D_ARRAY:
261 return A6XX_TEX_2D;
262 case VK_IMAGE_VIEW_TYPE_3D:
263 return A6XX_TEX_3D;
264 case VK_IMAGE_VIEW_TYPE_CUBE:
265 case VK_IMAGE_VIEW_TYPE_CUBE_ARRAY:
266 return storage ? A6XX_TEX_2D : A6XX_TEX_CUBE;
267 }
268 }
269
270 void
271 tu_cs_image_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
272 {
273 tu_cs_emit(cs, iview->PITCH);
274 tu_cs_emit(cs, iview->layer_size >> 6);
275 tu_cs_emit_qw(cs, iview->base_addr + iview->layer_size * layer);
276 }
277
278 void
279 tu_cs_image_ref_2d(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer, bool src)
280 {
281 tu_cs_emit_qw(cs, iview->base_addr + iview->layer_size * layer);
282 /* SP_PS_2D_SRC_PITCH has shifted pitch field */
283 tu_cs_emit(cs, iview->PITCH << (src ? 9 : 0));
284 }
285
286 void
287 tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
288 {
289 tu_cs_emit_qw(cs, iview->ubwc_addr + iview->ubwc_layer_size * layer);
290 tu_cs_emit(cs, iview->FLAG_BUFFER_PITCH);
291 }
292
293 void
294 tu_image_view_init(struct tu_image_view *iview,
295 const VkImageViewCreateInfo *pCreateInfo)
296 {
297 TU_FROM_HANDLE(tu_image, image, pCreateInfo->image);
298 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
299 VkFormat format = pCreateInfo->format;
300 VkImageAspectFlagBits aspect_mask = pCreateInfo->subresourceRange.aspectMask;
301
302 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
303 vk_find_struct_const(pCreateInfo->pNext, SAMPLER_YCBCR_CONVERSION_INFO);
304 const struct tu_sampler_ycbcr_conversion *conversion = ycbcr_conversion ?
305 tu_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion) : NULL;
306
307 switch (image->type) {
308 case VK_IMAGE_TYPE_1D:
309 case VK_IMAGE_TYPE_2D:
310 assert(range->baseArrayLayer + tu_get_layerCount(image, range) <=
311 image->layer_count);
312 break;
313 case VK_IMAGE_TYPE_3D:
314 assert(range->baseArrayLayer + tu_get_layerCount(image, range) <=
315 tu_minify(image->extent.depth, range->baseMipLevel));
316 break;
317 default:
318 unreachable("bad VkImageType");
319 }
320
321 iview->image = image;
322
323 memset(iview->descriptor, 0, sizeof(iview->descriptor));
324
325 struct fdl_layout *layout = &image->layout;
326
327 uint32_t width = u_minify(image->extent.width, range->baseMipLevel);
328 uint32_t height = u_minify(image->extent.height, range->baseMipLevel);
329 uint32_t storage_depth = tu_get_layerCount(image, range);
330 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
331 storage_depth = u_minify(image->extent.depth, range->baseMipLevel);
332 }
333
334 uint32_t depth = storage_depth;
335 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE ||
336 pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) {
337 /* Cubes are treated as 2D arrays for storage images, so only divide the
338 * depth by 6 for the texture descriptor.
339 */
340 depth /= 6;
341 }
342
343 uint64_t base_addr = image->bo->iova + image->bo_offset +
344 fdl_surface_offset(layout, range->baseMipLevel, range->baseArrayLayer);
345 uint64_t ubwc_addr = image->bo->iova + image->bo_offset +
346 fdl_ubwc_offset(layout, range->baseMipLevel, range->baseArrayLayer);
347
348 uint32_t pitch = layout->slices[range->baseMipLevel].pitch;
349 uint32_t ubwc_pitch = layout->ubwc_slices[range->baseMipLevel].pitch;
350 uint32_t layer_size = fdl_layer_stride(layout, range->baseMipLevel);
351
352 struct tu_native_format fmt = tu6_format_texture(format, layout->tile_mode);
353 /* note: freedreno layout assumes no TILE_ALL bit for non-UBWC
354 * this means smaller mipmap levels have a linear tile mode
355 */
356 fmt.tile_mode = fdl_tile_mode(layout, range->baseMipLevel);
357
358 bool ubwc_enabled = fdl_ubwc_enabled(layout, range->baseMipLevel);
359
360 unsigned fmt_tex = fmt.fmt;
361 if (fmt_tex == FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8) {
362 if (aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT)
363 fmt_tex = FMT6_Z24_UNORM_S8_UINT;
364 if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
365 fmt_tex = FMT6_S8Z24_UINT;
366 /* TODO: also use this format with storage descriptor ? */
367 }
368
369 iview->descriptor[0] =
370 A6XX_TEX_CONST_0_TILE_MODE(fmt.tile_mode) |
371 COND(vk_format_is_srgb(format), A6XX_TEX_CONST_0_SRGB) |
372 A6XX_TEX_CONST_0_FMT(fmt_tex) |
373 A6XX_TEX_CONST_0_SAMPLES(tu_msaa_samples(image->samples)) |
374 A6XX_TEX_CONST_0_SWAP(fmt.swap) |
375 tu6_texswiz(&pCreateInfo->components, conversion, format, aspect_mask) |
376 A6XX_TEX_CONST_0_MIPLVLS(tu_get_levelCount(image, range) - 1);
377 iview->descriptor[1] = A6XX_TEX_CONST_1_WIDTH(width) | A6XX_TEX_CONST_1_HEIGHT(height);
378 iview->descriptor[2] =
379 A6XX_TEX_CONST_2_FETCHSIZE(tu6_fetchsize(format)) |
380 A6XX_TEX_CONST_2_PITCH(pitch) |
381 A6XX_TEX_CONST_2_TYPE(tu6_tex_type(pCreateInfo->viewType, false));
382 iview->descriptor[3] = A6XX_TEX_CONST_3_ARRAY_PITCH(layer_size);
383 iview->descriptor[4] = base_addr;
384 iview->descriptor[5] = (base_addr >> 32) | A6XX_TEX_CONST_5_DEPTH(depth);
385
386 if (ubwc_enabled) {
387 uint32_t block_width, block_height;
388 fdl6_get_ubwc_blockwidth(&image->layout,
389 &block_width, &block_height);
390
391 iview->descriptor[3] |= A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_TILE_ALL;
392 iview->descriptor[7] = ubwc_addr;
393 iview->descriptor[8] = ubwc_addr >> 32;
394 iview->descriptor[9] |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(layout->ubwc_layer_size >> 2);
395 iview->descriptor[10] |=
396 A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(ubwc_pitch) |
397 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(util_logbase2_ceil(DIV_ROUND_UP(width, block_width))) |
398 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(util_logbase2_ceil(DIV_ROUND_UP(height, block_height)));
399 }
400
401 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
402 iview->descriptor[3] |=
403 A6XX_TEX_CONST_3_MIN_LAYERSZ(image->layout.slices[image->level_count - 1].size0);
404 }
405
406 iview->SP_PS_2D_SRC_INFO = A6XX_SP_PS_2D_SRC_INFO(
407 .color_format = fmt.fmt,
408 .tile_mode = fmt.tile_mode,
409 .color_swap = fmt.swap,
410 .flags = ubwc_enabled,
411 .srgb = vk_format_is_srgb(format),
412 .samples = tu_msaa_samples(image->samples),
413 .samples_average = image->samples > 1 &&
414 !vk_format_is_int(format) &&
415 !vk_format_is_depth_or_stencil(format),
416 .unk20 = 1,
417 .unk22 = 1).value;
418 iview->SP_PS_2D_SRC_SIZE =
419 A6XX_SP_PS_2D_SRC_SIZE(.width = width, .height = height).value;
420
421 /* note: these have same encoding for MRT and 2D (except 2D PITCH src) */
422 iview->PITCH = A6XX_RB_DEPTH_BUFFER_PITCH(pitch).value;
423 iview->FLAG_BUFFER_PITCH = A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(
424 .pitch = ubwc_pitch, .array_pitch = layout->ubwc_layer_size >> 2).value;
425
426 iview->base_addr = base_addr;
427 iview->ubwc_addr = ubwc_addr;
428 iview->layer_size = layer_size;
429 iview->ubwc_layer_size = layout->ubwc_layer_size;
430
431 /* Don't set fields that are only used for attachments/blit dest if COLOR
432 * is unsupported.
433 */
434 if (!(fmt.supported & FMT_COLOR))
435 return;
436
437 struct tu_native_format cfmt = tu6_format_color(format, layout->tile_mode);
438 cfmt.tile_mode = fmt.tile_mode;
439
440 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT) {
441 memset(iview->storage_descriptor, 0, sizeof(iview->storage_descriptor));
442
443 iview->storage_descriptor[0] =
444 A6XX_IBO_0_FMT(fmt.fmt) |
445 A6XX_IBO_0_TILE_MODE(fmt.tile_mode);
446 iview->storage_descriptor[1] =
447 A6XX_IBO_1_WIDTH(width) |
448 A6XX_IBO_1_HEIGHT(height);
449 iview->storage_descriptor[2] =
450 A6XX_IBO_2_PITCH(pitch) |
451 A6XX_IBO_2_TYPE(tu6_tex_type(pCreateInfo->viewType, true));
452 iview->storage_descriptor[3] = A6XX_IBO_3_ARRAY_PITCH(layer_size);
453
454 iview->storage_descriptor[4] = base_addr;
455 iview->storage_descriptor[5] = (base_addr >> 32) | A6XX_IBO_5_DEPTH(storage_depth);
456
457 if (ubwc_enabled) {
458 iview->storage_descriptor[3] |= A6XX_IBO_3_FLAG | A6XX_IBO_3_UNK27;
459 iview->storage_descriptor[7] |= ubwc_addr;
460 iview->storage_descriptor[8] |= ubwc_addr >> 32;
461 iview->storage_descriptor[9] = A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(layout->ubwc_layer_size >> 2);
462 iview->storage_descriptor[10] =
463 A6XX_IBO_10_FLAG_BUFFER_PITCH(ubwc_pitch);
464 }
465 }
466
467 iview->extent.width = width;
468 iview->extent.height = height;
469 iview->need_y2_align =
470 (fmt.tile_mode == TILE6_LINEAR && range->baseMipLevel != image->level_count - 1);
471
472 iview->ubwc_enabled = ubwc_enabled;
473
474 iview->RB_MRT_BUF_INFO = A6XX_RB_MRT_BUF_INFO(0,
475 .color_tile_mode = cfmt.tile_mode,
476 .color_format = cfmt.fmt,
477 .color_swap = cfmt.swap).value;
478 iview->SP_FS_MRT_REG = A6XX_SP_FS_MRT_REG(0,
479 .color_format = cfmt.fmt,
480 .color_sint = vk_format_is_sint(format),
481 .color_uint = vk_format_is_uint(format)).value;
482
483 iview->RB_2D_DST_INFO = A6XX_RB_2D_DST_INFO(
484 .color_format = cfmt.fmt,
485 .tile_mode = cfmt.tile_mode,
486 .color_swap = cfmt.swap,
487 .flags = ubwc_enabled,
488 .srgb = vk_format_is_srgb(format)).value;
489
490 iview->RB_BLIT_DST_INFO = A6XX_RB_BLIT_DST_INFO(
491 .tile_mode = cfmt.tile_mode,
492 .samples = tu_msaa_samples(iview->image->samples),
493 .color_format = cfmt.fmt,
494 .color_swap = cfmt.swap,
495 .flags = ubwc_enabled).value;
496 }
497
498 unsigned
499 tu_image_queue_family_mask(const struct tu_image *image,
500 uint32_t family,
501 uint32_t queue_family)
502 {
503 if (!image->exclusive)
504 return image->queue_family_mask;
505 if (family == VK_QUEUE_FAMILY_EXTERNAL)
506 return (1u << TU_MAX_QUEUE_FAMILIES) - 1u;
507 if (family == VK_QUEUE_FAMILY_IGNORED)
508 return 1u << queue_family;
509 return 1u << family;
510 }
511
512 VkResult
513 tu_CreateImage(VkDevice device,
514 const VkImageCreateInfo *pCreateInfo,
515 const VkAllocationCallbacks *pAllocator,
516 VkImage *pImage)
517 {
518 #ifdef ANDROID
519 const VkNativeBufferANDROID *gralloc_info =
520 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
521
522 if (gralloc_info)
523 return tu_image_from_gralloc(device, pCreateInfo, gralloc_info,
524 pAllocator, pImage);
525 #endif
526
527 uint64_t modifier = DRM_FORMAT_MOD_INVALID;
528 if (pCreateInfo->tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) {
529 const VkImageDrmFormatModifierListCreateInfoEXT *mod_info =
530 vk_find_struct_const(pCreateInfo->pNext,
531 IMAGE_DRM_FORMAT_MODIFIER_LIST_CREATE_INFO_EXT);
532
533 modifier = DRM_FORMAT_MOD_LINEAR;
534 for (unsigned i = 0; i < mod_info->drmFormatModifierCount; i++) {
535 if (mod_info->pDrmFormatModifiers[i] == DRM_FORMAT_MOD_QCOM_COMPRESSED)
536 modifier = DRM_FORMAT_MOD_QCOM_COMPRESSED;
537 }
538 } else {
539 const struct wsi_image_create_info *wsi_info =
540 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
541 if (wsi_info && wsi_info->scanout)
542 modifier = DRM_FORMAT_MOD_LINEAR;
543 }
544
545 return tu_image_create(device, pCreateInfo, pAllocator, pImage, modifier);
546 }
547
548 void
549 tu_DestroyImage(VkDevice _device,
550 VkImage _image,
551 const VkAllocationCallbacks *pAllocator)
552 {
553 TU_FROM_HANDLE(tu_device, device, _device);
554 TU_FROM_HANDLE(tu_image, image, _image);
555
556 if (!image)
557 return;
558
559 if (image->owned_memory != VK_NULL_HANDLE)
560 tu_FreeMemory(_device, image->owned_memory, pAllocator);
561
562 vk_free2(&device->alloc, pAllocator, image);
563 }
564
565 void
566 tu_GetImageSubresourceLayout(VkDevice _device,
567 VkImage _image,
568 const VkImageSubresource *pSubresource,
569 VkSubresourceLayout *pLayout)
570 {
571 TU_FROM_HANDLE(tu_image, image, _image);
572
573 const struct fdl_slice *slice = image->layout.slices + pSubresource->mipLevel;
574
575 pLayout->offset = fdl_surface_offset(&image->layout,
576 pSubresource->mipLevel,
577 pSubresource->arrayLayer);
578 pLayout->size = slice->size0;
579 pLayout->rowPitch = slice->pitch;
580 pLayout->arrayPitch = image->layout.layer_size;
581 pLayout->depthPitch = slice->size0;
582
583 if (image->layout.ubwc_layer_size) {
584 /* UBWC starts at offset 0 */
585 pLayout->offset = 0;
586 /* UBWC scanout won't match what the kernel wants if we have levels/layers */
587 assert(image->level_count == 1 && image->layer_count == 1);
588 }
589 }
590
591 VkResult tu_GetImageDrmFormatModifierPropertiesEXT(
592 VkDevice device,
593 VkImage _image,
594 VkImageDrmFormatModifierPropertiesEXT* pProperties)
595 {
596 TU_FROM_HANDLE(tu_image, image, _image);
597
598 assert(pProperties->sType ==
599 VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_PROPERTIES_EXT);
600
601 /* TODO invent a modifier for tiled but not UBWC buffers */
602
603 if (!image->layout.tile_mode)
604 pProperties->drmFormatModifier = DRM_FORMAT_MOD_LINEAR;
605 else if (image->layout.ubwc_layer_size)
606 pProperties->drmFormatModifier = DRM_FORMAT_MOD_QCOM_COMPRESSED;
607 else
608 pProperties->drmFormatModifier = DRM_FORMAT_MOD_INVALID;
609
610 return VK_SUCCESS;
611 }
612
613
614 VkResult
615 tu_CreateImageView(VkDevice _device,
616 const VkImageViewCreateInfo *pCreateInfo,
617 const VkAllocationCallbacks *pAllocator,
618 VkImageView *pView)
619 {
620 TU_FROM_HANDLE(tu_device, device, _device);
621 struct tu_image_view *view;
622
623 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
624 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
625 if (view == NULL)
626 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
627
628 tu_image_view_init(view, pCreateInfo);
629
630 *pView = tu_image_view_to_handle(view);
631
632 return VK_SUCCESS;
633 }
634
635 void
636 tu_DestroyImageView(VkDevice _device,
637 VkImageView _iview,
638 const VkAllocationCallbacks *pAllocator)
639 {
640 TU_FROM_HANDLE(tu_device, device, _device);
641 TU_FROM_HANDLE(tu_image_view, iview, _iview);
642
643 if (!iview)
644 return;
645 vk_free2(&device->alloc, pAllocator, iview);
646 }
647
648 void
649 tu_buffer_view_init(struct tu_buffer_view *view,
650 struct tu_device *device,
651 const VkBufferViewCreateInfo *pCreateInfo)
652 {
653 TU_FROM_HANDLE(tu_buffer, buffer, pCreateInfo->buffer);
654
655 view->buffer = buffer;
656
657 enum VkFormat vfmt = pCreateInfo->format;
658 enum pipe_format pfmt = vk_format_to_pipe_format(vfmt);
659 const struct tu_native_format fmt = tu6_format_texture(vfmt, TILE6_LINEAR);
660
661 uint32_t range;
662 if (pCreateInfo->range == VK_WHOLE_SIZE)
663 range = buffer->size - pCreateInfo->offset;
664 else
665 range = pCreateInfo->range;
666 uint32_t elements = range / util_format_get_blocksize(pfmt);
667
668 static const VkComponentMapping components = {
669 .r = VK_COMPONENT_SWIZZLE_R,
670 .g = VK_COMPONENT_SWIZZLE_G,
671 .b = VK_COMPONENT_SWIZZLE_B,
672 .a = VK_COMPONENT_SWIZZLE_A,
673 };
674
675 uint64_t iova = tu_buffer_iova(buffer) + pCreateInfo->offset;
676
677 memset(&view->descriptor, 0, sizeof(view->descriptor));
678
679 view->descriptor[0] =
680 A6XX_TEX_CONST_0_TILE_MODE(TILE6_LINEAR) |
681 A6XX_TEX_CONST_0_SWAP(fmt.swap) |
682 A6XX_TEX_CONST_0_FMT(fmt.fmt) |
683 A6XX_TEX_CONST_0_MIPLVLS(0) |
684 tu6_texswiz(&components, NULL, vfmt, VK_IMAGE_ASPECT_COLOR_BIT);
685 COND(vk_format_is_srgb(vfmt), A6XX_TEX_CONST_0_SRGB);
686 view->descriptor[1] =
687 A6XX_TEX_CONST_1_WIDTH(elements & MASK(15)) |
688 A6XX_TEX_CONST_1_HEIGHT(elements >> 15);
689 view->descriptor[2] =
690 A6XX_TEX_CONST_2_UNK4 |
691 A6XX_TEX_CONST_2_UNK31;
692 view->descriptor[4] = iova;
693 view->descriptor[5] = iova >> 32;
694 }
695
696 VkResult
697 tu_CreateBufferView(VkDevice _device,
698 const VkBufferViewCreateInfo *pCreateInfo,
699 const VkAllocationCallbacks *pAllocator,
700 VkBufferView *pView)
701 {
702 TU_FROM_HANDLE(tu_device, device, _device);
703 struct tu_buffer_view *view;
704
705 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
706 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
707 if (!view)
708 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
709
710 tu_buffer_view_init(view, device, pCreateInfo);
711
712 *pView = tu_buffer_view_to_handle(view);
713
714 return VK_SUCCESS;
715 }
716
717 void
718 tu_DestroyBufferView(VkDevice _device,
719 VkBufferView bufferView,
720 const VkAllocationCallbacks *pAllocator)
721 {
722 TU_FROM_HANDLE(tu_device, device, _device);
723 TU_FROM_HANDLE(tu_buffer_view, view, bufferView);
724
725 if (!view)
726 return;
727
728 vk_free2(&device->alloc, pAllocator, view);
729 }