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4b062b8bfa6305b854d825d8aee0a5a783c8ee22
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 /* Emit IB that preloads the descriptors that the shader uses */
44
45 static inline uint32_t
46 tu6_vkstage2opcode(VkShaderStageFlags stage)
47 {
48 switch (stage) {
49 case VK_SHADER_STAGE_VERTEX_BIT:
50 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
51 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
52 case VK_SHADER_STAGE_GEOMETRY_BIT:
53 return CP_LOAD_STATE6_GEOM;
54 case VK_SHADER_STAGE_FRAGMENT_BIT:
55 case VK_SHADER_STAGE_COMPUTE_BIT:
56 return CP_LOAD_STATE6_FRAG;
57 default:
58 unreachable("bad shader type");
59 }
60 }
61
62 static enum a6xx_state_block
63 tu6_tex_stage2sb(VkShaderStageFlags stage)
64 {
65 switch (stage) {
66 case VK_SHADER_STAGE_VERTEX_BIT:
67 return SB6_VS_TEX;
68 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
69 return SB6_HS_TEX;
70 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
71 return SB6_DS_TEX;
72 case VK_SHADER_STAGE_GEOMETRY_BIT:
73 return SB6_GS_TEX;
74 case VK_SHADER_STAGE_FRAGMENT_BIT:
75 return SB6_FS_TEX;
76 case VK_SHADER_STAGE_COMPUTE_BIT:
77 return SB6_CS_TEX;
78 default:
79 unreachable("bad shader stage");
80 }
81 }
82
83 static enum a6xx_state_block
84 tu6_ubo_stage2sb(VkShaderStageFlags stage)
85 {
86 switch (stage) {
87 case VK_SHADER_STAGE_VERTEX_BIT:
88 return SB6_VS_SHADER;
89 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
90 return SB6_HS_SHADER;
91 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
92 return SB6_DS_SHADER;
93 case VK_SHADER_STAGE_GEOMETRY_BIT:
94 return SB6_GS_SHADER;
95 case VK_SHADER_STAGE_FRAGMENT_BIT:
96 return SB6_FS_SHADER;
97 case VK_SHADER_STAGE_COMPUTE_BIT:
98 return SB6_CS_SHADER;
99 default:
100 unreachable("bad shader stage");
101 }
102 }
103
104 static void
105 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
106 enum a6xx_state_block sb, unsigned base, unsigned offset,
107 unsigned count)
108 {
109 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
110 * clear if emitting more packets will even help anything. Presumably the
111 * descriptor cache is relatively small, and these packets stop doing
112 * anything when there are too many descriptors.
113 */
114 tu_cs_emit_pkt7(cs, opcode, 3);
115 tu_cs_emit(cs,
116 CP_LOAD_STATE6_0_STATE_TYPE(st) |
117 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
118 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
119 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
120 tu_cs_emit_qw(cs, offset | (base << 28));
121 }
122
123 static unsigned
124 tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
125 {
126 const unsigned load_state_size = 4;
127 unsigned size = 0;
128 for (unsigned i = 0; i < layout->num_sets; i++) {
129 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
130 for (unsigned j = 0; j < set_layout->binding_count; j++) {
131 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
132 unsigned count = 0;
133 /* Note: some users, like amber for example, pass in
134 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
135 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
136 */
137 VkShaderStageFlags stages = compute ?
138 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
139 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
140 unsigned stage_count = util_bitcount(stages);
141 switch (binding->type) {
142 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
143 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
144 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
145 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
146 /* IBO-backed resources only need one packet for all graphics stages */
147 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
148 count += 1;
149 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
150 count += 1;
151 break;
152 case VK_DESCRIPTOR_TYPE_SAMPLER:
153 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
154 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
155 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
156 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
157 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
158 /* Textures and UBO's needs a packet for each stage */
159 count = stage_count;
160 break;
161 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
162 /* Because of how we pack combined images and samplers, we
163 * currently can't use one packet for the whole array.
164 */
165 count = stage_count * binding->array_size * 2;
166 break;
167 default:
168 unreachable("bad descriptor type");
169 }
170 size += count * load_state_size;
171 }
172 }
173 return size;
174 }
175
176 static void
177 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
178 {
179 unsigned size = tu6_load_state_size(pipeline->layout, compute);
180 if (size == 0)
181 return;
182
183 struct tu_cs cs;
184 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
185
186 struct tu_pipeline_layout *layout = pipeline->layout;
187 for (unsigned i = 0; i < layout->num_sets; i++) {
188 /* From 13.2.7. Descriptor Set Binding:
189 *
190 * A compatible descriptor set must be bound for all set numbers that
191 * any shaders in a pipeline access, at the time that a draw or
192 * dispatch command is recorded to execute using that pipeline.
193 * However, if none of the shaders in a pipeline statically use any
194 * bindings with a particular set number, then no descriptor set need
195 * be bound for that set number, even if the pipeline layout includes
196 * a non-trivial descriptor set layout for that set number.
197 *
198 * This means that descriptor sets unused by the pipeline may have a
199 * garbage or 0 BINDLESS_BASE register, which will cause context faults
200 * when prefetching descriptors from these sets. Skip prefetching for
201 * descriptors from them to avoid this. This is also an optimization,
202 * since these prefetches would be useless.
203 */
204 if (!(pipeline->active_desc_sets & (1u << i)))
205 continue;
206
207 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
208 for (unsigned j = 0; j < set_layout->binding_count; j++) {
209 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
210 unsigned base = i;
211 unsigned offset = binding->offset / 4;
212 /* Note: some users, like amber for example, pass in
213 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
214 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
215 */
216 VkShaderStageFlags stages = compute ?
217 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
218 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
219 unsigned count = binding->array_size;
220 if (count == 0 || stages == 0)
221 continue;
222 switch (binding->type) {
223 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
224 base = MAX_SETS;
225 offset = (layout->input_attachment_count +
226 layout->set[i].dynamic_offset_start +
227 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
228 /* fallthrough */
229 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
230 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
231 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
232 /* IBO-backed resources only need one packet for all graphics stages */
233 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
234 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
235 base, offset, count);
236 }
237 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
238 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
239 base, offset, count);
240 }
241 break;
242 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
243 base = MAX_SETS;
244 offset = (layout->set[i].input_attachment_start +
245 binding->input_attachment_offset) * A6XX_TEX_CONST_DWORDS;
246 case VK_DESCRIPTOR_TYPE_SAMPLER:
247 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
248 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
249 unsigned stage_log2;
250 for_each_bit(stage_log2, stages) {
251 VkShaderStageFlags stage = 1 << stage_log2;
252 emit_load_state(&cs, tu6_vkstage2opcode(stage),
253 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
254 ST6_SHADER : ST6_CONSTANTS,
255 tu6_tex_stage2sb(stage), base, offset, count);
256 }
257 break;
258 }
259 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
260 base = MAX_SETS;
261 offset = (layout->input_attachment_count +
262 layout->set[i].dynamic_offset_start +
263 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
264 /* fallthrough */
265 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
266 unsigned stage_log2;
267 for_each_bit(stage_log2, stages) {
268 VkShaderStageFlags stage = 1 << stage_log2;
269 emit_load_state(&cs, tu6_vkstage2opcode(stage), ST6_UBO,
270 tu6_ubo_stage2sb(stage), base, offset, count);
271 }
272 break;
273 }
274 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
275 unsigned stage_log2;
276 for_each_bit(stage_log2, stages) {
277 VkShaderStageFlags stage = 1 << stage_log2;
278 /* TODO: We could emit less CP_LOAD_STATE6 if we used
279 * struct-of-arrays instead of array-of-structs.
280 */
281 for (unsigned i = 0; i < count; i++) {
282 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
283 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
284 emit_load_state(&cs, tu6_vkstage2opcode(stage),
285 ST6_CONSTANTS, tu6_tex_stage2sb(stage),
286 base, tex_offset, 1);
287 emit_load_state(&cs, tu6_vkstage2opcode(stage),
288 ST6_SHADER, tu6_tex_stage2sb(stage),
289 base, sam_offset, 1);
290 }
291 }
292 break;
293 }
294 default:
295 unreachable("bad descriptor type");
296 }
297 }
298 }
299
300 pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
301 }
302
303 struct tu_pipeline_builder
304 {
305 struct tu_device *device;
306 struct tu_pipeline_cache *cache;
307 struct tu_pipeline_layout *layout;
308 const VkAllocationCallbacks *alloc;
309 const VkGraphicsPipelineCreateInfo *create_info;
310
311 struct tu_shader *shaders[MESA_SHADER_STAGES];
312 uint32_t shader_offsets[MESA_SHADER_STAGES];
313 uint32_t binning_vs_offset;
314 uint32_t shader_total_size;
315
316 bool rasterizer_discard;
317 /* these states are affectd by rasterizer_discard */
318 VkSampleCountFlagBits samples;
319 bool use_color_attachments;
320 bool use_dual_src_blend;
321 uint32_t color_attachment_count;
322 VkFormat color_attachment_formats[MAX_RTS];
323 VkFormat depth_attachment_format;
324 uint32_t render_components;
325 };
326
327 static enum tu_dynamic_state_bits
328 tu_dynamic_state_bit(VkDynamicState state)
329 {
330 switch (state) {
331 case VK_DYNAMIC_STATE_VIEWPORT:
332 return TU_DYNAMIC_VIEWPORT;
333 case VK_DYNAMIC_STATE_SCISSOR:
334 return TU_DYNAMIC_SCISSOR;
335 case VK_DYNAMIC_STATE_LINE_WIDTH:
336 return TU_DYNAMIC_LINE_WIDTH;
337 case VK_DYNAMIC_STATE_DEPTH_BIAS:
338 return TU_DYNAMIC_DEPTH_BIAS;
339 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
340 return TU_DYNAMIC_BLEND_CONSTANTS;
341 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
342 return TU_DYNAMIC_DEPTH_BOUNDS;
343 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
344 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
345 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
346 return TU_DYNAMIC_STENCIL_WRITE_MASK;
347 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
348 return TU_DYNAMIC_STENCIL_REFERENCE;
349 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
350 return TU_DYNAMIC_SAMPLE_LOCATIONS;
351 default:
352 unreachable("invalid dynamic state");
353 return 0;
354 }
355 }
356
357 static gl_shader_stage
358 tu_shader_stage(VkShaderStageFlagBits stage)
359 {
360 switch (stage) {
361 case VK_SHADER_STAGE_VERTEX_BIT:
362 return MESA_SHADER_VERTEX;
363 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
364 return MESA_SHADER_TESS_CTRL;
365 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
366 return MESA_SHADER_TESS_EVAL;
367 case VK_SHADER_STAGE_GEOMETRY_BIT:
368 return MESA_SHADER_GEOMETRY;
369 case VK_SHADER_STAGE_FRAGMENT_BIT:
370 return MESA_SHADER_FRAGMENT;
371 case VK_SHADER_STAGE_COMPUTE_BIT:
372 return MESA_SHADER_COMPUTE;
373 default:
374 unreachable("invalid VkShaderStageFlagBits");
375 return MESA_SHADER_NONE;
376 }
377 }
378
379 static bool
380 tu_logic_op_reads_dst(VkLogicOp op)
381 {
382 switch (op) {
383 case VK_LOGIC_OP_CLEAR:
384 case VK_LOGIC_OP_COPY:
385 case VK_LOGIC_OP_COPY_INVERTED:
386 case VK_LOGIC_OP_SET:
387 return false;
388 default:
389 return true;
390 }
391 }
392
393 static VkBlendFactor
394 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
395 {
396 /* treat dst alpha as 1.0 and avoid reading it */
397 switch (factor) {
398 case VK_BLEND_FACTOR_DST_ALPHA:
399 return VK_BLEND_FACTOR_ONE;
400 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
401 return VK_BLEND_FACTOR_ZERO;
402 default:
403 return factor;
404 }
405 }
406
407 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor)
408 {
409 switch (factor) {
410 case VK_BLEND_FACTOR_SRC1_COLOR:
411 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
412 case VK_BLEND_FACTOR_SRC1_ALPHA:
413 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
414 return true;
415 default:
416 return false;
417 }
418 }
419
420 static bool
421 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo *info)
422 {
423 if (!info)
424 return false;
425
426 for (unsigned i = 0; i < info->attachmentCount; i++) {
427 const VkPipelineColorBlendAttachmentState *blend = &info->pAttachments[i];
428 if (tu_blend_factor_is_dual_src(blend->srcColorBlendFactor) ||
429 tu_blend_factor_is_dual_src(blend->dstColorBlendFactor) ||
430 tu_blend_factor_is_dual_src(blend->srcAlphaBlendFactor) ||
431 tu_blend_factor_is_dual_src(blend->dstAlphaBlendFactor))
432 return true;
433 }
434
435 return false;
436 }
437
438 static enum pc_di_primtype
439 tu6_primtype(VkPrimitiveTopology topology)
440 {
441 switch (topology) {
442 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
443 return DI_PT_POINTLIST;
444 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
445 return DI_PT_LINELIST;
446 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
447 return DI_PT_LINESTRIP;
448 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
449 return DI_PT_TRILIST;
450 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
451 return DI_PT_TRISTRIP;
452 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
453 return DI_PT_TRIFAN;
454 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
455 return DI_PT_LINE_ADJ;
456 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
457 return DI_PT_LINESTRIP_ADJ;
458 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
459 return DI_PT_TRI_ADJ;
460 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
461 return DI_PT_TRISTRIP_ADJ;
462 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
463 default:
464 unreachable("invalid primitive topology");
465 return DI_PT_NONE;
466 }
467 }
468
469 static enum adreno_compare_func
470 tu6_compare_func(VkCompareOp op)
471 {
472 switch (op) {
473 case VK_COMPARE_OP_NEVER:
474 return FUNC_NEVER;
475 case VK_COMPARE_OP_LESS:
476 return FUNC_LESS;
477 case VK_COMPARE_OP_EQUAL:
478 return FUNC_EQUAL;
479 case VK_COMPARE_OP_LESS_OR_EQUAL:
480 return FUNC_LEQUAL;
481 case VK_COMPARE_OP_GREATER:
482 return FUNC_GREATER;
483 case VK_COMPARE_OP_NOT_EQUAL:
484 return FUNC_NOTEQUAL;
485 case VK_COMPARE_OP_GREATER_OR_EQUAL:
486 return FUNC_GEQUAL;
487 case VK_COMPARE_OP_ALWAYS:
488 return FUNC_ALWAYS;
489 default:
490 unreachable("invalid VkCompareOp");
491 return FUNC_NEVER;
492 }
493 }
494
495 static enum adreno_stencil_op
496 tu6_stencil_op(VkStencilOp op)
497 {
498 switch (op) {
499 case VK_STENCIL_OP_KEEP:
500 return STENCIL_KEEP;
501 case VK_STENCIL_OP_ZERO:
502 return STENCIL_ZERO;
503 case VK_STENCIL_OP_REPLACE:
504 return STENCIL_REPLACE;
505 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
506 return STENCIL_INCR_CLAMP;
507 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
508 return STENCIL_DECR_CLAMP;
509 case VK_STENCIL_OP_INVERT:
510 return STENCIL_INVERT;
511 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
512 return STENCIL_INCR_WRAP;
513 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
514 return STENCIL_DECR_WRAP;
515 default:
516 unreachable("invalid VkStencilOp");
517 return STENCIL_KEEP;
518 }
519 }
520
521 static enum a3xx_rop_code
522 tu6_rop(VkLogicOp op)
523 {
524 switch (op) {
525 case VK_LOGIC_OP_CLEAR:
526 return ROP_CLEAR;
527 case VK_LOGIC_OP_AND:
528 return ROP_AND;
529 case VK_LOGIC_OP_AND_REVERSE:
530 return ROP_AND_REVERSE;
531 case VK_LOGIC_OP_COPY:
532 return ROP_COPY;
533 case VK_LOGIC_OP_AND_INVERTED:
534 return ROP_AND_INVERTED;
535 case VK_LOGIC_OP_NO_OP:
536 return ROP_NOOP;
537 case VK_LOGIC_OP_XOR:
538 return ROP_XOR;
539 case VK_LOGIC_OP_OR:
540 return ROP_OR;
541 case VK_LOGIC_OP_NOR:
542 return ROP_NOR;
543 case VK_LOGIC_OP_EQUIVALENT:
544 return ROP_EQUIV;
545 case VK_LOGIC_OP_INVERT:
546 return ROP_INVERT;
547 case VK_LOGIC_OP_OR_REVERSE:
548 return ROP_OR_REVERSE;
549 case VK_LOGIC_OP_COPY_INVERTED:
550 return ROP_COPY_INVERTED;
551 case VK_LOGIC_OP_OR_INVERTED:
552 return ROP_OR_INVERTED;
553 case VK_LOGIC_OP_NAND:
554 return ROP_NAND;
555 case VK_LOGIC_OP_SET:
556 return ROP_SET;
557 default:
558 unreachable("invalid VkLogicOp");
559 return ROP_NOOP;
560 }
561 }
562
563 static enum adreno_rb_blend_factor
564 tu6_blend_factor(VkBlendFactor factor)
565 {
566 switch (factor) {
567 case VK_BLEND_FACTOR_ZERO:
568 return FACTOR_ZERO;
569 case VK_BLEND_FACTOR_ONE:
570 return FACTOR_ONE;
571 case VK_BLEND_FACTOR_SRC_COLOR:
572 return FACTOR_SRC_COLOR;
573 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
574 return FACTOR_ONE_MINUS_SRC_COLOR;
575 case VK_BLEND_FACTOR_DST_COLOR:
576 return FACTOR_DST_COLOR;
577 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
578 return FACTOR_ONE_MINUS_DST_COLOR;
579 case VK_BLEND_FACTOR_SRC_ALPHA:
580 return FACTOR_SRC_ALPHA;
581 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
582 return FACTOR_ONE_MINUS_SRC_ALPHA;
583 case VK_BLEND_FACTOR_DST_ALPHA:
584 return FACTOR_DST_ALPHA;
585 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
586 return FACTOR_ONE_MINUS_DST_ALPHA;
587 case VK_BLEND_FACTOR_CONSTANT_COLOR:
588 return FACTOR_CONSTANT_COLOR;
589 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
590 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
591 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
592 return FACTOR_CONSTANT_ALPHA;
593 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
594 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
595 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
596 return FACTOR_SRC_ALPHA_SATURATE;
597 case VK_BLEND_FACTOR_SRC1_COLOR:
598 return FACTOR_SRC1_COLOR;
599 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
600 return FACTOR_ONE_MINUS_SRC1_COLOR;
601 case VK_BLEND_FACTOR_SRC1_ALPHA:
602 return FACTOR_SRC1_ALPHA;
603 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
604 return FACTOR_ONE_MINUS_SRC1_ALPHA;
605 default:
606 unreachable("invalid VkBlendFactor");
607 return FACTOR_ZERO;
608 }
609 }
610
611 static enum a3xx_rb_blend_opcode
612 tu6_blend_op(VkBlendOp op)
613 {
614 switch (op) {
615 case VK_BLEND_OP_ADD:
616 return BLEND_DST_PLUS_SRC;
617 case VK_BLEND_OP_SUBTRACT:
618 return BLEND_SRC_MINUS_DST;
619 case VK_BLEND_OP_REVERSE_SUBTRACT:
620 return BLEND_DST_MINUS_SRC;
621 case VK_BLEND_OP_MIN:
622 return BLEND_MIN_DST_SRC;
623 case VK_BLEND_OP_MAX:
624 return BLEND_MAX_DST_SRC;
625 default:
626 unreachable("invalid VkBlendOp");
627 return BLEND_DST_PLUS_SRC;
628 }
629 }
630
631 void
632 tu6_emit_xs_config(struct tu_cs *cs,
633 gl_shader_stage stage, /* xs->type, but xs may be NULL */
634 const struct ir3_shader_variant *xs,
635 uint64_t binary_iova)
636 {
637 static const struct xs_config {
638 uint16_t reg_sp_xs_ctrl;
639 uint16_t reg_sp_xs_config;
640 uint16_t reg_hlsq_xs_ctrl;
641 uint16_t reg_sp_vs_obj_start;
642 uint8_t opcode;
643 enum a6xx_state_block sb : 8;
644 } xs_config[] = {
645 [MESA_SHADER_VERTEX] = {
646 REG_A6XX_SP_VS_CTRL_REG0,
647 REG_A6XX_SP_VS_CONFIG,
648 REG_A6XX_HLSQ_VS_CNTL,
649 REG_A6XX_SP_VS_OBJ_START_LO,
650 CP_LOAD_STATE6_GEOM,
651 SB6_VS_SHADER,
652 },
653 [MESA_SHADER_TESS_CTRL] = {
654 REG_A6XX_SP_HS_CTRL_REG0,
655 REG_A6XX_SP_HS_CONFIG,
656 REG_A6XX_HLSQ_HS_CNTL,
657 REG_A6XX_SP_HS_OBJ_START_LO,
658 CP_LOAD_STATE6_GEOM,
659 SB6_HS_SHADER,
660 },
661 [MESA_SHADER_TESS_EVAL] = {
662 REG_A6XX_SP_DS_CTRL_REG0,
663 REG_A6XX_SP_DS_CONFIG,
664 REG_A6XX_HLSQ_DS_CNTL,
665 REG_A6XX_SP_DS_OBJ_START_LO,
666 CP_LOAD_STATE6_GEOM,
667 SB6_DS_SHADER,
668 },
669 [MESA_SHADER_GEOMETRY] = {
670 REG_A6XX_SP_GS_CTRL_REG0,
671 REG_A6XX_SP_GS_CONFIG,
672 REG_A6XX_HLSQ_GS_CNTL,
673 REG_A6XX_SP_GS_OBJ_START_LO,
674 CP_LOAD_STATE6_GEOM,
675 SB6_GS_SHADER,
676 },
677 [MESA_SHADER_FRAGMENT] = {
678 REG_A6XX_SP_FS_CTRL_REG0,
679 REG_A6XX_SP_FS_CONFIG,
680 REG_A6XX_HLSQ_FS_CNTL,
681 REG_A6XX_SP_FS_OBJ_START_LO,
682 CP_LOAD_STATE6_FRAG,
683 SB6_FS_SHADER,
684 },
685 [MESA_SHADER_COMPUTE] = {
686 REG_A6XX_SP_CS_CTRL_REG0,
687 REG_A6XX_SP_CS_CONFIG,
688 REG_A6XX_HLSQ_CS_CNTL,
689 REG_A6XX_SP_CS_OBJ_START_LO,
690 CP_LOAD_STATE6_FRAG,
691 SB6_CS_SHADER,
692 },
693 };
694 const struct xs_config *cfg = &xs_config[stage];
695
696 if (!xs) {
697 /* shader stage disabled */
698 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 1);
699 tu_cs_emit(cs, 0);
700
701 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
702 tu_cs_emit(cs, 0);
703 return;
704 }
705
706 bool is_fs = xs->type == MESA_SHADER_FRAGMENT;
707 enum a3xx_threadsize threadsize = FOUR_QUADS;
708
709 /* TODO:
710 * the "threadsize" field may have nothing to do with threadsize,
711 * use a value that matches the blob until it is figured out
712 */
713 if (xs->type == MESA_SHADER_GEOMETRY)
714 threadsize = TWO_QUADS;
715
716 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_ctrl, 1);
717 tu_cs_emit(cs,
718 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize) |
719 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs->info.max_reg + 1) |
720 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
721 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs->branchstack) |
722 COND(xs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
723 COND(xs->need_fine_derivatives, A6XX_SP_VS_CTRL_REG0_DIFF_FINE) |
724 /* only fragment shader sets VARYING bit */
725 COND(xs->total_in && is_fs, A6XX_SP_FS_CTRL_REG0_VARYING) |
726 /* unknown bit, seems unnecessary */
727 COND(is_fs, 0x1000000));
728
729 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 2);
730 tu_cs_emit(cs, A6XX_SP_VS_CONFIG_ENABLED |
731 COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
732 COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
733 COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
734 COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
735 A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
736 A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
737 tu_cs_emit(cs, xs->instrlen);
738
739 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
740 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(xs->constlen, 4)) |
741 A6XX_HLSQ_VS_CNTL_ENABLED);
742
743 /* emit program binary
744 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
745 */
746
747 assert((binary_iova & 0x7f) == 0);
748
749 tu_cs_emit_pkt4(cs, cfg->reg_sp_vs_obj_start, 2);
750 tu_cs_emit_qw(cs, binary_iova);
751
752 tu_cs_emit_pkt7(cs, cfg->opcode, 3);
753 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
754 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
755 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
756 CP_LOAD_STATE6_0_STATE_BLOCK(cfg->sb) |
757 CP_LOAD_STATE6_0_NUM_UNIT(xs->instrlen));
758 tu_cs_emit_qw(cs, binary_iova);
759
760 /* emit immediates */
761
762 const struct ir3_const_state *const_state = &xs->shader->const_state;
763 uint32_t base = const_state->offsets.immediate;
764 int size = const_state->immediates_count;
765
766 /* truncate size to avoid writing constants that shader
767 * does not use:
768 */
769 size = MIN2(size + base, xs->constlen) - base;
770
771 if (size <= 0)
772 return;
773
774 tu_cs_emit_pkt7(cs, cfg->opcode, 3 + size * 4);
775 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
776 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
777 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
778 CP_LOAD_STATE6_0_STATE_BLOCK(cfg->sb) |
779 CP_LOAD_STATE6_0_NUM_UNIT(size));
780 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
781 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
782
783 for (unsigned i = 0; i < size; i++) {
784 tu_cs_emit(cs, const_state->immediates[i].val[0]);
785 tu_cs_emit(cs, const_state->immediates[i].val[1]);
786 tu_cs_emit(cs, const_state->immediates[i].val[2]);
787 tu_cs_emit(cs, const_state->immediates[i].val[3]);
788 }
789 }
790
791 static void
792 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
793 const struct ir3_shader_variant *v,
794 uint32_t binary_iova)
795 {
796 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
797 tu_cs_emit(cs, 0xff);
798
799 tu6_emit_xs_config(cs, MESA_SHADER_COMPUTE, v, binary_iova);
800
801 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
802 tu_cs_emit(cs, 0x41);
803
804 uint32_t local_invocation_id =
805 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
806 uint32_t work_group_id =
807 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
808
809 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
810 tu_cs_emit(cs,
811 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
812 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
813 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
814 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
815 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
816 }
817
818 static void
819 tu6_emit_vs_system_values(struct tu_cs *cs,
820 const struct ir3_shader_variant *vs,
821 const struct ir3_shader_variant *gs,
822 bool primid_passthru)
823 {
824 const uint32_t vertexid_regid =
825 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
826 const uint32_t instanceid_regid =
827 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
828 const uint32_t primitiveid_regid = gs ?
829 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
830 regid(63, 0);
831 const uint32_t gsheader_regid = gs ?
832 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
833 regid(63, 0);
834
835 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
836 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
837 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
838 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
839 0xfc000000);
840 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
841 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
842 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
843 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
844 0xfc00); /* VFD_CONTROL_5 */
845 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
846 }
847
848 /* Add any missing varyings needed for stream-out. Otherwise varyings not
849 * used by fragment shader will be stripped out.
850 */
851 static void
852 tu6_link_streamout(struct ir3_shader_linkage *l,
853 const struct ir3_shader_variant *v)
854 {
855 const struct ir3_stream_output_info *info = &v->shader->stream_output;
856
857 /*
858 * First, any stream-out varyings not already in linkage map (ie. also
859 * consumed by frag shader) need to be added:
860 */
861 for (unsigned i = 0; i < info->num_outputs; i++) {
862 const struct ir3_stream_output *out = &info->output[i];
863 unsigned compmask =
864 (1 << (out->num_components + out->start_component)) - 1;
865 unsigned k = out->register_index;
866 unsigned idx, nextloc = 0;
867
868 /* psize/pos need to be the last entries in linkage map, and will
869 * get added link_stream_out, so skip over them:
870 */
871 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
872 v->outputs[k].slot == VARYING_SLOT_POS)
873 continue;
874
875 for (idx = 0; idx < l->cnt; idx++) {
876 if (l->var[idx].regid == v->outputs[k].regid)
877 break;
878 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
879 }
880
881 /* add if not already in linkage map: */
882 if (idx == l->cnt)
883 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
884
885 /* expand component-mask if needed, ie streaming out all components
886 * but frag shader doesn't consume all components:
887 */
888 if (compmask & ~l->var[idx].compmask) {
889 l->var[idx].compmask |= compmask;
890 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
891 util_last_bit(l->var[idx].compmask));
892 }
893 }
894 }
895
896 static void
897 tu6_setup_streamout(const struct ir3_shader_variant *v,
898 struct ir3_shader_linkage *l, struct tu_streamout_state *tf)
899 {
900 const struct ir3_stream_output_info *info = &v->shader->stream_output;
901
902 memset(tf, 0, sizeof(*tf));
903
904 tf->prog_count = align(l->max_loc, 2) / 2;
905
906 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
907
908 /* set stride info to the streamout state */
909 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++)
910 tf->stride[i] = info->stride[i];
911
912 for (unsigned i = 0; i < info->num_outputs; i++) {
913 const struct ir3_stream_output *out = &info->output[i];
914 unsigned k = out->register_index;
915 unsigned idx;
916
917 /* Skip it, if there's an unused reg in the middle of outputs. */
918 if (v->outputs[k].regid == INVALID_REG)
919 continue;
920
921 tf->ncomp[out->output_buffer] += out->num_components;
922
923 /* linkage map sorted by order frag shader wants things, so
924 * a bit less ideal here..
925 */
926 for (idx = 0; idx < l->cnt; idx++)
927 if (l->var[idx].regid == v->outputs[k].regid)
928 break;
929
930 debug_assert(idx < l->cnt);
931
932 for (unsigned j = 0; j < out->num_components; j++) {
933 unsigned c = j + out->start_component;
934 unsigned loc = l->var[idx].loc + c;
935 unsigned off = j + out->dst_offset; /* in dwords */
936
937 if (loc & 1) {
938 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
939 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
940 A6XX_VPC_SO_PROG_B_OFF(off * 4);
941 } else {
942 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
943 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
944 A6XX_VPC_SO_PROG_A_OFF(off * 4);
945 }
946 }
947 }
948
949 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
950 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
951 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
952 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
953 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
954 }
955
956 static void
957 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
958 enum a6xx_state_block block, uint32_t offset,
959 uint32_t size, uint32_t *dwords) {
960 assert(size % 4 == 0);
961
962 tu_cs_emit_pkt7(cs, opcode, 3 + size);
963 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
964 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
965 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
966 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
967 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
968
969 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
970 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
971 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
972
973 tu_cs_emit_array(cs, dwords, size);
974 }
975
976 static void
977 tu6_emit_link_map(struct tu_cs *cs,
978 const struct ir3_shader_variant *producer,
979 const struct ir3_shader_variant *consumer) {
980 const struct ir3_const_state *const_state = &consumer->shader->const_state;
981 uint32_t base = const_state->offsets.primitive_map;
982 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
983 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
984 int size = DIV_ROUND_UP(num_loc, 4);
985
986 size = (MIN2(size + base, consumer->constlen) - base) * 4;
987 if (size <= 0)
988 return;
989
990 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size,
991 patch_locs);
992 }
993
994 static uint16_t
995 gl_primitive_to_tess(uint16_t primitive) {
996 switch (primitive) {
997 case GL_POINTS:
998 return TESS_POINTS;
999 case GL_LINE_STRIP:
1000 return TESS_LINES;
1001 case GL_TRIANGLE_STRIP:
1002 return TESS_CW_TRIS;
1003 default:
1004 unreachable("");
1005 }
1006 }
1007
1008 void
1009 tu6_emit_vpc(struct tu_cs *cs,
1010 const struct ir3_shader_variant *vs,
1011 const struct ir3_shader_variant *gs,
1012 const struct ir3_shader_variant *fs,
1013 struct tu_streamout_state *tf)
1014 {
1015 const struct ir3_shader_variant *last_shader = gs ?: vs;
1016 struct ir3_shader_linkage linkage = { .primid_loc = 0xff };
1017 if (fs)
1018 ir3_link_shaders(&linkage, last_shader, fs, true);
1019
1020 if (last_shader->shader->stream_output.num_outputs)
1021 tu6_link_streamout(&linkage, last_shader);
1022
1023 /* We do this after linking shaders in order to know whether PrimID
1024 * passthrough needs to be enabled.
1025 */
1026 bool primid_passthru = linkage.primid_loc != 0xff;
1027 tu6_emit_vs_system_values(cs, vs, gs, primid_passthru);
1028
1029 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
1030 tu_cs_emit(cs, ~linkage.varmask[0]);
1031 tu_cs_emit(cs, ~linkage.varmask[1]);
1032 tu_cs_emit(cs, ~linkage.varmask[2]);
1033 tu_cs_emit(cs, ~linkage.varmask[3]);
1034
1035 /* a6xx finds position/pointsize at the end */
1036 const uint32_t position_regid =
1037 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
1038 const uint32_t pointsize_regid =
1039 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
1040 const uint32_t layer_regid = gs ?
1041 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
1042
1043 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
1044 if (layer_regid != regid(63, 0)) {
1045 layer_loc = linkage.max_loc;
1046 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
1047 }
1048 if (position_regid != regid(63, 0)) {
1049 position_loc = linkage.max_loc;
1050 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
1051 }
1052 if (pointsize_regid != regid(63, 0)) {
1053 pointsize_loc = linkage.max_loc;
1054 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
1055 }
1056
1057 if (last_shader->shader->stream_output.num_outputs)
1058 tu6_setup_streamout(last_shader, &linkage, tf);
1059
1060 /* map outputs of the last shader to VPC */
1061 assert(linkage.cnt <= 32);
1062 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
1063 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
1064 uint32_t sp_out[16];
1065 uint32_t sp_vpc_dst[8];
1066 for (uint32_t i = 0; i < linkage.cnt; i++) {
1067 ((uint16_t *) sp_out)[i] =
1068 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
1069 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
1070 ((uint8_t *) sp_vpc_dst)[i] =
1071 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
1072 }
1073
1074 if (gs)
1075 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
1076 else
1077 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
1078 tu_cs_emit_array(cs, sp_out, sp_out_count);
1079
1080 if (gs)
1081 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
1082 else
1083 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
1084 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
1085
1086 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMID_CNTL, 1);
1087 tu_cs_emit(cs, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
1088
1089 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
1090 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
1091 COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
1092 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
1093 A6XX_VPC_CNTL_0_UNKLOC(0xff));
1094
1095 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
1096 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
1097 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
1098 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
1099
1100 if (gs) {
1101 uint32_t vertices_out, invocations, output, vec4_size;
1102 /* this detects the tu_clear_blit path, which doesn't set ->nir */
1103 if (gs->shader->nir) {
1104 tu6_emit_link_map(cs, vs, gs);
1105 vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
1106 output = gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
1107 invocations = gs->shader->nir->info.gs.invocations - 1;
1108 /* Size of per-primitive alloction in ldlw memory in vec4s. */
1109 vec4_size = gs->shader->nir->info.gs.vertices_in *
1110 DIV_ROUND_UP(vs->shader->output_size, 4);
1111 } else {
1112 vertices_out = 3;
1113 output = TESS_CW_TRIS;
1114 invocations = 0;
1115 vec4_size = 0;
1116 }
1117
1118 uint32_t primitive_regid =
1119 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
1120 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
1121 tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
1122 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
1123 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
1124
1125 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
1126 tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
1127
1128 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
1129 tu_cs_emit(cs, CONDREG(layer_regid,
1130 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
1131
1132 uint32_t flags_regid = ir3_find_output_regid(gs,
1133 VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
1134
1135 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
1136 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
1137 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
1138
1139 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
1140 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
1141 CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
1142 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
1143 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
1144
1145 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
1146 tu_cs_emit(cs,
1147 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
1148 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
1149 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
1150
1151 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
1152 tu_cs_emit(cs, 0);
1153
1154 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
1155 tu_cs_emit(cs, 0);
1156
1157 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
1158 tu_cs_emit(cs, 0xff);
1159
1160 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
1161 tu_cs_emit(cs, 0xffff00);
1162
1163 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1164 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
1165
1166 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
1167 tu_cs_emit(cs, 0);
1168
1169 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
1170 tu_cs_emit(cs, vs->shader->output_size);
1171 }
1172
1173 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
1174 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
1175
1176 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
1177 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
1178 (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
1179 }
1180
1181 static int
1182 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
1183 uint32_t index,
1184 uint8_t *interp_mode,
1185 uint8_t *ps_repl_mode)
1186 {
1187 enum
1188 {
1189 INTERP_SMOOTH = 0,
1190 INTERP_FLAT = 1,
1191 INTERP_ZERO = 2,
1192 INTERP_ONE = 3,
1193 };
1194 enum
1195 {
1196 PS_REPL_NONE = 0,
1197 PS_REPL_S = 1,
1198 PS_REPL_T = 2,
1199 PS_REPL_ONE_MINUS_T = 3,
1200 };
1201
1202 const uint32_t compmask = fs->inputs[index].compmask;
1203
1204 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1205 * fourth component occupy three consecutive varying slots
1206 */
1207 int shift = 0;
1208 *interp_mode = 0;
1209 *ps_repl_mode = 0;
1210 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1211 if (compmask & 0x1) {
1212 *ps_repl_mode |= PS_REPL_S << shift;
1213 shift += 2;
1214 }
1215 if (compmask & 0x2) {
1216 *ps_repl_mode |= PS_REPL_T << shift;
1217 shift += 2;
1218 }
1219 if (compmask & 0x4) {
1220 *interp_mode |= INTERP_ZERO << shift;
1221 shift += 2;
1222 }
1223 if (compmask & 0x8) {
1224 *interp_mode |= INTERP_ONE << 6;
1225 shift += 2;
1226 }
1227 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1228 fs->inputs[index].rasterflat) {
1229 for (int i = 0; i < 4; i++) {
1230 if (compmask & (1 << i)) {
1231 *interp_mode |= INTERP_FLAT << shift;
1232 shift += 2;
1233 }
1234 }
1235 }
1236
1237 return shift;
1238 }
1239
1240 static void
1241 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1242 const struct ir3_shader_variant *fs)
1243 {
1244 uint32_t interp_modes[8] = { 0 };
1245 uint32_t ps_repl_modes[8] = { 0 };
1246
1247 if (fs) {
1248 for (int i = -1;
1249 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1250
1251 /* get the mode for input i */
1252 uint8_t interp_mode;
1253 uint8_t ps_repl_mode;
1254 const int bits =
1255 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1256
1257 /* OR the mode into the array */
1258 const uint32_t inloc = fs->inputs[i].inloc * 2;
1259 uint32_t n = inloc / 32;
1260 uint32_t shift = inloc % 32;
1261 interp_modes[n] |= interp_mode << shift;
1262 ps_repl_modes[n] |= ps_repl_mode << shift;
1263 if (shift + bits > 32) {
1264 n++;
1265 shift = 32 - shift;
1266
1267 interp_modes[n] |= interp_mode >> shift;
1268 ps_repl_modes[n] |= ps_repl_mode >> shift;
1269 }
1270 }
1271 }
1272
1273 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1274 tu_cs_emit_array(cs, interp_modes, 8);
1275
1276 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1277 tu_cs_emit_array(cs, ps_repl_modes, 8);
1278 }
1279
1280 void
1281 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1282 {
1283 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1284 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
1285 uint32_t smask_in_regid;
1286
1287 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
1288 bool enable_varyings = fs->total_in > 0;
1289
1290 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1291 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1292 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1293 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1294 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1295 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1296 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1297 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1298 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1299
1300 if (fs->num_sampler_prefetch > 0) {
1301 assert(VALIDREG(ij_pix_regid));
1302 /* also, it seems like ij_pix is *required* to be r0.x */
1303 assert(ij_pix_regid == regid(0, 0));
1304 }
1305
1306 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1307 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1308 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1309 0x7000); // XXX);
1310 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1311 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1312 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1313 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1314 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1315 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1316 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1317 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1318 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1319 }
1320
1321 if (fs->num_sampler_prefetch > 0) {
1322 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1323 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1324 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1325 tu_cs_emit(cs,
1326 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1327 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1328 }
1329 }
1330
1331 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1332 tu_cs_emit(cs, 0x7);
1333 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1334 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1335 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1336 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
1337 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
1338 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
1339 0xfc00fc00);
1340 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1341 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1342 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
1343 0x0000fc00);
1344 tu_cs_emit(cs, 0xfc);
1345
1346 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1347 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1348
1349 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1350 tu_cs_emit(cs,
1351 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
1352 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
1353 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
1354 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
1355 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1356 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
1357 A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)) |
1358 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
1359
1360 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1361 tu_cs_emit(cs,
1362 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
1363 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
1364 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
1365 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1366 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
1367 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1368 COND(fs->fragcoord_compmask != 0, A6XX_RB_RENDER_CONTROL0_SIZE |
1369 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)) |
1370 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
1371 tu_cs_emit(cs,
1372 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1373 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1374 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
1375 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1376
1377 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1378 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1379
1380 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1381 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1382
1383 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1384 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1385 }
1386
1387 static void
1388 tu6_emit_fs_outputs(struct tu_cs *cs,
1389 const struct ir3_shader_variant *fs,
1390 uint32_t mrt_count, bool dual_src_blend,
1391 uint32_t render_components)
1392 {
1393 uint32_t smask_regid, posz_regid;
1394
1395 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1396 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1397
1398 uint32_t fragdata_regid[8];
1399 if (fs->color0_mrt) {
1400 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1401 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1402 fragdata_regid[i] = fragdata_regid[0];
1403 } else {
1404 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1405 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1406 }
1407
1408 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1409 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1410 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1411 COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE) |
1412 0xfc000000);
1413 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1414
1415 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1416 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1417 // TODO we could have a mix of half and full precision outputs,
1418 // we really need to figure out half-precision from IR3_REG_HALF
1419 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1420 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1421 }
1422
1423 tu_cs_emit_regs(cs,
1424 A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
1425
1426 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1427 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1428 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
1429 COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1430 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1431
1432 tu_cs_emit_regs(cs,
1433 A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
1434
1435 enum a6xx_ztest_mode zmode;
1436
1437 if (fs->no_earlyz || fs->has_kill || fs->writes_pos) {
1438 zmode = A6XX_LATE_Z;
1439 } else {
1440 zmode = A6XX_EARLY_Z;
1441 }
1442
1443 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1444 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1445
1446 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1447 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1448 }
1449
1450 static void
1451 tu6_emit_geometry_consts(struct tu_cs *cs,
1452 const struct ir3_shader_variant *vs,
1453 const struct ir3_shader_variant *gs) {
1454 unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
1455
1456 uint32_t params[4] = {
1457 vs->shader->output_size * num_vertices * 4, /* primitive stride */
1458 vs->shader->output_size * 4, /* vertex stride */
1459 0,
1460 0,
1461 };
1462 uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
1463 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1464 ARRAY_SIZE(params), params);
1465
1466 uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
1467 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1468 ARRAY_SIZE(params), params);
1469 }
1470
1471 /* get pointer to first variant, return NULL if shader is NULL */
1472 static const struct ir3_shader_variant *
1473 tu_shader_get_variant(const struct tu_shader *shader)
1474 {
1475 return shader ? &shader->variants[0] : NULL;
1476 }
1477
1478 static void
1479 tu6_emit_program(struct tu_cs *cs,
1480 struct tu_pipeline_builder *builder,
1481 const struct tu_bo *binary_bo,
1482 bool binning_pass,
1483 struct tu_streamout_state *tf)
1484 {
1485 const struct ir3_shader_variant *vs =
1486 tu_shader_get_variant(builder->shaders[MESA_SHADER_VERTEX]);
1487 const struct ir3_shader_variant *gs =
1488 tu_shader_get_variant(builder->shaders[MESA_SHADER_GEOMETRY]);
1489 const struct ir3_shader_variant *fs =
1490 tu_shader_get_variant(builder->shaders[MESA_SHADER_FRAGMENT]);
1491 gl_shader_stage stage = MESA_SHADER_VERTEX;
1492
1493 STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
1494
1495 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1496 tu_cs_emit(cs, 0xff); /* XXX */
1497
1498 /* if we have streamout, use full VS in binning pass, as the
1499 * binning pass VS will have outputs on other than position/psize
1500 * stripped out
1501 *
1502 * GS also can have streamout, but we completely disable the
1503 * the binning pass variant when GS is present because we don't
1504 * support compiling correct binning pass variants with GS
1505 */
1506 if (binning_pass && vs->shader->stream_output.num_outputs == 0 && !gs) {
1507 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1508 tu6_emit_xs_config(cs, stage, vs,
1509 binary_bo->iova + builder->binning_vs_offset);
1510 stage++;
1511 }
1512
1513 for (; stage < ARRAY_SIZE(builder->shaders); stage++) {
1514 const struct ir3_shader_variant *xs =
1515 tu_shader_get_variant(builder->shaders[stage]);
1516
1517 if (stage == MESA_SHADER_FRAGMENT && binning_pass)
1518 fs = xs = NULL;
1519
1520 tu6_emit_xs_config(cs, stage, xs,
1521 binary_bo->iova + builder->shader_offsets[stage]);
1522 }
1523
1524 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
1525 tu_cs_emit(cs, 0);
1526
1527 tu6_emit_vpc(cs, vs, gs, fs, tf);
1528 tu6_emit_vpc_varying_modes(cs, fs);
1529
1530 if (fs) {
1531 tu6_emit_fs_inputs(cs, fs);
1532 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
1533 builder->use_dual_src_blend,
1534 builder->render_components);
1535 } else {
1536 /* TODO: check if these can be skipped if fs is disabled */
1537 struct ir3_shader_variant dummy_variant = {};
1538 tu6_emit_fs_inputs(cs, &dummy_variant);
1539 tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count,
1540 builder->use_dual_src_blend,
1541 builder->render_components);
1542 }
1543
1544 if (gs)
1545 tu6_emit_geometry_consts(cs, vs, gs);
1546 }
1547
1548 static void
1549 tu6_emit_vertex_input(struct tu_cs *cs,
1550 const struct ir3_shader_variant *vs,
1551 const VkPipelineVertexInputStateCreateInfo *info,
1552 uint32_t *bindings_used)
1553 {
1554 uint32_t vfd_decode_idx = 0;
1555 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1556
1557 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1558 const VkVertexInputBindingDescription *binding =
1559 &info->pVertexBindingDescriptions[i];
1560
1561 tu_cs_emit_regs(cs,
1562 A6XX_VFD_FETCH_STRIDE(binding->binding, binding->stride));
1563
1564 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1565 binding_instanced |= 1 << binding->binding;
1566
1567 *bindings_used |= 1 << binding->binding;
1568 }
1569
1570 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1571
1572 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1573 const VkVertexInputAttributeDescription *attr =
1574 &info->pVertexAttributeDescriptions[i];
1575 uint32_t input_idx;
1576
1577 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1578 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1579 break;
1580 }
1581
1582 /* attribute not used, skip it */
1583 if (input_idx == vs->inputs_count)
1584 continue;
1585
1586 const struct tu_native_format format = tu6_format_vtx(attr->format);
1587 tu_cs_emit_regs(cs,
1588 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1589 .idx = attr->binding,
1590 .offset = attr->offset,
1591 .instanced = binding_instanced & (1 << attr->binding),
1592 .format = format.fmt,
1593 .swap = format.swap,
1594 .unk30 = 1,
1595 ._float = !vk_format_is_int(attr->format)),
1596 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, 1));
1597
1598 tu_cs_emit_regs(cs,
1599 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1600 .writemask = vs->inputs[input_idx].compmask,
1601 .regid = vs->inputs[input_idx].regid));
1602
1603 vfd_decode_idx++;
1604 }
1605
1606 tu_cs_emit_regs(cs,
1607 A6XX_VFD_CONTROL_0(
1608 .fetch_cnt = vfd_decode_idx, /* decode_cnt for binning pass ? */
1609 .decode_cnt = vfd_decode_idx));
1610 }
1611
1612 static uint32_t
1613 tu6_guardband_adj(uint32_t v)
1614 {
1615 if (v > 256)
1616 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1617 else
1618 return 511;
1619 }
1620
1621 void
1622 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1623 {
1624 float offsets[3];
1625 float scales[3];
1626 scales[0] = viewport->width / 2.0f;
1627 scales[1] = viewport->height / 2.0f;
1628 scales[2] = viewport->maxDepth - viewport->minDepth;
1629 offsets[0] = viewport->x + scales[0];
1630 offsets[1] = viewport->y + scales[1];
1631 offsets[2] = viewport->minDepth;
1632
1633 VkOffset2D min;
1634 VkOffset2D max;
1635 min.x = (int32_t) viewport->x;
1636 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1637 if (viewport->height >= 0.0f) {
1638 min.y = (int32_t) viewport->y;
1639 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1640 } else {
1641 min.y = (int32_t)(viewport->y + viewport->height);
1642 max.y = (int32_t) ceilf(viewport->y);
1643 }
1644 /* the spec allows viewport->height to be 0.0f */
1645 if (min.y == max.y)
1646 max.y++;
1647 assert(min.x >= 0 && min.x < max.x);
1648 assert(min.y >= 0 && min.y < max.y);
1649
1650 VkExtent2D guardband_adj;
1651 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1652 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1653
1654 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1655 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1656 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1657 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1658 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1659 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1660 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1661
1662 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1663 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1664 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1665 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1666 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1667
1668 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1669 tu_cs_emit(cs,
1670 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1671 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1672
1673 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1674 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1675
1676 tu_cs_emit_regs(cs,
1677 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1678 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1679
1680 tu_cs_emit_regs(cs,
1681 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1682 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1683 }
1684
1685 void
1686 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1687 {
1688 const VkOffset2D min = scissor->offset;
1689 const VkOffset2D max = {
1690 scissor->offset.x + scissor->extent.width,
1691 scissor->offset.y + scissor->extent.height,
1692 };
1693
1694 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1695 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1696 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1697 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1698 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1699 }
1700
1701 void
1702 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1703 {
1704 if (!samp_loc) {
1705 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1706 tu_cs_emit(cs, 0);
1707
1708 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1709 tu_cs_emit(cs, 0);
1710
1711 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1712 tu_cs_emit(cs, 0);
1713 return;
1714 }
1715
1716 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1717 assert(samp_loc->sampleLocationGridSize.width == 1);
1718 assert(samp_loc->sampleLocationGridSize.height == 1);
1719
1720 uint32_t sample_config =
1721 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1722 uint32_t sample_locations = 0;
1723 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1724 sample_locations |=
1725 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1726 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1727 }
1728
1729 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1730 tu_cs_emit(cs, sample_config);
1731 tu_cs_emit(cs, sample_locations);
1732
1733 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1734 tu_cs_emit(cs, sample_config);
1735 tu_cs_emit(cs, sample_locations);
1736
1737 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1738 tu_cs_emit(cs, sample_config);
1739 tu_cs_emit(cs, sample_locations);
1740 }
1741
1742 static void
1743 tu6_emit_gras_unknowns(struct tu_cs *cs)
1744 {
1745 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1746 tu_cs_emit(cs, 0x0);
1747 }
1748
1749 static void
1750 tu6_emit_point_size(struct tu_cs *cs)
1751 {
1752 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1753 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1754 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1755 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f).value);
1756 }
1757
1758 static uint32_t
1759 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1760 VkSampleCountFlagBits samples)
1761 {
1762 uint32_t gras_su_cntl = 0;
1763
1764 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1765 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1766 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1767 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1768
1769 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1770 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1771
1772 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1773
1774 if (rast_info->depthBiasEnable)
1775 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1776
1777 if (samples > VK_SAMPLE_COUNT_1_BIT)
1778 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1779
1780 return gras_su_cntl;
1781 }
1782
1783 void
1784 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1785 uint32_t gras_su_cntl,
1786 float line_width)
1787 {
1788 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1789 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1790
1791 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1792 tu_cs_emit(cs, gras_su_cntl);
1793 }
1794
1795 void
1796 tu6_emit_depth_bias(struct tu_cs *cs,
1797 float constant_factor,
1798 float clamp,
1799 float slope_factor)
1800 {
1801 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1802 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1803 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1804 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1805 }
1806
1807 static void
1808 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1809 {
1810 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1811 tu_cs_emit(cs, 0);
1812 }
1813
1814 static void
1815 tu6_emit_depth_control(struct tu_cs *cs,
1816 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1817 const VkPipelineRasterizationStateCreateInfo *rast_info)
1818 {
1819 assert(!ds_info->depthBoundsTestEnable);
1820
1821 uint32_t rb_depth_cntl = 0;
1822 if (ds_info->depthTestEnable) {
1823 rb_depth_cntl |=
1824 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1825 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1826 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1827
1828 if (rast_info->depthClampEnable)
1829 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1830
1831 if (ds_info->depthWriteEnable)
1832 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1833 }
1834
1835 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1836 tu_cs_emit(cs, rb_depth_cntl);
1837 }
1838
1839 static void
1840 tu6_emit_stencil_control(struct tu_cs *cs,
1841 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1842 {
1843 uint32_t rb_stencil_control = 0;
1844 if (ds_info->stencilTestEnable) {
1845 const VkStencilOpState *front = &ds_info->front;
1846 const VkStencilOpState *back = &ds_info->back;
1847 rb_stencil_control |=
1848 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1849 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1850 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1851 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1852 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1853 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1854 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1855 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1856 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1857 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1858 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1859 }
1860
1861 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1862 tu_cs_emit(cs, rb_stencil_control);
1863 }
1864
1865 void
1866 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1867 {
1868 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1869 tu_cs_emit(
1870 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1871 }
1872
1873 void
1874 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1875 {
1876 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1877 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1878 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1879 }
1880
1881 void
1882 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1883 {
1884 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1885 tu_cs_emit(cs,
1886 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1887 }
1888
1889 static uint32_t
1890 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1891 bool has_alpha)
1892 {
1893 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1894 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1895 has_alpha ? att->srcColorBlendFactor
1896 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1897 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1898 has_alpha ? att->dstColorBlendFactor
1899 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1900 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1901 const enum adreno_rb_blend_factor src_alpha_factor =
1902 tu6_blend_factor(att->srcAlphaBlendFactor);
1903 const enum adreno_rb_blend_factor dst_alpha_factor =
1904 tu6_blend_factor(att->dstAlphaBlendFactor);
1905
1906 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1907 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1908 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1909 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1910 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1911 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1912 }
1913
1914 static uint32_t
1915 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1916 uint32_t rb_mrt_control_rop,
1917 bool is_int,
1918 bool has_alpha)
1919 {
1920 uint32_t rb_mrt_control =
1921 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1922
1923 /* ignore blending and logic op for integer attachments */
1924 if (is_int) {
1925 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1926 return rb_mrt_control;
1927 }
1928
1929 rb_mrt_control |= rb_mrt_control_rop;
1930
1931 if (att->blendEnable) {
1932 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1933
1934 if (has_alpha)
1935 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1936 }
1937
1938 return rb_mrt_control;
1939 }
1940
1941 static void
1942 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1943 const VkPipelineColorBlendStateCreateInfo *blend_info,
1944 const VkFormat attachment_formats[MAX_RTS],
1945 uint32_t *blend_enable_mask)
1946 {
1947 *blend_enable_mask = 0;
1948
1949 bool rop_reads_dst = false;
1950 uint32_t rb_mrt_control_rop = 0;
1951 if (blend_info->logicOpEnable) {
1952 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1953 rb_mrt_control_rop =
1954 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1955 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1956 }
1957
1958 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1959 const VkPipelineColorBlendAttachmentState *att =
1960 &blend_info->pAttachments[i];
1961 const VkFormat format = attachment_formats[i];
1962
1963 uint32_t rb_mrt_control = 0;
1964 uint32_t rb_mrt_blend_control = 0;
1965 if (format != VK_FORMAT_UNDEFINED) {
1966 const bool is_int = vk_format_is_int(format);
1967 const bool has_alpha = vk_format_has_alpha(format);
1968
1969 rb_mrt_control =
1970 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1971 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1972
1973 if (att->blendEnable || rop_reads_dst)
1974 *blend_enable_mask |= 1 << i;
1975 }
1976
1977 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1978 tu_cs_emit(cs, rb_mrt_control);
1979 tu_cs_emit(cs, rb_mrt_blend_control);
1980 }
1981 }
1982
1983 static void
1984 tu6_emit_blend_control(struct tu_cs *cs,
1985 uint32_t blend_enable_mask,
1986 bool dual_src_blend,
1987 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1988 {
1989 const uint32_t sample_mask =
1990 msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff)
1991 : ((1 << msaa_info->rasterizationSamples) - 1);
1992
1993 tu_cs_emit_regs(cs,
1994 A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
1995 .dual_color_in_enable = dual_src_blend,
1996 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1997 .unk8 = true));
1998
1999 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
2000 tu_cs_emit_regs(cs,
2001 A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
2002 .independent_blend = true,
2003 .sample_mask = sample_mask,
2004 .dual_color_in_enable = dual_src_blend,
2005 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
2006 .alpha_to_one = msaa_info->alphaToOneEnable));
2007 }
2008
2009 void
2010 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
2011 {
2012 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2013 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
2014 }
2015
2016 static VkResult
2017 tu_pipeline_create(struct tu_device *dev,
2018 struct tu_pipeline_layout *layout,
2019 bool compute,
2020 const VkAllocationCallbacks *pAllocator,
2021 struct tu_pipeline **out_pipeline)
2022 {
2023 struct tu_pipeline *pipeline =
2024 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
2025 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2026 if (!pipeline)
2027 return VK_ERROR_OUT_OF_HOST_MEMORY;
2028
2029 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
2030
2031 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
2032 * that LOAD_STATE can potentially take up a large amount of space so we
2033 * calculate its size explicitly.
2034 */
2035 unsigned load_state_size = tu6_load_state_size(layout, compute);
2036 VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048 + load_state_size);
2037 if (result != VK_SUCCESS) {
2038 vk_free2(&dev->alloc, pAllocator, pipeline);
2039 return result;
2040 }
2041
2042 *out_pipeline = pipeline;
2043
2044 return VK_SUCCESS;
2045 }
2046
2047 static VkResult
2048 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
2049 {
2050 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
2051 NULL
2052 };
2053 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
2054 gl_shader_stage stage =
2055 tu_shader_stage(builder->create_info->pStages[i].stage);
2056 stage_infos[stage] = &builder->create_info->pStages[i];
2057 }
2058
2059 struct tu_shader_compile_options options;
2060 tu_shader_compile_options_init(&options, builder->create_info);
2061
2062 /* compile shaders in reverse order */
2063 struct tu_shader *next_stage_shader = NULL;
2064 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
2065 stage > MESA_SHADER_NONE; stage--) {
2066 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
2067 if (!stage_info && stage != MESA_SHADER_FRAGMENT)
2068 continue;
2069
2070 struct tu_shader *shader =
2071 tu_shader_create(builder->device, stage, stage_info, builder->layout,
2072 builder->alloc);
2073 if (!shader)
2074 return VK_ERROR_OUT_OF_HOST_MEMORY;
2075
2076 VkResult result =
2077 tu_shader_compile(builder->device, shader, next_stage_shader,
2078 &options, builder->alloc);
2079 if (result != VK_SUCCESS)
2080 return result;
2081
2082 builder->shaders[stage] = shader;
2083 builder->shader_offsets[stage] = builder->shader_total_size;
2084 builder->shader_total_size +=
2085 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
2086
2087 next_stage_shader = shader;
2088 }
2089
2090 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2091 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2092 const struct ir3_shader_variant *variant;
2093
2094 if (vs->ir3_shader.stream_output.num_outputs)
2095 variant = &vs->variants[0];
2096 else
2097 variant = &vs->variants[1];
2098
2099 builder->binning_vs_offset = builder->shader_total_size;
2100 builder->shader_total_size +=
2101 sizeof(uint32_t) * variant->info.sizedwords;
2102 }
2103
2104 return VK_SUCCESS;
2105 }
2106
2107 static VkResult
2108 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
2109 struct tu_pipeline *pipeline)
2110 {
2111 struct tu_bo *bo = &pipeline->program.binary_bo;
2112
2113 VkResult result =
2114 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
2115 if (result != VK_SUCCESS)
2116 return result;
2117
2118 result = tu_bo_map(builder->device, bo);
2119 if (result != VK_SUCCESS)
2120 return result;
2121
2122 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2123 const struct tu_shader *shader = builder->shaders[i];
2124 if (!shader)
2125 continue;
2126
2127 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
2128 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
2129 }
2130
2131 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2132 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2133 const struct ir3_shader_variant *variant;
2134 void *bin;
2135
2136 if (vs->ir3_shader.stream_output.num_outputs) {
2137 variant = &vs->variants[0];
2138 bin = vs->binary;
2139 } else {
2140 variant = &vs->variants[1];
2141 bin = vs->binning_binary;
2142 }
2143
2144 memcpy(bo->map + builder->binning_vs_offset, bin,
2145 sizeof(uint32_t) * variant->info.sizedwords);
2146 }
2147
2148 return VK_SUCCESS;
2149 }
2150
2151 static void
2152 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2153 struct tu_pipeline *pipeline)
2154 {
2155 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2156 builder->create_info->pDynamicState;
2157
2158 if (!dynamic_info)
2159 return;
2160
2161 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2162 pipeline->dynamic_state.mask |=
2163 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
2164 }
2165 }
2166
2167 static void
2168 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2169 struct tu_shader *shader,
2170 struct ir3_shader_variant *v)
2171 {
2172 link->ubo_state = v->shader->ubo_state;
2173 link->const_state = v->shader->const_state;
2174 link->constlen = v->constlen;
2175 link->push_consts = shader->push_consts;
2176 }
2177
2178 static void
2179 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2180 struct tu_pipeline *pipeline)
2181 {
2182 struct tu_cs prog_cs;
2183 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2184 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout);
2185 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2186
2187 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2188 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout);
2189 pipeline->program.binning_state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2190
2191 VkShaderStageFlags stages = 0;
2192 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2193 stages |= builder->create_info->pStages[i].stage;
2194 }
2195 pipeline->active_stages = stages;
2196
2197 uint32_t desc_sets = 0;
2198 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2199 if (!builder->shaders[i])
2200 continue;
2201
2202 tu_pipeline_set_linkage(&pipeline->program.link[i],
2203 builder->shaders[i],
2204 &builder->shaders[i]->variants[0]);
2205 desc_sets |= builder->shaders[i]->active_desc_sets;
2206 }
2207 pipeline->active_desc_sets = desc_sets;
2208
2209 if (builder->shaders[MESA_SHADER_FRAGMENT]) {
2210 memcpy(pipeline->program.input_attachment_idx,
2211 builder->shaders[MESA_SHADER_FRAGMENT]->attachment_idx,
2212 sizeof(pipeline->program.input_attachment_idx));
2213 }
2214 }
2215
2216 static void
2217 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2218 struct tu_pipeline *pipeline)
2219 {
2220 const VkPipelineVertexInputStateCreateInfo *vi_info =
2221 builder->create_info->pVertexInputState;
2222 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2223
2224 struct tu_cs vi_cs;
2225 tu_cs_begin_sub_stream(&pipeline->cs,
2226 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2227 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
2228 &pipeline->vi.bindings_used);
2229 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2230
2231 if (vs->has_binning_pass) {
2232 tu_cs_begin_sub_stream(&pipeline->cs,
2233 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2234 tu6_emit_vertex_input(
2235 &vi_cs, &vs->variants[1], vi_info, &pipeline->vi.bindings_used);
2236 pipeline->vi.binning_state_ib =
2237 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2238 }
2239 }
2240
2241 static void
2242 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2243 struct tu_pipeline *pipeline)
2244 {
2245 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2246 builder->create_info->pInputAssemblyState;
2247
2248 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2249 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2250 }
2251
2252 static void
2253 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2254 struct tu_pipeline *pipeline)
2255 {
2256 /* The spec says:
2257 *
2258 * pViewportState is a pointer to an instance of the
2259 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2260 * pipeline has rasterization disabled."
2261 *
2262 * We leave the relevant registers stale in that case.
2263 */
2264 if (builder->rasterizer_discard)
2265 return;
2266
2267 const VkPipelineViewportStateCreateInfo *vp_info =
2268 builder->create_info->pViewportState;
2269
2270 struct tu_cs vp_cs;
2271 tu_cs_begin_sub_stream(&pipeline->cs, 21, &vp_cs);
2272
2273 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
2274 assert(vp_info->viewportCount == 1);
2275 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
2276 }
2277
2278 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
2279 assert(vp_info->scissorCount == 1);
2280 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
2281 }
2282
2283 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
2284 }
2285
2286 static void
2287 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2288 struct tu_pipeline *pipeline)
2289 {
2290 const VkPipelineRasterizationStateCreateInfo *rast_info =
2291 builder->create_info->pRasterizationState;
2292
2293 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
2294
2295 struct tu_cs rast_cs;
2296 tu_cs_begin_sub_stream(&pipeline->cs, 20, &rast_cs);
2297
2298
2299 tu_cs_emit_regs(&rast_cs,
2300 A6XX_GRAS_CL_CNTL(
2301 .znear_clip_disable = rast_info->depthClampEnable,
2302 .zfar_clip_disable = rast_info->depthClampEnable,
2303 .unk5 = rast_info->depthClampEnable,
2304 .zero_gb_scale_z = 1,
2305 .vp_clip_code_ignore = 1));
2306 /* move to hw ctx init? */
2307 tu6_emit_gras_unknowns(&rast_cs);
2308 tu6_emit_point_size(&rast_cs);
2309
2310 const uint32_t gras_su_cntl =
2311 tu6_gras_su_cntl(rast_info, builder->samples);
2312
2313 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
2314 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
2315
2316 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
2317 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
2318 rast_info->depthBiasClamp,
2319 rast_info->depthBiasSlopeFactor);
2320 }
2321
2322 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
2323
2324 pipeline->rast.gras_su_cntl = gras_su_cntl;
2325 }
2326
2327 static void
2328 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2329 struct tu_pipeline *pipeline)
2330 {
2331 /* The spec says:
2332 *
2333 * pDepthStencilState is a pointer to an instance of the
2334 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2335 * the pipeline has rasterization disabled or if the subpass of the
2336 * render pass the pipeline is created against does not use a
2337 * depth/stencil attachment.
2338 *
2339 * Disable both depth and stencil tests if there is no ds attachment,
2340 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2341 * only the separate stencil attachment
2342 */
2343 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2344 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2345 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2346 ? builder->create_info->pDepthStencilState
2347 : &dummy_ds_info;
2348 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2349 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2350 ? ds_info : &dummy_ds_info;
2351
2352 struct tu_cs ds_cs;
2353 tu_cs_begin_sub_stream(&pipeline->cs, 12, &ds_cs);
2354
2355 /* move to hw ctx init? */
2356 tu6_emit_alpha_control_disable(&ds_cs);
2357
2358 tu6_emit_depth_control(&ds_cs, ds_info_depth,
2359 builder->create_info->pRasterizationState);
2360 tu6_emit_stencil_control(&ds_cs, ds_info);
2361
2362 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2363 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
2364 ds_info->back.compareMask);
2365 }
2366 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2367 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
2368 ds_info->back.writeMask);
2369 }
2370 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2371 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
2372 ds_info->back.reference);
2373 }
2374
2375 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
2376 }
2377
2378 static void
2379 tu_pipeline_builder_parse_multisample_and_color_blend(
2380 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2381 {
2382 /* The spec says:
2383 *
2384 * pMultisampleState is a pointer to an instance of the
2385 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2386 * has rasterization disabled.
2387 *
2388 * Also,
2389 *
2390 * pColorBlendState is a pointer to an instance of the
2391 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2392 * pipeline has rasterization disabled or if the subpass of the render
2393 * pass the pipeline is created against does not use any color
2394 * attachments.
2395 *
2396 * We leave the relevant registers stale when rasterization is disabled.
2397 */
2398 if (builder->rasterizer_discard)
2399 return;
2400
2401 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2402 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2403 builder->create_info->pMultisampleState;
2404 const VkPipelineColorBlendStateCreateInfo *blend_info =
2405 builder->use_color_attachments ? builder->create_info->pColorBlendState
2406 : &dummy_blend_info;
2407
2408 struct tu_cs blend_cs;
2409 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 18, &blend_cs);
2410
2411 uint32_t blend_enable_mask;
2412 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
2413 builder->color_attachment_formats,
2414 &blend_enable_mask);
2415
2416 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
2417 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
2418
2419 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SAMPLE_LOCATIONS)) {
2420 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2421 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2422 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2423
2424 if (sample_locations && sample_locations->sampleLocationsEnable)
2425 samp_loc = &sample_locations->sampleLocationsInfo;
2426
2427 tu6_emit_sample_locations(&blend_cs, samp_loc);
2428 }
2429
2430 tu6_emit_blend_control(&blend_cs, blend_enable_mask,
2431 builder->use_dual_src_blend, msaa_info);
2432
2433 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
2434 }
2435
2436 static void
2437 tu_pipeline_finish(struct tu_pipeline *pipeline,
2438 struct tu_device *dev,
2439 const VkAllocationCallbacks *alloc)
2440 {
2441 tu_cs_finish(&pipeline->cs);
2442
2443 if (pipeline->program.binary_bo.gem_handle)
2444 tu_bo_finish(dev, &pipeline->program.binary_bo);
2445 }
2446
2447 static VkResult
2448 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2449 struct tu_pipeline **pipeline)
2450 {
2451 VkResult result = tu_pipeline_create(builder->device, builder->layout,
2452 false, builder->alloc, pipeline);
2453 if (result != VK_SUCCESS)
2454 return result;
2455
2456 (*pipeline)->layout = builder->layout;
2457
2458 /* compile and upload shaders */
2459 result = tu_pipeline_builder_compile_shaders(builder);
2460 if (result == VK_SUCCESS)
2461 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
2462 if (result != VK_SUCCESS) {
2463 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
2464 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2465 *pipeline = VK_NULL_HANDLE;
2466
2467 return result;
2468 }
2469
2470 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2471 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2472 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2473 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2474 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2475 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2476 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2477 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2478 tu6_emit_load_state(*pipeline, false);
2479
2480 /* we should have reserved enough space upfront such that the CS never
2481 * grows
2482 */
2483 assert((*pipeline)->cs.bo_count == 1);
2484
2485 return VK_SUCCESS;
2486 }
2487
2488 static void
2489 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2490 {
2491 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2492 if (!builder->shaders[i])
2493 continue;
2494 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2495 }
2496 }
2497
2498 static void
2499 tu_pipeline_builder_init_graphics(
2500 struct tu_pipeline_builder *builder,
2501 struct tu_device *dev,
2502 struct tu_pipeline_cache *cache,
2503 const VkGraphicsPipelineCreateInfo *create_info,
2504 const VkAllocationCallbacks *alloc)
2505 {
2506 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2507
2508 *builder = (struct tu_pipeline_builder) {
2509 .device = dev,
2510 .cache = cache,
2511 .create_info = create_info,
2512 .alloc = alloc,
2513 .layout = layout,
2514 };
2515
2516 builder->rasterizer_discard =
2517 create_info->pRasterizationState->rasterizerDiscardEnable;
2518
2519 if (builder->rasterizer_discard) {
2520 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2521 } else {
2522 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2523
2524 const struct tu_render_pass *pass =
2525 tu_render_pass_from_handle(create_info->renderPass);
2526 const struct tu_subpass *subpass =
2527 &pass->subpasses[create_info->subpass];
2528
2529 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2530 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2531 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2532
2533 assert(subpass->color_count == 0 ||
2534 !create_info->pColorBlendState ||
2535 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2536 builder->color_attachment_count = subpass->color_count;
2537 for (uint32_t i = 0; i < subpass->color_count; i++) {
2538 const uint32_t a = subpass->color_attachments[i].attachment;
2539 if (a == VK_ATTACHMENT_UNUSED)
2540 continue;
2541
2542 builder->color_attachment_formats[i] = pass->attachments[a].format;
2543 builder->use_color_attachments = true;
2544 builder->render_components |= 0xf << (i * 4);
2545 }
2546
2547 if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
2548 builder->color_attachment_count++;
2549 builder->use_dual_src_blend = true;
2550 /* dual source blending has an extra fs output in the 2nd slot */
2551 if (subpass->color_attachments[0].attachment != VK_ATTACHMENT_UNUSED)
2552 builder->render_components |= 0xf << 4;
2553 }
2554 }
2555 }
2556
2557 static VkResult
2558 tu_graphics_pipeline_create(VkDevice device,
2559 VkPipelineCache pipelineCache,
2560 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2561 const VkAllocationCallbacks *pAllocator,
2562 VkPipeline *pPipeline)
2563 {
2564 TU_FROM_HANDLE(tu_device, dev, device);
2565 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2566
2567 struct tu_pipeline_builder builder;
2568 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2569 pCreateInfo, pAllocator);
2570
2571 struct tu_pipeline *pipeline = NULL;
2572 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2573 tu_pipeline_builder_finish(&builder);
2574
2575 if (result == VK_SUCCESS)
2576 *pPipeline = tu_pipeline_to_handle(pipeline);
2577 else
2578 *pPipeline = VK_NULL_HANDLE;
2579
2580 return result;
2581 }
2582
2583 VkResult
2584 tu_CreateGraphicsPipelines(VkDevice device,
2585 VkPipelineCache pipelineCache,
2586 uint32_t count,
2587 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2588 const VkAllocationCallbacks *pAllocator,
2589 VkPipeline *pPipelines)
2590 {
2591 VkResult final_result = VK_SUCCESS;
2592
2593 for (uint32_t i = 0; i < count; i++) {
2594 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2595 &pCreateInfos[i], pAllocator,
2596 &pPipelines[i]);
2597
2598 if (result != VK_SUCCESS)
2599 final_result = result;
2600 }
2601
2602 return final_result;
2603 }
2604
2605 static VkResult
2606 tu_compute_upload_shader(VkDevice device,
2607 struct tu_pipeline *pipeline,
2608 struct tu_shader *shader)
2609 {
2610 TU_FROM_HANDLE(tu_device, dev, device);
2611 struct tu_bo *bo = &pipeline->program.binary_bo;
2612 struct ir3_shader_variant *v = &shader->variants[0];
2613
2614 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2615 VkResult result =
2616 tu_bo_init_new(dev, bo, shader_size);
2617 if (result != VK_SUCCESS)
2618 return result;
2619
2620 result = tu_bo_map(dev, bo);
2621 if (result != VK_SUCCESS)
2622 return result;
2623
2624 memcpy(bo->map, shader->binary, shader_size);
2625
2626 return VK_SUCCESS;
2627 }
2628
2629
2630 static VkResult
2631 tu_compute_pipeline_create(VkDevice device,
2632 VkPipelineCache _cache,
2633 const VkComputePipelineCreateInfo *pCreateInfo,
2634 const VkAllocationCallbacks *pAllocator,
2635 VkPipeline *pPipeline)
2636 {
2637 TU_FROM_HANDLE(tu_device, dev, device);
2638 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2639 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2640 VkResult result;
2641
2642 struct tu_pipeline *pipeline;
2643
2644 *pPipeline = VK_NULL_HANDLE;
2645
2646 result = tu_pipeline_create(dev, layout, true, pAllocator, &pipeline);
2647 if (result != VK_SUCCESS)
2648 return result;
2649
2650 pipeline->layout = layout;
2651
2652 struct tu_shader_compile_options options;
2653 tu_shader_compile_options_init(&options, NULL);
2654
2655 struct tu_shader *shader =
2656 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2657 if (!shader) {
2658 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2659 goto fail;
2660 }
2661
2662 result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2663 if (result != VK_SUCCESS)
2664 goto fail;
2665
2666 struct ir3_shader_variant *v = &shader->variants[0];
2667
2668 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2669 shader, v);
2670
2671 result = tu_compute_upload_shader(device, pipeline, shader);
2672 if (result != VK_SUCCESS)
2673 goto fail;
2674
2675 for (int i = 0; i < 3; i++)
2676 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2677
2678 struct tu_cs prog_cs;
2679 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2680 tu6_emit_cs_config(&prog_cs, shader, v, pipeline->program.binary_bo.iova);
2681 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2682
2683 tu6_emit_load_state(pipeline, true);
2684
2685 *pPipeline = tu_pipeline_to_handle(pipeline);
2686 return VK_SUCCESS;
2687
2688 fail:
2689 if (shader)
2690 tu_shader_destroy(dev, shader, pAllocator);
2691
2692 tu_pipeline_finish(pipeline, dev, pAllocator);
2693 vk_free2(&dev->alloc, pAllocator, pipeline);
2694
2695 return result;
2696 }
2697
2698 VkResult
2699 tu_CreateComputePipelines(VkDevice device,
2700 VkPipelineCache pipelineCache,
2701 uint32_t count,
2702 const VkComputePipelineCreateInfo *pCreateInfos,
2703 const VkAllocationCallbacks *pAllocator,
2704 VkPipeline *pPipelines)
2705 {
2706 VkResult final_result = VK_SUCCESS;
2707
2708 for (uint32_t i = 0; i < count; i++) {
2709 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2710 &pCreateInfos[i],
2711 pAllocator, &pPipelines[i]);
2712 if (result != VK_SUCCESS)
2713 final_result = result;
2714 }
2715
2716 return final_result;
2717 }
2718
2719 void
2720 tu_DestroyPipeline(VkDevice _device,
2721 VkPipeline _pipeline,
2722 const VkAllocationCallbacks *pAllocator)
2723 {
2724 TU_FROM_HANDLE(tu_device, dev, _device);
2725 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2726
2727 if (!_pipeline)
2728 return;
2729
2730 tu_pipeline_finish(pipeline, dev, pAllocator);
2731 vk_free2(&dev->alloc, pAllocator, pipeline);
2732 }