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turnip: remove compute emit_border_color
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "main/menums.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34 #include "util/debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/u_atomic.h"
37 #include "vk_format.h"
38 #include "vk_util.h"
39
40 #include "tu_cs.h"
41
42 struct tu_pipeline_builder
43 {
44 struct tu_device *device;
45 struct tu_pipeline_cache *cache;
46 const VkAllocationCallbacks *alloc;
47 const VkGraphicsPipelineCreateInfo *create_info;
48
49 struct tu_shader *shaders[MESA_SHADER_STAGES];
50 uint32_t shader_offsets[MESA_SHADER_STAGES];
51 uint32_t binning_vs_offset;
52 uint32_t shader_total_size;
53
54 bool rasterizer_discard;
55 /* these states are affectd by rasterizer_discard */
56 VkSampleCountFlagBits samples;
57 bool use_depth_stencil_attachment;
58 bool use_color_attachments;
59 uint32_t color_attachment_count;
60 VkFormat color_attachment_formats[MAX_RTS];
61 };
62
63 static enum tu_dynamic_state_bits
64 tu_dynamic_state_bit(VkDynamicState state)
65 {
66 switch (state) {
67 case VK_DYNAMIC_STATE_VIEWPORT:
68 return TU_DYNAMIC_VIEWPORT;
69 case VK_DYNAMIC_STATE_SCISSOR:
70 return TU_DYNAMIC_SCISSOR;
71 case VK_DYNAMIC_STATE_LINE_WIDTH:
72 return TU_DYNAMIC_LINE_WIDTH;
73 case VK_DYNAMIC_STATE_DEPTH_BIAS:
74 return TU_DYNAMIC_DEPTH_BIAS;
75 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
76 return TU_DYNAMIC_BLEND_CONSTANTS;
77 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
78 return TU_DYNAMIC_DEPTH_BOUNDS;
79 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
80 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
81 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
82 return TU_DYNAMIC_STENCIL_WRITE_MASK;
83 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
84 return TU_DYNAMIC_STENCIL_REFERENCE;
85 default:
86 unreachable("invalid dynamic state");
87 return 0;
88 }
89 }
90
91 static gl_shader_stage
92 tu_shader_stage(VkShaderStageFlagBits stage)
93 {
94 switch (stage) {
95 case VK_SHADER_STAGE_VERTEX_BIT:
96 return MESA_SHADER_VERTEX;
97 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
98 return MESA_SHADER_TESS_CTRL;
99 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
100 return MESA_SHADER_TESS_EVAL;
101 case VK_SHADER_STAGE_GEOMETRY_BIT:
102 return MESA_SHADER_GEOMETRY;
103 case VK_SHADER_STAGE_FRAGMENT_BIT:
104 return MESA_SHADER_FRAGMENT;
105 case VK_SHADER_STAGE_COMPUTE_BIT:
106 return MESA_SHADER_COMPUTE;
107 default:
108 unreachable("invalid VkShaderStageFlagBits");
109 return MESA_SHADER_NONE;
110 }
111 }
112
113 static const VkVertexInputAttributeDescription *
114 tu_find_vertex_input_attribute(
115 const VkPipelineVertexInputStateCreateInfo *vi_info, uint32_t slot)
116 {
117 assert(slot >= VERT_ATTRIB_GENERIC0);
118 slot -= VERT_ATTRIB_GENERIC0;
119 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
120 if (vi_info->pVertexAttributeDescriptions[i].location == slot)
121 return &vi_info->pVertexAttributeDescriptions[i];
122 }
123 return NULL;
124 }
125
126 static const VkVertexInputBindingDescription *
127 tu_find_vertex_input_binding(
128 const VkPipelineVertexInputStateCreateInfo *vi_info,
129 const VkVertexInputAttributeDescription *vi_attr)
130 {
131 assert(vi_attr);
132 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
133 if (vi_info->pVertexBindingDescriptions[i].binding == vi_attr->binding)
134 return &vi_info->pVertexBindingDescriptions[i];
135 }
136 return NULL;
137 }
138
139 static bool
140 tu_logic_op_reads_dst(VkLogicOp op)
141 {
142 switch (op) {
143 case VK_LOGIC_OP_CLEAR:
144 case VK_LOGIC_OP_COPY:
145 case VK_LOGIC_OP_COPY_INVERTED:
146 case VK_LOGIC_OP_SET:
147 return false;
148 default:
149 return true;
150 }
151 }
152
153 static VkBlendFactor
154 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
155 {
156 /* treat dst alpha as 1.0 and avoid reading it */
157 switch (factor) {
158 case VK_BLEND_FACTOR_DST_ALPHA:
159 return VK_BLEND_FACTOR_ONE;
160 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
161 return VK_BLEND_FACTOR_ZERO;
162 default:
163 return factor;
164 }
165 }
166
167 static enum pc_di_primtype
168 tu6_primtype(VkPrimitiveTopology topology)
169 {
170 switch (topology) {
171 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
172 return DI_PT_POINTLIST;
173 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
174 return DI_PT_LINELIST;
175 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
176 return DI_PT_LINESTRIP;
177 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
178 return DI_PT_TRILIST;
179 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
180 return DI_PT_TRISTRIP;
181 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
182 return DI_PT_TRIFAN;
183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
184 return DI_PT_LINE_ADJ;
185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
186 return DI_PT_LINESTRIP_ADJ;
187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
188 return DI_PT_TRI_ADJ;
189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
190 return DI_PT_TRISTRIP_ADJ;
191 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
192 default:
193 unreachable("invalid primitive topology");
194 return DI_PT_NONE;
195 }
196 }
197
198 static enum adreno_compare_func
199 tu6_compare_func(VkCompareOp op)
200 {
201 switch (op) {
202 case VK_COMPARE_OP_NEVER:
203 return FUNC_NEVER;
204 case VK_COMPARE_OP_LESS:
205 return FUNC_LESS;
206 case VK_COMPARE_OP_EQUAL:
207 return FUNC_EQUAL;
208 case VK_COMPARE_OP_LESS_OR_EQUAL:
209 return FUNC_LEQUAL;
210 case VK_COMPARE_OP_GREATER:
211 return FUNC_GREATER;
212 case VK_COMPARE_OP_NOT_EQUAL:
213 return FUNC_NOTEQUAL;
214 case VK_COMPARE_OP_GREATER_OR_EQUAL:
215 return FUNC_GEQUAL;
216 case VK_COMPARE_OP_ALWAYS:
217 return FUNC_ALWAYS;
218 default:
219 unreachable("invalid VkCompareOp");
220 return FUNC_NEVER;
221 }
222 }
223
224 static enum adreno_stencil_op
225 tu6_stencil_op(VkStencilOp op)
226 {
227 switch (op) {
228 case VK_STENCIL_OP_KEEP:
229 return STENCIL_KEEP;
230 case VK_STENCIL_OP_ZERO:
231 return STENCIL_ZERO;
232 case VK_STENCIL_OP_REPLACE:
233 return STENCIL_REPLACE;
234 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
235 return STENCIL_INCR_CLAMP;
236 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
237 return STENCIL_DECR_CLAMP;
238 case VK_STENCIL_OP_INVERT:
239 return STENCIL_INVERT;
240 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
241 return STENCIL_INCR_WRAP;
242 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
243 return STENCIL_DECR_WRAP;
244 default:
245 unreachable("invalid VkStencilOp");
246 return STENCIL_KEEP;
247 }
248 }
249
250 static enum a3xx_rop_code
251 tu6_rop(VkLogicOp op)
252 {
253 switch (op) {
254 case VK_LOGIC_OP_CLEAR:
255 return ROP_CLEAR;
256 case VK_LOGIC_OP_AND:
257 return ROP_AND;
258 case VK_LOGIC_OP_AND_REVERSE:
259 return ROP_AND_REVERSE;
260 case VK_LOGIC_OP_COPY:
261 return ROP_COPY;
262 case VK_LOGIC_OP_AND_INVERTED:
263 return ROP_AND_INVERTED;
264 case VK_LOGIC_OP_NO_OP:
265 return ROP_NOOP;
266 case VK_LOGIC_OP_XOR:
267 return ROP_XOR;
268 case VK_LOGIC_OP_OR:
269 return ROP_OR;
270 case VK_LOGIC_OP_NOR:
271 return ROP_NOR;
272 case VK_LOGIC_OP_EQUIVALENT:
273 return ROP_EQUIV;
274 case VK_LOGIC_OP_INVERT:
275 return ROP_INVERT;
276 case VK_LOGIC_OP_OR_REVERSE:
277 return ROP_OR_REVERSE;
278 case VK_LOGIC_OP_COPY_INVERTED:
279 return ROP_COPY_INVERTED;
280 case VK_LOGIC_OP_OR_INVERTED:
281 return ROP_OR_INVERTED;
282 case VK_LOGIC_OP_NAND:
283 return ROP_NAND;
284 case VK_LOGIC_OP_SET:
285 return ROP_SET;
286 default:
287 unreachable("invalid VkLogicOp");
288 return ROP_NOOP;
289 }
290 }
291
292 static enum adreno_rb_blend_factor
293 tu6_blend_factor(VkBlendFactor factor)
294 {
295 switch (factor) {
296 case VK_BLEND_FACTOR_ZERO:
297 return FACTOR_ZERO;
298 case VK_BLEND_FACTOR_ONE:
299 return FACTOR_ONE;
300 case VK_BLEND_FACTOR_SRC_COLOR:
301 return FACTOR_SRC_COLOR;
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
303 return FACTOR_ONE_MINUS_SRC_COLOR;
304 case VK_BLEND_FACTOR_DST_COLOR:
305 return FACTOR_DST_COLOR;
306 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
307 return FACTOR_ONE_MINUS_DST_COLOR;
308 case VK_BLEND_FACTOR_SRC_ALPHA:
309 return FACTOR_SRC_ALPHA;
310 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
311 return FACTOR_ONE_MINUS_SRC_ALPHA;
312 case VK_BLEND_FACTOR_DST_ALPHA:
313 return FACTOR_DST_ALPHA;
314 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
315 return FACTOR_ONE_MINUS_DST_ALPHA;
316 case VK_BLEND_FACTOR_CONSTANT_COLOR:
317 return FACTOR_CONSTANT_COLOR;
318 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
319 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
320 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
321 return FACTOR_CONSTANT_ALPHA;
322 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
323 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
325 return FACTOR_SRC_ALPHA_SATURATE;
326 case VK_BLEND_FACTOR_SRC1_COLOR:
327 return FACTOR_SRC1_COLOR;
328 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
329 return FACTOR_ONE_MINUS_SRC1_COLOR;
330 case VK_BLEND_FACTOR_SRC1_ALPHA:
331 return FACTOR_SRC1_ALPHA;
332 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
333 return FACTOR_ONE_MINUS_SRC1_ALPHA;
334 default:
335 unreachable("invalid VkBlendFactor");
336 return FACTOR_ZERO;
337 }
338 }
339
340 static enum a3xx_rb_blend_opcode
341 tu6_blend_op(VkBlendOp op)
342 {
343 switch (op) {
344 case VK_BLEND_OP_ADD:
345 return BLEND_DST_PLUS_SRC;
346 case VK_BLEND_OP_SUBTRACT:
347 return BLEND_SRC_MINUS_DST;
348 case VK_BLEND_OP_REVERSE_SUBTRACT:
349 return BLEND_DST_MINUS_SRC;
350 case VK_BLEND_OP_MIN:
351 return BLEND_MIN_DST_SRC;
352 case VK_BLEND_OP_MAX:
353 return BLEND_MAX_DST_SRC;
354 default:
355 unreachable("invalid VkBlendOp");
356 return BLEND_DST_PLUS_SRC;
357 }
358 }
359
360 static void
361 tu6_emit_vs_config(struct tu_cs *cs, const struct ir3_shader_variant *vs)
362 {
363 uint32_t sp_vs_ctrl =
364 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
365 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
366 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
367 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
368 if (vs->need_pixlod)
369 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
370
371 uint32_t sp_vs_config = A6XX_SP_VS_CONFIG_NTEX(vs->num_samp) |
372 A6XX_SP_VS_CONFIG_NSAMP(vs->num_samp);
373 if (vs->instrlen)
374 sp_vs_config |= A6XX_SP_VS_CONFIG_ENABLED;
375
376 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
377 tu_cs_emit(cs, sp_vs_ctrl);
378
379 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
380 tu_cs_emit(cs, sp_vs_config);
381 tu_cs_emit(cs, vs->instrlen);
382
383 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
384 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
385 A6XX_HLSQ_VS_CNTL_ENABLED);
386 }
387
388 static void
389 tu6_emit_hs_config(struct tu_cs *cs, const struct ir3_shader_variant *hs)
390 {
391 uint32_t sp_hs_config = 0;
392 if (hs->instrlen)
393 sp_hs_config |= A6XX_SP_HS_CONFIG_ENABLED;
394
395 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
396 tu_cs_emit(cs, 0);
397
398 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
399 tu_cs_emit(cs, sp_hs_config);
400 tu_cs_emit(cs, hs->instrlen);
401
402 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
403 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
404 }
405
406 static void
407 tu6_emit_ds_config(struct tu_cs *cs, const struct ir3_shader_variant *ds)
408 {
409 uint32_t sp_ds_config = 0;
410 if (ds->instrlen)
411 sp_ds_config |= A6XX_SP_DS_CONFIG_ENABLED;
412
413 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
414 tu_cs_emit(cs, sp_ds_config);
415 tu_cs_emit(cs, ds->instrlen);
416
417 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
418 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
419 }
420
421 static void
422 tu6_emit_gs_config(struct tu_cs *cs, const struct ir3_shader_variant *gs)
423 {
424 uint32_t sp_gs_config = 0;
425 if (gs->instrlen)
426 sp_gs_config |= A6XX_SP_GS_CONFIG_ENABLED;
427
428 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
429 tu_cs_emit(cs, 0);
430
431 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
432 tu_cs_emit(cs, sp_gs_config);
433 tu_cs_emit(cs, gs->instrlen);
434
435 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
436 tu_cs_emit(cs, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
437 }
438
439 static void
440 tu6_emit_fs_config(struct tu_cs *cs, const struct ir3_shader_variant *fs)
441 {
442 uint32_t sp_fs_ctrl =
443 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
444 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
445 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
446 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
447 if (fs->total_in > 0 || fs->frag_coord)
448 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
449 if (fs->need_pixlod)
450 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
451
452 uint32_t sp_fs_config = A6XX_SP_FS_CONFIG_NTEX(fs->num_samp) |
453 A6XX_SP_FS_CONFIG_NSAMP(fs->num_samp) |
454 A6XX_SP_FS_CONFIG_NIBO(fs->image_mapping.num_ibo);
455 if (fs->instrlen)
456 sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
457
458 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A9A8, 1);
459 tu_cs_emit(cs, 0);
460
461 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_AB00, 1);
462 tu_cs_emit(cs, 0x5);
463
464 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
465 tu_cs_emit(cs, sp_fs_ctrl);
466
467 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
468 tu_cs_emit(cs, sp_fs_config);
469 tu_cs_emit(cs, fs->instrlen);
470
471 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
472 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
473 A6XX_HLSQ_FS_CNTL_ENABLED);
474
475 tu_cs_emit_pkt4(cs, REG_A6XX_SP_IBO_COUNT, 1);
476 tu_cs_emit(cs, fs->image_mapping.num_ibo);
477 }
478
479 static void
480 tu6_emit_cs_config(struct tu_cs *cs, const struct ir3_shader_variant *v)
481 {
482 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
483 tu_cs_emit(cs, 0xff);
484
485 unsigned constlen = align(v->constlen, 4);
486 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL, 1);
487 tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
488 A6XX_HLSQ_CS_CNTL_ENABLED);
489
490 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONFIG, 2);
491 tu_cs_emit(cs, A6XX_SP_CS_CONFIG_ENABLED |
492 A6XX_SP_CS_CONFIG_NIBO(v->image_mapping.num_ibo) |
493 A6XX_SP_CS_CONFIG_NTEX(v->num_samp) |
494 A6XX_SP_CS_CONFIG_NSAMP(v->num_samp) |
495 A6XX_SP_CS_CONFIG_NIBO(v->image_mapping.num_ibo));
496 tu_cs_emit(cs, v->instrlen);
497
498 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG0, 1);
499 tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
500 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v->info.max_reg + 1) |
501 A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
502 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
503 COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE));
504
505 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
506 tu_cs_emit(cs, 0x41);
507
508 uint32_t local_invocation_id =
509 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
510 uint32_t work_group_id =
511 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
512
513 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
514 tu_cs_emit(cs,
515 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
516 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
517 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
518 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
519 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
520
521 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_IBO_COUNT, 1);
522 tu_cs_emit(cs, v->image_mapping.num_ibo);
523 }
524
525 static void
526 tu6_emit_vs_system_values(struct tu_cs *cs,
527 const struct ir3_shader_variant *vs)
528 {
529 const uint32_t vertexid_regid =
530 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
531 const uint32_t instanceid_regid =
532 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
533
534 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
535 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
536 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
537 0xfcfc0000);
538 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
539 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
540 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
541 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_5 */
542 tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
543 }
544
545 static void
546 tu6_emit_vpc(struct tu_cs *cs,
547 const struct ir3_shader_variant *vs,
548 const struct ir3_shader_variant *fs,
549 bool binning_pass)
550 {
551 struct ir3_shader_linkage linkage = { 0 };
552 ir3_link_shaders(&linkage, vs, fs);
553
554 if (vs->shader->stream_output.num_outputs && !binning_pass)
555 tu_finishme("stream output");
556
557 BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
558 for (uint32_t i = 0; i < linkage.cnt; i++) {
559 const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
560 for (uint32_t j = 0; j < comp_count; j++)
561 BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
562 }
563
564 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
565 tu_cs_emit(cs, ~vpc_var_enables[0]);
566 tu_cs_emit(cs, ~vpc_var_enables[1]);
567 tu_cs_emit(cs, ~vpc_var_enables[2]);
568 tu_cs_emit(cs, ~vpc_var_enables[3]);
569
570 /* a6xx finds position/pointsize at the end */
571 const uint32_t position_regid =
572 ir3_find_output_regid(vs, VARYING_SLOT_POS);
573 const uint32_t pointsize_regid =
574 ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
575 uint32_t pointsize_loc = 0xff, position_loc = 0xff;
576 if (position_regid != regid(63, 0)) {
577 position_loc = linkage.max_loc;
578 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
579 }
580 if (pointsize_regid != regid(63, 0)) {
581 pointsize_loc = linkage.max_loc;
582 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
583 }
584
585 /* map vs outputs to VPC */
586 assert(linkage.cnt <= 32);
587 const uint32_t sp_vs_out_count = (linkage.cnt + 1) / 2;
588 const uint32_t sp_vs_vpc_dst_count = (linkage.cnt + 3) / 4;
589 uint32_t sp_vs_out[16];
590 uint32_t sp_vs_vpc_dst[8];
591 sp_vs_out[sp_vs_out_count - 1] = 0;
592 sp_vs_vpc_dst[sp_vs_vpc_dst_count - 1] = 0;
593 for (uint32_t i = 0; i < linkage.cnt; i++) {
594 ((uint16_t *) sp_vs_out)[i] =
595 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
596 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
597 ((uint8_t *) sp_vs_vpc_dst)[i] =
598 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
599 }
600
601 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count);
602 tu_cs_emit_array(cs, sp_vs_out, sp_vs_out_count);
603
604 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count);
605 tu_cs_emit_array(cs, sp_vs_vpc_dst, sp_vs_vpc_dst_count);
606
607 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
608 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
609 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
610 0xff00ff00);
611
612 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
613 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
614 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
615 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
616
617 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_SIV_CNTL, 1);
618 tu_cs_emit(cs, 0x0000ffff); /* XXX */
619
620 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
621 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
622
623 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
624 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
625 (vs->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
626 }
627
628 static int
629 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
630 uint32_t index,
631 uint8_t *interp_mode,
632 uint8_t *ps_repl_mode)
633 {
634 enum
635 {
636 INTERP_SMOOTH = 0,
637 INTERP_FLAT = 1,
638 INTERP_ZERO = 2,
639 INTERP_ONE = 3,
640 };
641 enum
642 {
643 PS_REPL_NONE = 0,
644 PS_REPL_S = 1,
645 PS_REPL_T = 2,
646 PS_REPL_ONE_MINUS_T = 3,
647 };
648
649 const uint32_t compmask = fs->inputs[index].compmask;
650
651 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
652 * fourth component occupy three consecutive varying slots
653 */
654 int shift = 0;
655 *interp_mode = 0;
656 *ps_repl_mode = 0;
657 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
658 if (compmask & 0x1) {
659 *ps_repl_mode |= PS_REPL_S << shift;
660 shift += 2;
661 }
662 if (compmask & 0x2) {
663 *ps_repl_mode |= PS_REPL_T << shift;
664 shift += 2;
665 }
666 if (compmask & 0x4) {
667 *interp_mode |= INTERP_ZERO << shift;
668 shift += 2;
669 }
670 if (compmask & 0x8) {
671 *interp_mode |= INTERP_ONE << 6;
672 shift += 2;
673 }
674 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
675 fs->inputs[index].rasterflat) {
676 for (int i = 0; i < 4; i++) {
677 if (compmask & (1 << i)) {
678 *interp_mode |= INTERP_FLAT << shift;
679 shift += 2;
680 }
681 }
682 }
683
684 return shift;
685 }
686
687 static void
688 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
689 const struct ir3_shader_variant *fs,
690 bool binning_pass)
691 {
692 uint32_t interp_modes[8] = { 0 };
693 uint32_t ps_repl_modes[8] = { 0 };
694
695 if (!binning_pass) {
696 for (int i = -1;
697 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
698
699 /* get the mode for input i */
700 uint8_t interp_mode;
701 uint8_t ps_repl_mode;
702 const int bits =
703 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
704
705 /* OR the mode into the array */
706 const uint32_t inloc = fs->inputs[i].inloc * 2;
707 uint32_t n = inloc / 32;
708 uint32_t shift = inloc % 32;
709 interp_modes[n] |= interp_mode << shift;
710 ps_repl_modes[n] |= ps_repl_mode << shift;
711 if (shift + bits > 32) {
712 n++;
713 shift = 32 - shift;
714
715 interp_modes[n] |= interp_mode >> shift;
716 ps_repl_modes[n] |= ps_repl_mode >> shift;
717 }
718 }
719 }
720
721 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
722 tu_cs_emit_array(cs, interp_modes, 8);
723
724 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
725 tu_cs_emit_array(cs, ps_repl_modes, 8);
726 }
727
728 static void
729 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
730 {
731 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
732 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
733 uint32_t smask_in_regid;
734
735 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
736 bool enable_varyings = fs->total_in > 0;
737
738 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
739 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
740 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
741 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
742 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
743 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
744 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
745 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
746 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SIZE);
747
748 if (fs->num_sampler_prefetch > 0) {
749 assert(VALIDREG(ij_pix_regid));
750 /* also, it seems like ij_pix is *required* to be r0.x */
751 assert(ij_pix_regid == regid(0, 0));
752 }
753
754 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
755 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
756 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
757 0x7000); // XXX);
758 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
759 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
760 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
761 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
762 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
763 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
764 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
765 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
766 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
767 }
768
769 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
770 tu_cs_emit(cs, 0x7);
771 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
772 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
773 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
774 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
775 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
776 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
777 0xfc00fc00);
778 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
779 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
780 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
781 0x0000fc00);
782 tu_cs_emit(cs, 0xfc);
783
784 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
785 tu_cs_emit(cs, enable_varyings ? 3 : 1);
786
787 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A982, 1);
788 tu_cs_emit(cs, 0); /* XXX */
789
790 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
791 tu_cs_emit(cs, 0xff); /* XXX */
792
793 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
794 tu_cs_emit(cs,
795 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
796 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
797 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
798 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
799 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
800 COND(fs->frag_coord,
801 A6XX_GRAS_CNTL_SIZE |
802 A6XX_GRAS_CNTL_XCOORD |
803 A6XX_GRAS_CNTL_YCOORD |
804 A6XX_GRAS_CNTL_ZCOORD |
805 A6XX_GRAS_CNTL_WCOORD) |
806 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
807
808 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
809 tu_cs_emit(cs,
810 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
811 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
812 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
813 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
814 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
815 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
816 COND(fs->frag_coord,
817 A6XX_RB_RENDER_CONTROL0_SIZE |
818 A6XX_RB_RENDER_CONTROL0_XCOORD |
819 A6XX_RB_RENDER_CONTROL0_YCOORD |
820 A6XX_RB_RENDER_CONTROL0_ZCOORD |
821 A6XX_RB_RENDER_CONTROL0_WCOORD) |
822 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
823 tu_cs_emit(cs,
824 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
825 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
826 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
827 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
828 }
829
830 static void
831 tu6_emit_fs_outputs(struct tu_cs *cs,
832 const struct ir3_shader_variant *fs,
833 uint32_t mrt_count)
834 {
835 uint32_t smask_regid, posz_regid;
836
837 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
838 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
839
840 uint32_t fragdata_regid[8];
841 if (fs->color0_mrt) {
842 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
843 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
844 fragdata_regid[i] = fragdata_regid[0];
845 } else {
846 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
847 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
848 }
849
850 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
851 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
852 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
853 0xfc000000);
854 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
855
856 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
857 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
858 // TODO we could have a mix of half and full precision outputs,
859 // we really need to figure out half-precision from IR3_REG_HALF
860 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
861 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
862 }
863
864 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
865 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
866 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
867 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
868
869 uint32_t gras_su_depth_plane_cntl = 0;
870 uint32_t rb_depth_plane_cntl = 0;
871 if (fs->no_earlyz | fs->writes_pos) {
872 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
873 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
874 }
875
876 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
877 tu_cs_emit(cs, gras_su_depth_plane_cntl);
878
879 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
880 tu_cs_emit(cs, rb_depth_plane_cntl);
881 }
882
883 static void
884 tu6_emit_shader_object(struct tu_cs *cs,
885 gl_shader_stage stage,
886 const struct ir3_shader_variant *variant,
887 const struct tu_bo *binary_bo,
888 uint32_t binary_offset)
889 {
890 uint16_t reg;
891 uint8_t opcode;
892 enum a6xx_state_block sb;
893 switch (stage) {
894 case MESA_SHADER_VERTEX:
895 reg = REG_A6XX_SP_VS_OBJ_START_LO;
896 opcode = CP_LOAD_STATE6_GEOM;
897 sb = SB6_VS_SHADER;
898 break;
899 case MESA_SHADER_TESS_CTRL:
900 reg = REG_A6XX_SP_HS_OBJ_START_LO;
901 opcode = CP_LOAD_STATE6_GEOM;
902 sb = SB6_HS_SHADER;
903 break;
904 case MESA_SHADER_TESS_EVAL:
905 reg = REG_A6XX_SP_DS_OBJ_START_LO;
906 opcode = CP_LOAD_STATE6_GEOM;
907 sb = SB6_DS_SHADER;
908 break;
909 case MESA_SHADER_GEOMETRY:
910 reg = REG_A6XX_SP_GS_OBJ_START_LO;
911 opcode = CP_LOAD_STATE6_GEOM;
912 sb = SB6_GS_SHADER;
913 break;
914 case MESA_SHADER_FRAGMENT:
915 reg = REG_A6XX_SP_FS_OBJ_START_LO;
916 opcode = CP_LOAD_STATE6_FRAG;
917 sb = SB6_FS_SHADER;
918 break;
919 case MESA_SHADER_COMPUTE:
920 reg = REG_A6XX_SP_CS_OBJ_START_LO;
921 opcode = CP_LOAD_STATE6_FRAG;
922 sb = SB6_CS_SHADER;
923 break;
924 default:
925 unreachable("invalid gl_shader_stage");
926 opcode = CP_LOAD_STATE6_GEOM;
927 sb = SB6_VS_SHADER;
928 break;
929 }
930
931 if (!variant->instrlen) {
932 tu_cs_emit_pkt4(cs, reg, 2);
933 tu_cs_emit_qw(cs, 0);
934 return;
935 }
936
937 assert(variant->type == stage);
938
939 const uint64_t binary_iova = binary_bo->iova + binary_offset;
940 assert((binary_iova & 0x3) == 0);
941
942 tu_cs_emit_pkt4(cs, reg, 2);
943 tu_cs_emit_qw(cs, binary_iova);
944
945 /* always indirect */
946 const bool indirect = true;
947 if (indirect) {
948 tu_cs_emit_pkt7(cs, opcode, 3);
949 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
950 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
951 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
952 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
953 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
954 tu_cs_emit_qw(cs, binary_iova);
955 } else {
956 const void *binary = binary_bo->map + binary_offset;
957
958 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
959 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
960 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
961 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
962 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
963 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
964 tu_cs_emit_qw(cs, 0);
965 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
966 }
967 }
968
969 static void
970 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
971 uint32_t opcode, enum a6xx_state_block block)
972 {
973 /* dummy variant */
974 if (!v->shader)
975 return;
976
977 const struct ir3_const_state *const_state = &v->shader->const_state;
978 uint32_t base = const_state->offsets.immediate;
979 int size = const_state->immediates_count;
980
981 /* truncate size to avoid writing constants that shader
982 * does not use:
983 */
984 size = MIN2(size + base, v->constlen) - base;
985
986 if (size <= 0)
987 return;
988
989 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
990 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
991 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
992 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
993 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
994 CP_LOAD_STATE6_0_NUM_UNIT(size));
995 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
996 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
997
998 for (unsigned i = 0; i < size; i++) {
999 tu_cs_emit(cs, const_state->immediates[i].val[0]);
1000 tu_cs_emit(cs, const_state->immediates[i].val[1]);
1001 tu_cs_emit(cs, const_state->immediates[i].val[2]);
1002 tu_cs_emit(cs, const_state->immediates[i].val[3]);
1003 }
1004 }
1005
1006 static void
1007 tu6_emit_program(struct tu_cs *cs,
1008 const struct tu_pipeline_builder *builder,
1009 const struct tu_bo *binary_bo,
1010 bool binning_pass)
1011 {
1012 static const struct ir3_shader_variant dummy_variant = {
1013 .type = MESA_SHADER_NONE
1014 };
1015 assert(builder->shaders[MESA_SHADER_VERTEX]);
1016 const struct ir3_shader_variant *vs =
1017 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
1018 const struct ir3_shader_variant *hs =
1019 builder->shaders[MESA_SHADER_TESS_CTRL]
1020 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
1021 : &dummy_variant;
1022 const struct ir3_shader_variant *ds =
1023 builder->shaders[MESA_SHADER_TESS_EVAL]
1024 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
1025 : &dummy_variant;
1026 const struct ir3_shader_variant *gs =
1027 builder->shaders[MESA_SHADER_GEOMETRY]
1028 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
1029 : &dummy_variant;
1030 const struct ir3_shader_variant *fs =
1031 builder->shaders[MESA_SHADER_FRAGMENT]
1032 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
1033 : &dummy_variant;
1034
1035 if (binning_pass) {
1036 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1037 fs = &dummy_variant;
1038 }
1039
1040 tu6_emit_vs_config(cs, vs);
1041 tu6_emit_hs_config(cs, hs);
1042 tu6_emit_ds_config(cs, ds);
1043 tu6_emit_gs_config(cs, gs);
1044 tu6_emit_fs_config(cs, fs);
1045
1046 tu6_emit_vs_system_values(cs, vs);
1047 tu6_emit_vpc(cs, vs, fs, binning_pass);
1048 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1049 tu6_emit_fs_inputs(cs, fs);
1050 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
1051
1052 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1053 binning_pass ? builder->binning_vs_offset : builder->shader_offsets[MESA_SHADER_VERTEX]);
1054
1055 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1056 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1057
1058 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1059 if (!binning_pass)
1060 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1061 }
1062
1063 static void
1064 tu6_emit_vertex_input(struct tu_cs *cs,
1065 const struct ir3_shader_variant *vs,
1066 const VkPipelineVertexInputStateCreateInfo *vi_info,
1067 uint8_t bindings[MAX_VERTEX_ATTRIBS],
1068 uint16_t strides[MAX_VERTEX_ATTRIBS],
1069 uint16_t offsets[MAX_VERTEX_ATTRIBS],
1070 uint32_t *count)
1071 {
1072 uint32_t vfd_decode_idx = 0;
1073
1074 for (uint32_t i = 0; i < vs->inputs_count; i++) {
1075 if (vs->inputs[i].sysval || !vs->inputs[i].compmask)
1076 continue;
1077
1078 const VkVertexInputAttributeDescription *vi_attr =
1079 tu_find_vertex_input_attribute(vi_info, vs->inputs[i].slot);
1080 const VkVertexInputBindingDescription *vi_binding =
1081 tu_find_vertex_input_binding(vi_info, vi_attr);
1082 assert(vi_attr && vi_binding);
1083
1084 const struct tu_native_format *format =
1085 tu6_get_native_format(vi_attr->format);
1086 assert(format && format->vtx >= 0);
1087
1088 uint32_t vfd_decode = A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx) |
1089 A6XX_VFD_DECODE_INSTR_FORMAT(format->vtx) |
1090 A6XX_VFD_DECODE_INSTR_SWAP(format->swap) |
1091 A6XX_VFD_DECODE_INSTR_UNK30;
1092 if (vi_binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1093 vfd_decode |= A6XX_VFD_DECODE_INSTR_INSTANCED;
1094 if (!vk_format_is_int(vi_attr->format))
1095 vfd_decode |= A6XX_VFD_DECODE_INSTR_FLOAT;
1096
1097 const uint32_t vfd_decode_step_rate = 1;
1098
1099 const uint32_t vfd_dest_cntl =
1100 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
1101 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid);
1102
1103 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DECODE(vfd_decode_idx), 2);
1104 tu_cs_emit(cs, vfd_decode);
1105 tu_cs_emit(cs, vfd_decode_step_rate);
1106
1107 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx), 1);
1108 tu_cs_emit(cs, vfd_dest_cntl);
1109
1110 bindings[vfd_decode_idx] = vi_binding->binding;
1111 strides[vfd_decode_idx] = vi_binding->stride;
1112 offsets[vfd_decode_idx] = vi_attr->offset;
1113
1114 vfd_decode_idx++;
1115 assert(vfd_decode_idx <= MAX_VERTEX_ATTRIBS);
1116 }
1117
1118 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_0, 1);
1119 tu_cs_emit(
1120 cs, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx) | (vfd_decode_idx << 8));
1121
1122 *count = vfd_decode_idx;
1123 }
1124
1125 static uint32_t
1126 tu6_guardband_adj(uint32_t v)
1127 {
1128 if (v > 256)
1129 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1130 else
1131 return 511;
1132 }
1133
1134 void
1135 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1136 {
1137 float offsets[3];
1138 float scales[3];
1139 scales[0] = viewport->width / 2.0f;
1140 scales[1] = viewport->height / 2.0f;
1141 scales[2] = viewport->maxDepth - viewport->minDepth;
1142 offsets[0] = viewport->x + scales[0];
1143 offsets[1] = viewport->y + scales[1];
1144 offsets[2] = viewport->minDepth;
1145
1146 VkOffset2D min;
1147 VkOffset2D max;
1148 min.x = (int32_t) viewport->x;
1149 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1150 if (viewport->height >= 0.0f) {
1151 min.y = (int32_t) viewport->y;
1152 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1153 } else {
1154 min.y = (int32_t)(viewport->y + viewport->height);
1155 max.y = (int32_t) ceilf(viewport->y);
1156 }
1157 /* the spec allows viewport->height to be 0.0f */
1158 if (min.y == max.y)
1159 max.y++;
1160 assert(min.x >= 0 && min.x < max.x);
1161 assert(min.y >= 0 && min.y < max.y);
1162
1163 VkExtent2D guardband_adj;
1164 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1165 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1166
1167 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1168 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]));
1169 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]));
1170 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]));
1171 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]));
1172 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]));
1173 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]));
1174
1175 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1176 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1177 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1178 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1179 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1180
1181 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1182 tu_cs_emit(cs,
1183 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1184 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1185 }
1186
1187 void
1188 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1189 {
1190 const VkOffset2D min = scissor->offset;
1191 const VkOffset2D max = {
1192 scissor->offset.x + scissor->extent.width,
1193 scissor->offset.y + scissor->extent.height,
1194 };
1195
1196 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1197 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1198 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1199 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1200 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1201 }
1202
1203 static void
1204 tu6_emit_gras_unknowns(struct tu_cs *cs)
1205 {
1206 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8000, 1);
1207 tu_cs_emit(cs, 0x80);
1208 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1209 tu_cs_emit(cs, 0x0);
1210 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LAYER_CNTL, 1);
1211 tu_cs_emit(cs, 0x0);
1212 }
1213
1214 static void
1215 tu6_emit_point_size(struct tu_cs *cs)
1216 {
1217 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1218 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1219 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1220 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f));
1221 }
1222
1223 static uint32_t
1224 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1225 VkSampleCountFlagBits samples)
1226 {
1227 uint32_t gras_su_cntl = 0;
1228
1229 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1230 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1231 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1232 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1233
1234 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1235 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1236
1237 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1238
1239 if (rast_info->depthBiasEnable)
1240 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1241
1242 if (samples > VK_SAMPLE_COUNT_1_BIT)
1243 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1244
1245 return gras_su_cntl;
1246 }
1247
1248 void
1249 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1250 uint32_t gras_su_cntl,
1251 float line_width)
1252 {
1253 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1254 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1255
1256 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1257 tu_cs_emit(cs, gras_su_cntl);
1258 }
1259
1260 void
1261 tu6_emit_depth_bias(struct tu_cs *cs,
1262 float constant_factor,
1263 float clamp,
1264 float slope_factor)
1265 {
1266 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1267 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor));
1268 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor));
1269 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp));
1270 }
1271
1272 static void
1273 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1274 {
1275 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1276 tu_cs_emit(cs, 0);
1277 }
1278
1279 static void
1280 tu6_emit_depth_control(struct tu_cs *cs,
1281 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1282 {
1283 assert(!ds_info->depthBoundsTestEnable);
1284
1285 uint32_t rb_depth_cntl = 0;
1286 if (ds_info->depthTestEnable) {
1287 rb_depth_cntl |=
1288 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1289 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1290 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1291
1292 if (ds_info->depthWriteEnable)
1293 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1294 }
1295
1296 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1297 tu_cs_emit(cs, rb_depth_cntl);
1298 }
1299
1300 static void
1301 tu6_emit_stencil_control(struct tu_cs *cs,
1302 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1303 {
1304 uint32_t rb_stencil_control = 0;
1305 if (ds_info->stencilTestEnable) {
1306 const VkStencilOpState *front = &ds_info->front;
1307 const VkStencilOpState *back = &ds_info->back;
1308 rb_stencil_control |=
1309 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1310 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1311 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1312 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1313 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1314 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1315 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1316 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1317 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1318 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1319 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1320 }
1321
1322 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1323 tu_cs_emit(cs, rb_stencil_control);
1324 }
1325
1326 void
1327 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1328 {
1329 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1330 tu_cs_emit(
1331 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1332 }
1333
1334 void
1335 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1336 {
1337 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1338 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1339 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1340 }
1341
1342 void
1343 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1344 {
1345 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1346 tu_cs_emit(cs,
1347 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1348 }
1349
1350 static uint32_t
1351 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1352 bool has_alpha)
1353 {
1354 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1355 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1356 has_alpha ? att->srcColorBlendFactor
1357 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1358 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1359 has_alpha ? att->dstColorBlendFactor
1360 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1361 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1362 const enum adreno_rb_blend_factor src_alpha_factor =
1363 tu6_blend_factor(att->srcAlphaBlendFactor);
1364 const enum adreno_rb_blend_factor dst_alpha_factor =
1365 tu6_blend_factor(att->dstAlphaBlendFactor);
1366
1367 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1368 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1369 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1370 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1371 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1372 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1373 }
1374
1375 static uint32_t
1376 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1377 uint32_t rb_mrt_control_rop,
1378 bool is_int,
1379 bool has_alpha)
1380 {
1381 uint32_t rb_mrt_control =
1382 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1383
1384 /* ignore blending and logic op for integer attachments */
1385 if (is_int) {
1386 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1387 return rb_mrt_control;
1388 }
1389
1390 rb_mrt_control |= rb_mrt_control_rop;
1391
1392 if (att->blendEnable) {
1393 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1394
1395 if (has_alpha)
1396 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1397 }
1398
1399 return rb_mrt_control;
1400 }
1401
1402 static void
1403 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1404 const VkPipelineColorBlendStateCreateInfo *blend_info,
1405 const VkFormat attachment_formats[MAX_RTS],
1406 uint32_t *blend_enable_mask)
1407 {
1408 *blend_enable_mask = 0;
1409
1410 bool rop_reads_dst = false;
1411 uint32_t rb_mrt_control_rop = 0;
1412 if (blend_info->logicOpEnable) {
1413 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1414 rb_mrt_control_rop =
1415 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1416 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1417 }
1418
1419 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1420 const VkPipelineColorBlendAttachmentState *att =
1421 &blend_info->pAttachments[i];
1422 const VkFormat format = attachment_formats[i];
1423
1424 uint32_t rb_mrt_control = 0;
1425 uint32_t rb_mrt_blend_control = 0;
1426 if (format != VK_FORMAT_UNDEFINED) {
1427 const bool is_int = vk_format_is_int(format);
1428 const bool has_alpha = vk_format_has_alpha(format);
1429
1430 rb_mrt_control =
1431 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1432 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1433
1434 if (att->blendEnable || rop_reads_dst)
1435 *blend_enable_mask |= 1 << i;
1436 }
1437
1438 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1439 tu_cs_emit(cs, rb_mrt_control);
1440 tu_cs_emit(cs, rb_mrt_blend_control);
1441 }
1442
1443 for (uint32_t i = blend_info->attachmentCount; i < MAX_RTS; i++) {
1444 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1445 tu_cs_emit(cs, 0);
1446 tu_cs_emit(cs, 0);
1447 }
1448 }
1449
1450 static void
1451 tu6_emit_blend_control(struct tu_cs *cs,
1452 uint32_t blend_enable_mask,
1453 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1454 {
1455 assert(!msaa_info->sampleShadingEnable);
1456 assert(!msaa_info->alphaToOneEnable);
1457
1458 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
1459 if (blend_enable_mask)
1460 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
1461 if (msaa_info->alphaToCoverageEnable)
1462 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
1463
1464 const uint32_t sample_mask =
1465 msaa_info->pSampleMask ? *msaa_info->pSampleMask
1466 : ((1 << msaa_info->rasterizationSamples) - 1);
1467
1468 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1469 uint32_t rb_blend_cntl =
1470 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
1471 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
1472 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
1473 if (msaa_info->alphaToCoverageEnable)
1474 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
1475
1476 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
1477 tu_cs_emit(cs, sp_blend_cntl);
1478
1479 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
1480 tu_cs_emit(cs, rb_blend_cntl);
1481 }
1482
1483 void
1484 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
1485 {
1486 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
1487 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
1488 }
1489
1490 static VkResult
1491 tu_pipeline_create(struct tu_device *dev,
1492 const VkAllocationCallbacks *pAllocator,
1493 struct tu_pipeline **out_pipeline)
1494 {
1495 struct tu_pipeline *pipeline =
1496 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
1497 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1498 if (!pipeline)
1499 return VK_ERROR_OUT_OF_HOST_MEMORY;
1500
1501 tu_cs_init(&pipeline->cs, TU_CS_MODE_SUB_STREAM, 2048);
1502
1503 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1504 VkResult result = tu_cs_reserve_space(dev, &pipeline->cs, 2048);
1505 if (result != VK_SUCCESS) {
1506 vk_free2(&dev->alloc, pAllocator, pipeline);
1507 return result;
1508 }
1509
1510 *out_pipeline = pipeline;
1511
1512 return VK_SUCCESS;
1513 }
1514
1515 static VkResult
1516 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1517 {
1518 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1519 NULL
1520 };
1521 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1522 gl_shader_stage stage =
1523 tu_shader_stage(builder->create_info->pStages[i].stage);
1524 stage_infos[stage] = &builder->create_info->pStages[i];
1525 }
1526
1527 struct tu_shader_compile_options options;
1528 tu_shader_compile_options_init(&options, builder->create_info);
1529
1530 /* compile shaders in reverse order */
1531 struct tu_shader *next_stage_shader = NULL;
1532 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1533 stage > MESA_SHADER_NONE; stage--) {
1534 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1535 if (!stage_info)
1536 continue;
1537
1538 struct tu_shader *shader =
1539 tu_shader_create(builder->device, stage, stage_info, builder->alloc);
1540 if (!shader)
1541 return VK_ERROR_OUT_OF_HOST_MEMORY;
1542
1543 VkResult result =
1544 tu_shader_compile(builder->device, shader, next_stage_shader,
1545 &options, builder->alloc);
1546 if (result != VK_SUCCESS)
1547 return result;
1548
1549 builder->shaders[stage] = shader;
1550 builder->shader_offsets[stage] = builder->shader_total_size;
1551 builder->shader_total_size +=
1552 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
1553
1554 next_stage_shader = shader;
1555 }
1556
1557 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1558 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1559 builder->binning_vs_offset = builder->shader_total_size;
1560 builder->shader_total_size +=
1561 sizeof(uint32_t) * vs->variants[1].info.sizedwords;
1562 }
1563
1564 return VK_SUCCESS;
1565 }
1566
1567 static VkResult
1568 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
1569 struct tu_pipeline *pipeline)
1570 {
1571 struct tu_bo *bo = &pipeline->program.binary_bo;
1572
1573 VkResult result =
1574 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
1575 if (result != VK_SUCCESS)
1576 return result;
1577
1578 result = tu_bo_map(builder->device, bo);
1579 if (result != VK_SUCCESS)
1580 return result;
1581
1582 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1583 const struct tu_shader *shader = builder->shaders[i];
1584 if (!shader)
1585 continue;
1586
1587 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
1588 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
1589 }
1590
1591 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1592 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1593 memcpy(bo->map + builder->binning_vs_offset, vs->binning_binary,
1594 sizeof(uint32_t) * vs->variants[1].info.sizedwords);
1595 }
1596
1597 return VK_SUCCESS;
1598 }
1599
1600 static void
1601 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
1602 struct tu_pipeline *pipeline)
1603 {
1604 const VkPipelineDynamicStateCreateInfo *dynamic_info =
1605 builder->create_info->pDynamicState;
1606
1607 if (!dynamic_info)
1608 return;
1609
1610 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
1611 pipeline->dynamic_state.mask |=
1612 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
1613 }
1614 }
1615
1616 static void
1617 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
1618 struct tu_pipeline *pipeline)
1619 {
1620 struct tu_cs prog_cs;
1621 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1622 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false);
1623 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1624
1625 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1626 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true);
1627 pipeline->program.binning_state_ib =
1628 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1629
1630 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1631 if (!builder->shaders[i])
1632 continue;
1633
1634 struct tu_program_descriptor_linkage *link = &pipeline->program.link[i];
1635 struct ir3_shader *shader = builder->shaders[i]->variants[0].shader;
1636
1637 link->ubo_state = shader->ubo_state;
1638 link->const_state = shader->const_state;
1639 link->constlen = builder->shaders[i]->variants[0].constlen;
1640 link->texture_map = builder->shaders[i]->texture_map;
1641 link->sampler_map = builder->shaders[i]->sampler_map;
1642 link->ubo_map = builder->shaders[i]->ubo_map;
1643 link->ssbo_map = builder->shaders[i]->ssbo_map;
1644 link->image_mapping = builder->shaders[i]->variants[0].image_mapping;
1645 }
1646 }
1647
1648 static void
1649 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
1650 struct tu_pipeline *pipeline)
1651 {
1652 const VkPipelineVertexInputStateCreateInfo *vi_info =
1653 builder->create_info->pVertexInputState;
1654 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1655
1656 struct tu_cs vi_cs;
1657 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1658 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1659 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
1660 pipeline->vi.bindings, pipeline->vi.strides,
1661 pipeline->vi.offsets, &pipeline->vi.count);
1662 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1663
1664 if (vs->has_binning_pass) {
1665 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1666 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1667 tu6_emit_vertex_input(
1668 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
1669 pipeline->vi.binning_strides, pipeline->vi.binning_offsets,
1670 &pipeline->vi.binning_count);
1671 pipeline->vi.binning_state_ib =
1672 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1673 }
1674 }
1675
1676 static void
1677 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
1678 struct tu_pipeline *pipeline)
1679 {
1680 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1681 builder->create_info->pInputAssemblyState;
1682
1683 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
1684 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
1685 }
1686
1687 static void
1688 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
1689 struct tu_pipeline *pipeline)
1690 {
1691 /* The spec says:
1692 *
1693 * pViewportState is a pointer to an instance of the
1694 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
1695 * pipeline has rasterization disabled."
1696 *
1697 * We leave the relevant registers stale in that case.
1698 */
1699 if (builder->rasterizer_discard)
1700 return;
1701
1702 const VkPipelineViewportStateCreateInfo *vp_info =
1703 builder->create_info->pViewportState;
1704
1705 struct tu_cs vp_cs;
1706 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 15, &vp_cs);
1707
1708 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
1709 assert(vp_info->viewportCount == 1);
1710 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
1711 }
1712
1713 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
1714 assert(vp_info->scissorCount == 1);
1715 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
1716 }
1717
1718 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
1719 }
1720
1721 static void
1722 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
1723 struct tu_pipeline *pipeline)
1724 {
1725 const VkPipelineRasterizationStateCreateInfo *rast_info =
1726 builder->create_info->pRasterizationState;
1727
1728 assert(!rast_info->depthClampEnable);
1729 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
1730
1731 struct tu_cs rast_cs;
1732 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 20, &rast_cs);
1733
1734 /* move to hw ctx init? */
1735 tu6_emit_gras_unknowns(&rast_cs);
1736 tu6_emit_point_size(&rast_cs);
1737
1738 const uint32_t gras_su_cntl =
1739 tu6_gras_su_cntl(rast_info, builder->samples);
1740
1741 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
1742 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
1743
1744 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
1745 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
1746 rast_info->depthBiasClamp,
1747 rast_info->depthBiasSlopeFactor);
1748 }
1749
1750 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
1751
1752 pipeline->rast.gras_su_cntl = gras_su_cntl;
1753 }
1754
1755 static void
1756 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
1757 struct tu_pipeline *pipeline)
1758 {
1759 /* The spec says:
1760 *
1761 * pDepthStencilState is a pointer to an instance of the
1762 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1763 * the pipeline has rasterization disabled or if the subpass of the
1764 * render pass the pipeline is created against does not use a
1765 * depth/stencil attachment.
1766 *
1767 * We disable both depth and stenil tests in those cases.
1768 */
1769 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
1770 const VkPipelineDepthStencilStateCreateInfo *ds_info =
1771 builder->use_depth_stencil_attachment
1772 ? builder->create_info->pDepthStencilState
1773 : &dummy_ds_info;
1774
1775 struct tu_cs ds_cs;
1776 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 12, &ds_cs);
1777
1778 /* move to hw ctx init? */
1779 tu6_emit_alpha_control_disable(&ds_cs);
1780
1781 tu6_emit_depth_control(&ds_cs, ds_info);
1782 tu6_emit_stencil_control(&ds_cs, ds_info);
1783
1784 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
1785 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
1786 ds_info->back.compareMask);
1787 }
1788 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
1789 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
1790 ds_info->back.writeMask);
1791 }
1792 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
1793 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
1794 ds_info->back.reference);
1795 }
1796
1797 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
1798 }
1799
1800 static void
1801 tu_pipeline_builder_parse_multisample_and_color_blend(
1802 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
1803 {
1804 /* The spec says:
1805 *
1806 * pMultisampleState is a pointer to an instance of the
1807 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1808 * has rasterization disabled.
1809 *
1810 * Also,
1811 *
1812 * pColorBlendState is a pointer to an instance of the
1813 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1814 * pipeline has rasterization disabled or if the subpass of the render
1815 * pass the pipeline is created against does not use any color
1816 * attachments.
1817 *
1818 * We leave the relevant registers stale when rasterization is disabled.
1819 */
1820 if (builder->rasterizer_discard)
1821 return;
1822
1823 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
1824 const VkPipelineMultisampleStateCreateInfo *msaa_info =
1825 builder->create_info->pMultisampleState;
1826 const VkPipelineColorBlendStateCreateInfo *blend_info =
1827 builder->use_color_attachments ? builder->create_info->pColorBlendState
1828 : &dummy_blend_info;
1829
1830 struct tu_cs blend_cs;
1831 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, MAX_RTS * 3 + 9,
1832 &blend_cs);
1833
1834 uint32_t blend_enable_mask;
1835 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
1836 builder->color_attachment_formats,
1837 &blend_enable_mask);
1838
1839 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
1840 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
1841
1842 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
1843
1844 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
1845 }
1846
1847 static void
1848 tu_pipeline_finish(struct tu_pipeline *pipeline,
1849 struct tu_device *dev,
1850 const VkAllocationCallbacks *alloc)
1851 {
1852 tu_cs_finish(dev, &pipeline->cs);
1853
1854 if (pipeline->program.binary_bo.gem_handle)
1855 tu_bo_finish(dev, &pipeline->program.binary_bo);
1856 }
1857
1858 static VkResult
1859 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
1860 struct tu_pipeline **pipeline)
1861 {
1862 VkResult result = tu_pipeline_create(builder->device, builder->alloc,
1863 pipeline);
1864 if (result != VK_SUCCESS)
1865 return result;
1866
1867 /* compile and upload shaders */
1868 result = tu_pipeline_builder_compile_shaders(builder);
1869 if (result == VK_SUCCESS)
1870 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
1871 if (result != VK_SUCCESS) {
1872 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
1873 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
1874 *pipeline = VK_NULL_HANDLE;
1875
1876 return result;
1877 }
1878
1879 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
1880 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
1881 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
1882 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
1883 tu_pipeline_builder_parse_viewport(builder, *pipeline);
1884 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
1885 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
1886 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
1887
1888 /* we should have reserved enough space upfront such that the CS never
1889 * grows
1890 */
1891 assert((*pipeline)->cs.bo_count == 1);
1892
1893 return VK_SUCCESS;
1894 }
1895
1896 static void
1897 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
1898 {
1899 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1900 if (!builder->shaders[i])
1901 continue;
1902 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
1903 }
1904 }
1905
1906 static void
1907 tu_pipeline_builder_init_graphics(
1908 struct tu_pipeline_builder *builder,
1909 struct tu_device *dev,
1910 struct tu_pipeline_cache *cache,
1911 const VkGraphicsPipelineCreateInfo *create_info,
1912 const VkAllocationCallbacks *alloc)
1913 {
1914 *builder = (struct tu_pipeline_builder) {
1915 .device = dev,
1916 .cache = cache,
1917 .create_info = create_info,
1918 .alloc = alloc,
1919 };
1920
1921 builder->rasterizer_discard =
1922 create_info->pRasterizationState->rasterizerDiscardEnable;
1923
1924 if (builder->rasterizer_discard) {
1925 builder->samples = VK_SAMPLE_COUNT_1_BIT;
1926 } else {
1927 builder->samples = create_info->pMultisampleState->rasterizationSamples;
1928
1929 const struct tu_render_pass *pass =
1930 tu_render_pass_from_handle(create_info->renderPass);
1931 const struct tu_subpass *subpass =
1932 &pass->subpasses[create_info->subpass];
1933
1934 builder->use_depth_stencil_attachment =
1935 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
1936
1937 assert(subpass->color_count == 0 ||
1938 !create_info->pColorBlendState ||
1939 subpass->color_count == create_info->pColorBlendState->attachmentCount);
1940 builder->color_attachment_count = subpass->color_count;
1941 for (uint32_t i = 0; i < subpass->color_count; i++) {
1942 const uint32_t a = subpass->color_attachments[i].attachment;
1943 if (a == VK_ATTACHMENT_UNUSED)
1944 continue;
1945
1946 builder->color_attachment_formats[i] = pass->attachments[a].format;
1947 builder->use_color_attachments = true;
1948 }
1949 }
1950 }
1951
1952 static VkResult
1953 tu_graphics_pipeline_create(VkDevice device,
1954 VkPipelineCache pipelineCache,
1955 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1956 const VkAllocationCallbacks *pAllocator,
1957 VkPipeline *pPipeline)
1958 {
1959 TU_FROM_HANDLE(tu_device, dev, device);
1960 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
1961
1962 struct tu_pipeline_builder builder;
1963 tu_pipeline_builder_init_graphics(&builder, dev, cache,
1964 pCreateInfo, pAllocator);
1965
1966 struct tu_pipeline *pipeline = NULL;
1967 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
1968 tu_pipeline_builder_finish(&builder);
1969
1970 if (result == VK_SUCCESS)
1971 *pPipeline = tu_pipeline_to_handle(pipeline);
1972 else
1973 *pPipeline = NULL;
1974
1975 return result;
1976 }
1977
1978 VkResult
1979 tu_CreateGraphicsPipelines(VkDevice device,
1980 VkPipelineCache pipelineCache,
1981 uint32_t count,
1982 const VkGraphicsPipelineCreateInfo *pCreateInfos,
1983 const VkAllocationCallbacks *pAllocator,
1984 VkPipeline *pPipelines)
1985 {
1986 VkResult final_result = VK_SUCCESS;
1987
1988 for (uint32_t i = 0; i < count; i++) {
1989 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
1990 &pCreateInfos[i], pAllocator,
1991 &pPipelines[i]);
1992
1993 if (result != VK_SUCCESS)
1994 final_result = result;
1995 }
1996
1997 return final_result;
1998 }
1999
2000 static void
2001 tu6_emit_compute_program(struct tu_cs *cs,
2002 struct tu_shader *shader,
2003 const struct tu_bo *binary_bo)
2004 {
2005 const struct ir3_shader_variant *v = &shader->variants[0];
2006
2007 tu6_emit_cs_config(cs, v);
2008
2009 /* The compute program is the only one in the pipeline, so 0 offset. */
2010 tu6_emit_shader_object(cs, MESA_SHADER_COMPUTE, v, binary_bo, 0);
2011
2012 tu6_emit_immediates(cs, v, CP_LOAD_STATE6_FRAG, SB6_CS_SHADER);
2013 }
2014
2015 static VkResult
2016 tu_compute_upload_shader(VkDevice device,
2017 struct tu_pipeline *pipeline,
2018 struct tu_shader *shader)
2019 {
2020 TU_FROM_HANDLE(tu_device, dev, device);
2021 struct tu_bo *bo = &pipeline->program.binary_bo;
2022 struct ir3_shader_variant *v = &shader->variants[0];
2023
2024 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2025 VkResult result =
2026 tu_bo_init_new(dev, bo, shader_size);
2027 if (result != VK_SUCCESS)
2028 return result;
2029
2030 result = tu_bo_map(dev, bo);
2031 if (result != VK_SUCCESS)
2032 return result;
2033
2034 memcpy(bo->map, shader->binary, shader_size);
2035
2036 return VK_SUCCESS;
2037 }
2038
2039
2040 static VkResult
2041 tu_compute_pipeline_create(VkDevice device,
2042 VkPipelineCache _cache,
2043 const VkComputePipelineCreateInfo *pCreateInfo,
2044 const VkAllocationCallbacks *pAllocator,
2045 VkPipeline *pPipeline)
2046 {
2047 TU_FROM_HANDLE(tu_device, dev, device);
2048 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2049 VkResult result;
2050
2051 struct tu_pipeline *pipeline;
2052
2053 result = tu_pipeline_create(dev, pAllocator, &pipeline);
2054 if (result != VK_SUCCESS)
2055 return result;
2056
2057 struct tu_shader_compile_options options;
2058 tu_shader_compile_options_init(&options, NULL);
2059
2060 struct tu_shader *shader =
2061 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, pAllocator);
2062 if (!shader) {
2063 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2064 goto fail;
2065 }
2066
2067 result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2068 if (result != VK_SUCCESS)
2069 return result;
2070
2071 struct tu_program_descriptor_linkage *link = &pipeline->program.link[MESA_SHADER_COMPUTE];
2072 struct ir3_shader_variant *v = &shader->variants[0];
2073
2074 link->ubo_state = v->shader->ubo_state;
2075 link->const_state = v->shader->const_state;
2076 link->constlen = v->constlen;
2077 link->texture_map = shader->texture_map;
2078 link->sampler_map = shader->sampler_map;
2079 link->ubo_map = shader->ubo_map;
2080 link->ssbo_map = shader->ssbo_map;
2081 link->image_mapping = v->image_mapping;
2082
2083 result = tu_compute_upload_shader(device, pipeline, shader);
2084 if (result != VK_SUCCESS)
2085 return result;
2086
2087 for (int i = 0; i < 3; i++)
2088 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2089
2090 struct tu_cs prog_cs;
2091 tu_cs_begin_sub_stream(dev, &pipeline->cs, 512, &prog_cs);
2092 tu6_emit_compute_program(&prog_cs, shader, &pipeline->program.binary_bo);
2093 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2094
2095 *pPipeline = tu_pipeline_to_handle(pipeline);
2096 return VK_SUCCESS;
2097
2098 fail:
2099 tu_shader_destroy(dev, shader, pAllocator);
2100 if (result != VK_SUCCESS) {
2101 tu_pipeline_finish(pipeline, dev, pAllocator);
2102 vk_free2(&dev->alloc, pAllocator, pipeline);
2103 }
2104
2105 return result;
2106 }
2107
2108 VkResult
2109 tu_CreateComputePipelines(VkDevice device,
2110 VkPipelineCache pipelineCache,
2111 uint32_t count,
2112 const VkComputePipelineCreateInfo *pCreateInfos,
2113 const VkAllocationCallbacks *pAllocator,
2114 VkPipeline *pPipelines)
2115 {
2116 VkResult final_result = VK_SUCCESS;
2117
2118 for (uint32_t i = 0; i < count; i++) {
2119 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2120 &pCreateInfos[i],
2121 pAllocator, &pPipelines[i]);
2122 if (result != VK_SUCCESS)
2123 final_result = result;
2124 }
2125
2126 return final_result;
2127 }
2128
2129 void
2130 tu_DestroyPipeline(VkDevice _device,
2131 VkPipeline _pipeline,
2132 const VkAllocationCallbacks *pAllocator)
2133 {
2134 TU_FROM_HANDLE(tu_device, dev, _device);
2135 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2136
2137 if (!_pipeline)
2138 return;
2139
2140 tu_pipeline_finish(pipeline, dev, pAllocator);
2141 vk_free2(&dev->alloc, pAllocator, pipeline);
2142 }