turnip: Remove RANGE_SIZE usage
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #include "vk_format.h"
81
82 #define MAX_VBS 32
83 #define MAX_VERTEX_ATTRIBS 32
84 #define MAX_RTS 8
85 #define MAX_VSC_PIPES 32
86 #define MAX_VIEWPORTS 1
87 #define MAX_SCISSORS 16
88 #define MAX_DISCARD_RECTANGLES 4
89 #define MAX_PUSH_CONSTANTS_SIZE 128
90 #define MAX_PUSH_DESCRIPTORS 32
91 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
92 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
93 #define MAX_DYNAMIC_BUFFERS \
94 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
95 #define MAX_SAMPLES_LOG2 4
96 #define NUM_META_FS_KEYS 13
97 #define TU_MAX_DRM_DEVICES 8
98 #define MAX_VIEWS 8
99 #define MAX_BIND_POINTS 2 /* compute + graphics */
100 /* The Qualcomm driver exposes 0x20000058 */
101 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
102 /* We use ldc for uniform buffer loads, just like the Qualcomm driver, so
103 * expose the same maximum range.
104 * TODO: The SIZE bitfield is 15 bits, and in 4-dword units, so the actual
105 * range might be higher.
106 */
107 #define MAX_UNIFORM_BUFFER_RANGE 0x10000
108
109 #define NUM_DEPTH_CLEAR_PIPELINES 3
110
111 /*
112 * This is the point we switch from using CP to compute shader
113 * for certain buffer operations.
114 */
115 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
116
117 #define A6XX_TEX_CONST_DWORDS 16
118 #define A6XX_TEX_SAMP_DWORDS 4
119
120 enum tu_mem_heap
121 {
122 TU_MEM_HEAP_VRAM,
123 TU_MEM_HEAP_VRAM_CPU_ACCESS,
124 TU_MEM_HEAP_GTT,
125 TU_MEM_HEAP_COUNT
126 };
127
128 enum tu_mem_type
129 {
130 TU_MEM_TYPE_VRAM,
131 TU_MEM_TYPE_GTT_WRITE_COMBINE,
132 TU_MEM_TYPE_VRAM_CPU_ACCESS,
133 TU_MEM_TYPE_GTT_CACHED,
134 TU_MEM_TYPE_COUNT
135 };
136
137 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
138
139 static inline uint32_t
140 align_u32(uint32_t v, uint32_t a)
141 {
142 assert(a != 0 && a == (a & -a));
143 return (v + a - 1) & ~(a - 1);
144 }
145
146 static inline uint32_t
147 align_u32_npot(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a * a;
150 }
151
152 static inline uint64_t
153 align_u64(uint64_t v, uint64_t a)
154 {
155 assert(a != 0 && a == (a & -a));
156 return (v + a - 1) & ~(a - 1);
157 }
158
159 static inline int32_t
160 align_i32(int32_t v, int32_t a)
161 {
162 assert(a != 0 && a == (a & -a));
163 return (v + a - 1) & ~(a - 1);
164 }
165
166 /** Alignment must be a power of 2. */
167 static inline bool
168 tu_is_aligned(uintmax_t n, uintmax_t a)
169 {
170 assert(a == (a & -a));
171 return (n & (a - 1)) == 0;
172 }
173
174 static inline uint32_t
175 round_up_u32(uint32_t v, uint32_t a)
176 {
177 return (v + a - 1) / a;
178 }
179
180 static inline uint64_t
181 round_up_u64(uint64_t v, uint64_t a)
182 {
183 return (v + a - 1) / a;
184 }
185
186 static inline uint32_t
187 tu_minify(uint32_t n, uint32_t levels)
188 {
189 if (unlikely(n == 0))
190 return 0;
191 else
192 return MAX2(n >> levels, 1);
193 }
194 static inline float
195 tu_clamp_f(float f, float min, float max)
196 {
197 assert(min < max);
198
199 if (f > max)
200 return max;
201 else if (f < min)
202 return min;
203 else
204 return f;
205 }
206
207 static inline bool
208 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
209 {
210 if (*inout_mask & clear_mask) {
211 *inout_mask &= ~clear_mask;
212 return true;
213 } else {
214 return false;
215 }
216 }
217
218 #define for_each_bit(b, dword) \
219 for (uint32_t __dword = (dword); \
220 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
221
222 #define typed_memcpy(dest, src, count) \
223 ({ \
224 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
225 memcpy((dest), (src), (count) * sizeof(*(src))); \
226 })
227
228 #define COND(bool, val) ((bool) ? (val) : 0)
229
230 /* Whenever we generate an error, pass it through this function. Useful for
231 * debugging, where we can break on it. Only call at error site, not when
232 * propagating errors. Might be useful to plug in a stack trace here.
233 */
234
235 struct tu_instance;
236
237 VkResult
238 __vk_errorf(struct tu_instance *instance,
239 VkResult error,
240 const char *file,
241 int line,
242 const char *format,
243 ...);
244
245 #define vk_error(instance, error) \
246 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
247 #define vk_errorf(instance, error, format, ...) \
248 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
249
250 void
251 __tu_finishme(const char *file, int line, const char *format, ...)
252 tu_printflike(3, 4);
253 void
254 tu_loge(const char *format, ...) tu_printflike(1, 2);
255 void
256 tu_loge_v(const char *format, va_list va);
257 void
258 tu_logi(const char *format, ...) tu_printflike(1, 2);
259 void
260 tu_logi_v(const char *format, va_list va);
261
262 /**
263 * Print a FINISHME message, including its source location.
264 */
265 #define tu_finishme(format, ...) \
266 do { \
267 static bool reported = false; \
268 if (!reported) { \
269 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
270 reported = true; \
271 } \
272 } while (0)
273
274 /* A non-fatal assert. Useful for debugging. */
275 #ifdef DEBUG
276 #define tu_assert(x) \
277 ({ \
278 if (unlikely(!(x))) \
279 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
280 })
281 #else
282 #define tu_assert(x)
283 #endif
284
285 /* Suppress -Wunused in stub functions */
286 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
287 static inline void
288 __tu_use_args(int ignore, ...)
289 {
290 }
291
292 #define tu_stub() \
293 do { \
294 tu_finishme("stub %s", __func__); \
295 } while (0)
296
297 void *
298 tu_lookup_entrypoint_unchecked(const char *name);
299 void *
300 tu_lookup_entrypoint_checked(
301 const char *name,
302 uint32_t core_version,
303 const struct tu_instance_extension_table *instance,
304 const struct tu_device_extension_table *device);
305
306 struct tu_physical_device
307 {
308 VK_LOADER_DATA _loader_data;
309
310 struct tu_instance *instance;
311
312 char path[20];
313 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
314 uint8_t driver_uuid[VK_UUID_SIZE];
315 uint8_t device_uuid[VK_UUID_SIZE];
316 uint8_t cache_uuid[VK_UUID_SIZE];
317
318 struct wsi_device wsi_device;
319
320 int local_fd;
321 int master_fd;
322
323 unsigned gpu_id;
324 uint32_t gmem_size;
325 uint64_t gmem_base;
326 uint32_t ccu_offset_gmem;
327 uint32_t ccu_offset_bypass;
328 /* alignment for size of tiles */
329 uint32_t tile_align_w;
330 #define TILE_ALIGN_H 16
331 /* gmem store/load granularity */
332 #define GMEM_ALIGN_W 16
333 #define GMEM_ALIGN_H 4
334
335 struct {
336 uint32_t PC_UNKNOWN_9805;
337 uint32_t SP_UNKNOWN_A0F8;
338 } magic;
339
340 /* This is the drivers on-disk cache used as a fallback as opposed to
341 * the pipeline cache defined by apps.
342 */
343 struct disk_cache *disk_cache;
344
345 struct tu_device_extension_table supported_extensions;
346 };
347
348 enum tu_debug_flags
349 {
350 TU_DEBUG_STARTUP = 1 << 0,
351 TU_DEBUG_NIR = 1 << 1,
352 TU_DEBUG_IR3 = 1 << 2,
353 TU_DEBUG_NOBIN = 1 << 3,
354 TU_DEBUG_SYSMEM = 1 << 4,
355 TU_DEBUG_FORCEBIN = 1 << 5,
356 };
357
358 struct tu_instance
359 {
360 VK_LOADER_DATA _loader_data;
361
362 VkAllocationCallbacks alloc;
363
364 uint32_t api_version;
365 int physical_device_count;
366 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
367
368 enum tu_debug_flags debug_flags;
369
370 struct vk_debug_report_instance debug_report_callbacks;
371
372 struct tu_instance_extension_table enabled_extensions;
373 };
374
375 VkResult
376 tu_wsi_init(struct tu_physical_device *physical_device);
377 void
378 tu_wsi_finish(struct tu_physical_device *physical_device);
379
380 bool
381 tu_instance_extension_supported(const char *name);
382 uint32_t
383 tu_physical_device_api_version(struct tu_physical_device *dev);
384 bool
385 tu_physical_device_extension_supported(struct tu_physical_device *dev,
386 const char *name);
387
388 struct cache_entry;
389
390 struct tu_pipeline_cache
391 {
392 struct tu_device *device;
393 pthread_mutex_t mutex;
394
395 uint32_t total_size;
396 uint32_t table_size;
397 uint32_t kernel_count;
398 struct cache_entry **hash_table;
399 bool modified;
400
401 VkAllocationCallbacks alloc;
402 };
403
404 struct tu_pipeline_key
405 {
406 };
407
408 void
409 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
410 struct tu_device *device);
411 void
412 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
413 void
414 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
415 const void *data,
416 size_t size);
417
418 struct tu_shader_variant;
419
420 bool
421 tu_create_shader_variants_from_pipeline_cache(
422 struct tu_device *device,
423 struct tu_pipeline_cache *cache,
424 const unsigned char *sha1,
425 struct tu_shader_variant **variants);
426
427 void
428 tu_pipeline_cache_insert_shaders(struct tu_device *device,
429 struct tu_pipeline_cache *cache,
430 const unsigned char *sha1,
431 struct tu_shader_variant **variants,
432 const void *const *codes,
433 const unsigned *code_sizes);
434
435 struct tu_meta_state
436 {
437 VkAllocationCallbacks alloc;
438
439 struct tu_pipeline_cache cache;
440 };
441
442 /* queue types */
443 #define TU_QUEUE_GENERAL 0
444
445 #define TU_MAX_QUEUE_FAMILIES 1
446
447 struct tu_fence
448 {
449 struct wsi_fence *fence_wsi;
450 bool signaled;
451 int fd;
452 };
453
454 void
455 tu_fence_init(struct tu_fence *fence, bool signaled);
456 void
457 tu_fence_finish(struct tu_fence *fence);
458 void
459 tu_fence_update_fd(struct tu_fence *fence, int fd);
460 void
461 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
462 void
463 tu_fence_signal(struct tu_fence *fence);
464 void
465 tu_fence_wait_idle(struct tu_fence *fence);
466
467 struct tu_queue
468 {
469 VK_LOADER_DATA _loader_data;
470 struct tu_device *device;
471 uint32_t queue_family_index;
472 int queue_idx;
473 VkDeviceQueueCreateFlags flags;
474
475 uint32_t msm_queue_id;
476 struct tu_fence submit_fence;
477 };
478
479 struct tu_bo
480 {
481 uint32_t gem_handle;
482 uint64_t size;
483 uint64_t iova;
484 void *map;
485 };
486
487 struct tu_device
488 {
489 VK_LOADER_DATA _loader_data;
490
491 VkAllocationCallbacks alloc;
492
493 struct tu_instance *instance;
494
495 struct tu_meta_state meta_state;
496
497 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
498 int queue_count[TU_MAX_QUEUE_FAMILIES];
499
500 struct tu_physical_device *physical_device;
501
502 struct ir3_compiler *compiler;
503
504 /* Backup in-memory cache to be used if the app doesn't provide one */
505 struct tu_pipeline_cache *mem_cache;
506
507 struct tu_bo vsc_draw_strm;
508 struct tu_bo vsc_prim_strm;
509 uint32_t vsc_draw_strm_pitch;
510 uint32_t vsc_prim_strm_pitch;
511
512 struct tu_bo border_color;
513
514 struct list_head shader_slabs;
515 mtx_t shader_slab_mutex;
516
517 struct tu_device_extension_table enabled_extensions;
518 };
519
520 VkResult
521 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
522 VkResult
523 tu_bo_init_dmabuf(struct tu_device *dev,
524 struct tu_bo *bo,
525 uint64_t size,
526 int fd);
527 int
528 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
529 void
530 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
531 VkResult
532 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
533
534 struct tu_cs_entry
535 {
536 /* No ownership */
537 const struct tu_bo *bo;
538
539 uint32_t size;
540 uint32_t offset;
541 };
542
543 struct ts_cs_memory {
544 uint32_t *map;
545 uint64_t iova;
546 };
547
548 enum tu_cs_mode
549 {
550
551 /*
552 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
553 * is full. tu_cs_begin must be called before command packet emission and
554 * tu_cs_end must be called after.
555 *
556 * This mode may create multiple entries internally. The entries must be
557 * submitted together.
558 */
559 TU_CS_MODE_GROW,
560
561 /*
562 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
563 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
564 * effect on it.
565 *
566 * This mode does not create any entry or any BO.
567 */
568 TU_CS_MODE_EXTERNAL,
569
570 /*
571 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
572 * command packet emission. tu_cs_begin_sub_stream must be called to get a
573 * sub-stream to emit comamnd packets to. When done with the sub-stream,
574 * tu_cs_end_sub_stream must be called.
575 *
576 * This mode does not create any entry internally.
577 */
578 TU_CS_MODE_SUB_STREAM,
579 };
580
581 struct tu_cs
582 {
583 uint32_t *start;
584 uint32_t *cur;
585 uint32_t *reserved_end;
586 uint32_t *end;
587
588 struct tu_device *device;
589 enum tu_cs_mode mode;
590 uint32_t next_bo_size;
591
592 struct tu_cs_entry *entries;
593 uint32_t entry_count;
594 uint32_t entry_capacity;
595
596 struct tu_bo **bos;
597 uint32_t bo_count;
598 uint32_t bo_capacity;
599
600 /* state for cond_exec_start/cond_exec_end */
601 uint32_t cond_flags;
602 uint32_t *cond_dwords;
603 };
604
605 struct tu_device_memory
606 {
607 struct tu_bo bo;
608 VkDeviceSize size;
609
610 /* for dedicated allocations */
611 struct tu_image *image;
612 struct tu_buffer *buffer;
613
614 uint32_t type_index;
615 void *map;
616 void *user_ptr;
617 };
618
619 struct tu_descriptor_range
620 {
621 uint64_t va;
622 uint32_t size;
623 };
624
625 struct tu_descriptor_set
626 {
627 const struct tu_descriptor_set_layout *layout;
628 struct tu_descriptor_pool *pool;
629 uint32_t size;
630
631 uint64_t va;
632 uint32_t *mapped_ptr;
633
634 uint32_t *dynamic_descriptors;
635
636 struct tu_bo *buffers[0];
637 };
638
639 struct tu_push_descriptor_set
640 {
641 struct tu_descriptor_set set;
642 uint32_t capacity;
643 };
644
645 struct tu_descriptor_pool_entry
646 {
647 uint32_t offset;
648 uint32_t size;
649 struct tu_descriptor_set *set;
650 };
651
652 struct tu_descriptor_pool
653 {
654 struct tu_bo bo;
655 uint64_t current_offset;
656 uint64_t size;
657
658 uint8_t *host_memory_base;
659 uint8_t *host_memory_ptr;
660 uint8_t *host_memory_end;
661
662 uint32_t entry_count;
663 uint32_t max_entry_count;
664 struct tu_descriptor_pool_entry entries[0];
665 };
666
667 struct tu_descriptor_update_template_entry
668 {
669 VkDescriptorType descriptor_type;
670
671 /* The number of descriptors to update */
672 uint32_t descriptor_count;
673
674 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
675 */
676 uint32_t dst_offset;
677
678 /* In dwords. Not valid/used for dynamic descriptors */
679 uint32_t dst_stride;
680
681 uint32_t buffer_offset;
682
683 /* Only valid for combined image samplers and samplers */
684 uint16_t has_sampler;
685
686 /* In bytes */
687 size_t src_offset;
688 size_t src_stride;
689
690 /* For push descriptors */
691 const uint32_t *immutable_samplers;
692 };
693
694 struct tu_descriptor_update_template
695 {
696 uint32_t entry_count;
697 struct tu_descriptor_update_template_entry entry[0];
698 };
699
700 struct tu_buffer
701 {
702 VkDeviceSize size;
703
704 VkBufferUsageFlags usage;
705 VkBufferCreateFlags flags;
706
707 struct tu_bo *bo;
708 VkDeviceSize bo_offset;
709 };
710
711 static inline uint64_t
712 tu_buffer_iova(struct tu_buffer *buffer)
713 {
714 return buffer->bo->iova + buffer->bo_offset;
715 }
716
717 enum tu_dynamic_state_bits
718 {
719 TU_DYNAMIC_VIEWPORT = 1 << 0,
720 TU_DYNAMIC_SCISSOR = 1 << 1,
721 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
722 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
723 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
724 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
725 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
726 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
727 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
728 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
729 TU_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
730 TU_DYNAMIC_ALL = (1 << 11) - 1,
731 };
732
733 struct tu_vertex_binding
734 {
735 struct tu_buffer *buffer;
736 VkDeviceSize offset;
737 };
738
739 struct tu_viewport_state
740 {
741 uint32_t count;
742 VkViewport viewports[MAX_VIEWPORTS];
743 };
744
745 struct tu_scissor_state
746 {
747 uint32_t count;
748 VkRect2D scissors[MAX_SCISSORS];
749 };
750
751 struct tu_discard_rectangle_state
752 {
753 uint32_t count;
754 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
755 };
756
757 struct tu_dynamic_state
758 {
759 /**
760 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
761 * Defines the set of saved dynamic state.
762 */
763 uint32_t mask;
764
765 struct tu_viewport_state viewport;
766
767 struct tu_scissor_state scissor;
768
769 float line_width;
770
771 struct
772 {
773 float bias;
774 float clamp;
775 float slope;
776 } depth_bias;
777
778 float blend_constants[4];
779
780 struct
781 {
782 float min;
783 float max;
784 } depth_bounds;
785
786 struct
787 {
788 uint32_t front;
789 uint32_t back;
790 } stencil_compare_mask;
791
792 struct
793 {
794 uint32_t front;
795 uint32_t back;
796 } stencil_write_mask;
797
798 struct
799 {
800 uint32_t front;
801 uint32_t back;
802 } stencil_reference;
803
804 struct tu_discard_rectangle_state discard_rectangle;
805 };
806
807 extern const struct tu_dynamic_state default_dynamic_state;
808
809 const char *
810 tu_get_debug_option_name(int id);
811
812 const char *
813 tu_get_perftest_option_name(int id);
814
815 struct tu_descriptor_state
816 {
817 struct tu_descriptor_set *sets[MAX_SETS];
818 uint32_t valid;
819 struct tu_push_descriptor_set push_set;
820 bool push_dirty;
821 uint32_t dynamic_descriptors[MAX_DYNAMIC_BUFFERS * A6XX_TEX_CONST_DWORDS];
822 uint32_t input_attachments[MAX_RTS * A6XX_TEX_CONST_DWORDS];
823 };
824
825 struct tu_tile
826 {
827 uint8_t pipe;
828 uint8_t slot;
829 VkOffset2D begin;
830 VkOffset2D end;
831 };
832
833 struct tu_tiling_config
834 {
835 VkRect2D render_area;
836
837 /* position and size of the first tile */
838 VkRect2D tile0;
839 /* number of tiles */
840 VkExtent2D tile_count;
841
842 /* size of the first VSC pipe */
843 VkExtent2D pipe0;
844 /* number of VSC pipes */
845 VkExtent2D pipe_count;
846
847 /* pipe register values */
848 uint32_t pipe_config[MAX_VSC_PIPES];
849 uint32_t pipe_sizes[MAX_VSC_PIPES];
850
851 /* Whether sysmem rendering must be used */
852 bool force_sysmem;
853 };
854
855 enum tu_cmd_dirty_bits
856 {
857 TU_CMD_DIRTY_PIPELINE = 1 << 0,
858 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
859 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
860 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
861 TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS = 1 << 4,
862 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 5,
863 TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 6,
864 TU_CMD_DIRTY_INPUT_ATTACHMENTS = 1 << 7,
865
866 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
867 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
868 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
869 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
870 TU_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 20,
871 TU_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 21,
872 };
873
874 struct tu_streamout_state {
875 uint16_t stride[IR3_MAX_SO_BUFFERS];
876 uint32_t ncomp[IR3_MAX_SO_BUFFERS];
877 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
878 uint32_t prog_count;
879 uint32_t vpc_so_buf_cntl;
880 };
881
882 struct tu_cmd_state
883 {
884 uint32_t dirty;
885
886 struct tu_pipeline *pipeline;
887 struct tu_pipeline *compute_pipeline;
888
889 /* Vertex buffers */
890 struct
891 {
892 struct tu_buffer *buffers[MAX_VBS];
893 VkDeviceSize offsets[MAX_VBS];
894 } vb;
895
896 struct tu_dynamic_state dynamic;
897
898 /* Stream output buffers */
899 struct
900 {
901 struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
902 VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
903 VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
904 } streamout_buf;
905
906 uint8_t streamout_reset;
907 uint8_t streamout_enabled;
908
909 /* Index buffer */
910 struct tu_buffer *index_buffer;
911 uint64_t index_offset;
912 uint32_t index_type;
913 uint32_t max_index_count;
914 uint64_t index_va;
915
916 const struct tu_render_pass *pass;
917 const struct tu_subpass *subpass;
918 const struct tu_framebuffer *framebuffer;
919
920 struct tu_tiling_config tiling_config;
921
922 struct tu_cs_entry tile_store_ib;
923 };
924
925 struct tu_cmd_pool
926 {
927 VkAllocationCallbacks alloc;
928 struct list_head cmd_buffers;
929 struct list_head free_cmd_buffers;
930 uint32_t queue_family_index;
931 };
932
933 struct tu_cmd_buffer_upload
934 {
935 uint8_t *map;
936 unsigned offset;
937 uint64_t size;
938 struct list_head list;
939 };
940
941 enum tu_cmd_buffer_status
942 {
943 TU_CMD_BUFFER_STATUS_INVALID,
944 TU_CMD_BUFFER_STATUS_INITIAL,
945 TU_CMD_BUFFER_STATUS_RECORDING,
946 TU_CMD_BUFFER_STATUS_EXECUTABLE,
947 TU_CMD_BUFFER_STATUS_PENDING,
948 };
949
950 struct tu_bo_list
951 {
952 uint32_t count;
953 uint32_t capacity;
954 struct drm_msm_gem_submit_bo *bo_infos;
955 };
956
957 #define TU_BO_LIST_FAILED (~0)
958
959 void
960 tu_bo_list_init(struct tu_bo_list *list);
961 void
962 tu_bo_list_destroy(struct tu_bo_list *list);
963 void
964 tu_bo_list_reset(struct tu_bo_list *list);
965 uint32_t
966 tu_bo_list_add(struct tu_bo_list *list,
967 const struct tu_bo *bo,
968 uint32_t flags);
969 VkResult
970 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
971
972 /* This struct defines the layout of the scratch_bo */
973 struct tu6_control
974 {
975 uint32_t seqno; /* seqno for async CP_EVENT_WRITE, etc */
976 uint32_t _pad0;
977 volatile uint32_t vsc_overflow;
978 uint32_t _pad1;
979 /* flag set from cmdstream when VSC overflow detected: */
980 uint32_t vsc_scratch;
981 uint32_t _pad2;
982 uint32_t _pad3;
983 uint32_t _pad4;
984
985 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
986 struct {
987 uint32_t offset;
988 uint32_t pad[7];
989 } flush_base[4];
990 };
991
992 #define ctrl_offset(member) offsetof(struct tu6_control, member)
993
994 struct tu_cmd_buffer
995 {
996 VK_LOADER_DATA _loader_data;
997
998 struct tu_device *device;
999
1000 struct tu_cmd_pool *pool;
1001 struct list_head pool_link;
1002
1003 VkCommandBufferUsageFlags usage_flags;
1004 VkCommandBufferLevel level;
1005 enum tu_cmd_buffer_status status;
1006
1007 struct tu_cmd_state state;
1008 struct tu_vertex_binding vertex_bindings[MAX_VBS];
1009 uint32_t queue_family_index;
1010
1011 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
1012 VkShaderStageFlags push_constant_stages;
1013 struct tu_descriptor_set meta_push_descriptors;
1014
1015 struct tu_descriptor_state descriptors[MAX_BIND_POINTS];
1016
1017 struct tu_cmd_buffer_upload upload;
1018
1019 VkResult record_result;
1020
1021 struct tu_bo_list bo_list;
1022 struct tu_cs cs;
1023 struct tu_cs draw_cs;
1024 struct tu_cs draw_epilogue_cs;
1025 struct tu_cs sub_cs;
1026
1027 struct tu_bo scratch_bo;
1028 uint32_t scratch_seqno;
1029
1030 struct tu_bo vsc_draw_strm;
1031 struct tu_bo vsc_prim_strm;
1032 uint32_t vsc_draw_strm_pitch;
1033 uint32_t vsc_prim_strm_pitch;
1034 bool use_vsc_data;
1035
1036 bool wait_for_idle;
1037 };
1038
1039 /* Temporary struct for tracking a register state to be written, used by
1040 * a6xx-pack.h and tu_cs_emit_regs()
1041 */
1042 struct tu_reg_value {
1043 uint32_t reg;
1044 uint64_t value;
1045 bool is_address;
1046 struct tu_bo *bo;
1047 bool bo_write;
1048 uint32_t bo_offset;
1049 uint32_t bo_shift;
1050 };
1051
1052 unsigned
1053 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
1054 struct tu_cs *cs,
1055 enum vgt_event_type event,
1056 bool need_seqno);
1057
1058 bool
1059 tu_get_memory_fd(struct tu_device *device,
1060 struct tu_device_memory *memory,
1061 int *pFD);
1062
1063 static inline struct tu_descriptor_state *
1064 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
1065 VkPipelineBindPoint bind_point)
1066 {
1067 return &cmd_buffer->descriptors[bind_point];
1068 }
1069
1070 /*
1071 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1072 *
1073 * Limitations: Can't call normal dispatch functions without binding or
1074 * rebinding
1075 * the compute pipeline.
1076 */
1077 void
1078 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1079 uint32_t x,
1080 uint32_t y,
1081 uint32_t z);
1082
1083 struct tu_event
1084 {
1085 struct tu_bo bo;
1086 };
1087
1088 struct tu_shader_module;
1089
1090 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1091 #define TU_HASH_SHADER_SISCHED (1 << 1)
1092 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1093 void
1094 tu_hash_shaders(unsigned char *hash,
1095 const VkPipelineShaderStageCreateInfo **stages,
1096 const struct tu_pipeline_layout *layout,
1097 const struct tu_pipeline_key *key,
1098 uint32_t flags);
1099
1100 static inline gl_shader_stage
1101 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1102 {
1103 assert(__builtin_popcount(vk_stage) == 1);
1104 return ffs(vk_stage) - 1;
1105 }
1106
1107 static inline VkShaderStageFlagBits
1108 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1109 {
1110 return (1 << mesa_stage);
1111 }
1112
1113 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1114
1115 #define tu_foreach_stage(stage, stage_bits) \
1116 for (gl_shader_stage stage, \
1117 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1118 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1119
1120 struct tu_shader_module
1121 {
1122 unsigned char sha1[20];
1123
1124 uint32_t code_size;
1125 const uint32_t *code[0];
1126 };
1127
1128 struct tu_shader_compile_options
1129 {
1130 struct ir3_shader_key key;
1131
1132 bool optimize;
1133 bool include_binning_pass;
1134 };
1135
1136 struct tu_push_constant_range
1137 {
1138 uint32_t lo;
1139 uint32_t count;
1140 };
1141
1142 struct tu_shader
1143 {
1144 struct ir3_shader ir3_shader;
1145
1146 struct tu_push_constant_range push_consts;
1147 unsigned attachment_idx[MAX_RTS];
1148
1149 /* This may be true for vertex shaders. When true, variants[1] is the
1150 * binning variant and binning_binary is non-NULL.
1151 */
1152 bool has_binning_pass;
1153
1154 void *binary;
1155 void *binning_binary;
1156
1157 struct ir3_shader_variant variants[0];
1158 };
1159
1160 struct tu_shader *
1161 tu_shader_create(struct tu_device *dev,
1162 gl_shader_stage stage,
1163 const VkPipelineShaderStageCreateInfo *stage_info,
1164 struct tu_pipeline_layout *layout,
1165 const VkAllocationCallbacks *alloc);
1166
1167 void
1168 tu_shader_destroy(struct tu_device *dev,
1169 struct tu_shader *shader,
1170 const VkAllocationCallbacks *alloc);
1171
1172 void
1173 tu_shader_compile_options_init(
1174 struct tu_shader_compile_options *options,
1175 const VkGraphicsPipelineCreateInfo *pipeline_info);
1176
1177 VkResult
1178 tu_shader_compile(struct tu_device *dev,
1179 struct tu_shader *shader,
1180 const struct tu_shader *next_stage,
1181 const struct tu_shader_compile_options *options,
1182 const VkAllocationCallbacks *alloc);
1183
1184 struct tu_program_descriptor_linkage
1185 {
1186 struct ir3_ubo_analysis_state ubo_state;
1187 struct ir3_const_state const_state;
1188
1189 uint32_t constlen;
1190
1191 struct tu_push_constant_range push_consts;
1192 };
1193
1194 struct tu_pipeline
1195 {
1196 struct tu_cs cs;
1197
1198 struct tu_dynamic_state dynamic_state;
1199
1200 struct tu_pipeline_layout *layout;
1201
1202 bool need_indirect_descriptor_sets;
1203 VkShaderStageFlags active_stages;
1204
1205 struct tu_streamout_state streamout;
1206
1207 struct
1208 {
1209 struct tu_bo binary_bo;
1210 struct tu_cs_entry state_ib;
1211 struct tu_cs_entry binning_state_ib;
1212
1213 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1214 unsigned input_attachment_idx[MAX_RTS];
1215 } program;
1216
1217 struct
1218 {
1219 struct tu_cs_entry state_ib;
1220 } load_state;
1221
1222 struct
1223 {
1224 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1225 uint32_t count;
1226
1227 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1228 uint32_t binning_count;
1229
1230 struct tu_cs_entry state_ib;
1231 struct tu_cs_entry binning_state_ib;
1232 } vi;
1233
1234 struct
1235 {
1236 enum pc_di_primtype primtype;
1237 bool primitive_restart;
1238 } ia;
1239
1240 struct
1241 {
1242 struct tu_cs_entry state_ib;
1243 } vp;
1244
1245 struct
1246 {
1247 uint32_t gras_su_cntl;
1248 struct tu_cs_entry state_ib;
1249 } rast;
1250
1251 struct
1252 {
1253 struct tu_cs_entry state_ib;
1254 } ds;
1255
1256 struct
1257 {
1258 struct tu_cs_entry state_ib;
1259 } blend;
1260
1261 struct
1262 {
1263 uint32_t local_size[3];
1264 } compute;
1265 };
1266
1267 void
1268 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1269
1270 void
1271 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1272
1273 void
1274 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc);
1275
1276 void
1277 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1278 uint32_t gras_su_cntl,
1279 float line_width);
1280
1281 void
1282 tu6_emit_depth_bias(struct tu_cs *cs,
1283 float constant_factor,
1284 float clamp,
1285 float slope_factor);
1286
1287 void
1288 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1289 uint32_t front,
1290 uint32_t back);
1291
1292 void
1293 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1294
1295 void
1296 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1297
1298 void
1299 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1300
1301 void tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits samples);
1302
1303 void tu6_emit_window_scissor(struct tu_cs *cs, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2);
1304
1305 void tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1);
1306
1307 struct tu_image_view;
1308
1309 void
1310 tu_resolve_sysmem(struct tu_cmd_buffer *cmd,
1311 struct tu_cs *cs,
1312 struct tu_image_view *src,
1313 struct tu_image_view *dst,
1314 uint32_t layers,
1315 const VkRect2D *rect);
1316
1317 void
1318 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1319 struct tu_cs *cs,
1320 uint32_t a,
1321 const VkRenderPassBeginInfo *info);
1322
1323 void
1324 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1325 struct tu_cs *cs,
1326 uint32_t a,
1327 const VkRenderPassBeginInfo *info);
1328
1329 void
1330 tu_load_gmem_attachment(struct tu_cmd_buffer *cmd,
1331 struct tu_cs *cs,
1332 uint32_t a,
1333 bool force_load);
1334
1335 /* expose this function to be able to emit load without checking LOAD_OP */
1336 void
1337 tu_emit_load_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a);
1338
1339 /* note: gmem store can also resolve */
1340 void
1341 tu_store_gmem_attachment(struct tu_cmd_buffer *cmd,
1342 struct tu_cs *cs,
1343 uint32_t a,
1344 uint32_t gmem_a);
1345
1346 struct tu_userdata_info *
1347 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1348 gl_shader_stage stage,
1349 int idx);
1350
1351 struct tu_shader_variant *
1352 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1353
1354 struct tu_graphics_pipeline_create_info
1355 {
1356 bool use_rectlist;
1357 bool db_depth_clear;
1358 bool db_stencil_clear;
1359 bool db_depth_disable_expclear;
1360 bool db_stencil_disable_expclear;
1361 bool db_flush_depth_inplace;
1362 bool db_flush_stencil_inplace;
1363 bool db_resummarize;
1364 uint32_t custom_blend_mode;
1365 };
1366
1367 enum tu_supported_formats {
1368 FMT_VERTEX = 1,
1369 FMT_TEXTURE = 2,
1370 FMT_COLOR = 4,
1371 };
1372
1373 struct tu_native_format
1374 {
1375 enum a6xx_format fmt : 8;
1376 enum a3xx_color_swap swap : 8;
1377 enum a6xx_tile_mode tile_mode : 8;
1378 enum tu_supported_formats supported : 8;
1379 };
1380
1381 struct tu_native_format tu6_format_vtx(VkFormat format);
1382 struct tu_native_format tu6_format_color(VkFormat format, enum a6xx_tile_mode tile_mode);
1383 struct tu_native_format tu6_format_texture(VkFormat format, enum a6xx_tile_mode tile_mode);
1384
1385 static inline enum a6xx_format
1386 tu6_base_format(VkFormat format)
1387 {
1388 /* note: tu6_format_color doesn't care about tiling for .fmt field */
1389 return tu6_format_color(format, TILE6_LINEAR).fmt;
1390 }
1391
1392 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1393
1394 struct tu_image
1395 {
1396 VkImageType type;
1397 /* The original VkFormat provided by the client. This may not match any
1398 * of the actual surface formats.
1399 */
1400 VkFormat vk_format;
1401 VkImageAspectFlags aspects;
1402 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1403 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1404 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1405 VkExtent3D extent;
1406 uint32_t level_count;
1407 uint32_t layer_count;
1408 VkSampleCountFlagBits samples;
1409
1410 struct fdl_layout layout;
1411
1412 unsigned queue_family_mask;
1413 bool exclusive;
1414 bool shareable;
1415
1416 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1417 VkDeviceMemory owned_memory;
1418
1419 /* Set when bound */
1420 struct tu_bo *bo;
1421 VkDeviceSize bo_offset;
1422 };
1423
1424 unsigned
1425 tu_image_queue_family_mask(const struct tu_image *image,
1426 uint32_t family,
1427 uint32_t queue_family);
1428
1429 static inline uint32_t
1430 tu_get_layerCount(const struct tu_image *image,
1431 const VkImageSubresourceRange *range)
1432 {
1433 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1434 ? image->layer_count - range->baseArrayLayer
1435 : range->layerCount;
1436 }
1437
1438 static inline uint32_t
1439 tu_get_levelCount(const struct tu_image *image,
1440 const VkImageSubresourceRange *range)
1441 {
1442 return range->levelCount == VK_REMAINING_MIP_LEVELS
1443 ? image->level_count - range->baseMipLevel
1444 : range->levelCount;
1445 }
1446
1447 enum a3xx_msaa_samples
1448 tu_msaa_samples(uint32_t samples);
1449 enum a6xx_tex_fetchsize
1450 tu6_fetchsize(VkFormat format);
1451
1452 struct tu_image_view
1453 {
1454 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1455
1456 uint64_t base_addr;
1457 uint64_t ubwc_addr;
1458 uint32_t layer_size;
1459 uint32_t ubwc_layer_size;
1460
1461 /* used to determine if fast gmem store path can be used */
1462 VkExtent2D extent;
1463 bool need_y2_align;
1464
1465 bool ubwc_enabled;
1466
1467 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1468
1469 /* Descriptor for use as a storage image as opposed to a sampled image.
1470 * This has a few differences for cube maps (e.g. type).
1471 */
1472 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1473
1474 /* pre-filled register values */
1475 uint32_t PITCH;
1476 uint32_t FLAG_BUFFER_PITCH;
1477
1478 uint32_t RB_MRT_BUF_INFO;
1479 uint32_t SP_FS_MRT_REG;
1480
1481 uint32_t SP_PS_2D_SRC_INFO;
1482 uint32_t SP_PS_2D_SRC_SIZE;
1483
1484 uint32_t RB_2D_DST_INFO;
1485
1486 uint32_t RB_BLIT_DST_INFO;
1487 };
1488
1489 struct tu_sampler {
1490 uint32_t descriptor[A6XX_TEX_SAMP_DWORDS];
1491 };
1492
1493 void
1494 tu_cs_image_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
1495
1496 void
1497 tu_cs_image_ref_2d(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer, bool src);
1498
1499 void
1500 tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
1501
1502 VkResult
1503 tu_image_create(VkDevice _device,
1504 const VkImageCreateInfo *pCreateInfo,
1505 const VkAllocationCallbacks *alloc,
1506 VkImage *pImage,
1507 uint64_t modifier);
1508
1509 VkResult
1510 tu_image_from_gralloc(VkDevice device_h,
1511 const VkImageCreateInfo *base_info,
1512 const VkNativeBufferANDROID *gralloc_info,
1513 const VkAllocationCallbacks *alloc,
1514 VkImage *out_image_h);
1515
1516 void
1517 tu_image_view_init(struct tu_image_view *view,
1518 const VkImageViewCreateInfo *pCreateInfo);
1519
1520 struct tu_buffer_view
1521 {
1522 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1523
1524 struct tu_buffer *buffer;
1525 };
1526 void
1527 tu_buffer_view_init(struct tu_buffer_view *view,
1528 struct tu_device *device,
1529 const VkBufferViewCreateInfo *pCreateInfo);
1530
1531 static inline struct VkExtent3D
1532 tu_sanitize_image_extent(const VkImageType imageType,
1533 const struct VkExtent3D imageExtent)
1534 {
1535 switch (imageType) {
1536 case VK_IMAGE_TYPE_1D:
1537 return (VkExtent3D) { imageExtent.width, 1, 1 };
1538 case VK_IMAGE_TYPE_2D:
1539 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1540 case VK_IMAGE_TYPE_3D:
1541 return imageExtent;
1542 default:
1543 unreachable("invalid image type");
1544 }
1545 }
1546
1547 static inline struct VkOffset3D
1548 tu_sanitize_image_offset(const VkImageType imageType,
1549 const struct VkOffset3D imageOffset)
1550 {
1551 switch (imageType) {
1552 case VK_IMAGE_TYPE_1D:
1553 return (VkOffset3D) { imageOffset.x, 0, 0 };
1554 case VK_IMAGE_TYPE_2D:
1555 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1556 case VK_IMAGE_TYPE_3D:
1557 return imageOffset;
1558 default:
1559 unreachable("invalid image type");
1560 }
1561 }
1562
1563 struct tu_attachment_info
1564 {
1565 struct tu_image_view *attachment;
1566 };
1567
1568 struct tu_framebuffer
1569 {
1570 uint32_t width;
1571 uint32_t height;
1572 uint32_t layers;
1573
1574 uint32_t attachment_count;
1575 struct tu_attachment_info attachments[0];
1576 };
1577
1578 struct tu_subpass_attachment
1579 {
1580 uint32_t attachment;
1581 };
1582
1583 struct tu_subpass
1584 {
1585 uint32_t input_count;
1586 uint32_t color_count;
1587 struct tu_subpass_attachment *input_attachments;
1588 struct tu_subpass_attachment *color_attachments;
1589 struct tu_subpass_attachment *resolve_attachments;
1590 struct tu_subpass_attachment depth_stencil_attachment;
1591
1592 VkSampleCountFlagBits samples;
1593
1594 /* pre-filled register values */
1595 uint32_t render_components;
1596 uint32_t srgb_cntl;
1597 };
1598
1599 struct tu_render_pass_attachment
1600 {
1601 VkFormat format;
1602 uint32_t samples;
1603 uint32_t cpp;
1604 VkImageAspectFlags clear_mask;
1605 bool load;
1606 bool store;
1607 int32_t gmem_offset;
1608 };
1609
1610 struct tu_render_pass
1611 {
1612 uint32_t attachment_count;
1613 uint32_t subpass_count;
1614 uint32_t gmem_pixels;
1615 uint32_t tile_align_w;
1616 struct tu_subpass_attachment *subpass_attachments;
1617 struct tu_render_pass_attachment *attachments;
1618 struct tu_subpass subpasses[0];
1619 };
1620
1621 VkResult
1622 tu_device_init_meta(struct tu_device *device);
1623 void
1624 tu_device_finish_meta(struct tu_device *device);
1625
1626 struct tu_query_pool
1627 {
1628 VkQueryType type;
1629 uint32_t stride;
1630 uint64_t size;
1631 uint32_t pipeline_statistics;
1632 struct tu_bo bo;
1633 };
1634
1635 struct tu_semaphore
1636 {
1637 uint32_t syncobj;
1638 uint32_t temp_syncobj;
1639 };
1640
1641 void
1642 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1643 VkPipelineBindPoint bind_point,
1644 struct tu_descriptor_set *set,
1645 unsigned idx);
1646
1647 void
1648 tu_update_descriptor_sets(struct tu_device *device,
1649 struct tu_cmd_buffer *cmd_buffer,
1650 VkDescriptorSet overrideSet,
1651 uint32_t descriptorWriteCount,
1652 const VkWriteDescriptorSet *pDescriptorWrites,
1653 uint32_t descriptorCopyCount,
1654 const VkCopyDescriptorSet *pDescriptorCopies);
1655
1656 void
1657 tu_update_descriptor_set_with_template(
1658 struct tu_device *device,
1659 struct tu_cmd_buffer *cmd_buffer,
1660 struct tu_descriptor_set *set,
1661 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1662 const void *pData);
1663
1664 void
1665 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1666 VkPipelineBindPoint pipelineBindPoint,
1667 VkPipelineLayout _layout,
1668 uint32_t set,
1669 uint32_t descriptorWriteCount,
1670 const VkWriteDescriptorSet *pDescriptorWrites);
1671
1672 int
1673 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1674
1675 int
1676 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1677
1678 int
1679 tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
1680
1681 int
1682 tu_drm_submitqueue_new(const struct tu_device *dev,
1683 int priority,
1684 uint32_t *queue_id);
1685
1686 void
1687 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1688
1689 uint32_t
1690 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1691 uint32_t
1692 tu_gem_import_dmabuf(const struct tu_device *dev,
1693 int prime_fd,
1694 uint64_t size);
1695 int
1696 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1697 void
1698 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1699 uint64_t
1700 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1701 uint64_t
1702 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1703
1704 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1705 \
1706 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1707 { \
1708 return (struct __tu_type *) _handle; \
1709 } \
1710 \
1711 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1712 { \
1713 return (__VkType) _obj; \
1714 }
1715
1716 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1717 \
1718 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1719 { \
1720 return (struct __tu_type *) (uintptr_t) _handle; \
1721 } \
1722 \
1723 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1724 { \
1725 return (__VkType)(uintptr_t) _obj; \
1726 }
1727
1728 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1729 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1730
1731 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1732 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1733 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1734 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1735 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1736
1737 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1738 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1739 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1740 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1741 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1742 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1743 VkDescriptorSetLayout)
1744 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1745 VkDescriptorUpdateTemplate)
1746 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1747 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1748 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1749 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1750 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1751 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1752 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1753 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1754 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1755 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1756 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1757 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1758 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1759 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1760
1761 #endif /* TU_PRIVATE_H */