d04fe99aad1f2805986bcc2437a335d4b529aeb1
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #define MAX_VBS 32
81 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_RTS 8
83 #define MAX_VSC_PIPES 32
84 #define MAX_VIEWPORTS 1
85 #define MAX_SCISSORS 16
86 #define MAX_DISCARD_RECTANGLES 4
87 #define MAX_PUSH_CONSTANTS_SIZE 128
88 #define MAX_PUSH_DESCRIPTORS 32
89 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
90 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
91 #define MAX_DYNAMIC_BUFFERS \
92 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
93 #define MAX_SAMPLES_LOG2 4
94 #define NUM_META_FS_KEYS 13
95 #define TU_MAX_DRM_DEVICES 8
96 #define MAX_VIEWS 8
97 /* The Qualcomm driver exposes 0x20000058 */
98 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
99
100 #define NUM_DEPTH_CLEAR_PIPELINES 3
101
102 /*
103 * This is the point we switch from using CP to compute shader
104 * for certain buffer operations.
105 */
106 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
107
108 #define A6XX_TEX_CONST_DWORDS 16
109 #define A6XX_TEX_SAMP_DWORDS 4
110
111 enum tu_mem_heap
112 {
113 TU_MEM_HEAP_VRAM,
114 TU_MEM_HEAP_VRAM_CPU_ACCESS,
115 TU_MEM_HEAP_GTT,
116 TU_MEM_HEAP_COUNT
117 };
118
119 enum tu_mem_type
120 {
121 TU_MEM_TYPE_VRAM,
122 TU_MEM_TYPE_GTT_WRITE_COMBINE,
123 TU_MEM_TYPE_VRAM_CPU_ACCESS,
124 TU_MEM_TYPE_GTT_CACHED,
125 TU_MEM_TYPE_COUNT
126 };
127
128 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129
130 static inline uint32_t
131 align_u32(uint32_t v, uint32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline uint32_t
138 align_u32_npot(uint32_t v, uint32_t a)
139 {
140 return (v + a - 1) / a * a;
141 }
142
143 static inline uint64_t
144 align_u64(uint64_t v, uint64_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 static inline int32_t
151 align_i32(int32_t v, int32_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 /** Alignment must be a power of 2. */
158 static inline bool
159 tu_is_aligned(uintmax_t n, uintmax_t a)
160 {
161 assert(a == (a & -a));
162 return (n & (a - 1)) == 0;
163 }
164
165 static inline uint32_t
166 round_up_u32(uint32_t v, uint32_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint64_t
172 round_up_u64(uint64_t v, uint64_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint32_t
178 tu_minify(uint32_t n, uint32_t levels)
179 {
180 if (unlikely(n == 0))
181 return 0;
182 else
183 return MAX2(n >> levels, 1);
184 }
185 static inline float
186 tu_clamp_f(float f, float min, float max)
187 {
188 assert(min < max);
189
190 if (f > max)
191 return max;
192 else if (f < min)
193 return min;
194 else
195 return f;
196 }
197
198 static inline bool
199 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
200 {
201 if (*inout_mask & clear_mask) {
202 *inout_mask &= ~clear_mask;
203 return true;
204 } else {
205 return false;
206 }
207 }
208
209 #define for_each_bit(b, dword) \
210 for (uint32_t __dword = (dword); \
211 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
212
213 #define typed_memcpy(dest, src, count) \
214 ({ \
215 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
216 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 })
218
219 #define COND(bool, val) ((bool) ? (val) : 0)
220
221 /* Whenever we generate an error, pass it through this function. Useful for
222 * debugging, where we can break on it. Only call at error site, not when
223 * propagating errors. Might be useful to plug in a stack trace here.
224 */
225
226 struct tu_instance;
227
228 VkResult
229 __vk_errorf(struct tu_instance *instance,
230 VkResult error,
231 const char *file,
232 int line,
233 const char *format,
234 ...);
235
236 #define vk_error(instance, error) \
237 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
238 #define vk_errorf(instance, error, format, ...) \
239 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
240
241 void
242 __tu_finishme(const char *file, int line, const char *format, ...)
243 tu_printflike(3, 4);
244 void
245 tu_loge(const char *format, ...) tu_printflike(1, 2);
246 void
247 tu_loge_v(const char *format, va_list va);
248 void
249 tu_logi(const char *format, ...) tu_printflike(1, 2);
250 void
251 tu_logi_v(const char *format, va_list va);
252
253 /**
254 * Print a FINISHME message, including its source location.
255 */
256 #define tu_finishme(format, ...) \
257 do { \
258 static bool reported = false; \
259 if (!reported) { \
260 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
261 reported = true; \
262 } \
263 } while (0)
264
265 /* A non-fatal assert. Useful for debugging. */
266 #ifdef DEBUG
267 #define tu_assert(x) \
268 ({ \
269 if (unlikely(!(x))) \
270 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
271 })
272 #else
273 #define tu_assert(x)
274 #endif
275
276 /* Suppress -Wunused in stub functions */
277 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
278 static inline void
279 __tu_use_args(int ignore, ...)
280 {
281 }
282
283 #define tu_stub() \
284 do { \
285 tu_finishme("stub %s", __func__); \
286 } while (0)
287
288 void *
289 tu_lookup_entrypoint_unchecked(const char *name);
290 void *
291 tu_lookup_entrypoint_checked(
292 const char *name,
293 uint32_t core_version,
294 const struct tu_instance_extension_table *instance,
295 const struct tu_device_extension_table *device);
296
297 struct tu_physical_device
298 {
299 VK_LOADER_DATA _loader_data;
300
301 struct tu_instance *instance;
302
303 char path[20];
304 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
305 uint8_t driver_uuid[VK_UUID_SIZE];
306 uint8_t device_uuid[VK_UUID_SIZE];
307 uint8_t cache_uuid[VK_UUID_SIZE];
308
309 struct wsi_device wsi_device;
310
311 int local_fd;
312 int master_fd;
313
314 unsigned gpu_id;
315 uint32_t gmem_size;
316 uint64_t gmem_base;
317 uint32_t tile_align_w;
318 uint32_t tile_align_h;
319
320 struct {
321 uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */
322 uint32_t RB_CCU_CNTL_gmem; /* for GMEM */
323 uint32_t PC_UNKNOWN_9805;
324 uint32_t SP_UNKNOWN_A0F8;
325 } magic;
326
327 /* This is the drivers on-disk cache used as a fallback as opposed to
328 * the pipeline cache defined by apps.
329 */
330 struct disk_cache *disk_cache;
331
332 struct tu_device_extension_table supported_extensions;
333 };
334
335 enum tu_debug_flags
336 {
337 TU_DEBUG_STARTUP = 1 << 0,
338 TU_DEBUG_NIR = 1 << 1,
339 TU_DEBUG_IR3 = 1 << 2,
340 TU_DEBUG_NOBIN = 1 << 3,
341 TU_DEBUG_SYSMEM = 1 << 4,
342 TU_DEBUG_FORCEBIN = 1 << 5,
343 };
344
345 struct tu_instance
346 {
347 VK_LOADER_DATA _loader_data;
348
349 VkAllocationCallbacks alloc;
350
351 uint32_t api_version;
352 int physical_device_count;
353 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
354
355 enum tu_debug_flags debug_flags;
356
357 struct vk_debug_report_instance debug_report_callbacks;
358
359 struct tu_instance_extension_table enabled_extensions;
360 };
361
362 VkResult
363 tu_wsi_init(struct tu_physical_device *physical_device);
364 void
365 tu_wsi_finish(struct tu_physical_device *physical_device);
366
367 bool
368 tu_instance_extension_supported(const char *name);
369 uint32_t
370 tu_physical_device_api_version(struct tu_physical_device *dev);
371 bool
372 tu_physical_device_extension_supported(struct tu_physical_device *dev,
373 const char *name);
374
375 struct cache_entry;
376
377 struct tu_pipeline_cache
378 {
379 struct tu_device *device;
380 pthread_mutex_t mutex;
381
382 uint32_t total_size;
383 uint32_t table_size;
384 uint32_t kernel_count;
385 struct cache_entry **hash_table;
386 bool modified;
387
388 VkAllocationCallbacks alloc;
389 };
390
391 struct tu_pipeline_key
392 {
393 };
394
395 void
396 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
397 struct tu_device *device);
398 void
399 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
400 void
401 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
402 const void *data,
403 size_t size);
404
405 struct tu_shader_variant;
406
407 bool
408 tu_create_shader_variants_from_pipeline_cache(
409 struct tu_device *device,
410 struct tu_pipeline_cache *cache,
411 const unsigned char *sha1,
412 struct tu_shader_variant **variants);
413
414 void
415 tu_pipeline_cache_insert_shaders(struct tu_device *device,
416 struct tu_pipeline_cache *cache,
417 const unsigned char *sha1,
418 struct tu_shader_variant **variants,
419 const void *const *codes,
420 const unsigned *code_sizes);
421
422 struct tu_meta_state
423 {
424 VkAllocationCallbacks alloc;
425
426 struct tu_pipeline_cache cache;
427 };
428
429 /* queue types */
430 #define TU_QUEUE_GENERAL 0
431
432 #define TU_MAX_QUEUE_FAMILIES 1
433
434 struct tu_fence
435 {
436 struct wsi_fence *fence_wsi;
437 bool signaled;
438 int fd;
439 };
440
441 void
442 tu_fence_init(struct tu_fence *fence, bool signaled);
443 void
444 tu_fence_finish(struct tu_fence *fence);
445 void
446 tu_fence_update_fd(struct tu_fence *fence, int fd);
447 void
448 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
449 void
450 tu_fence_signal(struct tu_fence *fence);
451 void
452 tu_fence_wait_idle(struct tu_fence *fence);
453
454 struct tu_queue
455 {
456 VK_LOADER_DATA _loader_data;
457 struct tu_device *device;
458 uint32_t queue_family_index;
459 int queue_idx;
460 VkDeviceQueueCreateFlags flags;
461
462 uint32_t msm_queue_id;
463 struct tu_fence submit_fence;
464 };
465
466 struct tu_bo
467 {
468 uint32_t gem_handle;
469 uint64_t size;
470 uint64_t iova;
471 void *map;
472 };
473
474 struct tu_device
475 {
476 VK_LOADER_DATA _loader_data;
477
478 VkAllocationCallbacks alloc;
479
480 struct tu_instance *instance;
481
482 struct tu_meta_state meta_state;
483
484 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
485 int queue_count[TU_MAX_QUEUE_FAMILIES];
486
487 struct tu_physical_device *physical_device;
488
489 struct ir3_compiler *compiler;
490
491 /* Backup in-memory cache to be used if the app doesn't provide one */
492 struct tu_pipeline_cache *mem_cache;
493
494 struct tu_bo vsc_data;
495 struct tu_bo vsc_data2;
496 uint32_t vsc_data_pitch;
497 uint32_t vsc_data2_pitch;
498
499 struct list_head shader_slabs;
500 mtx_t shader_slab_mutex;
501
502 struct tu_device_extension_table enabled_extensions;
503 };
504
505 VkResult
506 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
507 VkResult
508 tu_bo_init_dmabuf(struct tu_device *dev,
509 struct tu_bo *bo,
510 uint64_t size,
511 int fd);
512 int
513 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
514 void
515 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
516 VkResult
517 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
518
519 struct tu_cs_entry
520 {
521 /* No ownership */
522 const struct tu_bo *bo;
523
524 uint32_t size;
525 uint32_t offset;
526 };
527
528 struct ts_cs_memory {
529 uint32_t *map;
530 uint64_t iova;
531 };
532
533 enum tu_cs_mode
534 {
535
536 /*
537 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
538 * is full. tu_cs_begin must be called before command packet emission and
539 * tu_cs_end must be called after.
540 *
541 * This mode may create multiple entries internally. The entries must be
542 * submitted together.
543 */
544 TU_CS_MODE_GROW,
545
546 /*
547 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
548 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
549 * effect on it.
550 *
551 * This mode does not create any entry or any BO.
552 */
553 TU_CS_MODE_EXTERNAL,
554
555 /*
556 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
557 * command packet emission. tu_cs_begin_sub_stream must be called to get a
558 * sub-stream to emit comamnd packets to. When done with the sub-stream,
559 * tu_cs_end_sub_stream must be called.
560 *
561 * This mode does not create any entry internally.
562 */
563 TU_CS_MODE_SUB_STREAM,
564 };
565
566 struct tu_cs
567 {
568 uint32_t *start;
569 uint32_t *cur;
570 uint32_t *reserved_end;
571 uint32_t *end;
572
573 struct tu_device *device;
574 enum tu_cs_mode mode;
575 uint32_t next_bo_size;
576
577 struct tu_cs_entry *entries;
578 uint32_t entry_count;
579 uint32_t entry_capacity;
580
581 struct tu_bo **bos;
582 uint32_t bo_count;
583 uint32_t bo_capacity;
584
585 /* state for cond_exec_start/cond_exec_end */
586 uint32_t cond_flags;
587 uint32_t *cond_dwords;
588 };
589
590 struct tu_device_memory
591 {
592 struct tu_bo bo;
593 VkDeviceSize size;
594
595 /* for dedicated allocations */
596 struct tu_image *image;
597 struct tu_buffer *buffer;
598
599 uint32_t type_index;
600 void *map;
601 void *user_ptr;
602 };
603
604 struct tu_descriptor_range
605 {
606 uint64_t va;
607 uint32_t size;
608 };
609
610 struct tu_descriptor_set
611 {
612 const struct tu_descriptor_set_layout *layout;
613 uint32_t size;
614
615 uint64_t va;
616 uint32_t *mapped_ptr;
617 struct tu_descriptor_range *dynamic_descriptors;
618
619 struct tu_bo *descriptors[0];
620 };
621
622 struct tu_push_descriptor_set
623 {
624 struct tu_descriptor_set set;
625 uint32_t capacity;
626 };
627
628 struct tu_descriptor_pool_entry
629 {
630 uint32_t offset;
631 uint32_t size;
632 struct tu_descriptor_set *set;
633 };
634
635 struct tu_descriptor_pool
636 {
637 struct tu_bo bo;
638 uint64_t current_offset;
639 uint64_t size;
640
641 uint8_t *host_memory_base;
642 uint8_t *host_memory_ptr;
643 uint8_t *host_memory_end;
644
645 uint32_t entry_count;
646 uint32_t max_entry_count;
647 struct tu_descriptor_pool_entry entries[0];
648 };
649
650 struct tu_descriptor_update_template_entry
651 {
652 VkDescriptorType descriptor_type;
653
654 /* The number of descriptors to update */
655 uint32_t descriptor_count;
656
657 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
658 */
659 uint32_t dst_offset;
660
661 /* In dwords. Not valid/used for dynamic descriptors */
662 uint32_t dst_stride;
663
664 uint32_t buffer_offset;
665
666 /* Only valid for combined image samplers and samplers */
667 uint16_t has_sampler;
668
669 /* In bytes */
670 size_t src_offset;
671 size_t src_stride;
672
673 /* For push descriptors */
674 const uint32_t *immutable_samplers;
675 };
676
677 struct tu_descriptor_update_template
678 {
679 uint32_t entry_count;
680 VkPipelineBindPoint bind_point;
681 struct tu_descriptor_update_template_entry entry[0];
682 };
683
684 struct tu_buffer
685 {
686 VkDeviceSize size;
687
688 VkBufferUsageFlags usage;
689 VkBufferCreateFlags flags;
690
691 struct tu_bo *bo;
692 VkDeviceSize bo_offset;
693 };
694
695 static inline uint64_t
696 tu_buffer_iova(struct tu_buffer *buffer)
697 {
698 return buffer->bo->iova + buffer->bo_offset;
699 }
700
701 enum tu_dynamic_state_bits
702 {
703 TU_DYNAMIC_VIEWPORT = 1 << 0,
704 TU_DYNAMIC_SCISSOR = 1 << 1,
705 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
706 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
707 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
708 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
709 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
710 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
711 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
712 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
713 TU_DYNAMIC_ALL = (1 << 10) - 1,
714 };
715
716 struct tu_vertex_binding
717 {
718 struct tu_buffer *buffer;
719 VkDeviceSize offset;
720 };
721
722 struct tu_viewport_state
723 {
724 uint32_t count;
725 VkViewport viewports[MAX_VIEWPORTS];
726 };
727
728 struct tu_scissor_state
729 {
730 uint32_t count;
731 VkRect2D scissors[MAX_SCISSORS];
732 };
733
734 struct tu_discard_rectangle_state
735 {
736 uint32_t count;
737 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
738 };
739
740 struct tu_dynamic_state
741 {
742 /**
743 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
744 * Defines the set of saved dynamic state.
745 */
746 uint32_t mask;
747
748 struct tu_viewport_state viewport;
749
750 struct tu_scissor_state scissor;
751
752 float line_width;
753
754 struct
755 {
756 float bias;
757 float clamp;
758 float slope;
759 } depth_bias;
760
761 float blend_constants[4];
762
763 struct
764 {
765 float min;
766 float max;
767 } depth_bounds;
768
769 struct
770 {
771 uint32_t front;
772 uint32_t back;
773 } stencil_compare_mask;
774
775 struct
776 {
777 uint32_t front;
778 uint32_t back;
779 } stencil_write_mask;
780
781 struct
782 {
783 uint32_t front;
784 uint32_t back;
785 } stencil_reference;
786
787 struct tu_discard_rectangle_state discard_rectangle;
788 };
789
790 extern const struct tu_dynamic_state default_dynamic_state;
791
792 const char *
793 tu_get_debug_option_name(int id);
794
795 const char *
796 tu_get_perftest_option_name(int id);
797
798 struct tu_descriptor_state
799 {
800 struct tu_descriptor_set *sets[MAX_SETS];
801 uint32_t valid;
802 struct tu_push_descriptor_set push_set;
803 bool push_dirty;
804 uint64_t dynamic_buffers[MAX_DYNAMIC_BUFFERS];
805 };
806
807 struct tu_tile
808 {
809 uint8_t pipe;
810 uint8_t slot;
811 VkOffset2D begin;
812 VkOffset2D end;
813 };
814
815 struct tu_tiling_config
816 {
817 VkRect2D render_area;
818
819 /* position and size of the first tile */
820 VkRect2D tile0;
821 /* number of tiles */
822 VkExtent2D tile_count;
823
824 /* size of the first VSC pipe */
825 VkExtent2D pipe0;
826 /* number of VSC pipes */
827 VkExtent2D pipe_count;
828
829 /* pipe register values */
830 uint32_t pipe_config[MAX_VSC_PIPES];
831 uint32_t pipe_sizes[MAX_VSC_PIPES];
832
833 /* Whether sysmem rendering must be used */
834 bool force_sysmem;
835 };
836
837 enum tu_cmd_dirty_bits
838 {
839 TU_CMD_DIRTY_PIPELINE = 1 << 0,
840 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
841 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
842 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
843 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
844 TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 5,
845
846 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
847 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
848 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
849 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
850 };
851
852 struct tu_streamout_state {
853 uint16_t stride[IR3_MAX_SO_BUFFERS];
854 uint32_t ncomp[IR3_MAX_SO_BUFFERS];
855 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
856 uint32_t prog_count;
857 uint32_t vpc_so_buf_cntl;
858 };
859
860 struct tu_cmd_state
861 {
862 uint32_t dirty;
863
864 struct tu_pipeline *pipeline;
865 struct tu_pipeline *compute_pipeline;
866
867 /* Vertex buffers */
868 struct
869 {
870 struct tu_buffer *buffers[MAX_VBS];
871 VkDeviceSize offsets[MAX_VBS];
872 } vb;
873
874 struct tu_dynamic_state dynamic;
875
876 /* Stream output buffers */
877 struct
878 {
879 struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
880 VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
881 VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
882 } streamout_buf;
883
884 uint8_t streamout_reset;
885 uint8_t streamout_enabled;
886
887 /* Index buffer */
888 struct tu_buffer *index_buffer;
889 uint64_t index_offset;
890 uint32_t index_type;
891 uint32_t max_index_count;
892 uint64_t index_va;
893
894 const struct tu_render_pass *pass;
895 const struct tu_subpass *subpass;
896 const struct tu_framebuffer *framebuffer;
897
898 struct tu_tiling_config tiling_config;
899
900 struct tu_cs_entry tile_store_ib;
901 };
902
903 struct tu_cmd_pool
904 {
905 VkAllocationCallbacks alloc;
906 struct list_head cmd_buffers;
907 struct list_head free_cmd_buffers;
908 uint32_t queue_family_index;
909 };
910
911 struct tu_cmd_buffer_upload
912 {
913 uint8_t *map;
914 unsigned offset;
915 uint64_t size;
916 struct list_head list;
917 };
918
919 enum tu_cmd_buffer_status
920 {
921 TU_CMD_BUFFER_STATUS_INVALID,
922 TU_CMD_BUFFER_STATUS_INITIAL,
923 TU_CMD_BUFFER_STATUS_RECORDING,
924 TU_CMD_BUFFER_STATUS_EXECUTABLE,
925 TU_CMD_BUFFER_STATUS_PENDING,
926 };
927
928 struct tu_bo_list
929 {
930 uint32_t count;
931 uint32_t capacity;
932 struct drm_msm_gem_submit_bo *bo_infos;
933 };
934
935 #define TU_BO_LIST_FAILED (~0)
936
937 void
938 tu_bo_list_init(struct tu_bo_list *list);
939 void
940 tu_bo_list_destroy(struct tu_bo_list *list);
941 void
942 tu_bo_list_reset(struct tu_bo_list *list);
943 uint32_t
944 tu_bo_list_add(struct tu_bo_list *list,
945 const struct tu_bo *bo,
946 uint32_t flags);
947 VkResult
948 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
949
950 struct tu_cmd_buffer
951 {
952 VK_LOADER_DATA _loader_data;
953
954 struct tu_device *device;
955
956 struct tu_cmd_pool *pool;
957 struct list_head pool_link;
958
959 VkCommandBufferUsageFlags usage_flags;
960 VkCommandBufferLevel level;
961 enum tu_cmd_buffer_status status;
962
963 struct tu_cmd_state state;
964 struct tu_vertex_binding vertex_bindings[MAX_VBS];
965 uint32_t queue_family_index;
966
967 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
968 VkShaderStageFlags push_constant_stages;
969 struct tu_descriptor_set meta_push_descriptors;
970
971 struct tu_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
972
973 struct tu_cmd_buffer_upload upload;
974
975 VkResult record_result;
976
977 struct tu_bo_list bo_list;
978 struct tu_cs cs;
979 struct tu_cs draw_cs;
980 struct tu_cs draw_epilogue_cs;
981 struct tu_cs sub_cs;
982
983 struct tu_bo scratch_bo;
984 uint32_t scratch_seqno;
985 #define VSC_OVERFLOW 0x8
986 #define VSC_SCRATCH 0x10
987
988 struct tu_bo vsc_data;
989 struct tu_bo vsc_data2;
990 uint32_t vsc_data_pitch;
991 uint32_t vsc_data2_pitch;
992 bool use_vsc_data;
993
994 bool wait_for_idle;
995 };
996
997 /* Temporary struct for tracking a register state to be written, used by
998 * a6xx-pack.h and tu_cs_emit_regs()
999 */
1000 struct tu_reg_value {
1001 uint32_t reg;
1002 uint64_t value;
1003 bool is_address;
1004 struct tu_bo *bo;
1005 bool bo_write;
1006 uint32_t bo_offset;
1007 uint32_t bo_shift;
1008 };
1009
1010 unsigned
1011 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
1012 struct tu_cs *cs,
1013 enum vgt_event_type event,
1014 bool need_seqno);
1015
1016 bool
1017 tu_get_memory_fd(struct tu_device *device,
1018 struct tu_device_memory *memory,
1019 int *pFD);
1020
1021 static inline struct tu_descriptor_state *
1022 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
1023 VkPipelineBindPoint bind_point)
1024 {
1025 return &cmd_buffer->descriptors[bind_point];
1026 }
1027
1028 /*
1029 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1030 *
1031 * Limitations: Can't call normal dispatch functions without binding or
1032 * rebinding
1033 * the compute pipeline.
1034 */
1035 void
1036 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1037 uint32_t x,
1038 uint32_t y,
1039 uint32_t z);
1040
1041 struct tu_event
1042 {
1043 struct tu_bo bo;
1044 };
1045
1046 struct tu_shader_module;
1047
1048 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1049 #define TU_HASH_SHADER_SISCHED (1 << 1)
1050 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1051 void
1052 tu_hash_shaders(unsigned char *hash,
1053 const VkPipelineShaderStageCreateInfo **stages,
1054 const struct tu_pipeline_layout *layout,
1055 const struct tu_pipeline_key *key,
1056 uint32_t flags);
1057
1058 static inline gl_shader_stage
1059 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1060 {
1061 assert(__builtin_popcount(vk_stage) == 1);
1062 return ffs(vk_stage) - 1;
1063 }
1064
1065 static inline VkShaderStageFlagBits
1066 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1067 {
1068 return (1 << mesa_stage);
1069 }
1070
1071 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1072
1073 #define tu_foreach_stage(stage, stage_bits) \
1074 for (gl_shader_stage stage, \
1075 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1076 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1077
1078 struct tu_shader_module
1079 {
1080 unsigned char sha1[20];
1081
1082 uint32_t code_size;
1083 const uint32_t *code[0];
1084 };
1085
1086 struct tu_shader_compile_options
1087 {
1088 struct ir3_shader_key key;
1089
1090 bool optimize;
1091 bool include_binning_pass;
1092 };
1093
1094 struct tu_descriptor_map
1095 {
1096 /* TODO: avoid fixed size array/justify the size */
1097 unsigned num; /* number of array entries */
1098 unsigned num_desc; /* Number of descriptors (sum of array_size[]) */
1099 int set[128];
1100 int binding[128];
1101 int value[128];
1102 int array_size[128];
1103 };
1104
1105 struct tu_shader
1106 {
1107 struct ir3_shader ir3_shader;
1108
1109 struct tu_descriptor_map texture_map;
1110 struct tu_descriptor_map sampler_map;
1111 struct tu_descriptor_map ubo_map;
1112 struct tu_descriptor_map ssbo_map;
1113 struct tu_descriptor_map image_map;
1114
1115 /* This may be true for vertex shaders. When true, variants[1] is the
1116 * binning variant and binning_binary is non-NULL.
1117 */
1118 bool has_binning_pass;
1119
1120 void *binary;
1121 void *binning_binary;
1122
1123 struct ir3_shader_variant variants[0];
1124 };
1125
1126 struct tu_shader *
1127 tu_shader_create(struct tu_device *dev,
1128 gl_shader_stage stage,
1129 const VkPipelineShaderStageCreateInfo *stage_info,
1130 struct tu_pipeline_layout *layout,
1131 const VkAllocationCallbacks *alloc);
1132
1133 void
1134 tu_shader_destroy(struct tu_device *dev,
1135 struct tu_shader *shader,
1136 const VkAllocationCallbacks *alloc);
1137
1138 void
1139 tu_shader_compile_options_init(
1140 struct tu_shader_compile_options *options,
1141 const VkGraphicsPipelineCreateInfo *pipeline_info);
1142
1143 VkResult
1144 tu_shader_compile(struct tu_device *dev,
1145 struct tu_shader *shader,
1146 const struct tu_shader *next_stage,
1147 const struct tu_shader_compile_options *options,
1148 const VkAllocationCallbacks *alloc);
1149
1150 struct tu_program_descriptor_linkage
1151 {
1152 struct ir3_ubo_analysis_state ubo_state;
1153 struct ir3_const_state const_state;
1154
1155 uint32_t constlen;
1156
1157 struct tu_descriptor_map texture_map;
1158 struct tu_descriptor_map sampler_map;
1159 struct tu_descriptor_map ubo_map;
1160 struct tu_descriptor_map ssbo_map;
1161 struct tu_descriptor_map image_map;
1162 };
1163
1164 struct tu_pipeline
1165 {
1166 struct tu_cs cs;
1167
1168 struct tu_dynamic_state dynamic_state;
1169
1170 struct tu_pipeline_layout *layout;
1171
1172 bool need_indirect_descriptor_sets;
1173 VkShaderStageFlags active_stages;
1174
1175 struct tu_streamout_state streamout;
1176
1177 struct
1178 {
1179 struct tu_bo binary_bo;
1180 struct tu_cs_entry state_ib;
1181 struct tu_cs_entry binning_state_ib;
1182
1183 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1184 } program;
1185
1186 struct
1187 {
1188 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1189 uint16_t strides[MAX_VERTEX_ATTRIBS];
1190 uint16_t offsets[MAX_VERTEX_ATTRIBS];
1191 uint32_t count;
1192
1193 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1194 uint16_t binning_strides[MAX_VERTEX_ATTRIBS];
1195 uint16_t binning_offsets[MAX_VERTEX_ATTRIBS];
1196 uint32_t binning_count;
1197
1198 struct tu_cs_entry state_ib;
1199 struct tu_cs_entry binning_state_ib;
1200 } vi;
1201
1202 struct
1203 {
1204 enum pc_di_primtype primtype;
1205 bool primitive_restart;
1206 } ia;
1207
1208 struct
1209 {
1210 struct tu_cs_entry state_ib;
1211 } vp;
1212
1213 struct
1214 {
1215 uint32_t gras_su_cntl;
1216 struct tu_cs_entry state_ib;
1217 } rast;
1218
1219 struct
1220 {
1221 struct tu_cs_entry state_ib;
1222 } ds;
1223
1224 struct
1225 {
1226 struct tu_cs_entry state_ib;
1227 } blend;
1228
1229 struct
1230 {
1231 uint32_t local_size[3];
1232 } compute;
1233 };
1234
1235 void
1236 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1237
1238 void
1239 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1240
1241 void
1242 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1243 uint32_t gras_su_cntl,
1244 float line_width);
1245
1246 void
1247 tu6_emit_depth_bias(struct tu_cs *cs,
1248 float constant_factor,
1249 float clamp,
1250 float slope_factor);
1251
1252 void
1253 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1254 uint32_t front,
1255 uint32_t back);
1256
1257 void
1258 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1259
1260 void
1261 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1262
1263 void
1264 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1265
1266 struct tu_userdata_info *
1267 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1268 gl_shader_stage stage,
1269 int idx);
1270
1271 struct tu_shader_variant *
1272 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1273
1274 struct tu_graphics_pipeline_create_info
1275 {
1276 bool use_rectlist;
1277 bool db_depth_clear;
1278 bool db_stencil_clear;
1279 bool db_depth_disable_expclear;
1280 bool db_stencil_disable_expclear;
1281 bool db_flush_depth_inplace;
1282 bool db_flush_stencil_inplace;
1283 bool db_resummarize;
1284 uint32_t custom_blend_mode;
1285 };
1286
1287 enum tu_supported_formats {
1288 FMT_VERTEX = 1,
1289 FMT_TEXTURE = 2,
1290 FMT_COLOR = 4,
1291 };
1292
1293 struct tu_native_format
1294 {
1295 enum a6xx_format fmt : 8;
1296 enum a3xx_color_swap swap : 8;
1297 enum tu_supported_formats supported : 8;
1298 };
1299
1300 struct tu_native_format tu6_get_native_format(VkFormat format);
1301 struct tu_native_format tu6_format_vtx(VkFormat format);
1302 enum a6xx_format tu6_format_gmem(VkFormat format);
1303 struct tu_native_format tu6_format_color(VkFormat format, bool tiled);
1304 struct tu_native_format tu6_format_texture(VkFormat format, bool tiled);
1305
1306 void
1307 tu_pack_clear_value(const VkClearValue *val,
1308 VkFormat format,
1309 uint32_t buf[4]);
1310
1311 void
1312 tu_2d_clear_color(const VkClearColorValue *val, VkFormat format, uint32_t buf[4]);
1313
1314 void
1315 tu_2d_clear_zs(const VkClearDepthStencilValue *val, VkFormat format, uint32_t buf[4]);
1316
1317 enum a6xx_2d_ifmt tu6_fmt_to_ifmt(enum a6xx_format fmt);
1318 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1319
1320 struct tu_image_level
1321 {
1322 VkDeviceSize offset;
1323 VkDeviceSize size;
1324 uint32_t pitch;
1325 };
1326
1327 struct tu_image
1328 {
1329 VkImageType type;
1330 /* The original VkFormat provided by the client. This may not match any
1331 * of the actual surface formats.
1332 */
1333 VkFormat vk_format;
1334 VkImageAspectFlags aspects;
1335 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1336 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1337 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1338 VkExtent3D extent;
1339 uint32_t level_count;
1340 uint32_t layer_count;
1341 VkSampleCountFlagBits samples;
1342
1343
1344 uint32_t alignment;
1345
1346 struct fdl_layout layout;
1347
1348 unsigned queue_family_mask;
1349 bool exclusive;
1350 bool shareable;
1351
1352 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1353 VkDeviceMemory owned_memory;
1354
1355 /* Set when bound */
1356 struct tu_bo *bo;
1357 VkDeviceSize bo_offset;
1358 };
1359
1360 unsigned
1361 tu_image_queue_family_mask(const struct tu_image *image,
1362 uint32_t family,
1363 uint32_t queue_family);
1364
1365 static inline uint32_t
1366 tu_get_layerCount(const struct tu_image *image,
1367 const VkImageSubresourceRange *range)
1368 {
1369 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1370 ? image->layer_count - range->baseArrayLayer
1371 : range->layerCount;
1372 }
1373
1374 static inline uint32_t
1375 tu_get_levelCount(const struct tu_image *image,
1376 const VkImageSubresourceRange *range)
1377 {
1378 return range->levelCount == VK_REMAINING_MIP_LEVELS
1379 ? image->level_count - range->baseMipLevel
1380 : range->levelCount;
1381 }
1382
1383 static inline VkDeviceSize
1384 tu_layer_size(struct tu_image *image, int level)
1385 {
1386 return fdl_layer_stride(&image->layout, level);
1387 }
1388
1389 static inline uint32_t
1390 tu_image_stride(struct tu_image *image, int level)
1391 {
1392 return image->layout.slices[level].pitch * image->layout.cpp;
1393 }
1394
1395 static inline uint64_t
1396 tu_image_base(struct tu_image *image, int level, int layer)
1397 {
1398 return image->bo->iova + image->bo_offset +
1399 fdl_surface_offset(&image->layout, level, layer);
1400 }
1401
1402 #define tu_image_base_ref(image, level, layer) \
1403 .bo = image->bo, \
1404 .bo_offset = (image->bo_offset + fdl_surface_offset(&image->layout, \
1405 level, layer))
1406
1407 #define tu_image_view_base_ref(iview) \
1408 tu_image_base_ref(iview->image, iview->base_mip, iview->base_layer)
1409
1410 static inline VkDeviceSize
1411 tu_image_ubwc_size(struct tu_image *image, int level)
1412 {
1413 return image->layout.ubwc_layer_size;
1414 }
1415
1416 static inline uint32_t
1417 tu_image_ubwc_pitch(struct tu_image *image, int level)
1418 {
1419 return image->layout.ubwc_slices[level].pitch;
1420 }
1421
1422 static inline uint64_t
1423 tu_image_ubwc_surface_offset(struct tu_image *image, int level, int layer)
1424 {
1425 return image->layout.ubwc_slices[level].offset +
1426 layer * tu_image_ubwc_size(image, level);
1427 }
1428
1429 static inline uint64_t
1430 tu_image_ubwc_base(struct tu_image *image, int level, int layer)
1431 {
1432 return image->bo->iova + image->bo_offset +
1433 tu_image_ubwc_surface_offset(image, level, layer);
1434 }
1435
1436 #define tu_image_ubwc_base_ref(image, level, layer) \
1437 .bo = image->bo, \
1438 .bo_offset = (image->bo_offset + tu_image_ubwc_surface_offset(image, \
1439 level, layer))
1440
1441 #define tu_image_view_ubwc_base_ref(iview) \
1442 tu_image_ubwc_base_ref(iview->image, iview->base_mip, iview->base_layer)
1443
1444 enum a6xx_tile_mode
1445 tu6_get_image_tile_mode(struct tu_image *image, int level);
1446 enum a3xx_msaa_samples
1447 tu_msaa_samples(uint32_t samples);
1448
1449 struct tu_image_view
1450 {
1451 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1452
1453 VkImageViewType type;
1454 VkImageAspectFlags aspect_mask;
1455 VkFormat vk_format;
1456 uint32_t base_layer;
1457 uint32_t layer_count;
1458 uint32_t base_mip;
1459 uint32_t level_count;
1460 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1461
1462 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1463
1464 /* Descriptor for use as a storage image as opposed to a sampled image.
1465 * This has a few differences for cube maps (e.g. type).
1466 */
1467 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1468 };
1469
1470 struct tu_sampler
1471 {
1472 uint32_t state[A6XX_TEX_SAMP_DWORDS];
1473
1474 bool needs_border;
1475 VkBorderColor border;
1476 };
1477
1478 VkResult
1479 tu_image_create(VkDevice _device,
1480 const VkImageCreateInfo *pCreateInfo,
1481 const VkAllocationCallbacks *alloc,
1482 VkImage *pImage,
1483 uint64_t modifier);
1484
1485 VkResult
1486 tu_image_from_gralloc(VkDevice device_h,
1487 const VkImageCreateInfo *base_info,
1488 const VkNativeBufferANDROID *gralloc_info,
1489 const VkAllocationCallbacks *alloc,
1490 VkImage *out_image_h);
1491
1492 void
1493 tu_image_view_init(struct tu_image_view *view,
1494 struct tu_device *device,
1495 const VkImageViewCreateInfo *pCreateInfo);
1496
1497 struct tu_buffer_view
1498 {
1499 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1500
1501 struct tu_buffer *buffer;
1502 };
1503 void
1504 tu_buffer_view_init(struct tu_buffer_view *view,
1505 struct tu_device *device,
1506 const VkBufferViewCreateInfo *pCreateInfo);
1507
1508 static inline struct VkExtent3D
1509 tu_sanitize_image_extent(const VkImageType imageType,
1510 const struct VkExtent3D imageExtent)
1511 {
1512 switch (imageType) {
1513 case VK_IMAGE_TYPE_1D:
1514 return (VkExtent3D) { imageExtent.width, 1, 1 };
1515 case VK_IMAGE_TYPE_2D:
1516 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1517 case VK_IMAGE_TYPE_3D:
1518 return imageExtent;
1519 default:
1520 unreachable("invalid image type");
1521 }
1522 }
1523
1524 static inline struct VkOffset3D
1525 tu_sanitize_image_offset(const VkImageType imageType,
1526 const struct VkOffset3D imageOffset)
1527 {
1528 switch (imageType) {
1529 case VK_IMAGE_TYPE_1D:
1530 return (VkOffset3D) { imageOffset.x, 0, 0 };
1531 case VK_IMAGE_TYPE_2D:
1532 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1533 case VK_IMAGE_TYPE_3D:
1534 return imageOffset;
1535 default:
1536 unreachable("invalid image type");
1537 }
1538 }
1539
1540 struct tu_attachment_info
1541 {
1542 struct tu_image_view *attachment;
1543 };
1544
1545 struct tu_framebuffer
1546 {
1547 uint32_t width;
1548 uint32_t height;
1549 uint32_t layers;
1550
1551 uint32_t attachment_count;
1552 struct tu_attachment_info attachments[0];
1553 };
1554
1555 struct tu_subpass_attachment
1556 {
1557 uint32_t attachment;
1558 };
1559
1560 struct tu_subpass
1561 {
1562 uint32_t input_count;
1563 uint32_t color_count;
1564 struct tu_subpass_attachment *input_attachments;
1565 struct tu_subpass_attachment *color_attachments;
1566 struct tu_subpass_attachment *resolve_attachments;
1567 struct tu_subpass_attachment depth_stencil_attachment;
1568
1569 VkSampleCountFlagBits samples;
1570 };
1571
1572 struct tu_render_pass_attachment
1573 {
1574 VkFormat format;
1575 uint32_t cpp;
1576 VkAttachmentLoadOp load_op;
1577 VkAttachmentLoadOp stencil_load_op;
1578 VkAttachmentStoreOp store_op;
1579 VkAttachmentStoreOp stencil_store_op;
1580 int32_t gmem_offset;
1581 };
1582
1583 struct tu_render_pass
1584 {
1585 uint32_t attachment_count;
1586 uint32_t subpass_count;
1587 uint32_t gmem_pixels;
1588 struct tu_subpass_attachment *subpass_attachments;
1589 struct tu_render_pass_attachment *attachments;
1590 struct tu_subpass subpasses[0];
1591 };
1592
1593 VkResult
1594 tu_device_init_meta(struct tu_device *device);
1595 void
1596 tu_device_finish_meta(struct tu_device *device);
1597
1598 struct tu_query_pool
1599 {
1600 VkQueryType type;
1601 uint32_t stride;
1602 uint64_t size;
1603 uint32_t pipeline_statistics;
1604 struct tu_bo bo;
1605 };
1606
1607 struct tu_semaphore
1608 {
1609 uint32_t syncobj;
1610 uint32_t temp_syncobj;
1611 };
1612
1613 void
1614 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1615 VkPipelineBindPoint bind_point,
1616 struct tu_descriptor_set *set,
1617 unsigned idx);
1618
1619 void
1620 tu_update_descriptor_sets(struct tu_device *device,
1621 struct tu_cmd_buffer *cmd_buffer,
1622 VkDescriptorSet overrideSet,
1623 uint32_t descriptorWriteCount,
1624 const VkWriteDescriptorSet *pDescriptorWrites,
1625 uint32_t descriptorCopyCount,
1626 const VkCopyDescriptorSet *pDescriptorCopies);
1627
1628 void
1629 tu_update_descriptor_set_with_template(
1630 struct tu_device *device,
1631 struct tu_cmd_buffer *cmd_buffer,
1632 struct tu_descriptor_set *set,
1633 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1634 const void *pData);
1635
1636 void
1637 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1638 VkPipelineBindPoint pipelineBindPoint,
1639 VkPipelineLayout _layout,
1640 uint32_t set,
1641 uint32_t descriptorWriteCount,
1642 const VkWriteDescriptorSet *pDescriptorWrites);
1643
1644 int
1645 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1646
1647 int
1648 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1649
1650 int
1651 tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
1652
1653 int
1654 tu_drm_submitqueue_new(const struct tu_device *dev,
1655 int priority,
1656 uint32_t *queue_id);
1657
1658 void
1659 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1660
1661 uint32_t
1662 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1663 uint32_t
1664 tu_gem_import_dmabuf(const struct tu_device *dev,
1665 int prime_fd,
1666 uint64_t size);
1667 int
1668 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1669 void
1670 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1671 uint64_t
1672 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1673 uint64_t
1674 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1675
1676
1677 void
1678 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1679 struct tu_cs *cs,
1680 uint32_t attachment,
1681 const VkClearValue *value,
1682 const VkClearRect *rect);
1683
1684 void
1685 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1686 struct tu_cs *cs,
1687 uint32_t attachment,
1688 uint8_t component_mask,
1689 const VkClearValue *value);
1690
1691 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1692 \
1693 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1694 { \
1695 return (struct __tu_type *) _handle; \
1696 } \
1697 \
1698 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1699 { \
1700 return (__VkType) _obj; \
1701 }
1702
1703 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1704 \
1705 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1706 { \
1707 return (struct __tu_type *) (uintptr_t) _handle; \
1708 } \
1709 \
1710 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1711 { \
1712 return (__VkType)(uintptr_t) _obj; \
1713 }
1714
1715 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1716 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1717
1718 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1719 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1720 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1721 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1722 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1723
1724 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1725 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1726 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1727 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1728 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1729 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1730 VkDescriptorSetLayout)
1731 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1732 VkDescriptorUpdateTemplate)
1733 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1734 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1735 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1736 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1737 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1738 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1739 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1740 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1741 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1742 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1743 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1744 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1745 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1746 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1747
1748 #endif /* TU_PRIVATE_H */