turnip: Add tu6_control struct.
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #define MAX_VBS 32
81 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_RTS 8
83 #define MAX_VSC_PIPES 32
84 #define MAX_VIEWPORTS 1
85 #define MAX_SCISSORS 16
86 #define MAX_DISCARD_RECTANGLES 4
87 #define MAX_PUSH_CONSTANTS_SIZE 128
88 #define MAX_PUSH_DESCRIPTORS 32
89 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
90 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
91 #define MAX_DYNAMIC_BUFFERS \
92 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
93 #define MAX_SAMPLES_LOG2 4
94 #define NUM_META_FS_KEYS 13
95 #define TU_MAX_DRM_DEVICES 8
96 #define MAX_VIEWS 8
97 /* The Qualcomm driver exposes 0x20000058 */
98 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
99
100 #define NUM_DEPTH_CLEAR_PIPELINES 3
101
102 /*
103 * This is the point we switch from using CP to compute shader
104 * for certain buffer operations.
105 */
106 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
107
108 #define A6XX_TEX_CONST_DWORDS 16
109 #define A6XX_TEX_SAMP_DWORDS 4
110
111 enum tu_mem_heap
112 {
113 TU_MEM_HEAP_VRAM,
114 TU_MEM_HEAP_VRAM_CPU_ACCESS,
115 TU_MEM_HEAP_GTT,
116 TU_MEM_HEAP_COUNT
117 };
118
119 enum tu_mem_type
120 {
121 TU_MEM_TYPE_VRAM,
122 TU_MEM_TYPE_GTT_WRITE_COMBINE,
123 TU_MEM_TYPE_VRAM_CPU_ACCESS,
124 TU_MEM_TYPE_GTT_CACHED,
125 TU_MEM_TYPE_COUNT
126 };
127
128 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129
130 static inline uint32_t
131 align_u32(uint32_t v, uint32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline uint32_t
138 align_u32_npot(uint32_t v, uint32_t a)
139 {
140 return (v + a - 1) / a * a;
141 }
142
143 static inline uint64_t
144 align_u64(uint64_t v, uint64_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 static inline int32_t
151 align_i32(int32_t v, int32_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 /** Alignment must be a power of 2. */
158 static inline bool
159 tu_is_aligned(uintmax_t n, uintmax_t a)
160 {
161 assert(a == (a & -a));
162 return (n & (a - 1)) == 0;
163 }
164
165 static inline uint32_t
166 round_up_u32(uint32_t v, uint32_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint64_t
172 round_up_u64(uint64_t v, uint64_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint32_t
178 tu_minify(uint32_t n, uint32_t levels)
179 {
180 if (unlikely(n == 0))
181 return 0;
182 else
183 return MAX2(n >> levels, 1);
184 }
185 static inline float
186 tu_clamp_f(float f, float min, float max)
187 {
188 assert(min < max);
189
190 if (f > max)
191 return max;
192 else if (f < min)
193 return min;
194 else
195 return f;
196 }
197
198 static inline bool
199 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
200 {
201 if (*inout_mask & clear_mask) {
202 *inout_mask &= ~clear_mask;
203 return true;
204 } else {
205 return false;
206 }
207 }
208
209 #define for_each_bit(b, dword) \
210 for (uint32_t __dword = (dword); \
211 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
212
213 #define typed_memcpy(dest, src, count) \
214 ({ \
215 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
216 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 })
218
219 #define COND(bool, val) ((bool) ? (val) : 0)
220
221 /* Whenever we generate an error, pass it through this function. Useful for
222 * debugging, where we can break on it. Only call at error site, not when
223 * propagating errors. Might be useful to plug in a stack trace here.
224 */
225
226 struct tu_instance;
227
228 VkResult
229 __vk_errorf(struct tu_instance *instance,
230 VkResult error,
231 const char *file,
232 int line,
233 const char *format,
234 ...);
235
236 #define vk_error(instance, error) \
237 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
238 #define vk_errorf(instance, error, format, ...) \
239 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
240
241 void
242 __tu_finishme(const char *file, int line, const char *format, ...)
243 tu_printflike(3, 4);
244 void
245 tu_loge(const char *format, ...) tu_printflike(1, 2);
246 void
247 tu_loge_v(const char *format, va_list va);
248 void
249 tu_logi(const char *format, ...) tu_printflike(1, 2);
250 void
251 tu_logi_v(const char *format, va_list va);
252
253 /**
254 * Print a FINISHME message, including its source location.
255 */
256 #define tu_finishme(format, ...) \
257 do { \
258 static bool reported = false; \
259 if (!reported) { \
260 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
261 reported = true; \
262 } \
263 } while (0)
264
265 /* A non-fatal assert. Useful for debugging. */
266 #ifdef DEBUG
267 #define tu_assert(x) \
268 ({ \
269 if (unlikely(!(x))) \
270 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
271 })
272 #else
273 #define tu_assert(x)
274 #endif
275
276 /* Suppress -Wunused in stub functions */
277 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
278 static inline void
279 __tu_use_args(int ignore, ...)
280 {
281 }
282
283 #define tu_stub() \
284 do { \
285 tu_finishme("stub %s", __func__); \
286 } while (0)
287
288 void *
289 tu_lookup_entrypoint_unchecked(const char *name);
290 void *
291 tu_lookup_entrypoint_checked(
292 const char *name,
293 uint32_t core_version,
294 const struct tu_instance_extension_table *instance,
295 const struct tu_device_extension_table *device);
296
297 struct tu_physical_device
298 {
299 VK_LOADER_DATA _loader_data;
300
301 struct tu_instance *instance;
302
303 char path[20];
304 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
305 uint8_t driver_uuid[VK_UUID_SIZE];
306 uint8_t device_uuid[VK_UUID_SIZE];
307 uint8_t cache_uuid[VK_UUID_SIZE];
308
309 struct wsi_device wsi_device;
310
311 int local_fd;
312 int master_fd;
313
314 unsigned gpu_id;
315 uint32_t gmem_size;
316 uint64_t gmem_base;
317 uint32_t tile_align_w;
318 uint32_t tile_align_h;
319
320 struct {
321 uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */
322 uint32_t RB_CCU_CNTL_gmem; /* for GMEM */
323 uint32_t PC_UNKNOWN_9805;
324 uint32_t SP_UNKNOWN_A0F8;
325 } magic;
326
327 /* This is the drivers on-disk cache used as a fallback as opposed to
328 * the pipeline cache defined by apps.
329 */
330 struct disk_cache *disk_cache;
331
332 struct tu_device_extension_table supported_extensions;
333 };
334
335 enum tu_debug_flags
336 {
337 TU_DEBUG_STARTUP = 1 << 0,
338 TU_DEBUG_NIR = 1 << 1,
339 TU_DEBUG_IR3 = 1 << 2,
340 TU_DEBUG_NOBIN = 1 << 3,
341 TU_DEBUG_SYSMEM = 1 << 4,
342 TU_DEBUG_FORCEBIN = 1 << 5,
343 };
344
345 struct tu_instance
346 {
347 VK_LOADER_DATA _loader_data;
348
349 VkAllocationCallbacks alloc;
350
351 uint32_t api_version;
352 int physical_device_count;
353 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
354
355 enum tu_debug_flags debug_flags;
356
357 struct vk_debug_report_instance debug_report_callbacks;
358
359 struct tu_instance_extension_table enabled_extensions;
360 };
361
362 VkResult
363 tu_wsi_init(struct tu_physical_device *physical_device);
364 void
365 tu_wsi_finish(struct tu_physical_device *physical_device);
366
367 bool
368 tu_instance_extension_supported(const char *name);
369 uint32_t
370 tu_physical_device_api_version(struct tu_physical_device *dev);
371 bool
372 tu_physical_device_extension_supported(struct tu_physical_device *dev,
373 const char *name);
374
375 struct cache_entry;
376
377 struct tu_pipeline_cache
378 {
379 struct tu_device *device;
380 pthread_mutex_t mutex;
381
382 uint32_t total_size;
383 uint32_t table_size;
384 uint32_t kernel_count;
385 struct cache_entry **hash_table;
386 bool modified;
387
388 VkAllocationCallbacks alloc;
389 };
390
391 struct tu_pipeline_key
392 {
393 };
394
395 void
396 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
397 struct tu_device *device);
398 void
399 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
400 void
401 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
402 const void *data,
403 size_t size);
404
405 struct tu_shader_variant;
406
407 bool
408 tu_create_shader_variants_from_pipeline_cache(
409 struct tu_device *device,
410 struct tu_pipeline_cache *cache,
411 const unsigned char *sha1,
412 struct tu_shader_variant **variants);
413
414 void
415 tu_pipeline_cache_insert_shaders(struct tu_device *device,
416 struct tu_pipeline_cache *cache,
417 const unsigned char *sha1,
418 struct tu_shader_variant **variants,
419 const void *const *codes,
420 const unsigned *code_sizes);
421
422 struct tu_meta_state
423 {
424 VkAllocationCallbacks alloc;
425
426 struct tu_pipeline_cache cache;
427 };
428
429 /* queue types */
430 #define TU_QUEUE_GENERAL 0
431
432 #define TU_MAX_QUEUE_FAMILIES 1
433
434 struct tu_fence
435 {
436 struct wsi_fence *fence_wsi;
437 bool signaled;
438 int fd;
439 };
440
441 void
442 tu_fence_init(struct tu_fence *fence, bool signaled);
443 void
444 tu_fence_finish(struct tu_fence *fence);
445 void
446 tu_fence_update_fd(struct tu_fence *fence, int fd);
447 void
448 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
449 void
450 tu_fence_signal(struct tu_fence *fence);
451 void
452 tu_fence_wait_idle(struct tu_fence *fence);
453
454 struct tu_queue
455 {
456 VK_LOADER_DATA _loader_data;
457 struct tu_device *device;
458 uint32_t queue_family_index;
459 int queue_idx;
460 VkDeviceQueueCreateFlags flags;
461
462 uint32_t msm_queue_id;
463 struct tu_fence submit_fence;
464 };
465
466 struct tu_bo
467 {
468 uint32_t gem_handle;
469 uint64_t size;
470 uint64_t iova;
471 void *map;
472 };
473
474 struct tu_device
475 {
476 VK_LOADER_DATA _loader_data;
477
478 VkAllocationCallbacks alloc;
479
480 struct tu_instance *instance;
481
482 struct tu_meta_state meta_state;
483
484 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
485 int queue_count[TU_MAX_QUEUE_FAMILIES];
486
487 struct tu_physical_device *physical_device;
488
489 struct ir3_compiler *compiler;
490
491 /* Backup in-memory cache to be used if the app doesn't provide one */
492 struct tu_pipeline_cache *mem_cache;
493
494 struct tu_bo vsc_data;
495 struct tu_bo vsc_data2;
496 uint32_t vsc_data_pitch;
497 uint32_t vsc_data2_pitch;
498
499 struct list_head shader_slabs;
500 mtx_t shader_slab_mutex;
501
502 struct tu_device_extension_table enabled_extensions;
503 };
504
505 VkResult
506 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
507 VkResult
508 tu_bo_init_dmabuf(struct tu_device *dev,
509 struct tu_bo *bo,
510 uint64_t size,
511 int fd);
512 int
513 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
514 void
515 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
516 VkResult
517 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
518
519 struct tu_cs_entry
520 {
521 /* No ownership */
522 const struct tu_bo *bo;
523
524 uint32_t size;
525 uint32_t offset;
526 };
527
528 struct ts_cs_memory {
529 uint32_t *map;
530 uint64_t iova;
531 };
532
533 enum tu_cs_mode
534 {
535
536 /*
537 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
538 * is full. tu_cs_begin must be called before command packet emission and
539 * tu_cs_end must be called after.
540 *
541 * This mode may create multiple entries internally. The entries must be
542 * submitted together.
543 */
544 TU_CS_MODE_GROW,
545
546 /*
547 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
548 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
549 * effect on it.
550 *
551 * This mode does not create any entry or any BO.
552 */
553 TU_CS_MODE_EXTERNAL,
554
555 /*
556 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
557 * command packet emission. tu_cs_begin_sub_stream must be called to get a
558 * sub-stream to emit comamnd packets to. When done with the sub-stream,
559 * tu_cs_end_sub_stream must be called.
560 *
561 * This mode does not create any entry internally.
562 */
563 TU_CS_MODE_SUB_STREAM,
564 };
565
566 struct tu_cs
567 {
568 uint32_t *start;
569 uint32_t *cur;
570 uint32_t *reserved_end;
571 uint32_t *end;
572
573 struct tu_device *device;
574 enum tu_cs_mode mode;
575 uint32_t next_bo_size;
576
577 struct tu_cs_entry *entries;
578 uint32_t entry_count;
579 uint32_t entry_capacity;
580
581 struct tu_bo **bos;
582 uint32_t bo_count;
583 uint32_t bo_capacity;
584
585 /* state for cond_exec_start/cond_exec_end */
586 uint32_t cond_flags;
587 uint32_t *cond_dwords;
588 };
589
590 struct tu_device_memory
591 {
592 struct tu_bo bo;
593 VkDeviceSize size;
594
595 /* for dedicated allocations */
596 struct tu_image *image;
597 struct tu_buffer *buffer;
598
599 uint32_t type_index;
600 void *map;
601 void *user_ptr;
602 };
603
604 struct tu_descriptor_range
605 {
606 uint64_t va;
607 uint32_t size;
608 };
609
610 struct tu_descriptor_set
611 {
612 const struct tu_descriptor_set_layout *layout;
613 uint32_t size;
614
615 uint64_t va;
616 uint32_t *mapped_ptr;
617 struct tu_descriptor_range *dynamic_descriptors;
618
619 struct tu_bo *descriptors[0];
620 };
621
622 struct tu_push_descriptor_set
623 {
624 struct tu_descriptor_set set;
625 uint32_t capacity;
626 };
627
628 struct tu_descriptor_pool_entry
629 {
630 uint32_t offset;
631 uint32_t size;
632 struct tu_descriptor_set *set;
633 };
634
635 struct tu_descriptor_pool
636 {
637 struct tu_bo bo;
638 uint64_t current_offset;
639 uint64_t size;
640
641 uint8_t *host_memory_base;
642 uint8_t *host_memory_ptr;
643 uint8_t *host_memory_end;
644
645 uint32_t entry_count;
646 uint32_t max_entry_count;
647 struct tu_descriptor_pool_entry entries[0];
648 };
649
650 struct tu_descriptor_update_template_entry
651 {
652 VkDescriptorType descriptor_type;
653
654 /* The number of descriptors to update */
655 uint32_t descriptor_count;
656
657 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
658 */
659 uint32_t dst_offset;
660
661 /* In dwords. Not valid/used for dynamic descriptors */
662 uint32_t dst_stride;
663
664 uint32_t buffer_offset;
665
666 /* Only valid for combined image samplers and samplers */
667 uint16_t has_sampler;
668
669 /* In bytes */
670 size_t src_offset;
671 size_t src_stride;
672
673 /* For push descriptors */
674 const uint32_t *immutable_samplers;
675 };
676
677 struct tu_descriptor_update_template
678 {
679 uint32_t entry_count;
680 VkPipelineBindPoint bind_point;
681 struct tu_descriptor_update_template_entry entry[0];
682 };
683
684 struct tu_buffer
685 {
686 VkDeviceSize size;
687
688 VkBufferUsageFlags usage;
689 VkBufferCreateFlags flags;
690
691 struct tu_bo *bo;
692 VkDeviceSize bo_offset;
693 };
694
695 static inline uint64_t
696 tu_buffer_iova(struct tu_buffer *buffer)
697 {
698 return buffer->bo->iova + buffer->bo_offset;
699 }
700
701 enum tu_dynamic_state_bits
702 {
703 TU_DYNAMIC_VIEWPORT = 1 << 0,
704 TU_DYNAMIC_SCISSOR = 1 << 1,
705 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
706 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
707 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
708 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
709 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
710 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
711 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
712 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
713 TU_DYNAMIC_ALL = (1 << 10) - 1,
714 };
715
716 struct tu_vertex_binding
717 {
718 struct tu_buffer *buffer;
719 VkDeviceSize offset;
720 };
721
722 struct tu_viewport_state
723 {
724 uint32_t count;
725 VkViewport viewports[MAX_VIEWPORTS];
726 };
727
728 struct tu_scissor_state
729 {
730 uint32_t count;
731 VkRect2D scissors[MAX_SCISSORS];
732 };
733
734 struct tu_discard_rectangle_state
735 {
736 uint32_t count;
737 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
738 };
739
740 struct tu_dynamic_state
741 {
742 /**
743 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
744 * Defines the set of saved dynamic state.
745 */
746 uint32_t mask;
747
748 struct tu_viewport_state viewport;
749
750 struct tu_scissor_state scissor;
751
752 float line_width;
753
754 struct
755 {
756 float bias;
757 float clamp;
758 float slope;
759 } depth_bias;
760
761 float blend_constants[4];
762
763 struct
764 {
765 float min;
766 float max;
767 } depth_bounds;
768
769 struct
770 {
771 uint32_t front;
772 uint32_t back;
773 } stencil_compare_mask;
774
775 struct
776 {
777 uint32_t front;
778 uint32_t back;
779 } stencil_write_mask;
780
781 struct
782 {
783 uint32_t front;
784 uint32_t back;
785 } stencil_reference;
786
787 struct tu_discard_rectangle_state discard_rectangle;
788 };
789
790 extern const struct tu_dynamic_state default_dynamic_state;
791
792 const char *
793 tu_get_debug_option_name(int id);
794
795 const char *
796 tu_get_perftest_option_name(int id);
797
798 struct tu_descriptor_state
799 {
800 struct tu_descriptor_set *sets[MAX_SETS];
801 uint32_t valid;
802 struct tu_push_descriptor_set push_set;
803 bool push_dirty;
804 uint64_t dynamic_buffers[MAX_DYNAMIC_BUFFERS];
805 };
806
807 struct tu_tile
808 {
809 uint8_t pipe;
810 uint8_t slot;
811 VkOffset2D begin;
812 VkOffset2D end;
813 };
814
815 struct tu_tiling_config
816 {
817 VkRect2D render_area;
818
819 /* position and size of the first tile */
820 VkRect2D tile0;
821 /* number of tiles */
822 VkExtent2D tile_count;
823
824 /* size of the first VSC pipe */
825 VkExtent2D pipe0;
826 /* number of VSC pipes */
827 VkExtent2D pipe_count;
828
829 /* pipe register values */
830 uint32_t pipe_config[MAX_VSC_PIPES];
831 uint32_t pipe_sizes[MAX_VSC_PIPES];
832
833 /* Whether sysmem rendering must be used */
834 bool force_sysmem;
835 };
836
837 enum tu_cmd_dirty_bits
838 {
839 TU_CMD_DIRTY_PIPELINE = 1 << 0,
840 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
841 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
842 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
843 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
844 TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 5,
845
846 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
847 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
848 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
849 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
850 };
851
852 struct tu_streamout_state {
853 uint16_t stride[IR3_MAX_SO_BUFFERS];
854 uint32_t ncomp[IR3_MAX_SO_BUFFERS];
855 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
856 uint32_t prog_count;
857 uint32_t vpc_so_buf_cntl;
858 };
859
860 struct tu_cmd_state
861 {
862 uint32_t dirty;
863
864 struct tu_pipeline *pipeline;
865 struct tu_pipeline *compute_pipeline;
866
867 /* Vertex buffers */
868 struct
869 {
870 struct tu_buffer *buffers[MAX_VBS];
871 VkDeviceSize offsets[MAX_VBS];
872 } vb;
873
874 struct tu_dynamic_state dynamic;
875
876 /* Stream output buffers */
877 struct
878 {
879 struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
880 VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
881 VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
882 } streamout_buf;
883
884 uint8_t streamout_reset;
885 uint8_t streamout_enabled;
886
887 /* Index buffer */
888 struct tu_buffer *index_buffer;
889 uint64_t index_offset;
890 uint32_t index_type;
891 uint32_t max_index_count;
892 uint64_t index_va;
893
894 const struct tu_render_pass *pass;
895 const struct tu_subpass *subpass;
896 const struct tu_framebuffer *framebuffer;
897
898 struct tu_tiling_config tiling_config;
899
900 struct tu_cs_entry tile_store_ib;
901 };
902
903 struct tu_cmd_pool
904 {
905 VkAllocationCallbacks alloc;
906 struct list_head cmd_buffers;
907 struct list_head free_cmd_buffers;
908 uint32_t queue_family_index;
909 };
910
911 struct tu_cmd_buffer_upload
912 {
913 uint8_t *map;
914 unsigned offset;
915 uint64_t size;
916 struct list_head list;
917 };
918
919 enum tu_cmd_buffer_status
920 {
921 TU_CMD_BUFFER_STATUS_INVALID,
922 TU_CMD_BUFFER_STATUS_INITIAL,
923 TU_CMD_BUFFER_STATUS_RECORDING,
924 TU_CMD_BUFFER_STATUS_EXECUTABLE,
925 TU_CMD_BUFFER_STATUS_PENDING,
926 };
927
928 struct tu_bo_list
929 {
930 uint32_t count;
931 uint32_t capacity;
932 struct drm_msm_gem_submit_bo *bo_infos;
933 };
934
935 #define TU_BO_LIST_FAILED (~0)
936
937 void
938 tu_bo_list_init(struct tu_bo_list *list);
939 void
940 tu_bo_list_destroy(struct tu_bo_list *list);
941 void
942 tu_bo_list_reset(struct tu_bo_list *list);
943 uint32_t
944 tu_bo_list_add(struct tu_bo_list *list,
945 const struct tu_bo *bo,
946 uint32_t flags);
947 VkResult
948 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
949
950 /* This struct defines the layout of the scratch_bo */
951 struct tu6_control
952 {
953 uint32_t seqno; /* seqno for async CP_EVENT_WRITE, etc */
954 uint32_t _pad0;
955 volatile uint32_t vsc_overflow;
956 uint32_t _pad1;
957 /* flag set from cmdstream when VSC overflow detected: */
958 uint32_t vsc_scratch;
959 uint32_t _pad2;
960 uint32_t _pad3;
961 uint32_t _pad4;
962
963 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
964 struct {
965 uint32_t offset;
966 uint32_t pad[7];
967 } flush_base[4];
968 };
969
970 #define ctrl_offset(member) offsetof(struct tu6_control, member)
971
972 struct tu_cmd_buffer
973 {
974 VK_LOADER_DATA _loader_data;
975
976 struct tu_device *device;
977
978 struct tu_cmd_pool *pool;
979 struct list_head pool_link;
980
981 VkCommandBufferUsageFlags usage_flags;
982 VkCommandBufferLevel level;
983 enum tu_cmd_buffer_status status;
984
985 struct tu_cmd_state state;
986 struct tu_vertex_binding vertex_bindings[MAX_VBS];
987 uint32_t queue_family_index;
988
989 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
990 VkShaderStageFlags push_constant_stages;
991 struct tu_descriptor_set meta_push_descriptors;
992
993 struct tu_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
994
995 struct tu_cmd_buffer_upload upload;
996
997 VkResult record_result;
998
999 struct tu_bo_list bo_list;
1000 struct tu_cs cs;
1001 struct tu_cs draw_cs;
1002 struct tu_cs draw_epilogue_cs;
1003 struct tu_cs sub_cs;
1004
1005 struct tu_bo scratch_bo;
1006 uint32_t scratch_seqno;
1007
1008 struct tu_bo vsc_data;
1009 struct tu_bo vsc_data2;
1010 uint32_t vsc_data_pitch;
1011 uint32_t vsc_data2_pitch;
1012 bool use_vsc_data;
1013
1014 bool wait_for_idle;
1015 };
1016
1017 /* Temporary struct for tracking a register state to be written, used by
1018 * a6xx-pack.h and tu_cs_emit_regs()
1019 */
1020 struct tu_reg_value {
1021 uint32_t reg;
1022 uint64_t value;
1023 bool is_address;
1024 struct tu_bo *bo;
1025 bool bo_write;
1026 uint32_t bo_offset;
1027 uint32_t bo_shift;
1028 };
1029
1030 unsigned
1031 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
1032 struct tu_cs *cs,
1033 enum vgt_event_type event,
1034 bool need_seqno);
1035
1036 bool
1037 tu_get_memory_fd(struct tu_device *device,
1038 struct tu_device_memory *memory,
1039 int *pFD);
1040
1041 static inline struct tu_descriptor_state *
1042 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
1043 VkPipelineBindPoint bind_point)
1044 {
1045 return &cmd_buffer->descriptors[bind_point];
1046 }
1047
1048 /*
1049 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1050 *
1051 * Limitations: Can't call normal dispatch functions without binding or
1052 * rebinding
1053 * the compute pipeline.
1054 */
1055 void
1056 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1057 uint32_t x,
1058 uint32_t y,
1059 uint32_t z);
1060
1061 struct tu_event
1062 {
1063 struct tu_bo bo;
1064 };
1065
1066 struct tu_shader_module;
1067
1068 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1069 #define TU_HASH_SHADER_SISCHED (1 << 1)
1070 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1071 void
1072 tu_hash_shaders(unsigned char *hash,
1073 const VkPipelineShaderStageCreateInfo **stages,
1074 const struct tu_pipeline_layout *layout,
1075 const struct tu_pipeline_key *key,
1076 uint32_t flags);
1077
1078 static inline gl_shader_stage
1079 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1080 {
1081 assert(__builtin_popcount(vk_stage) == 1);
1082 return ffs(vk_stage) - 1;
1083 }
1084
1085 static inline VkShaderStageFlagBits
1086 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1087 {
1088 return (1 << mesa_stage);
1089 }
1090
1091 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1092
1093 #define tu_foreach_stage(stage, stage_bits) \
1094 for (gl_shader_stage stage, \
1095 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1096 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1097
1098 struct tu_shader_module
1099 {
1100 unsigned char sha1[20];
1101
1102 uint32_t code_size;
1103 const uint32_t *code[0];
1104 };
1105
1106 struct tu_shader_compile_options
1107 {
1108 struct ir3_shader_key key;
1109
1110 bool optimize;
1111 bool include_binning_pass;
1112 };
1113
1114 struct tu_descriptor_map
1115 {
1116 /* TODO: avoid fixed size array/justify the size */
1117 unsigned num; /* number of array entries */
1118 unsigned num_desc; /* Number of descriptors (sum of array_size[]) */
1119 int set[128];
1120 int binding[128];
1121 int value[128];
1122 int array_size[128];
1123 };
1124
1125 struct tu_shader
1126 {
1127 struct ir3_shader ir3_shader;
1128
1129 struct tu_descriptor_map texture_map;
1130 struct tu_descriptor_map sampler_map;
1131 struct tu_descriptor_map ubo_map;
1132 struct tu_descriptor_map ssbo_map;
1133 struct tu_descriptor_map image_map;
1134
1135 /* This may be true for vertex shaders. When true, variants[1] is the
1136 * binning variant and binning_binary is non-NULL.
1137 */
1138 bool has_binning_pass;
1139
1140 void *binary;
1141 void *binning_binary;
1142
1143 struct ir3_shader_variant variants[0];
1144 };
1145
1146 struct tu_shader *
1147 tu_shader_create(struct tu_device *dev,
1148 gl_shader_stage stage,
1149 const VkPipelineShaderStageCreateInfo *stage_info,
1150 struct tu_pipeline_layout *layout,
1151 const VkAllocationCallbacks *alloc);
1152
1153 void
1154 tu_shader_destroy(struct tu_device *dev,
1155 struct tu_shader *shader,
1156 const VkAllocationCallbacks *alloc);
1157
1158 void
1159 tu_shader_compile_options_init(
1160 struct tu_shader_compile_options *options,
1161 const VkGraphicsPipelineCreateInfo *pipeline_info);
1162
1163 VkResult
1164 tu_shader_compile(struct tu_device *dev,
1165 struct tu_shader *shader,
1166 const struct tu_shader *next_stage,
1167 const struct tu_shader_compile_options *options,
1168 const VkAllocationCallbacks *alloc);
1169
1170 struct tu_program_descriptor_linkage
1171 {
1172 struct ir3_ubo_analysis_state ubo_state;
1173 struct ir3_const_state const_state;
1174
1175 uint32_t constlen;
1176
1177 struct tu_descriptor_map texture_map;
1178 struct tu_descriptor_map sampler_map;
1179 struct tu_descriptor_map ubo_map;
1180 struct tu_descriptor_map ssbo_map;
1181 struct tu_descriptor_map image_map;
1182 };
1183
1184 struct tu_pipeline
1185 {
1186 struct tu_cs cs;
1187
1188 struct tu_dynamic_state dynamic_state;
1189
1190 struct tu_pipeline_layout *layout;
1191
1192 bool need_indirect_descriptor_sets;
1193 VkShaderStageFlags active_stages;
1194
1195 struct tu_streamout_state streamout;
1196
1197 struct
1198 {
1199 struct tu_bo binary_bo;
1200 struct tu_cs_entry state_ib;
1201 struct tu_cs_entry binning_state_ib;
1202
1203 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1204 } program;
1205
1206 struct
1207 {
1208 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1209 uint16_t strides[MAX_VERTEX_ATTRIBS];
1210 uint16_t offsets[MAX_VERTEX_ATTRIBS];
1211 uint32_t count;
1212
1213 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1214 uint16_t binning_strides[MAX_VERTEX_ATTRIBS];
1215 uint16_t binning_offsets[MAX_VERTEX_ATTRIBS];
1216 uint32_t binning_count;
1217
1218 struct tu_cs_entry state_ib;
1219 struct tu_cs_entry binning_state_ib;
1220 } vi;
1221
1222 struct
1223 {
1224 enum pc_di_primtype primtype;
1225 bool primitive_restart;
1226 } ia;
1227
1228 struct
1229 {
1230 struct tu_cs_entry state_ib;
1231 } vp;
1232
1233 struct
1234 {
1235 uint32_t gras_su_cntl;
1236 struct tu_cs_entry state_ib;
1237 } rast;
1238
1239 struct
1240 {
1241 struct tu_cs_entry state_ib;
1242 } ds;
1243
1244 struct
1245 {
1246 struct tu_cs_entry state_ib;
1247 } blend;
1248
1249 struct
1250 {
1251 uint32_t local_size[3];
1252 } compute;
1253 };
1254
1255 void
1256 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1257
1258 void
1259 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1260
1261 void
1262 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1263 uint32_t gras_su_cntl,
1264 float line_width);
1265
1266 void
1267 tu6_emit_depth_bias(struct tu_cs *cs,
1268 float constant_factor,
1269 float clamp,
1270 float slope_factor);
1271
1272 void
1273 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1274 uint32_t front,
1275 uint32_t back);
1276
1277 void
1278 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1279
1280 void
1281 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1282
1283 void
1284 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1285
1286 struct tu_userdata_info *
1287 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1288 gl_shader_stage stage,
1289 int idx);
1290
1291 struct tu_shader_variant *
1292 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1293
1294 struct tu_graphics_pipeline_create_info
1295 {
1296 bool use_rectlist;
1297 bool db_depth_clear;
1298 bool db_stencil_clear;
1299 bool db_depth_disable_expclear;
1300 bool db_stencil_disable_expclear;
1301 bool db_flush_depth_inplace;
1302 bool db_flush_stencil_inplace;
1303 bool db_resummarize;
1304 uint32_t custom_blend_mode;
1305 };
1306
1307 enum tu_supported_formats {
1308 FMT_VERTEX = 1,
1309 FMT_TEXTURE = 2,
1310 FMT_COLOR = 4,
1311 };
1312
1313 struct tu_native_format
1314 {
1315 enum a6xx_format fmt : 8;
1316 enum a3xx_color_swap swap : 8;
1317 enum tu_supported_formats supported : 8;
1318 };
1319
1320 struct tu_native_format tu6_get_native_format(VkFormat format);
1321 struct tu_native_format tu6_format_vtx(VkFormat format);
1322 enum a6xx_format tu6_format_gmem(VkFormat format);
1323 struct tu_native_format tu6_format_color(VkFormat format, bool tiled);
1324 struct tu_native_format tu6_format_texture(VkFormat format, bool tiled);
1325
1326 void
1327 tu_pack_clear_value(const VkClearValue *val,
1328 VkFormat format,
1329 uint32_t buf[4]);
1330
1331 void
1332 tu_2d_clear_color(const VkClearColorValue *val, VkFormat format, uint32_t buf[4]);
1333
1334 void
1335 tu_2d_clear_zs(const VkClearDepthStencilValue *val, VkFormat format, uint32_t buf[4]);
1336
1337 enum a6xx_2d_ifmt tu6_fmt_to_ifmt(enum a6xx_format fmt);
1338 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1339
1340 struct tu_image_level
1341 {
1342 VkDeviceSize offset;
1343 VkDeviceSize size;
1344 uint32_t pitch;
1345 };
1346
1347 struct tu_image
1348 {
1349 VkImageType type;
1350 /* The original VkFormat provided by the client. This may not match any
1351 * of the actual surface formats.
1352 */
1353 VkFormat vk_format;
1354 VkImageAspectFlags aspects;
1355 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1356 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1357 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1358 VkExtent3D extent;
1359 uint32_t level_count;
1360 uint32_t layer_count;
1361 VkSampleCountFlagBits samples;
1362
1363
1364 uint32_t alignment;
1365
1366 struct fdl_layout layout;
1367
1368 unsigned queue_family_mask;
1369 bool exclusive;
1370 bool shareable;
1371
1372 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1373 VkDeviceMemory owned_memory;
1374
1375 /* Set when bound */
1376 struct tu_bo *bo;
1377 VkDeviceSize bo_offset;
1378 };
1379
1380 unsigned
1381 tu_image_queue_family_mask(const struct tu_image *image,
1382 uint32_t family,
1383 uint32_t queue_family);
1384
1385 static inline uint32_t
1386 tu_get_layerCount(const struct tu_image *image,
1387 const VkImageSubresourceRange *range)
1388 {
1389 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1390 ? image->layer_count - range->baseArrayLayer
1391 : range->layerCount;
1392 }
1393
1394 static inline uint32_t
1395 tu_get_levelCount(const struct tu_image *image,
1396 const VkImageSubresourceRange *range)
1397 {
1398 return range->levelCount == VK_REMAINING_MIP_LEVELS
1399 ? image->level_count - range->baseMipLevel
1400 : range->levelCount;
1401 }
1402
1403 static inline VkDeviceSize
1404 tu_layer_size(struct tu_image *image, int level)
1405 {
1406 return fdl_layer_stride(&image->layout, level);
1407 }
1408
1409 static inline uint32_t
1410 tu_image_stride(struct tu_image *image, int level)
1411 {
1412 return image->layout.slices[level].pitch * image->layout.cpp;
1413 }
1414
1415 static inline uint64_t
1416 tu_image_base(struct tu_image *image, int level, int layer)
1417 {
1418 return image->bo->iova + image->bo_offset +
1419 fdl_surface_offset(&image->layout, level, layer);
1420 }
1421
1422 #define tu_image_base_ref(image, level, layer) \
1423 .bo = image->bo, \
1424 .bo_offset = (image->bo_offset + fdl_surface_offset(&image->layout, \
1425 level, layer))
1426
1427 #define tu_image_view_base_ref(iview) \
1428 tu_image_base_ref(iview->image, iview->base_mip, iview->base_layer)
1429
1430 static inline VkDeviceSize
1431 tu_image_ubwc_size(struct tu_image *image, int level)
1432 {
1433 return image->layout.ubwc_layer_size;
1434 }
1435
1436 static inline uint32_t
1437 tu_image_ubwc_pitch(struct tu_image *image, int level)
1438 {
1439 return image->layout.ubwc_slices[level].pitch;
1440 }
1441
1442 static inline uint64_t
1443 tu_image_ubwc_surface_offset(struct tu_image *image, int level, int layer)
1444 {
1445 return image->layout.ubwc_slices[level].offset +
1446 layer * tu_image_ubwc_size(image, level);
1447 }
1448
1449 static inline uint64_t
1450 tu_image_ubwc_base(struct tu_image *image, int level, int layer)
1451 {
1452 return image->bo->iova + image->bo_offset +
1453 tu_image_ubwc_surface_offset(image, level, layer);
1454 }
1455
1456 #define tu_image_ubwc_base_ref(image, level, layer) \
1457 .bo = image->bo, \
1458 .bo_offset = (image->bo_offset + tu_image_ubwc_surface_offset(image, \
1459 level, layer))
1460
1461 #define tu_image_view_ubwc_base_ref(iview) \
1462 tu_image_ubwc_base_ref(iview->image, iview->base_mip, iview->base_layer)
1463
1464 enum a6xx_tile_mode
1465 tu6_get_image_tile_mode(struct tu_image *image, int level);
1466 enum a3xx_msaa_samples
1467 tu_msaa_samples(uint32_t samples);
1468
1469 struct tu_image_view
1470 {
1471 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1472
1473 VkImageViewType type;
1474 VkImageAspectFlags aspect_mask;
1475 VkFormat vk_format;
1476 uint32_t base_layer;
1477 uint32_t layer_count;
1478 uint32_t base_mip;
1479 uint32_t level_count;
1480 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1481
1482 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1483
1484 /* Descriptor for use as a storage image as opposed to a sampled image.
1485 * This has a few differences for cube maps (e.g. type).
1486 */
1487 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1488 };
1489
1490 struct tu_sampler
1491 {
1492 uint32_t state[A6XX_TEX_SAMP_DWORDS];
1493
1494 bool needs_border;
1495 VkBorderColor border;
1496 };
1497
1498 VkResult
1499 tu_image_create(VkDevice _device,
1500 const VkImageCreateInfo *pCreateInfo,
1501 const VkAllocationCallbacks *alloc,
1502 VkImage *pImage,
1503 uint64_t modifier);
1504
1505 VkResult
1506 tu_image_from_gralloc(VkDevice device_h,
1507 const VkImageCreateInfo *base_info,
1508 const VkNativeBufferANDROID *gralloc_info,
1509 const VkAllocationCallbacks *alloc,
1510 VkImage *out_image_h);
1511
1512 void
1513 tu_image_view_init(struct tu_image_view *view,
1514 struct tu_device *device,
1515 const VkImageViewCreateInfo *pCreateInfo);
1516
1517 struct tu_buffer_view
1518 {
1519 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1520
1521 struct tu_buffer *buffer;
1522 };
1523 void
1524 tu_buffer_view_init(struct tu_buffer_view *view,
1525 struct tu_device *device,
1526 const VkBufferViewCreateInfo *pCreateInfo);
1527
1528 static inline struct VkExtent3D
1529 tu_sanitize_image_extent(const VkImageType imageType,
1530 const struct VkExtent3D imageExtent)
1531 {
1532 switch (imageType) {
1533 case VK_IMAGE_TYPE_1D:
1534 return (VkExtent3D) { imageExtent.width, 1, 1 };
1535 case VK_IMAGE_TYPE_2D:
1536 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1537 case VK_IMAGE_TYPE_3D:
1538 return imageExtent;
1539 default:
1540 unreachable("invalid image type");
1541 }
1542 }
1543
1544 static inline struct VkOffset3D
1545 tu_sanitize_image_offset(const VkImageType imageType,
1546 const struct VkOffset3D imageOffset)
1547 {
1548 switch (imageType) {
1549 case VK_IMAGE_TYPE_1D:
1550 return (VkOffset3D) { imageOffset.x, 0, 0 };
1551 case VK_IMAGE_TYPE_2D:
1552 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1553 case VK_IMAGE_TYPE_3D:
1554 return imageOffset;
1555 default:
1556 unreachable("invalid image type");
1557 }
1558 }
1559
1560 struct tu_attachment_info
1561 {
1562 struct tu_image_view *attachment;
1563 };
1564
1565 struct tu_framebuffer
1566 {
1567 uint32_t width;
1568 uint32_t height;
1569 uint32_t layers;
1570
1571 uint32_t attachment_count;
1572 struct tu_attachment_info attachments[0];
1573 };
1574
1575 struct tu_subpass_attachment
1576 {
1577 uint32_t attachment;
1578 };
1579
1580 struct tu_subpass
1581 {
1582 uint32_t input_count;
1583 uint32_t color_count;
1584 struct tu_subpass_attachment *input_attachments;
1585 struct tu_subpass_attachment *color_attachments;
1586 struct tu_subpass_attachment *resolve_attachments;
1587 struct tu_subpass_attachment depth_stencil_attachment;
1588
1589 VkSampleCountFlagBits samples;
1590 };
1591
1592 struct tu_render_pass_attachment
1593 {
1594 VkFormat format;
1595 uint32_t cpp;
1596 VkAttachmentLoadOp load_op;
1597 VkAttachmentLoadOp stencil_load_op;
1598 VkAttachmentStoreOp store_op;
1599 VkAttachmentStoreOp stencil_store_op;
1600 int32_t gmem_offset;
1601 };
1602
1603 struct tu_render_pass
1604 {
1605 uint32_t attachment_count;
1606 uint32_t subpass_count;
1607 uint32_t gmem_pixels;
1608 struct tu_subpass_attachment *subpass_attachments;
1609 struct tu_render_pass_attachment *attachments;
1610 struct tu_subpass subpasses[0];
1611 };
1612
1613 VkResult
1614 tu_device_init_meta(struct tu_device *device);
1615 void
1616 tu_device_finish_meta(struct tu_device *device);
1617
1618 struct tu_query_pool
1619 {
1620 VkQueryType type;
1621 uint32_t stride;
1622 uint64_t size;
1623 uint32_t pipeline_statistics;
1624 struct tu_bo bo;
1625 };
1626
1627 struct tu_semaphore
1628 {
1629 uint32_t syncobj;
1630 uint32_t temp_syncobj;
1631 };
1632
1633 void
1634 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1635 VkPipelineBindPoint bind_point,
1636 struct tu_descriptor_set *set,
1637 unsigned idx);
1638
1639 void
1640 tu_update_descriptor_sets(struct tu_device *device,
1641 struct tu_cmd_buffer *cmd_buffer,
1642 VkDescriptorSet overrideSet,
1643 uint32_t descriptorWriteCount,
1644 const VkWriteDescriptorSet *pDescriptorWrites,
1645 uint32_t descriptorCopyCount,
1646 const VkCopyDescriptorSet *pDescriptorCopies);
1647
1648 void
1649 tu_update_descriptor_set_with_template(
1650 struct tu_device *device,
1651 struct tu_cmd_buffer *cmd_buffer,
1652 struct tu_descriptor_set *set,
1653 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1654 const void *pData);
1655
1656 void
1657 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1658 VkPipelineBindPoint pipelineBindPoint,
1659 VkPipelineLayout _layout,
1660 uint32_t set,
1661 uint32_t descriptorWriteCount,
1662 const VkWriteDescriptorSet *pDescriptorWrites);
1663
1664 int
1665 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1666
1667 int
1668 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1669
1670 int
1671 tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
1672
1673 int
1674 tu_drm_submitqueue_new(const struct tu_device *dev,
1675 int priority,
1676 uint32_t *queue_id);
1677
1678 void
1679 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1680
1681 uint32_t
1682 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1683 uint32_t
1684 tu_gem_import_dmabuf(const struct tu_device *dev,
1685 int prime_fd,
1686 uint64_t size);
1687 int
1688 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1689 void
1690 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1691 uint64_t
1692 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1693 uint64_t
1694 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1695
1696
1697 void
1698 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1699 struct tu_cs *cs,
1700 uint32_t attachment,
1701 const VkClearValue *value,
1702 const VkClearRect *rect);
1703
1704 void
1705 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1706 struct tu_cs *cs,
1707 uint32_t attachment,
1708 uint8_t component_mask,
1709 const VkClearValue *value);
1710
1711 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1712 \
1713 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1714 { \
1715 return (struct __tu_type *) _handle; \
1716 } \
1717 \
1718 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1719 { \
1720 return (__VkType) _obj; \
1721 }
1722
1723 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1724 \
1725 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1726 { \
1727 return (struct __tu_type *) (uintptr_t) _handle; \
1728 } \
1729 \
1730 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1731 { \
1732 return (__VkType)(uintptr_t) _obj; \
1733 }
1734
1735 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1736 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1737
1738 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1739 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1740 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1741 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1742 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1743
1744 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1745 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1746 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1747 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1748 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1749 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1750 VkDescriptorSetLayout)
1751 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1752 VkDescriptorUpdateTemplate)
1753 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1754 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1755 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1756 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1757 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1758 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1759 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1760 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1761 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1762 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1763 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1764 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1765 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1766 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1767
1768 #endif /* TU_PRIVATE_H */