tu: Force sysmem with mipmapped non-aligned linear stores
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #define MAX_VBS 32
81 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_RTS 8
83 #define MAX_VSC_PIPES 32
84 #define MAX_VIEWPORTS 1
85 #define MAX_SCISSORS 16
86 #define MAX_DISCARD_RECTANGLES 4
87 #define MAX_PUSH_CONSTANTS_SIZE 128
88 #define MAX_PUSH_DESCRIPTORS 32
89 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
90 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
91 #define MAX_DYNAMIC_BUFFERS \
92 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
93 #define MAX_SAMPLES_LOG2 4
94 #define NUM_META_FS_KEYS 13
95 #define TU_MAX_DRM_DEVICES 8
96 #define MAX_VIEWS 8
97 /* The Qualcomm driver exposes 0x20000058 */
98 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
99
100 #define NUM_DEPTH_CLEAR_PIPELINES 3
101
102 /*
103 * This is the point we switch from using CP to compute shader
104 * for certain buffer operations.
105 */
106 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
107
108 #define A6XX_TEX_CONST_DWORDS 16
109 #define A6XX_TEX_SAMP_DWORDS 4
110
111 enum tu_mem_heap
112 {
113 TU_MEM_HEAP_VRAM,
114 TU_MEM_HEAP_VRAM_CPU_ACCESS,
115 TU_MEM_HEAP_GTT,
116 TU_MEM_HEAP_COUNT
117 };
118
119 enum tu_mem_type
120 {
121 TU_MEM_TYPE_VRAM,
122 TU_MEM_TYPE_GTT_WRITE_COMBINE,
123 TU_MEM_TYPE_VRAM_CPU_ACCESS,
124 TU_MEM_TYPE_GTT_CACHED,
125 TU_MEM_TYPE_COUNT
126 };
127
128 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129
130 static inline uint32_t
131 align_u32(uint32_t v, uint32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline uint32_t
138 align_u32_npot(uint32_t v, uint32_t a)
139 {
140 return (v + a - 1) / a * a;
141 }
142
143 static inline uint64_t
144 align_u64(uint64_t v, uint64_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 static inline int32_t
151 align_i32(int32_t v, int32_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 /** Alignment must be a power of 2. */
158 static inline bool
159 tu_is_aligned(uintmax_t n, uintmax_t a)
160 {
161 assert(a == (a & -a));
162 return (n & (a - 1)) == 0;
163 }
164
165 static inline uint32_t
166 round_up_u32(uint32_t v, uint32_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint64_t
172 round_up_u64(uint64_t v, uint64_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint32_t
178 tu_minify(uint32_t n, uint32_t levels)
179 {
180 if (unlikely(n == 0))
181 return 0;
182 else
183 return MAX2(n >> levels, 1);
184 }
185 static inline float
186 tu_clamp_f(float f, float min, float max)
187 {
188 assert(min < max);
189
190 if (f > max)
191 return max;
192 else if (f < min)
193 return min;
194 else
195 return f;
196 }
197
198 static inline bool
199 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
200 {
201 if (*inout_mask & clear_mask) {
202 *inout_mask &= ~clear_mask;
203 return true;
204 } else {
205 return false;
206 }
207 }
208
209 #define for_each_bit(b, dword) \
210 for (uint32_t __dword = (dword); \
211 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
212
213 #define typed_memcpy(dest, src, count) \
214 ({ \
215 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
216 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 })
218
219 #define COND(bool, val) ((bool) ? (val) : 0)
220
221 /* Whenever we generate an error, pass it through this function. Useful for
222 * debugging, where we can break on it. Only call at error site, not when
223 * propagating errors. Might be useful to plug in a stack trace here.
224 */
225
226 struct tu_instance;
227
228 VkResult
229 __vk_errorf(struct tu_instance *instance,
230 VkResult error,
231 const char *file,
232 int line,
233 const char *format,
234 ...);
235
236 #define vk_error(instance, error) \
237 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
238 #define vk_errorf(instance, error, format, ...) \
239 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
240
241 void
242 __tu_finishme(const char *file, int line, const char *format, ...)
243 tu_printflike(3, 4);
244 void
245 tu_loge(const char *format, ...) tu_printflike(1, 2);
246 void
247 tu_loge_v(const char *format, va_list va);
248 void
249 tu_logi(const char *format, ...) tu_printflike(1, 2);
250 void
251 tu_logi_v(const char *format, va_list va);
252
253 /**
254 * Print a FINISHME message, including its source location.
255 */
256 #define tu_finishme(format, ...) \
257 do { \
258 static bool reported = false; \
259 if (!reported) { \
260 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
261 reported = true; \
262 } \
263 } while (0)
264
265 /* A non-fatal assert. Useful for debugging. */
266 #ifdef DEBUG
267 #define tu_assert(x) \
268 ({ \
269 if (unlikely(!(x))) \
270 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
271 })
272 #else
273 #define tu_assert(x)
274 #endif
275
276 /* Suppress -Wunused in stub functions */
277 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
278 static inline void
279 __tu_use_args(int ignore, ...)
280 {
281 }
282
283 #define tu_stub() \
284 do { \
285 tu_finishme("stub %s", __func__); \
286 } while (0)
287
288 void *
289 tu_lookup_entrypoint_unchecked(const char *name);
290 void *
291 tu_lookup_entrypoint_checked(
292 const char *name,
293 uint32_t core_version,
294 const struct tu_instance_extension_table *instance,
295 const struct tu_device_extension_table *device);
296
297 struct tu_physical_device
298 {
299 VK_LOADER_DATA _loader_data;
300
301 struct tu_instance *instance;
302
303 char path[20];
304 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
305 uint8_t driver_uuid[VK_UUID_SIZE];
306 uint8_t device_uuid[VK_UUID_SIZE];
307 uint8_t cache_uuid[VK_UUID_SIZE];
308
309 struct wsi_device wsi_device;
310
311 int local_fd;
312 int master_fd;
313
314 unsigned gpu_id;
315 uint32_t gmem_size;
316 uint32_t tile_align_w;
317 uint32_t tile_align_h;
318
319 struct {
320 uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */
321 uint32_t RB_CCU_CNTL_gmem; /* for GMEM */
322 uint32_t PC_UNKNOWN_9805;
323 uint32_t SP_UNKNOWN_A0F8;
324 } magic;
325
326 /* This is the drivers on-disk cache used as a fallback as opposed to
327 * the pipeline cache defined by apps.
328 */
329 struct disk_cache *disk_cache;
330
331 struct tu_device_extension_table supported_extensions;
332 };
333
334 enum tu_debug_flags
335 {
336 TU_DEBUG_STARTUP = 1 << 0,
337 TU_DEBUG_NIR = 1 << 1,
338 TU_DEBUG_IR3 = 1 << 2,
339 TU_DEBUG_NOBIN = 1 << 3,
340 TU_DEBUG_SYSMEM = 1 << 4,
341 };
342
343 struct tu_instance
344 {
345 VK_LOADER_DATA _loader_data;
346
347 VkAllocationCallbacks alloc;
348
349 uint32_t api_version;
350 int physical_device_count;
351 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
352
353 enum tu_debug_flags debug_flags;
354
355 struct vk_debug_report_instance debug_report_callbacks;
356
357 struct tu_instance_extension_table enabled_extensions;
358 };
359
360 VkResult
361 tu_wsi_init(struct tu_physical_device *physical_device);
362 void
363 tu_wsi_finish(struct tu_physical_device *physical_device);
364
365 bool
366 tu_instance_extension_supported(const char *name);
367 uint32_t
368 tu_physical_device_api_version(struct tu_physical_device *dev);
369 bool
370 tu_physical_device_extension_supported(struct tu_physical_device *dev,
371 const char *name);
372
373 struct cache_entry;
374
375 struct tu_pipeline_cache
376 {
377 struct tu_device *device;
378 pthread_mutex_t mutex;
379
380 uint32_t total_size;
381 uint32_t table_size;
382 uint32_t kernel_count;
383 struct cache_entry **hash_table;
384 bool modified;
385
386 VkAllocationCallbacks alloc;
387 };
388
389 struct tu_pipeline_key
390 {
391 };
392
393 void
394 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
395 struct tu_device *device);
396 void
397 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
398 void
399 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
400 const void *data,
401 size_t size);
402
403 struct tu_shader_variant;
404
405 bool
406 tu_create_shader_variants_from_pipeline_cache(
407 struct tu_device *device,
408 struct tu_pipeline_cache *cache,
409 const unsigned char *sha1,
410 struct tu_shader_variant **variants);
411
412 void
413 tu_pipeline_cache_insert_shaders(struct tu_device *device,
414 struct tu_pipeline_cache *cache,
415 const unsigned char *sha1,
416 struct tu_shader_variant **variants,
417 const void *const *codes,
418 const unsigned *code_sizes);
419
420 struct tu_meta_state
421 {
422 VkAllocationCallbacks alloc;
423
424 struct tu_pipeline_cache cache;
425 };
426
427 /* queue types */
428 #define TU_QUEUE_GENERAL 0
429
430 #define TU_MAX_QUEUE_FAMILIES 1
431
432 struct tu_fence
433 {
434 struct wsi_fence *fence_wsi;
435 bool signaled;
436 int fd;
437 };
438
439 void
440 tu_fence_init(struct tu_fence *fence, bool signaled);
441 void
442 tu_fence_finish(struct tu_fence *fence);
443 void
444 tu_fence_update_fd(struct tu_fence *fence, int fd);
445 void
446 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
447 void
448 tu_fence_signal(struct tu_fence *fence);
449 void
450 tu_fence_wait_idle(struct tu_fence *fence);
451
452 struct tu_queue
453 {
454 VK_LOADER_DATA _loader_data;
455 struct tu_device *device;
456 uint32_t queue_family_index;
457 int queue_idx;
458 VkDeviceQueueCreateFlags flags;
459
460 uint32_t msm_queue_id;
461 struct tu_fence submit_fence;
462 };
463
464 struct tu_bo
465 {
466 uint32_t gem_handle;
467 uint64_t size;
468 uint64_t iova;
469 void *map;
470 };
471
472 struct tu_device
473 {
474 VK_LOADER_DATA _loader_data;
475
476 VkAllocationCallbacks alloc;
477
478 struct tu_instance *instance;
479
480 struct tu_meta_state meta_state;
481
482 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
483 int queue_count[TU_MAX_QUEUE_FAMILIES];
484
485 struct tu_physical_device *physical_device;
486
487 struct ir3_compiler *compiler;
488
489 /* Backup in-memory cache to be used if the app doesn't provide one */
490 struct tu_pipeline_cache *mem_cache;
491
492 struct tu_bo vsc_data;
493 struct tu_bo vsc_data2;
494 uint32_t vsc_data_pitch;
495 uint32_t vsc_data2_pitch;
496
497 struct list_head shader_slabs;
498 mtx_t shader_slab_mutex;
499
500 struct tu_device_extension_table enabled_extensions;
501 };
502
503 VkResult
504 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
505 VkResult
506 tu_bo_init_dmabuf(struct tu_device *dev,
507 struct tu_bo *bo,
508 uint64_t size,
509 int fd);
510 int
511 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
512 void
513 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
514 VkResult
515 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
516
517 struct tu_cs_entry
518 {
519 /* No ownership */
520 const struct tu_bo *bo;
521
522 uint32_t size;
523 uint32_t offset;
524 };
525
526 struct ts_cs_memory {
527 uint32_t *map;
528 uint64_t iova;
529 };
530
531 enum tu_cs_mode
532 {
533
534 /*
535 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
536 * is full. tu_cs_begin must be called before command packet emission and
537 * tu_cs_end must be called after.
538 *
539 * This mode may create multiple entries internally. The entries must be
540 * submitted together.
541 */
542 TU_CS_MODE_GROW,
543
544 /*
545 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
546 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
547 * effect on it.
548 *
549 * This mode does not create any entry or any BO.
550 */
551 TU_CS_MODE_EXTERNAL,
552
553 /*
554 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
555 * command packet emission. tu_cs_begin_sub_stream must be called to get a
556 * sub-stream to emit comamnd packets to. When done with the sub-stream,
557 * tu_cs_end_sub_stream must be called.
558 *
559 * This mode does not create any entry internally.
560 */
561 TU_CS_MODE_SUB_STREAM,
562 };
563
564 struct tu_cs
565 {
566 uint32_t *start;
567 uint32_t *cur;
568 uint32_t *reserved_end;
569 uint32_t *end;
570
571 enum tu_cs_mode mode;
572 uint32_t next_bo_size;
573
574 struct tu_cs_entry *entries;
575 uint32_t entry_count;
576 uint32_t entry_capacity;
577
578 struct tu_bo **bos;
579 uint32_t bo_count;
580 uint32_t bo_capacity;
581 };
582
583 struct tu_device_memory
584 {
585 struct tu_bo bo;
586 VkDeviceSize size;
587
588 /* for dedicated allocations */
589 struct tu_image *image;
590 struct tu_buffer *buffer;
591
592 uint32_t type_index;
593 void *map;
594 void *user_ptr;
595 };
596
597 struct tu_descriptor_range
598 {
599 uint64_t va;
600 uint32_t size;
601 };
602
603 struct tu_descriptor_set
604 {
605 const struct tu_descriptor_set_layout *layout;
606 uint32_t size;
607
608 uint64_t va;
609 uint32_t *mapped_ptr;
610 struct tu_descriptor_range *dynamic_descriptors;
611
612 struct tu_bo *descriptors[0];
613 };
614
615 struct tu_push_descriptor_set
616 {
617 struct tu_descriptor_set set;
618 uint32_t capacity;
619 };
620
621 struct tu_descriptor_pool_entry
622 {
623 uint32_t offset;
624 uint32_t size;
625 struct tu_descriptor_set *set;
626 };
627
628 struct tu_descriptor_pool
629 {
630 struct tu_bo bo;
631 uint64_t current_offset;
632 uint64_t size;
633
634 uint8_t *host_memory_base;
635 uint8_t *host_memory_ptr;
636 uint8_t *host_memory_end;
637
638 uint32_t entry_count;
639 uint32_t max_entry_count;
640 struct tu_descriptor_pool_entry entries[0];
641 };
642
643 struct tu_descriptor_update_template_entry
644 {
645 VkDescriptorType descriptor_type;
646
647 /* The number of descriptors to update */
648 uint32_t descriptor_count;
649
650 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
651 */
652 uint32_t dst_offset;
653
654 /* In dwords. Not valid/used for dynamic descriptors */
655 uint32_t dst_stride;
656
657 uint32_t buffer_offset;
658
659 /* Only valid for combined image samplers and samplers */
660 uint16_t has_sampler;
661
662 /* In bytes */
663 size_t src_offset;
664 size_t src_stride;
665
666 /* For push descriptors */
667 const uint32_t *immutable_samplers;
668 };
669
670 struct tu_descriptor_update_template
671 {
672 uint32_t entry_count;
673 VkPipelineBindPoint bind_point;
674 struct tu_descriptor_update_template_entry entry[0];
675 };
676
677 struct tu_buffer
678 {
679 VkDeviceSize size;
680
681 VkBufferUsageFlags usage;
682 VkBufferCreateFlags flags;
683
684 struct tu_bo *bo;
685 VkDeviceSize bo_offset;
686 };
687
688 static inline uint64_t
689 tu_buffer_iova(struct tu_buffer *buffer)
690 {
691 return buffer->bo->iova + buffer->bo_offset;
692 }
693
694 enum tu_dynamic_state_bits
695 {
696 TU_DYNAMIC_VIEWPORT = 1 << 0,
697 TU_DYNAMIC_SCISSOR = 1 << 1,
698 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
699 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
700 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
701 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
702 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
703 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
704 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
705 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
706 TU_DYNAMIC_ALL = (1 << 10) - 1,
707 };
708
709 struct tu_vertex_binding
710 {
711 struct tu_buffer *buffer;
712 VkDeviceSize offset;
713 };
714
715 struct tu_viewport_state
716 {
717 uint32_t count;
718 VkViewport viewports[MAX_VIEWPORTS];
719 };
720
721 struct tu_scissor_state
722 {
723 uint32_t count;
724 VkRect2D scissors[MAX_SCISSORS];
725 };
726
727 struct tu_discard_rectangle_state
728 {
729 uint32_t count;
730 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
731 };
732
733 struct tu_dynamic_state
734 {
735 /**
736 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
737 * Defines the set of saved dynamic state.
738 */
739 uint32_t mask;
740
741 struct tu_viewport_state viewport;
742
743 struct tu_scissor_state scissor;
744
745 float line_width;
746
747 struct
748 {
749 float bias;
750 float clamp;
751 float slope;
752 } depth_bias;
753
754 float blend_constants[4];
755
756 struct
757 {
758 float min;
759 float max;
760 } depth_bounds;
761
762 struct
763 {
764 uint32_t front;
765 uint32_t back;
766 } stencil_compare_mask;
767
768 struct
769 {
770 uint32_t front;
771 uint32_t back;
772 } stencil_write_mask;
773
774 struct
775 {
776 uint32_t front;
777 uint32_t back;
778 } stencil_reference;
779
780 struct tu_discard_rectangle_state discard_rectangle;
781 };
782
783 extern const struct tu_dynamic_state default_dynamic_state;
784
785 const char *
786 tu_get_debug_option_name(int id);
787
788 const char *
789 tu_get_perftest_option_name(int id);
790
791 struct tu_descriptor_state
792 {
793 struct tu_descriptor_set *sets[MAX_SETS];
794 uint32_t valid;
795 struct tu_push_descriptor_set push_set;
796 bool push_dirty;
797 uint64_t dynamic_buffers[MAX_DYNAMIC_BUFFERS];
798 };
799
800 struct tu_tile
801 {
802 uint8_t pipe;
803 uint8_t slot;
804 VkOffset2D begin;
805 VkOffset2D end;
806 };
807
808 struct tu_tiling_config
809 {
810 VkRect2D render_area;
811
812 /* position and size of the first tile */
813 VkRect2D tile0;
814 /* number of tiles */
815 VkExtent2D tile_count;
816
817 /* size of the first VSC pipe */
818 VkExtent2D pipe0;
819 /* number of VSC pipes */
820 VkExtent2D pipe_count;
821
822 /* pipe register values */
823 uint32_t pipe_config[MAX_VSC_PIPES];
824 uint32_t pipe_sizes[MAX_VSC_PIPES];
825
826 /* Whether sysmem rendering must be used */
827 bool force_sysmem;
828 };
829
830 enum tu_cmd_dirty_bits
831 {
832 TU_CMD_DIRTY_PIPELINE = 1 << 0,
833 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
834 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
835 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
836 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
837
838 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
839 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
840 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
841 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
842 };
843
844 struct tu_cmd_state
845 {
846 uint32_t dirty;
847
848 struct tu_pipeline *pipeline;
849 struct tu_pipeline *compute_pipeline;
850
851 /* Vertex buffers */
852 struct
853 {
854 struct tu_buffer *buffers[MAX_VBS];
855 VkDeviceSize offsets[MAX_VBS];
856 } vb;
857
858 struct tu_dynamic_state dynamic;
859
860 /* Index buffer */
861 struct tu_buffer *index_buffer;
862 uint64_t index_offset;
863 uint32_t index_type;
864 uint32_t max_index_count;
865 uint64_t index_va;
866
867 const struct tu_render_pass *pass;
868 const struct tu_subpass *subpass;
869 const struct tu_framebuffer *framebuffer;
870
871 struct tu_tiling_config tiling_config;
872
873 struct tu_cs_entry tile_load_ib;
874 struct tu_cs_entry tile_store_ib;
875 struct tu_cs_entry sysmem_clear_ib;
876 };
877
878 struct tu_cmd_pool
879 {
880 VkAllocationCallbacks alloc;
881 struct list_head cmd_buffers;
882 struct list_head free_cmd_buffers;
883 uint32_t queue_family_index;
884 };
885
886 struct tu_cmd_buffer_upload
887 {
888 uint8_t *map;
889 unsigned offset;
890 uint64_t size;
891 struct list_head list;
892 };
893
894 enum tu_cmd_buffer_status
895 {
896 TU_CMD_BUFFER_STATUS_INVALID,
897 TU_CMD_BUFFER_STATUS_INITIAL,
898 TU_CMD_BUFFER_STATUS_RECORDING,
899 TU_CMD_BUFFER_STATUS_EXECUTABLE,
900 TU_CMD_BUFFER_STATUS_PENDING,
901 };
902
903 struct tu_bo_list
904 {
905 uint32_t count;
906 uint32_t capacity;
907 struct drm_msm_gem_submit_bo *bo_infos;
908 };
909
910 #define TU_BO_LIST_FAILED (~0)
911
912 void
913 tu_bo_list_init(struct tu_bo_list *list);
914 void
915 tu_bo_list_destroy(struct tu_bo_list *list);
916 void
917 tu_bo_list_reset(struct tu_bo_list *list);
918 uint32_t
919 tu_bo_list_add(struct tu_bo_list *list,
920 const struct tu_bo *bo,
921 uint32_t flags);
922 VkResult
923 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
924
925 struct tu_cmd_buffer
926 {
927 VK_LOADER_DATA _loader_data;
928
929 struct tu_device *device;
930
931 struct tu_cmd_pool *pool;
932 struct list_head pool_link;
933
934 VkCommandBufferUsageFlags usage_flags;
935 VkCommandBufferLevel level;
936 enum tu_cmd_buffer_status status;
937
938 struct tu_cmd_state state;
939 struct tu_vertex_binding vertex_bindings[MAX_VBS];
940 uint32_t queue_family_index;
941
942 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
943 VkShaderStageFlags push_constant_stages;
944 struct tu_descriptor_set meta_push_descriptors;
945
946 struct tu_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
947
948 struct tu_cmd_buffer_upload upload;
949
950 VkResult record_result;
951
952 struct tu_bo_list bo_list;
953 struct tu_cs cs;
954 struct tu_cs draw_cs;
955 struct tu_cs draw_epilogue_cs;
956 struct tu_cs sub_cs;
957
958 uint16_t marker_reg;
959 uint32_t marker_seqno;
960
961 struct tu_bo scratch_bo;
962 uint32_t scratch_seqno;
963 #define VSC_OVERFLOW 0x8
964 #define VSC_SCRATCH 0x10
965
966 struct tu_bo vsc_data;
967 struct tu_bo vsc_data2;
968 uint32_t vsc_data_pitch;
969 uint32_t vsc_data2_pitch;
970 bool use_vsc_data;
971
972 bool wait_for_idle;
973 };
974
975 /* Temporary struct for tracking a register state to be written, used by
976 * a6xx-pack.h and tu_cs_emit_regs()
977 */
978 struct tu_reg_value {
979 uint32_t reg;
980 uint64_t value;
981 bool is_address;
982 struct tu_bo *bo;
983 bool bo_write;
984 uint32_t bo_offset;
985 uint32_t bo_shift;
986 };
987
988 unsigned
989 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
990 struct tu_cs *cs,
991 enum vgt_event_type event,
992 bool need_seqno);
993
994 bool
995 tu_get_memory_fd(struct tu_device *device,
996 struct tu_device_memory *memory,
997 int *pFD);
998
999 static inline struct tu_descriptor_state *
1000 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
1001 VkPipelineBindPoint bind_point)
1002 {
1003 return &cmd_buffer->descriptors[bind_point];
1004 }
1005
1006 /*
1007 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1008 *
1009 * Limitations: Can't call normal dispatch functions without binding or
1010 * rebinding
1011 * the compute pipeline.
1012 */
1013 void
1014 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1015 uint32_t x,
1016 uint32_t y,
1017 uint32_t z);
1018
1019 struct tu_event
1020 {
1021 struct tu_bo bo;
1022 };
1023
1024 struct tu_shader_module;
1025
1026 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1027 #define TU_HASH_SHADER_SISCHED (1 << 1)
1028 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1029 void
1030 tu_hash_shaders(unsigned char *hash,
1031 const VkPipelineShaderStageCreateInfo **stages,
1032 const struct tu_pipeline_layout *layout,
1033 const struct tu_pipeline_key *key,
1034 uint32_t flags);
1035
1036 static inline gl_shader_stage
1037 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1038 {
1039 assert(__builtin_popcount(vk_stage) == 1);
1040 return ffs(vk_stage) - 1;
1041 }
1042
1043 static inline VkShaderStageFlagBits
1044 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1045 {
1046 return (1 << mesa_stage);
1047 }
1048
1049 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1050
1051 #define tu_foreach_stage(stage, stage_bits) \
1052 for (gl_shader_stage stage, \
1053 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1054 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1055
1056 struct tu_shader_module
1057 {
1058 unsigned char sha1[20];
1059
1060 uint32_t code_size;
1061 const uint32_t *code[0];
1062 };
1063
1064 struct tu_shader_compile_options
1065 {
1066 struct ir3_shader_key key;
1067
1068 bool optimize;
1069 bool include_binning_pass;
1070 };
1071
1072 struct tu_descriptor_map
1073 {
1074 /* TODO: avoid fixed size array/justify the size */
1075 unsigned num; /* number of array entries */
1076 unsigned num_desc; /* Number of descriptors (sum of array_size[]) */
1077 int set[64];
1078 int binding[64];
1079 int value[64];
1080 int array_size[64];
1081 };
1082
1083 struct tu_shader
1084 {
1085 struct ir3_shader ir3_shader;
1086
1087 struct tu_descriptor_map texture_map;
1088 struct tu_descriptor_map sampler_map;
1089 struct tu_descriptor_map ubo_map;
1090 struct tu_descriptor_map ssbo_map;
1091 struct tu_descriptor_map image_map;
1092
1093 /* This may be true for vertex shaders. When true, variants[1] is the
1094 * binning variant and binning_binary is non-NULL.
1095 */
1096 bool has_binning_pass;
1097
1098 void *binary;
1099 void *binning_binary;
1100
1101 struct ir3_shader_variant variants[0];
1102 };
1103
1104 struct tu_shader *
1105 tu_shader_create(struct tu_device *dev,
1106 gl_shader_stage stage,
1107 const VkPipelineShaderStageCreateInfo *stage_info,
1108 struct tu_pipeline_layout *layout,
1109 const VkAllocationCallbacks *alloc);
1110
1111 void
1112 tu_shader_destroy(struct tu_device *dev,
1113 struct tu_shader *shader,
1114 const VkAllocationCallbacks *alloc);
1115
1116 void
1117 tu_shader_compile_options_init(
1118 struct tu_shader_compile_options *options,
1119 const VkGraphicsPipelineCreateInfo *pipeline_info);
1120
1121 VkResult
1122 tu_shader_compile(struct tu_device *dev,
1123 struct tu_shader *shader,
1124 const struct tu_shader *next_stage,
1125 const struct tu_shader_compile_options *options,
1126 const VkAllocationCallbacks *alloc);
1127
1128 struct tu_program_descriptor_linkage
1129 {
1130 struct ir3_ubo_analysis_state ubo_state;
1131 struct ir3_const_state const_state;
1132
1133 uint32_t constlen;
1134
1135 struct tu_descriptor_map texture_map;
1136 struct tu_descriptor_map sampler_map;
1137 struct tu_descriptor_map ubo_map;
1138 struct tu_descriptor_map ssbo_map;
1139 struct tu_descriptor_map image_map;
1140 };
1141
1142 struct tu_pipeline
1143 {
1144 struct tu_cs cs;
1145
1146 struct tu_dynamic_state dynamic_state;
1147
1148 struct tu_pipeline_layout *layout;
1149
1150 bool need_indirect_descriptor_sets;
1151 VkShaderStageFlags active_stages;
1152
1153 struct
1154 {
1155 struct tu_bo binary_bo;
1156 struct tu_cs_entry state_ib;
1157 struct tu_cs_entry binning_state_ib;
1158
1159 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1160 } program;
1161
1162 struct
1163 {
1164 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1165 uint16_t strides[MAX_VERTEX_ATTRIBS];
1166 uint16_t offsets[MAX_VERTEX_ATTRIBS];
1167 uint32_t count;
1168
1169 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1170 uint16_t binning_strides[MAX_VERTEX_ATTRIBS];
1171 uint16_t binning_offsets[MAX_VERTEX_ATTRIBS];
1172 uint32_t binning_count;
1173
1174 struct tu_cs_entry state_ib;
1175 struct tu_cs_entry binning_state_ib;
1176 } vi;
1177
1178 struct
1179 {
1180 enum pc_di_primtype primtype;
1181 bool primitive_restart;
1182 } ia;
1183
1184 struct
1185 {
1186 struct tu_cs_entry state_ib;
1187 } vp;
1188
1189 struct
1190 {
1191 uint32_t gras_su_cntl;
1192 struct tu_cs_entry state_ib;
1193 } rast;
1194
1195 struct
1196 {
1197 struct tu_cs_entry state_ib;
1198 } ds;
1199
1200 struct
1201 {
1202 struct tu_cs_entry state_ib;
1203 } blend;
1204
1205 struct
1206 {
1207 uint32_t local_size[3];
1208 } compute;
1209 };
1210
1211 void
1212 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1213
1214 void
1215 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1216
1217 void
1218 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1219 uint32_t gras_su_cntl,
1220 float line_width);
1221
1222 void
1223 tu6_emit_depth_bias(struct tu_cs *cs,
1224 float constant_factor,
1225 float clamp,
1226 float slope_factor);
1227
1228 void
1229 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1230 uint32_t front,
1231 uint32_t back);
1232
1233 void
1234 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1235
1236 void
1237 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1238
1239 void
1240 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1241
1242 struct tu_userdata_info *
1243 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1244 gl_shader_stage stage,
1245 int idx);
1246
1247 struct tu_shader_variant *
1248 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1249
1250 struct tu_graphics_pipeline_create_info
1251 {
1252 bool use_rectlist;
1253 bool db_depth_clear;
1254 bool db_stencil_clear;
1255 bool db_depth_disable_expclear;
1256 bool db_stencil_disable_expclear;
1257 bool db_flush_depth_inplace;
1258 bool db_flush_stencil_inplace;
1259 bool db_resummarize;
1260 uint32_t custom_blend_mode;
1261 };
1262
1263 struct tu_native_format
1264 {
1265 int vtx; /* VFMTn_xxx or -1 */
1266 int tex; /* TFMTn_xxx or -1 */
1267 int rb; /* RBn_xxx or -1 */
1268 int swap; /* enum a3xx_color_swap */
1269 bool present; /* internal only; always true to external users */
1270 };
1271
1272 const struct tu_native_format *
1273 tu6_get_native_format(VkFormat format);
1274
1275 void
1276 tu_pack_clear_value(const VkClearValue *val,
1277 VkFormat format,
1278 uint32_t buf[4]);
1279
1280 void
1281 tu_2d_clear_color(const VkClearColorValue *val, VkFormat format, uint32_t buf[4]);
1282
1283 void
1284 tu_2d_clear_zs(const VkClearDepthStencilValue *val, VkFormat format, uint32_t buf[4]);
1285
1286 enum a6xx_2d_ifmt tu6_fmt_to_ifmt(enum a6xx_format fmt);
1287 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1288
1289 struct tu_image_level
1290 {
1291 VkDeviceSize offset;
1292 VkDeviceSize size;
1293 uint32_t pitch;
1294 };
1295
1296 struct tu_image
1297 {
1298 VkImageType type;
1299 /* The original VkFormat provided by the client. This may not match any
1300 * of the actual surface formats.
1301 */
1302 VkFormat vk_format;
1303 VkImageAspectFlags aspects;
1304 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1305 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1306 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1307 VkExtent3D extent;
1308 uint32_t level_count;
1309 uint32_t layer_count;
1310 VkSampleCountFlagBits samples;
1311
1312
1313 uint32_t alignment;
1314
1315 struct fdl_layout layout;
1316
1317 unsigned queue_family_mask;
1318 bool exclusive;
1319 bool shareable;
1320
1321 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1322 VkDeviceMemory owned_memory;
1323
1324 /* Set when bound */
1325 struct tu_bo *bo;
1326 VkDeviceSize bo_offset;
1327 };
1328
1329 unsigned
1330 tu_image_queue_family_mask(const struct tu_image *image,
1331 uint32_t family,
1332 uint32_t queue_family);
1333
1334 static inline uint32_t
1335 tu_get_layerCount(const struct tu_image *image,
1336 const VkImageSubresourceRange *range)
1337 {
1338 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1339 ? image->layer_count - range->baseArrayLayer
1340 : range->layerCount;
1341 }
1342
1343 static inline uint32_t
1344 tu_get_levelCount(const struct tu_image *image,
1345 const VkImageSubresourceRange *range)
1346 {
1347 return range->levelCount == VK_REMAINING_MIP_LEVELS
1348 ? image->level_count - range->baseMipLevel
1349 : range->levelCount;
1350 }
1351
1352 static inline VkDeviceSize
1353 tu_layer_size(struct tu_image *image, int level)
1354 {
1355 return fdl_layer_stride(&image->layout, level);
1356 }
1357
1358 static inline uint32_t
1359 tu_image_stride(struct tu_image *image, int level)
1360 {
1361 return image->layout.slices[level].pitch * image->layout.cpp;
1362 }
1363
1364 static inline uint64_t
1365 tu_image_base(struct tu_image *image, int level, int layer)
1366 {
1367 return image->bo->iova + image->bo_offset +
1368 fdl_surface_offset(&image->layout, level, layer);
1369 }
1370
1371 #define tu_image_base_ref(image, level, layer) \
1372 .bo = image->bo, \
1373 .bo_offset = (image->bo_offset + fdl_surface_offset(&image->layout, \
1374 level, layer))
1375
1376 #define tu_image_view_base_ref(iview) \
1377 tu_image_base_ref(iview->image, iview->base_mip, iview->base_layer)
1378
1379 static inline VkDeviceSize
1380 tu_image_ubwc_size(struct tu_image *image, int level)
1381 {
1382 return image->layout.ubwc_layer_size;
1383 }
1384
1385 static inline uint32_t
1386 tu_image_ubwc_pitch(struct tu_image *image, int level)
1387 {
1388 return image->layout.ubwc_slices[level].pitch;
1389 }
1390
1391 static inline uint64_t
1392 tu_image_ubwc_surface_offset(struct tu_image *image, int level, int layer)
1393 {
1394 return image->layout.ubwc_slices[level].offset +
1395 layer * tu_image_ubwc_size(image, level);
1396 }
1397
1398 static inline uint64_t
1399 tu_image_ubwc_base(struct tu_image *image, int level, int layer)
1400 {
1401 return image->bo->iova + image->bo_offset +
1402 tu_image_ubwc_surface_offset(image, level, layer);
1403 }
1404
1405 #define tu_image_ubwc_base_ref(image, level, layer) \
1406 .bo = image->bo, \
1407 .bo_offset = (image->bo_offset + tu_image_ubwc_surface_offset(image, \
1408 level, layer))
1409
1410 #define tu_image_view_ubwc_base_ref(iview) \
1411 tu_image_ubwc_base_ref(iview->image, iview->base_mip, iview->base_layer)
1412
1413 enum a6xx_tile_mode
1414 tu6_get_image_tile_mode(struct tu_image *image, int level);
1415 enum a3xx_msaa_samples
1416 tu_msaa_samples(uint32_t samples);
1417
1418 struct tu_image_view
1419 {
1420 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1421
1422 VkImageViewType type;
1423 VkImageAspectFlags aspect_mask;
1424 VkFormat vk_format;
1425 uint32_t base_layer;
1426 uint32_t layer_count;
1427 uint32_t base_mip;
1428 uint32_t level_count;
1429 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1430
1431 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1432
1433 /* Descriptor for use as a storage image as opposed to a sampled image.
1434 * This has a few differences for cube maps (e.g. type).
1435 */
1436 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1437 };
1438
1439 struct tu_sampler
1440 {
1441 uint32_t state[A6XX_TEX_SAMP_DWORDS];
1442
1443 bool needs_border;
1444 VkBorderColor border;
1445 };
1446
1447 VkResult
1448 tu_image_create(VkDevice _device,
1449 const VkImageCreateInfo *pCreateInfo,
1450 const VkAllocationCallbacks *alloc,
1451 VkImage *pImage,
1452 uint64_t modifier);
1453
1454 VkResult
1455 tu_image_from_gralloc(VkDevice device_h,
1456 const VkImageCreateInfo *base_info,
1457 const VkNativeBufferANDROID *gralloc_info,
1458 const VkAllocationCallbacks *alloc,
1459 VkImage *out_image_h);
1460
1461 void
1462 tu_image_view_init(struct tu_image_view *view,
1463 struct tu_device *device,
1464 const VkImageViewCreateInfo *pCreateInfo);
1465
1466 struct tu_buffer_view
1467 {
1468 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1469
1470 struct tu_buffer *buffer;
1471 };
1472 void
1473 tu_buffer_view_init(struct tu_buffer_view *view,
1474 struct tu_device *device,
1475 const VkBufferViewCreateInfo *pCreateInfo);
1476
1477 static inline struct VkExtent3D
1478 tu_sanitize_image_extent(const VkImageType imageType,
1479 const struct VkExtent3D imageExtent)
1480 {
1481 switch (imageType) {
1482 case VK_IMAGE_TYPE_1D:
1483 return (VkExtent3D) { imageExtent.width, 1, 1 };
1484 case VK_IMAGE_TYPE_2D:
1485 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1486 case VK_IMAGE_TYPE_3D:
1487 return imageExtent;
1488 default:
1489 unreachable("invalid image type");
1490 }
1491 }
1492
1493 static inline struct VkOffset3D
1494 tu_sanitize_image_offset(const VkImageType imageType,
1495 const struct VkOffset3D imageOffset)
1496 {
1497 switch (imageType) {
1498 case VK_IMAGE_TYPE_1D:
1499 return (VkOffset3D) { imageOffset.x, 0, 0 };
1500 case VK_IMAGE_TYPE_2D:
1501 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1502 case VK_IMAGE_TYPE_3D:
1503 return imageOffset;
1504 default:
1505 unreachable("invalid image type");
1506 }
1507 }
1508
1509 struct tu_attachment_info
1510 {
1511 struct tu_image_view *attachment;
1512 };
1513
1514 struct tu_framebuffer
1515 {
1516 uint32_t width;
1517 uint32_t height;
1518 uint32_t layers;
1519
1520 uint32_t attachment_count;
1521 struct tu_attachment_info attachments[0];
1522 };
1523
1524 struct tu_subpass_attachment
1525 {
1526 uint32_t attachment;
1527 };
1528
1529 struct tu_subpass
1530 {
1531 uint32_t input_count;
1532 uint32_t color_count;
1533 struct tu_subpass_attachment *input_attachments;
1534 struct tu_subpass_attachment *color_attachments;
1535 struct tu_subpass_attachment *resolve_attachments;
1536 struct tu_subpass_attachment depth_stencil_attachment;
1537
1538 VkSampleCountFlagBits samples;
1539 };
1540
1541 struct tu_render_pass_attachment
1542 {
1543 VkFormat format;
1544 uint32_t cpp;
1545 VkAttachmentLoadOp load_op;
1546 VkAttachmentLoadOp stencil_load_op;
1547 VkAttachmentStoreOp store_op;
1548 VkAttachmentStoreOp stencil_store_op;
1549 int32_t gmem_offset;
1550 };
1551
1552 struct tu_render_pass
1553 {
1554 uint32_t attachment_count;
1555 uint32_t subpass_count;
1556 uint32_t gmem_pixels;
1557 struct tu_subpass_attachment *subpass_attachments;
1558 struct tu_render_pass_attachment *attachments;
1559 struct tu_subpass subpasses[0];
1560 };
1561
1562 VkResult
1563 tu_device_init_meta(struct tu_device *device);
1564 void
1565 tu_device_finish_meta(struct tu_device *device);
1566
1567 struct tu_query_pool
1568 {
1569 VkQueryType type;
1570 uint32_t stride;
1571 uint64_t size;
1572 uint32_t pipeline_statistics;
1573 struct tu_bo bo;
1574 };
1575
1576 struct tu_semaphore
1577 {
1578 uint32_t syncobj;
1579 uint32_t temp_syncobj;
1580 };
1581
1582 void
1583 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1584 VkPipelineBindPoint bind_point,
1585 struct tu_descriptor_set *set,
1586 unsigned idx);
1587
1588 void
1589 tu_update_descriptor_sets(struct tu_device *device,
1590 struct tu_cmd_buffer *cmd_buffer,
1591 VkDescriptorSet overrideSet,
1592 uint32_t descriptorWriteCount,
1593 const VkWriteDescriptorSet *pDescriptorWrites,
1594 uint32_t descriptorCopyCount,
1595 const VkCopyDescriptorSet *pDescriptorCopies);
1596
1597 void
1598 tu_update_descriptor_set_with_template(
1599 struct tu_device *device,
1600 struct tu_cmd_buffer *cmd_buffer,
1601 struct tu_descriptor_set *set,
1602 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1603 const void *pData);
1604
1605 void
1606 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1607 VkPipelineBindPoint pipelineBindPoint,
1608 VkPipelineLayout _layout,
1609 uint32_t set,
1610 uint32_t descriptorWriteCount,
1611 const VkWriteDescriptorSet *pDescriptorWrites);
1612
1613 int
1614 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1615
1616 int
1617 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1618
1619 int
1620 tu_drm_submitqueue_new(const struct tu_device *dev,
1621 int priority,
1622 uint32_t *queue_id);
1623
1624 void
1625 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1626
1627 uint32_t
1628 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1629 uint32_t
1630 tu_gem_import_dmabuf(const struct tu_device *dev,
1631 int prime_fd,
1632 uint64_t size);
1633 int
1634 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1635 void
1636 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1637 uint64_t
1638 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1639 uint64_t
1640 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1641
1642
1643 void
1644 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1645 struct tu_cs *cs,
1646 uint32_t attachment,
1647 const VkClearValue *value,
1648 const VkClearRect *rect);
1649
1650 void
1651 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1652 struct tu_cs *cs,
1653 uint32_t attachment,
1654 uint8_t component_mask,
1655 const VkClearValue *value);
1656
1657 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1658 \
1659 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1660 { \
1661 return (struct __tu_type *) _handle; \
1662 } \
1663 \
1664 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1665 { \
1666 return (__VkType) _obj; \
1667 }
1668
1669 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1670 \
1671 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1672 { \
1673 return (struct __tu_type *) (uintptr_t) _handle; \
1674 } \
1675 \
1676 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1677 { \
1678 return (__VkType)(uintptr_t) _obj; \
1679 }
1680
1681 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1682 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1683
1684 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1685 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1686 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1687 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1688 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1689
1690 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1691 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1692 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1693 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1694 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1695 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1696 VkDescriptorSetLayout)
1697 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1698 VkDescriptorUpdateTemplate)
1699 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1700 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1701 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1702 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1703 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1704 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1705 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1706 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1707 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1708 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1709 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1710 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1711 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1712 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1713
1714 #endif /* TU_PRIVATE_H */