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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 * DEALINGS IN THE SOFTWARE.
24 #include "tu_private.h"
26 #include "spirv/nir_spirv.h"
27 #include "util/mesa-sha1.h"
29 #include "ir3/ir3_nir.h"
32 tu_spirv_to_nir(struct ir3_compiler
*compiler
,
33 const uint32_t *words
,
35 gl_shader_stage stage
,
36 const char *entry_point_name
,
37 const VkSpecializationInfo
*spec_info
)
39 /* TODO these are made-up */
40 const struct spirv_to_nir_options spirv_options
= {
41 .lower_ubo_ssbo_access_to_offsets
= true,
44 const nir_shader_compiler_options
*nir_options
=
45 ir3_get_compiler_options(compiler
);
47 /* convert VkSpecializationInfo */
48 struct nir_spirv_specialization
*spec
= NULL
;
49 uint32_t num_spec
= 0;
50 if (spec_info
&& spec_info
->mapEntryCount
) {
51 spec
= malloc(sizeof(*spec
) * spec_info
->mapEntryCount
);
55 for (uint32_t i
= 0; i
< spec_info
->mapEntryCount
; i
++) {
56 const VkSpecializationMapEntry
*entry
= &spec_info
->pMapEntries
[i
];
57 const void *data
= spec_info
->pData
+ entry
->offset
;
58 assert(data
+ entry
->size
<= spec_info
->pData
+ spec_info
->dataSize
);
59 spec
[i
].id
= entry
->constantID
;
61 spec
[i
].data64
= *(const uint64_t *) data
;
63 spec
[i
].data32
= *(const uint32_t *) data
;
64 spec
[i
].defined_on_module
= false;
67 num_spec
= spec_info
->mapEntryCount
;
71 spirv_to_nir(words
, word_count
, spec
, num_spec
, stage
, entry_point_name
,
72 &spirv_options
, nir_options
);
76 assert(nir
->info
.stage
== stage
);
77 nir_validate_shader(nir
, "after spirv_to_nir");
83 tu_sort_variables_by_location(struct exec_list
*variables
)
85 struct exec_list sorted
;
86 exec_list_make_empty(&sorted
);
88 nir_foreach_variable_safe(var
, variables
)
90 exec_node_remove(&var
->node
);
92 /* insert the variable into the sorted list */
93 nir_variable
*next
= NULL
;
94 nir_foreach_variable(tmp
, &sorted
)
96 if (var
->data
.location
< tmp
->data
.location
) {
102 exec_node_insert_node_before(&next
->node
, &var
->node
);
104 exec_list_push_tail(&sorted
, &var
->node
);
107 exec_list_move_nodes_to(&sorted
, variables
);
111 map_add(struct tu_descriptor_map
*map
, int set
, int binding
)
114 for (index
= 0; index
< map
->num
; index
++) {
115 if (set
== map
->set
[index
] && binding
== map
->binding
[index
])
119 assert(index
< ARRAY_SIZE(map
->set
));
121 map
->set
[index
] = set
;
122 map
->binding
[index
] = binding
;
123 map
->num
= MAX2(map
->num
, index
+ 1);
128 lower_tex_src_to_offset(nir_tex_instr
*instr
, unsigned src_idx
,
129 struct tu_shader
*shader
, bool is_sampler
)
131 nir_deref_instr
*deref
=
132 nir_instr_as_deref(instr
->src
[src_idx
].src
.ssa
->parent_instr
);
134 if (deref
->deref_type
!= nir_deref_type_var
) {
135 tu_finishme("sampler array");
140 instr
->sampler_index
= map_add(&shader
->sampler_map
,
141 deref
->var
->data
.descriptor_set
,
142 deref
->var
->data
.binding
);
144 instr
->texture_index
= map_add(&shader
->texture_map
,
145 deref
->var
->data
.descriptor_set
,
146 deref
->var
->data
.binding
);
147 instr
->texture_array_size
= 1;
150 nir_tex_instr_remove_src(instr
, src_idx
);
154 lower_sampler(nir_tex_instr
*instr
, struct tu_shader
*shader
)
157 nir_tex_instr_src_index(instr
, nir_tex_src_texture_deref
);
159 if (texture_idx
>= 0)
160 lower_tex_src_to_offset(instr
, texture_idx
, shader
, false);
163 nir_tex_instr_src_index(instr
, nir_tex_src_sampler_deref
);
165 if (sampler_idx
>= 0)
166 lower_tex_src_to_offset(instr
, sampler_idx
, shader
, true);
168 if (texture_idx
< 0 && sampler_idx
< 0)
175 lower_intrinsic(nir_builder
*b
, nir_intrinsic_instr
*instr
,
176 struct tu_shader
*shader
)
178 if (instr
->intrinsic
!= nir_intrinsic_vulkan_resource_index
)
181 nir_const_value
*const_val
= nir_src_as_const_value(instr
->src
[0]);
182 if (!const_val
|| const_val
->u32
!= 0) {
183 tu_finishme("non-zero vulkan_resource_index array index");
187 if (nir_intrinsic_desc_type(instr
) != VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
188 tu_finishme("non-ubo vulkan_resource_index");
192 unsigned index
= map_add(&shader
->ubo_map
,
193 nir_intrinsic_desc_set(instr
),
194 nir_intrinsic_binding(instr
));
196 b
->cursor
= nir_before_instr(&instr
->instr
);
197 /* skip index 0 because ir3 treats it differently */
198 nir_ssa_def_rewrite_uses(&instr
->dest
.ssa
,
199 nir_src_for_ssa(nir_imm_int(b
, index
+ 1)));
200 nir_instr_remove(&instr
->instr
);
206 lower_impl(nir_function_impl
*impl
, struct tu_shader
*shader
)
209 nir_builder_init(&b
, impl
);
210 bool progress
= false;
212 nir_foreach_block(block
, impl
) {
213 nir_foreach_instr_safe(instr
, block
) {
214 switch (instr
->type
) {
215 case nir_instr_type_tex
:
216 progress
|= lower_sampler(nir_instr_as_tex(instr
), shader
);
218 case nir_instr_type_intrinsic
:
219 progress
|= lower_intrinsic(&b
, nir_instr_as_intrinsic(instr
), shader
);
231 tu_lower_io(nir_shader
*shader
, struct tu_shader
*tu_shader
)
233 bool progress
= false;
235 nir_foreach_function(function
, shader
) {
237 progress
|= lower_impl(function
->impl
, tu_shader
);
244 tu_shader_create(struct tu_device
*dev
,
245 gl_shader_stage stage
,
246 const VkPipelineShaderStageCreateInfo
*stage_info
,
247 const VkAllocationCallbacks
*alloc
)
249 const struct tu_shader_module
*module
=
250 tu_shader_module_from_handle(stage_info
->module
);
251 struct tu_shader
*shader
;
253 const uint32_t max_variant_count
= (stage
== MESA_SHADER_VERTEX
) ? 2 : 1;
256 sizeof(*shader
) + sizeof(struct ir3_shader_variant
) * max_variant_count
,
257 8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND
);
261 /* translate SPIR-V to NIR */
262 assert(module
->code_size
% 4 == 0);
263 nir_shader
*nir
= tu_spirv_to_nir(
264 dev
->compiler
, (const uint32_t *) module
->code
, module
->code_size
/ 4,
265 stage
, stage_info
->pName
, stage_info
->pSpecializationInfo
);
267 vk_free2(&dev
->alloc
, alloc
, shader
);
271 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_NIR
)) {
272 fprintf(stderr
, "translated nir:\n");
273 nir_print_shader(nir
, stderr
);
276 /* TODO what needs to happen? */
279 case MESA_SHADER_VERTEX
:
280 tu_sort_variables_by_location(&nir
->outputs
);
282 case MESA_SHADER_TESS_CTRL
:
283 case MESA_SHADER_TESS_EVAL
:
284 case MESA_SHADER_GEOMETRY
:
285 tu_sort_variables_by_location(&nir
->inputs
);
286 tu_sort_variables_by_location(&nir
->outputs
);
288 case MESA_SHADER_FRAGMENT
:
289 tu_sort_variables_by_location(&nir
->inputs
);
291 case MESA_SHADER_COMPUTE
:
294 unreachable("invalid gl_shader_stage");
298 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
,
300 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
,
302 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
305 NIR_PASS_V(nir
, nir_opt_copy_prop_vars
);
307 NIR_PASS_V(nir
, nir_lower_system_values
);
308 NIR_PASS_V(nir
, nir_lower_frexp
);
310 NIR_PASS_V(nir
, tu_lower_io
, shader
);
312 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, ir3_glsl_type_size
, 0);
314 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
316 shader
->ir3_shader
.compiler
= dev
->compiler
;
317 shader
->ir3_shader
.type
= stage
;
318 shader
->ir3_shader
.nir
= nir
;
324 tu_shader_destroy(struct tu_device
*dev
,
325 struct tu_shader
*shader
,
326 const VkAllocationCallbacks
*alloc
)
328 if (shader
->ir3_shader
.nir
)
329 ralloc_free(shader
->ir3_shader
.nir
);
331 for (uint32_t i
= 0; i
< 1 + shader
->has_binning_pass
; i
++) {
332 if (shader
->variants
[i
].ir
)
333 ir3_destroy(shader
->variants
[i
].ir
);
336 if (shader
->ir3_shader
.const_state
.immediates
)
337 free(shader
->ir3_shader
.const_state
.immediates
);
339 free(shader
->binary
);
340 if (shader
->binning_binary
)
341 free(shader
->binning_binary
);
343 vk_free2(&dev
->alloc
, alloc
, shader
);
347 tu_shader_compile_options_init(
348 struct tu_shader_compile_options
*options
,
349 const VkGraphicsPipelineCreateInfo
*pipeline_info
)
351 *options
= (struct tu_shader_compile_options
) {
354 .optimize
= !(pipeline_info
->flags
&
355 VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
),
356 .include_binning_pass
= true,
361 tu_compile_shader_variant(struct ir3_shader
*shader
,
362 const struct ir3_shader_key
*key
,
363 struct ir3_shader_variant
*nonbinning
,
364 struct ir3_shader_variant
*variant
)
366 variant
->shader
= shader
;
367 variant
->type
= shader
->type
;
369 variant
->binning_pass
= !!nonbinning
;
370 variant
->nonbinning
= nonbinning
;
372 int ret
= ir3_compile_shader_nir(shader
->compiler
, variant
);
376 /* when assemble fails, we rely on tu_shader_destroy to clean up the
379 return ir3_shader_assemble(variant
, shader
->compiler
->gpu_id
);
383 tu_shader_compile(struct tu_device
*dev
,
384 struct tu_shader
*shader
,
385 const struct tu_shader
*next_stage
,
386 const struct tu_shader_compile_options
*options
,
387 const VkAllocationCallbacks
*alloc
)
389 if (options
->optimize
) {
390 /* ignore the key for the first pass of optimization */
391 ir3_optimize_nir(&shader
->ir3_shader
, shader
->ir3_shader
.nir
, NULL
);
393 if (unlikely(dev
->physical_device
->instance
->debug_flags
&
395 fprintf(stderr
, "optimized nir:\n");
396 nir_print_shader(shader
->ir3_shader
.nir
, stderr
);
400 shader
->binary
= tu_compile_shader_variant(
401 &shader
->ir3_shader
, &options
->key
, NULL
, &shader
->variants
[0]);
403 return VK_ERROR_OUT_OF_HOST_MEMORY
;
405 /* compile another variant for the binning pass */
406 if (options
->include_binning_pass
&&
407 shader
->ir3_shader
.type
== MESA_SHADER_VERTEX
) {
408 shader
->binning_binary
= tu_compile_shader_variant(
409 &shader
->ir3_shader
, &options
->key
, &shader
->variants
[0],
410 &shader
->variants
[1]);
411 if (!shader
->binning_binary
)
412 return VK_ERROR_OUT_OF_HOST_MEMORY
;
414 shader
->has_binning_pass
= true;
417 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_IR3
)) {
418 fprintf(stderr
, "disassembled ir3:\n");
419 fprintf(stderr
, "shader: %s\n",
420 gl_shader_stage_name(shader
->ir3_shader
.type
));
421 ir3_shader_disasm(&shader
->variants
[0], shader
->binary
, stderr
);
423 if (shader
->has_binning_pass
) {
424 fprintf(stderr
, "disassembled ir3:\n");
425 fprintf(stderr
, "shader: %s (binning)\n",
426 gl_shader_stage_name(shader
->ir3_shader
.type
));
427 ir3_shader_disasm(&shader
->variants
[1], shader
->binning_binary
,
436 tu_CreateShaderModule(VkDevice _device
,
437 const VkShaderModuleCreateInfo
*pCreateInfo
,
438 const VkAllocationCallbacks
*pAllocator
,
439 VkShaderModule
*pShaderModule
)
441 TU_FROM_HANDLE(tu_device
, device
, _device
);
442 struct tu_shader_module
*module
;
444 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
445 assert(pCreateInfo
->flags
== 0);
446 assert(pCreateInfo
->codeSize
% 4 == 0);
448 module
= vk_alloc2(&device
->alloc
, pAllocator
,
449 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
450 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
452 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
454 module
->code_size
= pCreateInfo
->codeSize
;
455 memcpy(module
->code
, pCreateInfo
->pCode
, pCreateInfo
->codeSize
);
457 _mesa_sha1_compute(module
->code
, module
->code_size
, module
->sha1
);
459 *pShaderModule
= tu_shader_module_to_handle(module
);
465 tu_DestroyShaderModule(VkDevice _device
,
466 VkShaderModule _module
,
467 const VkAllocationCallbacks
*pAllocator
)
469 TU_FROM_HANDLE(tu_device
, device
, _device
);
470 TU_FROM_HANDLE(tu_shader_module
, module
, _module
);
475 vk_free2(&device
->alloc
, pAllocator
, module
);