src/freedreno/vulkan/tu_shader.c

   1 /*
   2  * Copyright © 2019 Google LLC
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "tu_private.h"
  25
  26 #include "spirv/nir_spirv.h"
  27 #include "util/mesa-sha1.h"
  28 #include "nir/nir_xfb_info.h"
  29 #include "nir/nir_vulkan.h"
  30 #include "vk_util.h"
  31
  32 #include "ir3/ir3_nir.h"
  33
  34 static nir_shader *
  35 tu_spirv_to_nir(struct ir3_compiler *compiler,
  36                 const uint32_t *words,
  37                 size_t word_count,
  38                 gl_shader_stage stage,
  39                 const char *entry_point_name,
  40                 const VkSpecializationInfo *spec_info)
  41 {
  42    /* TODO these are made-up */
  43    const struct spirv_to_nir_options spirv_options = {
  44       .frag_coord_is_sysval = true,
  45       .lower_ubo_ssbo_access_to_offsets = false,
  46
  47       .ubo_addr_format = nir_address_format_vec2_index_32bit_offset,
  48       .ssbo_addr_format = nir_address_format_vec2_index_32bit_offset,
  49
  50       /* Accessed via stg/ldg */
  51       .phys_ssbo_addr_format = nir_address_format_64bit_global,
  52
  53       /* Accessed via the const register file */
  54       .push_const_addr_format = nir_address_format_logical,
  55
  56       /* Accessed via ldl/stl */
  57       .shared_addr_format = nir_address_format_32bit_offset,
  58
  59       /* Accessed via stg/ldg (not used with Vulkan?) */
  60       .global_addr_format = nir_address_format_64bit_global,
  61
  62       .caps = {
  63          .transform_feedback = true,
  64          .tessellation = true,
  65          .draw_parameters = true,
  66          .variable_pointers = true,
  67          .stencil_export = true,
  68       },
  69    };
  70    const nir_shader_compiler_options *nir_options =
  71       ir3_get_compiler_options(compiler);
  72
  73    /* convert VkSpecializationInfo */
  74    struct nir_spirv_specialization *spec = NULL;
  75    uint32_t num_spec = 0;
  76    if (spec_info && spec_info->mapEntryCount) {
  77       spec = calloc(spec_info->mapEntryCount, sizeof(*spec));
  78       if (!spec)
  79          return NULL;
  80
  81       for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
  82          const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
  83          const void *data = spec_info->pData + entry->offset;
  84          assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
  85          spec[i].id = entry->constantID;
  86          switch (entry->size) {
  87          case 8:
  88             spec[i].value.u64 = *(const uint64_t *)data;
  89             break;
  90          case 4:
  91             spec[i].value.u32 = *(const uint32_t *)data;
  92             break;
  93          case 2:
  94             spec[i].value.u16 = *(const uint16_t *)data;
  95             break;
  96          case 1:
  97             spec[i].value.u8 = *(const uint8_t *)data;
  98             break;
  99          default:
 100             assert(!"Invalid spec constant size");
 101             break;
 102          }
 103          spec[i].defined_on_module = false;
 104       }
 105
 106       num_spec = spec_info->mapEntryCount;
 107    }
 108
 109    nir_shader *nir =
 110       spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
 111                    &spirv_options, nir_options);
 112
 113    free(spec);
 114
 115    assert(nir->info.stage == stage);
 116    nir_validate_shader(nir, "after spirv_to_nir");
 117
 118    return nir;
 119 }
 120
 121 static void
 122 lower_load_push_constant(nir_builder *b, nir_intrinsic_instr *instr,
 123                          struct tu_shader *shader)
 124 {
 125    nir_intrinsic_instr *load =
 126       nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
 127    load->num_components = instr->num_components;
 128    uint32_t base = nir_intrinsic_base(instr);
 129    assert(base % 4 == 0);
 130    assert(base >= shader->push_consts.lo * 16);
 131    base -= shader->push_consts.lo * 16;
 132    nir_intrinsic_set_base(load, base / 4);
 133    load->src[0] =
 134       nir_src_for_ssa(nir_ushr(b, instr->src[0].ssa, nir_imm_int(b, 2)));
 135    nir_ssa_dest_init(&load->instr, &load->dest,
 136                      load->num_components, instr->dest.ssa.bit_size,
 137                      instr->dest.ssa.name);
 138    nir_builder_instr_insert(b, &load->instr);
 139    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(&load->dest.ssa));
 140
 141    nir_instr_remove(&instr->instr);
 142 }
 143
 144 static void
 145 lower_vulkan_resource_index(nir_builder *b, nir_intrinsic_instr *instr,
 146                             struct tu_shader *shader,
 147                             const struct tu_pipeline_layout *layout)
 148 {
 149    nir_ssa_def *vulkan_idx = instr->src[0].ssa;
 150
 151    unsigned set = nir_intrinsic_desc_set(instr);
 152    unsigned binding = nir_intrinsic_binding(instr);
 153    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 154    struct tu_descriptor_set_binding_layout *binding_layout =
 155       &set_layout->binding[binding];
 156    uint32_t base;
 157
 158    shader->active_desc_sets |= 1u << set;
 159
 160    switch (binding_layout->type) {
 161    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 162    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 163       base = layout->set[set].dynamic_offset_start +
 164          binding_layout->dynamic_offset_offset;
 165       set = MAX_SETS;
 166       break;
 167    default:
 168       base = binding_layout->offset / (4 * A6XX_TEX_CONST_DWORDS);
 169       break;
 170    }
 171
 172    nir_ssa_def *def = nir_vec3(b, nir_imm_int(b, set),
 173                                nir_iadd(b, nir_imm_int(b, base), vulkan_idx),
 174                                nir_imm_int(b, 0));
 175
 176    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(def));
 177    nir_instr_remove(&instr->instr);
 178 }
 179
 180 static void
 181 lower_load_vulkan_descriptor(nir_intrinsic_instr *intrin)
 182 {
 183    /* Loading the descriptor happens as part of the load/store instruction so
 184     * this is a no-op.
 185     */
 186    nir_ssa_def_rewrite_uses(&intrin->dest.ssa, intrin->src[0]);
 187    nir_instr_remove(&intrin->instr);
 188 }
 189
 190 static void
 191 lower_ssbo_ubo_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin)
 192 {
 193    const nir_intrinsic_info *info = &nir_intrinsic_infos[intrin->intrinsic];
 194
 195    /* The bindless base is part of the instruction, which means that part of
 196     * the "pointer" has to be constant. We solve this in the same way the blob
 197     * does, by generating a bunch of if-statements. In the usual case where
 198     * the descriptor set is constant this will get optimized out.
 199     */
 200
 201    unsigned buffer_src;
 202    if (intrin->intrinsic == nir_intrinsic_store_ssbo) {
 203       /* This has the value first */
 204       buffer_src = 1;
 205    } else {
 206       buffer_src = 0;
 207    }
 208
 209    nir_ssa_def *base_idx = nir_channel(b, intrin->src[buffer_src].ssa, 0);
 210    nir_ssa_def *descriptor_idx = nir_channel(b, intrin->src[buffer_src].ssa, 1);
 211
 212    nir_ssa_def *results[MAX_SETS + 1] = { NULL };
 213
 214    for (unsigned i = 0; i < MAX_SETS + 1; i++) {
 215       /* if (base_idx == i) { ... */
 216       nir_if *nif = nir_push_if(b, nir_ieq(b, base_idx, nir_imm_int(b, i)));
 217
 218       nir_intrinsic_instr *bindless =
 219          nir_intrinsic_instr_create(b->shader,
 220                                     nir_intrinsic_bindless_resource_ir3);
 221       bindless->num_components = 0;
 222       nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 223                         1, 32, NULL);
 224       nir_intrinsic_set_desc_set(bindless, i);
 225       bindless->src[0] = nir_src_for_ssa(descriptor_idx);
 226       nir_builder_instr_insert(b, &bindless->instr);
 227
 228       nir_intrinsic_instr *copy =
 229          nir_intrinsic_instr_create(b->shader, intrin->intrinsic);
 230
 231       copy->num_components = intrin->num_components;
 232
 233       for (unsigned src = 0; src < info->num_srcs; src++) {
 234          if (src == buffer_src)
 235             copy->src[src] = nir_src_for_ssa(&bindless->dest.ssa);
 236          else
 237             copy->src[src] = nir_src_for_ssa(intrin->src[src].ssa);
 238       }
 239
 240       for (unsigned idx = 0; idx < info->num_indices; idx++) {
 241          copy->const_index[idx] = intrin->const_index[idx];
 242       }
 243
 244       if (info->has_dest) {
 245          nir_ssa_dest_init(&copy->instr, &copy->dest,
 246                            intrin->dest.ssa.num_components,
 247                            intrin->dest.ssa.bit_size,
 248                            intrin->dest.ssa.name);
 249          results[i] = &copy->dest.ssa;
 250       }
 251
 252       nir_builder_instr_insert(b, &copy->instr);
 253
 254       /* } else { ... */
 255       nir_push_else(b, nif);
 256    }
 257
 258    nir_ssa_def *result =
 259       nir_ssa_undef(b, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size);
 260    for (int i = MAX_SETS; i >= 0; i--) {
 261       nir_pop_if(b, NULL);
 262       if (info->has_dest)
 263          result = nir_if_phi(b, results[i], result);
 264    }
 265
 266    if (info->has_dest)
 267       nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(result));
 268    nir_instr_remove(&intrin->instr);
 269 }
 270
 271 static nir_ssa_def *
 272 build_bindless(nir_builder *b, nir_deref_instr *deref, bool is_sampler,
 273                struct tu_shader *shader,
 274                const struct tu_pipeline_layout *layout)
 275 {
 276    nir_variable *var = nir_deref_instr_get_variable(deref);
 277
 278    unsigned set = var->data.descriptor_set;
 279    unsigned binding = var->data.binding;
 280    const struct tu_descriptor_set_binding_layout *bind_layout =
 281       &layout->set[set].layout->binding[binding];
 282
 283    /* input attachments use non bindless workaround */
 284    if (bind_layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
 285       const struct glsl_type *glsl_type = glsl_without_array(var->type);
 286       uint32_t idx = var->data.index * 2;
 287
 288       b->shader->info.textures_used |=
 289          ((1ull << (bind_layout->array_size * 2)) - 1) << (idx * 2);
 290
 291       /* D24S8 workaround: stencil of D24S8 will be sampled as uint */
 292       if (glsl_get_sampler_result_type(glsl_type) == GLSL_TYPE_UINT)
 293          idx += 1;
 294
 295       if (deref->deref_type == nir_deref_type_var)
 296          return nir_imm_int(b, idx);
 297
 298       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 299       return nir_iadd(b, nir_imm_int(b, idx),
 300                       nir_imul_imm(b, arr_index, 2));
 301    }
 302
 303    shader->active_desc_sets |= 1u << set;
 304
 305    nir_ssa_def *desc_offset;
 306    unsigned descriptor_stride;
 307    unsigned offset = 0;
 308    /* Samplers come second in combined image/sampler descriptors, see
 309       * write_combined_image_sampler_descriptor().
 310       */
 311    if (is_sampler && bind_layout->type ==
 312          VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
 313       offset = 1;
 314    }
 315    desc_offset =
 316       nir_imm_int(b, (bind_layout->offset / (4 * A6XX_TEX_CONST_DWORDS)) +
 317                   offset);
 318    descriptor_stride = bind_layout->size / (4 * A6XX_TEX_CONST_DWORDS);
 319
 320    if (deref->deref_type != nir_deref_type_var) {
 321       assert(deref->deref_type == nir_deref_type_array);
 322
 323       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 324       desc_offset = nir_iadd(b, desc_offset,
 325                              nir_imul_imm(b, arr_index, descriptor_stride));
 326    }
 327
 328    nir_intrinsic_instr *bindless =
 329       nir_intrinsic_instr_create(b->shader,
 330                                  nir_intrinsic_bindless_resource_ir3);
 331    bindless->num_components = 0;
 332    nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 333                      1, 32, NULL);
 334    nir_intrinsic_set_desc_set(bindless, set);
 335    bindless->src[0] = nir_src_for_ssa(desc_offset);
 336    nir_builder_instr_insert(b, &bindless->instr);
 337
 338    return &bindless->dest.ssa;
 339 }
 340
 341 static void
 342 lower_image_deref(nir_builder *b,
 343                   nir_intrinsic_instr *instr, struct tu_shader *shader,
 344                   const struct tu_pipeline_layout *layout)
 345 {
 346    nir_deref_instr *deref = nir_src_as_deref(instr->src[0]);
 347    nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 348    nir_rewrite_image_intrinsic(instr, bindless, true);
 349 }
 350
 351 static bool
 352 lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
 353                 struct tu_shader *shader,
 354                 const struct tu_pipeline_layout *layout)
 355 {
 356    switch (instr->intrinsic) {
 357    case nir_intrinsic_load_push_constant:
 358       lower_load_push_constant(b, instr, shader);
 359       return true;
 360
 361    case nir_intrinsic_load_vulkan_descriptor:
 362       lower_load_vulkan_descriptor(instr);
 363       return true;
 364
 365    case nir_intrinsic_vulkan_resource_index:
 366       lower_vulkan_resource_index(b, instr, shader, layout);
 367       return true;
 368
 369    case nir_intrinsic_load_ubo:
 370    case nir_intrinsic_load_ssbo:
 371    case nir_intrinsic_store_ssbo:
 372    case nir_intrinsic_ssbo_atomic_add:
 373    case nir_intrinsic_ssbo_atomic_imin:
 374    case nir_intrinsic_ssbo_atomic_umin:
 375    case nir_intrinsic_ssbo_atomic_imax:
 376    case nir_intrinsic_ssbo_atomic_umax:
 377    case nir_intrinsic_ssbo_atomic_and:
 378    case nir_intrinsic_ssbo_atomic_or:
 379    case nir_intrinsic_ssbo_atomic_xor:
 380    case nir_intrinsic_ssbo_atomic_exchange:
 381    case nir_intrinsic_ssbo_atomic_comp_swap:
 382    case nir_intrinsic_ssbo_atomic_fadd:
 383    case nir_intrinsic_ssbo_atomic_fmin:
 384    case nir_intrinsic_ssbo_atomic_fmax:
 385    case nir_intrinsic_ssbo_atomic_fcomp_swap:
 386    case nir_intrinsic_get_buffer_size:
 387       lower_ssbo_ubo_intrinsic(b, instr);
 388       return true;
 389
 390    case nir_intrinsic_image_deref_load:
 391    case nir_intrinsic_image_deref_store:
 392    case nir_intrinsic_image_deref_atomic_add:
 393    case nir_intrinsic_image_deref_atomic_imin:
 394    case nir_intrinsic_image_deref_atomic_umin:
 395    case nir_intrinsic_image_deref_atomic_imax:
 396    case nir_intrinsic_image_deref_atomic_umax:
 397    case nir_intrinsic_image_deref_atomic_and:
 398    case nir_intrinsic_image_deref_atomic_or:
 399    case nir_intrinsic_image_deref_atomic_xor:
 400    case nir_intrinsic_image_deref_atomic_exchange:
 401    case nir_intrinsic_image_deref_atomic_comp_swap:
 402    case nir_intrinsic_image_deref_size:
 403    case nir_intrinsic_image_deref_samples:
 404       lower_image_deref(b, instr, shader, layout);
 405       return true;
 406
 407    default:
 408       return false;
 409    }
 410 }
 411
 412 static void
 413 lower_tex_ycbcr(const struct tu_pipeline_layout *layout,
 414                 nir_builder *builder,
 415                 nir_tex_instr *tex)
 416 {
 417    int deref_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 418    assert(deref_src_idx >= 0);
 419    nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src);
 420
 421    nir_variable *var = nir_deref_instr_get_variable(deref);
 422    const struct tu_descriptor_set_layout *set_layout =
 423       layout->set[var->data.descriptor_set].layout;
 424    const struct tu_descriptor_set_binding_layout *binding =
 425       &set_layout->binding[var->data.binding];
 426    const struct tu_sampler_ycbcr_conversion *ycbcr_samplers =
 427       tu_immutable_ycbcr_samplers(set_layout, binding);
 428
 429    if (!ycbcr_samplers)
 430       return;
 431
 432    /* For the following instructions, we don't apply any change */
 433    if (tex->op == nir_texop_txs ||
 434        tex->op == nir_texop_query_levels ||
 435        tex->op == nir_texop_lod)
 436       return;
 437
 438    assert(tex->texture_index == 0);
 439    unsigned array_index = 0;
 440    if (deref->deref_type != nir_deref_type_var) {
 441       assert(deref->deref_type == nir_deref_type_array);
 442       if (!nir_src_is_const(deref->arr.index))
 443          return;
 444       array_index = nir_src_as_uint(deref->arr.index);
 445       array_index = MIN2(array_index, binding->array_size - 1);
 446    }
 447    const struct tu_sampler_ycbcr_conversion *ycbcr_sampler = ycbcr_samplers + array_index;
 448
 449    if (ycbcr_sampler->ycbcr_model == VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY)
 450       return;
 451
 452    builder->cursor = nir_after_instr(&tex->instr);
 453
 454    uint8_t bits = vk_format_get_component_bits(ycbcr_sampler->format,
 455                                                UTIL_FORMAT_COLORSPACE_RGB,
 456                                                PIPE_SWIZZLE_X);
 457    uint32_t bpcs[3] = {bits, bits, bits}; /* TODO: use right bpc for each channel ? */
 458    nir_ssa_def *result = nir_convert_ycbcr_to_rgb(builder,
 459                                                   ycbcr_sampler->ycbcr_model,
 460                                                   ycbcr_sampler->ycbcr_range,
 461                                                   &tex->dest.ssa,
 462                                                   bpcs);
 463    nir_ssa_def_rewrite_uses_after(&tex->dest.ssa, nir_src_for_ssa(result),
 464                                   result->parent_instr);
 465
 466    builder->cursor = nir_before_instr(&tex->instr);
 467 }
 468
 469 static bool
 470 lower_tex(nir_builder *b, nir_tex_instr *tex,
 471           struct tu_shader *shader, const struct tu_pipeline_layout *layout)
 472 {
 473    lower_tex_ycbcr(layout, b, tex);
 474
 475    int sampler_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_deref);
 476    if (sampler_src_idx >= 0) {
 477       nir_deref_instr *deref = nir_src_as_deref(tex->src[sampler_src_idx].src);
 478       nir_ssa_def *bindless = build_bindless(b, deref, true, shader, layout);
 479       nir_instr_rewrite_src(&tex->instr, &tex->src[sampler_src_idx].src,
 480                             nir_src_for_ssa(bindless));
 481       tex->src[sampler_src_idx].src_type = nir_tex_src_sampler_handle;
 482    }
 483
 484    int tex_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 485    if (tex_src_idx >= 0) {
 486       nir_deref_instr *deref = nir_src_as_deref(tex->src[tex_src_idx].src);
 487       nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 488       nir_instr_rewrite_src(&tex->instr, &tex->src[tex_src_idx].src,
 489                             nir_src_for_ssa(bindless));
 490       tex->src[tex_src_idx].src_type = nir_tex_src_texture_handle;
 491
 492       /* for the input attachment case: */
 493       if (bindless->parent_instr->type != nir_instr_type_intrinsic)
 494          tex->src[tex_src_idx].src_type = nir_tex_src_texture_offset;
 495    }
 496
 497    return true;
 498 }
 499
 500 static bool
 501 lower_impl(nir_function_impl *impl, struct tu_shader *shader,
 502             const struct tu_pipeline_layout *layout)
 503 {
 504    nir_builder b;
 505    nir_builder_init(&b, impl);
 506    bool progress = false;
 507
 508    nir_foreach_block(block, impl) {
 509       nir_foreach_instr_safe(instr, block) {
 510          b.cursor = nir_before_instr(instr);
 511          switch (instr->type) {
 512          case nir_instr_type_tex:
 513             progress |= lower_tex(&b, nir_instr_as_tex(instr), shader, layout);
 514             break;
 515          case nir_instr_type_intrinsic:
 516             progress |= lower_intrinsic(&b, nir_instr_as_intrinsic(instr), shader, layout);
 517             break;
 518          default:
 519             break;
 520          }
 521       }
 522    }
 523
 524    if (progress)
 525       nir_metadata_preserve(impl, nir_metadata_none);
 526    else
 527       nir_metadata_preserve(impl, nir_metadata_all);
 528
 529    return progress;
 530 }
 531
 532
 533 /* Figure out the range of push constants that we're actually going to push to
 534  * the shader, and tell the backend to reserve this range when pushing UBO
 535  * constants.
 536  */
 537
 538 static void
 539 gather_push_constants(nir_shader *shader, struct tu_shader *tu_shader)
 540 {
 541    uint32_t min = UINT32_MAX, max = 0;
 542    nir_foreach_function(function, shader) {
 543       if (!function->impl)
 544          continue;
 545
 546       nir_foreach_block(block, function->impl) {
 547          nir_foreach_instr_safe(instr, block) {
 548             if (instr->type != nir_instr_type_intrinsic)
 549                continue;
 550
 551             nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 552             if (intrin->intrinsic != nir_intrinsic_load_push_constant)
 553                continue;
 554
 555             uint32_t base = nir_intrinsic_base(intrin);
 556             uint32_t range = nir_intrinsic_range(intrin);
 557             min = MIN2(min, base);
 558             max = MAX2(max, base + range);
 559             break;
 560          }
 561       }
 562    }
 563
 564    if (min >= max) {
 565       tu_shader->push_consts.lo = 0;
 566       tu_shader->push_consts.count = 0;
 567       return;
 568    }
 569
 570    /* CP_LOAD_STATE OFFSET and NUM_UNIT are in units of vec4 (4 dwords),
 571     * however there's an alignment requirement of 4 on OFFSET. Expand the
 572     * range and change units accordingly.
 573     */
 574    tu_shader->push_consts.lo = (min / 16) / 4 * 4;
 575    tu_shader->push_consts.count =
 576       align(max, 16) / 16 - tu_shader->push_consts.lo;
 577 }
 578
 579 static bool
 580 tu_lower_io(nir_shader *shader, struct tu_shader *tu_shader,
 581             const struct tu_pipeline_layout *layout)
 582 {
 583    bool progress = false;
 584
 585    gather_push_constants(shader, tu_shader);
 586
 587    nir_foreach_function(function, shader) {
 588       if (function->impl)
 589          progress |= lower_impl(function->impl, tu_shader, layout);
 590    }
 591
 592    /* Remove now-unused variables so that when we gather the shader info later
 593     * they won't be counted.
 594     */
 595
 596    if (progress)
 597       nir_opt_dce(shader);
 598
 599    progress |=
 600       nir_remove_dead_variables(shader,
 601                                 nir_var_uniform | nir_var_mem_ubo | nir_var_mem_ssbo,
 602                                 NULL);
 603
 604    return progress;
 605 }
 606
 607 static void
 608 shared_type_info(const struct glsl_type *type, unsigned *size, unsigned *align)
 609 {
 610    assert(glsl_type_is_vector_or_scalar(type));
 611
 612    unsigned comp_size =
 613       glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
 614    unsigned length = glsl_get_vector_elements(type);
 615    *size = comp_size * length;
 616    *align = 4;
 617 }
 618
 619 static void
 620 tu_gather_xfb_info(nir_shader *nir, struct ir3_stream_output_info *info)
 621 {
 622    nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
 623
 624    if (!xfb)
 625       return;
 626
 627    /* creating a map from VARYING_SLOT_* enums to consecutive index */
 628    uint8_t num_outputs = 0;
 629    uint64_t outputs_written = 0;
 630    for (int i = 0; i < xfb->output_count; i++)
 631       outputs_written |= BITFIELD64_BIT(xfb->outputs[i].location);
 632
 633    uint8_t output_map[VARYING_SLOT_TESS_MAX];
 634    memset(output_map, 0, sizeof(output_map));
 635
 636    for (unsigned attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 637       if (outputs_written & BITFIELD64_BIT(attr))
 638          output_map[attr] = num_outputs++;
 639    }
 640
 641    assert(xfb->output_count < IR3_MAX_SO_OUTPUTS);
 642    info->num_outputs = xfb->output_count;
 643
 644    for (int i = 0; i < IR3_MAX_SO_BUFFERS; i++)
 645       info->stride[i] = xfb->buffers[i].stride / 4;
 646
 647    for (int i = 0; i < xfb->output_count; i++) {
 648       info->output[i].register_index = output_map[xfb->outputs[i].location];
 649       info->output[i].start_component = xfb->outputs[i].component_offset;
 650       info->output[i].num_components =
 651                            util_bitcount(xfb->outputs[i].component_mask);
 652       info->output[i].output_buffer  = xfb->outputs[i].buffer;
 653       info->output[i].dst_offset = xfb->outputs[i].offset / 4;
 654       info->output[i].stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
 655    }
 656
 657    ralloc_free(xfb);
 658 }
 659
 660 struct tu_shader *
 661 tu_shader_create(struct tu_device *dev,
 662                  gl_shader_stage stage,
 663                  const VkPipelineShaderStageCreateInfo *stage_info,
 664                  struct tu_pipeline_layout *layout,
 665                  const VkAllocationCallbacks *alloc)
 666 {
 667    struct tu_shader *shader;
 668
 669    shader = vk_zalloc2(
 670       &dev->vk.alloc, alloc,
 671       sizeof(*shader),
 672       8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
 673    if (!shader)
 674       return NULL;
 675
 676    nir_shader *nir;
 677    if (stage_info) {
 678       /* translate SPIR-V to NIR */
 679       const struct tu_shader_module *module =
 680          tu_shader_module_from_handle(stage_info->module);
 681       assert(module->code_size % 4 == 0);
 682       nir = tu_spirv_to_nir(
 683          dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
 684          stage, stage_info->pName, stage_info->pSpecializationInfo);
 685    } else {
 686       assert(stage == MESA_SHADER_FRAGMENT);
 687       nir_builder fs_b;
 688       const nir_shader_compiler_options *nir_options =
 689          ir3_get_compiler_options(dev->compiler);
 690       nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, nir_options);
 691       fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
 692       nir = fs_b.shader;
 693    }
 694
 695    if (!nir) {
 696       vk_free2(&dev->vk.alloc, alloc, shader);
 697       return NULL;
 698    }
 699
 700    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
 701       fprintf(stderr, "translated nir:\n");
 702       nir_print_shader(nir, stderr);
 703    }
 704
 705    /* multi step inlining procedure */
 706    NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
 707    NIR_PASS_V(nir, nir_lower_returns);
 708    NIR_PASS_V(nir, nir_inline_functions);
 709    NIR_PASS_V(nir, nir_copy_prop);
 710    NIR_PASS_V(nir, nir_opt_deref);
 711    foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 712       if (!func->is_entrypoint)
 713          exec_node_remove(&func->node);
 714    }
 715    assert(exec_list_length(&nir->functions) == 1);
 716    NIR_PASS_V(nir, nir_lower_variable_initializers, ~nir_var_function_temp);
 717
 718    /* Split member structs.  We do this before lower_io_to_temporaries so that
 719     * it doesn't lower system values to temporaries by accident.
 720     */
 721    NIR_PASS_V(nir, nir_split_var_copies);
 722    NIR_PASS_V(nir, nir_split_per_member_structs);
 723
 724    NIR_PASS_V(nir, nir_remove_dead_variables,
 725               nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
 726               NULL);
 727
 728    /* Gather information for transform feedback.
 729     * This should be called after nir_split_per_member_structs.
 730     * Also needs to be called after nir_remove_dead_variables with varyings,
 731     * so that we could align stream outputs correctly.
 732     */
 733    struct ir3_stream_output_info so_info = {};
 734    if (nir->info.stage == MESA_SHADER_VERTEX ||
 735          nir->info.stage == MESA_SHADER_TESS_EVAL ||
 736          nir->info.stage == MESA_SHADER_GEOMETRY)
 737       tu_gather_xfb_info(nir, &so_info);
 738
 739    NIR_PASS_V(nir, nir_propagate_invariant);
 740
 741    NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, true);
 742
 743    NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 744    NIR_PASS_V(nir, nir_split_var_copies);
 745    NIR_PASS_V(nir, nir_lower_var_copies);
 746
 747    NIR_PASS_V(nir, nir_opt_copy_prop_vars);
 748    NIR_PASS_V(nir, nir_opt_combine_stores, nir_var_all);
 749
 750    /* ir3 doesn't support indirect input/output */
 751    /* TODO: We shouldn't perform this lowering pass on gl_TessLevelInner
 752     * and gl_TessLevelOuter. Since the tess levels are actually stored in
 753     * a global BO, they can be directly accessed via stg and ldg.
 754     * nir_lower_indirect_derefs will instead generate a big if-ladder which
 755     * isn't *incorrect* but is much less efficient. */
 756    NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out);
 757
 758    NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 759
 760    nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs, stage);
 761    nir_assign_io_var_locations(nir, nir_var_shader_out, &nir->num_outputs, stage);
 762
 763    NIR_PASS_V(nir, nir_lower_system_values);
 764    NIR_PASS_V(nir, nir_lower_frexp);
 765
 766    if (stage == MESA_SHADER_FRAGMENT) {
 767       NIR_PASS_V(nir, nir_lower_input_attachments,
 768                  &(nir_input_attachment_options) {
 769                      .use_fragcoord_sysval = true,
 770                      .use_layer_id_sysval = false,
 771                  });
 772    }
 773
 774    NIR_PASS_V(nir, nir_lower_explicit_io,
 775               nir_var_mem_ubo | nir_var_mem_ssbo,
 776               nir_address_format_vec2_index_32bit_offset);
 777
 778    if (nir->info.stage == MESA_SHADER_COMPUTE) {
 779       NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
 780                  nir_var_mem_shared, shared_type_info);
 781       NIR_PASS_V(nir, nir_lower_explicit_io,
 782                  nir_var_mem_shared,
 783                  nir_address_format_32bit_offset);
 784    }
 785
 786    NIR_PASS_V(nir, tu_lower_io, shader, layout);
 787
 788    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 789
 790    ir3_finalize_nir(dev->compiler, nir);
 791
 792    shader->ir3_shader =
 793       ir3_shader_from_nir(dev->compiler, nir,
 794                           align(shader->push_consts.count, 4),
 795                           &so_info);
 796
 797    return shader;
 798 }
 799
 800 void
 801 tu_shader_destroy(struct tu_device *dev,
 802                   struct tu_shader *shader,
 803                   const VkAllocationCallbacks *alloc)
 804 {
 805    ir3_shader_destroy(shader->ir3_shader);
 806
 807    vk_free2(&dev->vk.alloc, alloc, shader);
 808 }
 809
 810 VkResult
 811 tu_CreateShaderModule(VkDevice _device,
 812                       const VkShaderModuleCreateInfo *pCreateInfo,
 813                       const VkAllocationCallbacks *pAllocator,
 814                       VkShaderModule *pShaderModule)
 815 {
 816    TU_FROM_HANDLE(tu_device, device, _device);
 817    struct tu_shader_module *module;
 818
 819    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
 820    assert(pCreateInfo->flags == 0);
 821    assert(pCreateInfo->codeSize % 4 == 0);
 822
 823    module = vk_object_alloc(&device->vk, pAllocator,
 824                             sizeof(*module) + pCreateInfo->codeSize,
 825                             VK_OBJECT_TYPE_SHADER_MODULE);
 826    if (module == NULL)
 827       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 828
 829    module->code_size = pCreateInfo->codeSize;
 830    memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
 831
 832    _mesa_sha1_compute(module->code, module->code_size, module->sha1);
 833
 834    *pShaderModule = tu_shader_module_to_handle(module);
 835
 836    return VK_SUCCESS;
 837 }
 838
 839 void
 840 tu_DestroyShaderModule(VkDevice _device,
 841                        VkShaderModule _module,
 842                        const VkAllocationCallbacks *pAllocator)
 843 {
 844    TU_FROM_HANDLE(tu_device, device, _device);
 845    TU_FROM_HANDLE(tu_shader_module, module, _module);
 846
 847    if (!module)
 848       return;
 849
 850    vk_object_free(&device->vk, pAllocator, module);
 851 }