src/freedreno/vulkan/tu_shader.c

   1 /*
   2  * Copyright © 2019 Google LLC
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "tu_private.h"
  25
  26 #include "spirv/nir_spirv.h"
  27 #include "util/mesa-sha1.h"
  28 #include "nir/nir_xfb_info.h"
  29 #include "nir/nir_vulkan.h"
  30 #include "vk_util.h"
  31
  32 #include "ir3/ir3_nir.h"
  33
  34 static nir_shader *
  35 tu_spirv_to_nir(struct ir3_compiler *compiler,
  36                 const uint32_t *words,
  37                 size_t word_count,
  38                 gl_shader_stage stage,
  39                 const char *entry_point_name,
  40                 const VkSpecializationInfo *spec_info)
  41 {
  42    /* TODO these are made-up */
  43    const struct spirv_to_nir_options spirv_options = {
  44       .frag_coord_is_sysval = true,
  45       .lower_ubo_ssbo_access_to_offsets = false,
  46
  47       .ubo_addr_format = nir_address_format_vec2_index_32bit_offset,
  48       .ssbo_addr_format = nir_address_format_vec2_index_32bit_offset,
  49
  50       /* Accessed via stg/ldg */
  51       .phys_ssbo_addr_format = nir_address_format_64bit_global,
  52
  53       /* Accessed via the const register file */
  54       .push_const_addr_format = nir_address_format_logical,
  55
  56       /* Accessed via ldl/stl */
  57       .shared_addr_format = nir_address_format_32bit_offset,
  58
  59       /* Accessed via stg/ldg (not used with Vulkan?) */
  60       .global_addr_format = nir_address_format_64bit_global,
  61
  62       .caps = {
  63          .transform_feedback = true,
  64          .tessellation = true,
  65          .draw_parameters = true,
  66          .variable_pointers = true,
  67       },
  68    };
  69    const nir_shader_compiler_options *nir_options =
  70       ir3_get_compiler_options(compiler);
  71
  72    /* convert VkSpecializationInfo */
  73    struct nir_spirv_specialization *spec = NULL;
  74    uint32_t num_spec = 0;
  75    if (spec_info && spec_info->mapEntryCount) {
  76       spec = calloc(spec_info->mapEntryCount, sizeof(*spec));
  77       if (!spec)
  78          return NULL;
  79
  80       for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
  81          const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
  82          const void *data = spec_info->pData + entry->offset;
  83          assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
  84          spec[i].id = entry->constantID;
  85          switch (entry->size) {
  86          case 8:
  87             spec[i].value.u64 = *(const uint64_t *)data;
  88             break;
  89          case 4:
  90             spec[i].value.u32 = *(const uint32_t *)data;
  91             break;
  92          case 2:
  93             spec[i].value.u16 = *(const uint16_t *)data;
  94             break;
  95          case 1:
  96             spec[i].value.u8 = *(const uint8_t *)data;
  97             break;
  98          default:
  99             assert(!"Invalid spec constant size");
 100             break;
 101          }
 102          spec[i].defined_on_module = false;
 103       }
 104
 105       num_spec = spec_info->mapEntryCount;
 106    }
 107
 108    nir_shader *nir =
 109       spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
 110                    &spirv_options, nir_options);
 111
 112    free(spec);
 113
 114    assert(nir->info.stage == stage);
 115    nir_validate_shader(nir, "after spirv_to_nir");
 116
 117    return nir;
 118 }
 119
 120 static void
 121 lower_load_push_constant(nir_builder *b, nir_intrinsic_instr *instr,
 122                          struct tu_shader *shader)
 123 {
 124    nir_intrinsic_instr *load =
 125       nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
 126    load->num_components = instr->num_components;
 127    uint32_t base = nir_intrinsic_base(instr);
 128    assert(base % 4 == 0);
 129    assert(base >= shader->push_consts.lo * 16);
 130    base -= shader->push_consts.lo * 16;
 131    nir_intrinsic_set_base(load, base / 4);
 132    load->src[0] =
 133       nir_src_for_ssa(nir_ushr(b, instr->src[0].ssa, nir_imm_int(b, 2)));
 134    nir_ssa_dest_init(&load->instr, &load->dest,
 135                      load->num_components, instr->dest.ssa.bit_size,
 136                      instr->dest.ssa.name);
 137    nir_builder_instr_insert(b, &load->instr);
 138    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(&load->dest.ssa));
 139
 140    nir_instr_remove(&instr->instr);
 141 }
 142
 143 static void
 144 lower_vulkan_resource_index(nir_builder *b, nir_intrinsic_instr *instr,
 145                             struct tu_shader *shader,
 146                             const struct tu_pipeline_layout *layout)
 147 {
 148    nir_ssa_def *vulkan_idx = instr->src[0].ssa;
 149
 150    unsigned set = nir_intrinsic_desc_set(instr);
 151    unsigned binding = nir_intrinsic_binding(instr);
 152    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 153    struct tu_descriptor_set_binding_layout *binding_layout =
 154       &set_layout->binding[binding];
 155    uint32_t base;
 156
 157    shader->active_desc_sets |= 1u << set;
 158
 159    switch (binding_layout->type) {
 160    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 161    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 162       base = layout->set[set].dynamic_offset_start +
 163          binding_layout->dynamic_offset_offset;
 164       set = MAX_SETS;
 165       break;
 166    default:
 167       base = binding_layout->offset / (4 * A6XX_TEX_CONST_DWORDS);
 168       break;
 169    }
 170
 171    nir_ssa_def *def = nir_vec3(b, nir_imm_int(b, set),
 172                                nir_iadd(b, nir_imm_int(b, base), vulkan_idx),
 173                                nir_imm_int(b, 0));
 174
 175    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(def));
 176    nir_instr_remove(&instr->instr);
 177 }
 178
 179 static void
 180 lower_load_vulkan_descriptor(nir_intrinsic_instr *intrin)
 181 {
 182    /* Loading the descriptor happens as part of the load/store instruction so
 183     * this is a no-op.
 184     */
 185    nir_ssa_def_rewrite_uses(&intrin->dest.ssa, intrin->src[0]);
 186    nir_instr_remove(&intrin->instr);
 187 }
 188
 189 static void
 190 lower_ssbo_ubo_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin)
 191 {
 192    const nir_intrinsic_info *info = &nir_intrinsic_infos[intrin->intrinsic];
 193
 194    /* The bindless base is part of the instruction, which means that part of
 195     * the "pointer" has to be constant. We solve this in the same way the blob
 196     * does, by generating a bunch of if-statements. In the usual case where
 197     * the descriptor set is constant this will get optimized out.
 198     */
 199
 200    unsigned buffer_src;
 201    if (intrin->intrinsic == nir_intrinsic_store_ssbo) {
 202       /* This has the value first */
 203       buffer_src = 1;
 204    } else {
 205       buffer_src = 0;
 206    }
 207
 208    nir_ssa_def *base_idx = nir_channel(b, intrin->src[buffer_src].ssa, 0);
 209    nir_ssa_def *descriptor_idx = nir_channel(b, intrin->src[buffer_src].ssa, 1);
 210
 211    nir_ssa_def *results[MAX_SETS + 1] = { NULL };
 212
 213    for (unsigned i = 0; i < MAX_SETS + 1; i++) {
 214       /* if (base_idx == i) { ... */
 215       nir_if *nif = nir_push_if(b, nir_ieq(b, base_idx, nir_imm_int(b, i)));
 216
 217       nir_intrinsic_instr *bindless =
 218          nir_intrinsic_instr_create(b->shader,
 219                                     nir_intrinsic_bindless_resource_ir3);
 220       bindless->num_components = 0;
 221       nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 222                         1, 32, NULL);
 223       nir_intrinsic_set_desc_set(bindless, i);
 224       bindless->src[0] = nir_src_for_ssa(descriptor_idx);
 225       nir_builder_instr_insert(b, &bindless->instr);
 226
 227       nir_intrinsic_instr *copy =
 228          nir_intrinsic_instr_create(b->shader, intrin->intrinsic);
 229
 230       copy->num_components = intrin->num_components;
 231
 232       for (unsigned src = 0; src < info->num_srcs; src++) {
 233          if (src == buffer_src)
 234             copy->src[src] = nir_src_for_ssa(&bindless->dest.ssa);
 235          else
 236             copy->src[src] = nir_src_for_ssa(intrin->src[src].ssa);
 237       }
 238
 239       for (unsigned idx = 0; idx < info->num_indices; idx++) {
 240          copy->const_index[idx] = intrin->const_index[idx];
 241       }
 242
 243       if (info->has_dest) {
 244          nir_ssa_dest_init(&copy->instr, &copy->dest,
 245                            intrin->dest.ssa.num_components,
 246                            intrin->dest.ssa.bit_size,
 247                            intrin->dest.ssa.name);
 248          results[i] = &copy->dest.ssa;
 249       }
 250
 251       nir_builder_instr_insert(b, &copy->instr);
 252
 253       /* } else { ... */
 254       nir_push_else(b, nif);
 255    }
 256
 257    nir_ssa_def *result =
 258       nir_ssa_undef(b, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size);
 259    for (int i = MAX_SETS; i >= 0; i--) {
 260       nir_pop_if(b, NULL);
 261       if (info->has_dest)
 262          result = nir_if_phi(b, results[i], result);
 263    }
 264
 265    if (info->has_dest)
 266       nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(result));
 267    nir_instr_remove(&intrin->instr);
 268 }
 269
 270 static nir_ssa_def *
 271 build_bindless(nir_builder *b, nir_deref_instr *deref, bool is_sampler,
 272                struct tu_shader *shader,
 273                const struct tu_pipeline_layout *layout)
 274 {
 275    nir_variable *var = nir_deref_instr_get_variable(deref);
 276
 277    unsigned set = var->data.descriptor_set;
 278    unsigned binding = var->data.binding;
 279    const struct tu_descriptor_set_binding_layout *bind_layout =
 280       &layout->set[set].layout->binding[binding];
 281
 282    /* input attachments use non bindless workaround */
 283    if (bind_layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
 284       const struct glsl_type *glsl_type = glsl_without_array(var->type);
 285       uint32_t idx = var->data.index * 2;
 286
 287       b->shader->info.textures_used |=
 288          ((1ull << (bind_layout->array_size * 2)) - 1) << (idx * 2);
 289
 290       /* D24S8 workaround: stencil of D24S8 will be sampled as uint */
 291       if (glsl_get_sampler_result_type(glsl_type) == GLSL_TYPE_UINT)
 292          idx += 1;
 293
 294       if (deref->deref_type == nir_deref_type_var)
 295          return nir_imm_int(b, idx);
 296
 297       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 298       return nir_iadd(b, nir_imm_int(b, idx),
 299                       nir_imul_imm(b, arr_index, 2));
 300    }
 301
 302    shader->active_desc_sets |= 1u << set;
 303
 304    nir_ssa_def *desc_offset;
 305    unsigned descriptor_stride;
 306    unsigned offset = 0;
 307    /* Samplers come second in combined image/sampler descriptors, see
 308       * write_combined_image_sampler_descriptor().
 309       */
 310    if (is_sampler && bind_layout->type ==
 311          VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
 312       offset = 1;
 313    }
 314    desc_offset =
 315       nir_imm_int(b, (bind_layout->offset / (4 * A6XX_TEX_CONST_DWORDS)) +
 316                   offset);
 317    descriptor_stride = bind_layout->size / (4 * A6XX_TEX_CONST_DWORDS);
 318
 319    if (deref->deref_type != nir_deref_type_var) {
 320       assert(deref->deref_type == nir_deref_type_array);
 321
 322       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 323       desc_offset = nir_iadd(b, desc_offset,
 324                              nir_imul_imm(b, arr_index, descriptor_stride));
 325    }
 326
 327    nir_intrinsic_instr *bindless =
 328       nir_intrinsic_instr_create(b->shader,
 329                                  nir_intrinsic_bindless_resource_ir3);
 330    bindless->num_components = 0;
 331    nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 332                      1, 32, NULL);
 333    nir_intrinsic_set_desc_set(bindless, set);
 334    bindless->src[0] = nir_src_for_ssa(desc_offset);
 335    nir_builder_instr_insert(b, &bindless->instr);
 336
 337    return &bindless->dest.ssa;
 338 }
 339
 340 static void
 341 lower_image_deref(nir_builder *b,
 342                   nir_intrinsic_instr *instr, struct tu_shader *shader,
 343                   const struct tu_pipeline_layout *layout)
 344 {
 345    nir_deref_instr *deref = nir_src_as_deref(instr->src[0]);
 346    nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 347    nir_rewrite_image_intrinsic(instr, bindless, true);
 348 }
 349
 350 static bool
 351 lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
 352                 struct tu_shader *shader,
 353                 const struct tu_pipeline_layout *layout)
 354 {
 355    switch (instr->intrinsic) {
 356    case nir_intrinsic_load_layer_id:
 357       /* TODO: remove this when layered rendering is implemented */
 358       nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 359                                nir_src_for_ssa(nir_imm_int(b, 0)));
 360       nir_instr_remove(&instr->instr);
 361       return true;
 362
 363    case nir_intrinsic_load_push_constant:
 364       lower_load_push_constant(b, instr, shader);
 365       return true;
 366
 367    case nir_intrinsic_load_vulkan_descriptor:
 368       lower_load_vulkan_descriptor(instr);
 369       return true;
 370
 371    case nir_intrinsic_vulkan_resource_index:
 372       lower_vulkan_resource_index(b, instr, shader, layout);
 373       return true;
 374
 375    case nir_intrinsic_load_ubo:
 376    case nir_intrinsic_load_ssbo:
 377    case nir_intrinsic_store_ssbo:
 378    case nir_intrinsic_ssbo_atomic_add:
 379    case nir_intrinsic_ssbo_atomic_imin:
 380    case nir_intrinsic_ssbo_atomic_umin:
 381    case nir_intrinsic_ssbo_atomic_imax:
 382    case nir_intrinsic_ssbo_atomic_umax:
 383    case nir_intrinsic_ssbo_atomic_and:
 384    case nir_intrinsic_ssbo_atomic_or:
 385    case nir_intrinsic_ssbo_atomic_xor:
 386    case nir_intrinsic_ssbo_atomic_exchange:
 387    case nir_intrinsic_ssbo_atomic_comp_swap:
 388    case nir_intrinsic_ssbo_atomic_fadd:
 389    case nir_intrinsic_ssbo_atomic_fmin:
 390    case nir_intrinsic_ssbo_atomic_fmax:
 391    case nir_intrinsic_ssbo_atomic_fcomp_swap:
 392    case nir_intrinsic_get_buffer_size:
 393       lower_ssbo_ubo_intrinsic(b, instr);
 394       return true;
 395
 396    case nir_intrinsic_image_deref_load:
 397    case nir_intrinsic_image_deref_store:
 398    case nir_intrinsic_image_deref_atomic_add:
 399    case nir_intrinsic_image_deref_atomic_imin:
 400    case nir_intrinsic_image_deref_atomic_umin:
 401    case nir_intrinsic_image_deref_atomic_imax:
 402    case nir_intrinsic_image_deref_atomic_umax:
 403    case nir_intrinsic_image_deref_atomic_and:
 404    case nir_intrinsic_image_deref_atomic_or:
 405    case nir_intrinsic_image_deref_atomic_xor:
 406    case nir_intrinsic_image_deref_atomic_exchange:
 407    case nir_intrinsic_image_deref_atomic_comp_swap:
 408    case nir_intrinsic_image_deref_size:
 409    case nir_intrinsic_image_deref_samples:
 410       lower_image_deref(b, instr, shader, layout);
 411       return true;
 412
 413    default:
 414       return false;
 415    }
 416 }
 417
 418 static void
 419 lower_tex_ycbcr(const struct tu_pipeline_layout *layout,
 420                 nir_builder *builder,
 421                 nir_tex_instr *tex)
 422 {
 423    int deref_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 424    assert(deref_src_idx >= 0);
 425    nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src);
 426
 427    nir_variable *var = nir_deref_instr_get_variable(deref);
 428    const struct tu_descriptor_set_layout *set_layout =
 429       layout->set[var->data.descriptor_set].layout;
 430    const struct tu_descriptor_set_binding_layout *binding =
 431       &set_layout->binding[var->data.binding];
 432    const struct tu_sampler_ycbcr_conversion *ycbcr_samplers =
 433       tu_immutable_ycbcr_samplers(set_layout, binding);
 434
 435    if (!ycbcr_samplers)
 436       return;
 437
 438    /* For the following instructions, we don't apply any change */
 439    if (tex->op == nir_texop_txs ||
 440        tex->op == nir_texop_query_levels ||
 441        tex->op == nir_texop_lod)
 442       return;
 443
 444    assert(tex->texture_index == 0);
 445    unsigned array_index = 0;
 446    if (deref->deref_type != nir_deref_type_var) {
 447       assert(deref->deref_type == nir_deref_type_array);
 448       if (!nir_src_is_const(deref->arr.index))
 449          return;
 450       array_index = nir_src_as_uint(deref->arr.index);
 451       array_index = MIN2(array_index, binding->array_size - 1);
 452    }
 453    const struct tu_sampler_ycbcr_conversion *ycbcr_sampler = ycbcr_samplers + array_index;
 454
 455    if (ycbcr_sampler->ycbcr_model == VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY)
 456       return;
 457
 458    builder->cursor = nir_after_instr(&tex->instr);
 459
 460    uint8_t bits = vk_format_get_component_bits(ycbcr_sampler->format,
 461                                                UTIL_FORMAT_COLORSPACE_RGB,
 462                                                PIPE_SWIZZLE_X);
 463    uint32_t bpcs[3] = {bits, bits, bits}; /* TODO: use right bpc for each channel ? */
 464    nir_ssa_def *result = nir_convert_ycbcr_to_rgb(builder,
 465                                                   ycbcr_sampler->ycbcr_model,
 466                                                   ycbcr_sampler->ycbcr_range,
 467                                                   &tex->dest.ssa,
 468                                                   bpcs);
 469    nir_ssa_def_rewrite_uses_after(&tex->dest.ssa, nir_src_for_ssa(result),
 470                                   result->parent_instr);
 471
 472    builder->cursor = nir_before_instr(&tex->instr);
 473 }
 474
 475 static bool
 476 lower_tex(nir_builder *b, nir_tex_instr *tex,
 477           struct tu_shader *shader, const struct tu_pipeline_layout *layout)
 478 {
 479    lower_tex_ycbcr(layout, b, tex);
 480
 481    int sampler_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_deref);
 482    if (sampler_src_idx >= 0) {
 483       nir_deref_instr *deref = nir_src_as_deref(tex->src[sampler_src_idx].src);
 484       nir_ssa_def *bindless = build_bindless(b, deref, true, shader, layout);
 485       nir_instr_rewrite_src(&tex->instr, &tex->src[sampler_src_idx].src,
 486                             nir_src_for_ssa(bindless));
 487       tex->src[sampler_src_idx].src_type = nir_tex_src_sampler_handle;
 488    }
 489
 490    int tex_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 491    if (tex_src_idx >= 0) {
 492       nir_deref_instr *deref = nir_src_as_deref(tex->src[tex_src_idx].src);
 493       nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 494       nir_instr_rewrite_src(&tex->instr, &tex->src[tex_src_idx].src,
 495                             nir_src_for_ssa(bindless));
 496       tex->src[tex_src_idx].src_type = nir_tex_src_texture_handle;
 497
 498       /* for the input attachment case: */
 499       if (bindless->parent_instr->type != nir_instr_type_intrinsic)
 500          tex->src[tex_src_idx].src_type = nir_tex_src_texture_offset;
 501    }
 502
 503    return true;
 504 }
 505
 506 static bool
 507 lower_impl(nir_function_impl *impl, struct tu_shader *shader,
 508             const struct tu_pipeline_layout *layout)
 509 {
 510    nir_builder b;
 511    nir_builder_init(&b, impl);
 512    bool progress = false;
 513
 514    nir_foreach_block(block, impl) {
 515       nir_foreach_instr_safe(instr, block) {
 516          b.cursor = nir_before_instr(instr);
 517          switch (instr->type) {
 518          case nir_instr_type_tex:
 519             progress |= lower_tex(&b, nir_instr_as_tex(instr), shader, layout);
 520             break;
 521          case nir_instr_type_intrinsic:
 522             progress |= lower_intrinsic(&b, nir_instr_as_intrinsic(instr), shader, layout);
 523             break;
 524          default:
 525             break;
 526          }
 527       }
 528    }
 529
 530    if (progress)
 531       nir_metadata_preserve(impl, nir_metadata_none);
 532    else
 533       nir_metadata_preserve(impl, nir_metadata_all);
 534
 535    return progress;
 536 }
 537
 538
 539 /* Figure out the range of push constants that we're actually going to push to
 540  * the shader, and tell the backend to reserve this range when pushing UBO
 541  * constants.
 542  */
 543
 544 static void
 545 gather_push_constants(nir_shader *shader, struct tu_shader *tu_shader)
 546 {
 547    uint32_t min = UINT32_MAX, max = 0;
 548    nir_foreach_function(function, shader) {
 549       if (!function->impl)
 550          continue;
 551
 552       nir_foreach_block(block, function->impl) {
 553          nir_foreach_instr_safe(instr, block) {
 554             if (instr->type != nir_instr_type_intrinsic)
 555                continue;
 556
 557             nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 558             if (intrin->intrinsic != nir_intrinsic_load_push_constant)
 559                continue;
 560
 561             uint32_t base = nir_intrinsic_base(intrin);
 562             uint32_t range = nir_intrinsic_range(intrin);
 563             min = MIN2(min, base);
 564             max = MAX2(max, base + range);
 565             break;
 566          }
 567       }
 568    }
 569
 570    if (min >= max) {
 571       tu_shader->push_consts.lo = 0;
 572       tu_shader->push_consts.count = 0;
 573       return;
 574    }
 575
 576    /* CP_LOAD_STATE OFFSET and NUM_UNIT are in units of vec4 (4 dwords),
 577     * however there's an alignment requirement of 4 on OFFSET. Expand the
 578     * range and change units accordingly.
 579     */
 580    tu_shader->push_consts.lo = (min / 16) / 4 * 4;
 581    tu_shader->push_consts.count =
 582       align(max, 16) / 16 - tu_shader->push_consts.lo;
 583 }
 584
 585 static bool
 586 tu_lower_io(nir_shader *shader, struct tu_shader *tu_shader,
 587             const struct tu_pipeline_layout *layout)
 588 {
 589    bool progress = false;
 590
 591    gather_push_constants(shader, tu_shader);
 592
 593    nir_foreach_function(function, shader) {
 594       if (function->impl)
 595          progress |= lower_impl(function->impl, tu_shader, layout);
 596    }
 597
 598    /* Remove now-unused variables so that when we gather the shader info later
 599     * they won't be counted.
 600     */
 601
 602    if (progress)
 603       nir_opt_dce(shader);
 604
 605    progress |=
 606       nir_remove_dead_variables(shader,
 607                                 nir_var_uniform | nir_var_mem_ubo | nir_var_mem_ssbo,
 608                                 NULL);
 609
 610    return progress;
 611 }
 612
 613 static void
 614 shared_type_info(const struct glsl_type *type, unsigned *size, unsigned *align)
 615 {
 616    assert(glsl_type_is_vector_or_scalar(type));
 617
 618    unsigned comp_size =
 619       glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
 620    unsigned length = glsl_get_vector_elements(type);
 621    *size = comp_size * length;
 622    *align = 4;
 623 }
 624
 625 static void
 626 tu_gather_xfb_info(nir_shader *nir, struct ir3_stream_output_info *info)
 627 {
 628    nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
 629
 630    if (!xfb)
 631       return;
 632
 633    /* creating a map from VARYING_SLOT_* enums to consecutive index */
 634    uint8_t num_outputs = 0;
 635    uint64_t outputs_written = 0;
 636    for (int i = 0; i < xfb->output_count; i++)
 637       outputs_written |= BITFIELD64_BIT(xfb->outputs[i].location);
 638
 639    uint8_t output_map[VARYING_SLOT_TESS_MAX];
 640    memset(output_map, 0, sizeof(output_map));
 641
 642    for (unsigned attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 643       if (outputs_written & BITFIELD64_BIT(attr))
 644          output_map[attr] = num_outputs++;
 645    }
 646
 647    assert(xfb->output_count < IR3_MAX_SO_OUTPUTS);
 648    info->num_outputs = xfb->output_count;
 649
 650    for (int i = 0; i < IR3_MAX_SO_BUFFERS; i++)
 651       info->stride[i] = xfb->buffers[i].stride / 4;
 652
 653    for (int i = 0; i < xfb->output_count; i++) {
 654       info->output[i].register_index = output_map[xfb->outputs[i].location];
 655       info->output[i].start_component = xfb->outputs[i].component_offset;
 656       info->output[i].num_components =
 657                            util_bitcount(xfb->outputs[i].component_mask);
 658       info->output[i].output_buffer  = xfb->outputs[i].buffer;
 659       info->output[i].dst_offset = xfb->outputs[i].offset / 4;
 660       info->output[i].stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
 661    }
 662
 663    ralloc_free(xfb);
 664 }
 665
 666 struct tu_shader *
 667 tu_shader_create(struct tu_device *dev,
 668                  gl_shader_stage stage,
 669                  const VkPipelineShaderStageCreateInfo *stage_info,
 670                  struct tu_pipeline_layout *layout,
 671                  const VkAllocationCallbacks *alloc)
 672 {
 673    struct tu_shader *shader;
 674
 675    shader = vk_zalloc2(
 676       &dev->alloc, alloc,
 677       sizeof(*shader),
 678       8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
 679    if (!shader)
 680       return NULL;
 681
 682    nir_shader *nir;
 683    if (stage_info) {
 684       /* translate SPIR-V to NIR */
 685       const struct tu_shader_module *module =
 686          tu_shader_module_from_handle(stage_info->module);
 687       assert(module->code_size % 4 == 0);
 688       nir = tu_spirv_to_nir(
 689          dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
 690          stage, stage_info->pName, stage_info->pSpecializationInfo);
 691    } else {
 692       assert(stage == MESA_SHADER_FRAGMENT);
 693       nir_builder fs_b;
 694       const nir_shader_compiler_options *nir_options =
 695          ir3_get_compiler_options(dev->compiler);
 696       nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, nir_options);
 697       fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
 698       nir = fs_b.shader;
 699    }
 700
 701    if (!nir) {
 702       vk_free2(&dev->alloc, alloc, shader);
 703       return NULL;
 704    }
 705
 706    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
 707       fprintf(stderr, "translated nir:\n");
 708       nir_print_shader(nir, stderr);
 709    }
 710
 711    /* multi step inlining procedure */
 712    NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
 713    NIR_PASS_V(nir, nir_lower_returns);
 714    NIR_PASS_V(nir, nir_inline_functions);
 715    NIR_PASS_V(nir, nir_opt_deref);
 716    foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 717       if (!func->is_entrypoint)
 718          exec_node_remove(&func->node);
 719    }
 720    assert(exec_list_length(&nir->functions) == 1);
 721    NIR_PASS_V(nir, nir_lower_variable_initializers, ~nir_var_function_temp);
 722
 723    /* Split member structs.  We do this before lower_io_to_temporaries so that
 724     * it doesn't lower system values to temporaries by accident.
 725     */
 726    NIR_PASS_V(nir, nir_split_var_copies);
 727    NIR_PASS_V(nir, nir_split_per_member_structs);
 728
 729    NIR_PASS_V(nir, nir_remove_dead_variables,
 730               nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
 731               NULL);
 732
 733    /* Gather information for transform feedback.
 734     * This should be called after nir_split_per_member_structs.
 735     * Also needs to be called after nir_remove_dead_variables with varyings,
 736     * so that we could align stream outputs correctly.
 737     */
 738    struct ir3_stream_output_info so_info = {};
 739    if (nir->info.stage == MESA_SHADER_VERTEX ||
 740          nir->info.stage == MESA_SHADER_TESS_EVAL ||
 741          nir->info.stage == MESA_SHADER_GEOMETRY)
 742       tu_gather_xfb_info(nir, &so_info);
 743
 744    NIR_PASS_V(nir, nir_propagate_invariant);
 745
 746    NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, true);
 747
 748    NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 749    NIR_PASS_V(nir, nir_split_var_copies);
 750    NIR_PASS_V(nir, nir_lower_var_copies);
 751
 752    NIR_PASS_V(nir, nir_opt_copy_prop_vars);
 753    NIR_PASS_V(nir, nir_opt_combine_stores, nir_var_all);
 754
 755    /* ir3 doesn't support indirect input/output */
 756    /* TODO: We shouldn't perform this lowering pass on gl_TessLevelInner
 757     * and gl_TessLevelOuter. Since the tess levels are actually stored in
 758     * a global BO, they can be directly accessed via stg and ldg.
 759     * nir_lower_indirect_derefs will instead generate a big if-ladder which
 760     * isn't *incorrect* but is much less efficient. */
 761    NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out);
 762
 763    NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 764
 765    nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs, stage);
 766    nir_assign_io_var_locations(&nir->outputs, &nir->num_outputs, stage);
 767
 768    NIR_PASS_V(nir, nir_lower_system_values);
 769    NIR_PASS_V(nir, nir_lower_frexp);
 770
 771    if (stage == MESA_SHADER_FRAGMENT)
 772       NIR_PASS_V(nir, nir_lower_input_attachments, true);
 773
 774    NIR_PASS_V(nir, nir_lower_explicit_io,
 775               nir_var_mem_ubo | nir_var_mem_ssbo,
 776               nir_address_format_vec2_index_32bit_offset);
 777
 778    if (nir->info.stage == MESA_SHADER_COMPUTE) {
 779       NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
 780                  nir_var_mem_shared, shared_type_info);
 781       NIR_PASS_V(nir, nir_lower_explicit_io,
 782                  nir_var_mem_shared,
 783                  nir_address_format_32bit_offset);
 784    }
 785
 786    NIR_PASS_V(nir, tu_lower_io, shader, layout);
 787
 788    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 789
 790    ir3_finalize_nir(dev->compiler, nir);
 791
 792    shader->ir3_shader =
 793       ir3_shader_from_nir(dev->compiler, nir,
 794                           align(shader->push_consts.count, 4),
 795                           &so_info);
 796
 797    return shader;
 798 }
 799
 800 void
 801 tu_shader_destroy(struct tu_device *dev,
 802                   struct tu_shader *shader,
 803                   const VkAllocationCallbacks *alloc)
 804 {
 805    ir3_shader_destroy(shader->ir3_shader);
 806
 807    vk_free2(&dev->alloc, alloc, shader);
 808 }
 809
 810 VkResult
 811 tu_CreateShaderModule(VkDevice _device,
 812                       const VkShaderModuleCreateInfo *pCreateInfo,
 813                       const VkAllocationCallbacks *pAllocator,
 814                       VkShaderModule *pShaderModule)
 815 {
 816    TU_FROM_HANDLE(tu_device, device, _device);
 817    struct tu_shader_module *module;
 818
 819    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
 820    assert(pCreateInfo->flags == 0);
 821    assert(pCreateInfo->codeSize % 4 == 0);
 822
 823    module = vk_alloc2(&device->alloc, pAllocator,
 824                       sizeof(*module) + pCreateInfo->codeSize, 8,
 825                       VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 826    if (module == NULL)
 827       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 828
 829    module->code_size = pCreateInfo->codeSize;
 830    memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
 831
 832    _mesa_sha1_compute(module->code, module->code_size, module->sha1);
 833
 834    *pShaderModule = tu_shader_module_to_handle(module);
 835
 836    return VK_SUCCESS;
 837 }
 838
 839 void
 840 tu_DestroyShaderModule(VkDevice _device,
 841                        VkShaderModule _module,
 842                        const VkAllocationCallbacks *pAllocator)
 843 {
 844    TU_FROM_HANDLE(tu_device, device, _device);
 845    TU_FROM_HANDLE(tu_shader_module, module, _module);
 846
 847    if (!module)
 848       return;
 849
 850    vk_free2(&device->alloc, pAllocator, module);
 851 }