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09d7f18881e0b0ad0c902ae7e3882fd22013abc4
[mesa.git] / src / gallium / auxiliary / nir / tgsi_to_nir.c
1 /*
2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/ralloc.h"
26 #include "pipe/p_screen.h"
27
28 #include "compiler/nir/nir.h"
29 #include "compiler/nir/nir_control_flow.h"
30 #include "compiler/nir/nir_builder.h"
31 #include "compiler/glsl/gl_nir.h"
32 #include "compiler/glsl/list.h"
33 #include "compiler/shader_enums.h"
34
35 #include "tgsi_to_nir.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_dump.h"
38 #include "tgsi/tgsi_info.h"
39 #include "tgsi/tgsi_scan.h"
40 #include "tgsi/tgsi_from_mesa.h"
41
42 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
43 TGSI_SWIZZLE_##X, \
44 TGSI_SWIZZLE_##Y, \
45 TGSI_SWIZZLE_##Z, \
46 TGSI_SWIZZLE_##W, \
47 }
48
49 struct ttn_reg_info {
50 /** nir register containing this TGSI index. */
51 nir_register *reg;
52 nir_variable *var;
53 /** Offset (in vec4s) from the start of var for this TGSI index. */
54 int offset;
55 };
56
57 struct ttn_compile {
58 union tgsi_full_token *token;
59 nir_builder build;
60 struct tgsi_shader_info *scan;
61
62 struct ttn_reg_info *output_regs;
63 struct ttn_reg_info *temp_regs;
64 nir_ssa_def **imm_defs;
65
66 unsigned num_samp_types;
67 nir_alu_type *samp_types;
68
69 nir_register *addr_reg;
70
71 nir_variable **inputs;
72 nir_variable **outputs;
73 nir_variable *samplers[PIPE_MAX_SAMPLERS];
74 nir_variable *images[PIPE_MAX_SHADER_IMAGES];
75 nir_variable *ssbo[PIPE_MAX_SHADER_BUFFERS];
76
77 nir_variable *input_var_face;
78 nir_variable *input_var_position;
79 nir_variable *input_var_point;
80
81 /**
82 * Stack of nir_cursors where instructions should be pushed as we pop
83 * back out of the control flow stack.
84 *
85 * For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else
86 * instructions should be placed, and if_stack[if_stack_pos - 1] has where
87 * the next instructions outside of the if/then/else block go.
88 */
89 nir_cursor *if_stack;
90 unsigned if_stack_pos;
91
92 /**
93 * Stack of nir_cursors where instructions should be pushed as we pop
94 * back out of the control flow stack.
95 *
96 * loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside
97 * of the loop.
98 */
99 nir_cursor *loop_stack;
100 unsigned loop_stack_pos;
101
102 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
103 unsigned next_imm;
104
105 bool cap_scalar;
106 bool cap_face_is_sysval;
107 bool cap_position_is_sysval;
108 bool cap_point_is_sysval;
109 bool cap_packed_uniforms;
110 bool cap_samplers_as_deref;
111 };
112
113 #define ttn_swizzle(b, src, x, y, z, w) \
114 nir_swizzle(b, src, SWIZ(x, y, z, w), 4)
115 #define ttn_channel(b, src, swiz) \
116 nir_channel(b, src, TGSI_SWIZZLE_##swiz)
117
118 static gl_varying_slot
119 tgsi_varying_semantic_to_slot(unsigned semantic, unsigned index)
120 {
121 switch (semantic) {
122 case TGSI_SEMANTIC_POSITION:
123 return VARYING_SLOT_POS;
124 case TGSI_SEMANTIC_COLOR:
125 if (index == 0)
126 return VARYING_SLOT_COL0;
127 else
128 return VARYING_SLOT_COL1;
129 case TGSI_SEMANTIC_BCOLOR:
130 if (index == 0)
131 return VARYING_SLOT_BFC0;
132 else
133 return VARYING_SLOT_BFC1;
134 case TGSI_SEMANTIC_FOG:
135 return VARYING_SLOT_FOGC;
136 case TGSI_SEMANTIC_PSIZE:
137 return VARYING_SLOT_PSIZ;
138 case TGSI_SEMANTIC_GENERIC:
139 return VARYING_SLOT_VAR0 + index;
140 case TGSI_SEMANTIC_FACE:
141 return VARYING_SLOT_FACE;
142 case TGSI_SEMANTIC_EDGEFLAG:
143 return VARYING_SLOT_EDGE;
144 case TGSI_SEMANTIC_PRIMID:
145 return VARYING_SLOT_PRIMITIVE_ID;
146 case TGSI_SEMANTIC_CLIPDIST:
147 if (index == 0)
148 return VARYING_SLOT_CLIP_DIST0;
149 else
150 return VARYING_SLOT_CLIP_DIST1;
151 case TGSI_SEMANTIC_CLIPVERTEX:
152 return VARYING_SLOT_CLIP_VERTEX;
153 case TGSI_SEMANTIC_TEXCOORD:
154 return VARYING_SLOT_TEX0 + index;
155 case TGSI_SEMANTIC_PCOORD:
156 return VARYING_SLOT_PNTC;
157 case TGSI_SEMANTIC_VIEWPORT_INDEX:
158 return VARYING_SLOT_VIEWPORT;
159 case TGSI_SEMANTIC_LAYER:
160 return VARYING_SLOT_LAYER;
161 case TGSI_SEMANTIC_TESSINNER:
162 return VARYING_SLOT_TESS_LEVEL_INNER;
163 case TGSI_SEMANTIC_TESSOUTER:
164 return VARYING_SLOT_TESS_LEVEL_OUTER;
165 default:
166 fprintf(stderr, "Bad TGSI semantic: %d/%d\n", semantic, index);
167 abort();
168 }
169 }
170
171 static enum gl_frag_depth_layout
172 ttn_get_depth_layout(unsigned tgsi_fs_depth_layout)
173 {
174 switch (tgsi_fs_depth_layout) {
175 case TGSI_FS_DEPTH_LAYOUT_NONE:
176 return FRAG_DEPTH_LAYOUT_NONE;
177 case TGSI_FS_DEPTH_LAYOUT_ANY:
178 return FRAG_DEPTH_LAYOUT_ANY;
179 case TGSI_FS_DEPTH_LAYOUT_GREATER:
180 return FRAG_DEPTH_LAYOUT_GREATER;
181 case TGSI_FS_DEPTH_LAYOUT_LESS:
182 return FRAG_DEPTH_LAYOUT_LESS;
183 case TGSI_FS_DEPTH_LAYOUT_UNCHANGED:
184 return FRAG_DEPTH_LAYOUT_UNCHANGED;
185 default:
186 unreachable("bad TGSI FS depth layout");
187 }
188 }
189
190 static nir_ssa_def *
191 ttn_src_for_dest(nir_builder *b, nir_alu_dest *dest)
192 {
193 nir_alu_src src;
194 memset(&src, 0, sizeof(src));
195
196 if (dest->dest.is_ssa)
197 src.src = nir_src_for_ssa(&dest->dest.ssa);
198 else {
199 assert(!dest->dest.reg.indirect);
200 src.src = nir_src_for_reg(dest->dest.reg.reg);
201 src.src.reg.base_offset = dest->dest.reg.base_offset;
202 }
203
204 for (int i = 0; i < 4; i++)
205 src.swizzle[i] = i;
206
207 return nir_mov_alu(b, src, 4);
208 }
209
210 static enum glsl_interp_mode
211 ttn_translate_interp_mode(unsigned tgsi_interp)
212 {
213 switch (tgsi_interp) {
214 case TGSI_INTERPOLATE_CONSTANT:
215 return INTERP_MODE_FLAT;
216 case TGSI_INTERPOLATE_LINEAR:
217 return INTERP_MODE_NOPERSPECTIVE;
218 case TGSI_INTERPOLATE_PERSPECTIVE:
219 return INTERP_MODE_SMOOTH;
220 case TGSI_INTERPOLATE_COLOR:
221 return INTERP_MODE_SMOOTH;
222 default:
223 unreachable("bad TGSI interpolation mode");
224 }
225 }
226
227 static void
228 ttn_emit_declaration(struct ttn_compile *c)
229 {
230 nir_builder *b = &c->build;
231 struct tgsi_full_declaration *decl = &c->token->FullDeclaration;
232 unsigned array_size = decl->Range.Last - decl->Range.First + 1;
233 unsigned file = decl->Declaration.File;
234 unsigned i;
235
236 if (file == TGSI_FILE_TEMPORARY) {
237 if (decl->Declaration.Array) {
238 /* for arrays, we create variables instead of registers: */
239 nir_variable *var = rzalloc(b->shader, nir_variable);
240
241 var->type = glsl_array_type(glsl_vec4_type(), array_size, 0);
242 var->data.mode = nir_var_shader_temp;
243 var->name = ralloc_asprintf(var, "arr_%d", decl->Array.ArrayID);
244
245 exec_list_push_tail(&b->shader->globals, &var->node);
246
247 for (i = 0; i < array_size; i++) {
248 /* point all the matching slots to the same var,
249 * with appropriate offset set, mostly just so
250 * we know what to do when tgsi does a non-indirect
251 * access
252 */
253 c->temp_regs[decl->Range.First + i].reg = NULL;
254 c->temp_regs[decl->Range.First + i].var = var;
255 c->temp_regs[decl->Range.First + i].offset = i;
256 }
257 } else {
258 for (i = 0; i < array_size; i++) {
259 nir_register *reg = nir_local_reg_create(b->impl);
260 reg->num_components = 4;
261 c->temp_regs[decl->Range.First + i].reg = reg;
262 c->temp_regs[decl->Range.First + i].var = NULL;
263 c->temp_regs[decl->Range.First + i].offset = 0;
264 }
265 }
266 } else if (file == TGSI_FILE_ADDRESS) {
267 c->addr_reg = nir_local_reg_create(b->impl);
268 c->addr_reg->num_components = 4;
269 } else if (file == TGSI_FILE_SYSTEM_VALUE) {
270 /* Nothing to record for system values. */
271 } else if (file == TGSI_FILE_BUFFER) {
272 /* Nothing to record for buffers. */
273 } else if (file == TGSI_FILE_IMAGE) {
274 /* Nothing to record for images. */
275 } else if (file == TGSI_FILE_SAMPLER) {
276 /* Nothing to record for samplers. */
277 } else if (file == TGSI_FILE_SAMPLER_VIEW) {
278 struct tgsi_declaration_sampler_view *sview = &decl->SamplerView;
279 nir_alu_type type;
280
281 assert((sview->ReturnTypeX == sview->ReturnTypeY) &&
282 (sview->ReturnTypeX == sview->ReturnTypeZ) &&
283 (sview->ReturnTypeX == sview->ReturnTypeW));
284
285 switch (sview->ReturnTypeX) {
286 case TGSI_RETURN_TYPE_SINT:
287 type = nir_type_int;
288 break;
289 case TGSI_RETURN_TYPE_UINT:
290 type = nir_type_uint;
291 break;
292 case TGSI_RETURN_TYPE_FLOAT:
293 default:
294 type = nir_type_float;
295 break;
296 }
297
298 for (i = 0; i < array_size; i++) {
299 c->samp_types[decl->Range.First + i] = type;
300 }
301 } else {
302 bool is_array = (array_size > 1);
303
304 assert(file == TGSI_FILE_INPUT ||
305 file == TGSI_FILE_OUTPUT ||
306 file == TGSI_FILE_CONSTANT);
307
308 /* nothing to do for UBOs: */
309 if ((file == TGSI_FILE_CONSTANT) && decl->Declaration.Dimension &&
310 decl->Dim.Index2D != 0) {
311 b->shader->info.num_ubos =
312 MAX2(b->shader->info.num_ubos, decl->Dim.Index2D);
313 return;
314 }
315
316 if ((file == TGSI_FILE_INPUT) || (file == TGSI_FILE_OUTPUT)) {
317 is_array = (is_array && decl->Declaration.Array &&
318 (decl->Array.ArrayID != 0));
319 }
320
321 for (i = 0; i < array_size; i++) {
322 unsigned idx = decl->Range.First + i;
323 nir_variable *var = rzalloc(b->shader, nir_variable);
324
325 var->data.driver_location = idx;
326
327 var->type = glsl_vec4_type();
328 if (is_array)
329 var->type = glsl_array_type(var->type, array_size, 0);
330
331 switch (file) {
332 case TGSI_FILE_INPUT:
333 var->data.read_only = true;
334 var->data.mode = nir_var_shader_in;
335 var->name = ralloc_asprintf(var, "in_%d", idx);
336
337 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
338 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
339 var->type = glsl_bool_type();
340 if (c->cap_face_is_sysval) {
341 var->data.mode = nir_var_system_value;
342 var->data.location = SYSTEM_VALUE_FRONT_FACE;
343 } else {
344 var->data.location = VARYING_SLOT_FACE;
345 }
346 c->input_var_face = var;
347 } else if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
348 if (c->cap_position_is_sysval) {
349 var->data.mode = nir_var_system_value;
350 var->data.location = SYSTEM_VALUE_FRAG_COORD;
351 } else {
352 var->data.location = VARYING_SLOT_POS;
353 }
354 c->input_var_position = var;
355 } else if (decl->Semantic.Name == TGSI_SEMANTIC_PCOORD) {
356 if (c->cap_point_is_sysval) {
357 var->data.mode = nir_var_system_value;
358 var->data.location = SYSTEM_VALUE_POINT_COORD;
359 } else {
360 var->data.location = VARYING_SLOT_PNTC;
361 }
362 c->input_var_point = var;
363 } else {
364 var->data.location =
365 tgsi_varying_semantic_to_slot(decl->Semantic.Name,
366 decl->Semantic.Index);
367 }
368 } else {
369 assert(!decl->Declaration.Semantic);
370 var->data.location = VERT_ATTRIB_GENERIC0 + idx;
371 }
372 var->data.index = 0;
373 var->data.interpolation =
374 ttn_translate_interp_mode(decl->Interp.Interpolate);
375
376 exec_list_push_tail(&b->shader->inputs, &var->node);
377 c->inputs[idx] = var;
378
379 for (int i = 0; i < array_size; i++)
380 b->shader->info.inputs_read |= 1 << (var->data.location + i);
381
382 break;
383 case TGSI_FILE_OUTPUT: {
384 int semantic_name = decl->Semantic.Name;
385 int semantic_index = decl->Semantic.Index;
386 /* Since we can't load from outputs in the IR, we make temporaries
387 * for the outputs and emit stores to the real outputs at the end of
388 * the shader.
389 */
390 nir_register *reg = nir_local_reg_create(b->impl);
391 reg->num_components = 4;
392 if (is_array)
393 reg->num_array_elems = array_size;
394
395 var->data.mode = nir_var_shader_out;
396 var->name = ralloc_asprintf(var, "out_%d", idx);
397 var->data.index = 0;
398 var->data.interpolation =
399 ttn_translate_interp_mode(decl->Interp.Interpolate);
400 var->data.patch = semantic_name == TGSI_SEMANTIC_TESSINNER ||
401 semantic_name == TGSI_SEMANTIC_TESSOUTER ||
402 semantic_name == TGSI_SEMANTIC_PATCH;
403
404 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
405 switch (semantic_name) {
406 case TGSI_SEMANTIC_COLOR: {
407 /* TODO tgsi loses some information, so we cannot
408 * actually differentiate here between DSB and MRT
409 * at this point. But so far no drivers using tgsi-
410 * to-nir support dual source blend:
411 */
412 bool dual_src_blend = false;
413 if (dual_src_blend && (semantic_index == 1)) {
414 var->data.location = FRAG_RESULT_DATA0;
415 var->data.index = 1;
416 } else {
417 if (c->scan->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
418 var->data.location = FRAG_RESULT_COLOR;
419 else
420 var->data.location = FRAG_RESULT_DATA0 + semantic_index;
421 }
422 break;
423 }
424 case TGSI_SEMANTIC_POSITION:
425 var->data.location = FRAG_RESULT_DEPTH;
426 var->type = glsl_float_type();
427 break;
428 case TGSI_SEMANTIC_STENCIL:
429 var->data.location = FRAG_RESULT_STENCIL;
430 var->type = glsl_int_type();
431 break;
432 default:
433 fprintf(stderr, "Bad TGSI semantic: %d/%d\n",
434 decl->Semantic.Name, decl->Semantic.Index);
435 abort();
436 }
437 } else {
438 var->data.location =
439 tgsi_varying_semantic_to_slot(semantic_name, semantic_index);
440 }
441
442 if (is_array) {
443 unsigned j;
444 for (j = 0; j < array_size; j++) {
445 c->output_regs[idx + j].offset = i + j;
446 c->output_regs[idx + j].reg = reg;
447 }
448 } else {
449 c->output_regs[idx].offset = i;
450 c->output_regs[idx].reg = reg;
451 }
452
453 exec_list_push_tail(&b->shader->outputs, &var->node);
454 c->outputs[idx] = var;
455
456 for (int i = 0; i < array_size; i++)
457 b->shader->info.outputs_written |= 1ull << (var->data.location + i);
458 }
459 break;
460 case TGSI_FILE_CONSTANT:
461 var->data.mode = nir_var_uniform;
462 var->name = ralloc_asprintf(var, "uniform_%d", idx);
463 var->data.location = idx;
464
465 exec_list_push_tail(&b->shader->uniforms, &var->node);
466 break;
467 default:
468 unreachable("bad declaration file");
469 return;
470 }
471
472 if (is_array)
473 break;
474 }
475
476 }
477 }
478
479 static void
480 ttn_emit_immediate(struct ttn_compile *c)
481 {
482 nir_builder *b = &c->build;
483 struct tgsi_full_immediate *tgsi_imm = &c->token->FullImmediate;
484 nir_load_const_instr *load_const;
485 int i;
486
487 load_const = nir_load_const_instr_create(b->shader, 4, 32);
488 c->imm_defs[c->next_imm] = &load_const->def;
489 c->next_imm++;
490
491 for (i = 0; i < load_const->def.num_components; i++)
492 load_const->value[i].u32 = tgsi_imm->u[i].Uint;
493
494 nir_builder_instr_insert(b, &load_const->instr);
495 }
496
497 static nir_ssa_def *
498 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect);
499
500 /* generate either a constant or indirect deref chain for accessing an
501 * array variable.
502 */
503 static nir_deref_instr *
504 ttn_array_deref(struct ttn_compile *c, nir_variable *var, unsigned offset,
505 struct tgsi_ind_register *indirect)
506 {
507 nir_deref_instr *deref = nir_build_deref_var(&c->build, var);
508 nir_ssa_def *index = nir_imm_int(&c->build, offset);
509 if (indirect)
510 index = nir_iadd(&c->build, index, ttn_src_for_indirect(c, indirect));
511 return nir_build_deref_array(&c->build, deref, index);
512 }
513
514 /* Special case: Turn the frontface varying into a load of the
515 * frontface variable, and create the vector as required by TGSI.
516 */
517 static nir_ssa_def *
518 ttn_emulate_tgsi_front_face(struct ttn_compile *c)
519 {
520 nir_ssa_def *tgsi_frontface[4];
521
522 if (c->cap_face_is_sysval) {
523 /* When it's a system value, it should be an integer vector: (F, 0, 0, 1)
524 * F is 0xffffffff if front-facing, 0 if not.
525 */
526
527 nir_ssa_def *frontface = nir_load_front_face(&c->build, 1);
528
529 tgsi_frontface[0] = nir_bcsel(&c->build,
530 frontface,
531 nir_imm_int(&c->build, 0xffffffff),
532 nir_imm_int(&c->build, 0));
533 tgsi_frontface[1] = nir_imm_int(&c->build, 0);
534 tgsi_frontface[2] = nir_imm_int(&c->build, 0);
535 tgsi_frontface[3] = nir_imm_int(&c->build, 1);
536 } else {
537 /* When it's an input, it should be a float vector: (F, 0.0, 0.0, 1.0)
538 * F is positive if front-facing, negative if not.
539 */
540
541 assert(c->input_var_face);
542 nir_ssa_def *frontface = nir_load_var(&c->build, c->input_var_face);
543
544 tgsi_frontface[0] = nir_bcsel(&c->build,
545 frontface,
546 nir_imm_float(&c->build, 1.0),
547 nir_imm_float(&c->build, -1.0));
548 tgsi_frontface[1] = nir_imm_float(&c->build, 0.0);
549 tgsi_frontface[2] = nir_imm_float(&c->build, 0.0);
550 tgsi_frontface[3] = nir_imm_float(&c->build, 1.0);
551 }
552
553 return nir_vec(&c->build, tgsi_frontface, 4);
554 }
555
556 static nir_src
557 ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
558 struct tgsi_ind_register *indirect,
559 struct tgsi_dimension *dim,
560 struct tgsi_ind_register *dimind,
561 bool src_is_float)
562 {
563 nir_builder *b = &c->build;
564 nir_src src;
565
566 memset(&src, 0, sizeof(src));
567
568 switch (file) {
569 case TGSI_FILE_TEMPORARY:
570 if (c->temp_regs[index].var) {
571 unsigned offset = c->temp_regs[index].offset;
572 nir_variable *var = c->temp_regs[index].var;
573 nir_ssa_def *load = nir_load_deref(&c->build,
574 ttn_array_deref(c, var, offset, indirect));
575
576 src = nir_src_for_ssa(load);
577 } else {
578 assert(!indirect);
579 src.reg.reg = c->temp_regs[index].reg;
580 }
581 assert(!dim);
582 break;
583
584 case TGSI_FILE_ADDRESS:
585 src.reg.reg = c->addr_reg;
586 assert(!dim);
587 break;
588
589 case TGSI_FILE_IMMEDIATE:
590 src = nir_src_for_ssa(c->imm_defs[index]);
591 assert(!indirect);
592 assert(!dim);
593 break;
594
595 case TGSI_FILE_SYSTEM_VALUE: {
596 nir_intrinsic_op op;
597 nir_ssa_def *load;
598
599 assert(!indirect);
600 assert(!dim);
601
602 switch (c->scan->system_value_semantic_name[index]) {
603 case TGSI_SEMANTIC_VERTEXID_NOBASE:
604 op = nir_intrinsic_load_vertex_id_zero_base;
605 load = nir_load_vertex_id_zero_base(b);
606 break;
607 case TGSI_SEMANTIC_VERTEXID:
608 op = nir_intrinsic_load_vertex_id;
609 load = nir_load_vertex_id(b);
610 break;
611 case TGSI_SEMANTIC_BASEVERTEX:
612 op = nir_intrinsic_load_base_vertex;
613 load = nir_load_base_vertex(b);
614 break;
615 case TGSI_SEMANTIC_INSTANCEID:
616 op = nir_intrinsic_load_instance_id;
617 load = nir_load_instance_id(b);
618 break;
619 case TGSI_SEMANTIC_FACE:
620 assert(c->cap_face_is_sysval);
621 op = nir_intrinsic_load_front_face;
622 load = ttn_emulate_tgsi_front_face(c);
623 break;
624 case TGSI_SEMANTIC_POSITION:
625 assert(c->cap_position_is_sysval);
626 op = nir_intrinsic_load_frag_coord;
627 load = nir_load_frag_coord(b);
628 break;
629 case TGSI_SEMANTIC_PCOORD:
630 assert(c->cap_point_is_sysval);
631 op = nir_intrinsic_load_point_coord;
632 load = nir_load_point_coord(b);
633 break;
634 case TGSI_SEMANTIC_THREAD_ID:
635 op = nir_intrinsic_load_local_invocation_id;
636 load = nir_load_local_invocation_id(b);
637 break;
638 case TGSI_SEMANTIC_BLOCK_ID:
639 op = nir_intrinsic_load_work_group_id;
640 load = nir_load_work_group_id(b);
641 break;
642 case TGSI_SEMANTIC_CS_USER_DATA_AMD:
643 op = nir_intrinsic_load_user_data_amd;
644 load = nir_load_user_data_amd(b);
645 break;
646 default:
647 unreachable("bad system value");
648 }
649
650 src = nir_src_for_ssa(load);
651 b->shader->info.system_values_read |=
652 (1 << nir_system_value_from_intrinsic(op));
653
654 break;
655 }
656
657 case TGSI_FILE_INPUT:
658 if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
659 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_FACE) {
660 assert(!c->cap_face_is_sysval && c->input_var_face);
661 return nir_src_for_ssa(ttn_emulate_tgsi_front_face(c));
662 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
663 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_POSITION) {
664 assert(!c->cap_position_is_sysval && c->input_var_position);
665 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_position));
666 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
667 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_PCOORD) {
668 assert(!c->cap_point_is_sysval && c->input_var_point);
669 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_point));
670 } else {
671 /* Indirection on input arrays isn't supported by TTN. */
672 assert(!dim);
673 nir_deref_instr *deref = nir_build_deref_var(&c->build,
674 c->inputs[index]);
675 return nir_src_for_ssa(nir_load_deref(&c->build, deref));
676 }
677 break;
678
679 case TGSI_FILE_CONSTANT: {
680 nir_intrinsic_instr *load;
681 nir_intrinsic_op op;
682 unsigned srcn = 0;
683
684 if (dim && (dim->Index > 0 || dim->Indirect)) {
685 op = nir_intrinsic_load_ubo;
686 } else {
687 op = nir_intrinsic_load_uniform;
688 }
689
690 load = nir_intrinsic_instr_create(b->shader, op);
691 if (op == nir_intrinsic_load_uniform) {
692 nir_intrinsic_set_type(load, src_is_float ? nir_type_float :
693 nir_type_int);
694 }
695
696 load->num_components = 4;
697 if (dim && (dim->Index > 0 || dim->Indirect)) {
698 if (dimind) {
699 load->src[srcn] =
700 ttn_src_for_file_and_index(c, dimind->File, dimind->Index,
701 NULL, NULL, NULL, false);
702 } else {
703 /* UBOs start at index 1 in TGSI: */
704 load->src[srcn] =
705 nir_src_for_ssa(nir_imm_int(b, dim->Index - 1));
706 }
707 srcn++;
708 }
709
710 nir_ssa_def *offset;
711 if (op == nir_intrinsic_load_ubo) {
712 /* UBO loads don't have a base offset. */
713 offset = nir_imm_int(b, index);
714 if (indirect) {
715 offset = nir_iadd(b, offset, ttn_src_for_indirect(c, indirect));
716 }
717 /* UBO offsets are in bytes, but TGSI gives them to us in vec4's */
718 offset = nir_ishl(b, offset, nir_imm_int(b, 4));
719 } else {
720 nir_intrinsic_set_base(load, index);
721 if (indirect) {
722 offset = ttn_src_for_indirect(c, indirect);
723 } else {
724 offset = nir_imm_int(b, 0);
725 }
726 }
727 load->src[srcn++] = nir_src_for_ssa(offset);
728
729 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
730 nir_builder_instr_insert(b, &load->instr);
731
732 src = nir_src_for_ssa(&load->dest.ssa);
733 break;
734 }
735
736 default:
737 unreachable("bad src file");
738 }
739
740
741 return src;
742 }
743
744 static nir_ssa_def *
745 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect)
746 {
747 nir_builder *b = &c->build;
748 nir_alu_src src;
749 memset(&src, 0, sizeof(src));
750 for (int i = 0; i < 4; i++)
751 src.swizzle[i] = indirect->Swizzle;
752 src.src = ttn_src_for_file_and_index(c,
753 indirect->File,
754 indirect->Index,
755 NULL, NULL, NULL,
756 false);
757 return nir_mov_alu(b, src, 1);
758 }
759
760 static nir_alu_dest
761 ttn_get_dest(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
762 {
763 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
764 nir_alu_dest dest;
765 unsigned index = tgsi_dst->Index;
766
767 memset(&dest, 0, sizeof(dest));
768
769 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
770 if (c->temp_regs[index].var) {
771 nir_register *reg;
772
773 /* this works, because TGSI will give us a base offset
774 * (in case of indirect index) that points back into
775 * the array. Access can be direct or indirect, we
776 * don't really care. Just create a one-shot dst reg
777 * that will get store_var'd back into the array var
778 * at the end of ttn_emit_instruction()
779 */
780 reg = nir_local_reg_create(c->build.impl);
781 reg->num_components = 4;
782 dest.dest.reg.reg = reg;
783 dest.dest.reg.base_offset = 0;
784 } else {
785 assert(!tgsi_dst->Indirect);
786 dest.dest.reg.reg = c->temp_regs[index].reg;
787 dest.dest.reg.base_offset = c->temp_regs[index].offset;
788 }
789 } else if (tgsi_dst->File == TGSI_FILE_OUTPUT) {
790 dest.dest.reg.reg = c->output_regs[index].reg;
791 dest.dest.reg.base_offset = c->output_regs[index].offset;
792 } else if (tgsi_dst->File == TGSI_FILE_ADDRESS) {
793 assert(index == 0);
794 dest.dest.reg.reg = c->addr_reg;
795 }
796
797 dest.write_mask = tgsi_dst->WriteMask;
798 dest.saturate = false;
799
800 if (tgsi_dst->Indirect && (tgsi_dst->File != TGSI_FILE_TEMPORARY)) {
801 nir_src *indirect = ralloc(c->build.shader, nir_src);
802 *indirect = nir_src_for_ssa(ttn_src_for_indirect(c, &tgsi_fdst->Indirect));
803 dest.dest.reg.indirect = indirect;
804 }
805
806 return dest;
807 }
808
809 static nir_variable *
810 ttn_get_var(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
811 {
812 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
813 unsigned index = tgsi_dst->Index;
814
815 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
816 /* we should not have an indirect when there is no var! */
817 if (!c->temp_regs[index].var)
818 assert(!tgsi_dst->Indirect);
819 return c->temp_regs[index].var;
820 }
821
822 return NULL;
823 }
824
825 static nir_ssa_def *
826 ttn_get_src(struct ttn_compile *c, struct tgsi_full_src_register *tgsi_fsrc,
827 int src_idx)
828 {
829 nir_builder *b = &c->build;
830 struct tgsi_src_register *tgsi_src = &tgsi_fsrc->Register;
831 enum tgsi_opcode opcode = c->token->FullInstruction.Instruction.Opcode;
832 unsigned tgsi_src_type = tgsi_opcode_infer_src_type(opcode, src_idx);
833 bool src_is_float = (tgsi_src_type == TGSI_TYPE_FLOAT ||
834 tgsi_src_type == TGSI_TYPE_DOUBLE ||
835 tgsi_src_type == TGSI_TYPE_UNTYPED);
836 nir_alu_src src;
837
838 memset(&src, 0, sizeof(src));
839
840 if (tgsi_src->File == TGSI_FILE_NULL) {
841 return nir_imm_float(b, 0.0);
842 } else if (tgsi_src->File == TGSI_FILE_SAMPLER ||
843 tgsi_src->File == TGSI_FILE_IMAGE ||
844 tgsi_src->File == TGSI_FILE_BUFFER) {
845 /* Only the index of the resource gets used in texturing, and it will
846 * handle looking that up on its own instead of using the nir_alu_src.
847 */
848 assert(!tgsi_src->Indirect);
849 return NULL;
850 } else {
851 struct tgsi_ind_register *ind = NULL;
852 struct tgsi_dimension *dim = NULL;
853 struct tgsi_ind_register *dimind = NULL;
854 if (tgsi_src->Indirect)
855 ind = &tgsi_fsrc->Indirect;
856 if (tgsi_src->Dimension) {
857 dim = &tgsi_fsrc->Dimension;
858 if (dim->Indirect)
859 dimind = &tgsi_fsrc->DimIndirect;
860 }
861 src.src = ttn_src_for_file_and_index(c,
862 tgsi_src->File,
863 tgsi_src->Index,
864 ind, dim, dimind,
865 src_is_float);
866 }
867
868 src.swizzle[0] = tgsi_src->SwizzleX;
869 src.swizzle[1] = tgsi_src->SwizzleY;
870 src.swizzle[2] = tgsi_src->SwizzleZ;
871 src.swizzle[3] = tgsi_src->SwizzleW;
872
873 nir_ssa_def *def = nir_mov_alu(b, src, 4);
874
875 if (tgsi_type_is_64bit(tgsi_src_type))
876 def = nir_bitcast_vector(b, def, 64);
877
878 if (tgsi_src->Absolute) {
879 if (src_is_float)
880 def = nir_fabs(b, def);
881 else
882 def = nir_iabs(b, def);
883 }
884
885 if (tgsi_src->Negate) {
886 if (src_is_float)
887 def = nir_fneg(b, def);
888 else
889 def = nir_ineg(b, def);
890 }
891
892 return def;
893 }
894
895 static void
896 ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
897 nir_ssa_def *def, unsigned write_mask)
898 {
899 if (!(dest.write_mask & write_mask))
900 return;
901
902 nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
903 mov->dest = dest;
904 mov->dest.write_mask &= write_mask;
905 mov->src[0].src = nir_src_for_ssa(def);
906 for (unsigned i = def->num_components; i < 4; i++)
907 mov->src[0].swizzle[i] = def->num_components - 1;
908 nir_builder_instr_insert(b, &mov->instr);
909 }
910
911 static void
912 ttn_move_dest(nir_builder *b, nir_alu_dest dest, nir_ssa_def *def)
913 {
914 ttn_move_dest_masked(b, dest, def, TGSI_WRITEMASK_XYZW);
915 }
916
917 static void
918 ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, unsigned dest_bitsize,
919 nir_ssa_def **src)
920 {
921 nir_ssa_def *def = nir_build_alu_src_arr(b, op, src);
922 if (def->bit_size == 1)
923 def = nir_ineg(b, nir_b2i(b, def, dest_bitsize));
924 assert(def->bit_size == dest_bitsize);
925 if (dest_bitsize == 64) {
926 if (def->num_components > 2) {
927 /* 32 -> 64 bit conversion ops are supposed to only convert the first
928 * two components, and we need to truncate here to avoid creating a
929 * vec8 after bitcasting the destination.
930 */
931 def = nir_channels(b, def, 0x3);
932 }
933 def = nir_bitcast_vector(b, def, 32);
934 }
935 ttn_move_dest(b, dest, def);
936 }
937
938 static void
939 ttn_arl(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
940 {
941 ttn_move_dest(b, dest, nir_f2i32(b, nir_ffloor(b, src[0])));
942 }
943
944 /* EXP - Approximate Exponential Base 2
945 * dst.x = 2^{\lfloor src.x\rfloor}
946 * dst.y = src.x - \lfloor src.x\rfloor
947 * dst.z = 2^{src.x}
948 * dst.w = 1.0
949 */
950 static void
951 ttn_exp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
952 {
953 nir_ssa_def *srcx = ttn_channel(b, src[0], X);
954
955 ttn_move_dest_masked(b, dest, nir_fexp2(b, nir_ffloor(b, srcx)),
956 TGSI_WRITEMASK_X);
957 ttn_move_dest_masked(b, dest, nir_fsub(b, srcx, nir_ffloor(b, srcx)),
958 TGSI_WRITEMASK_Y);
959 ttn_move_dest_masked(b, dest, nir_fexp2(b, srcx), TGSI_WRITEMASK_Z);
960 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
961 }
962
963 /* LOG - Approximate Logarithm Base 2
964 * dst.x = \lfloor\log_2{|src.x|}\rfloor
965 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
966 * dst.z = \log_2{|src.x|}
967 * dst.w = 1.0
968 */
969 static void
970 ttn_log(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
971 {
972 nir_ssa_def *abs_srcx = nir_fabs(b, ttn_channel(b, src[0], X));
973 nir_ssa_def *log2 = nir_flog2(b, abs_srcx);
974
975 ttn_move_dest_masked(b, dest, nir_ffloor(b, log2), TGSI_WRITEMASK_X);
976 ttn_move_dest_masked(b, dest,
977 nir_fdiv(b, abs_srcx, nir_fexp2(b, nir_ffloor(b, log2))),
978 TGSI_WRITEMASK_Y);
979 ttn_move_dest_masked(b, dest, nir_flog2(b, abs_srcx), TGSI_WRITEMASK_Z);
980 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
981 }
982
983 /* DST - Distance Vector
984 * dst.x = 1.0
985 * dst.y = src0.y \times src1.y
986 * dst.z = src0.z
987 * dst.w = src1.w
988 */
989 static void
990 ttn_dst(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
991 {
992 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_X);
993 ttn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), TGSI_WRITEMASK_Y);
994 ttn_move_dest_masked(b, dest, nir_mov(b, src[0]), TGSI_WRITEMASK_Z);
995 ttn_move_dest_masked(b, dest, nir_mov(b, src[1]), TGSI_WRITEMASK_W);
996 }
997
998 /* LIT - Light Coefficients
999 * dst.x = 1.0
1000 * dst.y = max(src.x, 0.0)
1001 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
1002 * dst.w = 1.0
1003 */
1004 static void
1005 ttn_lit(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1006 {
1007 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_XW);
1008
1009 ttn_move_dest_masked(b, dest, nir_fmax(b, ttn_channel(b, src[0], X),
1010 nir_imm_float(b, 0.0)), TGSI_WRITEMASK_Y);
1011
1012 if (dest.write_mask & TGSI_WRITEMASK_Z) {
1013 nir_ssa_def *src0_y = ttn_channel(b, src[0], Y);
1014 nir_ssa_def *wclamp = nir_fmax(b, nir_fmin(b, ttn_channel(b, src[0], W),
1015 nir_imm_float(b, 128.0)),
1016 nir_imm_float(b, -128.0));
1017 nir_ssa_def *pow = nir_fpow(b, nir_fmax(b, src0_y, nir_imm_float(b, 0.0)),
1018 wclamp);
1019
1020 ttn_move_dest_masked(b, dest,
1021 nir_bcsel(b,
1022 nir_flt(b,
1023 ttn_channel(b, src[0], X),
1024 nir_imm_float(b, 0.0)),
1025 nir_imm_float(b, 0.0),
1026 pow),
1027 TGSI_WRITEMASK_Z);
1028 }
1029 }
1030
1031 static void
1032 ttn_sle(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1033 {
1034 ttn_move_dest(b, dest, nir_sge(b, src[1], src[0]));
1035 }
1036
1037 static void
1038 ttn_sgt(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1039 {
1040 ttn_move_dest(b, dest, nir_slt(b, src[1], src[0]));
1041 }
1042
1043 static void
1044 ttn_dp2(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1045 {
1046 ttn_move_dest(b, dest, nir_fdot2(b, src[0], src[1]));
1047 }
1048
1049 static void
1050 ttn_dp3(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1051 {
1052 ttn_move_dest(b, dest, nir_fdot3(b, src[0], src[1]));
1053 }
1054
1055 static void
1056 ttn_dp4(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1057 {
1058 ttn_move_dest(b, dest, nir_fdot4(b, src[0], src[1]));
1059 }
1060
1061 static void
1062 ttn_umad(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1063 {
1064 ttn_move_dest(b, dest, nir_iadd(b, nir_imul(b, src[0], src[1]), src[2]));
1065 }
1066
1067 static void
1068 ttn_arr(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1069 {
1070 ttn_move_dest(b, dest, nir_f2i32(b, nir_fround_even(b, src[0])));
1071 }
1072
1073 static void
1074 ttn_cmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1075 {
1076 ttn_move_dest(b, dest, nir_bcsel(b,
1077 nir_flt(b, src[0], nir_imm_float(b, 0.0)),
1078 src[1], src[2]));
1079 }
1080
1081 static void
1082 ttn_ucmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1083 {
1084 ttn_move_dest(b, dest, nir_bcsel(b,
1085 nir_ine(b, src[0], nir_imm_int(b, 0)),
1086 src[1], src[2]));
1087 }
1088
1089 static void
1090 ttn_kill(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1091 {
1092 nir_intrinsic_instr *discard =
1093 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard);
1094 nir_builder_instr_insert(b, &discard->instr);
1095 b->shader->info.fs.uses_discard = true;
1096 }
1097
1098 static void
1099 ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1100 {
1101 nir_ssa_def *cmp = nir_bany(b, nir_flt(b, src[0], nir_imm_float(b, 0.0)));
1102 nir_intrinsic_instr *discard =
1103 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard_if);
1104 discard->src[0] = nir_src_for_ssa(cmp);
1105 nir_builder_instr_insert(b, &discard->instr);
1106 b->shader->info.fs.uses_discard = true;
1107 }
1108
1109 static void
1110 ttn_if(struct ttn_compile *c, nir_ssa_def *src, bool is_uint)
1111 {
1112 nir_builder *b = &c->build;
1113 nir_ssa_def *src_x = ttn_channel(b, src, X);
1114
1115 nir_if *if_stmt = nir_if_create(b->shader);
1116 if (is_uint) {
1117 /* equivalent to TGSI UIF, src is interpreted as integer */
1118 if_stmt->condition = nir_src_for_ssa(nir_ine(b, src_x, nir_imm_int(b, 0)));
1119 } else {
1120 /* equivalent to TGSI IF, src is interpreted as float */
1121 if_stmt->condition = nir_src_for_ssa(nir_fne(b, src_x, nir_imm_float(b, 0.0)));
1122 }
1123 nir_builder_cf_insert(b, &if_stmt->cf_node);
1124
1125 c->if_stack[c->if_stack_pos] = nir_after_cf_node(&if_stmt->cf_node);
1126 c->if_stack_pos++;
1127
1128 b->cursor = nir_after_cf_list(&if_stmt->then_list);
1129
1130 c->if_stack[c->if_stack_pos] = nir_after_cf_list(&if_stmt->else_list);
1131 c->if_stack_pos++;
1132 }
1133
1134 static void
1135 ttn_else(struct ttn_compile *c)
1136 {
1137 nir_builder *b = &c->build;
1138
1139 b->cursor = c->if_stack[c->if_stack_pos - 1];
1140 }
1141
1142 static void
1143 ttn_endif(struct ttn_compile *c)
1144 {
1145 nir_builder *b = &c->build;
1146
1147 c->if_stack_pos -= 2;
1148 b->cursor = c->if_stack[c->if_stack_pos];
1149 }
1150
1151 static void
1152 ttn_bgnloop(struct ttn_compile *c)
1153 {
1154 nir_builder *b = &c->build;
1155
1156 nir_loop *loop = nir_loop_create(b->shader);
1157 nir_builder_cf_insert(b, &loop->cf_node);
1158
1159 c->loop_stack[c->loop_stack_pos] = nir_after_cf_node(&loop->cf_node);
1160 c->loop_stack_pos++;
1161
1162 b->cursor = nir_after_cf_list(&loop->body);
1163 }
1164
1165 static void
1166 ttn_cont(nir_builder *b)
1167 {
1168 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_continue);
1169 nir_builder_instr_insert(b, &instr->instr);
1170 }
1171
1172 static void
1173 ttn_brk(nir_builder *b)
1174 {
1175 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
1176 nir_builder_instr_insert(b, &instr->instr);
1177 }
1178
1179 static void
1180 ttn_endloop(struct ttn_compile *c)
1181 {
1182 nir_builder *b = &c->build;
1183
1184 c->loop_stack_pos--;
1185 b->cursor = c->loop_stack[c->loop_stack_pos];
1186 }
1187
1188 static void
1189 get_texture_info(unsigned texture,
1190 enum glsl_sampler_dim *dim,
1191 bool *is_shadow,
1192 bool *is_array)
1193 {
1194 assert(is_array);
1195 *is_array = false;
1196
1197 if (is_shadow)
1198 *is_shadow = false;
1199
1200 switch (texture) {
1201 case TGSI_TEXTURE_BUFFER:
1202 *dim = GLSL_SAMPLER_DIM_BUF;
1203 break;
1204 case TGSI_TEXTURE_1D:
1205 *dim = GLSL_SAMPLER_DIM_1D;
1206 break;
1207 case TGSI_TEXTURE_1D_ARRAY:
1208 *dim = GLSL_SAMPLER_DIM_1D;
1209 *is_array = true;
1210 break;
1211 case TGSI_TEXTURE_SHADOW1D:
1212 *dim = GLSL_SAMPLER_DIM_1D;
1213 *is_shadow = true;
1214 break;
1215 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1216 *dim = GLSL_SAMPLER_DIM_1D;
1217 *is_shadow = true;
1218 *is_array = true;
1219 break;
1220 case TGSI_TEXTURE_2D:
1221 *dim = GLSL_SAMPLER_DIM_2D;
1222 break;
1223 case TGSI_TEXTURE_2D_ARRAY:
1224 *dim = GLSL_SAMPLER_DIM_2D;
1225 *is_array = true;
1226 break;
1227 case TGSI_TEXTURE_2D_MSAA:
1228 *dim = GLSL_SAMPLER_DIM_MS;
1229 break;
1230 case TGSI_TEXTURE_2D_ARRAY_MSAA:
1231 *dim = GLSL_SAMPLER_DIM_MS;
1232 *is_array = true;
1233 break;
1234 case TGSI_TEXTURE_SHADOW2D:
1235 *dim = GLSL_SAMPLER_DIM_2D;
1236 *is_shadow = true;
1237 break;
1238 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1239 *dim = GLSL_SAMPLER_DIM_2D;
1240 *is_shadow = true;
1241 *is_array = true;
1242 break;
1243 case TGSI_TEXTURE_3D:
1244 *dim = GLSL_SAMPLER_DIM_3D;
1245 break;
1246 case TGSI_TEXTURE_CUBE:
1247 *dim = GLSL_SAMPLER_DIM_CUBE;
1248 break;
1249 case TGSI_TEXTURE_CUBE_ARRAY:
1250 *dim = GLSL_SAMPLER_DIM_CUBE;
1251 *is_array = true;
1252 break;
1253 case TGSI_TEXTURE_SHADOWCUBE:
1254 *dim = GLSL_SAMPLER_DIM_CUBE;
1255 *is_shadow = true;
1256 break;
1257 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1258 *dim = GLSL_SAMPLER_DIM_CUBE;
1259 *is_shadow = true;
1260 *is_array = true;
1261 break;
1262 case TGSI_TEXTURE_RECT:
1263 *dim = GLSL_SAMPLER_DIM_RECT;
1264 break;
1265 case TGSI_TEXTURE_SHADOWRECT:
1266 *dim = GLSL_SAMPLER_DIM_RECT;
1267 *is_shadow = true;
1268 break;
1269 default:
1270 fprintf(stderr, "Unknown TGSI texture target %d\n", texture);
1271 abort();
1272 }
1273 }
1274
1275 static enum glsl_base_type
1276 base_type_for_alu_type(nir_alu_type type)
1277 {
1278 type = nir_alu_type_get_base_type(type);
1279
1280 switch (type) {
1281 case nir_type_float:
1282 return GLSL_TYPE_FLOAT;
1283 case nir_type_int:
1284 return GLSL_TYPE_INT;
1285 case nir_type_uint:
1286 return GLSL_TYPE_UINT;
1287 default:
1288 unreachable("invalid type");
1289 }
1290 }
1291
1292 static nir_variable *
1293 get_sampler_var(struct ttn_compile *c, int binding,
1294 enum glsl_sampler_dim dim,
1295 bool is_shadow,
1296 bool is_array,
1297 enum glsl_base_type base_type)
1298 {
1299 nir_variable *var = c->samplers[binding];
1300 if (!var) {
1301 const struct glsl_type *type =
1302 glsl_sampler_type(dim, is_shadow, is_array, base_type);
1303 var = nir_variable_create(c->build.shader, nir_var_uniform, type,
1304 "sampler");
1305 var->data.binding = binding;
1306 var->data.explicit_binding = true;
1307 c->samplers[binding] = var;
1308 }
1309
1310 return var;
1311 }
1312
1313 static nir_variable *
1314 get_image_var(struct ttn_compile *c, int binding,
1315 enum glsl_sampler_dim dim,
1316 bool is_array,
1317 enum glsl_base_type base_type,
1318 enum gl_access_qualifier access,
1319 GLenum format)
1320 {
1321 nir_variable *var = c->images[binding];
1322
1323 if (!var) {
1324 const struct glsl_type *type = glsl_image_type(dim, is_array, base_type);
1325
1326 var = nir_variable_create(c->build.shader, nir_var_uniform, type, "image");
1327 var->data.binding = binding;
1328 var->data.explicit_binding = true;
1329 var->data.image.access = access;
1330 var->data.image.format = format;
1331 c->images[binding] = var;
1332 }
1333
1334 return var;
1335 }
1336
1337 static void
1338 add_ssbo_var(struct ttn_compile *c, int binding)
1339 {
1340 nir_variable *var = c->ssbo[binding];
1341
1342 if (!var) {
1343 /* A length of 0 is used to denote unsized arrays */
1344 const struct glsl_type *type = glsl_array_type(glsl_uint_type(), 0, 0);
1345
1346 struct glsl_struct_field field = {
1347 .type = type,
1348 .name = "data",
1349 .location = -1,
1350 };
1351
1352 var = nir_variable_create(c->build.shader, nir_var_mem_ssbo, type, "ssbo");
1353 var->data.binding = binding;
1354 var->interface_type =
1355 glsl_interface_type(&field, 1, GLSL_INTERFACE_PACKING_STD430,
1356 false, "data");
1357 c->ssbo[binding] = var;
1358 }
1359 }
1360
1361 static void
1362 ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1363 {
1364 nir_builder *b = &c->build;
1365 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1366 nir_tex_instr *instr;
1367 nir_texop op;
1368 unsigned num_srcs, samp = 1, sview, i;
1369
1370 switch (tgsi_inst->Instruction.Opcode) {
1371 case TGSI_OPCODE_TEX:
1372 op = nir_texop_tex;
1373 num_srcs = 1;
1374 break;
1375 case TGSI_OPCODE_TEX2:
1376 op = nir_texop_tex;
1377 num_srcs = 1;
1378 samp = 2;
1379 break;
1380 case TGSI_OPCODE_TXP:
1381 op = nir_texop_tex;
1382 num_srcs = 2;
1383 break;
1384 case TGSI_OPCODE_TXB:
1385 op = nir_texop_txb;
1386 num_srcs = 2;
1387 break;
1388 case TGSI_OPCODE_TXB2:
1389 op = nir_texop_txb;
1390 num_srcs = 2;
1391 samp = 2;
1392 break;
1393 case TGSI_OPCODE_TXL:
1394 case TGSI_OPCODE_TEX_LZ:
1395 op = nir_texop_txl;
1396 num_srcs = 2;
1397 break;
1398 case TGSI_OPCODE_TXL2:
1399 op = nir_texop_txl;
1400 num_srcs = 2;
1401 samp = 2;
1402 break;
1403 case TGSI_OPCODE_TXF:
1404 case TGSI_OPCODE_TXF_LZ:
1405 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
1406 tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1407 op = nir_texop_txf_ms;
1408 } else {
1409 op = nir_texop_txf;
1410 }
1411 num_srcs = 2;
1412 break;
1413 case TGSI_OPCODE_TXD:
1414 op = nir_texop_txd;
1415 num_srcs = 3;
1416 samp = 3;
1417 break;
1418 case TGSI_OPCODE_LODQ:
1419 op = nir_texop_lod;
1420 num_srcs = 1;
1421 break;
1422
1423 default:
1424 fprintf(stderr, "unknown TGSI tex op %d\n", tgsi_inst->Instruction.Opcode);
1425 abort();
1426 }
1427
1428 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
1429 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1430 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
1431 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1432 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
1433 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
1434 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1435 num_srcs++;
1436 }
1437
1438 /* Deref sources */
1439 num_srcs += 2;
1440
1441 num_srcs += tgsi_inst->Texture.NumOffsets;
1442
1443 instr = nir_tex_instr_create(b->shader, num_srcs);
1444 instr->op = op;
1445
1446 get_texture_info(tgsi_inst->Texture.Texture,
1447 &instr->sampler_dim, &instr->is_shadow, &instr->is_array);
1448
1449 switch (instr->sampler_dim) {
1450 case GLSL_SAMPLER_DIM_1D:
1451 case GLSL_SAMPLER_DIM_BUF:
1452 instr->coord_components = 1;
1453 break;
1454 case GLSL_SAMPLER_DIM_2D:
1455 case GLSL_SAMPLER_DIM_RECT:
1456 case GLSL_SAMPLER_DIM_EXTERNAL:
1457 case GLSL_SAMPLER_DIM_MS:
1458 instr->coord_components = 2;
1459 break;
1460 case GLSL_SAMPLER_DIM_3D:
1461 case GLSL_SAMPLER_DIM_CUBE:
1462 instr->coord_components = 3;
1463 break;
1464 case GLSL_SAMPLER_DIM_SUBPASS:
1465 case GLSL_SAMPLER_DIM_SUBPASS_MS:
1466 unreachable("invalid sampler_dim");
1467 }
1468
1469 if (instr->is_array)
1470 instr->coord_components++;
1471
1472 assert(tgsi_inst->Src[samp].Register.File == TGSI_FILE_SAMPLER);
1473
1474 /* TODO if we supported any opc's which take an explicit SVIEW
1475 * src, we would use that here instead. But for the "legacy"
1476 * texture opc's the SVIEW index is same as SAMP index:
1477 */
1478 sview = tgsi_inst->Src[samp].Register.Index;
1479
1480 if (op == nir_texop_lod) {
1481 instr->dest_type = nir_type_float;
1482 } else if (sview < c->num_samp_types) {
1483 instr->dest_type = c->samp_types[sview];
1484 } else {
1485 instr->dest_type = nir_type_float;
1486 }
1487
1488 nir_variable *var =
1489 get_sampler_var(c, sview, instr->sampler_dim,
1490 instr->is_shadow,
1491 instr->is_array,
1492 base_type_for_alu_type(instr->dest_type));
1493
1494 nir_deref_instr *deref = nir_build_deref_var(b, var);
1495
1496 unsigned src_number = 0;
1497
1498 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1499 instr->src[src_number].src_type = nir_tex_src_texture_deref;
1500 src_number++;
1501 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1502 instr->src[src_number].src_type = nir_tex_src_sampler_deref;
1503 src_number++;
1504
1505 instr->src[src_number].src =
1506 nir_src_for_ssa(nir_swizzle(b, src[0], SWIZ(X, Y, Z, W),
1507 instr->coord_components));
1508 instr->src[src_number].src_type = nir_tex_src_coord;
1509 src_number++;
1510
1511 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1512 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1513 instr->src[src_number].src_type = nir_tex_src_projector;
1514 src_number++;
1515 }
1516
1517 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
1518 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1519 instr->src[src_number].src_type = nir_tex_src_bias;
1520 src_number++;
1521 }
1522
1523 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB2) {
1524 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1525 instr->src[src_number].src_type = nir_tex_src_bias;
1526 src_number++;
1527 }
1528
1529 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
1530 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ) {
1531 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ)
1532 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1533 else
1534 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1535 instr->src[src_number].src_type = nir_tex_src_lod;
1536 src_number++;
1537 }
1538
1539 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
1540 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1541 instr->src[src_number].src_type = nir_tex_src_lod;
1542 src_number++;
1543 }
1544
1545 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF ||
1546 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ) {
1547 if (op == nir_texop_txf_ms) {
1548 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1549 instr->src[src_number].src_type = nir_tex_src_ms_index;
1550 } else {
1551 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ)
1552 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1553 else
1554 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1555 instr->src[src_number].src_type = nir_tex_src_lod;
1556 }
1557 src_number++;
1558 }
1559
1560 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
1561 instr->src[src_number].src_type = nir_tex_src_ddx;
1562 instr->src[src_number].src =
1563 nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1564 nir_tex_instr_src_size(instr, src_number)));
1565 src_number++;
1566 instr->src[src_number].src_type = nir_tex_src_ddy;
1567 instr->src[src_number].src =
1568 nir_src_for_ssa(nir_swizzle(b, src[2], SWIZ(X, Y, Z, W),
1569 nir_tex_instr_src_size(instr, src_number)));
1570 src_number++;
1571 }
1572
1573 if (instr->is_shadow) {
1574 if (instr->coord_components == 4)
1575 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1576 else if (instr->coord_components == 3)
1577 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1578 else
1579 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], Z));
1580
1581 instr->src[src_number].src_type = nir_tex_src_comparator;
1582 src_number++;
1583 }
1584
1585 for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) {
1586 struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i];
1587 /* since TexOffset ins't using tgsi_full_src_register we get to
1588 * do some extra gymnastics:
1589 */
1590 nir_alu_src src;
1591
1592 memset(&src, 0, sizeof(src));
1593
1594 src.src = ttn_src_for_file_and_index(c,
1595 tex_offset->File,
1596 tex_offset->Index,
1597 NULL, NULL, NULL,
1598 true);
1599
1600 src.swizzle[0] = tex_offset->SwizzleX;
1601 src.swizzle[1] = tex_offset->SwizzleY;
1602 src.swizzle[2] = tex_offset->SwizzleZ;
1603 src.swizzle[3] = TGSI_SWIZZLE_W;
1604
1605 instr->src[src_number].src_type = nir_tex_src_offset;
1606 instr->src[src_number].src = nir_src_for_ssa(
1607 nir_mov_alu(b, src, nir_tex_instr_src_size(instr, src_number)));
1608 src_number++;
1609 }
1610
1611 assert(src_number == num_srcs);
1612 assert(src_number == instr->num_srcs);
1613
1614 nir_ssa_dest_init(&instr->instr, &instr->dest,
1615 nir_tex_instr_dest_size(instr),
1616 32, NULL);
1617 nir_builder_instr_insert(b, &instr->instr);
1618
1619 /* Resolve the writemask on the texture op. */
1620 ttn_move_dest(b, dest, &instr->dest.ssa);
1621 }
1622
1623 /* TGSI_OPCODE_TXQ is actually two distinct operations:
1624 *
1625 * dst.x = texture\_width(unit, lod)
1626 * dst.y = texture\_height(unit, lod)
1627 * dst.z = texture\_depth(unit, lod)
1628 * dst.w = texture\_levels(unit)
1629 *
1630 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels
1631 */
1632 static void
1633 ttn_txq(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1634 {
1635 nir_builder *b = &c->build;
1636 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1637 nir_tex_instr *txs, *qlv;
1638
1639 txs = nir_tex_instr_create(b->shader, 2);
1640 txs->op = nir_texop_txs;
1641 get_texture_info(tgsi_inst->Texture.Texture,
1642 &txs->sampler_dim, &txs->is_shadow, &txs->is_array);
1643
1644 qlv = nir_tex_instr_create(b->shader, 1);
1645 qlv->op = nir_texop_query_levels;
1646 get_texture_info(tgsi_inst->Texture.Texture,
1647 &qlv->sampler_dim, &qlv->is_shadow, &qlv->is_array);
1648
1649 assert(tgsi_inst->Src[1].Register.File == TGSI_FILE_SAMPLER);
1650 int tex_index = tgsi_inst->Src[1].Register.Index;
1651
1652 nir_variable *var =
1653 get_sampler_var(c, tex_index, txs->sampler_dim,
1654 txs->is_shadow,
1655 txs->is_array,
1656 base_type_for_alu_type(txs->dest_type));
1657
1658 nir_deref_instr *deref = nir_build_deref_var(b, var);
1659
1660 txs->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1661 txs->src[0].src_type = nir_tex_src_texture_deref;
1662
1663 qlv->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1664 qlv->src[0].src_type = nir_tex_src_texture_deref;
1665
1666 /* lod: */
1667 txs->src[1].src = nir_src_for_ssa(ttn_channel(b, src[0], X));
1668 txs->src[1].src_type = nir_tex_src_lod;
1669
1670 nir_ssa_dest_init(&txs->instr, &txs->dest,
1671 nir_tex_instr_dest_size(txs), 32, NULL);
1672 nir_builder_instr_insert(b, &txs->instr);
1673
1674 nir_ssa_dest_init(&qlv->instr, &qlv->dest, 1, 32, NULL);
1675 nir_builder_instr_insert(b, &qlv->instr);
1676
1677 ttn_move_dest_masked(b, dest, &txs->dest.ssa, TGSI_WRITEMASK_XYZ);
1678 ttn_move_dest_masked(b, dest, &qlv->dest.ssa, TGSI_WRITEMASK_W);
1679 }
1680
1681 static enum glsl_base_type
1682 get_image_base_type(struct tgsi_full_instruction *tgsi_inst)
1683 {
1684 const struct util_format_description *desc =
1685 util_format_description(tgsi_inst->Memory.Format);
1686
1687 if (desc->channel[0].pure_integer) {
1688 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED)
1689 return GLSL_TYPE_INT;
1690 else
1691 return GLSL_TYPE_UINT;
1692 }
1693 return GLSL_TYPE_FLOAT;
1694 }
1695
1696 static enum gl_access_qualifier
1697 get_mem_qualifier(struct tgsi_full_instruction *tgsi_inst)
1698 {
1699 enum gl_access_qualifier access = 0;
1700
1701 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_COHERENT)
1702 access |= ACCESS_COHERENT;
1703 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT)
1704 access |= ACCESS_RESTRICT;
1705 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
1706 access |= ACCESS_VOLATILE;
1707 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
1708 access |= ACCESS_STREAM_CACHE_POLICY;
1709
1710 return access;
1711 }
1712
1713 static GLenum
1714 get_image_format(struct tgsi_full_instruction *tgsi_inst)
1715 {
1716 switch (tgsi_inst->Memory.Format) {
1717 case PIPE_FORMAT_R8_UNORM:
1718 return GL_R8;
1719 case PIPE_FORMAT_R8G8_UNORM:
1720 return GL_RG8;
1721 case PIPE_FORMAT_R8G8B8A8_UNORM:
1722 return GL_RGBA8;
1723 case PIPE_FORMAT_R16_UNORM:
1724 return GL_R16;
1725 case PIPE_FORMAT_R16G16_UNORM:
1726 return GL_RG16;
1727 case PIPE_FORMAT_R16G16B16A16_UNORM:
1728 return GL_RGBA16;
1729
1730 case PIPE_FORMAT_R8_SNORM:
1731 return GL_R8_SNORM;
1732 case PIPE_FORMAT_R8G8_SNORM:
1733 return GL_RG8_SNORM;
1734 case PIPE_FORMAT_R8G8B8A8_SNORM:
1735 return GL_RGBA8_SNORM;
1736 case PIPE_FORMAT_R16_SNORM:
1737 return GL_R16_SNORM;
1738 case PIPE_FORMAT_R16G16_SNORM:
1739 return GL_RG16_SNORM;
1740 case PIPE_FORMAT_R16G16B16A16_SNORM:
1741 return GL_RGBA16_SNORM;
1742
1743 case PIPE_FORMAT_R8_UINT:
1744 return GL_R8UI;
1745 case PIPE_FORMAT_R8G8_UINT:
1746 return GL_RG8UI;
1747 case PIPE_FORMAT_R8G8B8A8_UINT:
1748 return GL_RGBA8UI;
1749 case PIPE_FORMAT_R16_UINT:
1750 return GL_R16UI;
1751 case PIPE_FORMAT_R16G16_UINT:
1752 return GL_RG16UI;
1753 case PIPE_FORMAT_R16G16B16A16_UINT:
1754 return GL_RGBA16UI;
1755 case PIPE_FORMAT_R32_UINT:
1756 return GL_R32UI;
1757 case PIPE_FORMAT_R32G32_UINT:
1758 return GL_RG32UI;
1759 case PIPE_FORMAT_R32G32B32A32_UINT:
1760 return GL_RGBA32UI;
1761
1762 case PIPE_FORMAT_R8_SINT:
1763 return GL_R8I;
1764 case PIPE_FORMAT_R8G8_SINT:
1765 return GL_RG8I;
1766 case PIPE_FORMAT_R8G8B8A8_SINT:
1767 return GL_RGBA8I;
1768 case PIPE_FORMAT_R16_SINT:
1769 return GL_R16I;
1770 case PIPE_FORMAT_R16G16_SINT:
1771 return GL_RG16I;
1772 case PIPE_FORMAT_R16G16B16A16_SINT:
1773 return GL_RGBA16I;
1774 case PIPE_FORMAT_R32_SINT:
1775 return GL_R32I;
1776 case PIPE_FORMAT_R32G32_SINT:
1777 return GL_RG32I;
1778 case PIPE_FORMAT_R32G32B32A32_SINT:
1779 return GL_RGBA32I;
1780
1781 case PIPE_FORMAT_R16_FLOAT:
1782 return GL_R16F;
1783 case PIPE_FORMAT_R16G16_FLOAT:
1784 return GL_RG16F;
1785 case PIPE_FORMAT_R16G16B16A16_FLOAT:
1786 return GL_RGBA16F;
1787 case PIPE_FORMAT_R32_FLOAT:
1788 return GL_R32F;
1789 case PIPE_FORMAT_R32G32_FLOAT:
1790 return GL_RG32F;
1791 case PIPE_FORMAT_R32G32B32A32_FLOAT:
1792 return GL_RGBA32F;
1793
1794 case PIPE_FORMAT_R11G11B10_FLOAT:
1795 return GL_R11F_G11F_B10F;
1796 case PIPE_FORMAT_R10G10B10A2_UINT:
1797 return GL_RGB10_A2UI;
1798 case PIPE_FORMAT_R10G10B10A2_UNORM:
1799 return GL_RGB10_A2;
1800
1801 default:
1802 unreachable("unhandled image format");
1803 }
1804 }
1805
1806 static void
1807 ttn_mem(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1808 {
1809 nir_builder *b = &c->build;
1810 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1811 nir_intrinsic_instr *instr = NULL;
1812 unsigned resource_index, addr_src_index, file;
1813
1814 switch (tgsi_inst->Instruction.Opcode) {
1815 case TGSI_OPCODE_LOAD:
1816 assert(!tgsi_inst->Src[0].Register.Indirect);
1817 resource_index = tgsi_inst->Src[0].Register.Index;
1818 file = tgsi_inst->Src[0].Register.File;
1819 addr_src_index = 1;
1820 break;
1821 case TGSI_OPCODE_STORE:
1822 assert(!tgsi_inst->Dst[0].Register.Indirect);
1823 resource_index = tgsi_inst->Dst[0].Register.Index;
1824 file = tgsi_inst->Dst[0].Register.File;
1825 addr_src_index = 0;
1826 break;
1827 default:
1828 unreachable("unexpected memory opcode");
1829 }
1830
1831 if (file == TGSI_FILE_BUFFER) {
1832 nir_intrinsic_op op;
1833
1834 switch (tgsi_inst->Instruction.Opcode) {
1835 case TGSI_OPCODE_LOAD:
1836 op = nir_intrinsic_load_ssbo;
1837 break;
1838 case TGSI_OPCODE_STORE:
1839 op = nir_intrinsic_store_ssbo;
1840 break;
1841 }
1842
1843 add_ssbo_var(c, resource_index);
1844
1845 instr = nir_intrinsic_instr_create(b->shader, op);
1846 instr->num_components = util_last_bit(tgsi_inst->Dst[0].Register.WriteMask);
1847 nir_intrinsic_set_access(instr, get_mem_qualifier(tgsi_inst));
1848 nir_intrinsic_set_align(instr, 4, 0);
1849
1850 unsigned i = 0;
1851 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1852 instr->src[i++] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1853 instr->num_components));
1854 instr->src[i++] = nir_src_for_ssa(nir_imm_int(b, resource_index));
1855 instr->src[i++] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], X));
1856
1857 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1858 nir_intrinsic_set_write_mask(instr, tgsi_inst->Dst[0].Register.WriteMask);
1859
1860 } else if (file == TGSI_FILE_IMAGE) {
1861 nir_intrinsic_op op;
1862
1863 switch (tgsi_inst->Instruction.Opcode) {
1864 case TGSI_OPCODE_LOAD:
1865 op = nir_intrinsic_image_deref_load;
1866 break;
1867 case TGSI_OPCODE_STORE:
1868 op = nir_intrinsic_image_deref_store;
1869 break;
1870 }
1871
1872 instr = nir_intrinsic_instr_create(b->shader, op);
1873
1874 /* Set the image variable dereference. */
1875 enum glsl_sampler_dim dim;
1876 bool is_array;
1877 get_texture_info(tgsi_inst->Memory.Texture, &dim, NULL, &is_array);
1878
1879 enum glsl_base_type base_type = get_image_base_type(tgsi_inst);
1880 enum gl_access_qualifier access = get_mem_qualifier(tgsi_inst);
1881 GLenum format = get_image_format(tgsi_inst);
1882
1883 nir_variable *image =
1884 get_image_var(c, resource_index,
1885 dim, is_array, base_type, access, format);
1886 nir_deref_instr *image_deref = nir_build_deref_var(b, image);
1887 const struct glsl_type *type = image_deref->type;
1888 unsigned coord_components = glsl_get_sampler_coordinate_components(type);
1889
1890 nir_intrinsic_set_access(instr, image_deref->var->data.image.access);
1891
1892 instr->src[0] = nir_src_for_ssa(&image_deref->dest.ssa);
1893 instr->src[1] = nir_src_for_ssa(nir_swizzle(b, src[addr_src_index],
1894 SWIZ(X, Y, Z, W),
1895 coord_components));
1896
1897 /* Set the sample argument, which is undefined for single-sample images. */
1898 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_MS) {
1899 instr->src[2] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], W));
1900 } else {
1901 instr->src[2] = nir_src_for_ssa(nir_ssa_undef(b, 1, 32));
1902 }
1903
1904 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
1905 instr->src[3] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W), 4));
1906 }
1907
1908 instr->num_components = 4;
1909 } else {
1910 unreachable("unexpected file");
1911 }
1912
1913
1914 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_LOAD) {
1915 nir_ssa_dest_init(&instr->instr, &instr->dest,
1916 util_last_bit(tgsi_inst->Dst[0].Register.WriteMask),
1917 32, NULL);
1918 nir_builder_instr_insert(b, &instr->instr);
1919 ttn_move_dest(b, dest, &instr->dest.ssa);
1920 } else {
1921 nir_builder_instr_insert(b, &instr->instr);
1922 }
1923 }
1924
1925 static const nir_op op_trans[TGSI_OPCODE_LAST] = {
1926 [TGSI_OPCODE_ARL] = 0,
1927 [TGSI_OPCODE_MOV] = nir_op_mov,
1928 [TGSI_OPCODE_LIT] = 0,
1929 [TGSI_OPCODE_RCP] = nir_op_frcp,
1930 [TGSI_OPCODE_RSQ] = nir_op_frsq,
1931 [TGSI_OPCODE_EXP] = 0,
1932 [TGSI_OPCODE_LOG] = 0,
1933 [TGSI_OPCODE_MUL] = nir_op_fmul,
1934 [TGSI_OPCODE_ADD] = nir_op_fadd,
1935 [TGSI_OPCODE_DP3] = 0,
1936 [TGSI_OPCODE_DP4] = 0,
1937 [TGSI_OPCODE_DST] = 0,
1938 [TGSI_OPCODE_MIN] = nir_op_fmin,
1939 [TGSI_OPCODE_MAX] = nir_op_fmax,
1940 [TGSI_OPCODE_SLT] = nir_op_slt,
1941 [TGSI_OPCODE_SGE] = nir_op_sge,
1942 [TGSI_OPCODE_MAD] = nir_op_ffma,
1943 [TGSI_OPCODE_TEX_LZ] = 0,
1944 [TGSI_OPCODE_LRP] = 0,
1945 [TGSI_OPCODE_SQRT] = nir_op_fsqrt,
1946 [TGSI_OPCODE_FRC] = nir_op_ffract,
1947 [TGSI_OPCODE_TXF_LZ] = 0,
1948 [TGSI_OPCODE_FLR] = nir_op_ffloor,
1949 [TGSI_OPCODE_ROUND] = nir_op_fround_even,
1950 [TGSI_OPCODE_EX2] = nir_op_fexp2,
1951 [TGSI_OPCODE_LG2] = nir_op_flog2,
1952 [TGSI_OPCODE_POW] = nir_op_fpow,
1953 [TGSI_OPCODE_COS] = nir_op_fcos,
1954 [TGSI_OPCODE_DDX] = nir_op_fddx,
1955 [TGSI_OPCODE_DDY] = nir_op_fddy,
1956 [TGSI_OPCODE_KILL] = 0,
1957 [TGSI_OPCODE_PK2H] = 0, /* XXX */
1958 [TGSI_OPCODE_PK2US] = 0, /* XXX */
1959 [TGSI_OPCODE_PK4B] = 0, /* XXX */
1960 [TGSI_OPCODE_PK4UB] = 0, /* XXX */
1961 [TGSI_OPCODE_SEQ] = nir_op_seq,
1962 [TGSI_OPCODE_SGT] = 0,
1963 [TGSI_OPCODE_SIN] = nir_op_fsin,
1964 [TGSI_OPCODE_SNE] = nir_op_sne,
1965 [TGSI_OPCODE_SLE] = 0,
1966 [TGSI_OPCODE_TEX] = 0,
1967 [TGSI_OPCODE_TXD] = 0,
1968 [TGSI_OPCODE_TXP] = 0,
1969 [TGSI_OPCODE_UP2H] = 0, /* XXX */
1970 [TGSI_OPCODE_UP2US] = 0, /* XXX */
1971 [TGSI_OPCODE_UP4B] = 0, /* XXX */
1972 [TGSI_OPCODE_UP4UB] = 0, /* XXX */
1973 [TGSI_OPCODE_ARR] = 0,
1974
1975 /* No function calls, yet. */
1976 [TGSI_OPCODE_CAL] = 0, /* XXX */
1977 [TGSI_OPCODE_RET] = 0, /* XXX */
1978
1979 [TGSI_OPCODE_SSG] = nir_op_fsign,
1980 [TGSI_OPCODE_CMP] = 0,
1981 [TGSI_OPCODE_TXB] = 0,
1982 [TGSI_OPCODE_DIV] = nir_op_fdiv,
1983 [TGSI_OPCODE_DP2] = 0,
1984 [TGSI_OPCODE_TXL] = 0,
1985
1986 [TGSI_OPCODE_BRK] = 0,
1987 [TGSI_OPCODE_IF] = 0,
1988 [TGSI_OPCODE_UIF] = 0,
1989 [TGSI_OPCODE_ELSE] = 0,
1990 [TGSI_OPCODE_ENDIF] = 0,
1991
1992 [TGSI_OPCODE_DDX_FINE] = nir_op_fddx_fine,
1993 [TGSI_OPCODE_DDY_FINE] = nir_op_fddy_fine,
1994
1995 [TGSI_OPCODE_CEIL] = nir_op_fceil,
1996 [TGSI_OPCODE_I2F] = nir_op_i2f32,
1997 [TGSI_OPCODE_NOT] = nir_op_inot,
1998 [TGSI_OPCODE_TRUNC] = nir_op_ftrunc,
1999 [TGSI_OPCODE_SHL] = nir_op_ishl,
2000 [TGSI_OPCODE_AND] = nir_op_iand,
2001 [TGSI_OPCODE_OR] = nir_op_ior,
2002 [TGSI_OPCODE_MOD] = nir_op_umod,
2003 [TGSI_OPCODE_XOR] = nir_op_ixor,
2004 [TGSI_OPCODE_TXF] = 0,
2005 [TGSI_OPCODE_TXQ] = 0,
2006
2007 [TGSI_OPCODE_CONT] = 0,
2008
2009 [TGSI_OPCODE_EMIT] = 0, /* XXX */
2010 [TGSI_OPCODE_ENDPRIM] = 0, /* XXX */
2011
2012 [TGSI_OPCODE_BGNLOOP] = 0,
2013 [TGSI_OPCODE_BGNSUB] = 0, /* XXX: no function calls */
2014 [TGSI_OPCODE_ENDLOOP] = 0,
2015 [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */
2016
2017 [TGSI_OPCODE_NOP] = 0,
2018 [TGSI_OPCODE_FSEQ] = nir_op_feq,
2019 [TGSI_OPCODE_FSGE] = nir_op_fge,
2020 [TGSI_OPCODE_FSLT] = nir_op_flt,
2021 [TGSI_OPCODE_FSNE] = nir_op_fne,
2022
2023 [TGSI_OPCODE_KILL_IF] = 0,
2024
2025 [TGSI_OPCODE_END] = 0,
2026
2027 [TGSI_OPCODE_F2I] = nir_op_f2i32,
2028 [TGSI_OPCODE_IDIV] = nir_op_idiv,
2029 [TGSI_OPCODE_IMAX] = nir_op_imax,
2030 [TGSI_OPCODE_IMIN] = nir_op_imin,
2031 [TGSI_OPCODE_INEG] = nir_op_ineg,
2032 [TGSI_OPCODE_ISGE] = nir_op_ige,
2033 [TGSI_OPCODE_ISHR] = nir_op_ishr,
2034 [TGSI_OPCODE_ISLT] = nir_op_ilt,
2035 [TGSI_OPCODE_F2U] = nir_op_f2u32,
2036 [TGSI_OPCODE_U2F] = nir_op_u2f32,
2037 [TGSI_OPCODE_UADD] = nir_op_iadd,
2038 [TGSI_OPCODE_UDIV] = nir_op_udiv,
2039 [TGSI_OPCODE_UMAD] = 0,
2040 [TGSI_OPCODE_UMAX] = nir_op_umax,
2041 [TGSI_OPCODE_UMIN] = nir_op_umin,
2042 [TGSI_OPCODE_UMOD] = nir_op_umod,
2043 [TGSI_OPCODE_UMUL] = nir_op_imul,
2044 [TGSI_OPCODE_USEQ] = nir_op_ieq,
2045 [TGSI_OPCODE_USGE] = nir_op_uge,
2046 [TGSI_OPCODE_USHR] = nir_op_ushr,
2047 [TGSI_OPCODE_USLT] = nir_op_ult,
2048 [TGSI_OPCODE_USNE] = nir_op_ine,
2049
2050 [TGSI_OPCODE_SWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
2051 [TGSI_OPCODE_CASE] = 0, /* not emitted by glsl_to_tgsi.cpp */
2052 [TGSI_OPCODE_DEFAULT] = 0, /* not emitted by glsl_to_tgsi.cpp */
2053 [TGSI_OPCODE_ENDSWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
2054
2055 /* XXX: SAMPLE opcodes */
2056
2057 [TGSI_OPCODE_UARL] = nir_op_mov,
2058 [TGSI_OPCODE_UCMP] = 0,
2059 [TGSI_OPCODE_IABS] = nir_op_iabs,
2060 [TGSI_OPCODE_ISSG] = nir_op_isign,
2061
2062 [TGSI_OPCODE_LOAD] = 0,
2063 [TGSI_OPCODE_STORE] = 0,
2064
2065 /* XXX: atomics */
2066
2067 [TGSI_OPCODE_TEX2] = 0,
2068 [TGSI_OPCODE_TXB2] = 0,
2069 [TGSI_OPCODE_TXL2] = 0,
2070
2071 [TGSI_OPCODE_IMUL_HI] = nir_op_imul_high,
2072 [TGSI_OPCODE_UMUL_HI] = nir_op_umul_high,
2073
2074 [TGSI_OPCODE_TG4] = 0,
2075 [TGSI_OPCODE_LODQ] = 0,
2076
2077 [TGSI_OPCODE_IBFE] = nir_op_ibitfield_extract,
2078 [TGSI_OPCODE_UBFE] = nir_op_ubitfield_extract,
2079 [TGSI_OPCODE_BFI] = nir_op_bitfield_insert,
2080 [TGSI_OPCODE_BREV] = nir_op_bitfield_reverse,
2081 [TGSI_OPCODE_POPC] = nir_op_bit_count,
2082 [TGSI_OPCODE_LSB] = nir_op_find_lsb,
2083 [TGSI_OPCODE_IMSB] = nir_op_ifind_msb,
2084 [TGSI_OPCODE_UMSB] = nir_op_ufind_msb,
2085
2086 [TGSI_OPCODE_INTERP_CENTROID] = 0, /* XXX */
2087 [TGSI_OPCODE_INTERP_SAMPLE] = 0, /* XXX */
2088 [TGSI_OPCODE_INTERP_OFFSET] = 0, /* XXX */
2089
2090 [TGSI_OPCODE_F2D] = nir_op_f2f64,
2091 [TGSI_OPCODE_D2F] = nir_op_f2f32,
2092 [TGSI_OPCODE_DMUL] = nir_op_fmul,
2093 [TGSI_OPCODE_D2U] = nir_op_f2u32,
2094 [TGSI_OPCODE_U2D] = nir_op_u2f64,
2095
2096 [TGSI_OPCODE_U64ADD] = nir_op_iadd,
2097 [TGSI_OPCODE_U64MUL] = nir_op_imul,
2098 [TGSI_OPCODE_U64DIV] = nir_op_udiv,
2099 [TGSI_OPCODE_U64SNE] = nir_op_ine,
2100 };
2101
2102 static void
2103 ttn_emit_instruction(struct ttn_compile *c)
2104 {
2105 nir_builder *b = &c->build;
2106 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
2107 unsigned i;
2108 unsigned tgsi_op = tgsi_inst->Instruction.Opcode;
2109 struct tgsi_full_dst_register *tgsi_dst = &tgsi_inst->Dst[0];
2110
2111 if (tgsi_op == TGSI_OPCODE_END)
2112 return;
2113
2114 nir_ssa_def *src[TGSI_FULL_MAX_SRC_REGISTERS];
2115 for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) {
2116 src[i] = ttn_get_src(c, &tgsi_inst->Src[i], i);
2117 }
2118 nir_alu_dest dest = ttn_get_dest(c, tgsi_dst);
2119
2120 unsigned tgsi_dst_type = tgsi_opcode_infer_dst_type(tgsi_op, 0);
2121
2122 /* The destination bitsize of the NIR opcode (not TGSI, where it's always
2123 * 32 bits). This needs to be passed into ttn_alu() because it can't be
2124 * inferred for comparison opcodes.
2125 */
2126 unsigned dst_bitsize = tgsi_type_is_64bit(tgsi_dst_type) ? 64 : 32;
2127
2128 switch (tgsi_op) {
2129 case TGSI_OPCODE_RSQ:
2130 ttn_move_dest(b, dest, nir_frsq(b, ttn_channel(b, src[0], X)));
2131 break;
2132
2133 case TGSI_OPCODE_SQRT:
2134 ttn_move_dest(b, dest, nir_fsqrt(b, ttn_channel(b, src[0], X)));
2135 break;
2136
2137 case TGSI_OPCODE_RCP:
2138 ttn_move_dest(b, dest, nir_frcp(b, ttn_channel(b, src[0], X)));
2139 break;
2140
2141 case TGSI_OPCODE_EX2:
2142 ttn_move_dest(b, dest, nir_fexp2(b, ttn_channel(b, src[0], X)));
2143 break;
2144
2145 case TGSI_OPCODE_LG2:
2146 ttn_move_dest(b, dest, nir_flog2(b, ttn_channel(b, src[0], X)));
2147 break;
2148
2149 case TGSI_OPCODE_POW:
2150 ttn_move_dest(b, dest, nir_fpow(b,
2151 ttn_channel(b, src[0], X),
2152 ttn_channel(b, src[1], X)));
2153 break;
2154
2155 case TGSI_OPCODE_COS:
2156 ttn_move_dest(b, dest, nir_fcos(b, ttn_channel(b, src[0], X)));
2157 break;
2158
2159 case TGSI_OPCODE_SIN:
2160 ttn_move_dest(b, dest, nir_fsin(b, ttn_channel(b, src[0], X)));
2161 break;
2162
2163 case TGSI_OPCODE_ARL:
2164 ttn_arl(b, op_trans[tgsi_op], dest, src);
2165 break;
2166
2167 case TGSI_OPCODE_EXP:
2168 ttn_exp(b, op_trans[tgsi_op], dest, src);
2169 break;
2170
2171 case TGSI_OPCODE_LOG:
2172 ttn_log(b, op_trans[tgsi_op], dest, src);
2173 break;
2174
2175 case TGSI_OPCODE_DST:
2176 ttn_dst(b, op_trans[tgsi_op], dest, src);
2177 break;
2178
2179 case TGSI_OPCODE_LIT:
2180 ttn_lit(b, op_trans[tgsi_op], dest, src);
2181 break;
2182
2183 case TGSI_OPCODE_DP2:
2184 ttn_dp2(b, op_trans[tgsi_op], dest, src);
2185 break;
2186
2187 case TGSI_OPCODE_DP3:
2188 ttn_dp3(b, op_trans[tgsi_op], dest, src);
2189 break;
2190
2191 case TGSI_OPCODE_DP4:
2192 ttn_dp4(b, op_trans[tgsi_op], dest, src);
2193 break;
2194
2195 case TGSI_OPCODE_UMAD:
2196 ttn_umad(b, op_trans[tgsi_op], dest, src);
2197 break;
2198
2199 case TGSI_OPCODE_LRP:
2200 ttn_move_dest(b, dest, nir_flrp(b, src[2], src[1], src[0]));
2201 break;
2202
2203 case TGSI_OPCODE_KILL:
2204 ttn_kill(b, op_trans[tgsi_op], dest, src);
2205 break;
2206
2207 case TGSI_OPCODE_ARR:
2208 ttn_arr(b, op_trans[tgsi_op], dest, src);
2209 break;
2210
2211 case TGSI_OPCODE_CMP:
2212 ttn_cmp(b, op_trans[tgsi_op], dest, src);
2213 break;
2214
2215 case TGSI_OPCODE_UCMP:
2216 ttn_ucmp(b, op_trans[tgsi_op], dest, src);
2217 break;
2218
2219 case TGSI_OPCODE_SGT:
2220 ttn_sgt(b, op_trans[tgsi_op], dest, src);
2221 break;
2222
2223 case TGSI_OPCODE_SLE:
2224 ttn_sle(b, op_trans[tgsi_op], dest, src);
2225 break;
2226
2227 case TGSI_OPCODE_KILL_IF:
2228 ttn_kill_if(b, op_trans[tgsi_op], dest, src);
2229 break;
2230
2231 case TGSI_OPCODE_TEX:
2232 case TGSI_OPCODE_TEX_LZ:
2233 case TGSI_OPCODE_TXP:
2234 case TGSI_OPCODE_TXL:
2235 case TGSI_OPCODE_TXB:
2236 case TGSI_OPCODE_TXD:
2237 case TGSI_OPCODE_TEX2:
2238 case TGSI_OPCODE_TXL2:
2239 case TGSI_OPCODE_TXB2:
2240 case TGSI_OPCODE_TXF:
2241 case TGSI_OPCODE_TXF_LZ:
2242 case TGSI_OPCODE_TG4:
2243 case TGSI_OPCODE_LODQ:
2244 ttn_tex(c, dest, src);
2245 break;
2246
2247 case TGSI_OPCODE_TXQ:
2248 ttn_txq(c, dest, src);
2249 break;
2250
2251 case TGSI_OPCODE_LOAD:
2252 case TGSI_OPCODE_STORE:
2253 ttn_mem(c, dest, src);
2254 break;
2255
2256 case TGSI_OPCODE_NOP:
2257 break;
2258
2259 case TGSI_OPCODE_IF:
2260 ttn_if(c, src[0], false);
2261 break;
2262
2263 case TGSI_OPCODE_UIF:
2264 ttn_if(c, src[0], true);
2265 break;
2266
2267 case TGSI_OPCODE_ELSE:
2268 ttn_else(c);
2269 break;
2270
2271 case TGSI_OPCODE_ENDIF:
2272 ttn_endif(c);
2273 break;
2274
2275 case TGSI_OPCODE_BGNLOOP:
2276 ttn_bgnloop(c);
2277 break;
2278
2279 case TGSI_OPCODE_BRK:
2280 ttn_brk(b);
2281 break;
2282
2283 case TGSI_OPCODE_CONT:
2284 ttn_cont(b);
2285 break;
2286
2287 case TGSI_OPCODE_ENDLOOP:
2288 ttn_endloop(c);
2289 break;
2290
2291 default:
2292 if (op_trans[tgsi_op] != 0 || tgsi_op == TGSI_OPCODE_MOV) {
2293 ttn_alu(b, op_trans[tgsi_op], dest, dst_bitsize, src);
2294 } else {
2295 fprintf(stderr, "unknown TGSI opcode: %s\n",
2296 tgsi_get_opcode_name(tgsi_op));
2297 abort();
2298 }
2299 break;
2300 }
2301
2302 if (tgsi_inst->Instruction.Saturate) {
2303 assert(!dest.dest.is_ssa);
2304 ttn_move_dest(b, dest, nir_fsat(b, ttn_src_for_dest(b, &dest)));
2305 }
2306
2307 /* if the dst has a matching var, append store_var to move
2308 * output from reg to var
2309 */
2310 nir_variable *var = ttn_get_var(c, tgsi_dst);
2311 if (var) {
2312 unsigned index = tgsi_dst->Register.Index;
2313 unsigned offset = c->temp_regs[index].offset;
2314 struct tgsi_ind_register *indirect = tgsi_dst->Register.Indirect ?
2315 &tgsi_dst->Indirect : NULL;
2316 nir_src val = nir_src_for_reg(dest.dest.reg.reg);
2317 nir_store_deref(b, ttn_array_deref(c, var, offset, indirect),
2318 nir_ssa_for_src(b, val, 4), dest.write_mask);
2319 }
2320 }
2321
2322 /**
2323 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
2324 * variables at the end of the shader.
2325 *
2326 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
2327 * written, because there's no output load intrinsic, which means we couldn't
2328 * handle writemasks.
2329 */
2330 static void
2331 ttn_add_output_stores(struct ttn_compile *c)
2332 {
2333 nir_builder *b = &c->build;
2334
2335 for (int i = 0; i < c->build.shader->num_outputs; i++) {
2336 nir_variable *var = c->outputs[i];
2337 if (!var)
2338 continue;
2339
2340 nir_src src = nir_src_for_reg(c->output_regs[i].reg);
2341 src.reg.base_offset = c->output_regs[i].offset;
2342
2343 nir_ssa_def *store_value = nir_ssa_for_src(b, src, 4);
2344 if (c->build.shader->info.stage == MESA_SHADER_FRAGMENT) {
2345 /* TGSI uses TGSI_SEMANTIC_POSITION.z for the depth output
2346 * and TGSI_SEMANTIC_STENCIL.y for the stencil output,
2347 * while NIR uses a single-component output.
2348 */
2349 if (var->data.location == FRAG_RESULT_DEPTH)
2350 store_value = nir_channel(b, store_value, 2);
2351 else if (var->data.location == FRAG_RESULT_STENCIL)
2352 store_value = nir_channel(b, store_value, 1);
2353 }
2354
2355 nir_store_deref(b, nir_build_deref_var(b, var), store_value,
2356 (1 << store_value->num_components) - 1);
2357 }
2358 }
2359
2360 /**
2361 * Parses the given TGSI tokens.
2362 */
2363 static void
2364 ttn_parse_tgsi(struct ttn_compile *c, const void *tgsi_tokens)
2365 {
2366 struct tgsi_parse_context parser;
2367 int ret;
2368
2369 ret = tgsi_parse_init(&parser, tgsi_tokens);
2370 assert(ret == TGSI_PARSE_OK);
2371
2372 while (!tgsi_parse_end_of_tokens(&parser)) {
2373 tgsi_parse_token(&parser);
2374 c->token = &parser.FullToken;
2375
2376 switch (parser.FullToken.Token.Type) {
2377 case TGSI_TOKEN_TYPE_DECLARATION:
2378 ttn_emit_declaration(c);
2379 break;
2380
2381 case TGSI_TOKEN_TYPE_INSTRUCTION:
2382 ttn_emit_instruction(c);
2383 break;
2384
2385 case TGSI_TOKEN_TYPE_IMMEDIATE:
2386 ttn_emit_immediate(c);
2387 break;
2388 }
2389 }
2390
2391 tgsi_parse_free(&parser);
2392 }
2393
2394 static void
2395 ttn_read_pipe_caps(struct ttn_compile *c,
2396 struct pipe_screen *screen)
2397 {
2398 c->cap_scalar = screen->get_shader_param(screen, c->scan->processor, PIPE_SHADER_CAP_SCALAR_ISA);
2399 c->cap_packed_uniforms = screen->get_param(screen, PIPE_CAP_PACKED_UNIFORMS);
2400 c->cap_samplers_as_deref = screen->get_param(screen, PIPE_CAP_NIR_SAMPLERS_AS_DEREF);
2401 c->cap_face_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL);
2402 c->cap_position_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL);
2403 c->cap_point_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL);
2404 }
2405
2406 /**
2407 * Initializes a TGSI-to-NIR compiler.
2408 */
2409 static struct ttn_compile *
2410 ttn_compile_init(const void *tgsi_tokens,
2411 const nir_shader_compiler_options *options,
2412 struct pipe_screen *screen)
2413 {
2414 struct ttn_compile *c;
2415 struct nir_shader *s;
2416 struct tgsi_shader_info scan;
2417
2418 assert(options || screen);
2419 c = rzalloc(NULL, struct ttn_compile);
2420
2421 tgsi_scan_shader(tgsi_tokens, &scan);
2422 c->scan = &scan;
2423
2424 if (!options) {
2425 options =
2426 screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR, scan.processor);
2427 }
2428
2429 nir_builder_init_simple_shader(&c->build, NULL,
2430 tgsi_processor_to_shader_stage(scan.processor),
2431 options);
2432
2433 s = c->build.shader;
2434
2435 if (screen) {
2436 ttn_read_pipe_caps(c, screen);
2437 } else {
2438 /* TTN used to be hard coded to always make FACE a sysval,
2439 * so it makes sense to preserve that behavior so users don't break. */
2440 c->cap_face_is_sysval = true;
2441 }
2442
2443 if (s->info.stage == MESA_SHADER_FRAGMENT)
2444 s->info.fs.untyped_color_outputs = true;
2445
2446 s->num_inputs = scan.file_max[TGSI_FILE_INPUT] + 1;
2447 s->num_uniforms = scan.const_file_max[0] + 1;
2448 s->num_outputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
2449
2450 for (unsigned i = 0; i < TGSI_PROPERTY_COUNT; i++) {
2451 unsigned value = scan.properties[i];
2452
2453 switch (i) {
2454 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
2455 break; /* handled in ttn_emit_declaration */
2456 case TGSI_PROPERTY_FS_COORD_ORIGIN:
2457 s->info.fs.origin_upper_left = value == TGSI_FS_COORD_ORIGIN_UPPER_LEFT;
2458 break;
2459 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
2460 s->info.fs.pixel_center_integer = value == TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
2461 break;
2462 case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
2463 s->info.fs.depth_layout = ttn_get_depth_layout(value);
2464 break;
2465 case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION:
2466 s->info.vs.window_space_position = value;
2467 break;
2468 case TGSI_PROPERTY_NEXT_SHADER:
2469 s->info.next_stage = tgsi_processor_to_shader_stage(value);
2470 break;
2471 case TGSI_PROPERTY_VS_BLIT_SGPRS_AMD:
2472 s->info.vs.blit_sgprs_amd = value;
2473 break;
2474 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH:
2475 s->info.cs.local_size[0] = value;
2476 break;
2477 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT:
2478 s->info.cs.local_size[1] = value;
2479 break;
2480 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH:
2481 s->info.cs.local_size[2] = value;
2482 break;
2483 case TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD:
2484 s->info.cs.user_data_components_amd = value;
2485 break;
2486 default:
2487 if (value) {
2488 fprintf(stderr, "tgsi_to_nir: unhandled TGSI property %u = %u\n",
2489 i, value);
2490 unreachable("unhandled TGSI property");
2491 }
2492 }
2493 }
2494
2495 if (s->info.stage == MESA_SHADER_COMPUTE &&
2496 (!s->info.cs.local_size[0] ||
2497 !s->info.cs.local_size[1] ||
2498 !s->info.cs.local_size[2]))
2499 s->info.cs.local_size_variable = true;
2500
2501 c->inputs = rzalloc_array(c, struct nir_variable *, s->num_inputs);
2502 c->outputs = rzalloc_array(c, struct nir_variable *, s->num_outputs);
2503
2504 c->output_regs = rzalloc_array(c, struct ttn_reg_info,
2505 scan.file_max[TGSI_FILE_OUTPUT] + 1);
2506 c->temp_regs = rzalloc_array(c, struct ttn_reg_info,
2507 scan.file_max[TGSI_FILE_TEMPORARY] + 1);
2508 c->imm_defs = rzalloc_array(c, nir_ssa_def *,
2509 scan.file_max[TGSI_FILE_IMMEDIATE] + 1);
2510
2511 c->num_samp_types = scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1;
2512 c->samp_types = rzalloc_array(c, nir_alu_type, c->num_samp_types);
2513
2514 c->if_stack = rzalloc_array(c, nir_cursor,
2515 (scan.opcode_count[TGSI_OPCODE_IF] +
2516 scan.opcode_count[TGSI_OPCODE_UIF]) * 2);
2517 c->loop_stack = rzalloc_array(c, nir_cursor,
2518 scan.opcode_count[TGSI_OPCODE_BGNLOOP]);
2519
2520
2521 ttn_parse_tgsi(c, tgsi_tokens);
2522 ttn_add_output_stores(c);
2523
2524 nir_validate_shader(c->build.shader, "TTN: after parsing TGSI and creating the NIR shader");
2525
2526 return c;
2527 }
2528
2529 static void
2530 ttn_optimize_nir(nir_shader *nir, bool scalar)
2531 {
2532 bool progress;
2533 do {
2534 progress = false;
2535
2536 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2537
2538 if (scalar) {
2539 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
2540 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
2541 }
2542
2543 NIR_PASS_V(nir, nir_lower_alu);
2544 NIR_PASS_V(nir, nir_lower_pack);
2545 NIR_PASS(progress, nir, nir_copy_prop);
2546 NIR_PASS(progress, nir, nir_opt_remove_phis);
2547 NIR_PASS(progress, nir, nir_opt_dce);
2548
2549 if (nir_opt_trivial_continues(nir)) {
2550 progress = true;
2551 NIR_PASS(progress, nir, nir_copy_prop);
2552 NIR_PASS(progress, nir, nir_opt_dce);
2553 }
2554
2555 NIR_PASS(progress, nir, nir_opt_if, false);
2556 NIR_PASS(progress, nir, nir_opt_dead_cf);
2557 NIR_PASS(progress, nir, nir_opt_cse);
2558 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
2559
2560 NIR_PASS(progress, nir, nir_opt_algebraic);
2561 NIR_PASS(progress, nir, nir_opt_constant_folding);
2562
2563 NIR_PASS(progress, nir, nir_opt_undef);
2564 NIR_PASS(progress, nir, nir_opt_conditional_discard);
2565
2566 if (nir->options->max_unroll_iterations) {
2567 NIR_PASS(progress, nir, nir_opt_loop_unroll, (nir_variable_mode)0);
2568 }
2569
2570 } while (progress);
2571
2572 }
2573
2574 /**
2575 * Finalizes the NIR in a similar way as st_glsl_to_nir does.
2576 *
2577 * Drivers expect that these passes are already performed,
2578 * so we have to do it here too.
2579 */
2580 static void
2581 ttn_finalize_nir(struct ttn_compile *c)
2582 {
2583 struct nir_shader *nir = c->build.shader;
2584
2585 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2586 NIR_PASS_V(nir, nir_lower_regs_to_ssa);
2587
2588 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2589 NIR_PASS_V(nir, nir_split_var_copies);
2590 NIR_PASS_V(nir, nir_lower_var_copies);
2591 NIR_PASS_V(nir, nir_lower_system_values);
2592
2593 if (c->cap_packed_uniforms)
2594 NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, 16);
2595
2596 if (c->cap_samplers_as_deref)
2597 NIR_PASS_V(nir, gl_nir_lower_samplers_as_deref, NULL);
2598 else
2599 NIR_PASS_V(nir, gl_nir_lower_samplers, NULL);
2600
2601 ttn_optimize_nir(nir, c->cap_scalar);
2602 nir_shader_gather_info(nir, c->build.impl);
2603 nir_validate_shader(nir, "TTN: after all optimizations");
2604 }
2605
2606 struct nir_shader *
2607 tgsi_to_nir(const void *tgsi_tokens,
2608 struct pipe_screen *screen)
2609 {
2610 struct ttn_compile *c;
2611 struct nir_shader *s;
2612
2613 c = ttn_compile_init(tgsi_tokens, NULL, screen);
2614 s = c->build.shader;
2615 ttn_finalize_nir(c);
2616 ralloc_free(c);
2617
2618 return s;
2619 }
2620
2621 struct nir_shader *
2622 tgsi_to_nir_noscreen(const void *tgsi_tokens,
2623 const nir_shader_compiler_options *options)
2624 {
2625 struct ttn_compile *c;
2626 struct nir_shader *s;
2627
2628 c = ttn_compile_init(tgsi_tokens, options, NULL);
2629 s = c->build.shader;
2630 ralloc_free(c);
2631
2632 return s;
2633 }
2634