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24187503a30958ebdd3d4b552383f4b122577455
[mesa.git] / src / gallium / auxiliary / nir / tgsi_to_nir.c
1 /*
2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/ralloc.h"
26 #include "pipe/p_screen.h"
27
28 #include "compiler/nir/nir.h"
29 #include "compiler/nir/nir_control_flow.h"
30 #include "compiler/nir/nir_builder.h"
31 #include "compiler/glsl/gl_nir.h"
32 #include "compiler/glsl/list.h"
33 #include "compiler/shader_enums.h"
34
35 #include "tgsi_to_nir.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_dump.h"
38 #include "tgsi/tgsi_info.h"
39 #include "tgsi/tgsi_scan.h"
40 #include "tgsi/tgsi_from_mesa.h"
41
42 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
43 TGSI_SWIZZLE_##X, \
44 TGSI_SWIZZLE_##Y, \
45 TGSI_SWIZZLE_##Z, \
46 TGSI_SWIZZLE_##W, \
47 }
48
49 struct ttn_reg_info {
50 /** nir register containing this TGSI index. */
51 nir_register *reg;
52 nir_variable *var;
53 /** Offset (in vec4s) from the start of var for this TGSI index. */
54 int offset;
55 };
56
57 struct ttn_compile {
58 union tgsi_full_token *token;
59 nir_builder build;
60 struct tgsi_shader_info *scan;
61
62 struct ttn_reg_info *output_regs;
63 struct ttn_reg_info *temp_regs;
64 nir_ssa_def **imm_defs;
65
66 unsigned num_samp_types;
67 nir_alu_type *samp_types;
68
69 nir_register *addr_reg;
70
71 nir_variable **inputs;
72 nir_variable **outputs;
73 nir_variable *samplers[PIPE_MAX_SAMPLERS];
74 nir_variable *images[PIPE_MAX_SHADER_IMAGES];
75 nir_variable *ssbo[PIPE_MAX_SHADER_BUFFERS];
76
77 nir_variable *input_var_face;
78 nir_variable *input_var_position;
79 nir_variable *input_var_point;
80
81 /**
82 * Stack of nir_cursors where instructions should be pushed as we pop
83 * back out of the control flow stack.
84 *
85 * For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else
86 * instructions should be placed, and if_stack[if_stack_pos - 1] has where
87 * the next instructions outside of the if/then/else block go.
88 */
89 nir_cursor *if_stack;
90 unsigned if_stack_pos;
91
92 /**
93 * Stack of nir_cursors where instructions should be pushed as we pop
94 * back out of the control flow stack.
95 *
96 * loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside
97 * of the loop.
98 */
99 nir_cursor *loop_stack;
100 unsigned loop_stack_pos;
101
102 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
103 unsigned next_imm;
104
105 bool cap_scalar;
106 bool cap_face_is_sysval;
107 bool cap_position_is_sysval;
108 bool cap_point_is_sysval;
109 bool cap_packed_uniforms;
110 bool cap_samplers_as_deref;
111 };
112
113 #define ttn_swizzle(b, src, x, y, z, w) \
114 nir_swizzle(b, src, SWIZ(x, y, z, w), 4)
115 #define ttn_channel(b, src, swiz) \
116 nir_channel(b, src, TGSI_SWIZZLE_##swiz)
117
118 static gl_varying_slot
119 tgsi_varying_semantic_to_slot(unsigned semantic, unsigned index)
120 {
121 switch (semantic) {
122 case TGSI_SEMANTIC_POSITION:
123 return VARYING_SLOT_POS;
124 case TGSI_SEMANTIC_COLOR:
125 if (index == 0)
126 return VARYING_SLOT_COL0;
127 else
128 return VARYING_SLOT_COL1;
129 case TGSI_SEMANTIC_BCOLOR:
130 if (index == 0)
131 return VARYING_SLOT_BFC0;
132 else
133 return VARYING_SLOT_BFC1;
134 case TGSI_SEMANTIC_FOG:
135 return VARYING_SLOT_FOGC;
136 case TGSI_SEMANTIC_PSIZE:
137 return VARYING_SLOT_PSIZ;
138 case TGSI_SEMANTIC_GENERIC:
139 return VARYING_SLOT_VAR0 + index;
140 case TGSI_SEMANTIC_FACE:
141 return VARYING_SLOT_FACE;
142 case TGSI_SEMANTIC_EDGEFLAG:
143 return VARYING_SLOT_EDGE;
144 case TGSI_SEMANTIC_PRIMID:
145 return VARYING_SLOT_PRIMITIVE_ID;
146 case TGSI_SEMANTIC_CLIPDIST:
147 if (index == 0)
148 return VARYING_SLOT_CLIP_DIST0;
149 else
150 return VARYING_SLOT_CLIP_DIST1;
151 case TGSI_SEMANTIC_CLIPVERTEX:
152 return VARYING_SLOT_CLIP_VERTEX;
153 case TGSI_SEMANTIC_TEXCOORD:
154 return VARYING_SLOT_TEX0 + index;
155 case TGSI_SEMANTIC_PCOORD:
156 return VARYING_SLOT_PNTC;
157 case TGSI_SEMANTIC_VIEWPORT_INDEX:
158 return VARYING_SLOT_VIEWPORT;
159 case TGSI_SEMANTIC_LAYER:
160 return VARYING_SLOT_LAYER;
161 default:
162 fprintf(stderr, "Bad TGSI semantic: %d/%d\n", semantic, index);
163 abort();
164 }
165 }
166
167 static enum gl_frag_depth_layout
168 ttn_get_depth_layout(unsigned tgsi_fs_depth_layout)
169 {
170 switch (tgsi_fs_depth_layout) {
171 case TGSI_FS_DEPTH_LAYOUT_NONE:
172 return FRAG_DEPTH_LAYOUT_NONE;
173 case TGSI_FS_DEPTH_LAYOUT_ANY:
174 return FRAG_DEPTH_LAYOUT_ANY;
175 case TGSI_FS_DEPTH_LAYOUT_GREATER:
176 return FRAG_DEPTH_LAYOUT_GREATER;
177 case TGSI_FS_DEPTH_LAYOUT_LESS:
178 return FRAG_DEPTH_LAYOUT_LESS;
179 case TGSI_FS_DEPTH_LAYOUT_UNCHANGED:
180 return FRAG_DEPTH_LAYOUT_UNCHANGED;
181 default:
182 unreachable("bad TGSI FS depth layout");
183 }
184 }
185
186 static nir_ssa_def *
187 ttn_src_for_dest(nir_builder *b, nir_alu_dest *dest)
188 {
189 nir_alu_src src;
190 memset(&src, 0, sizeof(src));
191
192 if (dest->dest.is_ssa)
193 src.src = nir_src_for_ssa(&dest->dest.ssa);
194 else {
195 assert(!dest->dest.reg.indirect);
196 src.src = nir_src_for_reg(dest->dest.reg.reg);
197 src.src.reg.base_offset = dest->dest.reg.base_offset;
198 }
199
200 for (int i = 0; i < 4; i++)
201 src.swizzle[i] = i;
202
203 return nir_mov_alu(b, src, 4);
204 }
205
206 static enum glsl_interp_mode
207 ttn_translate_interp_mode(unsigned tgsi_interp)
208 {
209 switch (tgsi_interp) {
210 case TGSI_INTERPOLATE_CONSTANT:
211 return INTERP_MODE_FLAT;
212 case TGSI_INTERPOLATE_LINEAR:
213 return INTERP_MODE_NOPERSPECTIVE;
214 case TGSI_INTERPOLATE_PERSPECTIVE:
215 return INTERP_MODE_SMOOTH;
216 case TGSI_INTERPOLATE_COLOR:
217 return INTERP_MODE_SMOOTH;
218 default:
219 unreachable("bad TGSI interpolation mode");
220 }
221 }
222
223 static void
224 ttn_emit_declaration(struct ttn_compile *c)
225 {
226 nir_builder *b = &c->build;
227 struct tgsi_full_declaration *decl = &c->token->FullDeclaration;
228 unsigned array_size = decl->Range.Last - decl->Range.First + 1;
229 unsigned file = decl->Declaration.File;
230 unsigned i;
231
232 if (file == TGSI_FILE_TEMPORARY) {
233 if (decl->Declaration.Array) {
234 /* for arrays, we create variables instead of registers: */
235 nir_variable *var = rzalloc(b->shader, nir_variable);
236
237 var->type = glsl_array_type(glsl_vec4_type(), array_size, 0);
238 var->data.mode = nir_var_shader_temp;
239 var->name = ralloc_asprintf(var, "arr_%d", decl->Array.ArrayID);
240
241 exec_list_push_tail(&b->shader->globals, &var->node);
242
243 for (i = 0; i < array_size; i++) {
244 /* point all the matching slots to the same var,
245 * with appropriate offset set, mostly just so
246 * we know what to do when tgsi does a non-indirect
247 * access
248 */
249 c->temp_regs[decl->Range.First + i].reg = NULL;
250 c->temp_regs[decl->Range.First + i].var = var;
251 c->temp_regs[decl->Range.First + i].offset = i;
252 }
253 } else {
254 for (i = 0; i < array_size; i++) {
255 nir_register *reg = nir_local_reg_create(b->impl);
256 reg->num_components = 4;
257 c->temp_regs[decl->Range.First + i].reg = reg;
258 c->temp_regs[decl->Range.First + i].var = NULL;
259 c->temp_regs[decl->Range.First + i].offset = 0;
260 }
261 }
262 } else if (file == TGSI_FILE_ADDRESS) {
263 c->addr_reg = nir_local_reg_create(b->impl);
264 c->addr_reg->num_components = 4;
265 } else if (file == TGSI_FILE_SYSTEM_VALUE) {
266 /* Nothing to record for system values. */
267 } else if (file == TGSI_FILE_BUFFER) {
268 /* Nothing to record for buffers. */
269 } else if (file == TGSI_FILE_IMAGE) {
270 /* Nothing to record for images. */
271 } else if (file == TGSI_FILE_SAMPLER) {
272 /* Nothing to record for samplers. */
273 } else if (file == TGSI_FILE_SAMPLER_VIEW) {
274 struct tgsi_declaration_sampler_view *sview = &decl->SamplerView;
275 nir_alu_type type;
276
277 assert((sview->ReturnTypeX == sview->ReturnTypeY) &&
278 (sview->ReturnTypeX == sview->ReturnTypeZ) &&
279 (sview->ReturnTypeX == sview->ReturnTypeW));
280
281 switch (sview->ReturnTypeX) {
282 case TGSI_RETURN_TYPE_SINT:
283 type = nir_type_int;
284 break;
285 case TGSI_RETURN_TYPE_UINT:
286 type = nir_type_uint;
287 break;
288 case TGSI_RETURN_TYPE_FLOAT:
289 default:
290 type = nir_type_float;
291 break;
292 }
293
294 for (i = 0; i < array_size; i++) {
295 c->samp_types[decl->Range.First + i] = type;
296 }
297 } else {
298 bool is_array = (array_size > 1);
299
300 assert(file == TGSI_FILE_INPUT ||
301 file == TGSI_FILE_OUTPUT ||
302 file == TGSI_FILE_CONSTANT);
303
304 /* nothing to do for UBOs: */
305 if ((file == TGSI_FILE_CONSTANT) && decl->Declaration.Dimension &&
306 decl->Dim.Index2D != 0) {
307 b->shader->info.num_ubos =
308 MAX2(b->shader->info.num_ubos, decl->Dim.Index2D);
309 return;
310 }
311
312 if ((file == TGSI_FILE_INPUT) || (file == TGSI_FILE_OUTPUT)) {
313 is_array = (is_array && decl->Declaration.Array &&
314 (decl->Array.ArrayID != 0));
315 }
316
317 for (i = 0; i < array_size; i++) {
318 unsigned idx = decl->Range.First + i;
319 nir_variable *var = rzalloc(b->shader, nir_variable);
320
321 var->data.driver_location = idx;
322
323 var->type = glsl_vec4_type();
324 if (is_array)
325 var->type = glsl_array_type(var->type, array_size, 0);
326
327 switch (file) {
328 case TGSI_FILE_INPUT:
329 var->data.read_only = true;
330 var->data.mode = nir_var_shader_in;
331 var->name = ralloc_asprintf(var, "in_%d", idx);
332
333 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
334 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
335 var->type = glsl_bool_type();
336 if (c->cap_face_is_sysval) {
337 var->data.mode = nir_var_system_value;
338 var->data.location = SYSTEM_VALUE_FRONT_FACE;
339 } else {
340 var->data.location = VARYING_SLOT_FACE;
341 }
342 c->input_var_face = var;
343 } else if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
344 if (c->cap_position_is_sysval) {
345 var->data.mode = nir_var_system_value;
346 var->data.location = SYSTEM_VALUE_FRAG_COORD;
347 } else {
348 var->data.location = VARYING_SLOT_POS;
349 }
350 c->input_var_position = var;
351 } else if (decl->Semantic.Name == TGSI_SEMANTIC_PCOORD) {
352 if (c->cap_point_is_sysval) {
353 var->data.mode = nir_var_system_value;
354 var->data.location = SYSTEM_VALUE_POINT_COORD;
355 } else {
356 var->data.location = VARYING_SLOT_PNTC;
357 }
358 c->input_var_point = var;
359 } else {
360 var->data.location =
361 tgsi_varying_semantic_to_slot(decl->Semantic.Name,
362 decl->Semantic.Index);
363 }
364 } else {
365 assert(!decl->Declaration.Semantic);
366 var->data.location = VERT_ATTRIB_GENERIC0 + idx;
367 }
368 var->data.index = 0;
369 var->data.interpolation =
370 ttn_translate_interp_mode(decl->Interp.Interpolate);
371
372 exec_list_push_tail(&b->shader->inputs, &var->node);
373 c->inputs[idx] = var;
374
375 for (int i = 0; i < array_size; i++)
376 b->shader->info.inputs_read |= 1 << (var->data.location + i);
377
378 break;
379 case TGSI_FILE_OUTPUT: {
380 int semantic_name = decl->Semantic.Name;
381 int semantic_index = decl->Semantic.Index;
382 /* Since we can't load from outputs in the IR, we make temporaries
383 * for the outputs and emit stores to the real outputs at the end of
384 * the shader.
385 */
386 nir_register *reg = nir_local_reg_create(b->impl);
387 reg->num_components = 4;
388 if (is_array)
389 reg->num_array_elems = array_size;
390
391 var->data.mode = nir_var_shader_out;
392 var->name = ralloc_asprintf(var, "out_%d", idx);
393 var->data.index = 0;
394 var->data.interpolation =
395 ttn_translate_interp_mode(decl->Interp.Interpolate);
396
397 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
398 switch (semantic_name) {
399 case TGSI_SEMANTIC_COLOR: {
400 /* TODO tgsi loses some information, so we cannot
401 * actually differentiate here between DSB and MRT
402 * at this point. But so far no drivers using tgsi-
403 * to-nir support dual source blend:
404 */
405 bool dual_src_blend = false;
406 if (dual_src_blend && (semantic_index == 1)) {
407 var->data.location = FRAG_RESULT_DATA0;
408 var->data.index = 1;
409 } else {
410 if (c->scan->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
411 var->data.location = FRAG_RESULT_COLOR;
412 else
413 var->data.location = FRAG_RESULT_DATA0 + semantic_index;
414 }
415 break;
416 }
417 case TGSI_SEMANTIC_POSITION:
418 var->data.location = FRAG_RESULT_DEPTH;
419 var->type = glsl_float_type();
420 break;
421 case TGSI_SEMANTIC_STENCIL:
422 var->data.location = FRAG_RESULT_STENCIL;
423 var->type = glsl_int_type();
424 break;
425 default:
426 fprintf(stderr, "Bad TGSI semantic: %d/%d\n",
427 decl->Semantic.Name, decl->Semantic.Index);
428 abort();
429 }
430 } else {
431 var->data.location =
432 tgsi_varying_semantic_to_slot(semantic_name, semantic_index);
433 }
434
435 if (is_array) {
436 unsigned j;
437 for (j = 0; j < array_size; j++) {
438 c->output_regs[idx + j].offset = i + j;
439 c->output_regs[idx + j].reg = reg;
440 }
441 } else {
442 c->output_regs[idx].offset = i;
443 c->output_regs[idx].reg = reg;
444 }
445
446 exec_list_push_tail(&b->shader->outputs, &var->node);
447 c->outputs[idx] = var;
448
449 for (int i = 0; i < array_size; i++)
450 b->shader->info.outputs_written |= 1ull << (var->data.location + i);
451 }
452 break;
453 case TGSI_FILE_CONSTANT:
454 var->data.mode = nir_var_uniform;
455 var->name = ralloc_asprintf(var, "uniform_%d", idx);
456 var->data.location = idx;
457
458 exec_list_push_tail(&b->shader->uniforms, &var->node);
459 break;
460 default:
461 unreachable("bad declaration file");
462 return;
463 }
464
465 if (is_array)
466 break;
467 }
468
469 }
470 }
471
472 static void
473 ttn_emit_immediate(struct ttn_compile *c)
474 {
475 nir_builder *b = &c->build;
476 struct tgsi_full_immediate *tgsi_imm = &c->token->FullImmediate;
477 nir_load_const_instr *load_const;
478 int i;
479
480 load_const = nir_load_const_instr_create(b->shader, 4, 32);
481 c->imm_defs[c->next_imm] = &load_const->def;
482 c->next_imm++;
483
484 for (i = 0; i < load_const->def.num_components; i++)
485 load_const->value[i].u32 = tgsi_imm->u[i].Uint;
486
487 nir_builder_instr_insert(b, &load_const->instr);
488 }
489
490 static nir_ssa_def *
491 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect);
492
493 /* generate either a constant or indirect deref chain for accessing an
494 * array variable.
495 */
496 static nir_deref_instr *
497 ttn_array_deref(struct ttn_compile *c, nir_variable *var, unsigned offset,
498 struct tgsi_ind_register *indirect)
499 {
500 nir_deref_instr *deref = nir_build_deref_var(&c->build, var);
501 nir_ssa_def *index = nir_imm_int(&c->build, offset);
502 if (indirect)
503 index = nir_iadd(&c->build, index, ttn_src_for_indirect(c, indirect));
504 return nir_build_deref_array(&c->build, deref, index);
505 }
506
507 /* Special case: Turn the frontface varying into a load of the
508 * frontface variable, and create the vector as required by TGSI.
509 */
510 static nir_ssa_def *
511 ttn_emulate_tgsi_front_face(struct ttn_compile *c)
512 {
513 nir_ssa_def *tgsi_frontface[4];
514
515 if (c->cap_face_is_sysval) {
516 /* When it's a system value, it should be an integer vector: (F, 0, 0, 1)
517 * F is 0xffffffff if front-facing, 0 if not.
518 */
519
520 nir_ssa_def *frontface = nir_load_front_face(&c->build, 1);
521
522 tgsi_frontface[0] = nir_bcsel(&c->build,
523 frontface,
524 nir_imm_int(&c->build, 0xffffffff),
525 nir_imm_int(&c->build, 0));
526 tgsi_frontface[1] = nir_imm_int(&c->build, 0);
527 tgsi_frontface[2] = nir_imm_int(&c->build, 0);
528 tgsi_frontface[3] = nir_imm_int(&c->build, 1);
529 } else {
530 /* When it's an input, it should be a float vector: (F, 0.0, 0.0, 1.0)
531 * F is positive if front-facing, negative if not.
532 */
533
534 assert(c->input_var_face);
535 nir_ssa_def *frontface = nir_load_var(&c->build, c->input_var_face);
536
537 tgsi_frontface[0] = nir_bcsel(&c->build,
538 frontface,
539 nir_imm_float(&c->build, 1.0),
540 nir_imm_float(&c->build, -1.0));
541 tgsi_frontface[1] = nir_imm_float(&c->build, 0.0);
542 tgsi_frontface[2] = nir_imm_float(&c->build, 0.0);
543 tgsi_frontface[3] = nir_imm_float(&c->build, 1.0);
544 }
545
546 return nir_vec(&c->build, tgsi_frontface, 4);
547 }
548
549 static nir_src
550 ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
551 struct tgsi_ind_register *indirect,
552 struct tgsi_dimension *dim,
553 struct tgsi_ind_register *dimind,
554 bool src_is_float)
555 {
556 nir_builder *b = &c->build;
557 nir_src src;
558
559 memset(&src, 0, sizeof(src));
560
561 switch (file) {
562 case TGSI_FILE_TEMPORARY:
563 if (c->temp_regs[index].var) {
564 unsigned offset = c->temp_regs[index].offset;
565 nir_variable *var = c->temp_regs[index].var;
566 nir_ssa_def *load = nir_load_deref(&c->build,
567 ttn_array_deref(c, var, offset, indirect));
568
569 src = nir_src_for_ssa(load);
570 } else {
571 assert(!indirect);
572 src.reg.reg = c->temp_regs[index].reg;
573 }
574 assert(!dim);
575 break;
576
577 case TGSI_FILE_ADDRESS:
578 src.reg.reg = c->addr_reg;
579 assert(!dim);
580 break;
581
582 case TGSI_FILE_IMMEDIATE:
583 src = nir_src_for_ssa(c->imm_defs[index]);
584 assert(!indirect);
585 assert(!dim);
586 break;
587
588 case TGSI_FILE_SYSTEM_VALUE: {
589 nir_intrinsic_op op;
590 nir_ssa_def *load;
591
592 assert(!indirect);
593 assert(!dim);
594
595 switch (c->scan->system_value_semantic_name[index]) {
596 case TGSI_SEMANTIC_VERTEXID_NOBASE:
597 op = nir_intrinsic_load_vertex_id_zero_base;
598 load = nir_load_vertex_id_zero_base(b);
599 break;
600 case TGSI_SEMANTIC_VERTEXID:
601 op = nir_intrinsic_load_vertex_id;
602 load = nir_load_vertex_id(b);
603 break;
604 case TGSI_SEMANTIC_BASEVERTEX:
605 op = nir_intrinsic_load_base_vertex;
606 load = nir_load_base_vertex(b);
607 break;
608 case TGSI_SEMANTIC_INSTANCEID:
609 op = nir_intrinsic_load_instance_id;
610 load = nir_load_instance_id(b);
611 break;
612 case TGSI_SEMANTIC_FACE:
613 assert(c->cap_face_is_sysval);
614 op = nir_intrinsic_load_front_face;
615 load = ttn_emulate_tgsi_front_face(c);
616 break;
617 case TGSI_SEMANTIC_POSITION:
618 assert(c->cap_position_is_sysval);
619 op = nir_intrinsic_load_frag_coord;
620 load = nir_load_frag_coord(b);
621 break;
622 case TGSI_SEMANTIC_PCOORD:
623 assert(c->cap_point_is_sysval);
624 op = nir_intrinsic_load_point_coord;
625 load = nir_load_point_coord(b);
626 break;
627 case TGSI_SEMANTIC_THREAD_ID:
628 op = nir_intrinsic_load_local_invocation_id;
629 load = nir_load_local_invocation_id(b);
630 break;
631 case TGSI_SEMANTIC_BLOCK_ID:
632 op = nir_intrinsic_load_work_group_id;
633 load = nir_load_work_group_id(b);
634 break;
635 case TGSI_SEMANTIC_CS_USER_DATA_AMD:
636 op = nir_intrinsic_load_user_data_amd;
637 load = nir_load_user_data_amd(b);
638 break;
639 default:
640 unreachable("bad system value");
641 }
642
643 src = nir_src_for_ssa(load);
644 b->shader->info.system_values_read |=
645 (1 << nir_system_value_from_intrinsic(op));
646
647 break;
648 }
649
650 case TGSI_FILE_INPUT:
651 if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
652 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_FACE) {
653 assert(!c->cap_face_is_sysval && c->input_var_face);
654 return nir_src_for_ssa(ttn_emulate_tgsi_front_face(c));
655 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
656 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_POSITION) {
657 assert(!c->cap_position_is_sysval && c->input_var_position);
658 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_position));
659 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
660 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_PCOORD) {
661 assert(!c->cap_point_is_sysval && c->input_var_point);
662 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_point));
663 } else {
664 /* Indirection on input arrays isn't supported by TTN. */
665 assert(!dim);
666 nir_deref_instr *deref = nir_build_deref_var(&c->build,
667 c->inputs[index]);
668 return nir_src_for_ssa(nir_load_deref(&c->build, deref));
669 }
670 break;
671
672 case TGSI_FILE_CONSTANT: {
673 nir_intrinsic_instr *load;
674 nir_intrinsic_op op;
675 unsigned srcn = 0;
676
677 if (dim && (dim->Index > 0 || dim->Indirect)) {
678 op = nir_intrinsic_load_ubo;
679 } else {
680 op = nir_intrinsic_load_uniform;
681 }
682
683 load = nir_intrinsic_instr_create(b->shader, op);
684 if (op == nir_intrinsic_load_uniform) {
685 nir_intrinsic_set_type(load, src_is_float ? nir_type_float :
686 nir_type_int);
687 }
688
689 load->num_components = 4;
690 if (dim && (dim->Index > 0 || dim->Indirect)) {
691 if (dimind) {
692 load->src[srcn] =
693 ttn_src_for_file_and_index(c, dimind->File, dimind->Index,
694 NULL, NULL, NULL, false);
695 } else {
696 /* UBOs start at index 1 in TGSI: */
697 load->src[srcn] =
698 nir_src_for_ssa(nir_imm_int(b, dim->Index - 1));
699 }
700 srcn++;
701 }
702
703 nir_ssa_def *offset;
704 if (op == nir_intrinsic_load_ubo) {
705 /* UBO loads don't have a base offset. */
706 offset = nir_imm_int(b, index);
707 if (indirect) {
708 offset = nir_iadd(b, offset, ttn_src_for_indirect(c, indirect));
709 }
710 /* UBO offsets are in bytes, but TGSI gives them to us in vec4's */
711 offset = nir_ishl(b, offset, nir_imm_int(b, 4));
712 } else {
713 nir_intrinsic_set_base(load, index);
714 if (indirect) {
715 offset = ttn_src_for_indirect(c, indirect);
716 } else {
717 offset = nir_imm_int(b, 0);
718 }
719 }
720 load->src[srcn++] = nir_src_for_ssa(offset);
721
722 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
723 nir_builder_instr_insert(b, &load->instr);
724
725 src = nir_src_for_ssa(&load->dest.ssa);
726 break;
727 }
728
729 default:
730 unreachable("bad src file");
731 }
732
733
734 return src;
735 }
736
737 static nir_ssa_def *
738 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect)
739 {
740 nir_builder *b = &c->build;
741 nir_alu_src src;
742 memset(&src, 0, sizeof(src));
743 for (int i = 0; i < 4; i++)
744 src.swizzle[i] = indirect->Swizzle;
745 src.src = ttn_src_for_file_and_index(c,
746 indirect->File,
747 indirect->Index,
748 NULL, NULL, NULL,
749 false);
750 return nir_mov_alu(b, src, 1);
751 }
752
753 static nir_alu_dest
754 ttn_get_dest(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
755 {
756 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
757 nir_alu_dest dest;
758 unsigned index = tgsi_dst->Index;
759
760 memset(&dest, 0, sizeof(dest));
761
762 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
763 if (c->temp_regs[index].var) {
764 nir_register *reg;
765
766 /* this works, because TGSI will give us a base offset
767 * (in case of indirect index) that points back into
768 * the array. Access can be direct or indirect, we
769 * don't really care. Just create a one-shot dst reg
770 * that will get store_var'd back into the array var
771 * at the end of ttn_emit_instruction()
772 */
773 reg = nir_local_reg_create(c->build.impl);
774 reg->num_components = 4;
775 dest.dest.reg.reg = reg;
776 dest.dest.reg.base_offset = 0;
777 } else {
778 assert(!tgsi_dst->Indirect);
779 dest.dest.reg.reg = c->temp_regs[index].reg;
780 dest.dest.reg.base_offset = c->temp_regs[index].offset;
781 }
782 } else if (tgsi_dst->File == TGSI_FILE_OUTPUT) {
783 dest.dest.reg.reg = c->output_regs[index].reg;
784 dest.dest.reg.base_offset = c->output_regs[index].offset;
785 } else if (tgsi_dst->File == TGSI_FILE_ADDRESS) {
786 assert(index == 0);
787 dest.dest.reg.reg = c->addr_reg;
788 }
789
790 dest.write_mask = tgsi_dst->WriteMask;
791 dest.saturate = false;
792
793 if (tgsi_dst->Indirect && (tgsi_dst->File != TGSI_FILE_TEMPORARY)) {
794 nir_src *indirect = ralloc(c->build.shader, nir_src);
795 *indirect = nir_src_for_ssa(ttn_src_for_indirect(c, &tgsi_fdst->Indirect));
796 dest.dest.reg.indirect = indirect;
797 }
798
799 return dest;
800 }
801
802 static nir_variable *
803 ttn_get_var(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
804 {
805 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
806 unsigned index = tgsi_dst->Index;
807
808 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
809 /* we should not have an indirect when there is no var! */
810 if (!c->temp_regs[index].var)
811 assert(!tgsi_dst->Indirect);
812 return c->temp_regs[index].var;
813 }
814
815 return NULL;
816 }
817
818 static nir_ssa_def *
819 ttn_get_src(struct ttn_compile *c, struct tgsi_full_src_register *tgsi_fsrc,
820 int src_idx)
821 {
822 nir_builder *b = &c->build;
823 struct tgsi_src_register *tgsi_src = &tgsi_fsrc->Register;
824 enum tgsi_opcode opcode = c->token->FullInstruction.Instruction.Opcode;
825 unsigned tgsi_src_type = tgsi_opcode_infer_src_type(opcode, src_idx);
826 bool src_is_float = (tgsi_src_type == TGSI_TYPE_FLOAT ||
827 tgsi_src_type == TGSI_TYPE_DOUBLE ||
828 tgsi_src_type == TGSI_TYPE_UNTYPED);
829 nir_alu_src src;
830
831 memset(&src, 0, sizeof(src));
832
833 if (tgsi_src->File == TGSI_FILE_NULL) {
834 return nir_imm_float(b, 0.0);
835 } else if (tgsi_src->File == TGSI_FILE_SAMPLER ||
836 tgsi_src->File == TGSI_FILE_IMAGE ||
837 tgsi_src->File == TGSI_FILE_BUFFER) {
838 /* Only the index of the resource gets used in texturing, and it will
839 * handle looking that up on its own instead of using the nir_alu_src.
840 */
841 assert(!tgsi_src->Indirect);
842 return NULL;
843 } else {
844 struct tgsi_ind_register *ind = NULL;
845 struct tgsi_dimension *dim = NULL;
846 struct tgsi_ind_register *dimind = NULL;
847 if (tgsi_src->Indirect)
848 ind = &tgsi_fsrc->Indirect;
849 if (tgsi_src->Dimension) {
850 dim = &tgsi_fsrc->Dimension;
851 if (dim->Indirect)
852 dimind = &tgsi_fsrc->DimIndirect;
853 }
854 src.src = ttn_src_for_file_and_index(c,
855 tgsi_src->File,
856 tgsi_src->Index,
857 ind, dim, dimind,
858 src_is_float);
859 }
860
861 src.swizzle[0] = tgsi_src->SwizzleX;
862 src.swizzle[1] = tgsi_src->SwizzleY;
863 src.swizzle[2] = tgsi_src->SwizzleZ;
864 src.swizzle[3] = tgsi_src->SwizzleW;
865
866 nir_ssa_def *def = nir_mov_alu(b, src, 4);
867
868 if (tgsi_type_is_64bit(tgsi_src_type))
869 def = nir_bitcast_vector(b, def, 64);
870
871 if (tgsi_src->Absolute) {
872 if (src_is_float)
873 def = nir_fabs(b, def);
874 else
875 def = nir_iabs(b, def);
876 }
877
878 if (tgsi_src->Negate) {
879 if (src_is_float)
880 def = nir_fneg(b, def);
881 else
882 def = nir_ineg(b, def);
883 }
884
885 return def;
886 }
887
888 static void
889 ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
890 nir_ssa_def *def, unsigned write_mask)
891 {
892 if (!(dest.write_mask & write_mask))
893 return;
894
895 nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
896 mov->dest = dest;
897 mov->dest.write_mask &= write_mask;
898 mov->src[0].src = nir_src_for_ssa(def);
899 for (unsigned i = def->num_components; i < 4; i++)
900 mov->src[0].swizzle[i] = def->num_components - 1;
901 nir_builder_instr_insert(b, &mov->instr);
902 }
903
904 static void
905 ttn_move_dest(nir_builder *b, nir_alu_dest dest, nir_ssa_def *def)
906 {
907 ttn_move_dest_masked(b, dest, def, TGSI_WRITEMASK_XYZW);
908 }
909
910 static void
911 ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, unsigned dest_bitsize,
912 nir_ssa_def **src)
913 {
914 nir_ssa_def *def = nir_build_alu_src_arr(b, op, src);
915 if (def->bit_size == 1)
916 def = nir_ineg(b, nir_b2i(b, def, dest_bitsize));
917 assert(def->bit_size == dest_bitsize);
918 if (dest_bitsize == 64) {
919 if (def->num_components > 2) {
920 /* 32 -> 64 bit conversion ops are supposed to only convert the first
921 * two components, and we need to truncate here to avoid creating a
922 * vec8 after bitcasting the destination.
923 */
924 def = nir_channels(b, def, 0x3);
925 }
926 def = nir_bitcast_vector(b, def, 32);
927 }
928 ttn_move_dest(b, dest, def);
929 }
930
931 static void
932 ttn_arl(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
933 {
934 ttn_move_dest(b, dest, nir_f2i32(b, nir_ffloor(b, src[0])));
935 }
936
937 /* EXP - Approximate Exponential Base 2
938 * dst.x = 2^{\lfloor src.x\rfloor}
939 * dst.y = src.x - \lfloor src.x\rfloor
940 * dst.z = 2^{src.x}
941 * dst.w = 1.0
942 */
943 static void
944 ttn_exp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
945 {
946 nir_ssa_def *srcx = ttn_channel(b, src[0], X);
947
948 ttn_move_dest_masked(b, dest, nir_fexp2(b, nir_ffloor(b, srcx)),
949 TGSI_WRITEMASK_X);
950 ttn_move_dest_masked(b, dest, nir_fsub(b, srcx, nir_ffloor(b, srcx)),
951 TGSI_WRITEMASK_Y);
952 ttn_move_dest_masked(b, dest, nir_fexp2(b, srcx), TGSI_WRITEMASK_Z);
953 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
954 }
955
956 /* LOG - Approximate Logarithm Base 2
957 * dst.x = \lfloor\log_2{|src.x|}\rfloor
958 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
959 * dst.z = \log_2{|src.x|}
960 * dst.w = 1.0
961 */
962 static void
963 ttn_log(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
964 {
965 nir_ssa_def *abs_srcx = nir_fabs(b, ttn_channel(b, src[0], X));
966 nir_ssa_def *log2 = nir_flog2(b, abs_srcx);
967
968 ttn_move_dest_masked(b, dest, nir_ffloor(b, log2), TGSI_WRITEMASK_X);
969 ttn_move_dest_masked(b, dest,
970 nir_fdiv(b, abs_srcx, nir_fexp2(b, nir_ffloor(b, log2))),
971 TGSI_WRITEMASK_Y);
972 ttn_move_dest_masked(b, dest, nir_flog2(b, abs_srcx), TGSI_WRITEMASK_Z);
973 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
974 }
975
976 /* DST - Distance Vector
977 * dst.x = 1.0
978 * dst.y = src0.y \times src1.y
979 * dst.z = src0.z
980 * dst.w = src1.w
981 */
982 static void
983 ttn_dst(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
984 {
985 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_X);
986 ttn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), TGSI_WRITEMASK_Y);
987 ttn_move_dest_masked(b, dest, nir_mov(b, src[0]), TGSI_WRITEMASK_Z);
988 ttn_move_dest_masked(b, dest, nir_mov(b, src[1]), TGSI_WRITEMASK_W);
989 }
990
991 /* LIT - Light Coefficients
992 * dst.x = 1.0
993 * dst.y = max(src.x, 0.0)
994 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
995 * dst.w = 1.0
996 */
997 static void
998 ttn_lit(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
999 {
1000 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_XW);
1001
1002 ttn_move_dest_masked(b, dest, nir_fmax(b, ttn_channel(b, src[0], X),
1003 nir_imm_float(b, 0.0)), TGSI_WRITEMASK_Y);
1004
1005 if (dest.write_mask & TGSI_WRITEMASK_Z) {
1006 nir_ssa_def *src0_y = ttn_channel(b, src[0], Y);
1007 nir_ssa_def *wclamp = nir_fmax(b, nir_fmin(b, ttn_channel(b, src[0], W),
1008 nir_imm_float(b, 128.0)),
1009 nir_imm_float(b, -128.0));
1010 nir_ssa_def *pow = nir_fpow(b, nir_fmax(b, src0_y, nir_imm_float(b, 0.0)),
1011 wclamp);
1012
1013 ttn_move_dest_masked(b, dest,
1014 nir_bcsel(b,
1015 nir_flt(b,
1016 ttn_channel(b, src[0], X),
1017 nir_imm_float(b, 0.0)),
1018 nir_imm_float(b, 0.0),
1019 pow),
1020 TGSI_WRITEMASK_Z);
1021 }
1022 }
1023
1024 static void
1025 ttn_sle(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1026 {
1027 ttn_move_dest(b, dest, nir_sge(b, src[1], src[0]));
1028 }
1029
1030 static void
1031 ttn_sgt(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1032 {
1033 ttn_move_dest(b, dest, nir_slt(b, src[1], src[0]));
1034 }
1035
1036 static void
1037 ttn_dp2(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1038 {
1039 ttn_move_dest(b, dest, nir_fdot2(b, src[0], src[1]));
1040 }
1041
1042 static void
1043 ttn_dp3(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1044 {
1045 ttn_move_dest(b, dest, nir_fdot3(b, src[0], src[1]));
1046 }
1047
1048 static void
1049 ttn_dp4(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1050 {
1051 ttn_move_dest(b, dest, nir_fdot4(b, src[0], src[1]));
1052 }
1053
1054 static void
1055 ttn_umad(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1056 {
1057 ttn_move_dest(b, dest, nir_iadd(b, nir_imul(b, src[0], src[1]), src[2]));
1058 }
1059
1060 static void
1061 ttn_arr(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1062 {
1063 ttn_move_dest(b, dest, nir_f2i32(b, nir_fround_even(b, src[0])));
1064 }
1065
1066 static void
1067 ttn_cmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1068 {
1069 ttn_move_dest(b, dest, nir_bcsel(b,
1070 nir_flt(b, src[0], nir_imm_float(b, 0.0)),
1071 src[1], src[2]));
1072 }
1073
1074 static void
1075 ttn_ucmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1076 {
1077 ttn_move_dest(b, dest, nir_bcsel(b,
1078 nir_ine(b, src[0], nir_imm_int(b, 0)),
1079 src[1], src[2]));
1080 }
1081
1082 static void
1083 ttn_kill(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1084 {
1085 nir_intrinsic_instr *discard =
1086 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard);
1087 nir_builder_instr_insert(b, &discard->instr);
1088 b->shader->info.fs.uses_discard = true;
1089 }
1090
1091 static void
1092 ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1093 {
1094 nir_ssa_def *cmp = nir_bany(b, nir_flt(b, src[0], nir_imm_float(b, 0.0)));
1095 nir_intrinsic_instr *discard =
1096 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard_if);
1097 discard->src[0] = nir_src_for_ssa(cmp);
1098 nir_builder_instr_insert(b, &discard->instr);
1099 b->shader->info.fs.uses_discard = true;
1100 }
1101
1102 static void
1103 ttn_if(struct ttn_compile *c, nir_ssa_def *src, bool is_uint)
1104 {
1105 nir_builder *b = &c->build;
1106 nir_ssa_def *src_x = ttn_channel(b, src, X);
1107
1108 nir_if *if_stmt = nir_if_create(b->shader);
1109 if (is_uint) {
1110 /* equivalent to TGSI UIF, src is interpreted as integer */
1111 if_stmt->condition = nir_src_for_ssa(nir_ine(b, src_x, nir_imm_int(b, 0)));
1112 } else {
1113 /* equivalent to TGSI IF, src is interpreted as float */
1114 if_stmt->condition = nir_src_for_ssa(nir_fne(b, src_x, nir_imm_float(b, 0.0)));
1115 }
1116 nir_builder_cf_insert(b, &if_stmt->cf_node);
1117
1118 c->if_stack[c->if_stack_pos] = nir_after_cf_node(&if_stmt->cf_node);
1119 c->if_stack_pos++;
1120
1121 b->cursor = nir_after_cf_list(&if_stmt->then_list);
1122
1123 c->if_stack[c->if_stack_pos] = nir_after_cf_list(&if_stmt->else_list);
1124 c->if_stack_pos++;
1125 }
1126
1127 static void
1128 ttn_else(struct ttn_compile *c)
1129 {
1130 nir_builder *b = &c->build;
1131
1132 b->cursor = c->if_stack[c->if_stack_pos - 1];
1133 }
1134
1135 static void
1136 ttn_endif(struct ttn_compile *c)
1137 {
1138 nir_builder *b = &c->build;
1139
1140 c->if_stack_pos -= 2;
1141 b->cursor = c->if_stack[c->if_stack_pos];
1142 }
1143
1144 static void
1145 ttn_bgnloop(struct ttn_compile *c)
1146 {
1147 nir_builder *b = &c->build;
1148
1149 nir_loop *loop = nir_loop_create(b->shader);
1150 nir_builder_cf_insert(b, &loop->cf_node);
1151
1152 c->loop_stack[c->loop_stack_pos] = nir_after_cf_node(&loop->cf_node);
1153 c->loop_stack_pos++;
1154
1155 b->cursor = nir_after_cf_list(&loop->body);
1156 }
1157
1158 static void
1159 ttn_cont(nir_builder *b)
1160 {
1161 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_continue);
1162 nir_builder_instr_insert(b, &instr->instr);
1163 }
1164
1165 static void
1166 ttn_brk(nir_builder *b)
1167 {
1168 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
1169 nir_builder_instr_insert(b, &instr->instr);
1170 }
1171
1172 static void
1173 ttn_endloop(struct ttn_compile *c)
1174 {
1175 nir_builder *b = &c->build;
1176
1177 c->loop_stack_pos--;
1178 b->cursor = c->loop_stack[c->loop_stack_pos];
1179 }
1180
1181 static void
1182 get_texture_info(unsigned texture,
1183 enum glsl_sampler_dim *dim,
1184 bool *is_shadow,
1185 bool *is_array)
1186 {
1187 assert(is_array);
1188 *is_array = false;
1189
1190 if (is_shadow)
1191 *is_shadow = false;
1192
1193 switch (texture) {
1194 case TGSI_TEXTURE_BUFFER:
1195 *dim = GLSL_SAMPLER_DIM_BUF;
1196 break;
1197 case TGSI_TEXTURE_1D:
1198 *dim = GLSL_SAMPLER_DIM_1D;
1199 break;
1200 case TGSI_TEXTURE_1D_ARRAY:
1201 *dim = GLSL_SAMPLER_DIM_1D;
1202 *is_array = true;
1203 break;
1204 case TGSI_TEXTURE_SHADOW1D:
1205 *dim = GLSL_SAMPLER_DIM_1D;
1206 *is_shadow = true;
1207 break;
1208 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1209 *dim = GLSL_SAMPLER_DIM_1D;
1210 *is_shadow = true;
1211 *is_array = true;
1212 break;
1213 case TGSI_TEXTURE_2D:
1214 *dim = GLSL_SAMPLER_DIM_2D;
1215 break;
1216 case TGSI_TEXTURE_2D_ARRAY:
1217 *dim = GLSL_SAMPLER_DIM_2D;
1218 *is_array = true;
1219 break;
1220 case TGSI_TEXTURE_2D_MSAA:
1221 *dim = GLSL_SAMPLER_DIM_MS;
1222 break;
1223 case TGSI_TEXTURE_2D_ARRAY_MSAA:
1224 *dim = GLSL_SAMPLER_DIM_MS;
1225 *is_array = true;
1226 break;
1227 case TGSI_TEXTURE_SHADOW2D:
1228 *dim = GLSL_SAMPLER_DIM_2D;
1229 *is_shadow = true;
1230 break;
1231 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1232 *dim = GLSL_SAMPLER_DIM_2D;
1233 *is_shadow = true;
1234 *is_array = true;
1235 break;
1236 case TGSI_TEXTURE_3D:
1237 *dim = GLSL_SAMPLER_DIM_3D;
1238 break;
1239 case TGSI_TEXTURE_CUBE:
1240 *dim = GLSL_SAMPLER_DIM_CUBE;
1241 break;
1242 case TGSI_TEXTURE_CUBE_ARRAY:
1243 *dim = GLSL_SAMPLER_DIM_CUBE;
1244 *is_array = true;
1245 break;
1246 case TGSI_TEXTURE_SHADOWCUBE:
1247 *dim = GLSL_SAMPLER_DIM_CUBE;
1248 *is_shadow = true;
1249 break;
1250 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1251 *dim = GLSL_SAMPLER_DIM_CUBE;
1252 *is_shadow = true;
1253 *is_array = true;
1254 break;
1255 case TGSI_TEXTURE_RECT:
1256 *dim = GLSL_SAMPLER_DIM_RECT;
1257 break;
1258 case TGSI_TEXTURE_SHADOWRECT:
1259 *dim = GLSL_SAMPLER_DIM_RECT;
1260 *is_shadow = true;
1261 break;
1262 default:
1263 fprintf(stderr, "Unknown TGSI texture target %d\n", texture);
1264 abort();
1265 }
1266 }
1267
1268 static enum glsl_base_type
1269 base_type_for_alu_type(nir_alu_type type)
1270 {
1271 type = nir_alu_type_get_base_type(type);
1272
1273 switch (type) {
1274 case nir_type_float:
1275 return GLSL_TYPE_FLOAT;
1276 case nir_type_int:
1277 return GLSL_TYPE_INT;
1278 case nir_type_uint:
1279 return GLSL_TYPE_UINT;
1280 default:
1281 unreachable("invalid type");
1282 }
1283 }
1284
1285 static nir_variable *
1286 get_sampler_var(struct ttn_compile *c, int binding,
1287 enum glsl_sampler_dim dim,
1288 bool is_shadow,
1289 bool is_array,
1290 enum glsl_base_type base_type)
1291 {
1292 nir_variable *var = c->samplers[binding];
1293 if (!var) {
1294 const struct glsl_type *type =
1295 glsl_sampler_type(dim, is_shadow, is_array, base_type);
1296 var = nir_variable_create(c->build.shader, nir_var_uniform, type,
1297 "sampler");
1298 var->data.binding = binding;
1299 var->data.explicit_binding = true;
1300 c->samplers[binding] = var;
1301 }
1302
1303 return var;
1304 }
1305
1306 static nir_variable *
1307 get_image_var(struct ttn_compile *c, int binding,
1308 enum glsl_sampler_dim dim,
1309 bool is_array,
1310 enum glsl_base_type base_type,
1311 enum gl_access_qualifier access,
1312 GLenum format)
1313 {
1314 nir_variable *var = c->images[binding];
1315
1316 if (!var) {
1317 const struct glsl_type *type = glsl_image_type(dim, is_array, base_type);
1318
1319 var = nir_variable_create(c->build.shader, nir_var_uniform, type, "image");
1320 var->data.binding = binding;
1321 var->data.explicit_binding = true;
1322 var->data.image.access = access;
1323 var->data.image.format = format;
1324 c->images[binding] = var;
1325 }
1326
1327 return var;
1328 }
1329
1330 static void
1331 add_ssbo_var(struct ttn_compile *c, int binding)
1332 {
1333 nir_variable *var = c->ssbo[binding];
1334
1335 if (!var) {
1336 /* A length of 0 is used to denote unsized arrays */
1337 const struct glsl_type *type = glsl_array_type(glsl_uint_type(), 0, 0);
1338
1339 struct glsl_struct_field field = {
1340 .type = type,
1341 .name = "data",
1342 .location = -1,
1343 };
1344
1345 var = nir_variable_create(c->build.shader, nir_var_mem_ssbo, type, "ssbo");
1346 var->data.binding = binding;
1347 var->interface_type =
1348 glsl_interface_type(&field, 1, GLSL_INTERFACE_PACKING_STD430,
1349 false, "data");
1350 c->ssbo[binding] = var;
1351 }
1352 }
1353
1354 static void
1355 ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1356 {
1357 nir_builder *b = &c->build;
1358 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1359 nir_tex_instr *instr;
1360 nir_texop op;
1361 unsigned num_srcs, samp = 1, sview, i;
1362
1363 switch (tgsi_inst->Instruction.Opcode) {
1364 case TGSI_OPCODE_TEX:
1365 op = nir_texop_tex;
1366 num_srcs = 1;
1367 break;
1368 case TGSI_OPCODE_TEX2:
1369 op = nir_texop_tex;
1370 num_srcs = 1;
1371 samp = 2;
1372 break;
1373 case TGSI_OPCODE_TXP:
1374 op = nir_texop_tex;
1375 num_srcs = 2;
1376 break;
1377 case TGSI_OPCODE_TXB:
1378 op = nir_texop_txb;
1379 num_srcs = 2;
1380 break;
1381 case TGSI_OPCODE_TXB2:
1382 op = nir_texop_txb;
1383 num_srcs = 2;
1384 samp = 2;
1385 break;
1386 case TGSI_OPCODE_TXL:
1387 case TGSI_OPCODE_TEX_LZ:
1388 op = nir_texop_txl;
1389 num_srcs = 2;
1390 break;
1391 case TGSI_OPCODE_TXL2:
1392 op = nir_texop_txl;
1393 num_srcs = 2;
1394 samp = 2;
1395 break;
1396 case TGSI_OPCODE_TXF:
1397 case TGSI_OPCODE_TXF_LZ:
1398 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
1399 tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1400 op = nir_texop_txf_ms;
1401 } else {
1402 op = nir_texop_txf;
1403 }
1404 num_srcs = 2;
1405 break;
1406 case TGSI_OPCODE_TXD:
1407 op = nir_texop_txd;
1408 num_srcs = 3;
1409 samp = 3;
1410 break;
1411 case TGSI_OPCODE_LODQ:
1412 op = nir_texop_lod;
1413 num_srcs = 1;
1414 break;
1415
1416 default:
1417 fprintf(stderr, "unknown TGSI tex op %d\n", tgsi_inst->Instruction.Opcode);
1418 abort();
1419 }
1420
1421 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
1422 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1423 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
1424 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1425 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
1426 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
1427 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1428 num_srcs++;
1429 }
1430
1431 /* Deref sources */
1432 num_srcs += 2;
1433
1434 num_srcs += tgsi_inst->Texture.NumOffsets;
1435
1436 instr = nir_tex_instr_create(b->shader, num_srcs);
1437 instr->op = op;
1438
1439 get_texture_info(tgsi_inst->Texture.Texture,
1440 &instr->sampler_dim, &instr->is_shadow, &instr->is_array);
1441
1442 switch (instr->sampler_dim) {
1443 case GLSL_SAMPLER_DIM_1D:
1444 case GLSL_SAMPLER_DIM_BUF:
1445 instr->coord_components = 1;
1446 break;
1447 case GLSL_SAMPLER_DIM_2D:
1448 case GLSL_SAMPLER_DIM_RECT:
1449 case GLSL_SAMPLER_DIM_EXTERNAL:
1450 case GLSL_SAMPLER_DIM_MS:
1451 instr->coord_components = 2;
1452 break;
1453 case GLSL_SAMPLER_DIM_3D:
1454 case GLSL_SAMPLER_DIM_CUBE:
1455 instr->coord_components = 3;
1456 break;
1457 case GLSL_SAMPLER_DIM_SUBPASS:
1458 case GLSL_SAMPLER_DIM_SUBPASS_MS:
1459 unreachable("invalid sampler_dim");
1460 }
1461
1462 if (instr->is_array)
1463 instr->coord_components++;
1464
1465 assert(tgsi_inst->Src[samp].Register.File == TGSI_FILE_SAMPLER);
1466
1467 /* TODO if we supported any opc's which take an explicit SVIEW
1468 * src, we would use that here instead. But for the "legacy"
1469 * texture opc's the SVIEW index is same as SAMP index:
1470 */
1471 sview = tgsi_inst->Src[samp].Register.Index;
1472
1473 if (op == nir_texop_lod) {
1474 instr->dest_type = nir_type_float;
1475 } else if (sview < c->num_samp_types) {
1476 instr->dest_type = c->samp_types[sview];
1477 } else {
1478 instr->dest_type = nir_type_float;
1479 }
1480
1481 nir_variable *var =
1482 get_sampler_var(c, sview, instr->sampler_dim,
1483 instr->is_shadow,
1484 instr->is_array,
1485 base_type_for_alu_type(instr->dest_type));
1486
1487 nir_deref_instr *deref = nir_build_deref_var(b, var);
1488
1489 unsigned src_number = 0;
1490
1491 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1492 instr->src[src_number].src_type = nir_tex_src_texture_deref;
1493 src_number++;
1494 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1495 instr->src[src_number].src_type = nir_tex_src_sampler_deref;
1496 src_number++;
1497
1498 instr->src[src_number].src =
1499 nir_src_for_ssa(nir_swizzle(b, src[0], SWIZ(X, Y, Z, W),
1500 instr->coord_components));
1501 instr->src[src_number].src_type = nir_tex_src_coord;
1502 src_number++;
1503
1504 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1505 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1506 instr->src[src_number].src_type = nir_tex_src_projector;
1507 src_number++;
1508 }
1509
1510 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
1511 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1512 instr->src[src_number].src_type = nir_tex_src_bias;
1513 src_number++;
1514 }
1515
1516 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB2) {
1517 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1518 instr->src[src_number].src_type = nir_tex_src_bias;
1519 src_number++;
1520 }
1521
1522 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
1523 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ) {
1524 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ)
1525 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1526 else
1527 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1528 instr->src[src_number].src_type = nir_tex_src_lod;
1529 src_number++;
1530 }
1531
1532 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
1533 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1534 instr->src[src_number].src_type = nir_tex_src_lod;
1535 src_number++;
1536 }
1537
1538 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF ||
1539 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ) {
1540 if (op == nir_texop_txf_ms) {
1541 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1542 instr->src[src_number].src_type = nir_tex_src_ms_index;
1543 } else {
1544 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ)
1545 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1546 else
1547 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1548 instr->src[src_number].src_type = nir_tex_src_lod;
1549 }
1550 src_number++;
1551 }
1552
1553 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
1554 instr->src[src_number].src_type = nir_tex_src_ddx;
1555 instr->src[src_number].src =
1556 nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1557 nir_tex_instr_src_size(instr, src_number)));
1558 src_number++;
1559 instr->src[src_number].src_type = nir_tex_src_ddy;
1560 instr->src[src_number].src =
1561 nir_src_for_ssa(nir_swizzle(b, src[2], SWIZ(X, Y, Z, W),
1562 nir_tex_instr_src_size(instr, src_number)));
1563 src_number++;
1564 }
1565
1566 if (instr->is_shadow) {
1567 if (instr->coord_components == 4)
1568 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1569 else if (instr->coord_components == 3)
1570 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1571 else
1572 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], Z));
1573
1574 instr->src[src_number].src_type = nir_tex_src_comparator;
1575 src_number++;
1576 }
1577
1578 for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) {
1579 struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i];
1580 /* since TexOffset ins't using tgsi_full_src_register we get to
1581 * do some extra gymnastics:
1582 */
1583 nir_alu_src src;
1584
1585 memset(&src, 0, sizeof(src));
1586
1587 src.src = ttn_src_for_file_and_index(c,
1588 tex_offset->File,
1589 tex_offset->Index,
1590 NULL, NULL, NULL,
1591 true);
1592
1593 src.swizzle[0] = tex_offset->SwizzleX;
1594 src.swizzle[1] = tex_offset->SwizzleY;
1595 src.swizzle[2] = tex_offset->SwizzleZ;
1596 src.swizzle[3] = TGSI_SWIZZLE_W;
1597
1598 instr->src[src_number].src_type = nir_tex_src_offset;
1599 instr->src[src_number].src = nir_src_for_ssa(
1600 nir_mov_alu(b, src, nir_tex_instr_src_size(instr, src_number)));
1601 src_number++;
1602 }
1603
1604 assert(src_number == num_srcs);
1605 assert(src_number == instr->num_srcs);
1606
1607 nir_ssa_dest_init(&instr->instr, &instr->dest,
1608 nir_tex_instr_dest_size(instr),
1609 32, NULL);
1610 nir_builder_instr_insert(b, &instr->instr);
1611
1612 /* Resolve the writemask on the texture op. */
1613 ttn_move_dest(b, dest, &instr->dest.ssa);
1614 }
1615
1616 /* TGSI_OPCODE_TXQ is actually two distinct operations:
1617 *
1618 * dst.x = texture\_width(unit, lod)
1619 * dst.y = texture\_height(unit, lod)
1620 * dst.z = texture\_depth(unit, lod)
1621 * dst.w = texture\_levels(unit)
1622 *
1623 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels
1624 */
1625 static void
1626 ttn_txq(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1627 {
1628 nir_builder *b = &c->build;
1629 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1630 nir_tex_instr *txs, *qlv;
1631
1632 txs = nir_tex_instr_create(b->shader, 2);
1633 txs->op = nir_texop_txs;
1634 get_texture_info(tgsi_inst->Texture.Texture,
1635 &txs->sampler_dim, &txs->is_shadow, &txs->is_array);
1636
1637 qlv = nir_tex_instr_create(b->shader, 1);
1638 qlv->op = nir_texop_query_levels;
1639 get_texture_info(tgsi_inst->Texture.Texture,
1640 &qlv->sampler_dim, &qlv->is_shadow, &qlv->is_array);
1641
1642 assert(tgsi_inst->Src[1].Register.File == TGSI_FILE_SAMPLER);
1643 int tex_index = tgsi_inst->Src[1].Register.Index;
1644
1645 nir_variable *var =
1646 get_sampler_var(c, tex_index, txs->sampler_dim,
1647 txs->is_shadow,
1648 txs->is_array,
1649 base_type_for_alu_type(txs->dest_type));
1650
1651 nir_deref_instr *deref = nir_build_deref_var(b, var);
1652
1653 txs->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1654 txs->src[0].src_type = nir_tex_src_texture_deref;
1655
1656 qlv->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1657 qlv->src[0].src_type = nir_tex_src_texture_deref;
1658
1659 /* lod: */
1660 txs->src[1].src = nir_src_for_ssa(ttn_channel(b, src[0], X));
1661 txs->src[1].src_type = nir_tex_src_lod;
1662
1663 nir_ssa_dest_init(&txs->instr, &txs->dest,
1664 nir_tex_instr_dest_size(txs), 32, NULL);
1665 nir_builder_instr_insert(b, &txs->instr);
1666
1667 nir_ssa_dest_init(&qlv->instr, &qlv->dest, 1, 32, NULL);
1668 nir_builder_instr_insert(b, &qlv->instr);
1669
1670 ttn_move_dest_masked(b, dest, &txs->dest.ssa, TGSI_WRITEMASK_XYZ);
1671 ttn_move_dest_masked(b, dest, &qlv->dest.ssa, TGSI_WRITEMASK_W);
1672 }
1673
1674 static enum glsl_base_type
1675 get_image_base_type(struct tgsi_full_instruction *tgsi_inst)
1676 {
1677 const struct util_format_description *desc =
1678 util_format_description(tgsi_inst->Memory.Format);
1679
1680 if (desc->channel[0].pure_integer) {
1681 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED)
1682 return GLSL_TYPE_INT;
1683 else
1684 return GLSL_TYPE_UINT;
1685 }
1686 return GLSL_TYPE_FLOAT;
1687 }
1688
1689 static enum gl_access_qualifier
1690 get_mem_qualifier(struct tgsi_full_instruction *tgsi_inst)
1691 {
1692 enum gl_access_qualifier access = 0;
1693
1694 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_COHERENT)
1695 access |= ACCESS_COHERENT;
1696 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT)
1697 access |= ACCESS_RESTRICT;
1698 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
1699 access |= ACCESS_VOLATILE;
1700 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
1701 access |= ACCESS_STREAM_CACHE_POLICY;
1702
1703 return access;
1704 }
1705
1706 static GLenum
1707 get_image_format(struct tgsi_full_instruction *tgsi_inst)
1708 {
1709 switch (tgsi_inst->Memory.Format) {
1710 case PIPE_FORMAT_R8_UNORM:
1711 return GL_R8;
1712 case PIPE_FORMAT_R8G8_UNORM:
1713 return GL_RG8;
1714 case PIPE_FORMAT_R8G8B8A8_UNORM:
1715 return GL_RGBA8;
1716 case PIPE_FORMAT_R16_UNORM:
1717 return GL_R16;
1718 case PIPE_FORMAT_R16G16_UNORM:
1719 return GL_RG16;
1720 case PIPE_FORMAT_R16G16B16A16_UNORM:
1721 return GL_RGBA16;
1722
1723 case PIPE_FORMAT_R8_SNORM:
1724 return GL_R8_SNORM;
1725 case PIPE_FORMAT_R8G8_SNORM:
1726 return GL_RG8_SNORM;
1727 case PIPE_FORMAT_R8G8B8A8_SNORM:
1728 return GL_RGBA8_SNORM;
1729 case PIPE_FORMAT_R16_SNORM:
1730 return GL_R16_SNORM;
1731 case PIPE_FORMAT_R16G16_SNORM:
1732 return GL_RG16_SNORM;
1733 case PIPE_FORMAT_R16G16B16A16_SNORM:
1734 return GL_RGBA16_SNORM;
1735
1736 case PIPE_FORMAT_R8_UINT:
1737 return GL_R8UI;
1738 case PIPE_FORMAT_R8G8_UINT:
1739 return GL_RG8UI;
1740 case PIPE_FORMAT_R8G8B8A8_UINT:
1741 return GL_RGBA8UI;
1742 case PIPE_FORMAT_R16_UINT:
1743 return GL_R16UI;
1744 case PIPE_FORMAT_R16G16_UINT:
1745 return GL_RG16UI;
1746 case PIPE_FORMAT_R16G16B16A16_UINT:
1747 return GL_RGBA16UI;
1748 case PIPE_FORMAT_R32_UINT:
1749 return GL_R32UI;
1750 case PIPE_FORMAT_R32G32_UINT:
1751 return GL_RG32UI;
1752 case PIPE_FORMAT_R32G32B32A32_UINT:
1753 return GL_RGBA32UI;
1754
1755 case PIPE_FORMAT_R8_SINT:
1756 return GL_R8I;
1757 case PIPE_FORMAT_R8G8_SINT:
1758 return GL_RG8I;
1759 case PIPE_FORMAT_R8G8B8A8_SINT:
1760 return GL_RGBA8I;
1761 case PIPE_FORMAT_R16_SINT:
1762 return GL_R16I;
1763 case PIPE_FORMAT_R16G16_SINT:
1764 return GL_RG16I;
1765 case PIPE_FORMAT_R16G16B16A16_SINT:
1766 return GL_RGBA16I;
1767 case PIPE_FORMAT_R32_SINT:
1768 return GL_R32I;
1769 case PIPE_FORMAT_R32G32_SINT:
1770 return GL_RG32I;
1771 case PIPE_FORMAT_R32G32B32A32_SINT:
1772 return GL_RGBA32I;
1773
1774 case PIPE_FORMAT_R16_FLOAT:
1775 return GL_R16F;
1776 case PIPE_FORMAT_R16G16_FLOAT:
1777 return GL_RG16F;
1778 case PIPE_FORMAT_R16G16B16A16_FLOAT:
1779 return GL_RGBA16F;
1780 case PIPE_FORMAT_R32_FLOAT:
1781 return GL_R32F;
1782 case PIPE_FORMAT_R32G32_FLOAT:
1783 return GL_RG32F;
1784 case PIPE_FORMAT_R32G32B32A32_FLOAT:
1785 return GL_RGBA32F;
1786
1787 case PIPE_FORMAT_R11G11B10_FLOAT:
1788 return GL_R11F_G11F_B10F;
1789 case PIPE_FORMAT_R10G10B10A2_UINT:
1790 return GL_RGB10_A2UI;
1791 case PIPE_FORMAT_R10G10B10A2_UNORM:
1792 return GL_RGB10_A2;
1793
1794 default:
1795 unreachable("unhandled image format");
1796 }
1797 }
1798
1799 static void
1800 ttn_mem(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1801 {
1802 nir_builder *b = &c->build;
1803 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1804 nir_intrinsic_instr *instr = NULL;
1805 unsigned resource_index, addr_src_index, file;
1806
1807 switch (tgsi_inst->Instruction.Opcode) {
1808 case TGSI_OPCODE_LOAD:
1809 assert(!tgsi_inst->Src[0].Register.Indirect);
1810 resource_index = tgsi_inst->Src[0].Register.Index;
1811 file = tgsi_inst->Src[0].Register.File;
1812 addr_src_index = 1;
1813 break;
1814 case TGSI_OPCODE_STORE:
1815 assert(!tgsi_inst->Dst[0].Register.Indirect);
1816 resource_index = tgsi_inst->Dst[0].Register.Index;
1817 file = tgsi_inst->Dst[0].Register.File;
1818 addr_src_index = 0;
1819 break;
1820 default:
1821 unreachable("unexpected memory opcode");
1822 }
1823
1824 if (file == TGSI_FILE_BUFFER) {
1825 nir_intrinsic_op op;
1826
1827 switch (tgsi_inst->Instruction.Opcode) {
1828 case TGSI_OPCODE_LOAD:
1829 op = nir_intrinsic_load_ssbo;
1830 break;
1831 case TGSI_OPCODE_STORE:
1832 op = nir_intrinsic_store_ssbo;
1833 break;
1834 }
1835
1836 add_ssbo_var(c, resource_index);
1837
1838 instr = nir_intrinsic_instr_create(b->shader, op);
1839 instr->num_components = util_last_bit(tgsi_inst->Dst[0].Register.WriteMask);
1840 nir_intrinsic_set_access(instr, get_mem_qualifier(tgsi_inst));
1841 nir_intrinsic_set_align(instr, 4, 0);
1842
1843 unsigned i = 0;
1844 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1845 instr->src[i++] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1846 instr->num_components));
1847 instr->src[i++] = nir_src_for_ssa(nir_imm_int(b, resource_index));
1848 instr->src[i++] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], X));
1849
1850 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1851 nir_intrinsic_set_write_mask(instr, tgsi_inst->Dst[0].Register.WriteMask);
1852
1853 } else if (file == TGSI_FILE_IMAGE) {
1854 nir_intrinsic_op op;
1855
1856 switch (tgsi_inst->Instruction.Opcode) {
1857 case TGSI_OPCODE_LOAD:
1858 op = nir_intrinsic_image_deref_load;
1859 break;
1860 case TGSI_OPCODE_STORE:
1861 op = nir_intrinsic_image_deref_store;
1862 break;
1863 }
1864
1865 instr = nir_intrinsic_instr_create(b->shader, op);
1866
1867 /* Set the image variable dereference. */
1868 enum glsl_sampler_dim dim;
1869 bool is_array;
1870 get_texture_info(tgsi_inst->Memory.Texture, &dim, NULL, &is_array);
1871
1872 enum glsl_base_type base_type = get_image_base_type(tgsi_inst);
1873 enum gl_access_qualifier access = get_mem_qualifier(tgsi_inst);
1874 GLenum format = get_image_format(tgsi_inst);
1875
1876 nir_variable *image =
1877 get_image_var(c, resource_index,
1878 dim, is_array, base_type, access, format);
1879 nir_deref_instr *image_deref = nir_build_deref_var(b, image);
1880 const struct glsl_type *type = image_deref->type;
1881 unsigned coord_components = glsl_get_sampler_coordinate_components(type);
1882
1883 nir_intrinsic_set_access(instr, image_deref->var->data.image.access);
1884
1885 instr->src[0] = nir_src_for_ssa(&image_deref->dest.ssa);
1886 instr->src[1] = nir_src_for_ssa(nir_swizzle(b, src[addr_src_index],
1887 SWIZ(X, Y, Z, W),
1888 coord_components));
1889
1890 /* Set the sample argument, which is undefined for single-sample images. */
1891 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_MS) {
1892 instr->src[2] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], W));
1893 } else {
1894 instr->src[2] = nir_src_for_ssa(nir_ssa_undef(b, 1, 32));
1895 }
1896
1897 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
1898 instr->src[3] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W), 4));
1899 }
1900
1901 instr->num_components = 4;
1902 } else {
1903 unreachable("unexpected file");
1904 }
1905
1906
1907 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_LOAD) {
1908 nir_ssa_dest_init(&instr->instr, &instr->dest,
1909 util_last_bit(tgsi_inst->Dst[0].Register.WriteMask),
1910 32, NULL);
1911 nir_builder_instr_insert(b, &instr->instr);
1912 ttn_move_dest(b, dest, &instr->dest.ssa);
1913 } else {
1914 nir_builder_instr_insert(b, &instr->instr);
1915 }
1916 }
1917
1918 static const nir_op op_trans[TGSI_OPCODE_LAST] = {
1919 [TGSI_OPCODE_ARL] = 0,
1920 [TGSI_OPCODE_MOV] = nir_op_mov,
1921 [TGSI_OPCODE_LIT] = 0,
1922 [TGSI_OPCODE_RCP] = nir_op_frcp,
1923 [TGSI_OPCODE_RSQ] = nir_op_frsq,
1924 [TGSI_OPCODE_EXP] = 0,
1925 [TGSI_OPCODE_LOG] = 0,
1926 [TGSI_OPCODE_MUL] = nir_op_fmul,
1927 [TGSI_OPCODE_ADD] = nir_op_fadd,
1928 [TGSI_OPCODE_DP3] = 0,
1929 [TGSI_OPCODE_DP4] = 0,
1930 [TGSI_OPCODE_DST] = 0,
1931 [TGSI_OPCODE_MIN] = nir_op_fmin,
1932 [TGSI_OPCODE_MAX] = nir_op_fmax,
1933 [TGSI_OPCODE_SLT] = nir_op_slt,
1934 [TGSI_OPCODE_SGE] = nir_op_sge,
1935 [TGSI_OPCODE_MAD] = nir_op_ffma,
1936 [TGSI_OPCODE_TEX_LZ] = 0,
1937 [TGSI_OPCODE_LRP] = 0,
1938 [TGSI_OPCODE_SQRT] = nir_op_fsqrt,
1939 [TGSI_OPCODE_FRC] = nir_op_ffract,
1940 [TGSI_OPCODE_TXF_LZ] = 0,
1941 [TGSI_OPCODE_FLR] = nir_op_ffloor,
1942 [TGSI_OPCODE_ROUND] = nir_op_fround_even,
1943 [TGSI_OPCODE_EX2] = nir_op_fexp2,
1944 [TGSI_OPCODE_LG2] = nir_op_flog2,
1945 [TGSI_OPCODE_POW] = nir_op_fpow,
1946 [TGSI_OPCODE_COS] = nir_op_fcos,
1947 [TGSI_OPCODE_DDX] = nir_op_fddx,
1948 [TGSI_OPCODE_DDY] = nir_op_fddy,
1949 [TGSI_OPCODE_KILL] = 0,
1950 [TGSI_OPCODE_PK2H] = 0, /* XXX */
1951 [TGSI_OPCODE_PK2US] = 0, /* XXX */
1952 [TGSI_OPCODE_PK4B] = 0, /* XXX */
1953 [TGSI_OPCODE_PK4UB] = 0, /* XXX */
1954 [TGSI_OPCODE_SEQ] = nir_op_seq,
1955 [TGSI_OPCODE_SGT] = 0,
1956 [TGSI_OPCODE_SIN] = nir_op_fsin,
1957 [TGSI_OPCODE_SNE] = nir_op_sne,
1958 [TGSI_OPCODE_SLE] = 0,
1959 [TGSI_OPCODE_TEX] = 0,
1960 [TGSI_OPCODE_TXD] = 0,
1961 [TGSI_OPCODE_TXP] = 0,
1962 [TGSI_OPCODE_UP2H] = 0, /* XXX */
1963 [TGSI_OPCODE_UP2US] = 0, /* XXX */
1964 [TGSI_OPCODE_UP4B] = 0, /* XXX */
1965 [TGSI_OPCODE_UP4UB] = 0, /* XXX */
1966 [TGSI_OPCODE_ARR] = 0,
1967
1968 /* No function calls, yet. */
1969 [TGSI_OPCODE_CAL] = 0, /* XXX */
1970 [TGSI_OPCODE_RET] = 0, /* XXX */
1971
1972 [TGSI_OPCODE_SSG] = nir_op_fsign,
1973 [TGSI_OPCODE_CMP] = 0,
1974 [TGSI_OPCODE_TXB] = 0,
1975 [TGSI_OPCODE_DIV] = nir_op_fdiv,
1976 [TGSI_OPCODE_DP2] = 0,
1977 [TGSI_OPCODE_TXL] = 0,
1978
1979 [TGSI_OPCODE_BRK] = 0,
1980 [TGSI_OPCODE_IF] = 0,
1981 [TGSI_OPCODE_UIF] = 0,
1982 [TGSI_OPCODE_ELSE] = 0,
1983 [TGSI_OPCODE_ENDIF] = 0,
1984
1985 [TGSI_OPCODE_DDX_FINE] = nir_op_fddx_fine,
1986 [TGSI_OPCODE_DDY_FINE] = nir_op_fddy_fine,
1987
1988 [TGSI_OPCODE_CEIL] = nir_op_fceil,
1989 [TGSI_OPCODE_I2F] = nir_op_i2f32,
1990 [TGSI_OPCODE_NOT] = nir_op_inot,
1991 [TGSI_OPCODE_TRUNC] = nir_op_ftrunc,
1992 [TGSI_OPCODE_SHL] = nir_op_ishl,
1993 [TGSI_OPCODE_AND] = nir_op_iand,
1994 [TGSI_OPCODE_OR] = nir_op_ior,
1995 [TGSI_OPCODE_MOD] = nir_op_umod,
1996 [TGSI_OPCODE_XOR] = nir_op_ixor,
1997 [TGSI_OPCODE_TXF] = 0,
1998 [TGSI_OPCODE_TXQ] = 0,
1999
2000 [TGSI_OPCODE_CONT] = 0,
2001
2002 [TGSI_OPCODE_EMIT] = 0, /* XXX */
2003 [TGSI_OPCODE_ENDPRIM] = 0, /* XXX */
2004
2005 [TGSI_OPCODE_BGNLOOP] = 0,
2006 [TGSI_OPCODE_BGNSUB] = 0, /* XXX: no function calls */
2007 [TGSI_OPCODE_ENDLOOP] = 0,
2008 [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */
2009
2010 [TGSI_OPCODE_NOP] = 0,
2011 [TGSI_OPCODE_FSEQ] = nir_op_feq,
2012 [TGSI_OPCODE_FSGE] = nir_op_fge,
2013 [TGSI_OPCODE_FSLT] = nir_op_flt,
2014 [TGSI_OPCODE_FSNE] = nir_op_fne,
2015
2016 [TGSI_OPCODE_KILL_IF] = 0,
2017
2018 [TGSI_OPCODE_END] = 0,
2019
2020 [TGSI_OPCODE_F2I] = nir_op_f2i32,
2021 [TGSI_OPCODE_IDIV] = nir_op_idiv,
2022 [TGSI_OPCODE_IMAX] = nir_op_imax,
2023 [TGSI_OPCODE_IMIN] = nir_op_imin,
2024 [TGSI_OPCODE_INEG] = nir_op_ineg,
2025 [TGSI_OPCODE_ISGE] = nir_op_ige,
2026 [TGSI_OPCODE_ISHR] = nir_op_ishr,
2027 [TGSI_OPCODE_ISLT] = nir_op_ilt,
2028 [TGSI_OPCODE_F2U] = nir_op_f2u32,
2029 [TGSI_OPCODE_U2F] = nir_op_u2f32,
2030 [TGSI_OPCODE_UADD] = nir_op_iadd,
2031 [TGSI_OPCODE_UDIV] = nir_op_udiv,
2032 [TGSI_OPCODE_UMAD] = 0,
2033 [TGSI_OPCODE_UMAX] = nir_op_umax,
2034 [TGSI_OPCODE_UMIN] = nir_op_umin,
2035 [TGSI_OPCODE_UMOD] = nir_op_umod,
2036 [TGSI_OPCODE_UMUL] = nir_op_imul,
2037 [TGSI_OPCODE_USEQ] = nir_op_ieq,
2038 [TGSI_OPCODE_USGE] = nir_op_uge,
2039 [TGSI_OPCODE_USHR] = nir_op_ushr,
2040 [TGSI_OPCODE_USLT] = nir_op_ult,
2041 [TGSI_OPCODE_USNE] = nir_op_ine,
2042
2043 [TGSI_OPCODE_SWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
2044 [TGSI_OPCODE_CASE] = 0, /* not emitted by glsl_to_tgsi.cpp */
2045 [TGSI_OPCODE_DEFAULT] = 0, /* not emitted by glsl_to_tgsi.cpp */
2046 [TGSI_OPCODE_ENDSWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
2047
2048 /* XXX: SAMPLE opcodes */
2049
2050 [TGSI_OPCODE_UARL] = nir_op_mov,
2051 [TGSI_OPCODE_UCMP] = 0,
2052 [TGSI_OPCODE_IABS] = nir_op_iabs,
2053 [TGSI_OPCODE_ISSG] = nir_op_isign,
2054
2055 [TGSI_OPCODE_LOAD] = 0,
2056 [TGSI_OPCODE_STORE] = 0,
2057
2058 /* XXX: atomics */
2059
2060 [TGSI_OPCODE_TEX2] = 0,
2061 [TGSI_OPCODE_TXB2] = 0,
2062 [TGSI_OPCODE_TXL2] = 0,
2063
2064 [TGSI_OPCODE_IMUL_HI] = nir_op_imul_high,
2065 [TGSI_OPCODE_UMUL_HI] = nir_op_umul_high,
2066
2067 [TGSI_OPCODE_TG4] = 0,
2068 [TGSI_OPCODE_LODQ] = 0,
2069
2070 [TGSI_OPCODE_IBFE] = nir_op_ibitfield_extract,
2071 [TGSI_OPCODE_UBFE] = nir_op_ubitfield_extract,
2072 [TGSI_OPCODE_BFI] = nir_op_bitfield_insert,
2073 [TGSI_OPCODE_BREV] = nir_op_bitfield_reverse,
2074 [TGSI_OPCODE_POPC] = nir_op_bit_count,
2075 [TGSI_OPCODE_LSB] = nir_op_find_lsb,
2076 [TGSI_OPCODE_IMSB] = nir_op_ifind_msb,
2077 [TGSI_OPCODE_UMSB] = nir_op_ufind_msb,
2078
2079 [TGSI_OPCODE_INTERP_CENTROID] = 0, /* XXX */
2080 [TGSI_OPCODE_INTERP_SAMPLE] = 0, /* XXX */
2081 [TGSI_OPCODE_INTERP_OFFSET] = 0, /* XXX */
2082
2083 [TGSI_OPCODE_F2D] = nir_op_f2f64,
2084 [TGSI_OPCODE_D2F] = nir_op_f2f32,
2085 [TGSI_OPCODE_DMUL] = nir_op_fmul,
2086 [TGSI_OPCODE_D2U] = nir_op_f2u32,
2087 [TGSI_OPCODE_U2D] = nir_op_u2f64,
2088
2089 [TGSI_OPCODE_U64ADD] = nir_op_iadd,
2090 [TGSI_OPCODE_U64MUL] = nir_op_imul,
2091 [TGSI_OPCODE_U64DIV] = nir_op_udiv,
2092 [TGSI_OPCODE_U64SNE] = nir_op_ine,
2093 };
2094
2095 static void
2096 ttn_emit_instruction(struct ttn_compile *c)
2097 {
2098 nir_builder *b = &c->build;
2099 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
2100 unsigned i;
2101 unsigned tgsi_op = tgsi_inst->Instruction.Opcode;
2102 struct tgsi_full_dst_register *tgsi_dst = &tgsi_inst->Dst[0];
2103
2104 if (tgsi_op == TGSI_OPCODE_END)
2105 return;
2106
2107 nir_ssa_def *src[TGSI_FULL_MAX_SRC_REGISTERS];
2108 for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) {
2109 src[i] = ttn_get_src(c, &tgsi_inst->Src[i], i);
2110 }
2111 nir_alu_dest dest = ttn_get_dest(c, tgsi_dst);
2112
2113 unsigned tgsi_dst_type = tgsi_opcode_infer_dst_type(tgsi_op, 0);
2114
2115 /* The destination bitsize of the NIR opcode (not TGSI, where it's always
2116 * 32 bits). This needs to be passed into ttn_alu() because it can't be
2117 * inferred for comparison opcodes.
2118 */
2119 unsigned dst_bitsize = tgsi_type_is_64bit(tgsi_dst_type) ? 64 : 32;
2120
2121 switch (tgsi_op) {
2122 case TGSI_OPCODE_RSQ:
2123 ttn_move_dest(b, dest, nir_frsq(b, ttn_channel(b, src[0], X)));
2124 break;
2125
2126 case TGSI_OPCODE_SQRT:
2127 ttn_move_dest(b, dest, nir_fsqrt(b, ttn_channel(b, src[0], X)));
2128 break;
2129
2130 case TGSI_OPCODE_RCP:
2131 ttn_move_dest(b, dest, nir_frcp(b, ttn_channel(b, src[0], X)));
2132 break;
2133
2134 case TGSI_OPCODE_EX2:
2135 ttn_move_dest(b, dest, nir_fexp2(b, ttn_channel(b, src[0], X)));
2136 break;
2137
2138 case TGSI_OPCODE_LG2:
2139 ttn_move_dest(b, dest, nir_flog2(b, ttn_channel(b, src[0], X)));
2140 break;
2141
2142 case TGSI_OPCODE_POW:
2143 ttn_move_dest(b, dest, nir_fpow(b,
2144 ttn_channel(b, src[0], X),
2145 ttn_channel(b, src[1], X)));
2146 break;
2147
2148 case TGSI_OPCODE_COS:
2149 ttn_move_dest(b, dest, nir_fcos(b, ttn_channel(b, src[0], X)));
2150 break;
2151
2152 case TGSI_OPCODE_SIN:
2153 ttn_move_dest(b, dest, nir_fsin(b, ttn_channel(b, src[0], X)));
2154 break;
2155
2156 case TGSI_OPCODE_ARL:
2157 ttn_arl(b, op_trans[tgsi_op], dest, src);
2158 break;
2159
2160 case TGSI_OPCODE_EXP:
2161 ttn_exp(b, op_trans[tgsi_op], dest, src);
2162 break;
2163
2164 case TGSI_OPCODE_LOG:
2165 ttn_log(b, op_trans[tgsi_op], dest, src);
2166 break;
2167
2168 case TGSI_OPCODE_DST:
2169 ttn_dst(b, op_trans[tgsi_op], dest, src);
2170 break;
2171
2172 case TGSI_OPCODE_LIT:
2173 ttn_lit(b, op_trans[tgsi_op], dest, src);
2174 break;
2175
2176 case TGSI_OPCODE_DP2:
2177 ttn_dp2(b, op_trans[tgsi_op], dest, src);
2178 break;
2179
2180 case TGSI_OPCODE_DP3:
2181 ttn_dp3(b, op_trans[tgsi_op], dest, src);
2182 break;
2183
2184 case TGSI_OPCODE_DP4:
2185 ttn_dp4(b, op_trans[tgsi_op], dest, src);
2186 break;
2187
2188 case TGSI_OPCODE_UMAD:
2189 ttn_umad(b, op_trans[tgsi_op], dest, src);
2190 break;
2191
2192 case TGSI_OPCODE_LRP:
2193 ttn_move_dest(b, dest, nir_flrp(b, src[2], src[1], src[0]));
2194 break;
2195
2196 case TGSI_OPCODE_KILL:
2197 ttn_kill(b, op_trans[tgsi_op], dest, src);
2198 break;
2199
2200 case TGSI_OPCODE_ARR:
2201 ttn_arr(b, op_trans[tgsi_op], dest, src);
2202 break;
2203
2204 case TGSI_OPCODE_CMP:
2205 ttn_cmp(b, op_trans[tgsi_op], dest, src);
2206 break;
2207
2208 case TGSI_OPCODE_UCMP:
2209 ttn_ucmp(b, op_trans[tgsi_op], dest, src);
2210 break;
2211
2212 case TGSI_OPCODE_SGT:
2213 ttn_sgt(b, op_trans[tgsi_op], dest, src);
2214 break;
2215
2216 case TGSI_OPCODE_SLE:
2217 ttn_sle(b, op_trans[tgsi_op], dest, src);
2218 break;
2219
2220 case TGSI_OPCODE_KILL_IF:
2221 ttn_kill_if(b, op_trans[tgsi_op], dest, src);
2222 break;
2223
2224 case TGSI_OPCODE_TEX:
2225 case TGSI_OPCODE_TEX_LZ:
2226 case TGSI_OPCODE_TXP:
2227 case TGSI_OPCODE_TXL:
2228 case TGSI_OPCODE_TXB:
2229 case TGSI_OPCODE_TXD:
2230 case TGSI_OPCODE_TEX2:
2231 case TGSI_OPCODE_TXL2:
2232 case TGSI_OPCODE_TXB2:
2233 case TGSI_OPCODE_TXF:
2234 case TGSI_OPCODE_TXF_LZ:
2235 case TGSI_OPCODE_TG4:
2236 case TGSI_OPCODE_LODQ:
2237 ttn_tex(c, dest, src);
2238 break;
2239
2240 case TGSI_OPCODE_TXQ:
2241 ttn_txq(c, dest, src);
2242 break;
2243
2244 case TGSI_OPCODE_LOAD:
2245 case TGSI_OPCODE_STORE:
2246 ttn_mem(c, dest, src);
2247 break;
2248
2249 case TGSI_OPCODE_NOP:
2250 break;
2251
2252 case TGSI_OPCODE_IF:
2253 ttn_if(c, src[0], false);
2254 break;
2255
2256 case TGSI_OPCODE_UIF:
2257 ttn_if(c, src[0], true);
2258 break;
2259
2260 case TGSI_OPCODE_ELSE:
2261 ttn_else(c);
2262 break;
2263
2264 case TGSI_OPCODE_ENDIF:
2265 ttn_endif(c);
2266 break;
2267
2268 case TGSI_OPCODE_BGNLOOP:
2269 ttn_bgnloop(c);
2270 break;
2271
2272 case TGSI_OPCODE_BRK:
2273 ttn_brk(b);
2274 break;
2275
2276 case TGSI_OPCODE_CONT:
2277 ttn_cont(b);
2278 break;
2279
2280 case TGSI_OPCODE_ENDLOOP:
2281 ttn_endloop(c);
2282 break;
2283
2284 default:
2285 if (op_trans[tgsi_op] != 0 || tgsi_op == TGSI_OPCODE_MOV) {
2286 ttn_alu(b, op_trans[tgsi_op], dest, dst_bitsize, src);
2287 } else {
2288 fprintf(stderr, "unknown TGSI opcode: %s\n",
2289 tgsi_get_opcode_name(tgsi_op));
2290 abort();
2291 }
2292 break;
2293 }
2294
2295 if (tgsi_inst->Instruction.Saturate) {
2296 assert(!dest.dest.is_ssa);
2297 ttn_move_dest(b, dest, nir_fsat(b, ttn_src_for_dest(b, &dest)));
2298 }
2299
2300 /* if the dst has a matching var, append store_var to move
2301 * output from reg to var
2302 */
2303 nir_variable *var = ttn_get_var(c, tgsi_dst);
2304 if (var) {
2305 unsigned index = tgsi_dst->Register.Index;
2306 unsigned offset = c->temp_regs[index].offset;
2307 struct tgsi_ind_register *indirect = tgsi_dst->Register.Indirect ?
2308 &tgsi_dst->Indirect : NULL;
2309 nir_src val = nir_src_for_reg(dest.dest.reg.reg);
2310 nir_store_deref(b, ttn_array_deref(c, var, offset, indirect),
2311 nir_ssa_for_src(b, val, 4), dest.write_mask);
2312 }
2313 }
2314
2315 /**
2316 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
2317 * variables at the end of the shader.
2318 *
2319 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
2320 * written, because there's no output load intrinsic, which means we couldn't
2321 * handle writemasks.
2322 */
2323 static void
2324 ttn_add_output_stores(struct ttn_compile *c)
2325 {
2326 nir_builder *b = &c->build;
2327
2328 for (int i = 0; i < c->build.shader->num_outputs; i++) {
2329 nir_variable *var = c->outputs[i];
2330 if (!var)
2331 continue;
2332
2333 nir_src src = nir_src_for_reg(c->output_regs[i].reg);
2334 src.reg.base_offset = c->output_regs[i].offset;
2335
2336 nir_ssa_def *store_value = nir_ssa_for_src(b, src, 4);
2337 if (c->build.shader->info.stage == MESA_SHADER_FRAGMENT) {
2338 /* TGSI uses TGSI_SEMANTIC_POSITION.z for the depth output
2339 * and TGSI_SEMANTIC_STENCIL.y for the stencil output,
2340 * while NIR uses a single-component output.
2341 */
2342 if (var->data.location == FRAG_RESULT_DEPTH)
2343 store_value = nir_channel(b, store_value, 2);
2344 else if (var->data.location == FRAG_RESULT_STENCIL)
2345 store_value = nir_channel(b, store_value, 1);
2346 }
2347
2348 nir_store_deref(b, nir_build_deref_var(b, var), store_value,
2349 (1 << store_value->num_components) - 1);
2350 }
2351 }
2352
2353 /**
2354 * Parses the given TGSI tokens.
2355 */
2356 static void
2357 ttn_parse_tgsi(struct ttn_compile *c, const void *tgsi_tokens)
2358 {
2359 struct tgsi_parse_context parser;
2360 int ret;
2361
2362 ret = tgsi_parse_init(&parser, tgsi_tokens);
2363 assert(ret == TGSI_PARSE_OK);
2364
2365 while (!tgsi_parse_end_of_tokens(&parser)) {
2366 tgsi_parse_token(&parser);
2367 c->token = &parser.FullToken;
2368
2369 switch (parser.FullToken.Token.Type) {
2370 case TGSI_TOKEN_TYPE_DECLARATION:
2371 ttn_emit_declaration(c);
2372 break;
2373
2374 case TGSI_TOKEN_TYPE_INSTRUCTION:
2375 ttn_emit_instruction(c);
2376 break;
2377
2378 case TGSI_TOKEN_TYPE_IMMEDIATE:
2379 ttn_emit_immediate(c);
2380 break;
2381 }
2382 }
2383
2384 tgsi_parse_free(&parser);
2385 }
2386
2387 static void
2388 ttn_read_pipe_caps(struct ttn_compile *c,
2389 struct pipe_screen *screen)
2390 {
2391 c->cap_scalar = screen->get_shader_param(screen, c->scan->processor, PIPE_SHADER_CAP_SCALAR_ISA);
2392 c->cap_packed_uniforms = screen->get_param(screen, PIPE_CAP_PACKED_UNIFORMS);
2393 c->cap_samplers_as_deref = screen->get_param(screen, PIPE_CAP_NIR_SAMPLERS_AS_DEREF);
2394 c->cap_face_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL);
2395 c->cap_position_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL);
2396 c->cap_point_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL);
2397 }
2398
2399 /**
2400 * Initializes a TGSI-to-NIR compiler.
2401 */
2402 static struct ttn_compile *
2403 ttn_compile_init(const void *tgsi_tokens,
2404 const nir_shader_compiler_options *options,
2405 struct pipe_screen *screen)
2406 {
2407 struct ttn_compile *c;
2408 struct nir_shader *s;
2409 struct tgsi_shader_info scan;
2410
2411 assert(options || screen);
2412 c = rzalloc(NULL, struct ttn_compile);
2413
2414 tgsi_scan_shader(tgsi_tokens, &scan);
2415 c->scan = &scan;
2416
2417 if (!options) {
2418 options =
2419 screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR, scan.processor);
2420 }
2421
2422 nir_builder_init_simple_shader(&c->build, NULL,
2423 tgsi_processor_to_shader_stage(scan.processor),
2424 options);
2425
2426 s = c->build.shader;
2427
2428 if (screen) {
2429 ttn_read_pipe_caps(c, screen);
2430 } else {
2431 /* TTN used to be hard coded to always make FACE a sysval,
2432 * so it makes sense to preserve that behavior so users don't break. */
2433 c->cap_face_is_sysval = true;
2434 }
2435
2436 if (s->info.stage == MESA_SHADER_FRAGMENT)
2437 s->info.fs.untyped_color_outputs = true;
2438
2439 s->num_inputs = scan.file_max[TGSI_FILE_INPUT] + 1;
2440 s->num_uniforms = scan.const_file_max[0] + 1;
2441 s->num_outputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
2442
2443 for (unsigned i = 0; i < TGSI_PROPERTY_COUNT; i++) {
2444 unsigned value = scan.properties[i];
2445
2446 switch (i) {
2447 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
2448 break; /* handled in ttn_emit_declaration */
2449 case TGSI_PROPERTY_FS_COORD_ORIGIN:
2450 s->info.fs.origin_upper_left = value == TGSI_FS_COORD_ORIGIN_UPPER_LEFT;
2451 break;
2452 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
2453 s->info.fs.pixel_center_integer = value == TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
2454 break;
2455 case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
2456 s->info.fs.depth_layout = ttn_get_depth_layout(value);
2457 break;
2458 case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION:
2459 s->info.vs.window_space_position = value;
2460 break;
2461 case TGSI_PROPERTY_NEXT_SHADER:
2462 s->info.next_stage = tgsi_processor_to_shader_stage(value);
2463 break;
2464 case TGSI_PROPERTY_VS_BLIT_SGPRS_AMD:
2465 s->info.vs.blit_sgprs_amd = value;
2466 break;
2467 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH:
2468 s->info.cs.local_size[0] = value;
2469 break;
2470 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT:
2471 s->info.cs.local_size[1] = value;
2472 break;
2473 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH:
2474 s->info.cs.local_size[2] = value;
2475 break;
2476 case TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD:
2477 s->info.cs.user_data_components_amd = value;
2478 break;
2479 default:
2480 if (value) {
2481 fprintf(stderr, "tgsi_to_nir: unhandled TGSI property %u = %u\n",
2482 i, value);
2483 unreachable("unhandled TGSI property");
2484 }
2485 }
2486 }
2487
2488 if (s->info.stage == MESA_SHADER_COMPUTE &&
2489 (!s->info.cs.local_size[0] ||
2490 !s->info.cs.local_size[1] ||
2491 !s->info.cs.local_size[2]))
2492 s->info.cs.local_size_variable = true;
2493
2494 c->inputs = rzalloc_array(c, struct nir_variable *, s->num_inputs);
2495 c->outputs = rzalloc_array(c, struct nir_variable *, s->num_outputs);
2496
2497 c->output_regs = rzalloc_array(c, struct ttn_reg_info,
2498 scan.file_max[TGSI_FILE_OUTPUT] + 1);
2499 c->temp_regs = rzalloc_array(c, struct ttn_reg_info,
2500 scan.file_max[TGSI_FILE_TEMPORARY] + 1);
2501 c->imm_defs = rzalloc_array(c, nir_ssa_def *,
2502 scan.file_max[TGSI_FILE_IMMEDIATE] + 1);
2503
2504 c->num_samp_types = scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1;
2505 c->samp_types = rzalloc_array(c, nir_alu_type, c->num_samp_types);
2506
2507 c->if_stack = rzalloc_array(c, nir_cursor,
2508 (scan.opcode_count[TGSI_OPCODE_IF] +
2509 scan.opcode_count[TGSI_OPCODE_UIF]) * 2);
2510 c->loop_stack = rzalloc_array(c, nir_cursor,
2511 scan.opcode_count[TGSI_OPCODE_BGNLOOP]);
2512
2513
2514 ttn_parse_tgsi(c, tgsi_tokens);
2515 ttn_add_output_stores(c);
2516
2517 nir_validate_shader(c->build.shader, "TTN: after parsing TGSI and creating the NIR shader");
2518
2519 return c;
2520 }
2521
2522 static void
2523 ttn_optimize_nir(nir_shader *nir, bool scalar)
2524 {
2525 bool progress;
2526 do {
2527 progress = false;
2528
2529 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2530
2531 if (scalar) {
2532 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
2533 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
2534 }
2535
2536 NIR_PASS_V(nir, nir_lower_alu);
2537 NIR_PASS_V(nir, nir_lower_pack);
2538 NIR_PASS(progress, nir, nir_copy_prop);
2539 NIR_PASS(progress, nir, nir_opt_remove_phis);
2540 NIR_PASS(progress, nir, nir_opt_dce);
2541
2542 if (nir_opt_trivial_continues(nir)) {
2543 progress = true;
2544 NIR_PASS(progress, nir, nir_copy_prop);
2545 NIR_PASS(progress, nir, nir_opt_dce);
2546 }
2547
2548 NIR_PASS(progress, nir, nir_opt_if, false);
2549 NIR_PASS(progress, nir, nir_opt_dead_cf);
2550 NIR_PASS(progress, nir, nir_opt_cse);
2551 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
2552
2553 NIR_PASS(progress, nir, nir_opt_algebraic);
2554 NIR_PASS(progress, nir, nir_opt_constant_folding);
2555
2556 NIR_PASS(progress, nir, nir_opt_undef);
2557 NIR_PASS(progress, nir, nir_opt_conditional_discard);
2558
2559 if (nir->options->max_unroll_iterations) {
2560 NIR_PASS(progress, nir, nir_opt_loop_unroll, (nir_variable_mode)0);
2561 }
2562
2563 } while (progress);
2564
2565 }
2566
2567 /**
2568 * Finalizes the NIR in a similar way as st_glsl_to_nir does.
2569 *
2570 * Drivers expect that these passes are already performed,
2571 * so we have to do it here too.
2572 */
2573 static void
2574 ttn_finalize_nir(struct ttn_compile *c)
2575 {
2576 struct nir_shader *nir = c->build.shader;
2577
2578 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2579 NIR_PASS_V(nir, nir_lower_regs_to_ssa);
2580
2581 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2582 NIR_PASS_V(nir, nir_split_var_copies);
2583 NIR_PASS_V(nir, nir_lower_var_copies);
2584 NIR_PASS_V(nir, nir_lower_system_values);
2585
2586 if (c->cap_packed_uniforms)
2587 NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, 16);
2588
2589 if (c->cap_samplers_as_deref)
2590 NIR_PASS_V(nir, gl_nir_lower_samplers_as_deref, NULL);
2591 else
2592 NIR_PASS_V(nir, gl_nir_lower_samplers, NULL);
2593
2594 ttn_optimize_nir(nir, c->cap_scalar);
2595 nir_shader_gather_info(nir, c->build.impl);
2596 nir_validate_shader(nir, "TTN: after all optimizations");
2597 }
2598
2599 struct nir_shader *
2600 tgsi_to_nir(const void *tgsi_tokens,
2601 struct pipe_screen *screen)
2602 {
2603 struct ttn_compile *c;
2604 struct nir_shader *s;
2605
2606 c = ttn_compile_init(tgsi_tokens, NULL, screen);
2607 s = c->build.shader;
2608 ttn_finalize_nir(c);
2609 ralloc_free(c);
2610
2611 return s;
2612 }
2613
2614 struct nir_shader *
2615 tgsi_to_nir_noscreen(const void *tgsi_tokens,
2616 const nir_shader_compiler_options *options)
2617 {
2618 struct ttn_compile *c;
2619 struct nir_shader *s;
2620
2621 c = ttn_compile_init(tgsi_tokens, options, NULL);
2622 s = c->build.shader;
2623 ralloc_free(c);
2624
2625 return s;
2626 }
2627