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[mesa.git] / src / gallium / auxiliary / nir / tgsi_to_nir.c
1 /*
2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/ralloc.h"
26 #include "compiler/nir/nir.h"
27 #include "compiler/nir/nir_control_flow.h"
28 #include "compiler/nir/nir_builder.h"
29 #include "compiler/glsl/list.h"
30 #include "compiler/shader_enums.h"
31
32 #include "tgsi_to_nir.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_info.h"
36 #include "tgsi/tgsi_scan.h"
37
38 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
39 TGSI_SWIZZLE_##X, \
40 TGSI_SWIZZLE_##Y, \
41 TGSI_SWIZZLE_##Z, \
42 TGSI_SWIZZLE_##W, \
43 }
44
45 struct ttn_reg_info {
46 /** nir register containing this TGSI index. */
47 nir_register *reg;
48 nir_variable *var;
49 /** Offset (in vec4s) from the start of var for this TGSI index. */
50 int offset;
51 };
52
53 struct ttn_compile {
54 union tgsi_full_token *token;
55 nir_builder build;
56 struct tgsi_shader_info *scan;
57
58 struct ttn_reg_info *output_regs;
59 struct ttn_reg_info *temp_regs;
60 nir_ssa_def **imm_defs;
61
62 unsigned num_samp_types;
63 nir_alu_type *samp_types;
64
65 nir_register *addr_reg;
66
67 /**
68 * Stack of nir_cursors where instructions should be pushed as we pop
69 * back out of the control flow stack.
70 *
71 * For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else
72 * instructions should be placed, and if_stack[if_stack_pos - 1] has where
73 * the next instructions outside of the if/then/else block go.
74 */
75 nir_cursor *if_stack;
76 unsigned if_stack_pos;
77
78 /**
79 * Stack of nir_cursors where instructions should be pushed as we pop
80 * back out of the control flow stack.
81 *
82 * loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside
83 * of the loop.
84 */
85 nir_cursor *loop_stack;
86 unsigned loop_stack_pos;
87
88 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
89 unsigned next_imm;
90 };
91
92 #define ttn_swizzle(b, src, x, y, z, w) \
93 nir_swizzle(b, src, SWIZ(x, y, z, w), 4, false)
94 #define ttn_channel(b, src, swiz) \
95 nir_swizzle(b, src, SWIZ(swiz, swiz, swiz, swiz), 1, false)
96
97 static gl_varying_slot
98 tgsi_varying_semantic_to_slot(unsigned semantic, unsigned index)
99 {
100 switch (semantic) {
101 case TGSI_SEMANTIC_POSITION:
102 return VARYING_SLOT_POS;
103 case TGSI_SEMANTIC_COLOR:
104 if (index == 0)
105 return VARYING_SLOT_COL0;
106 else
107 return VARYING_SLOT_COL1;
108 case TGSI_SEMANTIC_BCOLOR:
109 if (index == 0)
110 return VARYING_SLOT_BFC0;
111 else
112 return VARYING_SLOT_BFC1;
113 case TGSI_SEMANTIC_FOG:
114 return VARYING_SLOT_FOGC;
115 case TGSI_SEMANTIC_PSIZE:
116 return VARYING_SLOT_PSIZ;
117 case TGSI_SEMANTIC_GENERIC:
118 return VARYING_SLOT_VAR0 + index;
119 case TGSI_SEMANTIC_FACE:
120 return VARYING_SLOT_FACE;
121 case TGSI_SEMANTIC_EDGEFLAG:
122 return VARYING_SLOT_EDGE;
123 case TGSI_SEMANTIC_PRIMID:
124 return VARYING_SLOT_PRIMITIVE_ID;
125 case TGSI_SEMANTIC_CLIPDIST:
126 if (index == 0)
127 return VARYING_SLOT_CLIP_DIST0;
128 else
129 return VARYING_SLOT_CLIP_DIST1;
130 case TGSI_SEMANTIC_CLIPVERTEX:
131 return VARYING_SLOT_CLIP_VERTEX;
132 case TGSI_SEMANTIC_TEXCOORD:
133 return VARYING_SLOT_TEX0 + index;
134 case TGSI_SEMANTIC_PCOORD:
135 return VARYING_SLOT_PNTC;
136 case TGSI_SEMANTIC_VIEWPORT_INDEX:
137 return VARYING_SLOT_VIEWPORT;
138 case TGSI_SEMANTIC_LAYER:
139 return VARYING_SLOT_LAYER;
140 default:
141 fprintf(stderr, "Bad TGSI semantic: %d/%d\n", semantic, index);
142 abort();
143 }
144 }
145
146 /* Temporary helper to remap back to TGSI style semantic name/index
147 * values, for use in drivers that haven't been converted to using
148 * VARYING_SLOT_
149 */
150 void
151 varying_slot_to_tgsi_semantic(gl_varying_slot slot,
152 unsigned *semantic_name, unsigned *semantic_index)
153 {
154 static const unsigned map[][2] = {
155 [VARYING_SLOT_POS] = { TGSI_SEMANTIC_POSITION, 0 },
156 [VARYING_SLOT_COL0] = { TGSI_SEMANTIC_COLOR, 0 },
157 [VARYING_SLOT_COL1] = { TGSI_SEMANTIC_COLOR, 1 },
158 [VARYING_SLOT_BFC0] = { TGSI_SEMANTIC_BCOLOR, 0 },
159 [VARYING_SLOT_BFC1] = { TGSI_SEMANTIC_BCOLOR, 1 },
160 [VARYING_SLOT_FOGC] = { TGSI_SEMANTIC_FOG, 0 },
161 [VARYING_SLOT_PSIZ] = { TGSI_SEMANTIC_PSIZE, 0 },
162 [VARYING_SLOT_FACE] = { TGSI_SEMANTIC_FACE, 0 },
163 [VARYING_SLOT_EDGE] = { TGSI_SEMANTIC_EDGEFLAG, 0 },
164 [VARYING_SLOT_PRIMITIVE_ID] = { TGSI_SEMANTIC_PRIMID, 0 },
165 [VARYING_SLOT_CLIP_DIST0] = { TGSI_SEMANTIC_CLIPDIST, 0 },
166 [VARYING_SLOT_CLIP_DIST1] = { TGSI_SEMANTIC_CLIPDIST, 1 },
167 [VARYING_SLOT_CLIP_VERTEX] = { TGSI_SEMANTIC_CLIPVERTEX, 0 },
168 [VARYING_SLOT_PNTC] = { TGSI_SEMANTIC_PCOORD, 0 },
169 [VARYING_SLOT_VIEWPORT] = { TGSI_SEMANTIC_VIEWPORT_INDEX, 0 },
170 [VARYING_SLOT_LAYER] = { TGSI_SEMANTIC_LAYER, 0 },
171 };
172
173 if (slot >= VARYING_SLOT_VAR0) {
174 *semantic_name = TGSI_SEMANTIC_GENERIC;
175 *semantic_index = slot - VARYING_SLOT_VAR0;
176 return;
177 }
178
179 if (slot >= VARYING_SLOT_TEX0 && slot <= VARYING_SLOT_TEX7) {
180 *semantic_name = TGSI_SEMANTIC_TEXCOORD;
181 *semantic_index = slot - VARYING_SLOT_TEX0;
182 return;
183 }
184
185 if (slot >= ARRAY_SIZE(map)) {
186 fprintf(stderr, "Unknown varying slot %d\n", slot);
187 abort();
188 }
189
190 *semantic_name = map[slot][0];
191 *semantic_index = map[slot][1];
192 }
193
194 /* Temporary helper to remap back to TGSI style semantic name/index
195 * values, for use in drivers that haven't been converted to using
196 * FRAG_RESULT_
197 */
198 void
199 frag_result_to_tgsi_semantic(gl_frag_result slot,
200 unsigned *semantic_name, unsigned *semantic_index)
201 {
202 static const unsigned map[][2] = {
203 [FRAG_RESULT_DEPTH] = { TGSI_SEMANTIC_POSITION, 0 },
204 [FRAG_RESULT_COLOR] = { TGSI_SEMANTIC_COLOR, -1 },
205 [FRAG_RESULT_DATA0 + 0] = { TGSI_SEMANTIC_COLOR, 0 },
206 [FRAG_RESULT_DATA0 + 1] = { TGSI_SEMANTIC_COLOR, 1 },
207 [FRAG_RESULT_DATA0 + 2] = { TGSI_SEMANTIC_COLOR, 2 },
208 [FRAG_RESULT_DATA0 + 3] = { TGSI_SEMANTIC_COLOR, 3 },
209 [FRAG_RESULT_DATA0 + 4] = { TGSI_SEMANTIC_COLOR, 4 },
210 [FRAG_RESULT_DATA0 + 5] = { TGSI_SEMANTIC_COLOR, 5 },
211 [FRAG_RESULT_DATA0 + 6] = { TGSI_SEMANTIC_COLOR, 6 },
212 [FRAG_RESULT_DATA0 + 7] = { TGSI_SEMANTIC_COLOR, 7 },
213 };
214
215 *semantic_name = map[slot][0];
216 *semantic_index = map[slot][1];
217 }
218
219 static nir_ssa_def *
220 ttn_src_for_dest(nir_builder *b, nir_alu_dest *dest)
221 {
222 nir_alu_src src;
223 memset(&src, 0, sizeof(src));
224
225 if (dest->dest.is_ssa)
226 src.src = nir_src_for_ssa(&dest->dest.ssa);
227 else {
228 assert(!dest->dest.reg.indirect);
229 src.src = nir_src_for_reg(dest->dest.reg.reg);
230 src.src.reg.base_offset = dest->dest.reg.base_offset;
231 }
232
233 for (int i = 0; i < 4; i++)
234 src.swizzle[i] = i;
235
236 return nir_fmov_alu(b, src, 4);
237 }
238
239 static void
240 ttn_emit_declaration(struct ttn_compile *c)
241 {
242 nir_builder *b = &c->build;
243 struct tgsi_full_declaration *decl = &c->token->FullDeclaration;
244 unsigned array_size = decl->Range.Last - decl->Range.First + 1;
245 unsigned file = decl->Declaration.File;
246 unsigned i;
247
248 if (file == TGSI_FILE_TEMPORARY) {
249 if (decl->Declaration.Array) {
250 /* for arrays, we create variables instead of registers: */
251 nir_variable *var = rzalloc(b->shader, nir_variable);
252
253 var->type = glsl_array_type(glsl_vec4_type(), array_size);
254 var->data.mode = nir_var_global;
255 var->name = ralloc_asprintf(var, "arr_%d", decl->Array.ArrayID);
256
257 exec_list_push_tail(&b->shader->globals, &var->node);
258
259 for (i = 0; i < array_size; i++) {
260 /* point all the matching slots to the same var,
261 * with appropriate offset set, mostly just so
262 * we know what to do when tgsi does a non-indirect
263 * access
264 */
265 c->temp_regs[decl->Range.First + i].reg = NULL;
266 c->temp_regs[decl->Range.First + i].var = var;
267 c->temp_regs[decl->Range.First + i].offset = i;
268 }
269 } else {
270 for (i = 0; i < array_size; i++) {
271 nir_register *reg = nir_local_reg_create(b->impl);
272 reg->num_components = 4;
273 c->temp_regs[decl->Range.First + i].reg = reg;
274 c->temp_regs[decl->Range.First + i].var = NULL;
275 c->temp_regs[decl->Range.First + i].offset = 0;
276 }
277 }
278 } else if (file == TGSI_FILE_ADDRESS) {
279 c->addr_reg = nir_local_reg_create(b->impl);
280 c->addr_reg->num_components = 4;
281 } else if (file == TGSI_FILE_SYSTEM_VALUE) {
282 /* Nothing to record for system values. */
283 } else if (file == TGSI_FILE_SAMPLER) {
284 /* Nothing to record for samplers. */
285 } else if (file == TGSI_FILE_SAMPLER_VIEW) {
286 struct tgsi_declaration_sampler_view *sview = &decl->SamplerView;
287 nir_alu_type type;
288
289 assert((sview->ReturnTypeX == sview->ReturnTypeY) &&
290 (sview->ReturnTypeX == sview->ReturnTypeZ) &&
291 (sview->ReturnTypeX == sview->ReturnTypeW));
292
293 switch (sview->ReturnTypeX) {
294 case TGSI_RETURN_TYPE_SINT:
295 type = nir_type_int;
296 break;
297 case TGSI_RETURN_TYPE_UINT:
298 type = nir_type_uint;
299 break;
300 case TGSI_RETURN_TYPE_FLOAT:
301 default:
302 type = nir_type_float;
303 break;
304 }
305
306 for (i = 0; i < array_size; i++) {
307 c->samp_types[decl->Range.First + i] = type;
308 }
309 } else {
310 bool is_array = (array_size > 1);
311
312 assert(file == TGSI_FILE_INPUT ||
313 file == TGSI_FILE_OUTPUT ||
314 file == TGSI_FILE_CONSTANT);
315
316 /* nothing to do for UBOs: */
317 if ((file == TGSI_FILE_CONSTANT) && decl->Declaration.Dimension) {
318 b->shader->info.num_ubos =
319 MAX2(b->shader->info.num_ubos, decl->Dim.Index2D);
320 return;
321 }
322
323 if ((file == TGSI_FILE_INPUT) || (file == TGSI_FILE_OUTPUT)) {
324 is_array = (is_array && decl->Declaration.Array &&
325 (decl->Array.ArrayID != 0));
326 }
327
328 for (i = 0; i < array_size; i++) {
329 unsigned idx = decl->Range.First + i;
330 nir_variable *var = rzalloc(b->shader, nir_variable);
331
332 var->data.driver_location = idx;
333
334 var->type = glsl_vec4_type();
335 if (is_array)
336 var->type = glsl_array_type(var->type, array_size);
337
338 switch (file) {
339 case TGSI_FILE_INPUT:
340 var->data.read_only = true;
341 var->data.mode = nir_var_shader_in;
342 var->name = ralloc_asprintf(var, "in_%d", idx);
343
344 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
345 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
346 var->data.location = SYSTEM_VALUE_FRONT_FACE;
347 var->data.mode = nir_var_system_value;
348 } else {
349 var->data.location =
350 tgsi_varying_semantic_to_slot(decl->Semantic.Name,
351 decl->Semantic.Index);
352 }
353 } else {
354 assert(!decl->Declaration.Semantic);
355 var->data.location = VERT_ATTRIB_GENERIC0 + idx;
356 }
357 var->data.index = 0;
358
359 /* We definitely need to translate the interpolation field, because
360 * nir_print will decode it.
361 */
362 switch (decl->Interp.Interpolate) {
363 case TGSI_INTERPOLATE_CONSTANT:
364 var->data.interpolation = INTERP_MODE_FLAT;
365 break;
366 case TGSI_INTERPOLATE_LINEAR:
367 var->data.interpolation = INTERP_MODE_NOPERSPECTIVE;
368 break;
369 case TGSI_INTERPOLATE_PERSPECTIVE:
370 var->data.interpolation = INTERP_MODE_SMOOTH;
371 break;
372 }
373
374 exec_list_push_tail(&b->shader->inputs, &var->node);
375
376 for (int i = 0; i < array_size; i++)
377 b->shader->info.inputs_read |= 1 << (var->data.location + i);
378
379 break;
380 case TGSI_FILE_OUTPUT: {
381 int semantic_name = decl->Semantic.Name;
382 int semantic_index = decl->Semantic.Index;
383 /* Since we can't load from outputs in the IR, we make temporaries
384 * for the outputs and emit stores to the real outputs at the end of
385 * the shader.
386 */
387 nir_register *reg = nir_local_reg_create(b->impl);
388 reg->num_components = 4;
389 if (is_array)
390 reg->num_array_elems = array_size;
391
392 var->data.mode = nir_var_shader_out;
393 var->name = ralloc_asprintf(var, "out_%d", idx);
394 var->data.index = 0;
395
396 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
397 switch (semantic_name) {
398 case TGSI_SEMANTIC_COLOR: {
399 /* TODO tgsi loses some information, so we cannot
400 * actually differentiate here between DSB and MRT
401 * at this point. But so far no drivers using tgsi-
402 * to-nir support dual source blend:
403 */
404 bool dual_src_blend = false;
405 if (dual_src_blend && (semantic_index == 1)) {
406 var->data.location = FRAG_RESULT_DATA0;
407 var->data.index = 1;
408 } else {
409 if (c->scan->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
410 var->data.location = FRAG_RESULT_COLOR;
411 else
412 var->data.location = FRAG_RESULT_DATA0 + semantic_index;
413 }
414 break;
415 }
416 case TGSI_SEMANTIC_POSITION:
417 var->data.location = FRAG_RESULT_DEPTH;
418 break;
419 default:
420 fprintf(stderr, "Bad TGSI semantic: %d/%d\n",
421 decl->Semantic.Name, decl->Semantic.Index);
422 abort();
423 }
424 } else {
425 var->data.location =
426 tgsi_varying_semantic_to_slot(semantic_name, semantic_index);
427 }
428
429 if (is_array) {
430 unsigned j;
431 for (j = 0; j < array_size; j++) {
432 c->output_regs[idx + j].offset = i + j;
433 c->output_regs[idx + j].reg = reg;
434 }
435 } else {
436 c->output_regs[idx].offset = i;
437 c->output_regs[idx].reg = reg;
438 }
439
440 exec_list_push_tail(&b->shader->outputs, &var->node);
441
442 for (int i = 0; i < array_size; i++)
443 b->shader->info.outputs_written |= 1 << (var->data.location + i);
444 }
445 break;
446 case TGSI_FILE_CONSTANT:
447 var->data.mode = nir_var_uniform;
448 var->name = ralloc_asprintf(var, "uniform_%d", idx);
449
450 exec_list_push_tail(&b->shader->uniforms, &var->node);
451 break;
452 default:
453 unreachable("bad declaration file");
454 return;
455 }
456
457 if (is_array)
458 break;
459 }
460
461 }
462 }
463
464 static void
465 ttn_emit_immediate(struct ttn_compile *c)
466 {
467 nir_builder *b = &c->build;
468 struct tgsi_full_immediate *tgsi_imm = &c->token->FullImmediate;
469 nir_load_const_instr *load_const;
470 int i;
471
472 load_const = nir_load_const_instr_create(b->shader, 4, 32);
473 c->imm_defs[c->next_imm] = &load_const->def;
474 c->next_imm++;
475
476 for (i = 0; i < 4; i++)
477 load_const->value.u32[i] = tgsi_imm->u[i].Uint;
478
479 nir_builder_instr_insert(b, &load_const->instr);
480 }
481
482 static nir_ssa_def *
483 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect);
484
485 /* generate either a constant or indirect deref chain for accessing an
486 * array variable.
487 */
488 static nir_deref_var *
489 ttn_array_deref(struct ttn_compile *c, nir_intrinsic_instr *instr,
490 nir_variable *var, unsigned offset,
491 struct tgsi_ind_register *indirect)
492 {
493 nir_deref_var *deref = nir_deref_var_create(instr, var);
494 nir_deref_array *arr = nir_deref_array_create(deref);
495
496 arr->base_offset = offset;
497 arr->deref.type = glsl_get_array_element(var->type);
498
499 if (indirect) {
500 arr->deref_array_type = nir_deref_array_type_indirect;
501 arr->indirect = nir_src_for_ssa(ttn_src_for_indirect(c, indirect));
502 } else {
503 arr->deref_array_type = nir_deref_array_type_direct;
504 }
505
506 deref->deref.child = &arr->deref;
507
508 return deref;
509 }
510
511 static nir_src
512 ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
513 struct tgsi_ind_register *indirect,
514 struct tgsi_dimension *dim,
515 struct tgsi_ind_register *dimind)
516 {
517 nir_builder *b = &c->build;
518 nir_src src;
519
520 memset(&src, 0, sizeof(src));
521
522 switch (file) {
523 case TGSI_FILE_TEMPORARY:
524 if (c->temp_regs[index].var) {
525 unsigned offset = c->temp_regs[index].offset;
526 nir_variable *var = c->temp_regs[index].var;
527 nir_intrinsic_instr *load;
528
529 load = nir_intrinsic_instr_create(b->shader,
530 nir_intrinsic_load_var);
531 load->num_components = 4;
532 load->variables[0] = ttn_array_deref(c, load, var, offset, indirect);
533 nir_ssa_dest_init(&load->instr, &load->dest,
534 4, 32, NULL);
535 nir_builder_instr_insert(b, &load->instr);
536
537 src = nir_src_for_ssa(&load->dest.ssa);
538
539 } else {
540 assert(!indirect);
541 src.reg.reg = c->temp_regs[index].reg;
542 }
543 assert(!dim);
544 break;
545
546 case TGSI_FILE_ADDRESS:
547 src.reg.reg = c->addr_reg;
548 assert(!dim);
549 break;
550
551 case TGSI_FILE_IMMEDIATE:
552 src = nir_src_for_ssa(c->imm_defs[index]);
553 assert(!indirect);
554 assert(!dim);
555 break;
556
557 case TGSI_FILE_SYSTEM_VALUE: {
558 nir_intrinsic_instr *load;
559 nir_intrinsic_op op;
560 unsigned ncomp = 1;
561
562 assert(!indirect);
563 assert(!dim);
564
565 switch (c->scan->system_value_semantic_name[index]) {
566 case TGSI_SEMANTIC_VERTEXID_NOBASE:
567 op = nir_intrinsic_load_vertex_id_zero_base;
568 break;
569 case TGSI_SEMANTIC_VERTEXID:
570 op = nir_intrinsic_load_vertex_id;
571 break;
572 case TGSI_SEMANTIC_BASEVERTEX:
573 op = nir_intrinsic_load_base_vertex;
574 break;
575 case TGSI_SEMANTIC_INSTANCEID:
576 op = nir_intrinsic_load_instance_id;
577 break;
578 default:
579 unreachable("bad system value");
580 }
581
582 load = nir_intrinsic_instr_create(b->shader, op);
583 load->num_components = ncomp;
584
585 nir_ssa_dest_init(&load->instr, &load->dest, ncomp, 32, NULL);
586 nir_builder_instr_insert(b, &load->instr);
587
588 src = nir_src_for_ssa(&load->dest.ssa);
589
590 b->shader->info.system_values_read |=
591 (1 << nir_system_value_from_intrinsic(op));
592
593 break;
594 }
595
596 case TGSI_FILE_INPUT:
597 case TGSI_FILE_CONSTANT: {
598 nir_intrinsic_instr *load;
599 nir_intrinsic_op op;
600 unsigned srcn = 0;
601
602 switch (file) {
603 case TGSI_FILE_INPUT:
604 /* Special case: Turn the frontface varying into a load of the
605 * frontface intrinsic plus math, and appending the silly floats.
606 */
607 if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
608 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_FACE) {
609 nir_ssa_def *tgsi_frontface[4] = {
610 nir_bcsel(&c->build,
611 nir_load_system_value(&c->build,
612 nir_intrinsic_load_front_face, 0),
613 nir_imm_float(&c->build, 1.0),
614 nir_imm_float(&c->build, -1.0)),
615 nir_imm_float(&c->build, 0.0),
616 nir_imm_float(&c->build, 0.0),
617 nir_imm_float(&c->build, 1.0),
618 };
619
620 return nir_src_for_ssa(nir_vec(&c->build, tgsi_frontface, 4));
621 }
622
623 op = nir_intrinsic_load_input;
624 assert(!dim);
625 break;
626 case TGSI_FILE_CONSTANT:
627 if (dim) {
628 op = nir_intrinsic_load_ubo;
629 } else {
630 op = nir_intrinsic_load_uniform;
631 }
632 break;
633 default:
634 unreachable("No other load files supported");
635 break;
636 }
637
638 load = nir_intrinsic_instr_create(b->shader, op);
639
640 load->num_components = 4;
641 if (dim) {
642 if (dimind) {
643 load->src[srcn] =
644 ttn_src_for_file_and_index(c, dimind->File, dimind->Index,
645 NULL, NULL, NULL);
646 } else {
647 /* UBOs start at index 1 in TGSI: */
648 load->src[srcn] =
649 nir_src_for_ssa(nir_imm_int(b, dim->Index - 1));
650 }
651 srcn++;
652 }
653
654 nir_ssa_def *offset;
655 if (op == nir_intrinsic_load_ubo) {
656 /* UBO loads don't have a base offset. */
657 offset = nir_imm_int(b, index);
658 if (indirect) {
659 offset = nir_iadd(b, offset, ttn_src_for_indirect(c, indirect));
660 }
661 /* UBO offsets are in bytes, but TGSI gives them to us in vec4's */
662 offset = nir_ishl(b, offset, nir_imm_int(b, 4));
663 } else {
664 nir_intrinsic_set_base(load, index);
665 if (indirect) {
666 offset = ttn_src_for_indirect(c, indirect);
667 } else {
668 offset = nir_imm_int(b, 0);
669 }
670 }
671 load->src[srcn++] = nir_src_for_ssa(offset);
672
673 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
674 nir_builder_instr_insert(b, &load->instr);
675
676 src = nir_src_for_ssa(&load->dest.ssa);
677 break;
678 }
679
680 default:
681 unreachable("bad src file");
682 }
683
684
685 return src;
686 }
687
688 static nir_ssa_def *
689 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect)
690 {
691 nir_builder *b = &c->build;
692 nir_alu_src src;
693 memset(&src, 0, sizeof(src));
694 for (int i = 0; i < 4; i++)
695 src.swizzle[i] = indirect->Swizzle;
696 src.src = ttn_src_for_file_and_index(c,
697 indirect->File,
698 indirect->Index,
699 NULL, NULL, NULL);
700 return nir_imov_alu(b, src, 1);
701 }
702
703 static nir_alu_dest
704 ttn_get_dest(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
705 {
706 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
707 nir_alu_dest dest;
708 unsigned index = tgsi_dst->Index;
709
710 memset(&dest, 0, sizeof(dest));
711
712 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
713 if (c->temp_regs[index].var) {
714 nir_register *reg;
715
716 /* this works, because TGSI will give us a base offset
717 * (in case of indirect index) that points back into
718 * the array. Access can be direct or indirect, we
719 * don't really care. Just create a one-shot dst reg
720 * that will get store_var'd back into the array var
721 * at the end of ttn_emit_instruction()
722 */
723 reg = nir_local_reg_create(c->build.impl);
724 reg->num_components = 4;
725 dest.dest.reg.reg = reg;
726 dest.dest.reg.base_offset = 0;
727 } else {
728 assert(!tgsi_dst->Indirect);
729 dest.dest.reg.reg = c->temp_regs[index].reg;
730 dest.dest.reg.base_offset = c->temp_regs[index].offset;
731 }
732 } else if (tgsi_dst->File == TGSI_FILE_OUTPUT) {
733 dest.dest.reg.reg = c->output_regs[index].reg;
734 dest.dest.reg.base_offset = c->output_regs[index].offset;
735 } else if (tgsi_dst->File == TGSI_FILE_ADDRESS) {
736 assert(index == 0);
737 dest.dest.reg.reg = c->addr_reg;
738 }
739
740 dest.write_mask = tgsi_dst->WriteMask;
741 dest.saturate = false;
742
743 if (tgsi_dst->Indirect && (tgsi_dst->File != TGSI_FILE_TEMPORARY)) {
744 nir_src *indirect = ralloc(c->build.shader, nir_src);
745 *indirect = nir_src_for_ssa(ttn_src_for_indirect(c, &tgsi_fdst->Indirect));
746 dest.dest.reg.indirect = indirect;
747 }
748
749 return dest;
750 }
751
752 static nir_variable *
753 ttn_get_var(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
754 {
755 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
756 unsigned index = tgsi_dst->Index;
757
758 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
759 /* we should not have an indirect when there is no var! */
760 if (!c->temp_regs[index].var)
761 assert(!tgsi_dst->Indirect);
762 return c->temp_regs[index].var;
763 }
764
765 return NULL;
766 }
767
768 static nir_ssa_def *
769 ttn_get_src(struct ttn_compile *c, struct tgsi_full_src_register *tgsi_fsrc)
770 {
771 nir_builder *b = &c->build;
772 struct tgsi_src_register *tgsi_src = &tgsi_fsrc->Register;
773 unsigned tgsi_opcode = c->token->FullInstruction.Instruction.Opcode;
774 unsigned tgsi_src_type = tgsi_opcode_infer_src_type(tgsi_opcode);
775 bool src_is_float = !(tgsi_src_type == TGSI_TYPE_SIGNED ||
776 tgsi_src_type == TGSI_TYPE_UNSIGNED);
777 nir_alu_src src;
778
779 memset(&src, 0, sizeof(src));
780
781 if (tgsi_src->File == TGSI_FILE_NULL) {
782 return nir_imm_float(b, 0.0);
783 } else if (tgsi_src->File == TGSI_FILE_SAMPLER) {
784 /* Only the index of the sampler gets used in texturing, and it will
785 * handle looking that up on its own instead of using the nir_alu_src.
786 */
787 assert(!tgsi_src->Indirect);
788 return NULL;
789 } else {
790 struct tgsi_ind_register *ind = NULL;
791 struct tgsi_dimension *dim = NULL;
792 struct tgsi_ind_register *dimind = NULL;
793 if (tgsi_src->Indirect)
794 ind = &tgsi_fsrc->Indirect;
795 if (tgsi_src->Dimension) {
796 dim = &tgsi_fsrc->Dimension;
797 if (dim->Indirect)
798 dimind = &tgsi_fsrc->DimIndirect;
799 }
800 src.src = ttn_src_for_file_and_index(c,
801 tgsi_src->File,
802 tgsi_src->Index,
803 ind, dim, dimind);
804 }
805
806 src.swizzle[0] = tgsi_src->SwizzleX;
807 src.swizzle[1] = tgsi_src->SwizzleY;
808 src.swizzle[2] = tgsi_src->SwizzleZ;
809 src.swizzle[3] = tgsi_src->SwizzleW;
810
811 nir_ssa_def *def = nir_fmov_alu(b, src, 4);
812
813 if (tgsi_src->Absolute) {
814 if (src_is_float)
815 def = nir_fabs(b, def);
816 else
817 def = nir_iabs(b, def);
818 }
819
820 if (tgsi_src->Negate) {
821 if (src_is_float)
822 def = nir_fneg(b, def);
823 else
824 def = nir_ineg(b, def);
825 }
826
827 return def;
828 }
829
830 static void
831 ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
832 {
833 unsigned num_srcs = nir_op_infos[op].num_inputs;
834 nir_alu_instr *instr = nir_alu_instr_create(b->shader, op);
835 unsigned i;
836
837 for (i = 0; i < num_srcs; i++)
838 instr->src[i].src = nir_src_for_ssa(src[i]);
839
840 instr->dest = dest;
841 nir_builder_instr_insert(b, &instr->instr);
842 }
843
844 static void
845 ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
846 nir_ssa_def *def, unsigned write_mask)
847 {
848 if (!(dest.write_mask & write_mask))
849 return;
850
851 nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_imov);
852 mov->dest = dest;
853 mov->dest.write_mask &= write_mask;
854 mov->src[0].src = nir_src_for_ssa(def);
855 for (unsigned i = def->num_components; i < 4; i++)
856 mov->src[0].swizzle[i] = def->num_components - 1;
857 nir_builder_instr_insert(b, &mov->instr);
858 }
859
860 static void
861 ttn_move_dest(nir_builder *b, nir_alu_dest dest, nir_ssa_def *def)
862 {
863 ttn_move_dest_masked(b, dest, def, TGSI_WRITEMASK_XYZW);
864 }
865
866 static void
867 ttn_arl(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
868 {
869 ttn_move_dest(b, dest, nir_f2i32(b, nir_ffloor(b, src[0])));
870 }
871
872 /* EXP - Approximate Exponential Base 2
873 * dst.x = 2^{\lfloor src.x\rfloor}
874 * dst.y = src.x - \lfloor src.x\rfloor
875 * dst.z = 2^{src.x}
876 * dst.w = 1.0
877 */
878 static void
879 ttn_exp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
880 {
881 nir_ssa_def *srcx = ttn_channel(b, src[0], X);
882
883 ttn_move_dest_masked(b, dest, nir_fexp2(b, nir_ffloor(b, srcx)),
884 TGSI_WRITEMASK_X);
885 ttn_move_dest_masked(b, dest, nir_fsub(b, srcx, nir_ffloor(b, srcx)),
886 TGSI_WRITEMASK_Y);
887 ttn_move_dest_masked(b, dest, nir_fexp2(b, srcx), TGSI_WRITEMASK_Z);
888 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
889 }
890
891 /* LOG - Approximate Logarithm Base 2
892 * dst.x = \lfloor\log_2{|src.x|}\rfloor
893 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
894 * dst.z = \log_2{|src.x|}
895 * dst.w = 1.0
896 */
897 static void
898 ttn_log(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
899 {
900 nir_ssa_def *abs_srcx = nir_fabs(b, ttn_channel(b, src[0], X));
901 nir_ssa_def *log2 = nir_flog2(b, abs_srcx);
902
903 ttn_move_dest_masked(b, dest, nir_ffloor(b, log2), TGSI_WRITEMASK_X);
904 ttn_move_dest_masked(b, dest,
905 nir_fdiv(b, abs_srcx, nir_fexp2(b, nir_ffloor(b, log2))),
906 TGSI_WRITEMASK_Y);
907 ttn_move_dest_masked(b, dest, nir_flog2(b, abs_srcx), TGSI_WRITEMASK_Z);
908 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
909 }
910
911 /* DST - Distance Vector
912 * dst.x = 1.0
913 * dst.y = src0.y \times src1.y
914 * dst.z = src0.z
915 * dst.w = src1.w
916 */
917 static void
918 ttn_dst(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
919 {
920 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_X);
921 ttn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), TGSI_WRITEMASK_Y);
922 ttn_move_dest_masked(b, dest, nir_fmov(b, src[0]), TGSI_WRITEMASK_Z);
923 ttn_move_dest_masked(b, dest, nir_fmov(b, src[1]), TGSI_WRITEMASK_W);
924 }
925
926 /* LIT - Light Coefficients
927 * dst.x = 1.0
928 * dst.y = max(src.x, 0.0)
929 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
930 * dst.w = 1.0
931 */
932 static void
933 ttn_lit(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
934 {
935 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_XW);
936
937 ttn_move_dest_masked(b, dest, nir_fmax(b, ttn_channel(b, src[0], X),
938 nir_imm_float(b, 0.0)), TGSI_WRITEMASK_Y);
939
940 if (dest.write_mask & TGSI_WRITEMASK_Z) {
941 nir_ssa_def *src0_y = ttn_channel(b, src[0], Y);
942 nir_ssa_def *wclamp = nir_fmax(b, nir_fmin(b, ttn_channel(b, src[0], W),
943 nir_imm_float(b, 128.0)),
944 nir_imm_float(b, -128.0));
945 nir_ssa_def *pow = nir_fpow(b, nir_fmax(b, src0_y, nir_imm_float(b, 0.0)),
946 wclamp);
947
948 ttn_move_dest_masked(b, dest,
949 nir_bcsel(b,
950 nir_fge(b,
951 nir_imm_float(b, 0.0),
952 ttn_channel(b, src[0], X)),
953 nir_imm_float(b, 0.0),
954 pow),
955 TGSI_WRITEMASK_Z);
956 }
957 }
958
959 /* SCS - Sine Cosine
960 * dst.x = \cos{src.x}
961 * dst.y = \sin{src.x}
962 * dst.z = 0.0
963 * dst.w = 1.0
964 */
965 static void
966 ttn_scs(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
967 {
968 ttn_move_dest_masked(b, dest, nir_fcos(b, ttn_channel(b, src[0], X)),
969 TGSI_WRITEMASK_X);
970 ttn_move_dest_masked(b, dest, nir_fsin(b, ttn_channel(b, src[0], X)),
971 TGSI_WRITEMASK_Y);
972 ttn_move_dest_masked(b, dest, nir_imm_float(b, 0.0), TGSI_WRITEMASK_Z);
973 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
974 }
975
976 static void
977 ttn_sle(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
978 {
979 ttn_move_dest(b, dest, nir_sge(b, src[1], src[0]));
980 }
981
982 static void
983 ttn_sgt(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
984 {
985 ttn_move_dest(b, dest, nir_slt(b, src[1], src[0]));
986 }
987
988 static void
989 ttn_dp2(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
990 {
991 ttn_move_dest(b, dest, nir_fdot2(b, src[0], src[1]));
992 }
993
994 static void
995 ttn_dp3(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
996 {
997 ttn_move_dest(b, dest, nir_fdot3(b, src[0], src[1]));
998 }
999
1000 static void
1001 ttn_dp4(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1002 {
1003 ttn_move_dest(b, dest, nir_fdot4(b, src[0], src[1]));
1004 }
1005
1006 static void
1007 ttn_umad(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1008 {
1009 ttn_move_dest(b, dest, nir_iadd(b, nir_imul(b, src[0], src[1]), src[2]));
1010 }
1011
1012 static void
1013 ttn_arr(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1014 {
1015 ttn_move_dest(b, dest, nir_ffloor(b, nir_fadd(b, src[0], nir_imm_float(b, 0.5))));
1016 }
1017
1018 static void
1019 ttn_cmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1020 {
1021 ttn_move_dest(b, dest, nir_bcsel(b,
1022 nir_flt(b, src[0], nir_imm_float(b, 0.0)),
1023 src[1], src[2]));
1024 }
1025
1026 static void
1027 ttn_ucmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1028 {
1029 ttn_move_dest(b, dest, nir_bcsel(b,
1030 nir_ine(b, src[0], nir_imm_int(b, 0)),
1031 src[1], src[2]));
1032 }
1033
1034 static void
1035 ttn_kill(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1036 {
1037 nir_intrinsic_instr *discard =
1038 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard);
1039 nir_builder_instr_insert(b, &discard->instr);
1040 b->shader->info.fs.uses_discard = true;
1041 }
1042
1043 static void
1044 ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1045 {
1046 nir_ssa_def *cmp = nir_bany_inequal4(b, nir_flt(b, src[0],
1047 nir_imm_float(b, 0.0)),
1048 nir_imm_int(b, 0));
1049 nir_intrinsic_instr *discard =
1050 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard_if);
1051 discard->src[0] = nir_src_for_ssa(cmp);
1052 nir_builder_instr_insert(b, &discard->instr);
1053 b->shader->info.fs.uses_discard = true;
1054 }
1055
1056 static void
1057 ttn_if(struct ttn_compile *c, nir_ssa_def *src, bool is_uint)
1058 {
1059 nir_builder *b = &c->build;
1060
1061 src = ttn_channel(b, src, X);
1062
1063 nir_if *if_stmt = nir_if_create(b->shader);
1064 if (is_uint) {
1065 if_stmt->condition = nir_src_for_ssa(nir_ine(b, src, nir_imm_int(b, 0)));
1066 } else {
1067 if_stmt->condition = nir_src_for_ssa(nir_fne(b, src, nir_imm_int(b, 0)));
1068 }
1069 nir_builder_cf_insert(b, &if_stmt->cf_node);
1070
1071 c->if_stack[c->if_stack_pos] = nir_after_cf_node(&if_stmt->cf_node);
1072 c->if_stack_pos++;
1073
1074 b->cursor = nir_after_cf_list(&if_stmt->then_list);
1075
1076 c->if_stack[c->if_stack_pos] = nir_after_cf_list(&if_stmt->else_list);
1077 c->if_stack_pos++;
1078 }
1079
1080 static void
1081 ttn_else(struct ttn_compile *c)
1082 {
1083 nir_builder *b = &c->build;
1084
1085 b->cursor = c->if_stack[c->if_stack_pos - 1];
1086 }
1087
1088 static void
1089 ttn_endif(struct ttn_compile *c)
1090 {
1091 nir_builder *b = &c->build;
1092
1093 c->if_stack_pos -= 2;
1094 b->cursor = c->if_stack[c->if_stack_pos];
1095 }
1096
1097 static void
1098 ttn_bgnloop(struct ttn_compile *c)
1099 {
1100 nir_builder *b = &c->build;
1101
1102 nir_loop *loop = nir_loop_create(b->shader);
1103 nir_builder_cf_insert(b, &loop->cf_node);
1104
1105 c->loop_stack[c->loop_stack_pos] = nir_after_cf_node(&loop->cf_node);
1106 c->loop_stack_pos++;
1107
1108 b->cursor = nir_after_cf_list(&loop->body);
1109 }
1110
1111 static void
1112 ttn_cont(nir_builder *b)
1113 {
1114 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_continue);
1115 nir_builder_instr_insert(b, &instr->instr);
1116 }
1117
1118 static void
1119 ttn_brk(nir_builder *b)
1120 {
1121 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
1122 nir_builder_instr_insert(b, &instr->instr);
1123 }
1124
1125 static void
1126 ttn_endloop(struct ttn_compile *c)
1127 {
1128 nir_builder *b = &c->build;
1129
1130 c->loop_stack_pos--;
1131 b->cursor = c->loop_stack[c->loop_stack_pos];
1132 }
1133
1134 static void
1135 setup_texture_info(nir_tex_instr *instr, unsigned texture)
1136 {
1137 switch (texture) {
1138 case TGSI_TEXTURE_BUFFER:
1139 instr->sampler_dim = GLSL_SAMPLER_DIM_BUF;
1140 break;
1141 case TGSI_TEXTURE_1D:
1142 instr->sampler_dim = GLSL_SAMPLER_DIM_1D;
1143 break;
1144 case TGSI_TEXTURE_1D_ARRAY:
1145 instr->sampler_dim = GLSL_SAMPLER_DIM_1D;
1146 instr->is_array = true;
1147 break;
1148 case TGSI_TEXTURE_SHADOW1D:
1149 instr->sampler_dim = GLSL_SAMPLER_DIM_1D;
1150 instr->is_shadow = true;
1151 break;
1152 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1153 instr->sampler_dim = GLSL_SAMPLER_DIM_1D;
1154 instr->is_shadow = true;
1155 instr->is_array = true;
1156 break;
1157 case TGSI_TEXTURE_2D:
1158 instr->sampler_dim = GLSL_SAMPLER_DIM_2D;
1159 break;
1160 case TGSI_TEXTURE_2D_ARRAY:
1161 instr->sampler_dim = GLSL_SAMPLER_DIM_2D;
1162 instr->is_array = true;
1163 break;
1164 case TGSI_TEXTURE_2D_MSAA:
1165 instr->sampler_dim = GLSL_SAMPLER_DIM_MS;
1166 break;
1167 case TGSI_TEXTURE_2D_ARRAY_MSAA:
1168 instr->sampler_dim = GLSL_SAMPLER_DIM_MS;
1169 instr->is_array = true;
1170 break;
1171 case TGSI_TEXTURE_SHADOW2D:
1172 instr->sampler_dim = GLSL_SAMPLER_DIM_2D;
1173 instr->is_shadow = true;
1174 break;
1175 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1176 instr->sampler_dim = GLSL_SAMPLER_DIM_2D;
1177 instr->is_shadow = true;
1178 instr->is_array = true;
1179 break;
1180 case TGSI_TEXTURE_3D:
1181 instr->sampler_dim = GLSL_SAMPLER_DIM_3D;
1182 break;
1183 case TGSI_TEXTURE_CUBE:
1184 instr->sampler_dim = GLSL_SAMPLER_DIM_CUBE;
1185 break;
1186 case TGSI_TEXTURE_CUBE_ARRAY:
1187 instr->sampler_dim = GLSL_SAMPLER_DIM_CUBE;
1188 instr->is_array = true;
1189 break;
1190 case TGSI_TEXTURE_SHADOWCUBE:
1191 instr->sampler_dim = GLSL_SAMPLER_DIM_CUBE;
1192 instr->is_shadow = true;
1193 break;
1194 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1195 instr->sampler_dim = GLSL_SAMPLER_DIM_CUBE;
1196 instr->is_shadow = true;
1197 instr->is_array = true;
1198 break;
1199 case TGSI_TEXTURE_RECT:
1200 instr->sampler_dim = GLSL_SAMPLER_DIM_RECT;
1201 break;
1202 case TGSI_TEXTURE_SHADOWRECT:
1203 instr->sampler_dim = GLSL_SAMPLER_DIM_RECT;
1204 instr->is_shadow = true;
1205 break;
1206 default:
1207 fprintf(stderr, "Unknown TGSI texture target %d\n", texture);
1208 abort();
1209 }
1210 }
1211
1212 static void
1213 ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1214 {
1215 nir_builder *b = &c->build;
1216 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1217 nir_tex_instr *instr;
1218 nir_texop op;
1219 unsigned num_srcs, samp = 1, sview, i;
1220
1221 switch (tgsi_inst->Instruction.Opcode) {
1222 case TGSI_OPCODE_TEX:
1223 op = nir_texop_tex;
1224 num_srcs = 1;
1225 break;
1226 case TGSI_OPCODE_TEX2:
1227 op = nir_texop_tex;
1228 num_srcs = 1;
1229 samp = 2;
1230 break;
1231 case TGSI_OPCODE_TXP:
1232 op = nir_texop_tex;
1233 num_srcs = 2;
1234 break;
1235 case TGSI_OPCODE_TXB:
1236 op = nir_texop_txb;
1237 num_srcs = 2;
1238 break;
1239 case TGSI_OPCODE_TXB2:
1240 op = nir_texop_txb;
1241 num_srcs = 2;
1242 samp = 2;
1243 break;
1244 case TGSI_OPCODE_TXL:
1245 op = nir_texop_txl;
1246 num_srcs = 2;
1247 break;
1248 case TGSI_OPCODE_TXL2:
1249 op = nir_texop_txl;
1250 num_srcs = 2;
1251 samp = 2;
1252 break;
1253 case TGSI_OPCODE_TXF:
1254 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
1255 tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1256 op = nir_texop_txf_ms;
1257 } else {
1258 op = nir_texop_txf;
1259 }
1260 num_srcs = 2;
1261 break;
1262 case TGSI_OPCODE_TXD:
1263 op = nir_texop_txd;
1264 num_srcs = 3;
1265 samp = 3;
1266 break;
1267 case TGSI_OPCODE_LODQ:
1268 op = nir_texop_lod;
1269 num_srcs = 1;
1270 break;
1271
1272 default:
1273 fprintf(stderr, "unknown TGSI tex op %d\n", tgsi_inst->Instruction.Opcode);
1274 abort();
1275 }
1276
1277 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
1278 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1279 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
1280 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1281 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
1282 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
1283 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1284 num_srcs++;
1285 }
1286
1287 num_srcs += tgsi_inst->Texture.NumOffsets;
1288
1289 instr = nir_tex_instr_create(b->shader, num_srcs);
1290 instr->op = op;
1291
1292 setup_texture_info(instr, tgsi_inst->Texture.Texture);
1293
1294 switch (instr->sampler_dim) {
1295 case GLSL_SAMPLER_DIM_1D:
1296 case GLSL_SAMPLER_DIM_BUF:
1297 instr->coord_components = 1;
1298 break;
1299 case GLSL_SAMPLER_DIM_2D:
1300 case GLSL_SAMPLER_DIM_RECT:
1301 case GLSL_SAMPLER_DIM_EXTERNAL:
1302 case GLSL_SAMPLER_DIM_MS:
1303 instr->coord_components = 2;
1304 break;
1305 case GLSL_SAMPLER_DIM_3D:
1306 case GLSL_SAMPLER_DIM_CUBE:
1307 instr->coord_components = 3;
1308 break;
1309 case GLSL_SAMPLER_DIM_SUBPASS:
1310 case GLSL_SAMPLER_DIM_SUBPASS_MS:
1311 unreachable("invalid sampler_dim");
1312 }
1313
1314 if (instr->is_array)
1315 instr->coord_components++;
1316
1317 assert(tgsi_inst->Src[samp].Register.File == TGSI_FILE_SAMPLER);
1318 instr->texture_index = tgsi_inst->Src[samp].Register.Index;
1319 instr->sampler_index = tgsi_inst->Src[samp].Register.Index;
1320
1321 /* TODO if we supported any opc's which take an explicit SVIEW
1322 * src, we would use that here instead. But for the "legacy"
1323 * texture opc's the SVIEW index is same as SAMP index:
1324 */
1325 sview = instr->texture_index;
1326
1327 if (op == nir_texop_lod) {
1328 instr->dest_type = nir_type_float;
1329 } else if (sview < c->num_samp_types) {
1330 instr->dest_type = c->samp_types[sview];
1331 } else {
1332 instr->dest_type = nir_type_float;
1333 }
1334
1335 unsigned src_number = 0;
1336
1337 instr->src[src_number].src =
1338 nir_src_for_ssa(nir_swizzle(b, src[0], SWIZ(X, Y, Z, W),
1339 instr->coord_components, false));
1340 instr->src[src_number].src_type = nir_tex_src_coord;
1341 src_number++;
1342
1343 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1344 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1345 instr->src[src_number].src_type = nir_tex_src_projector;
1346 src_number++;
1347 }
1348
1349 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
1350 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1351 instr->src[src_number].src_type = nir_tex_src_bias;
1352 src_number++;
1353 }
1354
1355 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB2) {
1356 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1357 instr->src[src_number].src_type = nir_tex_src_bias;
1358 src_number++;
1359 }
1360
1361 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL) {
1362 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1363 instr->src[src_number].src_type = nir_tex_src_lod;
1364 src_number++;
1365 }
1366
1367 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
1368 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1369 instr->src[src_number].src_type = nir_tex_src_lod;
1370 src_number++;
1371 }
1372
1373 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
1374 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1375 if (op == nir_texop_txf_ms)
1376 instr->src[src_number].src_type = nir_tex_src_ms_index;
1377 else
1378 instr->src[src_number].src_type = nir_tex_src_lod;
1379 src_number++;
1380 }
1381
1382 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
1383 instr->src[src_number].src_type = nir_tex_src_ddx;
1384 instr->src[src_number].src =
1385 nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1386 nir_tex_instr_src_size(instr, src_number),
1387 false));
1388 src_number++;
1389 instr->src[src_number].src_type = nir_tex_src_ddy;
1390 instr->src[src_number].src =
1391 nir_src_for_ssa(nir_swizzle(b, src[2], SWIZ(X, Y, Z, W),
1392 nir_tex_instr_src_size(instr, src_number),
1393 false));
1394 src_number++;
1395 }
1396
1397 if (instr->is_shadow) {
1398 if (instr->coord_components == 4)
1399 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1400 else if (instr->coord_components == 3)
1401 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1402 else
1403 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], Z));
1404
1405 instr->src[src_number].src_type = nir_tex_src_comparator;
1406 src_number++;
1407 }
1408
1409 for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) {
1410 struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i];
1411 /* since TexOffset ins't using tgsi_full_src_register we get to
1412 * do some extra gymnastics:
1413 */
1414 nir_alu_src src;
1415
1416 memset(&src, 0, sizeof(src));
1417
1418 src.src = ttn_src_for_file_and_index(c,
1419 tex_offset->File,
1420 tex_offset->Index,
1421 NULL, NULL, NULL);
1422
1423 src.swizzle[0] = tex_offset->SwizzleX;
1424 src.swizzle[1] = tex_offset->SwizzleY;
1425 src.swizzle[2] = tex_offset->SwizzleZ;
1426 src.swizzle[3] = TGSI_SWIZZLE_W;
1427
1428 instr->src[src_number].src_type = nir_tex_src_offset;
1429 instr->src[src_number].src = nir_src_for_ssa(
1430 nir_fmov_alu(b, src, nir_tex_instr_src_size(instr, src_number)));
1431 src_number++;
1432 }
1433
1434 assert(src_number == num_srcs);
1435
1436 nir_ssa_dest_init(&instr->instr, &instr->dest,
1437 nir_tex_instr_dest_size(instr),
1438 32, NULL);
1439 nir_builder_instr_insert(b, &instr->instr);
1440
1441 /* Resolve the writemask on the texture op. */
1442 ttn_move_dest(b, dest, &instr->dest.ssa);
1443 }
1444
1445 /* TGSI_OPCODE_TXQ is actually two distinct operations:
1446 *
1447 * dst.x = texture\_width(unit, lod)
1448 * dst.y = texture\_height(unit, lod)
1449 * dst.z = texture\_depth(unit, lod)
1450 * dst.w = texture\_levels(unit)
1451 *
1452 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels
1453 */
1454 static void
1455 ttn_txq(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1456 {
1457 nir_builder *b = &c->build;
1458 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1459 nir_tex_instr *txs, *qlv;
1460
1461 txs = nir_tex_instr_create(b->shader, 1);
1462 txs->op = nir_texop_txs;
1463 setup_texture_info(txs, tgsi_inst->Texture.Texture);
1464
1465 qlv = nir_tex_instr_create(b->shader, 0);
1466 qlv->op = nir_texop_query_levels;
1467 setup_texture_info(qlv, tgsi_inst->Texture.Texture);
1468
1469 assert(tgsi_inst->Src[1].Register.File == TGSI_FILE_SAMPLER);
1470 txs->texture_index = tgsi_inst->Src[1].Register.Index;
1471 qlv->texture_index = tgsi_inst->Src[1].Register.Index;
1472
1473 /* only single src, the lod: */
1474 txs->src[0].src = nir_src_for_ssa(ttn_channel(b, src[0], X));
1475 txs->src[0].src_type = nir_tex_src_lod;
1476
1477 nir_ssa_dest_init(&txs->instr, &txs->dest,
1478 nir_tex_instr_dest_size(txs), 32, NULL);
1479 nir_builder_instr_insert(b, &txs->instr);
1480
1481 nir_ssa_dest_init(&qlv->instr, &qlv->dest, 1, 32, NULL);
1482 nir_builder_instr_insert(b, &qlv->instr);
1483
1484 ttn_move_dest_masked(b, dest, &txs->dest.ssa, TGSI_WRITEMASK_XYZ);
1485 ttn_move_dest_masked(b, dest, &qlv->dest.ssa, TGSI_WRITEMASK_W);
1486 }
1487
1488 static const nir_op op_trans[TGSI_OPCODE_LAST] = {
1489 [TGSI_OPCODE_ARL] = 0,
1490 [TGSI_OPCODE_MOV] = nir_op_fmov,
1491 [TGSI_OPCODE_LIT] = 0,
1492 [TGSI_OPCODE_RCP] = nir_op_frcp,
1493 [TGSI_OPCODE_RSQ] = nir_op_frsq,
1494 [TGSI_OPCODE_EXP] = 0,
1495 [TGSI_OPCODE_LOG] = 0,
1496 [TGSI_OPCODE_MUL] = nir_op_fmul,
1497 [TGSI_OPCODE_ADD] = nir_op_fadd,
1498 [TGSI_OPCODE_DP3] = 0,
1499 [TGSI_OPCODE_DP4] = 0,
1500 [TGSI_OPCODE_DST] = 0,
1501 [TGSI_OPCODE_MIN] = nir_op_fmin,
1502 [TGSI_OPCODE_MAX] = nir_op_fmax,
1503 [TGSI_OPCODE_SLT] = nir_op_slt,
1504 [TGSI_OPCODE_SGE] = nir_op_sge,
1505 [TGSI_OPCODE_MAD] = nir_op_ffma,
1506 [TGSI_OPCODE_LRP] = 0,
1507 [TGSI_OPCODE_SQRT] = nir_op_fsqrt,
1508 [TGSI_OPCODE_FRC] = nir_op_ffract,
1509 [TGSI_OPCODE_FLR] = nir_op_ffloor,
1510 [TGSI_OPCODE_ROUND] = nir_op_fround_even,
1511 [TGSI_OPCODE_EX2] = nir_op_fexp2,
1512 [TGSI_OPCODE_LG2] = nir_op_flog2,
1513 [TGSI_OPCODE_POW] = nir_op_fpow,
1514 [TGSI_OPCODE_COS] = nir_op_fcos,
1515 [TGSI_OPCODE_DDX] = nir_op_fddx,
1516 [TGSI_OPCODE_DDY] = nir_op_fddy,
1517 [TGSI_OPCODE_KILL] = 0,
1518 [TGSI_OPCODE_PK2H] = 0, /* XXX */
1519 [TGSI_OPCODE_PK2US] = 0, /* XXX */
1520 [TGSI_OPCODE_PK4B] = 0, /* XXX */
1521 [TGSI_OPCODE_PK4UB] = 0, /* XXX */
1522 [TGSI_OPCODE_SEQ] = nir_op_seq,
1523 [TGSI_OPCODE_SGT] = 0,
1524 [TGSI_OPCODE_SIN] = nir_op_fsin,
1525 [TGSI_OPCODE_SNE] = nir_op_sne,
1526 [TGSI_OPCODE_SLE] = 0,
1527 [TGSI_OPCODE_TEX] = 0,
1528 [TGSI_OPCODE_TXD] = 0,
1529 [TGSI_OPCODE_TXP] = 0,
1530 [TGSI_OPCODE_UP2H] = 0, /* XXX */
1531 [TGSI_OPCODE_UP2US] = 0, /* XXX */
1532 [TGSI_OPCODE_UP4B] = 0, /* XXX */
1533 [TGSI_OPCODE_UP4UB] = 0, /* XXX */
1534 [TGSI_OPCODE_ARR] = 0,
1535
1536 /* No function calls, yet. */
1537 [TGSI_OPCODE_CAL] = 0, /* XXX */
1538 [TGSI_OPCODE_RET] = 0, /* XXX */
1539
1540 [TGSI_OPCODE_SSG] = nir_op_fsign,
1541 [TGSI_OPCODE_CMP] = 0,
1542 [TGSI_OPCODE_SCS] = 0,
1543 [TGSI_OPCODE_TXB] = 0,
1544 [TGSI_OPCODE_DIV] = nir_op_fdiv,
1545 [TGSI_OPCODE_DP2] = 0,
1546 [TGSI_OPCODE_TXL] = 0,
1547
1548 [TGSI_OPCODE_BRK] = 0,
1549 [TGSI_OPCODE_IF] = 0,
1550 [TGSI_OPCODE_UIF] = 0,
1551 [TGSI_OPCODE_ELSE] = 0,
1552 [TGSI_OPCODE_ENDIF] = 0,
1553
1554 [TGSI_OPCODE_DDX_FINE] = nir_op_fddx_fine,
1555 [TGSI_OPCODE_DDY_FINE] = nir_op_fddy_fine,
1556
1557 [TGSI_OPCODE_CEIL] = nir_op_fceil,
1558 [TGSI_OPCODE_I2F] = nir_op_i2f32,
1559 [TGSI_OPCODE_NOT] = nir_op_inot,
1560 [TGSI_OPCODE_TRUNC] = nir_op_ftrunc,
1561 [TGSI_OPCODE_SHL] = nir_op_ishl,
1562 [TGSI_OPCODE_AND] = nir_op_iand,
1563 [TGSI_OPCODE_OR] = nir_op_ior,
1564 [TGSI_OPCODE_MOD] = nir_op_umod,
1565 [TGSI_OPCODE_XOR] = nir_op_ixor,
1566 [TGSI_OPCODE_TXF] = 0,
1567 [TGSI_OPCODE_TXQ] = 0,
1568
1569 [TGSI_OPCODE_CONT] = 0,
1570
1571 [TGSI_OPCODE_EMIT] = 0, /* XXX */
1572 [TGSI_OPCODE_ENDPRIM] = 0, /* XXX */
1573
1574 [TGSI_OPCODE_BGNLOOP] = 0,
1575 [TGSI_OPCODE_BGNSUB] = 0, /* XXX: no function calls */
1576 [TGSI_OPCODE_ENDLOOP] = 0,
1577 [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */
1578
1579 [TGSI_OPCODE_NOP] = 0,
1580 [TGSI_OPCODE_FSEQ] = nir_op_feq,
1581 [TGSI_OPCODE_FSGE] = nir_op_fge,
1582 [TGSI_OPCODE_FSLT] = nir_op_flt,
1583 [TGSI_OPCODE_FSNE] = nir_op_fne,
1584
1585 /* No control flow yet */
1586 [TGSI_OPCODE_BREAKC] = 0, /* not emitted by glsl_to_tgsi.cpp */
1587
1588 [TGSI_OPCODE_KILL_IF] = 0,
1589
1590 [TGSI_OPCODE_END] = 0,
1591
1592 [TGSI_OPCODE_F2I] = nir_op_f2i32,
1593 [TGSI_OPCODE_IDIV] = nir_op_idiv,
1594 [TGSI_OPCODE_IMAX] = nir_op_imax,
1595 [TGSI_OPCODE_IMIN] = nir_op_imin,
1596 [TGSI_OPCODE_INEG] = nir_op_ineg,
1597 [TGSI_OPCODE_ISGE] = nir_op_ige,
1598 [TGSI_OPCODE_ISHR] = nir_op_ishr,
1599 [TGSI_OPCODE_ISLT] = nir_op_ilt,
1600 [TGSI_OPCODE_F2U] = nir_op_f2u32,
1601 [TGSI_OPCODE_U2F] = nir_op_u2f32,
1602 [TGSI_OPCODE_UADD] = nir_op_iadd,
1603 [TGSI_OPCODE_UDIV] = nir_op_udiv,
1604 [TGSI_OPCODE_UMAD] = 0,
1605 [TGSI_OPCODE_UMAX] = nir_op_umax,
1606 [TGSI_OPCODE_UMIN] = nir_op_umin,
1607 [TGSI_OPCODE_UMOD] = nir_op_umod,
1608 [TGSI_OPCODE_UMUL] = nir_op_imul,
1609 [TGSI_OPCODE_USEQ] = nir_op_ieq,
1610 [TGSI_OPCODE_USGE] = nir_op_uge,
1611 [TGSI_OPCODE_USHR] = nir_op_ushr,
1612 [TGSI_OPCODE_USLT] = nir_op_ult,
1613 [TGSI_OPCODE_USNE] = nir_op_ine,
1614
1615 [TGSI_OPCODE_SWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
1616 [TGSI_OPCODE_CASE] = 0, /* not emitted by glsl_to_tgsi.cpp */
1617 [TGSI_OPCODE_DEFAULT] = 0, /* not emitted by glsl_to_tgsi.cpp */
1618 [TGSI_OPCODE_ENDSWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
1619
1620 /* XXX: SAMPLE opcodes */
1621
1622 [TGSI_OPCODE_UARL] = nir_op_imov,
1623 [TGSI_OPCODE_UCMP] = 0,
1624 [TGSI_OPCODE_IABS] = nir_op_iabs,
1625 [TGSI_OPCODE_ISSG] = nir_op_isign,
1626
1627 /* XXX: atomics */
1628
1629 [TGSI_OPCODE_TEX2] = 0,
1630 [TGSI_OPCODE_TXB2] = 0,
1631 [TGSI_OPCODE_TXL2] = 0,
1632
1633 [TGSI_OPCODE_IMUL_HI] = nir_op_imul_high,
1634 [TGSI_OPCODE_UMUL_HI] = nir_op_umul_high,
1635
1636 [TGSI_OPCODE_TG4] = 0,
1637 [TGSI_OPCODE_LODQ] = 0,
1638
1639 [TGSI_OPCODE_IBFE] = nir_op_ibitfield_extract,
1640 [TGSI_OPCODE_UBFE] = nir_op_ubitfield_extract,
1641 [TGSI_OPCODE_BFI] = nir_op_bitfield_insert,
1642 [TGSI_OPCODE_BREV] = nir_op_bitfield_reverse,
1643 [TGSI_OPCODE_POPC] = nir_op_bit_count,
1644 [TGSI_OPCODE_LSB] = nir_op_find_lsb,
1645 [TGSI_OPCODE_IMSB] = nir_op_ifind_msb,
1646 [TGSI_OPCODE_UMSB] = nir_op_ufind_msb,
1647
1648 [TGSI_OPCODE_INTERP_CENTROID] = 0, /* XXX */
1649 [TGSI_OPCODE_INTERP_SAMPLE] = 0, /* XXX */
1650 [TGSI_OPCODE_INTERP_OFFSET] = 0, /* XXX */
1651 };
1652
1653 static void
1654 ttn_emit_instruction(struct ttn_compile *c)
1655 {
1656 nir_builder *b = &c->build;
1657 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1658 unsigned i;
1659 unsigned tgsi_op = tgsi_inst->Instruction.Opcode;
1660 struct tgsi_full_dst_register *tgsi_dst = &tgsi_inst->Dst[0];
1661
1662 if (tgsi_op == TGSI_OPCODE_END)
1663 return;
1664
1665 nir_ssa_def *src[TGSI_FULL_MAX_SRC_REGISTERS];
1666 for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) {
1667 src[i] = ttn_get_src(c, &tgsi_inst->Src[i]);
1668 }
1669 nir_alu_dest dest = ttn_get_dest(c, tgsi_dst);
1670
1671 switch (tgsi_op) {
1672 case TGSI_OPCODE_RSQ:
1673 ttn_move_dest(b, dest, nir_frsq(b, ttn_channel(b, src[0], X)));
1674 break;
1675
1676 case TGSI_OPCODE_SQRT:
1677 ttn_move_dest(b, dest, nir_fsqrt(b, ttn_channel(b, src[0], X)));
1678 break;
1679
1680 case TGSI_OPCODE_RCP:
1681 ttn_move_dest(b, dest, nir_frcp(b, ttn_channel(b, src[0], X)));
1682 break;
1683
1684 case TGSI_OPCODE_EX2:
1685 ttn_move_dest(b, dest, nir_fexp2(b, ttn_channel(b, src[0], X)));
1686 break;
1687
1688 case TGSI_OPCODE_LG2:
1689 ttn_move_dest(b, dest, nir_flog2(b, ttn_channel(b, src[0], X)));
1690 break;
1691
1692 case TGSI_OPCODE_POW:
1693 ttn_move_dest(b, dest, nir_fpow(b,
1694 ttn_channel(b, src[0], X),
1695 ttn_channel(b, src[1], X)));
1696 break;
1697
1698 case TGSI_OPCODE_COS:
1699 ttn_move_dest(b, dest, nir_fcos(b, ttn_channel(b, src[0], X)));
1700 break;
1701
1702 case TGSI_OPCODE_SIN:
1703 ttn_move_dest(b, dest, nir_fsin(b, ttn_channel(b, src[0], X)));
1704 break;
1705
1706 case TGSI_OPCODE_ARL:
1707 ttn_arl(b, op_trans[tgsi_op], dest, src);
1708 break;
1709
1710 case TGSI_OPCODE_EXP:
1711 ttn_exp(b, op_trans[tgsi_op], dest, src);
1712 break;
1713
1714 case TGSI_OPCODE_LOG:
1715 ttn_log(b, op_trans[tgsi_op], dest, src);
1716 break;
1717
1718 case TGSI_OPCODE_DST:
1719 ttn_dst(b, op_trans[tgsi_op], dest, src);
1720 break;
1721
1722 case TGSI_OPCODE_LIT:
1723 ttn_lit(b, op_trans[tgsi_op], dest, src);
1724 break;
1725
1726 case TGSI_OPCODE_DP2:
1727 ttn_dp2(b, op_trans[tgsi_op], dest, src);
1728 break;
1729
1730 case TGSI_OPCODE_DP3:
1731 ttn_dp3(b, op_trans[tgsi_op], dest, src);
1732 break;
1733
1734 case TGSI_OPCODE_DP4:
1735 ttn_dp4(b, op_trans[tgsi_op], dest, src);
1736 break;
1737
1738 case TGSI_OPCODE_UMAD:
1739 ttn_umad(b, op_trans[tgsi_op], dest, src);
1740 break;
1741
1742 case TGSI_OPCODE_LRP:
1743 ttn_move_dest(b, dest, nir_flrp(b, src[2], src[1], src[0]));
1744 break;
1745
1746 case TGSI_OPCODE_KILL:
1747 ttn_kill(b, op_trans[tgsi_op], dest, src);
1748 break;
1749
1750 case TGSI_OPCODE_ARR:
1751 ttn_arr(b, op_trans[tgsi_op], dest, src);
1752 break;
1753
1754 case TGSI_OPCODE_CMP:
1755 ttn_cmp(b, op_trans[tgsi_op], dest, src);
1756 break;
1757
1758 case TGSI_OPCODE_UCMP:
1759 ttn_ucmp(b, op_trans[tgsi_op], dest, src);
1760 break;
1761
1762 case TGSI_OPCODE_SCS:
1763 ttn_scs(b, op_trans[tgsi_op], dest, src);
1764 break;
1765
1766 case TGSI_OPCODE_SGT:
1767 ttn_sgt(b, op_trans[tgsi_op], dest, src);
1768 break;
1769
1770 case TGSI_OPCODE_SLE:
1771 ttn_sle(b, op_trans[tgsi_op], dest, src);
1772 break;
1773
1774 case TGSI_OPCODE_KILL_IF:
1775 ttn_kill_if(b, op_trans[tgsi_op], dest, src);
1776 break;
1777
1778 case TGSI_OPCODE_TEX:
1779 case TGSI_OPCODE_TXP:
1780 case TGSI_OPCODE_TXL:
1781 case TGSI_OPCODE_TXB:
1782 case TGSI_OPCODE_TXD:
1783 case TGSI_OPCODE_TEX2:
1784 case TGSI_OPCODE_TXL2:
1785 case TGSI_OPCODE_TXB2:
1786 case TGSI_OPCODE_TXF:
1787 case TGSI_OPCODE_TG4:
1788 case TGSI_OPCODE_LODQ:
1789 ttn_tex(c, dest, src);
1790 break;
1791
1792 case TGSI_OPCODE_TXQ:
1793 ttn_txq(c, dest, src);
1794 break;
1795
1796 case TGSI_OPCODE_NOP:
1797 break;
1798
1799 case TGSI_OPCODE_IF:
1800 ttn_if(c, src[0], false);
1801 break;
1802
1803 case TGSI_OPCODE_UIF:
1804 ttn_if(c, src[0], true);
1805 break;
1806
1807 case TGSI_OPCODE_ELSE:
1808 ttn_else(c);
1809 break;
1810
1811 case TGSI_OPCODE_ENDIF:
1812 ttn_endif(c);
1813 break;
1814
1815 case TGSI_OPCODE_BGNLOOP:
1816 ttn_bgnloop(c);
1817 break;
1818
1819 case TGSI_OPCODE_BRK:
1820 ttn_brk(b);
1821 break;
1822
1823 case TGSI_OPCODE_CONT:
1824 ttn_cont(b);
1825 break;
1826
1827 case TGSI_OPCODE_ENDLOOP:
1828 ttn_endloop(c);
1829 break;
1830
1831 default:
1832 if (op_trans[tgsi_op] != 0 || tgsi_op == TGSI_OPCODE_MOV) {
1833 ttn_alu(b, op_trans[tgsi_op], dest, src);
1834 } else {
1835 fprintf(stderr, "unknown TGSI opcode: %s\n",
1836 tgsi_get_opcode_name(tgsi_op));
1837 abort();
1838 }
1839 break;
1840 }
1841
1842 if (tgsi_inst->Instruction.Saturate) {
1843 assert(!dest.dest.is_ssa);
1844 ttn_move_dest(b, dest, nir_fsat(b, ttn_src_for_dest(b, &dest)));
1845 }
1846
1847 /* if the dst has a matching var, append store_var to move
1848 * output from reg to var
1849 */
1850 nir_variable *var = ttn_get_var(c, tgsi_dst);
1851 if (var) {
1852 unsigned index = tgsi_dst->Register.Index;
1853 unsigned offset = c->temp_regs[index].offset;
1854 nir_intrinsic_instr *store =
1855 nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_var);
1856 struct tgsi_ind_register *indirect = tgsi_dst->Register.Indirect ?
1857 &tgsi_dst->Indirect : NULL;
1858
1859 store->num_components = 4;
1860 nir_intrinsic_set_write_mask(store, dest.write_mask);
1861 store->variables[0] = ttn_array_deref(c, store, var, offset, indirect);
1862 store->src[0] = nir_src_for_reg(dest.dest.reg.reg);
1863
1864 nir_builder_instr_insert(b, &store->instr);
1865 }
1866 }
1867
1868 /**
1869 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
1870 * variables at the end of the shader.
1871 *
1872 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
1873 * written, because there's no output load intrinsic, which means we couldn't
1874 * handle writemasks.
1875 */
1876 static void
1877 ttn_add_output_stores(struct ttn_compile *c)
1878 {
1879 nir_builder *b = &c->build;
1880
1881 foreach_list_typed(nir_variable, var, node, &b->shader->outputs) {
1882 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1883 unsigned i;
1884
1885 for (i = 0; i < array_len; i++) {
1886 nir_intrinsic_instr *store =
1887 nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_output);
1888 unsigned loc = var->data.driver_location + i;
1889
1890 nir_src src = nir_src_for_reg(c->output_regs[loc].reg);
1891 src.reg.base_offset = c->output_regs[loc].offset;
1892
1893 if (c->build.shader->stage == MESA_SHADER_FRAGMENT &&
1894 var->data.location == FRAG_RESULT_DEPTH) {
1895 /* TGSI uses TGSI_SEMANTIC_POSITION.z for the depth output, while
1896 * NIR uses a single float FRAG_RESULT_DEPTH.
1897 */
1898 src = nir_src_for_ssa(nir_channel(b, nir_ssa_for_src(b, src, 4), 2));
1899 store->num_components = 1;
1900 } else {
1901 store->num_components = 4;
1902 }
1903 store->src[0] = src;
1904
1905 nir_intrinsic_set_base(store, loc);
1906 nir_intrinsic_set_write_mask(store, 0xf);
1907 store->src[1] = nir_src_for_ssa(nir_imm_int(b, 0));
1908 nir_builder_instr_insert(b, &store->instr);
1909 }
1910 }
1911 }
1912
1913 static gl_shader_stage
1914 tgsi_processor_to_shader_stage(unsigned processor)
1915 {
1916 switch (processor) {
1917 case PIPE_SHADER_FRAGMENT: return MESA_SHADER_FRAGMENT;
1918 case PIPE_SHADER_VERTEX: return MESA_SHADER_VERTEX;
1919 case PIPE_SHADER_GEOMETRY: return MESA_SHADER_GEOMETRY;
1920 case PIPE_SHADER_TESS_CTRL: return MESA_SHADER_TESS_CTRL;
1921 case PIPE_SHADER_TESS_EVAL: return MESA_SHADER_TESS_EVAL;
1922 case PIPE_SHADER_COMPUTE: return MESA_SHADER_COMPUTE;
1923 default:
1924 unreachable("invalid TGSI processor");
1925 }
1926 }
1927
1928 struct nir_shader *
1929 tgsi_to_nir(const void *tgsi_tokens,
1930 const nir_shader_compiler_options *options)
1931 {
1932 struct tgsi_parse_context parser;
1933 struct tgsi_shader_info scan;
1934 struct ttn_compile *c;
1935 struct nir_shader *s;
1936 int ret;
1937
1938 c = rzalloc(NULL, struct ttn_compile);
1939
1940 tgsi_scan_shader(tgsi_tokens, &scan);
1941 c->scan = &scan;
1942
1943 nir_builder_init_simple_shader(&c->build, NULL,
1944 tgsi_processor_to_shader_stage(scan.processor),
1945 options);
1946 s = c->build.shader;
1947
1948 s->num_inputs = scan.file_max[TGSI_FILE_INPUT] + 1;
1949 s->num_uniforms = scan.const_file_max[0] + 1;
1950 s->num_outputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
1951
1952 c->output_regs = rzalloc_array(c, struct ttn_reg_info,
1953 scan.file_max[TGSI_FILE_OUTPUT] + 1);
1954 c->temp_regs = rzalloc_array(c, struct ttn_reg_info,
1955 scan.file_max[TGSI_FILE_TEMPORARY] + 1);
1956 c->imm_defs = rzalloc_array(c, nir_ssa_def *,
1957 scan.file_max[TGSI_FILE_IMMEDIATE] + 1);
1958
1959 c->num_samp_types = scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1;
1960 c->samp_types = rzalloc_array(c, nir_alu_type, c->num_samp_types);
1961
1962 c->if_stack = rzalloc_array(c, nir_cursor,
1963 (scan.opcode_count[TGSI_OPCODE_IF] +
1964 scan.opcode_count[TGSI_OPCODE_UIF]) * 2);
1965 c->loop_stack = rzalloc_array(c, nir_cursor,
1966 scan.opcode_count[TGSI_OPCODE_BGNLOOP]);
1967
1968 ret = tgsi_parse_init(&parser, tgsi_tokens);
1969 assert(ret == TGSI_PARSE_OK);
1970
1971 while (!tgsi_parse_end_of_tokens(&parser)) {
1972 tgsi_parse_token(&parser);
1973 c->token = &parser.FullToken;
1974
1975 switch (parser.FullToken.Token.Type) {
1976 case TGSI_TOKEN_TYPE_DECLARATION:
1977 ttn_emit_declaration(c);
1978 break;
1979
1980 case TGSI_TOKEN_TYPE_INSTRUCTION:
1981 ttn_emit_instruction(c);
1982 break;
1983
1984 case TGSI_TOKEN_TYPE_IMMEDIATE:
1985 ttn_emit_immediate(c);
1986 break;
1987 }
1988 }
1989
1990 tgsi_parse_free(&parser);
1991
1992 ttn_add_output_stores(c);
1993
1994 ralloc_free(c);
1995 return s;
1996 }