2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #pragma GCC diagnostic ignored "-Wdeclaration-after-statement"
29 #include "util/ralloc.h"
30 #include "glsl/nir/nir.h"
31 #include "glsl/nir/nir_control_flow.h"
32 #include "glsl/nir/nir_builder.h"
33 #include "glsl/list.h"
34 #include "glsl/nir/shader_enums.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "tgsi/tgsi_parse.h"
38 #include "tgsi/tgsi_dump.h"
39 #include "tgsi/tgsi_info.h"
40 #include "tgsi/tgsi_scan.h"
42 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
50 /** nir register containing this TGSI index. */
53 /** Offset (in vec4s) from the start of var for this TGSI index. */
58 union tgsi_full_token
*token
;
60 struct tgsi_shader_info
*scan
;
62 struct ttn_reg_info
*output_regs
;
63 struct ttn_reg_info
*temp_regs
;
64 nir_ssa_def
**imm_defs
;
66 unsigned num_samp_types
;
67 nir_alu_type
*samp_types
;
69 nir_register
*addr_reg
;
72 * Stack of nir_cursors where instructions should be pushed as we pop
73 * back out of the control flow stack.
75 * For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else
76 * instructions should be placed, and if_stack[if_stack_pos - 1] has where
77 * the next instructions outside of the if/then/else block go.
80 unsigned if_stack_pos
;
83 * Stack of nir_cursors where instructions should be pushed as we pop
84 * back out of the control flow stack.
86 * loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside
89 nir_cursor
*loop_stack
;
90 unsigned loop_stack_pos
;
92 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
96 #define ttn_swizzle(b, src, x, y, z, w) \
97 nir_swizzle(b, src, SWIZ(x, y, z, w), 4, false)
98 #define ttn_channel(b, src, swiz) \
99 nir_swizzle(b, src, SWIZ(swiz, swiz, swiz, swiz), 1, false)
101 static gl_varying_slot
102 tgsi_varying_semantic_to_slot(unsigned semantic
, unsigned index
)
105 case TGSI_SEMANTIC_POSITION
:
106 return VARYING_SLOT_POS
;
107 case TGSI_SEMANTIC_COLOR
:
109 return VARYING_SLOT_COL0
;
111 return VARYING_SLOT_COL1
;
112 case TGSI_SEMANTIC_BCOLOR
:
114 return VARYING_SLOT_BFC0
;
116 return VARYING_SLOT_BFC1
;
117 case TGSI_SEMANTIC_FOG
:
118 return VARYING_SLOT_FOGC
;
119 case TGSI_SEMANTIC_PSIZE
:
120 return VARYING_SLOT_PSIZ
;
121 case TGSI_SEMANTIC_GENERIC
:
122 return VARYING_SLOT_VAR0
+ index
;
123 case TGSI_SEMANTIC_FACE
:
124 return VARYING_SLOT_FACE
;
125 case TGSI_SEMANTIC_EDGEFLAG
:
126 return VARYING_SLOT_EDGE
;
127 case TGSI_SEMANTIC_PRIMID
:
128 return VARYING_SLOT_PRIMITIVE_ID
;
129 case TGSI_SEMANTIC_CLIPDIST
:
131 return VARYING_SLOT_CLIP_DIST0
;
133 return VARYING_SLOT_CLIP_DIST1
;
134 case TGSI_SEMANTIC_CLIPVERTEX
:
135 return VARYING_SLOT_CLIP_VERTEX
;
136 case TGSI_SEMANTIC_TEXCOORD
:
137 return VARYING_SLOT_TEX0
+ index
;
138 case TGSI_SEMANTIC_PCOORD
:
139 return VARYING_SLOT_PNTC
;
140 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
141 return VARYING_SLOT_VIEWPORT
;
142 case TGSI_SEMANTIC_LAYER
:
143 return VARYING_SLOT_LAYER
;
145 fprintf(stderr
, "Bad TGSI semantic: %d/%d\n", semantic
, index
);
150 /* Temporary helper to remap back to TGSI style semantic name/index
151 * values, for use in drivers that haven't been converted to using
155 varying_slot_to_tgsi_semantic(gl_varying_slot slot
,
156 unsigned *semantic_name
, unsigned *semantic_index
)
158 static const unsigned map
[][2] = {
159 [VARYING_SLOT_POS
] = { TGSI_SEMANTIC_POSITION
, 0 },
160 [VARYING_SLOT_COL0
] = { TGSI_SEMANTIC_COLOR
, 0 },
161 [VARYING_SLOT_COL1
] = { TGSI_SEMANTIC_COLOR
, 1 },
162 [VARYING_SLOT_BFC0
] = { TGSI_SEMANTIC_BCOLOR
, 0 },
163 [VARYING_SLOT_BFC1
] = { TGSI_SEMANTIC_BCOLOR
, 1 },
164 [VARYING_SLOT_FOGC
] = { TGSI_SEMANTIC_FOG
, 0 },
165 [VARYING_SLOT_PSIZ
] = { TGSI_SEMANTIC_PSIZE
, 0 },
166 [VARYING_SLOT_FACE
] = { TGSI_SEMANTIC_FACE
, 0 },
167 [VARYING_SLOT_EDGE
] = { TGSI_SEMANTIC_EDGEFLAG
, 0 },
168 [VARYING_SLOT_PRIMITIVE_ID
] = { TGSI_SEMANTIC_PRIMID
, 0 },
169 [VARYING_SLOT_CLIP_DIST0
] = { TGSI_SEMANTIC_CLIPDIST
, 0 },
170 [VARYING_SLOT_CLIP_DIST1
] = { TGSI_SEMANTIC_CLIPDIST
, 1 },
171 [VARYING_SLOT_CLIP_VERTEX
] = { TGSI_SEMANTIC_CLIPVERTEX
, 0 },
172 [VARYING_SLOT_PNTC
] = { TGSI_SEMANTIC_PCOORD
, 0 },
173 [VARYING_SLOT_VIEWPORT
] = { TGSI_SEMANTIC_VIEWPORT_INDEX
, 0 },
174 [VARYING_SLOT_LAYER
] = { TGSI_SEMANTIC_LAYER
, 0 },
177 if (slot
>= VARYING_SLOT_VAR0
) {
178 *semantic_name
= TGSI_SEMANTIC_GENERIC
;
179 *semantic_index
= slot
- VARYING_SLOT_VAR0
;
183 if (slot
>= VARYING_SLOT_TEX0
&& slot
<= VARYING_SLOT_TEX7
) {
184 *semantic_name
= TGSI_SEMANTIC_TEXCOORD
;
185 *semantic_index
= slot
- VARYING_SLOT_TEX0
;
189 if (slot
>= ARRAY_SIZE(map
)) {
190 fprintf(stderr
, "Unknown varying slot %d\n", slot
);
194 *semantic_name
= map
[slot
][0];
195 *semantic_index
= map
[slot
][1];
198 /* Temporary helper to remap back to TGSI style semantic name/index
199 * values, for use in drivers that haven't been converted to using
203 frag_result_to_tgsi_semantic(gl_frag_result slot
,
204 unsigned *semantic_name
, unsigned *semantic_index
)
206 static const unsigned map
[][2] = {
207 [FRAG_RESULT_DEPTH
] = { TGSI_SEMANTIC_POSITION
, 0 },
208 [FRAG_RESULT_COLOR
] = { TGSI_SEMANTIC_COLOR
, -1 },
209 [FRAG_RESULT_DATA0
+ 0] = { TGSI_SEMANTIC_COLOR
, 0 },
210 [FRAG_RESULT_DATA0
+ 1] = { TGSI_SEMANTIC_COLOR
, 1 },
211 [FRAG_RESULT_DATA0
+ 2] = { TGSI_SEMANTIC_COLOR
, 2 },
212 [FRAG_RESULT_DATA0
+ 3] = { TGSI_SEMANTIC_COLOR
, 3 },
213 [FRAG_RESULT_DATA0
+ 4] = { TGSI_SEMANTIC_COLOR
, 4 },
214 [FRAG_RESULT_DATA0
+ 5] = { TGSI_SEMANTIC_COLOR
, 5 },
215 [FRAG_RESULT_DATA0
+ 6] = { TGSI_SEMANTIC_COLOR
, 6 },
216 [FRAG_RESULT_DATA0
+ 7] = { TGSI_SEMANTIC_COLOR
, 7 },
219 *semantic_name
= map
[slot
][0];
220 *semantic_index
= map
[slot
][1];
224 ttn_src_for_dest(nir_builder
*b
, nir_alu_dest
*dest
)
227 memset(&src
, 0, sizeof(src
));
229 if (dest
->dest
.is_ssa
)
230 src
.src
= nir_src_for_ssa(&dest
->dest
.ssa
);
232 assert(!dest
->dest
.reg
.indirect
);
233 src
.src
= nir_src_for_reg(dest
->dest
.reg
.reg
);
234 src
.src
.reg
.base_offset
= dest
->dest
.reg
.base_offset
;
237 for (int i
= 0; i
< 4; i
++)
240 return nir_fmov_alu(b
, src
, 4);
244 ttn_emit_declaration(struct ttn_compile
*c
)
246 nir_builder
*b
= &c
->build
;
247 struct tgsi_full_declaration
*decl
= &c
->token
->FullDeclaration
;
248 unsigned array_size
= decl
->Range
.Last
- decl
->Range
.First
+ 1;
249 unsigned file
= decl
->Declaration
.File
;
252 if (file
== TGSI_FILE_TEMPORARY
) {
253 if (decl
->Declaration
.Array
) {
254 /* for arrays, we create variables instead of registers: */
255 nir_variable
*var
= rzalloc(b
->shader
, nir_variable
);
257 var
->type
= glsl_array_type(glsl_vec4_type(), array_size
);
258 var
->data
.mode
= nir_var_global
;
259 var
->name
= ralloc_asprintf(var
, "arr_%d", decl
->Array
.ArrayID
);
261 exec_list_push_tail(&b
->shader
->globals
, &var
->node
);
263 for (i
= 0; i
< array_size
; i
++) {
264 /* point all the matching slots to the same var,
265 * with appropriate offset set, mostly just so
266 * we know what to do when tgsi does a non-indirect
269 c
->temp_regs
[decl
->Range
.First
+ i
].reg
= NULL
;
270 c
->temp_regs
[decl
->Range
.First
+ i
].var
= var
;
271 c
->temp_regs
[decl
->Range
.First
+ i
].offset
= i
;
274 for (i
= 0; i
< array_size
; i
++) {
275 nir_register
*reg
= nir_local_reg_create(b
->impl
);
276 reg
->num_components
= 4;
277 c
->temp_regs
[decl
->Range
.First
+ i
].reg
= reg
;
278 c
->temp_regs
[decl
->Range
.First
+ i
].var
= NULL
;
279 c
->temp_regs
[decl
->Range
.First
+ i
].offset
= 0;
282 } else if (file
== TGSI_FILE_ADDRESS
) {
283 c
->addr_reg
= nir_local_reg_create(b
->impl
);
284 c
->addr_reg
->num_components
= 4;
285 } else if (file
== TGSI_FILE_SYSTEM_VALUE
) {
286 /* Nothing to record for system values. */
287 } else if (file
== TGSI_FILE_SAMPLER
) {
288 /* Nothing to record for samplers. */
289 } else if (file
== TGSI_FILE_SAMPLER_VIEW
) {
290 struct tgsi_declaration_sampler_view
*sview
= &decl
->SamplerView
;
293 assert((sview
->ReturnTypeX
== sview
->ReturnTypeY
) &&
294 (sview
->ReturnTypeX
== sview
->ReturnTypeZ
) &&
295 (sview
->ReturnTypeX
== sview
->ReturnTypeW
));
297 switch (sview
->ReturnTypeX
) {
298 case TGSI_RETURN_TYPE_SINT
:
301 case TGSI_RETURN_TYPE_UINT
:
302 type
= nir_type_uint
;
304 case TGSI_RETURN_TYPE_FLOAT
:
306 type
= nir_type_float
;
310 for (i
= 0; i
< array_size
; i
++) {
311 c
->samp_types
[decl
->Range
.First
+ i
] = type
;
314 bool is_array
= (array_size
> 1);
316 assert(file
== TGSI_FILE_INPUT
||
317 file
== TGSI_FILE_OUTPUT
||
318 file
== TGSI_FILE_CONSTANT
);
320 /* nothing to do for UBOs: */
321 if ((file
== TGSI_FILE_CONSTANT
) && decl
->Declaration
.Dimension
)
324 if ((file
== TGSI_FILE_INPUT
) || (file
== TGSI_FILE_OUTPUT
)) {
325 is_array
= (is_array
&& decl
->Declaration
.Array
&&
326 (decl
->Array
.ArrayID
!= 0));
329 for (i
= 0; i
< array_size
; i
++) {
330 unsigned idx
= decl
->Range
.First
+ i
;
331 nir_variable
*var
= rzalloc(b
->shader
, nir_variable
);
333 var
->data
.driver_location
= idx
;
335 var
->type
= glsl_vec4_type();
337 var
->type
= glsl_array_type(var
->type
, array_size
);
340 case TGSI_FILE_INPUT
:
341 var
->data
.read_only
= true;
342 var
->data
.mode
= nir_var_shader_in
;
343 var
->name
= ralloc_asprintf(var
, "in_%d", idx
);
345 if (c
->scan
->processor
== TGSI_PROCESSOR_FRAGMENT
) {
347 tgsi_varying_semantic_to_slot(decl
->Semantic
.Name
,
348 decl
->Semantic
.Index
);
350 assert(!decl
->Declaration
.Semantic
);
351 var
->data
.location
= VERT_ATTRIB_GENERIC0
+ idx
;
355 /* We definitely need to translate the interpolation field, because
356 * nir_print will decode it.
358 switch (decl
->Interp
.Interpolate
) {
359 case TGSI_INTERPOLATE_CONSTANT
:
360 var
->data
.interpolation
= INTERP_QUALIFIER_FLAT
;
362 case TGSI_INTERPOLATE_LINEAR
:
363 var
->data
.interpolation
= INTERP_QUALIFIER_NOPERSPECTIVE
;
365 case TGSI_INTERPOLATE_PERSPECTIVE
:
366 var
->data
.interpolation
= INTERP_QUALIFIER_SMOOTH
;
370 exec_list_push_tail(&b
->shader
->inputs
, &var
->node
);
372 case TGSI_FILE_OUTPUT
: {
373 int semantic_name
= decl
->Semantic
.Name
;
374 int semantic_index
= decl
->Semantic
.Index
;
375 /* Since we can't load from outputs in the IR, we make temporaries
376 * for the outputs and emit stores to the real outputs at the end of
379 nir_register
*reg
= nir_local_reg_create(b
->impl
);
380 reg
->num_components
= 4;
382 reg
->num_array_elems
= array_size
;
384 var
->data
.mode
= nir_var_shader_out
;
385 var
->name
= ralloc_asprintf(var
, "out_%d", idx
);
388 if (c
->scan
->processor
== TGSI_PROCESSOR_FRAGMENT
) {
389 switch (semantic_name
) {
390 case TGSI_SEMANTIC_COLOR
: {
391 /* TODO tgsi loses some information, so we cannot
392 * actually differentiate here between DSB and MRT
393 * at this point. But so far no drivers using tgsi-
394 * to-nir support dual source blend:
396 bool dual_src_blend
= false;
397 if (dual_src_blend
&& (semantic_index
== 1)) {
398 var
->data
.location
= FRAG_RESULT_DATA0
;
401 if (c
->scan
->properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
402 var
->data
.location
= FRAG_RESULT_COLOR
;
404 var
->data
.location
= FRAG_RESULT_DATA0
+ semantic_index
;
408 case TGSI_SEMANTIC_POSITION
:
409 var
->data
.location
= FRAG_RESULT_DEPTH
;
412 fprintf(stderr
, "Bad TGSI semantic: %d/%d\n",
413 decl
->Semantic
.Name
, decl
->Semantic
.Index
);
418 tgsi_varying_semantic_to_slot(semantic_name
, semantic_index
);
423 for (j
= 0; j
< array_size
; j
++) {
424 c
->output_regs
[idx
+ j
].offset
= i
+ j
;
425 c
->output_regs
[idx
+ j
].reg
= reg
;
428 c
->output_regs
[idx
].offset
= i
;
429 c
->output_regs
[idx
].reg
= reg
;
432 exec_list_push_tail(&b
->shader
->outputs
, &var
->node
);
435 case TGSI_FILE_CONSTANT
:
436 var
->data
.mode
= nir_var_uniform
;
437 var
->name
= ralloc_asprintf(var
, "uniform_%d", idx
);
439 exec_list_push_tail(&b
->shader
->uniforms
, &var
->node
);
442 unreachable("bad declaration file");
454 ttn_emit_immediate(struct ttn_compile
*c
)
456 nir_builder
*b
= &c
->build
;
457 struct tgsi_full_immediate
*tgsi_imm
= &c
->token
->FullImmediate
;
458 nir_load_const_instr
*load_const
;
461 load_const
= nir_load_const_instr_create(b
->shader
, 4);
462 c
->imm_defs
[c
->next_imm
] = &load_const
->def
;
465 for (i
= 0; i
< 4; i
++)
466 load_const
->value
.u
[i
] = tgsi_imm
->u
[i
].Uint
;
468 nir_builder_instr_insert(b
, &load_const
->instr
);
472 ttn_src_for_indirect(struct ttn_compile
*c
, struct tgsi_ind_register
*indirect
);
474 /* generate either a constant or indirect deref chain for accessing an
477 static nir_deref_var
*
478 ttn_array_deref(struct ttn_compile
*c
, nir_intrinsic_instr
*instr
,
479 nir_variable
*var
, unsigned offset
,
480 struct tgsi_ind_register
*indirect
)
482 nir_deref_var
*deref
= nir_deref_var_create(instr
, var
);
483 nir_deref_array
*arr
= nir_deref_array_create(deref
);
485 arr
->base_offset
= offset
;
486 arr
->deref
.type
= glsl_get_array_element(var
->type
);
489 arr
->deref_array_type
= nir_deref_array_type_indirect
;
490 arr
->indirect
= nir_src_for_ssa(ttn_src_for_indirect(c
, indirect
));
492 arr
->deref_array_type
= nir_deref_array_type_direct
;
495 deref
->deref
.child
= &arr
->deref
;
501 ttn_src_for_file_and_index(struct ttn_compile
*c
, unsigned file
, unsigned index
,
502 struct tgsi_ind_register
*indirect
,
503 struct tgsi_dimension
*dim
,
504 struct tgsi_ind_register
*dimind
)
506 nir_builder
*b
= &c
->build
;
509 memset(&src
, 0, sizeof(src
));
512 case TGSI_FILE_TEMPORARY
:
513 if (c
->temp_regs
[index
].var
) {
514 unsigned offset
= c
->temp_regs
[index
].offset
;
515 nir_variable
*var
= c
->temp_regs
[index
].var
;
516 nir_intrinsic_instr
*load
;
518 load
= nir_intrinsic_instr_create(b
->shader
,
519 nir_intrinsic_load_var
);
520 load
->num_components
= 4;
521 load
->variables
[0] = ttn_array_deref(c
, load
, var
, offset
, indirect
);
523 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, NULL
);
524 nir_builder_instr_insert(b
, &load
->instr
);
526 src
= nir_src_for_ssa(&load
->dest
.ssa
);
530 src
.reg
.reg
= c
->temp_regs
[index
].reg
;
535 case TGSI_FILE_ADDRESS
:
536 src
.reg
.reg
= c
->addr_reg
;
540 case TGSI_FILE_IMMEDIATE
:
541 src
= nir_src_for_ssa(c
->imm_defs
[index
]);
546 case TGSI_FILE_SYSTEM_VALUE
: {
547 nir_intrinsic_instr
*load
;
554 switch (c
->scan
->system_value_semantic_name
[index
]) {
555 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
556 op
= nir_intrinsic_load_vertex_id_zero_base
;
558 case TGSI_SEMANTIC_VERTEXID
:
559 op
= nir_intrinsic_load_vertex_id
;
561 case TGSI_SEMANTIC_BASEVERTEX
:
562 op
= nir_intrinsic_load_base_vertex
;
564 case TGSI_SEMANTIC_INSTANCEID
:
565 op
= nir_intrinsic_load_instance_id
;
568 unreachable("bad system value");
571 load
= nir_intrinsic_instr_create(b
->shader
, op
);
572 load
->num_components
= ncomp
;
574 nir_ssa_dest_init(&load
->instr
, &load
->dest
, ncomp
, NULL
);
575 nir_builder_instr_insert(b
, &load
->instr
);
577 src
= nir_src_for_ssa(&load
->dest
.ssa
);
581 case TGSI_FILE_INPUT
:
582 case TGSI_FILE_CONSTANT
: {
583 nir_intrinsic_instr
*load
;
588 case TGSI_FILE_INPUT
:
589 op
= nir_intrinsic_load_input
;
592 case TGSI_FILE_CONSTANT
:
594 op
= nir_intrinsic_load_ubo
;
596 op
= nir_intrinsic_load_uniform
;
600 unreachable("No other load files supported");
604 load
= nir_intrinsic_instr_create(b
->shader
, op
);
606 load
->num_components
= 4;
610 ttn_src_for_file_and_index(c
, dimind
->File
, dimind
->Index
,
613 /* UBOs start at index 1 in TGSI: */
615 nir_src_for_ssa(nir_imm_int(b
, dim
->Index
- 1));
622 /* UBO loads don't have a const_index[0] base offset. */
623 offset
= nir_imm_int(b
, index
);
625 offset
= nir_iadd(b
, offset
, ttn_src_for_indirect(c
, indirect
));
627 /* UBO offsets are in bytes, but TGSI gives them to us in vec4's */
628 offset
= nir_ishl(b
, offset
, nir_imm_int(b
, 4));
630 load
->const_index
[0] = index
;
632 offset
= ttn_src_for_indirect(c
, indirect
);
634 offset
= nir_imm_int(b
, 0);
637 load
->src
[srcn
++] = nir_src_for_ssa(offset
);
639 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, NULL
);
640 nir_builder_instr_insert(b
, &load
->instr
);
642 src
= nir_src_for_ssa(&load
->dest
.ssa
);
647 unreachable("bad src file");
655 ttn_src_for_indirect(struct ttn_compile
*c
, struct tgsi_ind_register
*indirect
)
657 nir_builder
*b
= &c
->build
;
659 memset(&src
, 0, sizeof(src
));
660 for (int i
= 0; i
< 4; i
++)
661 src
.swizzle
[i
] = indirect
->Swizzle
;
662 src
.src
= ttn_src_for_file_and_index(c
,
666 return nir_imov_alu(b
, src
, 1);
670 ttn_get_dest(struct ttn_compile
*c
, struct tgsi_full_dst_register
*tgsi_fdst
)
672 struct tgsi_dst_register
*tgsi_dst
= &tgsi_fdst
->Register
;
674 unsigned index
= tgsi_dst
->Index
;
676 memset(&dest
, 0, sizeof(dest
));
678 if (tgsi_dst
->File
== TGSI_FILE_TEMPORARY
) {
679 if (c
->temp_regs
[index
].var
) {
680 nir_builder
*b
= &c
->build
;
681 nir_intrinsic_instr
*load
;
682 struct tgsi_ind_register
*indirect
=
683 tgsi_dst
->Indirect
? &tgsi_fdst
->Indirect
: NULL
;
686 /* this works, because TGSI will give us a base offset
687 * (in case of indirect index) that points back into
688 * the array. Access can be direct or indirect, we
689 * don't really care. Just create a one-shot dst reg
690 * that will get store_var'd back into the array var
691 * at the end of ttn_emit_instruction()
693 reg
= nir_local_reg_create(c
->build
.impl
);
694 reg
->num_components
= 4;
695 dest
.dest
.reg
.reg
= reg
;
696 dest
.dest
.reg
.base_offset
= 0;
698 /* since the alu op might not write to all components
699 * of the temporary, we must first do a load_var to
700 * get the previous array elements into the register.
701 * This is one area that NIR could use a bit of
702 * improvement (or opt pass to clean up the mess
703 * once things are scalarized)
706 load
= nir_intrinsic_instr_create(c
->build
.shader
,
707 nir_intrinsic_load_var
);
708 load
->num_components
= 4;
710 ttn_array_deref(c
, load
, c
->temp_regs
[index
].var
,
711 c
->temp_regs
[index
].offset
,
714 load
->dest
= nir_dest_for_reg(reg
);
716 nir_builder_instr_insert(b
, &load
->instr
);
718 assert(!tgsi_dst
->Indirect
);
719 dest
.dest
.reg
.reg
= c
->temp_regs
[index
].reg
;
720 dest
.dest
.reg
.base_offset
= c
->temp_regs
[index
].offset
;
722 } else if (tgsi_dst
->File
== TGSI_FILE_OUTPUT
) {
723 dest
.dest
.reg
.reg
= c
->output_regs
[index
].reg
;
724 dest
.dest
.reg
.base_offset
= c
->output_regs
[index
].offset
;
725 } else if (tgsi_dst
->File
== TGSI_FILE_ADDRESS
) {
727 dest
.dest
.reg
.reg
= c
->addr_reg
;
730 dest
.write_mask
= tgsi_dst
->WriteMask
;
731 dest
.saturate
= false;
733 if (tgsi_dst
->Indirect
&& (tgsi_dst
->File
!= TGSI_FILE_TEMPORARY
)) {
734 nir_src
*indirect
= ralloc(c
->build
.shader
, nir_src
);
735 *indirect
= nir_src_for_ssa(ttn_src_for_indirect(c
, &tgsi_fdst
->Indirect
));
736 dest
.dest
.reg
.indirect
= indirect
;
742 static nir_variable
*
743 ttn_get_var(struct ttn_compile
*c
, struct tgsi_full_dst_register
*tgsi_fdst
)
745 struct tgsi_dst_register
*tgsi_dst
= &tgsi_fdst
->Register
;
746 unsigned index
= tgsi_dst
->Index
;
748 if (tgsi_dst
->File
== TGSI_FILE_TEMPORARY
) {
749 /* we should not have an indirect when there is no var! */
750 if (!c
->temp_regs
[index
].var
)
751 assert(!tgsi_dst
->Indirect
);
752 return c
->temp_regs
[index
].var
;
759 ttn_get_src(struct ttn_compile
*c
, struct tgsi_full_src_register
*tgsi_fsrc
)
761 nir_builder
*b
= &c
->build
;
762 struct tgsi_src_register
*tgsi_src
= &tgsi_fsrc
->Register
;
763 unsigned tgsi_opcode
= c
->token
->FullInstruction
.Instruction
.Opcode
;
764 unsigned tgsi_src_type
= tgsi_opcode_infer_src_type(tgsi_opcode
);
765 bool src_is_float
= !(tgsi_src_type
== TGSI_TYPE_SIGNED
||
766 tgsi_src_type
== TGSI_TYPE_UNSIGNED
);
769 memset(&src
, 0, sizeof(src
));
771 if (tgsi_src
->File
== TGSI_FILE_NULL
) {
772 return nir_imm_float(b
, 0.0);
773 } else if (tgsi_src
->File
== TGSI_FILE_SAMPLER
) {
774 /* Only the index of the sampler gets used in texturing, and it will
775 * handle looking that up on its own instead of using the nir_alu_src.
777 assert(!tgsi_src
->Indirect
);
780 struct tgsi_ind_register
*ind
= NULL
;
781 struct tgsi_dimension
*dim
= NULL
;
782 struct tgsi_ind_register
*dimind
= NULL
;
783 if (tgsi_src
->Indirect
)
784 ind
= &tgsi_fsrc
->Indirect
;
785 if (tgsi_src
->Dimension
) {
786 dim
= &tgsi_fsrc
->Dimension
;
788 dimind
= &tgsi_fsrc
->DimIndirect
;
790 src
.src
= ttn_src_for_file_and_index(c
,
796 src
.swizzle
[0] = tgsi_src
->SwizzleX
;
797 src
.swizzle
[1] = tgsi_src
->SwizzleY
;
798 src
.swizzle
[2] = tgsi_src
->SwizzleZ
;
799 src
.swizzle
[3] = tgsi_src
->SwizzleW
;
801 nir_ssa_def
*def
= nir_fmov_alu(b
, src
, 4);
803 if (tgsi_src
->Absolute
) {
805 def
= nir_fabs(b
, def
);
807 def
= nir_iabs(b
, def
);
810 if (tgsi_src
->Negate
) {
812 def
= nir_fneg(b
, def
);
814 def
= nir_ineg(b
, def
);
821 ttn_alu(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
823 unsigned num_srcs
= nir_op_infos
[op
].num_inputs
;
824 nir_alu_instr
*instr
= nir_alu_instr_create(b
->shader
, op
);
827 for (i
= 0; i
< num_srcs
; i
++)
828 instr
->src
[i
].src
= nir_src_for_ssa(src
[i
]);
831 nir_builder_instr_insert(b
, &instr
->instr
);
835 ttn_move_dest_masked(nir_builder
*b
, nir_alu_dest dest
,
836 nir_ssa_def
*def
, unsigned write_mask
)
838 if (!(dest
.write_mask
& write_mask
))
841 nir_alu_instr
*mov
= nir_alu_instr_create(b
->shader
, nir_op_imov
);
843 mov
->dest
.write_mask
&= write_mask
;
844 mov
->src
[0].src
= nir_src_for_ssa(def
);
845 for (unsigned i
= def
->num_components
; i
< 4; i
++)
846 mov
->src
[0].swizzle
[i
] = def
->num_components
- 1;
847 nir_builder_instr_insert(b
, &mov
->instr
);
851 ttn_move_dest(nir_builder
*b
, nir_alu_dest dest
, nir_ssa_def
*def
)
853 ttn_move_dest_masked(b
, dest
, def
, TGSI_WRITEMASK_XYZW
);
857 ttn_arl(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
859 ttn_move_dest(b
, dest
, nir_f2i(b
, nir_ffloor(b
, src
[0])));
862 /* EXP - Approximate Exponential Base 2
863 * dst.x = 2^{\lfloor src.x\rfloor}
864 * dst.y = src.x - \lfloor src.x\rfloor
869 ttn_exp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
871 nir_ssa_def
*srcx
= ttn_channel(b
, src
[0], X
);
873 ttn_move_dest_masked(b
, dest
, nir_fexp2(b
, nir_ffloor(b
, srcx
)),
875 ttn_move_dest_masked(b
, dest
, nir_fsub(b
, srcx
, nir_ffloor(b
, srcx
)),
877 ttn_move_dest_masked(b
, dest
, nir_fexp2(b
, srcx
), TGSI_WRITEMASK_Z
);
878 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
881 /* LOG - Approximate Logarithm Base 2
882 * dst.x = \lfloor\log_2{|src.x|}\rfloor
883 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
884 * dst.z = \log_2{|src.x|}
888 ttn_log(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
890 nir_ssa_def
*abs_srcx
= nir_fabs(b
, ttn_channel(b
, src
[0], X
));
891 nir_ssa_def
*log2
= nir_flog2(b
, abs_srcx
);
893 ttn_move_dest_masked(b
, dest
, nir_ffloor(b
, log2
), TGSI_WRITEMASK_X
);
894 ttn_move_dest_masked(b
, dest
,
895 nir_fdiv(b
, abs_srcx
, nir_fexp2(b
, nir_ffloor(b
, log2
))),
897 ttn_move_dest_masked(b
, dest
, nir_flog2(b
, abs_srcx
), TGSI_WRITEMASK_Z
);
898 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
901 /* DST - Distance Vector
903 * dst.y = src0.y \times src1.y
908 ttn_dst(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
910 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_X
);
911 ttn_move_dest_masked(b
, dest
, nir_fmul(b
, src
[0], src
[1]), TGSI_WRITEMASK_Y
);
912 ttn_move_dest_masked(b
, dest
, nir_fmov(b
, src
[0]), TGSI_WRITEMASK_Z
);
913 ttn_move_dest_masked(b
, dest
, nir_fmov(b
, src
[1]), TGSI_WRITEMASK_W
);
916 /* LIT - Light Coefficients
918 * dst.y = max(src.x, 0.0)
919 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
923 ttn_lit(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
925 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_XW
);
927 ttn_move_dest_masked(b
, dest
, nir_fmax(b
, ttn_channel(b
, src
[0], X
),
928 nir_imm_float(b
, 0.0)), TGSI_WRITEMASK_Y
);
930 if (dest
.write_mask
& TGSI_WRITEMASK_Z
) {
931 nir_ssa_def
*src0_y
= ttn_channel(b
, src
[0], Y
);
932 nir_ssa_def
*wclamp
= nir_fmax(b
, nir_fmin(b
, ttn_channel(b
, src
[0], W
),
933 nir_imm_float(b
, 128.0)),
934 nir_imm_float(b
, -128.0));
935 nir_ssa_def
*pow
= nir_fpow(b
, nir_fmax(b
, src0_y
, nir_imm_float(b
, 0.0)),
938 ttn_move_dest_masked(b
, dest
,
941 nir_imm_float(b
, 0.0),
942 ttn_channel(b
, src
[0], X
)),
943 nir_imm_float(b
, 0.0),
950 * dst.x = \cos{src.x}
951 * dst.y = \sin{src.x}
956 ttn_scs(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
958 ttn_move_dest_masked(b
, dest
, nir_fcos(b
, ttn_channel(b
, src
[0], X
)),
960 ttn_move_dest_masked(b
, dest
, nir_fsin(b
, ttn_channel(b
, src
[0], X
)),
962 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 0.0), TGSI_WRITEMASK_Z
);
963 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
967 ttn_sle(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
969 ttn_move_dest(b
, dest
, nir_sge(b
, src
[1], src
[0]));
973 ttn_sgt(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
975 ttn_move_dest(b
, dest
, nir_slt(b
, src
[1], src
[0]));
979 ttn_clamp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
981 ttn_move_dest(b
, dest
, nir_fmin(b
, nir_fmax(b
, src
[0], src
[1]), src
[2]));
985 ttn_xpd(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
987 ttn_move_dest_masked(b
, dest
,
990 ttn_swizzle(b
, src
[0], Y
, Z
, X
, X
),
991 ttn_swizzle(b
, src
[1], Z
, X
, Y
, X
)),
993 ttn_swizzle(b
, src
[1], Y
, Z
, X
, X
),
994 ttn_swizzle(b
, src
[0], Z
, X
, Y
, X
))),
996 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
1000 ttn_dp2a(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1002 ttn_move_dest(b
, dest
,
1003 ttn_channel(b
, nir_fadd(b
, nir_fdot2(b
, src
[0], src
[1]),
1009 ttn_dp2(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1011 ttn_move_dest(b
, dest
, nir_fdot2(b
, src
[0], src
[1]));
1015 ttn_dp3(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1017 ttn_move_dest(b
, dest
, nir_fdot3(b
, src
[0], src
[1]));
1021 ttn_dp4(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1023 ttn_move_dest(b
, dest
, nir_fdot4(b
, src
[0], src
[1]));
1027 ttn_dph(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1029 ttn_move_dest(b
, dest
, nir_fadd(b
, nir_fdot3(b
, src
[0], src
[1]),
1030 ttn_channel(b
, src
[1], W
)));
1034 ttn_umad(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1036 ttn_move_dest(b
, dest
, nir_iadd(b
, nir_imul(b
, src
[0], src
[1]), src
[2]));
1040 ttn_arr(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1042 ttn_move_dest(b
, dest
, nir_ffloor(b
, nir_fadd(b
, src
[0], nir_imm_float(b
, 0.5))));
1046 ttn_cmp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1048 ttn_move_dest(b
, dest
, nir_bcsel(b
,
1049 nir_flt(b
, src
[0], nir_imm_float(b
, 0.0)),
1054 ttn_ucmp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1056 ttn_move_dest(b
, dest
, nir_bcsel(b
,
1057 nir_ine(b
, src
[0], nir_imm_int(b
, 0)),
1062 ttn_kill(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1064 nir_intrinsic_instr
*discard
=
1065 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard
);
1066 nir_builder_instr_insert(b
, &discard
->instr
);
1070 ttn_kill_if(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1072 nir_ssa_def
*cmp
= nir_bany4(b
, nir_flt(b
, src
[0], nir_imm_float(b
, 0.0)));
1073 nir_intrinsic_instr
*discard
=
1074 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
1075 discard
->src
[0] = nir_src_for_ssa(cmp
);
1076 nir_builder_instr_insert(b
, &discard
->instr
);
1080 ttn_if(struct ttn_compile
*c
, nir_ssa_def
*src
, bool is_uint
)
1082 nir_builder
*b
= &c
->build
;
1084 src
= ttn_channel(b
, src
, X
);
1086 nir_if
*if_stmt
= nir_if_create(b
->shader
);
1088 if_stmt
->condition
= nir_src_for_ssa(nir_ine(b
, src
, nir_imm_int(b
, 0)));
1090 if_stmt
->condition
= nir_src_for_ssa(nir_fne(b
, src
, nir_imm_int(b
, 0)));
1092 nir_builder_cf_insert(b
, &if_stmt
->cf_node
);
1094 c
->if_stack
[c
->if_stack_pos
] = nir_after_cf_node(&if_stmt
->cf_node
);
1097 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
1099 c
->if_stack
[c
->if_stack_pos
] = nir_after_cf_list(&if_stmt
->else_list
);
1104 ttn_else(struct ttn_compile
*c
)
1106 nir_builder
*b
= &c
->build
;
1108 b
->cursor
= c
->if_stack
[c
->if_stack_pos
- 1];
1112 ttn_endif(struct ttn_compile
*c
)
1114 nir_builder
*b
= &c
->build
;
1116 c
->if_stack_pos
-= 2;
1117 b
->cursor
= c
->if_stack
[c
->if_stack_pos
];
1121 ttn_bgnloop(struct ttn_compile
*c
)
1123 nir_builder
*b
= &c
->build
;
1125 nir_loop
*loop
= nir_loop_create(b
->shader
);
1126 nir_builder_cf_insert(b
, &loop
->cf_node
);
1128 c
->loop_stack
[c
->loop_stack_pos
] = nir_after_cf_node(&loop
->cf_node
);
1129 c
->loop_stack_pos
++;
1131 b
->cursor
= nir_after_cf_list(&loop
->body
);
1135 ttn_cont(nir_builder
*b
)
1137 nir_jump_instr
*instr
= nir_jump_instr_create(b
->shader
, nir_jump_continue
);
1138 nir_builder_instr_insert(b
, &instr
->instr
);
1142 ttn_brk(nir_builder
*b
)
1144 nir_jump_instr
*instr
= nir_jump_instr_create(b
->shader
, nir_jump_break
);
1145 nir_builder_instr_insert(b
, &instr
->instr
);
1149 ttn_endloop(struct ttn_compile
*c
)
1151 nir_builder
*b
= &c
->build
;
1153 c
->loop_stack_pos
--;
1154 b
->cursor
= c
->loop_stack
[c
->loop_stack_pos
];
1158 setup_texture_info(nir_tex_instr
*instr
, unsigned texture
)
1161 case TGSI_TEXTURE_BUFFER
:
1162 instr
->sampler_dim
= GLSL_SAMPLER_DIM_BUF
;
1164 case TGSI_TEXTURE_1D
:
1165 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
1167 case TGSI_TEXTURE_1D_ARRAY
:
1168 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
1169 instr
->is_array
= true;
1171 case TGSI_TEXTURE_SHADOW1D
:
1172 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
1173 instr
->is_shadow
= true;
1175 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1176 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
1177 instr
->is_shadow
= true;
1178 instr
->is_array
= true;
1180 case TGSI_TEXTURE_2D
:
1181 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
1183 case TGSI_TEXTURE_2D_ARRAY
:
1184 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
1185 instr
->is_array
= true;
1187 case TGSI_TEXTURE_2D_MSAA
:
1188 instr
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
1190 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
1191 instr
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
1192 instr
->is_array
= true;
1194 case TGSI_TEXTURE_SHADOW2D
:
1195 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
1196 instr
->is_shadow
= true;
1198 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1199 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
1200 instr
->is_shadow
= true;
1201 instr
->is_array
= true;
1203 case TGSI_TEXTURE_3D
:
1204 instr
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
1206 case TGSI_TEXTURE_CUBE
:
1207 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
1209 case TGSI_TEXTURE_CUBE_ARRAY
:
1210 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
1211 instr
->is_array
= true;
1213 case TGSI_TEXTURE_SHADOWCUBE
:
1214 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
1215 instr
->is_shadow
= true;
1217 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1218 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
1219 instr
->is_shadow
= true;
1220 instr
->is_array
= true;
1222 case TGSI_TEXTURE_RECT
:
1223 instr
->sampler_dim
= GLSL_SAMPLER_DIM_RECT
;
1225 case TGSI_TEXTURE_SHADOWRECT
:
1226 instr
->sampler_dim
= GLSL_SAMPLER_DIM_RECT
;
1227 instr
->is_shadow
= true;
1230 fprintf(stderr
, "Unknown TGSI texture target %d\n", texture
);
1236 ttn_tex(struct ttn_compile
*c
, nir_alu_dest dest
, nir_ssa_def
**src
)
1238 nir_builder
*b
= &c
->build
;
1239 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
1240 nir_tex_instr
*instr
;
1242 unsigned num_srcs
, samp
= 1, sview
, i
;
1244 switch (tgsi_inst
->Instruction
.Opcode
) {
1245 case TGSI_OPCODE_TEX
:
1249 case TGSI_OPCODE_TEX2
:
1254 case TGSI_OPCODE_TXP
:
1258 case TGSI_OPCODE_TXB
:
1262 case TGSI_OPCODE_TXB2
:
1267 case TGSI_OPCODE_TXL
:
1271 case TGSI_OPCODE_TXL2
:
1276 case TGSI_OPCODE_TXF
:
1277 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_2D_MSAA
||
1278 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1279 op
= nir_texop_txf_ms
;
1285 case TGSI_OPCODE_TXD
:
1290 case TGSI_OPCODE_LODQ
:
1296 fprintf(stderr
, "unknown TGSI tex op %d\n", tgsi_inst
->Instruction
.Opcode
);
1300 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
1301 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
1302 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
1303 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
1304 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
1305 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
1306 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1310 num_srcs
+= tgsi_inst
->Texture
.NumOffsets
;
1312 instr
= nir_tex_instr_create(b
->shader
, num_srcs
);
1315 setup_texture_info(instr
, tgsi_inst
->Texture
.Texture
);
1317 switch (instr
->sampler_dim
) {
1318 case GLSL_SAMPLER_DIM_1D
:
1319 case GLSL_SAMPLER_DIM_BUF
:
1320 instr
->coord_components
= 1;
1322 case GLSL_SAMPLER_DIM_2D
:
1323 case GLSL_SAMPLER_DIM_RECT
:
1324 case GLSL_SAMPLER_DIM_EXTERNAL
:
1325 case GLSL_SAMPLER_DIM_MS
:
1326 instr
->coord_components
= 2;
1328 case GLSL_SAMPLER_DIM_3D
:
1329 case GLSL_SAMPLER_DIM_CUBE
:
1330 instr
->coord_components
= 3;
1334 if (instr
->is_array
)
1335 instr
->coord_components
++;
1337 assert(tgsi_inst
->Src
[samp
].Register
.File
== TGSI_FILE_SAMPLER
);
1338 instr
->sampler_index
= tgsi_inst
->Src
[samp
].Register
.Index
;
1340 /* TODO if we supported any opc's which take an explicit SVIEW
1341 * src, we would use that here instead. But for the "legacy"
1342 * texture opc's the SVIEW index is same as SAMP index:
1344 sview
= instr
->sampler_index
;
1346 if (op
== nir_texop_lod
) {
1347 instr
->dest_type
= nir_type_float
;
1348 } else if (sview
< c
->num_samp_types
) {
1349 instr
->dest_type
= c
->samp_types
[sview
];
1351 instr
->dest_type
= nir_type_float
;
1354 unsigned src_number
= 0;
1356 instr
->src
[src_number
].src
=
1357 nir_src_for_ssa(nir_swizzle(b
, src
[0], SWIZ(X
, Y
, Z
, W
),
1358 instr
->coord_components
, false));
1359 instr
->src
[src_number
].src_type
= nir_tex_src_coord
;
1362 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1363 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1364 instr
->src
[src_number
].src_type
= nir_tex_src_projector
;
1368 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
) {
1369 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1370 instr
->src
[src_number
].src_type
= nir_tex_src_bias
;
1374 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
) {
1375 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[1], X
));
1376 instr
->src
[src_number
].src_type
= nir_tex_src_bias
;
1380 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
) {
1381 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1382 instr
->src
[src_number
].src_type
= nir_tex_src_lod
;
1386 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
1387 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[1], X
));
1388 instr
->src
[src_number
].src_type
= nir_tex_src_lod
;
1392 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
) {
1393 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1394 if (op
== nir_texop_txf_ms
)
1395 instr
->src
[src_number
].src_type
= nir_tex_src_ms_index
;
1397 instr
->src
[src_number
].src_type
= nir_tex_src_lod
;
1401 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
1402 instr
->src
[src_number
].src
=
1403 nir_src_for_ssa(nir_swizzle(b
, src
[1], SWIZ(X
, Y
, Z
, W
),
1404 instr
->coord_components
, false));
1405 instr
->src
[src_number
].src_type
= nir_tex_src_ddx
;
1407 instr
->src
[src_number
].src
=
1408 nir_src_for_ssa(nir_swizzle(b
, src
[2], SWIZ(X
, Y
, Z
, W
),
1409 instr
->coord_components
, false));
1410 instr
->src
[src_number
].src_type
= nir_tex_src_ddy
;
1414 if (instr
->is_shadow
) {
1415 if (instr
->coord_components
== 4)
1416 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[1], X
));
1417 else if (instr
->coord_components
== 3)
1418 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1420 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], Z
));
1422 instr
->src
[src_number
].src_type
= nir_tex_src_comparitor
;
1426 for (i
= 0; i
< tgsi_inst
->Texture
.NumOffsets
; i
++) {
1427 struct tgsi_texture_offset
*tex_offset
= &tgsi_inst
->TexOffsets
[i
];
1428 /* since TexOffset ins't using tgsi_full_src_register we get to
1429 * do some extra gymnastics:
1433 memset(&src
, 0, sizeof(src
));
1435 src
.src
= ttn_src_for_file_and_index(c
,
1440 src
.swizzle
[0] = tex_offset
->SwizzleX
;
1441 src
.swizzle
[1] = tex_offset
->SwizzleY
;
1442 src
.swizzle
[2] = tex_offset
->SwizzleZ
;
1443 src
.swizzle
[3] = TGSI_SWIZZLE_W
;
1445 instr
->src
[src_number
].src_type
= nir_tex_src_offset
;
1446 instr
->src
[src_number
].src
= nir_src_for_ssa(
1447 nir_fmov_alu(b
, src
, nir_tex_instr_src_size(instr
, src_number
)));
1451 assert(src_number
== num_srcs
);
1453 nir_ssa_dest_init(&instr
->instr
, &instr
->dest
, 4, NULL
);
1454 nir_builder_instr_insert(b
, &instr
->instr
);
1456 /* Resolve the writemask on the texture op. */
1457 ttn_move_dest(b
, dest
, &instr
->dest
.ssa
);
1460 /* TGSI_OPCODE_TXQ is actually two distinct operations:
1462 * dst.x = texture\_width(unit, lod)
1463 * dst.y = texture\_height(unit, lod)
1464 * dst.z = texture\_depth(unit, lod)
1465 * dst.w = texture\_levels(unit)
1467 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels
1470 ttn_txq(struct ttn_compile
*c
, nir_alu_dest dest
, nir_ssa_def
**src
)
1472 nir_builder
*b
= &c
->build
;
1473 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
1474 nir_tex_instr
*txs
, *qlv
;
1476 txs
= nir_tex_instr_create(b
->shader
, 1);
1477 txs
->op
= nir_texop_txs
;
1478 setup_texture_info(txs
, tgsi_inst
->Texture
.Texture
);
1480 qlv
= nir_tex_instr_create(b
->shader
, 0);
1481 qlv
->op
= nir_texop_query_levels
;
1482 setup_texture_info(qlv
, tgsi_inst
->Texture
.Texture
);
1484 assert(tgsi_inst
->Src
[1].Register
.File
== TGSI_FILE_SAMPLER
);
1485 txs
->sampler_index
= tgsi_inst
->Src
[1].Register
.Index
;
1486 qlv
->sampler_index
= tgsi_inst
->Src
[1].Register
.Index
;
1488 /* only single src, the lod: */
1489 txs
->src
[0].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], X
));
1490 txs
->src
[0].src_type
= nir_tex_src_lod
;
1492 nir_ssa_dest_init(&txs
->instr
, &txs
->dest
, 3, NULL
);
1493 nir_builder_instr_insert(b
, &txs
->instr
);
1495 nir_ssa_dest_init(&qlv
->instr
, &qlv
->dest
, 1, NULL
);
1496 nir_builder_instr_insert(b
, &qlv
->instr
);
1498 ttn_move_dest_masked(b
, dest
, &txs
->dest
.ssa
, TGSI_WRITEMASK_XYZ
);
1499 ttn_move_dest_masked(b
, dest
, &qlv
->dest
.ssa
, TGSI_WRITEMASK_W
);
1502 static const nir_op op_trans
[TGSI_OPCODE_LAST
] = {
1503 [TGSI_OPCODE_ARL
] = 0,
1504 [TGSI_OPCODE_MOV
] = nir_op_fmov
,
1505 [TGSI_OPCODE_LIT
] = 0,
1506 [TGSI_OPCODE_RCP
] = nir_op_frcp
,
1507 [TGSI_OPCODE_RSQ
] = nir_op_frsq
,
1508 [TGSI_OPCODE_EXP
] = 0,
1509 [TGSI_OPCODE_LOG
] = 0,
1510 [TGSI_OPCODE_MUL
] = nir_op_fmul
,
1511 [TGSI_OPCODE_ADD
] = nir_op_fadd
,
1512 [TGSI_OPCODE_DP3
] = 0,
1513 [TGSI_OPCODE_DP4
] = 0,
1514 [TGSI_OPCODE_DST
] = 0,
1515 [TGSI_OPCODE_MIN
] = nir_op_fmin
,
1516 [TGSI_OPCODE_MAX
] = nir_op_fmax
,
1517 [TGSI_OPCODE_SLT
] = nir_op_slt
,
1518 [TGSI_OPCODE_SGE
] = nir_op_sge
,
1519 [TGSI_OPCODE_MAD
] = nir_op_ffma
,
1520 [TGSI_OPCODE_SUB
] = nir_op_fsub
,
1521 [TGSI_OPCODE_LRP
] = 0,
1522 [TGSI_OPCODE_SQRT
] = nir_op_fsqrt
,
1523 [TGSI_OPCODE_DP2A
] = 0,
1524 [TGSI_OPCODE_FRC
] = nir_op_ffract
,
1525 [TGSI_OPCODE_CLAMP
] = 0,
1526 [TGSI_OPCODE_FLR
] = nir_op_ffloor
,
1527 [TGSI_OPCODE_ROUND
] = nir_op_fround_even
,
1528 [TGSI_OPCODE_EX2
] = nir_op_fexp2
,
1529 [TGSI_OPCODE_LG2
] = nir_op_flog2
,
1530 [TGSI_OPCODE_POW
] = nir_op_fpow
,
1531 [TGSI_OPCODE_XPD
] = 0,
1532 [TGSI_OPCODE_ABS
] = nir_op_fabs
,
1533 [TGSI_OPCODE_DPH
] = 0,
1534 [TGSI_OPCODE_COS
] = nir_op_fcos
,
1535 [TGSI_OPCODE_DDX
] = nir_op_fddx
,
1536 [TGSI_OPCODE_DDY
] = nir_op_fddy
,
1537 [TGSI_OPCODE_KILL
] = 0,
1538 [TGSI_OPCODE_PK2H
] = 0, /* XXX */
1539 [TGSI_OPCODE_PK2US
] = 0, /* XXX */
1540 [TGSI_OPCODE_PK4B
] = 0, /* XXX */
1541 [TGSI_OPCODE_PK4UB
] = 0, /* XXX */
1542 [TGSI_OPCODE_SEQ
] = nir_op_seq
,
1543 [TGSI_OPCODE_SGT
] = 0,
1544 [TGSI_OPCODE_SIN
] = nir_op_fsin
,
1545 [TGSI_OPCODE_SNE
] = nir_op_sne
,
1546 [TGSI_OPCODE_SLE
] = 0,
1547 [TGSI_OPCODE_TEX
] = 0,
1548 [TGSI_OPCODE_TXD
] = 0,
1549 [TGSI_OPCODE_TXP
] = 0,
1550 [TGSI_OPCODE_UP2H
] = 0, /* XXX */
1551 [TGSI_OPCODE_UP2US
] = 0, /* XXX */
1552 [TGSI_OPCODE_UP4B
] = 0, /* XXX */
1553 [TGSI_OPCODE_UP4UB
] = 0, /* XXX */
1554 [TGSI_OPCODE_ARR
] = 0,
1556 /* No function calls, yet. */
1557 [TGSI_OPCODE_CAL
] = 0, /* XXX */
1558 [TGSI_OPCODE_RET
] = 0, /* XXX */
1560 [TGSI_OPCODE_SSG
] = nir_op_fsign
,
1561 [TGSI_OPCODE_CMP
] = 0,
1562 [TGSI_OPCODE_SCS
] = 0,
1563 [TGSI_OPCODE_TXB
] = 0,
1564 [TGSI_OPCODE_DIV
] = nir_op_fdiv
,
1565 [TGSI_OPCODE_DP2
] = 0,
1566 [TGSI_OPCODE_DP2A
] = 0,
1567 [TGSI_OPCODE_TXL
] = 0,
1569 [TGSI_OPCODE_BRK
] = 0,
1570 [TGSI_OPCODE_IF
] = 0,
1571 [TGSI_OPCODE_UIF
] = 0,
1572 [TGSI_OPCODE_ELSE
] = 0,
1573 [TGSI_OPCODE_ENDIF
] = 0,
1575 [TGSI_OPCODE_DDX_FINE
] = nir_op_fddx_fine
,
1576 [TGSI_OPCODE_DDY_FINE
] = nir_op_fddy_fine
,
1578 [TGSI_OPCODE_PUSHA
] = 0, /* XXX */
1579 [TGSI_OPCODE_POPA
] = 0, /* XXX */
1581 [TGSI_OPCODE_CEIL
] = nir_op_fceil
,
1582 [TGSI_OPCODE_I2F
] = nir_op_i2f
,
1583 [TGSI_OPCODE_NOT
] = nir_op_inot
,
1584 [TGSI_OPCODE_TRUNC
] = nir_op_ftrunc
,
1585 [TGSI_OPCODE_SHL
] = nir_op_ishl
,
1586 [TGSI_OPCODE_AND
] = nir_op_iand
,
1587 [TGSI_OPCODE_OR
] = nir_op_ior
,
1588 [TGSI_OPCODE_MOD
] = nir_op_umod
,
1589 [TGSI_OPCODE_XOR
] = nir_op_ixor
,
1590 [TGSI_OPCODE_SAD
] = 0, /* XXX */
1591 [TGSI_OPCODE_TXF
] = 0,
1592 [TGSI_OPCODE_TXQ
] = 0,
1594 [TGSI_OPCODE_CONT
] = 0,
1596 [TGSI_OPCODE_EMIT
] = 0, /* XXX */
1597 [TGSI_OPCODE_ENDPRIM
] = 0, /* XXX */
1599 [TGSI_OPCODE_BGNLOOP
] = 0,
1600 [TGSI_OPCODE_BGNSUB
] = 0, /* XXX: no function calls */
1601 [TGSI_OPCODE_ENDLOOP
] = 0,
1602 [TGSI_OPCODE_ENDSUB
] = 0, /* XXX: no function calls */
1604 [TGSI_OPCODE_TXQ_LZ
] = 0,
1605 [TGSI_OPCODE_NOP
] = 0,
1606 [TGSI_OPCODE_FSEQ
] = nir_op_feq
,
1607 [TGSI_OPCODE_FSGE
] = nir_op_fge
,
1608 [TGSI_OPCODE_FSLT
] = nir_op_flt
,
1609 [TGSI_OPCODE_FSNE
] = nir_op_fne
,
1611 /* No control flow yet */
1612 [TGSI_OPCODE_CALLNZ
] = 0, /* XXX */
1613 [TGSI_OPCODE_BREAKC
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1615 [TGSI_OPCODE_KILL_IF
] = 0,
1617 [TGSI_OPCODE_END
] = 0,
1619 [TGSI_OPCODE_F2I
] = nir_op_f2i
,
1620 [TGSI_OPCODE_IDIV
] = nir_op_idiv
,
1621 [TGSI_OPCODE_IMAX
] = nir_op_imax
,
1622 [TGSI_OPCODE_IMIN
] = nir_op_imin
,
1623 [TGSI_OPCODE_INEG
] = nir_op_ineg
,
1624 [TGSI_OPCODE_ISGE
] = nir_op_ige
,
1625 [TGSI_OPCODE_ISHR
] = nir_op_ishr
,
1626 [TGSI_OPCODE_ISLT
] = nir_op_ilt
,
1627 [TGSI_OPCODE_F2U
] = nir_op_f2u
,
1628 [TGSI_OPCODE_U2F
] = nir_op_u2f
,
1629 [TGSI_OPCODE_UADD
] = nir_op_iadd
,
1630 [TGSI_OPCODE_UDIV
] = nir_op_udiv
,
1631 [TGSI_OPCODE_UMAD
] = 0,
1632 [TGSI_OPCODE_UMAX
] = nir_op_umax
,
1633 [TGSI_OPCODE_UMIN
] = nir_op_umin
,
1634 [TGSI_OPCODE_UMOD
] = nir_op_umod
,
1635 [TGSI_OPCODE_UMUL
] = nir_op_imul
,
1636 [TGSI_OPCODE_USEQ
] = nir_op_ieq
,
1637 [TGSI_OPCODE_USGE
] = nir_op_uge
,
1638 [TGSI_OPCODE_USHR
] = nir_op_ushr
,
1639 [TGSI_OPCODE_USLT
] = nir_op_ult
,
1640 [TGSI_OPCODE_USNE
] = nir_op_ine
,
1642 [TGSI_OPCODE_SWITCH
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1643 [TGSI_OPCODE_CASE
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1644 [TGSI_OPCODE_DEFAULT
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1645 [TGSI_OPCODE_ENDSWITCH
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1647 /* XXX: SAMPLE opcodes */
1649 [TGSI_OPCODE_UARL
] = nir_op_imov
,
1650 [TGSI_OPCODE_UCMP
] = 0,
1651 [TGSI_OPCODE_IABS
] = nir_op_iabs
,
1652 [TGSI_OPCODE_ISSG
] = nir_op_isign
,
1656 [TGSI_OPCODE_TEX2
] = 0,
1657 [TGSI_OPCODE_TXB2
] = 0,
1658 [TGSI_OPCODE_TXL2
] = 0,
1660 [TGSI_OPCODE_IMUL_HI
] = nir_op_imul_high
,
1661 [TGSI_OPCODE_UMUL_HI
] = nir_op_umul_high
,
1663 [TGSI_OPCODE_TG4
] = 0,
1664 [TGSI_OPCODE_LODQ
] = 0,
1666 [TGSI_OPCODE_IBFE
] = nir_op_ibitfield_extract
,
1667 [TGSI_OPCODE_UBFE
] = nir_op_ubitfield_extract
,
1668 [TGSI_OPCODE_BFI
] = nir_op_bitfield_insert
,
1669 [TGSI_OPCODE_BREV
] = nir_op_bitfield_reverse
,
1670 [TGSI_OPCODE_POPC
] = nir_op_bit_count
,
1671 [TGSI_OPCODE_LSB
] = nir_op_find_lsb
,
1672 [TGSI_OPCODE_IMSB
] = nir_op_ifind_msb
,
1673 [TGSI_OPCODE_UMSB
] = nir_op_ufind_msb
,
1675 [TGSI_OPCODE_INTERP_CENTROID
] = 0, /* XXX */
1676 [TGSI_OPCODE_INTERP_SAMPLE
] = 0, /* XXX */
1677 [TGSI_OPCODE_INTERP_OFFSET
] = 0, /* XXX */
1681 ttn_emit_instruction(struct ttn_compile
*c
)
1683 nir_builder
*b
= &c
->build
;
1684 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
1686 unsigned tgsi_op
= tgsi_inst
->Instruction
.Opcode
;
1687 struct tgsi_full_dst_register
*tgsi_dst
= &tgsi_inst
->Dst
[0];
1689 if (tgsi_op
== TGSI_OPCODE_END
)
1692 nir_ssa_def
*src
[TGSI_FULL_MAX_SRC_REGISTERS
];
1693 for (i
= 0; i
< tgsi_inst
->Instruction
.NumSrcRegs
; i
++) {
1694 src
[i
] = ttn_get_src(c
, &tgsi_inst
->Src
[i
]);
1696 nir_alu_dest dest
= ttn_get_dest(c
, tgsi_dst
);
1699 case TGSI_OPCODE_RSQ
:
1700 ttn_move_dest(b
, dest
, nir_frsq(b
, ttn_channel(b
, src
[0], X
)));
1703 case TGSI_OPCODE_SQRT
:
1704 ttn_move_dest(b
, dest
, nir_fsqrt(b
, ttn_channel(b
, src
[0], X
)));
1707 case TGSI_OPCODE_RCP
:
1708 ttn_move_dest(b
, dest
, nir_frcp(b
, ttn_channel(b
, src
[0], X
)));
1711 case TGSI_OPCODE_EX2
:
1712 ttn_move_dest(b
, dest
, nir_fexp2(b
, ttn_channel(b
, src
[0], X
)));
1715 case TGSI_OPCODE_LG2
:
1716 ttn_move_dest(b
, dest
, nir_flog2(b
, ttn_channel(b
, src
[0], X
)));
1719 case TGSI_OPCODE_POW
:
1720 ttn_move_dest(b
, dest
, nir_fpow(b
,
1721 ttn_channel(b
, src
[0], X
),
1722 ttn_channel(b
, src
[1], X
)));
1725 case TGSI_OPCODE_COS
:
1726 ttn_move_dest(b
, dest
, nir_fcos(b
, ttn_channel(b
, src
[0], X
)));
1729 case TGSI_OPCODE_SIN
:
1730 ttn_move_dest(b
, dest
, nir_fsin(b
, ttn_channel(b
, src
[0], X
)));
1733 case TGSI_OPCODE_ARL
:
1734 ttn_arl(b
, op_trans
[tgsi_op
], dest
, src
);
1737 case TGSI_OPCODE_EXP
:
1738 ttn_exp(b
, op_trans
[tgsi_op
], dest
, src
);
1741 case TGSI_OPCODE_LOG
:
1742 ttn_log(b
, op_trans
[tgsi_op
], dest
, src
);
1745 case TGSI_OPCODE_DST
:
1746 ttn_dst(b
, op_trans
[tgsi_op
], dest
, src
);
1749 case TGSI_OPCODE_LIT
:
1750 ttn_lit(b
, op_trans
[tgsi_op
], dest
, src
);
1753 case TGSI_OPCODE_CLAMP
:
1754 ttn_clamp(b
, op_trans
[tgsi_op
], dest
, src
);
1757 case TGSI_OPCODE_XPD
:
1758 ttn_xpd(b
, op_trans
[tgsi_op
], dest
, src
);
1761 case TGSI_OPCODE_DP2
:
1762 ttn_dp2(b
, op_trans
[tgsi_op
], dest
, src
);
1765 case TGSI_OPCODE_DP3
:
1766 ttn_dp3(b
, op_trans
[tgsi_op
], dest
, src
);
1769 case TGSI_OPCODE_DP4
:
1770 ttn_dp4(b
, op_trans
[tgsi_op
], dest
, src
);
1773 case TGSI_OPCODE_DP2A
:
1774 ttn_dp2a(b
, op_trans
[tgsi_op
], dest
, src
);
1777 case TGSI_OPCODE_DPH
:
1778 ttn_dph(b
, op_trans
[tgsi_op
], dest
, src
);
1781 case TGSI_OPCODE_UMAD
:
1782 ttn_umad(b
, op_trans
[tgsi_op
], dest
, src
);
1785 case TGSI_OPCODE_LRP
:
1786 ttn_move_dest(b
, dest
, nir_flrp(b
, src
[2], src
[1], src
[0]));
1789 case TGSI_OPCODE_KILL
:
1790 ttn_kill(b
, op_trans
[tgsi_op
], dest
, src
);
1793 case TGSI_OPCODE_ARR
:
1794 ttn_arr(b
, op_trans
[tgsi_op
], dest
, src
);
1797 case TGSI_OPCODE_CMP
:
1798 ttn_cmp(b
, op_trans
[tgsi_op
], dest
, src
);
1801 case TGSI_OPCODE_UCMP
:
1802 ttn_ucmp(b
, op_trans
[tgsi_op
], dest
, src
);
1805 case TGSI_OPCODE_SCS
:
1806 ttn_scs(b
, op_trans
[tgsi_op
], dest
, src
);
1809 case TGSI_OPCODE_SGT
:
1810 ttn_sgt(b
, op_trans
[tgsi_op
], dest
, src
);
1813 case TGSI_OPCODE_SLE
:
1814 ttn_sle(b
, op_trans
[tgsi_op
], dest
, src
);
1817 case TGSI_OPCODE_KILL_IF
:
1818 ttn_kill_if(b
, op_trans
[tgsi_op
], dest
, src
);
1821 case TGSI_OPCODE_TEX
:
1822 case TGSI_OPCODE_TXP
:
1823 case TGSI_OPCODE_TXL
:
1824 case TGSI_OPCODE_TXB
:
1825 case TGSI_OPCODE_TXD
:
1826 case TGSI_OPCODE_TEX2
:
1827 case TGSI_OPCODE_TXL2
:
1828 case TGSI_OPCODE_TXB2
:
1829 case TGSI_OPCODE_TXQ_LZ
:
1830 case TGSI_OPCODE_TXF
:
1831 case TGSI_OPCODE_TG4
:
1832 case TGSI_OPCODE_LODQ
:
1833 ttn_tex(c
, dest
, src
);
1836 case TGSI_OPCODE_TXQ
:
1837 ttn_txq(c
, dest
, src
);
1840 case TGSI_OPCODE_NOP
:
1843 case TGSI_OPCODE_IF
:
1844 ttn_if(c
, src
[0], false);
1847 case TGSI_OPCODE_UIF
:
1848 ttn_if(c
, src
[0], true);
1851 case TGSI_OPCODE_ELSE
:
1855 case TGSI_OPCODE_ENDIF
:
1859 case TGSI_OPCODE_BGNLOOP
:
1863 case TGSI_OPCODE_BRK
:
1867 case TGSI_OPCODE_CONT
:
1871 case TGSI_OPCODE_ENDLOOP
:
1876 if (op_trans
[tgsi_op
] != 0 || tgsi_op
== TGSI_OPCODE_MOV
) {
1877 ttn_alu(b
, op_trans
[tgsi_op
], dest
, src
);
1879 fprintf(stderr
, "unknown TGSI opcode: %s\n",
1880 tgsi_get_opcode_name(tgsi_op
));
1886 if (tgsi_inst
->Instruction
.Saturate
) {
1887 assert(!dest
.dest
.is_ssa
);
1888 ttn_move_dest(b
, dest
, nir_fsat(b
, ttn_src_for_dest(b
, &dest
)));
1891 /* if the dst has a matching var, append store_global to move
1892 * output from reg to var
1894 nir_variable
*var
= ttn_get_var(c
, tgsi_dst
);
1896 unsigned index
= tgsi_dst
->Register
.Index
;
1897 unsigned offset
= c
->temp_regs
[index
].offset
;
1898 nir_intrinsic_instr
*store
=
1899 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_var
);
1900 struct tgsi_ind_register
*indirect
= tgsi_dst
->Register
.Indirect
?
1901 &tgsi_dst
->Indirect
: NULL
;
1903 store
->num_components
= 4;
1904 store
->variables
[0] = ttn_array_deref(c
, store
, var
, offset
, indirect
);
1905 store
->src
[0] = nir_src_for_reg(dest
.dest
.reg
.reg
);
1907 nir_builder_instr_insert(b
, &store
->instr
);
1912 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
1913 * variables at the end of the shader.
1915 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
1916 * written, because there's no output load intrinsic, which means we couldn't
1917 * handle writemasks.
1920 ttn_add_output_stores(struct ttn_compile
*c
)
1922 nir_builder
*b
= &c
->build
;
1924 foreach_list_typed(nir_variable
, var
, node
, &b
->shader
->outputs
) {
1925 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1928 for (i
= 0; i
< array_len
; i
++) {
1929 nir_intrinsic_instr
*store
=
1930 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
1931 unsigned loc
= var
->data
.driver_location
+ i
;
1932 store
->num_components
= 4;
1933 store
->src
[0].reg
.reg
= c
->output_regs
[loc
].reg
;
1934 store
->src
[0].reg
.base_offset
= c
->output_regs
[loc
].offset
;
1935 store
->const_index
[0] = loc
;
1936 store
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
1937 nir_builder_instr_insert(b
, &store
->instr
);
1942 static gl_shader_stage
1943 tgsi_processor_to_shader_stage(unsigned processor
)
1945 switch (processor
) {
1946 case TGSI_PROCESSOR_FRAGMENT
: return MESA_SHADER_FRAGMENT
;
1947 case TGSI_PROCESSOR_VERTEX
: return MESA_SHADER_VERTEX
;
1948 case TGSI_PROCESSOR_GEOMETRY
: return MESA_SHADER_GEOMETRY
;
1949 case TGSI_PROCESSOR_TESS_CTRL
: return MESA_SHADER_TESS_CTRL
;
1950 case TGSI_PROCESSOR_TESS_EVAL
: return MESA_SHADER_TESS_EVAL
;
1951 case TGSI_PROCESSOR_COMPUTE
: return MESA_SHADER_COMPUTE
;
1953 unreachable("invalid TGSI processor");
1958 tgsi_to_nir(const void *tgsi_tokens
,
1959 const nir_shader_compiler_options
*options
)
1961 struct tgsi_parse_context parser
;
1962 struct tgsi_shader_info scan
;
1963 struct ttn_compile
*c
;
1964 struct nir_shader
*s
;
1967 c
= rzalloc(NULL
, struct ttn_compile
);
1969 tgsi_scan_shader(tgsi_tokens
, &scan
);
1972 s
= nir_shader_create(NULL
, tgsi_processor_to_shader_stage(scan
.processor
),
1975 nir_function
*func
= nir_function_create(s
, "main");
1976 nir_function_overload
*overload
= nir_function_overload_create(func
);
1977 nir_function_impl
*impl
= nir_function_impl_create(overload
);
1979 nir_builder_init(&c
->build
, impl
);
1980 c
->build
.cursor
= nir_after_cf_list(&impl
->body
);
1982 s
->num_inputs
= scan
.file_max
[TGSI_FILE_INPUT
] + 1;
1983 s
->num_uniforms
= scan
.const_file_max
[0] + 1;
1984 s
->num_outputs
= scan
.file_max
[TGSI_FILE_OUTPUT
] + 1;
1986 c
->output_regs
= rzalloc_array(c
, struct ttn_reg_info
,
1987 scan
.file_max
[TGSI_FILE_OUTPUT
] + 1);
1988 c
->temp_regs
= rzalloc_array(c
, struct ttn_reg_info
,
1989 scan
.file_max
[TGSI_FILE_TEMPORARY
] + 1);
1990 c
->imm_defs
= rzalloc_array(c
, nir_ssa_def
*,
1991 scan
.file_max
[TGSI_FILE_IMMEDIATE
] + 1);
1993 c
->num_samp_types
= scan
.file_max
[TGSI_FILE_SAMPLER_VIEW
] + 1;
1994 c
->samp_types
= rzalloc_array(c
, nir_alu_type
, c
->num_samp_types
);
1996 c
->if_stack
= rzalloc_array(c
, nir_cursor
,
1997 (scan
.opcode_count
[TGSI_OPCODE_IF
] +
1998 scan
.opcode_count
[TGSI_OPCODE_UIF
]) * 2);
1999 c
->loop_stack
= rzalloc_array(c
, nir_cursor
,
2000 scan
.opcode_count
[TGSI_OPCODE_BGNLOOP
]);
2002 ret
= tgsi_parse_init(&parser
, tgsi_tokens
);
2003 assert(ret
== TGSI_PARSE_OK
);
2005 while (!tgsi_parse_end_of_tokens(&parser
)) {
2006 tgsi_parse_token(&parser
);
2007 c
->token
= &parser
.FullToken
;
2009 switch (parser
.FullToken
.Token
.Type
) {
2010 case TGSI_TOKEN_TYPE_DECLARATION
:
2011 ttn_emit_declaration(c
);
2014 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2015 ttn_emit_instruction(c
);
2018 case TGSI_TOKEN_TYPE_IMMEDIATE
:
2019 ttn_emit_immediate(c
);
2024 tgsi_parse_free(&parser
);
2026 ttn_add_output_stores(c
);