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[mesa.git] / src / gallium / auxiliary / nir / tgsi_to_nir.c
1 /*
2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/ralloc.h"
26 #include "pipe/p_screen.h"
27
28 #include "compiler/nir/nir.h"
29 #include "compiler/nir/nir_control_flow.h"
30 #include "compiler/nir/nir_builder.h"
31 #include "compiler/glsl/gl_nir.h"
32 #include "compiler/glsl/list.h"
33 #include "compiler/shader_enums.h"
34
35 #include "tgsi_to_nir.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_dump.h"
38 #include "tgsi/tgsi_info.h"
39 #include "tgsi/tgsi_scan.h"
40 #include "tgsi/tgsi_from_mesa.h"
41
42 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
43 TGSI_SWIZZLE_##X, \
44 TGSI_SWIZZLE_##Y, \
45 TGSI_SWIZZLE_##Z, \
46 TGSI_SWIZZLE_##W, \
47 }
48
49 struct ttn_reg_info {
50 /** nir register containing this TGSI index. */
51 nir_register *reg;
52 nir_variable *var;
53 /** Offset (in vec4s) from the start of var for this TGSI index. */
54 int offset;
55 };
56
57 struct ttn_compile {
58 union tgsi_full_token *token;
59 nir_builder build;
60 struct tgsi_shader_info *scan;
61
62 struct ttn_reg_info *output_regs;
63 struct ttn_reg_info *temp_regs;
64 nir_ssa_def **imm_defs;
65
66 unsigned num_samp_types;
67 nir_alu_type *samp_types;
68
69 nir_register *addr_reg;
70
71 nir_variable **inputs;
72 nir_variable **outputs;
73 nir_variable *samplers[PIPE_MAX_SAMPLERS];
74 nir_variable *images[PIPE_MAX_SHADER_IMAGES];
75 nir_variable *ssbo[PIPE_MAX_SHADER_BUFFERS];
76
77 nir_variable *input_var_face;
78 nir_variable *input_var_position;
79 nir_variable *input_var_point;
80
81 /**
82 * Stack of nir_cursors where instructions should be pushed as we pop
83 * back out of the control flow stack.
84 *
85 * For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else
86 * instructions should be placed, and if_stack[if_stack_pos - 1] has where
87 * the next instructions outside of the if/then/else block go.
88 */
89 nir_cursor *if_stack;
90 unsigned if_stack_pos;
91
92 /**
93 * Stack of nir_cursors where instructions should be pushed as we pop
94 * back out of the control flow stack.
95 *
96 * loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside
97 * of the loop.
98 */
99 nir_cursor *loop_stack;
100 unsigned loop_stack_pos;
101
102 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
103 unsigned next_imm;
104
105 bool cap_scalar;
106 bool cap_face_is_sysval;
107 bool cap_position_is_sysval;
108 bool cap_point_is_sysval;
109 bool cap_packed_uniforms;
110 bool cap_samplers_as_deref;
111 };
112
113 #define ttn_swizzle(b, src, x, y, z, w) \
114 nir_swizzle(b, src, SWIZ(x, y, z, w), 4)
115 #define ttn_channel(b, src, swiz) \
116 nir_channel(b, src, TGSI_SWIZZLE_##swiz)
117
118 static gl_varying_slot
119 tgsi_varying_semantic_to_slot(unsigned semantic, unsigned index)
120 {
121 switch (semantic) {
122 case TGSI_SEMANTIC_POSITION:
123 return VARYING_SLOT_POS;
124 case TGSI_SEMANTIC_COLOR:
125 if (index == 0)
126 return VARYING_SLOT_COL0;
127 else
128 return VARYING_SLOT_COL1;
129 case TGSI_SEMANTIC_BCOLOR:
130 if (index == 0)
131 return VARYING_SLOT_BFC0;
132 else
133 return VARYING_SLOT_BFC1;
134 case TGSI_SEMANTIC_FOG:
135 return VARYING_SLOT_FOGC;
136 case TGSI_SEMANTIC_PSIZE:
137 return VARYING_SLOT_PSIZ;
138 case TGSI_SEMANTIC_GENERIC:
139 assert(index < 32);
140 return VARYING_SLOT_VAR0 + index;
141 case TGSI_SEMANTIC_FACE:
142 return VARYING_SLOT_FACE;
143 case TGSI_SEMANTIC_EDGEFLAG:
144 return VARYING_SLOT_EDGE;
145 case TGSI_SEMANTIC_PRIMID:
146 return VARYING_SLOT_PRIMITIVE_ID;
147 case TGSI_SEMANTIC_CLIPDIST:
148 if (index == 0)
149 return VARYING_SLOT_CLIP_DIST0;
150 else
151 return VARYING_SLOT_CLIP_DIST1;
152 case TGSI_SEMANTIC_CLIPVERTEX:
153 return VARYING_SLOT_CLIP_VERTEX;
154 case TGSI_SEMANTIC_TEXCOORD:
155 assert(index < 8);
156 return VARYING_SLOT_TEX0 + index;
157 case TGSI_SEMANTIC_PCOORD:
158 return VARYING_SLOT_PNTC;
159 case TGSI_SEMANTIC_VIEWPORT_INDEX:
160 return VARYING_SLOT_VIEWPORT;
161 case TGSI_SEMANTIC_LAYER:
162 return VARYING_SLOT_LAYER;
163 case TGSI_SEMANTIC_TESSINNER:
164 return VARYING_SLOT_TESS_LEVEL_INNER;
165 case TGSI_SEMANTIC_TESSOUTER:
166 return VARYING_SLOT_TESS_LEVEL_OUTER;
167 default:
168 fprintf(stderr, "Bad TGSI semantic: %d/%d\n", semantic, index);
169 abort();
170 }
171 }
172
173 static enum gl_frag_depth_layout
174 ttn_get_depth_layout(unsigned tgsi_fs_depth_layout)
175 {
176 switch (tgsi_fs_depth_layout) {
177 case TGSI_FS_DEPTH_LAYOUT_NONE:
178 return FRAG_DEPTH_LAYOUT_NONE;
179 case TGSI_FS_DEPTH_LAYOUT_ANY:
180 return FRAG_DEPTH_LAYOUT_ANY;
181 case TGSI_FS_DEPTH_LAYOUT_GREATER:
182 return FRAG_DEPTH_LAYOUT_GREATER;
183 case TGSI_FS_DEPTH_LAYOUT_LESS:
184 return FRAG_DEPTH_LAYOUT_LESS;
185 case TGSI_FS_DEPTH_LAYOUT_UNCHANGED:
186 return FRAG_DEPTH_LAYOUT_UNCHANGED;
187 default:
188 unreachable("bad TGSI FS depth layout");
189 }
190 }
191
192 static nir_ssa_def *
193 ttn_src_for_dest(nir_builder *b, nir_alu_dest *dest)
194 {
195 nir_alu_src src;
196 memset(&src, 0, sizeof(src));
197
198 if (dest->dest.is_ssa)
199 src.src = nir_src_for_ssa(&dest->dest.ssa);
200 else {
201 assert(!dest->dest.reg.indirect);
202 src.src = nir_src_for_reg(dest->dest.reg.reg);
203 src.src.reg.base_offset = dest->dest.reg.base_offset;
204 }
205
206 for (int i = 0; i < 4; i++)
207 src.swizzle[i] = i;
208
209 return nir_mov_alu(b, src, 4);
210 }
211
212 static enum glsl_interp_mode
213 ttn_translate_interp_mode(unsigned tgsi_interp)
214 {
215 switch (tgsi_interp) {
216 case TGSI_INTERPOLATE_CONSTANT:
217 return INTERP_MODE_FLAT;
218 case TGSI_INTERPOLATE_LINEAR:
219 return INTERP_MODE_NOPERSPECTIVE;
220 case TGSI_INTERPOLATE_PERSPECTIVE:
221 return INTERP_MODE_SMOOTH;
222 case TGSI_INTERPOLATE_COLOR:
223 return INTERP_MODE_SMOOTH;
224 default:
225 unreachable("bad TGSI interpolation mode");
226 }
227 }
228
229 static void
230 ttn_emit_declaration(struct ttn_compile *c)
231 {
232 nir_builder *b = &c->build;
233 struct tgsi_full_declaration *decl = &c->token->FullDeclaration;
234 unsigned array_size = decl->Range.Last - decl->Range.First + 1;
235 unsigned file = decl->Declaration.File;
236 unsigned i;
237
238 if (file == TGSI_FILE_TEMPORARY) {
239 if (decl->Declaration.Array) {
240 /* for arrays, we create variables instead of registers: */
241 nir_variable *var = rzalloc(b->shader, nir_variable);
242
243 var->type = glsl_array_type(glsl_vec4_type(), array_size, 0);
244 var->data.mode = nir_var_shader_temp;
245 var->name = ralloc_asprintf(var, "arr_%d", decl->Array.ArrayID);
246
247 exec_list_push_tail(&b->shader->globals, &var->node);
248
249 for (i = 0; i < array_size; i++) {
250 /* point all the matching slots to the same var,
251 * with appropriate offset set, mostly just so
252 * we know what to do when tgsi does a non-indirect
253 * access
254 */
255 c->temp_regs[decl->Range.First + i].reg = NULL;
256 c->temp_regs[decl->Range.First + i].var = var;
257 c->temp_regs[decl->Range.First + i].offset = i;
258 }
259 } else {
260 for (i = 0; i < array_size; i++) {
261 nir_register *reg = nir_local_reg_create(b->impl);
262 reg->num_components = 4;
263 c->temp_regs[decl->Range.First + i].reg = reg;
264 c->temp_regs[decl->Range.First + i].var = NULL;
265 c->temp_regs[decl->Range.First + i].offset = 0;
266 }
267 }
268 } else if (file == TGSI_FILE_ADDRESS) {
269 c->addr_reg = nir_local_reg_create(b->impl);
270 c->addr_reg->num_components = 4;
271 } else if (file == TGSI_FILE_SYSTEM_VALUE) {
272 /* Nothing to record for system values. */
273 } else if (file == TGSI_FILE_BUFFER) {
274 /* Nothing to record for buffers. */
275 } else if (file == TGSI_FILE_IMAGE) {
276 /* Nothing to record for images. */
277 } else if (file == TGSI_FILE_SAMPLER) {
278 /* Nothing to record for samplers. */
279 } else if (file == TGSI_FILE_SAMPLER_VIEW) {
280 struct tgsi_declaration_sampler_view *sview = &decl->SamplerView;
281 nir_alu_type type;
282
283 assert((sview->ReturnTypeX == sview->ReturnTypeY) &&
284 (sview->ReturnTypeX == sview->ReturnTypeZ) &&
285 (sview->ReturnTypeX == sview->ReturnTypeW));
286
287 switch (sview->ReturnTypeX) {
288 case TGSI_RETURN_TYPE_SINT:
289 type = nir_type_int;
290 break;
291 case TGSI_RETURN_TYPE_UINT:
292 type = nir_type_uint;
293 break;
294 case TGSI_RETURN_TYPE_FLOAT:
295 default:
296 type = nir_type_float;
297 break;
298 }
299
300 for (i = 0; i < array_size; i++) {
301 c->samp_types[decl->Range.First + i] = type;
302 }
303 } else {
304 bool is_array = (array_size > 1);
305
306 assert(file == TGSI_FILE_INPUT ||
307 file == TGSI_FILE_OUTPUT ||
308 file == TGSI_FILE_CONSTANT);
309
310 /* nothing to do for UBOs: */
311 if ((file == TGSI_FILE_CONSTANT) && decl->Declaration.Dimension &&
312 decl->Dim.Index2D != 0) {
313 b->shader->info.num_ubos =
314 MAX2(b->shader->info.num_ubos, decl->Dim.Index2D);
315 return;
316 }
317
318 if ((file == TGSI_FILE_INPUT) || (file == TGSI_FILE_OUTPUT)) {
319 is_array = (is_array && decl->Declaration.Array &&
320 (decl->Array.ArrayID != 0));
321 }
322
323 for (i = 0; i < array_size; i++) {
324 unsigned idx = decl->Range.First + i;
325 nir_variable *var = rzalloc(b->shader, nir_variable);
326
327 var->data.driver_location = idx;
328
329 var->type = glsl_vec4_type();
330 if (is_array)
331 var->type = glsl_array_type(var->type, array_size, 0);
332
333 switch (file) {
334 case TGSI_FILE_INPUT:
335 var->data.read_only = true;
336 var->data.mode = nir_var_shader_in;
337 var->name = ralloc_asprintf(var, "in_%d", idx);
338
339 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
340 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
341 var->type = glsl_bool_type();
342 if (c->cap_face_is_sysval) {
343 var->data.mode = nir_var_system_value;
344 var->data.location = SYSTEM_VALUE_FRONT_FACE;
345 } else {
346 var->data.location = VARYING_SLOT_FACE;
347 }
348 c->input_var_face = var;
349 } else if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
350 if (c->cap_position_is_sysval) {
351 var->data.mode = nir_var_system_value;
352 var->data.location = SYSTEM_VALUE_FRAG_COORD;
353 } else {
354 var->data.location = VARYING_SLOT_POS;
355 }
356 c->input_var_position = var;
357 } else if (decl->Semantic.Name == TGSI_SEMANTIC_PCOORD) {
358 if (c->cap_point_is_sysval) {
359 var->data.mode = nir_var_system_value;
360 var->data.location = SYSTEM_VALUE_POINT_COORD;
361 } else {
362 var->data.location = VARYING_SLOT_PNTC;
363 }
364 c->input_var_point = var;
365 } else {
366 var->data.location =
367 tgsi_varying_semantic_to_slot(decl->Semantic.Name,
368 decl->Semantic.Index);
369 }
370 } else {
371 assert(!decl->Declaration.Semantic);
372 var->data.location = VERT_ATTRIB_GENERIC0 + idx;
373 }
374 var->data.index = 0;
375 var->data.interpolation =
376 ttn_translate_interp_mode(decl->Interp.Interpolate);
377
378 exec_list_push_tail(&b->shader->inputs, &var->node);
379 c->inputs[idx] = var;
380
381 for (int i = 0; i < array_size; i++)
382 b->shader->info.inputs_read |= 1 << (var->data.location + i);
383
384 break;
385 case TGSI_FILE_OUTPUT: {
386 int semantic_name = decl->Semantic.Name;
387 int semantic_index = decl->Semantic.Index;
388 /* Since we can't load from outputs in the IR, we make temporaries
389 * for the outputs and emit stores to the real outputs at the end of
390 * the shader.
391 */
392 nir_register *reg = nir_local_reg_create(b->impl);
393 reg->num_components = 4;
394 if (is_array)
395 reg->num_array_elems = array_size;
396
397 var->data.mode = nir_var_shader_out;
398 var->name = ralloc_asprintf(var, "out_%d", idx);
399 var->data.index = 0;
400 var->data.interpolation =
401 ttn_translate_interp_mode(decl->Interp.Interpolate);
402 var->data.patch = semantic_name == TGSI_SEMANTIC_TESSINNER ||
403 semantic_name == TGSI_SEMANTIC_TESSOUTER ||
404 semantic_name == TGSI_SEMANTIC_PATCH;
405
406 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
407 switch (semantic_name) {
408 case TGSI_SEMANTIC_COLOR: {
409 /* TODO tgsi loses some information, so we cannot
410 * actually differentiate here between DSB and MRT
411 * at this point. But so far no drivers using tgsi-
412 * to-nir support dual source blend:
413 */
414 bool dual_src_blend = false;
415 if (dual_src_blend && (semantic_index == 1)) {
416 var->data.location = FRAG_RESULT_DATA0;
417 var->data.index = 1;
418 } else {
419 if (c->scan->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
420 var->data.location = FRAG_RESULT_COLOR;
421 else
422 var->data.location = FRAG_RESULT_DATA0 + semantic_index;
423 }
424 break;
425 }
426 case TGSI_SEMANTIC_POSITION:
427 var->data.location = FRAG_RESULT_DEPTH;
428 var->type = glsl_float_type();
429 break;
430 case TGSI_SEMANTIC_STENCIL:
431 var->data.location = FRAG_RESULT_STENCIL;
432 var->type = glsl_int_type();
433 break;
434 default:
435 fprintf(stderr, "Bad TGSI semantic: %d/%d\n",
436 decl->Semantic.Name, decl->Semantic.Index);
437 abort();
438 }
439 } else {
440 var->data.location =
441 tgsi_varying_semantic_to_slot(semantic_name, semantic_index);
442 }
443
444 if (is_array) {
445 unsigned j;
446 for (j = 0; j < array_size; j++) {
447 c->output_regs[idx + j].offset = i + j;
448 c->output_regs[idx + j].reg = reg;
449 }
450 } else {
451 c->output_regs[idx].offset = i;
452 c->output_regs[idx].reg = reg;
453 }
454
455 exec_list_push_tail(&b->shader->outputs, &var->node);
456 c->outputs[idx] = var;
457
458 for (int i = 0; i < array_size; i++)
459 b->shader->info.outputs_written |= 1ull << (var->data.location + i);
460 }
461 break;
462 case TGSI_FILE_CONSTANT:
463 var->data.mode = nir_var_uniform;
464 var->name = ralloc_asprintf(var, "uniform_%d", idx);
465 var->data.location = idx;
466
467 exec_list_push_tail(&b->shader->uniforms, &var->node);
468 break;
469 default:
470 unreachable("bad declaration file");
471 return;
472 }
473
474 if (is_array)
475 break;
476 }
477
478 }
479 }
480
481 static void
482 ttn_emit_immediate(struct ttn_compile *c)
483 {
484 nir_builder *b = &c->build;
485 struct tgsi_full_immediate *tgsi_imm = &c->token->FullImmediate;
486 nir_load_const_instr *load_const;
487 int i;
488
489 load_const = nir_load_const_instr_create(b->shader, 4, 32);
490 c->imm_defs[c->next_imm] = &load_const->def;
491 c->next_imm++;
492
493 for (i = 0; i < load_const->def.num_components; i++)
494 load_const->value[i].u32 = tgsi_imm->u[i].Uint;
495
496 nir_builder_instr_insert(b, &load_const->instr);
497 }
498
499 static nir_ssa_def *
500 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect);
501
502 /* generate either a constant or indirect deref chain for accessing an
503 * array variable.
504 */
505 static nir_deref_instr *
506 ttn_array_deref(struct ttn_compile *c, nir_variable *var, unsigned offset,
507 struct tgsi_ind_register *indirect)
508 {
509 nir_deref_instr *deref = nir_build_deref_var(&c->build, var);
510 nir_ssa_def *index = nir_imm_int(&c->build, offset);
511 if (indirect)
512 index = nir_iadd(&c->build, index, ttn_src_for_indirect(c, indirect));
513 return nir_build_deref_array(&c->build, deref, index);
514 }
515
516 /* Special case: Turn the frontface varying into a load of the
517 * frontface variable, and create the vector as required by TGSI.
518 */
519 static nir_ssa_def *
520 ttn_emulate_tgsi_front_face(struct ttn_compile *c)
521 {
522 nir_ssa_def *tgsi_frontface[4];
523
524 if (c->cap_face_is_sysval) {
525 /* When it's a system value, it should be an integer vector: (F, 0, 0, 1)
526 * F is 0xffffffff if front-facing, 0 if not.
527 */
528
529 nir_ssa_def *frontface = nir_load_front_face(&c->build, 1);
530
531 tgsi_frontface[0] = nir_bcsel(&c->build,
532 frontface,
533 nir_imm_int(&c->build, 0xffffffff),
534 nir_imm_int(&c->build, 0));
535 tgsi_frontface[1] = nir_imm_int(&c->build, 0);
536 tgsi_frontface[2] = nir_imm_int(&c->build, 0);
537 tgsi_frontface[3] = nir_imm_int(&c->build, 1);
538 } else {
539 /* When it's an input, it should be a float vector: (F, 0.0, 0.0, 1.0)
540 * F is positive if front-facing, negative if not.
541 */
542
543 assert(c->input_var_face);
544 nir_ssa_def *frontface = nir_load_var(&c->build, c->input_var_face);
545
546 tgsi_frontface[0] = nir_bcsel(&c->build,
547 frontface,
548 nir_imm_float(&c->build, 1.0),
549 nir_imm_float(&c->build, -1.0));
550 tgsi_frontface[1] = nir_imm_float(&c->build, 0.0);
551 tgsi_frontface[2] = nir_imm_float(&c->build, 0.0);
552 tgsi_frontface[3] = nir_imm_float(&c->build, 1.0);
553 }
554
555 return nir_vec(&c->build, tgsi_frontface, 4);
556 }
557
558 static nir_src
559 ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
560 struct tgsi_ind_register *indirect,
561 struct tgsi_dimension *dim,
562 struct tgsi_ind_register *dimind,
563 bool src_is_float)
564 {
565 nir_builder *b = &c->build;
566 nir_src src;
567
568 memset(&src, 0, sizeof(src));
569
570 switch (file) {
571 case TGSI_FILE_TEMPORARY:
572 if (c->temp_regs[index].var) {
573 unsigned offset = c->temp_regs[index].offset;
574 nir_variable *var = c->temp_regs[index].var;
575 nir_ssa_def *load = nir_load_deref(&c->build,
576 ttn_array_deref(c, var, offset, indirect));
577
578 src = nir_src_for_ssa(load);
579 } else {
580 assert(!indirect);
581 src.reg.reg = c->temp_regs[index].reg;
582 }
583 assert(!dim);
584 break;
585
586 case TGSI_FILE_ADDRESS:
587 src.reg.reg = c->addr_reg;
588 assert(!dim);
589 break;
590
591 case TGSI_FILE_IMMEDIATE:
592 src = nir_src_for_ssa(c->imm_defs[index]);
593 assert(!indirect);
594 assert(!dim);
595 break;
596
597 case TGSI_FILE_SYSTEM_VALUE: {
598 nir_intrinsic_op op;
599 nir_ssa_def *load;
600
601 assert(!indirect);
602 assert(!dim);
603
604 switch (c->scan->system_value_semantic_name[index]) {
605 case TGSI_SEMANTIC_VERTEXID_NOBASE:
606 op = nir_intrinsic_load_vertex_id_zero_base;
607 load = nir_load_vertex_id_zero_base(b);
608 break;
609 case TGSI_SEMANTIC_VERTEXID:
610 op = nir_intrinsic_load_vertex_id;
611 load = nir_load_vertex_id(b);
612 break;
613 case TGSI_SEMANTIC_BASEVERTEX:
614 op = nir_intrinsic_load_base_vertex;
615 load = nir_load_base_vertex(b);
616 break;
617 case TGSI_SEMANTIC_INSTANCEID:
618 op = nir_intrinsic_load_instance_id;
619 load = nir_load_instance_id(b);
620 break;
621 case TGSI_SEMANTIC_FACE:
622 assert(c->cap_face_is_sysval);
623 op = nir_intrinsic_load_front_face;
624 load = ttn_emulate_tgsi_front_face(c);
625 break;
626 case TGSI_SEMANTIC_POSITION:
627 assert(c->cap_position_is_sysval);
628 op = nir_intrinsic_load_frag_coord;
629 load = nir_load_frag_coord(b);
630 break;
631 case TGSI_SEMANTIC_PCOORD:
632 assert(c->cap_point_is_sysval);
633 op = nir_intrinsic_load_point_coord;
634 load = nir_load_point_coord(b);
635 break;
636 case TGSI_SEMANTIC_THREAD_ID:
637 op = nir_intrinsic_load_local_invocation_id;
638 load = nir_load_local_invocation_id(b);
639 break;
640 case TGSI_SEMANTIC_BLOCK_ID:
641 op = nir_intrinsic_load_work_group_id;
642 load = nir_load_work_group_id(b);
643 break;
644 case TGSI_SEMANTIC_CS_USER_DATA_AMD:
645 op = nir_intrinsic_load_user_data_amd;
646 load = nir_load_user_data_amd(b);
647 break;
648 case TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL:
649 op = nir_intrinsic_load_tess_level_inner_default;
650 load = nir_load_tess_level_inner_default(b);
651 break;
652 case TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL:
653 op = nir_intrinsic_load_tess_level_outer_default;
654 load = nir_load_tess_level_outer_default(b);
655 break;
656 default:
657 unreachable("bad system value");
658 }
659
660 if (load->num_components == 3)
661 load = nir_swizzle(b, load, SWIZ(X, Y, Z, Z), 4);
662
663 src = nir_src_for_ssa(load);
664 b->shader->info.system_values_read |=
665 (1 << nir_system_value_from_intrinsic(op));
666
667 break;
668 }
669
670 case TGSI_FILE_INPUT:
671 if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
672 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_FACE) {
673 assert(!c->cap_face_is_sysval && c->input_var_face);
674 return nir_src_for_ssa(ttn_emulate_tgsi_front_face(c));
675 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
676 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_POSITION) {
677 assert(!c->cap_position_is_sysval && c->input_var_position);
678 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_position));
679 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
680 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_PCOORD) {
681 assert(!c->cap_point_is_sysval && c->input_var_point);
682 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_point));
683 } else {
684 /* Indirection on input arrays isn't supported by TTN. */
685 assert(!dim);
686 nir_deref_instr *deref = nir_build_deref_var(&c->build,
687 c->inputs[index]);
688 return nir_src_for_ssa(nir_load_deref(&c->build, deref));
689 }
690 break;
691
692 case TGSI_FILE_CONSTANT: {
693 nir_intrinsic_instr *load;
694 nir_intrinsic_op op;
695 unsigned srcn = 0;
696
697 if (dim && (dim->Index > 0 || dim->Indirect)) {
698 op = nir_intrinsic_load_ubo;
699 } else {
700 op = nir_intrinsic_load_uniform;
701 }
702
703 load = nir_intrinsic_instr_create(b->shader, op);
704 if (op == nir_intrinsic_load_uniform) {
705 nir_intrinsic_set_type(load, src_is_float ? nir_type_float :
706 nir_type_int);
707 }
708
709 load->num_components = 4;
710 if (dim && (dim->Index > 0 || dim->Indirect)) {
711 if (dimind) {
712 load->src[srcn] =
713 ttn_src_for_file_and_index(c, dimind->File, dimind->Index,
714 NULL, NULL, NULL, false);
715 } else {
716 /* UBOs start at index 1 in TGSI: */
717 load->src[srcn] =
718 nir_src_for_ssa(nir_imm_int(b, dim->Index - 1));
719 }
720 srcn++;
721 }
722
723 nir_ssa_def *offset;
724 if (op == nir_intrinsic_load_ubo) {
725 /* UBO loads don't have a base offset. */
726 offset = nir_imm_int(b, index);
727 if (indirect) {
728 offset = nir_iadd(b, offset, ttn_src_for_indirect(c, indirect));
729 }
730 /* UBO offsets are in bytes, but TGSI gives them to us in vec4's */
731 offset = nir_ishl(b, offset, nir_imm_int(b, 4));
732 } else {
733 nir_intrinsic_set_base(load, index);
734 if (indirect) {
735 offset = ttn_src_for_indirect(c, indirect);
736 } else {
737 offset = nir_imm_int(b, 0);
738 }
739 }
740 load->src[srcn++] = nir_src_for_ssa(offset);
741
742 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
743 nir_builder_instr_insert(b, &load->instr);
744
745 src = nir_src_for_ssa(&load->dest.ssa);
746 break;
747 }
748
749 default:
750 unreachable("bad src file");
751 }
752
753
754 return src;
755 }
756
757 static nir_ssa_def *
758 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect)
759 {
760 nir_builder *b = &c->build;
761 nir_alu_src src;
762 memset(&src, 0, sizeof(src));
763 for (int i = 0; i < 4; i++)
764 src.swizzle[i] = indirect->Swizzle;
765 src.src = ttn_src_for_file_and_index(c,
766 indirect->File,
767 indirect->Index,
768 NULL, NULL, NULL,
769 false);
770 return nir_mov_alu(b, src, 1);
771 }
772
773 static nir_alu_dest
774 ttn_get_dest(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
775 {
776 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
777 nir_alu_dest dest;
778 unsigned index = tgsi_dst->Index;
779
780 memset(&dest, 0, sizeof(dest));
781
782 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
783 if (c->temp_regs[index].var) {
784 nir_register *reg;
785
786 /* this works, because TGSI will give us a base offset
787 * (in case of indirect index) that points back into
788 * the array. Access can be direct or indirect, we
789 * don't really care. Just create a one-shot dst reg
790 * that will get store_var'd back into the array var
791 * at the end of ttn_emit_instruction()
792 */
793 reg = nir_local_reg_create(c->build.impl);
794 reg->num_components = 4;
795 dest.dest.reg.reg = reg;
796 dest.dest.reg.base_offset = 0;
797 } else {
798 assert(!tgsi_dst->Indirect);
799 dest.dest.reg.reg = c->temp_regs[index].reg;
800 dest.dest.reg.base_offset = c->temp_regs[index].offset;
801 }
802 } else if (tgsi_dst->File == TGSI_FILE_OUTPUT) {
803 dest.dest.reg.reg = c->output_regs[index].reg;
804 dest.dest.reg.base_offset = c->output_regs[index].offset;
805 } else if (tgsi_dst->File == TGSI_FILE_ADDRESS) {
806 assert(index == 0);
807 dest.dest.reg.reg = c->addr_reg;
808 }
809
810 dest.write_mask = tgsi_dst->WriteMask;
811 dest.saturate = false;
812
813 if (tgsi_dst->Indirect && (tgsi_dst->File != TGSI_FILE_TEMPORARY)) {
814 nir_src *indirect = ralloc(c->build.shader, nir_src);
815 *indirect = nir_src_for_ssa(ttn_src_for_indirect(c, &tgsi_fdst->Indirect));
816 dest.dest.reg.indirect = indirect;
817 }
818
819 return dest;
820 }
821
822 static nir_variable *
823 ttn_get_var(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
824 {
825 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
826 unsigned index = tgsi_dst->Index;
827
828 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
829 /* we should not have an indirect when there is no var! */
830 if (!c->temp_regs[index].var)
831 assert(!tgsi_dst->Indirect);
832 return c->temp_regs[index].var;
833 }
834
835 return NULL;
836 }
837
838 static nir_ssa_def *
839 ttn_get_src(struct ttn_compile *c, struct tgsi_full_src_register *tgsi_fsrc,
840 int src_idx)
841 {
842 nir_builder *b = &c->build;
843 struct tgsi_src_register *tgsi_src = &tgsi_fsrc->Register;
844 enum tgsi_opcode opcode = c->token->FullInstruction.Instruction.Opcode;
845 unsigned tgsi_src_type = tgsi_opcode_infer_src_type(opcode, src_idx);
846 bool src_is_float = (tgsi_src_type == TGSI_TYPE_FLOAT ||
847 tgsi_src_type == TGSI_TYPE_DOUBLE ||
848 tgsi_src_type == TGSI_TYPE_UNTYPED);
849 nir_alu_src src;
850
851 memset(&src, 0, sizeof(src));
852
853 if (tgsi_src->File == TGSI_FILE_NULL) {
854 return nir_imm_float(b, 0.0);
855 } else if (tgsi_src->File == TGSI_FILE_SAMPLER ||
856 tgsi_src->File == TGSI_FILE_IMAGE ||
857 tgsi_src->File == TGSI_FILE_BUFFER) {
858 /* Only the index of the resource gets used in texturing, and it will
859 * handle looking that up on its own instead of using the nir_alu_src.
860 */
861 assert(!tgsi_src->Indirect);
862 return NULL;
863 } else {
864 struct tgsi_ind_register *ind = NULL;
865 struct tgsi_dimension *dim = NULL;
866 struct tgsi_ind_register *dimind = NULL;
867 if (tgsi_src->Indirect)
868 ind = &tgsi_fsrc->Indirect;
869 if (tgsi_src->Dimension) {
870 dim = &tgsi_fsrc->Dimension;
871 if (dim->Indirect)
872 dimind = &tgsi_fsrc->DimIndirect;
873 }
874 src.src = ttn_src_for_file_and_index(c,
875 tgsi_src->File,
876 tgsi_src->Index,
877 ind, dim, dimind,
878 src_is_float);
879 }
880
881 src.swizzle[0] = tgsi_src->SwizzleX;
882 src.swizzle[1] = tgsi_src->SwizzleY;
883 src.swizzle[2] = tgsi_src->SwizzleZ;
884 src.swizzle[3] = tgsi_src->SwizzleW;
885
886 nir_ssa_def *def = nir_mov_alu(b, src, 4);
887
888 if (tgsi_type_is_64bit(tgsi_src_type))
889 def = nir_bitcast_vector(b, def, 64);
890
891 if (tgsi_src->Absolute) {
892 if (src_is_float)
893 def = nir_fabs(b, def);
894 else
895 def = nir_iabs(b, def);
896 }
897
898 if (tgsi_src->Negate) {
899 if (src_is_float)
900 def = nir_fneg(b, def);
901 else
902 def = nir_ineg(b, def);
903 }
904
905 return def;
906 }
907
908 static void
909 ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
910 nir_ssa_def *def, unsigned write_mask)
911 {
912 if (!(dest.write_mask & write_mask))
913 return;
914
915 nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
916 mov->dest = dest;
917 mov->dest.write_mask &= write_mask;
918 mov->src[0].src = nir_src_for_ssa(def);
919 for (unsigned i = def->num_components; i < 4; i++)
920 mov->src[0].swizzle[i] = def->num_components - 1;
921 nir_builder_instr_insert(b, &mov->instr);
922 }
923
924 static void
925 ttn_move_dest(nir_builder *b, nir_alu_dest dest, nir_ssa_def *def)
926 {
927 ttn_move_dest_masked(b, dest, def, TGSI_WRITEMASK_XYZW);
928 }
929
930 static void
931 ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, unsigned dest_bitsize,
932 nir_ssa_def **src)
933 {
934 nir_ssa_def *def = nir_build_alu_src_arr(b, op, src);
935 if (def->bit_size == 1)
936 def = nir_ineg(b, nir_b2i(b, def, dest_bitsize));
937 assert(def->bit_size == dest_bitsize);
938 if (dest_bitsize == 64) {
939 if (def->num_components > 2) {
940 /* 32 -> 64 bit conversion ops are supposed to only convert the first
941 * two components, and we need to truncate here to avoid creating a
942 * vec8 after bitcasting the destination.
943 */
944 def = nir_channels(b, def, 0x3);
945 }
946 def = nir_bitcast_vector(b, def, 32);
947 }
948 ttn_move_dest(b, dest, def);
949 }
950
951 static void
952 ttn_arl(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
953 {
954 ttn_move_dest(b, dest, nir_f2i32(b, nir_ffloor(b, src[0])));
955 }
956
957 /* EXP - Approximate Exponential Base 2
958 * dst.x = 2^{\lfloor src.x\rfloor}
959 * dst.y = src.x - \lfloor src.x\rfloor
960 * dst.z = 2^{src.x}
961 * dst.w = 1.0
962 */
963 static void
964 ttn_exp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
965 {
966 nir_ssa_def *srcx = ttn_channel(b, src[0], X);
967
968 ttn_move_dest_masked(b, dest, nir_fexp2(b, nir_ffloor(b, srcx)),
969 TGSI_WRITEMASK_X);
970 ttn_move_dest_masked(b, dest, nir_fsub(b, srcx, nir_ffloor(b, srcx)),
971 TGSI_WRITEMASK_Y);
972 ttn_move_dest_masked(b, dest, nir_fexp2(b, srcx), TGSI_WRITEMASK_Z);
973 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
974 }
975
976 /* LOG - Approximate Logarithm Base 2
977 * dst.x = \lfloor\log_2{|src.x|}\rfloor
978 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
979 * dst.z = \log_2{|src.x|}
980 * dst.w = 1.0
981 */
982 static void
983 ttn_log(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
984 {
985 nir_ssa_def *abs_srcx = nir_fabs(b, ttn_channel(b, src[0], X));
986 nir_ssa_def *log2 = nir_flog2(b, abs_srcx);
987
988 ttn_move_dest_masked(b, dest, nir_ffloor(b, log2), TGSI_WRITEMASK_X);
989 ttn_move_dest_masked(b, dest,
990 nir_fdiv(b, abs_srcx, nir_fexp2(b, nir_ffloor(b, log2))),
991 TGSI_WRITEMASK_Y);
992 ttn_move_dest_masked(b, dest, nir_flog2(b, abs_srcx), TGSI_WRITEMASK_Z);
993 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
994 }
995
996 /* DST - Distance Vector
997 * dst.x = 1.0
998 * dst.y = src0.y \times src1.y
999 * dst.z = src0.z
1000 * dst.w = src1.w
1001 */
1002 static void
1003 ttn_dst(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1004 {
1005 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_X);
1006 ttn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), TGSI_WRITEMASK_Y);
1007 ttn_move_dest_masked(b, dest, nir_mov(b, src[0]), TGSI_WRITEMASK_Z);
1008 ttn_move_dest_masked(b, dest, nir_mov(b, src[1]), TGSI_WRITEMASK_W);
1009 }
1010
1011 /* LIT - Light Coefficients
1012 * dst.x = 1.0
1013 * dst.y = max(src.x, 0.0)
1014 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
1015 * dst.w = 1.0
1016 */
1017 static void
1018 ttn_lit(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1019 {
1020 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_XW);
1021
1022 ttn_move_dest_masked(b, dest, nir_fmax(b, ttn_channel(b, src[0], X),
1023 nir_imm_float(b, 0.0)), TGSI_WRITEMASK_Y);
1024
1025 if (dest.write_mask & TGSI_WRITEMASK_Z) {
1026 nir_ssa_def *src0_y = ttn_channel(b, src[0], Y);
1027 nir_ssa_def *wclamp = nir_fmax(b, nir_fmin(b, ttn_channel(b, src[0], W),
1028 nir_imm_float(b, 128.0)),
1029 nir_imm_float(b, -128.0));
1030 nir_ssa_def *pow = nir_fpow(b, nir_fmax(b, src0_y, nir_imm_float(b, 0.0)),
1031 wclamp);
1032
1033 ttn_move_dest_masked(b, dest,
1034 nir_bcsel(b,
1035 nir_flt(b,
1036 ttn_channel(b, src[0], X),
1037 nir_imm_float(b, 0.0)),
1038 nir_imm_float(b, 0.0),
1039 pow),
1040 TGSI_WRITEMASK_Z);
1041 }
1042 }
1043
1044 static void
1045 ttn_sle(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1046 {
1047 ttn_move_dest(b, dest, nir_sge(b, src[1], src[0]));
1048 }
1049
1050 static void
1051 ttn_sgt(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1052 {
1053 ttn_move_dest(b, dest, nir_slt(b, src[1], src[0]));
1054 }
1055
1056 static void
1057 ttn_dp2(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1058 {
1059 ttn_move_dest(b, dest, nir_fdot2(b, src[0], src[1]));
1060 }
1061
1062 static void
1063 ttn_dp3(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1064 {
1065 ttn_move_dest(b, dest, nir_fdot3(b, src[0], src[1]));
1066 }
1067
1068 static void
1069 ttn_dp4(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1070 {
1071 ttn_move_dest(b, dest, nir_fdot4(b, src[0], src[1]));
1072 }
1073
1074 static void
1075 ttn_umad(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1076 {
1077 ttn_move_dest(b, dest, nir_iadd(b, nir_imul(b, src[0], src[1]), src[2]));
1078 }
1079
1080 static void
1081 ttn_arr(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1082 {
1083 ttn_move_dest(b, dest, nir_f2i32(b, nir_fround_even(b, src[0])));
1084 }
1085
1086 static void
1087 ttn_cmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1088 {
1089 ttn_move_dest(b, dest, nir_bcsel(b,
1090 nir_flt(b, src[0], nir_imm_float(b, 0.0)),
1091 src[1], src[2]));
1092 }
1093
1094 static void
1095 ttn_ucmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1096 {
1097 ttn_move_dest(b, dest, nir_bcsel(b,
1098 nir_ine(b, src[0], nir_imm_int(b, 0)),
1099 src[1], src[2]));
1100 }
1101
1102 static void
1103 ttn_kill(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1104 {
1105 nir_intrinsic_instr *discard =
1106 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard);
1107 nir_builder_instr_insert(b, &discard->instr);
1108 b->shader->info.fs.uses_discard = true;
1109 }
1110
1111 static void
1112 ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1113 {
1114 nir_ssa_def *cmp = nir_bany(b, nir_flt(b, src[0], nir_imm_float(b, 0.0)));
1115 nir_intrinsic_instr *discard =
1116 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard_if);
1117 discard->src[0] = nir_src_for_ssa(cmp);
1118 nir_builder_instr_insert(b, &discard->instr);
1119 b->shader->info.fs.uses_discard = true;
1120 }
1121
1122 static void
1123 ttn_if(struct ttn_compile *c, nir_ssa_def *src, bool is_uint)
1124 {
1125 nir_builder *b = &c->build;
1126 nir_ssa_def *src_x = ttn_channel(b, src, X);
1127
1128 nir_if *if_stmt = nir_if_create(b->shader);
1129 if (is_uint) {
1130 /* equivalent to TGSI UIF, src is interpreted as integer */
1131 if_stmt->condition = nir_src_for_ssa(nir_ine(b, src_x, nir_imm_int(b, 0)));
1132 } else {
1133 /* equivalent to TGSI IF, src is interpreted as float */
1134 if_stmt->condition = nir_src_for_ssa(nir_fne(b, src_x, nir_imm_float(b, 0.0)));
1135 }
1136 nir_builder_cf_insert(b, &if_stmt->cf_node);
1137
1138 c->if_stack[c->if_stack_pos] = nir_after_cf_node(&if_stmt->cf_node);
1139 c->if_stack_pos++;
1140
1141 b->cursor = nir_after_cf_list(&if_stmt->then_list);
1142
1143 c->if_stack[c->if_stack_pos] = nir_after_cf_list(&if_stmt->else_list);
1144 c->if_stack_pos++;
1145 }
1146
1147 static void
1148 ttn_else(struct ttn_compile *c)
1149 {
1150 nir_builder *b = &c->build;
1151
1152 b->cursor = c->if_stack[c->if_stack_pos - 1];
1153 }
1154
1155 static void
1156 ttn_endif(struct ttn_compile *c)
1157 {
1158 nir_builder *b = &c->build;
1159
1160 c->if_stack_pos -= 2;
1161 b->cursor = c->if_stack[c->if_stack_pos];
1162 }
1163
1164 static void
1165 ttn_bgnloop(struct ttn_compile *c)
1166 {
1167 nir_builder *b = &c->build;
1168
1169 nir_loop *loop = nir_loop_create(b->shader);
1170 nir_builder_cf_insert(b, &loop->cf_node);
1171
1172 c->loop_stack[c->loop_stack_pos] = nir_after_cf_node(&loop->cf_node);
1173 c->loop_stack_pos++;
1174
1175 b->cursor = nir_after_cf_list(&loop->body);
1176 }
1177
1178 static void
1179 ttn_cont(nir_builder *b)
1180 {
1181 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_continue);
1182 nir_builder_instr_insert(b, &instr->instr);
1183 }
1184
1185 static void
1186 ttn_brk(nir_builder *b)
1187 {
1188 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
1189 nir_builder_instr_insert(b, &instr->instr);
1190 }
1191
1192 static void
1193 ttn_endloop(struct ttn_compile *c)
1194 {
1195 nir_builder *b = &c->build;
1196
1197 c->loop_stack_pos--;
1198 b->cursor = c->loop_stack[c->loop_stack_pos];
1199 }
1200
1201 static void
1202 get_texture_info(unsigned texture,
1203 enum glsl_sampler_dim *dim,
1204 bool *is_shadow,
1205 bool *is_array)
1206 {
1207 assert(is_array);
1208 *is_array = false;
1209
1210 if (is_shadow)
1211 *is_shadow = false;
1212
1213 switch (texture) {
1214 case TGSI_TEXTURE_BUFFER:
1215 *dim = GLSL_SAMPLER_DIM_BUF;
1216 break;
1217 case TGSI_TEXTURE_1D:
1218 *dim = GLSL_SAMPLER_DIM_1D;
1219 break;
1220 case TGSI_TEXTURE_1D_ARRAY:
1221 *dim = GLSL_SAMPLER_DIM_1D;
1222 *is_array = true;
1223 break;
1224 case TGSI_TEXTURE_SHADOW1D:
1225 *dim = GLSL_SAMPLER_DIM_1D;
1226 *is_shadow = true;
1227 break;
1228 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1229 *dim = GLSL_SAMPLER_DIM_1D;
1230 *is_shadow = true;
1231 *is_array = true;
1232 break;
1233 case TGSI_TEXTURE_2D:
1234 *dim = GLSL_SAMPLER_DIM_2D;
1235 break;
1236 case TGSI_TEXTURE_2D_ARRAY:
1237 *dim = GLSL_SAMPLER_DIM_2D;
1238 *is_array = true;
1239 break;
1240 case TGSI_TEXTURE_2D_MSAA:
1241 *dim = GLSL_SAMPLER_DIM_MS;
1242 break;
1243 case TGSI_TEXTURE_2D_ARRAY_MSAA:
1244 *dim = GLSL_SAMPLER_DIM_MS;
1245 *is_array = true;
1246 break;
1247 case TGSI_TEXTURE_SHADOW2D:
1248 *dim = GLSL_SAMPLER_DIM_2D;
1249 *is_shadow = true;
1250 break;
1251 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1252 *dim = GLSL_SAMPLER_DIM_2D;
1253 *is_shadow = true;
1254 *is_array = true;
1255 break;
1256 case TGSI_TEXTURE_3D:
1257 *dim = GLSL_SAMPLER_DIM_3D;
1258 break;
1259 case TGSI_TEXTURE_CUBE:
1260 *dim = GLSL_SAMPLER_DIM_CUBE;
1261 break;
1262 case TGSI_TEXTURE_CUBE_ARRAY:
1263 *dim = GLSL_SAMPLER_DIM_CUBE;
1264 *is_array = true;
1265 break;
1266 case TGSI_TEXTURE_SHADOWCUBE:
1267 *dim = GLSL_SAMPLER_DIM_CUBE;
1268 *is_shadow = true;
1269 break;
1270 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1271 *dim = GLSL_SAMPLER_DIM_CUBE;
1272 *is_shadow = true;
1273 *is_array = true;
1274 break;
1275 case TGSI_TEXTURE_RECT:
1276 *dim = GLSL_SAMPLER_DIM_RECT;
1277 break;
1278 case TGSI_TEXTURE_SHADOWRECT:
1279 *dim = GLSL_SAMPLER_DIM_RECT;
1280 *is_shadow = true;
1281 break;
1282 default:
1283 fprintf(stderr, "Unknown TGSI texture target %d\n", texture);
1284 abort();
1285 }
1286 }
1287
1288 static enum glsl_base_type
1289 base_type_for_alu_type(nir_alu_type type)
1290 {
1291 type = nir_alu_type_get_base_type(type);
1292
1293 switch (type) {
1294 case nir_type_float:
1295 return GLSL_TYPE_FLOAT;
1296 case nir_type_int:
1297 return GLSL_TYPE_INT;
1298 case nir_type_uint:
1299 return GLSL_TYPE_UINT;
1300 default:
1301 unreachable("invalid type");
1302 }
1303 }
1304
1305 static nir_variable *
1306 get_sampler_var(struct ttn_compile *c, int binding,
1307 enum glsl_sampler_dim dim,
1308 bool is_shadow,
1309 bool is_array,
1310 enum glsl_base_type base_type)
1311 {
1312 nir_variable *var = c->samplers[binding];
1313 if (!var) {
1314 const struct glsl_type *type =
1315 glsl_sampler_type(dim, is_shadow, is_array, base_type);
1316 var = nir_variable_create(c->build.shader, nir_var_uniform, type,
1317 "sampler");
1318 var->data.binding = binding;
1319 var->data.explicit_binding = true;
1320 c->samplers[binding] = var;
1321 }
1322
1323 return var;
1324 }
1325
1326 static nir_variable *
1327 get_image_var(struct ttn_compile *c, int binding,
1328 enum glsl_sampler_dim dim,
1329 bool is_array,
1330 enum glsl_base_type base_type,
1331 enum gl_access_qualifier access,
1332 GLenum format)
1333 {
1334 nir_variable *var = c->images[binding];
1335
1336 if (!var) {
1337 const struct glsl_type *type = glsl_image_type(dim, is_array, base_type);
1338
1339 var = nir_variable_create(c->build.shader, nir_var_uniform, type, "image");
1340 var->data.binding = binding;
1341 var->data.explicit_binding = true;
1342 var->data.image.access = access;
1343 var->data.image.format = format;
1344 c->images[binding] = var;
1345 }
1346
1347 return var;
1348 }
1349
1350 static void
1351 add_ssbo_var(struct ttn_compile *c, int binding)
1352 {
1353 nir_variable *var = c->ssbo[binding];
1354
1355 if (!var) {
1356 /* A length of 0 is used to denote unsized arrays */
1357 const struct glsl_type *type = glsl_array_type(glsl_uint_type(), 0, 0);
1358
1359 struct glsl_struct_field field = {
1360 .type = type,
1361 .name = "data",
1362 .location = -1,
1363 };
1364
1365 var = nir_variable_create(c->build.shader, nir_var_mem_ssbo, type, "ssbo");
1366 var->data.binding = binding;
1367 var->interface_type =
1368 glsl_interface_type(&field, 1, GLSL_INTERFACE_PACKING_STD430,
1369 false, "data");
1370 c->ssbo[binding] = var;
1371 }
1372 }
1373
1374 static void
1375 ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1376 {
1377 nir_builder *b = &c->build;
1378 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1379 nir_tex_instr *instr;
1380 nir_texop op;
1381 unsigned num_srcs, samp = 1, sview, i;
1382
1383 switch (tgsi_inst->Instruction.Opcode) {
1384 case TGSI_OPCODE_TEX:
1385 op = nir_texop_tex;
1386 num_srcs = 1;
1387 break;
1388 case TGSI_OPCODE_TEX2:
1389 op = nir_texop_tex;
1390 num_srcs = 1;
1391 samp = 2;
1392 break;
1393 case TGSI_OPCODE_TXP:
1394 op = nir_texop_tex;
1395 num_srcs = 2;
1396 break;
1397 case TGSI_OPCODE_TXB:
1398 op = nir_texop_txb;
1399 num_srcs = 2;
1400 break;
1401 case TGSI_OPCODE_TXB2:
1402 op = nir_texop_txb;
1403 num_srcs = 2;
1404 samp = 2;
1405 break;
1406 case TGSI_OPCODE_TXL:
1407 case TGSI_OPCODE_TEX_LZ:
1408 op = nir_texop_txl;
1409 num_srcs = 2;
1410 break;
1411 case TGSI_OPCODE_TXL2:
1412 op = nir_texop_txl;
1413 num_srcs = 2;
1414 samp = 2;
1415 break;
1416 case TGSI_OPCODE_TXF:
1417 case TGSI_OPCODE_TXF_LZ:
1418 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
1419 tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1420 op = nir_texop_txf_ms;
1421 } else {
1422 op = nir_texop_txf;
1423 }
1424 num_srcs = 2;
1425 break;
1426 case TGSI_OPCODE_TXD:
1427 op = nir_texop_txd;
1428 num_srcs = 3;
1429 samp = 3;
1430 break;
1431 case TGSI_OPCODE_LODQ:
1432 op = nir_texop_lod;
1433 num_srcs = 1;
1434 break;
1435
1436 default:
1437 fprintf(stderr, "unknown TGSI tex op %d\n", tgsi_inst->Instruction.Opcode);
1438 abort();
1439 }
1440
1441 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
1442 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1443 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
1444 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1445 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
1446 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
1447 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1448 num_srcs++;
1449 }
1450
1451 /* Deref sources */
1452 num_srcs += 2;
1453
1454 num_srcs += tgsi_inst->Texture.NumOffsets;
1455
1456 instr = nir_tex_instr_create(b->shader, num_srcs);
1457 instr->op = op;
1458
1459 get_texture_info(tgsi_inst->Texture.Texture,
1460 &instr->sampler_dim, &instr->is_shadow, &instr->is_array);
1461
1462 switch (instr->sampler_dim) {
1463 case GLSL_SAMPLER_DIM_1D:
1464 case GLSL_SAMPLER_DIM_BUF:
1465 instr->coord_components = 1;
1466 break;
1467 case GLSL_SAMPLER_DIM_2D:
1468 case GLSL_SAMPLER_DIM_RECT:
1469 case GLSL_SAMPLER_DIM_EXTERNAL:
1470 case GLSL_SAMPLER_DIM_MS:
1471 instr->coord_components = 2;
1472 break;
1473 case GLSL_SAMPLER_DIM_3D:
1474 case GLSL_SAMPLER_DIM_CUBE:
1475 instr->coord_components = 3;
1476 break;
1477 case GLSL_SAMPLER_DIM_SUBPASS:
1478 case GLSL_SAMPLER_DIM_SUBPASS_MS:
1479 unreachable("invalid sampler_dim");
1480 }
1481
1482 if (instr->is_array)
1483 instr->coord_components++;
1484
1485 assert(tgsi_inst->Src[samp].Register.File == TGSI_FILE_SAMPLER);
1486
1487 /* TODO if we supported any opc's which take an explicit SVIEW
1488 * src, we would use that here instead. But for the "legacy"
1489 * texture opc's the SVIEW index is same as SAMP index:
1490 */
1491 sview = tgsi_inst->Src[samp].Register.Index;
1492
1493 if (op == nir_texop_lod) {
1494 instr->dest_type = nir_type_float;
1495 } else if (sview < c->num_samp_types) {
1496 instr->dest_type = c->samp_types[sview];
1497 } else {
1498 instr->dest_type = nir_type_float;
1499 }
1500
1501 nir_variable *var =
1502 get_sampler_var(c, sview, instr->sampler_dim,
1503 instr->is_shadow,
1504 instr->is_array,
1505 base_type_for_alu_type(instr->dest_type));
1506
1507 nir_deref_instr *deref = nir_build_deref_var(b, var);
1508
1509 unsigned src_number = 0;
1510
1511 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1512 instr->src[src_number].src_type = nir_tex_src_texture_deref;
1513 src_number++;
1514 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1515 instr->src[src_number].src_type = nir_tex_src_sampler_deref;
1516 src_number++;
1517
1518 instr->src[src_number].src =
1519 nir_src_for_ssa(nir_swizzle(b, src[0], SWIZ(X, Y, Z, W),
1520 instr->coord_components));
1521 instr->src[src_number].src_type = nir_tex_src_coord;
1522 src_number++;
1523
1524 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1525 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1526 instr->src[src_number].src_type = nir_tex_src_projector;
1527 src_number++;
1528 }
1529
1530 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
1531 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1532 instr->src[src_number].src_type = nir_tex_src_bias;
1533 src_number++;
1534 }
1535
1536 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB2) {
1537 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1538 instr->src[src_number].src_type = nir_tex_src_bias;
1539 src_number++;
1540 }
1541
1542 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
1543 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ) {
1544 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ)
1545 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1546 else
1547 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1548 instr->src[src_number].src_type = nir_tex_src_lod;
1549 src_number++;
1550 }
1551
1552 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
1553 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1554 instr->src[src_number].src_type = nir_tex_src_lod;
1555 src_number++;
1556 }
1557
1558 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF ||
1559 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ) {
1560 if (op == nir_texop_txf_ms) {
1561 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1562 instr->src[src_number].src_type = nir_tex_src_ms_index;
1563 } else {
1564 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ)
1565 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1566 else
1567 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1568 instr->src[src_number].src_type = nir_tex_src_lod;
1569 }
1570 src_number++;
1571 }
1572
1573 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
1574 instr->src[src_number].src_type = nir_tex_src_ddx;
1575 instr->src[src_number].src =
1576 nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1577 nir_tex_instr_src_size(instr, src_number)));
1578 src_number++;
1579 instr->src[src_number].src_type = nir_tex_src_ddy;
1580 instr->src[src_number].src =
1581 nir_src_for_ssa(nir_swizzle(b, src[2], SWIZ(X, Y, Z, W),
1582 nir_tex_instr_src_size(instr, src_number)));
1583 src_number++;
1584 }
1585
1586 if (instr->is_shadow) {
1587 if (instr->coord_components == 4)
1588 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1589 else if (instr->coord_components == 3)
1590 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1591 else
1592 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], Z));
1593
1594 instr->src[src_number].src_type = nir_tex_src_comparator;
1595 src_number++;
1596 }
1597
1598 for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) {
1599 struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i];
1600 /* since TexOffset ins't using tgsi_full_src_register we get to
1601 * do some extra gymnastics:
1602 */
1603 nir_alu_src src;
1604
1605 memset(&src, 0, sizeof(src));
1606
1607 src.src = ttn_src_for_file_and_index(c,
1608 tex_offset->File,
1609 tex_offset->Index,
1610 NULL, NULL, NULL,
1611 true);
1612
1613 src.swizzle[0] = tex_offset->SwizzleX;
1614 src.swizzle[1] = tex_offset->SwizzleY;
1615 src.swizzle[2] = tex_offset->SwizzleZ;
1616 src.swizzle[3] = TGSI_SWIZZLE_W;
1617
1618 instr->src[src_number].src_type = nir_tex_src_offset;
1619 instr->src[src_number].src = nir_src_for_ssa(
1620 nir_mov_alu(b, src, nir_tex_instr_src_size(instr, src_number)));
1621 src_number++;
1622 }
1623
1624 assert(src_number == num_srcs);
1625 assert(src_number == instr->num_srcs);
1626
1627 nir_ssa_dest_init(&instr->instr, &instr->dest,
1628 nir_tex_instr_dest_size(instr),
1629 32, NULL);
1630 nir_builder_instr_insert(b, &instr->instr);
1631
1632 /* Resolve the writemask on the texture op. */
1633 ttn_move_dest(b, dest, &instr->dest.ssa);
1634 }
1635
1636 /* TGSI_OPCODE_TXQ is actually two distinct operations:
1637 *
1638 * dst.x = texture\_width(unit, lod)
1639 * dst.y = texture\_height(unit, lod)
1640 * dst.z = texture\_depth(unit, lod)
1641 * dst.w = texture\_levels(unit)
1642 *
1643 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels
1644 */
1645 static void
1646 ttn_txq(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1647 {
1648 nir_builder *b = &c->build;
1649 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1650 nir_tex_instr *txs, *qlv;
1651
1652 txs = nir_tex_instr_create(b->shader, 2);
1653 txs->op = nir_texop_txs;
1654 get_texture_info(tgsi_inst->Texture.Texture,
1655 &txs->sampler_dim, &txs->is_shadow, &txs->is_array);
1656
1657 qlv = nir_tex_instr_create(b->shader, 1);
1658 qlv->op = nir_texop_query_levels;
1659 get_texture_info(tgsi_inst->Texture.Texture,
1660 &qlv->sampler_dim, &qlv->is_shadow, &qlv->is_array);
1661
1662 assert(tgsi_inst->Src[1].Register.File == TGSI_FILE_SAMPLER);
1663 int tex_index = tgsi_inst->Src[1].Register.Index;
1664
1665 nir_variable *var =
1666 get_sampler_var(c, tex_index, txs->sampler_dim,
1667 txs->is_shadow,
1668 txs->is_array,
1669 base_type_for_alu_type(txs->dest_type));
1670
1671 nir_deref_instr *deref = nir_build_deref_var(b, var);
1672
1673 txs->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1674 txs->src[0].src_type = nir_tex_src_texture_deref;
1675
1676 qlv->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1677 qlv->src[0].src_type = nir_tex_src_texture_deref;
1678
1679 /* lod: */
1680 txs->src[1].src = nir_src_for_ssa(ttn_channel(b, src[0], X));
1681 txs->src[1].src_type = nir_tex_src_lod;
1682
1683 nir_ssa_dest_init(&txs->instr, &txs->dest,
1684 nir_tex_instr_dest_size(txs), 32, NULL);
1685 nir_builder_instr_insert(b, &txs->instr);
1686
1687 nir_ssa_dest_init(&qlv->instr, &qlv->dest, 1, 32, NULL);
1688 nir_builder_instr_insert(b, &qlv->instr);
1689
1690 ttn_move_dest_masked(b, dest, &txs->dest.ssa, TGSI_WRITEMASK_XYZ);
1691 ttn_move_dest_masked(b, dest, &qlv->dest.ssa, TGSI_WRITEMASK_W);
1692 }
1693
1694 static enum glsl_base_type
1695 get_image_base_type(struct tgsi_full_instruction *tgsi_inst)
1696 {
1697 const struct util_format_description *desc =
1698 util_format_description(tgsi_inst->Memory.Format);
1699
1700 if (desc->channel[0].pure_integer) {
1701 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED)
1702 return GLSL_TYPE_INT;
1703 else
1704 return GLSL_TYPE_UINT;
1705 }
1706 return GLSL_TYPE_FLOAT;
1707 }
1708
1709 static enum gl_access_qualifier
1710 get_mem_qualifier(struct tgsi_full_instruction *tgsi_inst)
1711 {
1712 enum gl_access_qualifier access = 0;
1713
1714 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_COHERENT)
1715 access |= ACCESS_COHERENT;
1716 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT)
1717 access |= ACCESS_RESTRICT;
1718 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
1719 access |= ACCESS_VOLATILE;
1720 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
1721 access |= ACCESS_STREAM_CACHE_POLICY;
1722
1723 return access;
1724 }
1725
1726 static GLenum
1727 get_image_format(struct tgsi_full_instruction *tgsi_inst)
1728 {
1729 switch (tgsi_inst->Memory.Format) {
1730 case PIPE_FORMAT_R8_UNORM:
1731 return GL_R8;
1732 case PIPE_FORMAT_R8G8_UNORM:
1733 return GL_RG8;
1734 case PIPE_FORMAT_R8G8B8A8_UNORM:
1735 return GL_RGBA8;
1736 case PIPE_FORMAT_R16_UNORM:
1737 return GL_R16;
1738 case PIPE_FORMAT_R16G16_UNORM:
1739 return GL_RG16;
1740 case PIPE_FORMAT_R16G16B16A16_UNORM:
1741 return GL_RGBA16;
1742
1743 case PIPE_FORMAT_R8_SNORM:
1744 return GL_R8_SNORM;
1745 case PIPE_FORMAT_R8G8_SNORM:
1746 return GL_RG8_SNORM;
1747 case PIPE_FORMAT_R8G8B8A8_SNORM:
1748 return GL_RGBA8_SNORM;
1749 case PIPE_FORMAT_R16_SNORM:
1750 return GL_R16_SNORM;
1751 case PIPE_FORMAT_R16G16_SNORM:
1752 return GL_RG16_SNORM;
1753 case PIPE_FORMAT_R16G16B16A16_SNORM:
1754 return GL_RGBA16_SNORM;
1755
1756 case PIPE_FORMAT_R8_UINT:
1757 return GL_R8UI;
1758 case PIPE_FORMAT_R8G8_UINT:
1759 return GL_RG8UI;
1760 case PIPE_FORMAT_R8G8B8A8_UINT:
1761 return GL_RGBA8UI;
1762 case PIPE_FORMAT_R16_UINT:
1763 return GL_R16UI;
1764 case PIPE_FORMAT_R16G16_UINT:
1765 return GL_RG16UI;
1766 case PIPE_FORMAT_R16G16B16A16_UINT:
1767 return GL_RGBA16UI;
1768 case PIPE_FORMAT_R32_UINT:
1769 return GL_R32UI;
1770 case PIPE_FORMAT_R32G32_UINT:
1771 return GL_RG32UI;
1772 case PIPE_FORMAT_R32G32B32A32_UINT:
1773 return GL_RGBA32UI;
1774
1775 case PIPE_FORMAT_R8_SINT:
1776 return GL_R8I;
1777 case PIPE_FORMAT_R8G8_SINT:
1778 return GL_RG8I;
1779 case PIPE_FORMAT_R8G8B8A8_SINT:
1780 return GL_RGBA8I;
1781 case PIPE_FORMAT_R16_SINT:
1782 return GL_R16I;
1783 case PIPE_FORMAT_R16G16_SINT:
1784 return GL_RG16I;
1785 case PIPE_FORMAT_R16G16B16A16_SINT:
1786 return GL_RGBA16I;
1787 case PIPE_FORMAT_R32_SINT:
1788 return GL_R32I;
1789 case PIPE_FORMAT_R32G32_SINT:
1790 return GL_RG32I;
1791 case PIPE_FORMAT_R32G32B32A32_SINT:
1792 return GL_RGBA32I;
1793
1794 case PIPE_FORMAT_R16_FLOAT:
1795 return GL_R16F;
1796 case PIPE_FORMAT_R16G16_FLOAT:
1797 return GL_RG16F;
1798 case PIPE_FORMAT_R16G16B16A16_FLOAT:
1799 return GL_RGBA16F;
1800 case PIPE_FORMAT_R32_FLOAT:
1801 return GL_R32F;
1802 case PIPE_FORMAT_R32G32_FLOAT:
1803 return GL_RG32F;
1804 case PIPE_FORMAT_R32G32B32A32_FLOAT:
1805 return GL_RGBA32F;
1806
1807 case PIPE_FORMAT_R11G11B10_FLOAT:
1808 return GL_R11F_G11F_B10F;
1809 case PIPE_FORMAT_R10G10B10A2_UINT:
1810 return GL_RGB10_A2UI;
1811 case PIPE_FORMAT_R10G10B10A2_UNORM:
1812 return GL_RGB10_A2;
1813
1814 default:
1815 unreachable("unhandled image format");
1816 }
1817 }
1818
1819 static void
1820 ttn_mem(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1821 {
1822 nir_builder *b = &c->build;
1823 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1824 nir_intrinsic_instr *instr = NULL;
1825 unsigned resource_index, addr_src_index, file;
1826
1827 switch (tgsi_inst->Instruction.Opcode) {
1828 case TGSI_OPCODE_LOAD:
1829 assert(!tgsi_inst->Src[0].Register.Indirect);
1830 resource_index = tgsi_inst->Src[0].Register.Index;
1831 file = tgsi_inst->Src[0].Register.File;
1832 addr_src_index = 1;
1833 break;
1834 case TGSI_OPCODE_STORE:
1835 assert(!tgsi_inst->Dst[0].Register.Indirect);
1836 resource_index = tgsi_inst->Dst[0].Register.Index;
1837 file = tgsi_inst->Dst[0].Register.File;
1838 addr_src_index = 0;
1839 break;
1840 default:
1841 unreachable("unexpected memory opcode");
1842 }
1843
1844 if (file == TGSI_FILE_BUFFER) {
1845 nir_intrinsic_op op;
1846
1847 switch (tgsi_inst->Instruction.Opcode) {
1848 case TGSI_OPCODE_LOAD:
1849 op = nir_intrinsic_load_ssbo;
1850 break;
1851 case TGSI_OPCODE_STORE:
1852 op = nir_intrinsic_store_ssbo;
1853 break;
1854 }
1855
1856 add_ssbo_var(c, resource_index);
1857
1858 instr = nir_intrinsic_instr_create(b->shader, op);
1859 instr->num_components = util_last_bit(tgsi_inst->Dst[0].Register.WriteMask);
1860 nir_intrinsic_set_access(instr, get_mem_qualifier(tgsi_inst));
1861 nir_intrinsic_set_align(instr, 4, 0);
1862
1863 unsigned i = 0;
1864 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1865 instr->src[i++] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1866 instr->num_components));
1867 instr->src[i++] = nir_src_for_ssa(nir_imm_int(b, resource_index));
1868 instr->src[i++] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], X));
1869
1870 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1871 nir_intrinsic_set_write_mask(instr, tgsi_inst->Dst[0].Register.WriteMask);
1872
1873 } else if (file == TGSI_FILE_IMAGE) {
1874 nir_intrinsic_op op;
1875
1876 switch (tgsi_inst->Instruction.Opcode) {
1877 case TGSI_OPCODE_LOAD:
1878 op = nir_intrinsic_image_deref_load;
1879 break;
1880 case TGSI_OPCODE_STORE:
1881 op = nir_intrinsic_image_deref_store;
1882 break;
1883 }
1884
1885 instr = nir_intrinsic_instr_create(b->shader, op);
1886
1887 /* Set the image variable dereference. */
1888 enum glsl_sampler_dim dim;
1889 bool is_array;
1890 get_texture_info(tgsi_inst->Memory.Texture, &dim, NULL, &is_array);
1891
1892 enum glsl_base_type base_type = get_image_base_type(tgsi_inst);
1893 enum gl_access_qualifier access = get_mem_qualifier(tgsi_inst);
1894 GLenum format = get_image_format(tgsi_inst);
1895
1896 nir_variable *image =
1897 get_image_var(c, resource_index,
1898 dim, is_array, base_type, access, format);
1899 nir_deref_instr *image_deref = nir_build_deref_var(b, image);
1900 const struct glsl_type *type = image_deref->type;
1901
1902 nir_intrinsic_set_access(instr, image_deref->var->data.image.access);
1903
1904 instr->src[0] = nir_src_for_ssa(&image_deref->dest.ssa);
1905 instr->src[1] = nir_src_for_ssa(src[addr_src_index]);
1906
1907 /* Set the sample argument, which is undefined for single-sample images. */
1908 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_MS) {
1909 instr->src[2] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], W));
1910 } else {
1911 instr->src[2] = nir_src_for_ssa(nir_ssa_undef(b, 1, 32));
1912 }
1913
1914 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
1915 instr->src[3] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W), 4));
1916 }
1917
1918 instr->num_components = 4;
1919 } else {
1920 unreachable("unexpected file");
1921 }
1922
1923
1924 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_LOAD) {
1925 nir_ssa_dest_init(&instr->instr, &instr->dest,
1926 util_last_bit(tgsi_inst->Dst[0].Register.WriteMask),
1927 32, NULL);
1928 nir_builder_instr_insert(b, &instr->instr);
1929 ttn_move_dest(b, dest, &instr->dest.ssa);
1930 } else {
1931 nir_builder_instr_insert(b, &instr->instr);
1932 }
1933 }
1934
1935 static const nir_op op_trans[TGSI_OPCODE_LAST] = {
1936 [TGSI_OPCODE_ARL] = 0,
1937 [TGSI_OPCODE_MOV] = nir_op_mov,
1938 [TGSI_OPCODE_LIT] = 0,
1939 [TGSI_OPCODE_RCP] = nir_op_frcp,
1940 [TGSI_OPCODE_RSQ] = nir_op_frsq,
1941 [TGSI_OPCODE_EXP] = 0,
1942 [TGSI_OPCODE_LOG] = 0,
1943 [TGSI_OPCODE_MUL] = nir_op_fmul,
1944 [TGSI_OPCODE_ADD] = nir_op_fadd,
1945 [TGSI_OPCODE_DP3] = 0,
1946 [TGSI_OPCODE_DP4] = 0,
1947 [TGSI_OPCODE_DST] = 0,
1948 [TGSI_OPCODE_MIN] = nir_op_fmin,
1949 [TGSI_OPCODE_MAX] = nir_op_fmax,
1950 [TGSI_OPCODE_SLT] = nir_op_slt,
1951 [TGSI_OPCODE_SGE] = nir_op_sge,
1952 [TGSI_OPCODE_MAD] = nir_op_ffma,
1953 [TGSI_OPCODE_TEX_LZ] = 0,
1954 [TGSI_OPCODE_LRP] = 0,
1955 [TGSI_OPCODE_SQRT] = nir_op_fsqrt,
1956 [TGSI_OPCODE_FRC] = nir_op_ffract,
1957 [TGSI_OPCODE_TXF_LZ] = 0,
1958 [TGSI_OPCODE_FLR] = nir_op_ffloor,
1959 [TGSI_OPCODE_ROUND] = nir_op_fround_even,
1960 [TGSI_OPCODE_EX2] = nir_op_fexp2,
1961 [TGSI_OPCODE_LG2] = nir_op_flog2,
1962 [TGSI_OPCODE_POW] = nir_op_fpow,
1963 [TGSI_OPCODE_COS] = nir_op_fcos,
1964 [TGSI_OPCODE_DDX] = nir_op_fddx,
1965 [TGSI_OPCODE_DDY] = nir_op_fddy,
1966 [TGSI_OPCODE_KILL] = 0,
1967 [TGSI_OPCODE_PK2H] = 0, /* XXX */
1968 [TGSI_OPCODE_PK2US] = 0, /* XXX */
1969 [TGSI_OPCODE_PK4B] = 0, /* XXX */
1970 [TGSI_OPCODE_PK4UB] = 0, /* XXX */
1971 [TGSI_OPCODE_SEQ] = nir_op_seq,
1972 [TGSI_OPCODE_SGT] = 0,
1973 [TGSI_OPCODE_SIN] = nir_op_fsin,
1974 [TGSI_OPCODE_SNE] = nir_op_sne,
1975 [TGSI_OPCODE_SLE] = 0,
1976 [TGSI_OPCODE_TEX] = 0,
1977 [TGSI_OPCODE_TXD] = 0,
1978 [TGSI_OPCODE_TXP] = 0,
1979 [TGSI_OPCODE_UP2H] = 0, /* XXX */
1980 [TGSI_OPCODE_UP2US] = 0, /* XXX */
1981 [TGSI_OPCODE_UP4B] = 0, /* XXX */
1982 [TGSI_OPCODE_UP4UB] = 0, /* XXX */
1983 [TGSI_OPCODE_ARR] = 0,
1984
1985 /* No function calls, yet. */
1986 [TGSI_OPCODE_CAL] = 0, /* XXX */
1987 [TGSI_OPCODE_RET] = 0, /* XXX */
1988
1989 [TGSI_OPCODE_SSG] = nir_op_fsign,
1990 [TGSI_OPCODE_CMP] = 0,
1991 [TGSI_OPCODE_TXB] = 0,
1992 [TGSI_OPCODE_DIV] = nir_op_fdiv,
1993 [TGSI_OPCODE_DP2] = 0,
1994 [TGSI_OPCODE_TXL] = 0,
1995
1996 [TGSI_OPCODE_BRK] = 0,
1997 [TGSI_OPCODE_IF] = 0,
1998 [TGSI_OPCODE_UIF] = 0,
1999 [TGSI_OPCODE_ELSE] = 0,
2000 [TGSI_OPCODE_ENDIF] = 0,
2001
2002 [TGSI_OPCODE_DDX_FINE] = nir_op_fddx_fine,
2003 [TGSI_OPCODE_DDY_FINE] = nir_op_fddy_fine,
2004
2005 [TGSI_OPCODE_CEIL] = nir_op_fceil,
2006 [TGSI_OPCODE_I2F] = nir_op_i2f32,
2007 [TGSI_OPCODE_NOT] = nir_op_inot,
2008 [TGSI_OPCODE_TRUNC] = nir_op_ftrunc,
2009 [TGSI_OPCODE_SHL] = nir_op_ishl,
2010 [TGSI_OPCODE_AND] = nir_op_iand,
2011 [TGSI_OPCODE_OR] = nir_op_ior,
2012 [TGSI_OPCODE_MOD] = nir_op_umod,
2013 [TGSI_OPCODE_XOR] = nir_op_ixor,
2014 [TGSI_OPCODE_TXF] = 0,
2015 [TGSI_OPCODE_TXQ] = 0,
2016
2017 [TGSI_OPCODE_CONT] = 0,
2018
2019 [TGSI_OPCODE_EMIT] = 0, /* XXX */
2020 [TGSI_OPCODE_ENDPRIM] = 0, /* XXX */
2021
2022 [TGSI_OPCODE_BGNLOOP] = 0,
2023 [TGSI_OPCODE_BGNSUB] = 0, /* XXX: no function calls */
2024 [TGSI_OPCODE_ENDLOOP] = 0,
2025 [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */
2026
2027 [TGSI_OPCODE_NOP] = 0,
2028 [TGSI_OPCODE_FSEQ] = nir_op_feq,
2029 [TGSI_OPCODE_FSGE] = nir_op_fge,
2030 [TGSI_OPCODE_FSLT] = nir_op_flt,
2031 [TGSI_OPCODE_FSNE] = nir_op_fne,
2032
2033 [TGSI_OPCODE_KILL_IF] = 0,
2034
2035 [TGSI_OPCODE_END] = 0,
2036
2037 [TGSI_OPCODE_F2I] = nir_op_f2i32,
2038 [TGSI_OPCODE_IDIV] = nir_op_idiv,
2039 [TGSI_OPCODE_IMAX] = nir_op_imax,
2040 [TGSI_OPCODE_IMIN] = nir_op_imin,
2041 [TGSI_OPCODE_INEG] = nir_op_ineg,
2042 [TGSI_OPCODE_ISGE] = nir_op_ige,
2043 [TGSI_OPCODE_ISHR] = nir_op_ishr,
2044 [TGSI_OPCODE_ISLT] = nir_op_ilt,
2045 [TGSI_OPCODE_F2U] = nir_op_f2u32,
2046 [TGSI_OPCODE_U2F] = nir_op_u2f32,
2047 [TGSI_OPCODE_UADD] = nir_op_iadd,
2048 [TGSI_OPCODE_UDIV] = nir_op_udiv,
2049 [TGSI_OPCODE_UMAD] = 0,
2050 [TGSI_OPCODE_UMAX] = nir_op_umax,
2051 [TGSI_OPCODE_UMIN] = nir_op_umin,
2052 [TGSI_OPCODE_UMOD] = nir_op_umod,
2053 [TGSI_OPCODE_UMUL] = nir_op_imul,
2054 [TGSI_OPCODE_USEQ] = nir_op_ieq,
2055 [TGSI_OPCODE_USGE] = nir_op_uge,
2056 [TGSI_OPCODE_USHR] = nir_op_ushr,
2057 [TGSI_OPCODE_USLT] = nir_op_ult,
2058 [TGSI_OPCODE_USNE] = nir_op_ine,
2059
2060 [TGSI_OPCODE_SWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
2061 [TGSI_OPCODE_CASE] = 0, /* not emitted by glsl_to_tgsi.cpp */
2062 [TGSI_OPCODE_DEFAULT] = 0, /* not emitted by glsl_to_tgsi.cpp */
2063 [TGSI_OPCODE_ENDSWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
2064
2065 /* XXX: SAMPLE opcodes */
2066
2067 [TGSI_OPCODE_UARL] = nir_op_mov,
2068 [TGSI_OPCODE_UCMP] = 0,
2069 [TGSI_OPCODE_IABS] = nir_op_iabs,
2070 [TGSI_OPCODE_ISSG] = nir_op_isign,
2071
2072 [TGSI_OPCODE_LOAD] = 0,
2073 [TGSI_OPCODE_STORE] = 0,
2074
2075 /* XXX: atomics */
2076
2077 [TGSI_OPCODE_TEX2] = 0,
2078 [TGSI_OPCODE_TXB2] = 0,
2079 [TGSI_OPCODE_TXL2] = 0,
2080
2081 [TGSI_OPCODE_IMUL_HI] = nir_op_imul_high,
2082 [TGSI_OPCODE_UMUL_HI] = nir_op_umul_high,
2083
2084 [TGSI_OPCODE_TG4] = 0,
2085 [TGSI_OPCODE_LODQ] = 0,
2086
2087 [TGSI_OPCODE_IBFE] = nir_op_ibitfield_extract,
2088 [TGSI_OPCODE_UBFE] = nir_op_ubitfield_extract,
2089 [TGSI_OPCODE_BFI] = nir_op_bitfield_insert,
2090 [TGSI_OPCODE_BREV] = nir_op_bitfield_reverse,
2091 [TGSI_OPCODE_POPC] = nir_op_bit_count,
2092 [TGSI_OPCODE_LSB] = nir_op_find_lsb,
2093 [TGSI_OPCODE_IMSB] = nir_op_ifind_msb,
2094 [TGSI_OPCODE_UMSB] = nir_op_ufind_msb,
2095
2096 [TGSI_OPCODE_INTERP_CENTROID] = 0, /* XXX */
2097 [TGSI_OPCODE_INTERP_SAMPLE] = 0, /* XXX */
2098 [TGSI_OPCODE_INTERP_OFFSET] = 0, /* XXX */
2099
2100 [TGSI_OPCODE_F2D] = nir_op_f2f64,
2101 [TGSI_OPCODE_D2F] = nir_op_f2f32,
2102 [TGSI_OPCODE_DMUL] = nir_op_fmul,
2103 [TGSI_OPCODE_D2U] = nir_op_f2u32,
2104 [TGSI_OPCODE_U2D] = nir_op_u2f64,
2105
2106 [TGSI_OPCODE_U64ADD] = nir_op_iadd,
2107 [TGSI_OPCODE_U64MUL] = nir_op_imul,
2108 [TGSI_OPCODE_U64DIV] = nir_op_udiv,
2109 [TGSI_OPCODE_U64SNE] = nir_op_ine,
2110 };
2111
2112 static void
2113 ttn_emit_instruction(struct ttn_compile *c)
2114 {
2115 nir_builder *b = &c->build;
2116 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
2117 unsigned i;
2118 unsigned tgsi_op = tgsi_inst->Instruction.Opcode;
2119 struct tgsi_full_dst_register *tgsi_dst = &tgsi_inst->Dst[0];
2120
2121 if (tgsi_op == TGSI_OPCODE_END)
2122 return;
2123
2124 nir_ssa_def *src[TGSI_FULL_MAX_SRC_REGISTERS];
2125 for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) {
2126 src[i] = ttn_get_src(c, &tgsi_inst->Src[i], i);
2127 }
2128 nir_alu_dest dest = ttn_get_dest(c, tgsi_dst);
2129
2130 unsigned tgsi_dst_type = tgsi_opcode_infer_dst_type(tgsi_op, 0);
2131
2132 /* The destination bitsize of the NIR opcode (not TGSI, where it's always
2133 * 32 bits). This needs to be passed into ttn_alu() because it can't be
2134 * inferred for comparison opcodes.
2135 */
2136 unsigned dst_bitsize = tgsi_type_is_64bit(tgsi_dst_type) ? 64 : 32;
2137
2138 switch (tgsi_op) {
2139 case TGSI_OPCODE_RSQ:
2140 ttn_move_dest(b, dest, nir_frsq(b, ttn_channel(b, src[0], X)));
2141 break;
2142
2143 case TGSI_OPCODE_SQRT:
2144 ttn_move_dest(b, dest, nir_fsqrt(b, ttn_channel(b, src[0], X)));
2145 break;
2146
2147 case TGSI_OPCODE_RCP:
2148 ttn_move_dest(b, dest, nir_frcp(b, ttn_channel(b, src[0], X)));
2149 break;
2150
2151 case TGSI_OPCODE_EX2:
2152 ttn_move_dest(b, dest, nir_fexp2(b, ttn_channel(b, src[0], X)));
2153 break;
2154
2155 case TGSI_OPCODE_LG2:
2156 ttn_move_dest(b, dest, nir_flog2(b, ttn_channel(b, src[0], X)));
2157 break;
2158
2159 case TGSI_OPCODE_POW:
2160 ttn_move_dest(b, dest, nir_fpow(b,
2161 ttn_channel(b, src[0], X),
2162 ttn_channel(b, src[1], X)));
2163 break;
2164
2165 case TGSI_OPCODE_COS:
2166 ttn_move_dest(b, dest, nir_fcos(b, ttn_channel(b, src[0], X)));
2167 break;
2168
2169 case TGSI_OPCODE_SIN:
2170 ttn_move_dest(b, dest, nir_fsin(b, ttn_channel(b, src[0], X)));
2171 break;
2172
2173 case TGSI_OPCODE_ARL:
2174 ttn_arl(b, op_trans[tgsi_op], dest, src);
2175 break;
2176
2177 case TGSI_OPCODE_EXP:
2178 ttn_exp(b, op_trans[tgsi_op], dest, src);
2179 break;
2180
2181 case TGSI_OPCODE_LOG:
2182 ttn_log(b, op_trans[tgsi_op], dest, src);
2183 break;
2184
2185 case TGSI_OPCODE_DST:
2186 ttn_dst(b, op_trans[tgsi_op], dest, src);
2187 break;
2188
2189 case TGSI_OPCODE_LIT:
2190 ttn_lit(b, op_trans[tgsi_op], dest, src);
2191 break;
2192
2193 case TGSI_OPCODE_DP2:
2194 ttn_dp2(b, op_trans[tgsi_op], dest, src);
2195 break;
2196
2197 case TGSI_OPCODE_DP3:
2198 ttn_dp3(b, op_trans[tgsi_op], dest, src);
2199 break;
2200
2201 case TGSI_OPCODE_DP4:
2202 ttn_dp4(b, op_trans[tgsi_op], dest, src);
2203 break;
2204
2205 case TGSI_OPCODE_UMAD:
2206 ttn_umad(b, op_trans[tgsi_op], dest, src);
2207 break;
2208
2209 case TGSI_OPCODE_LRP:
2210 ttn_move_dest(b, dest, nir_flrp(b, src[2], src[1], src[0]));
2211 break;
2212
2213 case TGSI_OPCODE_KILL:
2214 ttn_kill(b, op_trans[tgsi_op], dest, src);
2215 break;
2216
2217 case TGSI_OPCODE_ARR:
2218 ttn_arr(b, op_trans[tgsi_op], dest, src);
2219 break;
2220
2221 case TGSI_OPCODE_CMP:
2222 ttn_cmp(b, op_trans[tgsi_op], dest, src);
2223 break;
2224
2225 case TGSI_OPCODE_UCMP:
2226 ttn_ucmp(b, op_trans[tgsi_op], dest, src);
2227 break;
2228
2229 case TGSI_OPCODE_SGT:
2230 ttn_sgt(b, op_trans[tgsi_op], dest, src);
2231 break;
2232
2233 case TGSI_OPCODE_SLE:
2234 ttn_sle(b, op_trans[tgsi_op], dest, src);
2235 break;
2236
2237 case TGSI_OPCODE_KILL_IF:
2238 ttn_kill_if(b, op_trans[tgsi_op], dest, src);
2239 break;
2240
2241 case TGSI_OPCODE_TEX:
2242 case TGSI_OPCODE_TEX_LZ:
2243 case TGSI_OPCODE_TXP:
2244 case TGSI_OPCODE_TXL:
2245 case TGSI_OPCODE_TXB:
2246 case TGSI_OPCODE_TXD:
2247 case TGSI_OPCODE_TEX2:
2248 case TGSI_OPCODE_TXL2:
2249 case TGSI_OPCODE_TXB2:
2250 case TGSI_OPCODE_TXF:
2251 case TGSI_OPCODE_TXF_LZ:
2252 case TGSI_OPCODE_TG4:
2253 case TGSI_OPCODE_LODQ:
2254 ttn_tex(c, dest, src);
2255 break;
2256
2257 case TGSI_OPCODE_TXQ:
2258 ttn_txq(c, dest, src);
2259 break;
2260
2261 case TGSI_OPCODE_LOAD:
2262 case TGSI_OPCODE_STORE:
2263 ttn_mem(c, dest, src);
2264 break;
2265
2266 case TGSI_OPCODE_NOP:
2267 break;
2268
2269 case TGSI_OPCODE_IF:
2270 ttn_if(c, src[0], false);
2271 break;
2272
2273 case TGSI_OPCODE_UIF:
2274 ttn_if(c, src[0], true);
2275 break;
2276
2277 case TGSI_OPCODE_ELSE:
2278 ttn_else(c);
2279 break;
2280
2281 case TGSI_OPCODE_ENDIF:
2282 ttn_endif(c);
2283 break;
2284
2285 case TGSI_OPCODE_BGNLOOP:
2286 ttn_bgnloop(c);
2287 break;
2288
2289 case TGSI_OPCODE_BRK:
2290 ttn_brk(b);
2291 break;
2292
2293 case TGSI_OPCODE_CONT:
2294 ttn_cont(b);
2295 break;
2296
2297 case TGSI_OPCODE_ENDLOOP:
2298 ttn_endloop(c);
2299 break;
2300
2301 default:
2302 if (op_trans[tgsi_op] != 0 || tgsi_op == TGSI_OPCODE_MOV) {
2303 ttn_alu(b, op_trans[tgsi_op], dest, dst_bitsize, src);
2304 } else {
2305 fprintf(stderr, "unknown TGSI opcode: %s\n",
2306 tgsi_get_opcode_name(tgsi_op));
2307 abort();
2308 }
2309 break;
2310 }
2311
2312 if (tgsi_inst->Instruction.Saturate) {
2313 assert(!dest.dest.is_ssa);
2314 ttn_move_dest(b, dest, nir_fsat(b, ttn_src_for_dest(b, &dest)));
2315 }
2316
2317 /* if the dst has a matching var, append store_var to move
2318 * output from reg to var
2319 */
2320 nir_variable *var = ttn_get_var(c, tgsi_dst);
2321 if (var) {
2322 unsigned index = tgsi_dst->Register.Index;
2323 unsigned offset = c->temp_regs[index].offset;
2324 struct tgsi_ind_register *indirect = tgsi_dst->Register.Indirect ?
2325 &tgsi_dst->Indirect : NULL;
2326 nir_src val = nir_src_for_reg(dest.dest.reg.reg);
2327 nir_store_deref(b, ttn_array_deref(c, var, offset, indirect),
2328 nir_ssa_for_src(b, val, 4), dest.write_mask);
2329 }
2330 }
2331
2332 /**
2333 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
2334 * variables at the end of the shader.
2335 *
2336 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
2337 * written, because there's no output load intrinsic, which means we couldn't
2338 * handle writemasks.
2339 */
2340 static void
2341 ttn_add_output_stores(struct ttn_compile *c)
2342 {
2343 nir_builder *b = &c->build;
2344
2345 for (int i = 0; i < c->build.shader->num_outputs; i++) {
2346 nir_variable *var = c->outputs[i];
2347 if (!var)
2348 continue;
2349
2350 nir_src src = nir_src_for_reg(c->output_regs[i].reg);
2351 src.reg.base_offset = c->output_regs[i].offset;
2352
2353 nir_ssa_def *store_value = nir_ssa_for_src(b, src, 4);
2354 if (c->build.shader->info.stage == MESA_SHADER_FRAGMENT) {
2355 /* TGSI uses TGSI_SEMANTIC_POSITION.z for the depth output
2356 * and TGSI_SEMANTIC_STENCIL.y for the stencil output,
2357 * while NIR uses a single-component output.
2358 */
2359 if (var->data.location == FRAG_RESULT_DEPTH)
2360 store_value = nir_channel(b, store_value, 2);
2361 else if (var->data.location == FRAG_RESULT_STENCIL)
2362 store_value = nir_channel(b, store_value, 1);
2363 }
2364
2365 nir_store_deref(b, nir_build_deref_var(b, var), store_value,
2366 (1 << store_value->num_components) - 1);
2367 }
2368 }
2369
2370 /**
2371 * Parses the given TGSI tokens.
2372 */
2373 static void
2374 ttn_parse_tgsi(struct ttn_compile *c, const void *tgsi_tokens)
2375 {
2376 struct tgsi_parse_context parser;
2377 int ret;
2378
2379 ret = tgsi_parse_init(&parser, tgsi_tokens);
2380 assert(ret == TGSI_PARSE_OK);
2381
2382 while (!tgsi_parse_end_of_tokens(&parser)) {
2383 tgsi_parse_token(&parser);
2384 c->token = &parser.FullToken;
2385
2386 switch (parser.FullToken.Token.Type) {
2387 case TGSI_TOKEN_TYPE_DECLARATION:
2388 ttn_emit_declaration(c);
2389 break;
2390
2391 case TGSI_TOKEN_TYPE_INSTRUCTION:
2392 ttn_emit_instruction(c);
2393 break;
2394
2395 case TGSI_TOKEN_TYPE_IMMEDIATE:
2396 ttn_emit_immediate(c);
2397 break;
2398 }
2399 }
2400
2401 tgsi_parse_free(&parser);
2402 }
2403
2404 static void
2405 ttn_read_pipe_caps(struct ttn_compile *c,
2406 struct pipe_screen *screen)
2407 {
2408 c->cap_scalar = screen->get_shader_param(screen, c->scan->processor, PIPE_SHADER_CAP_SCALAR_ISA);
2409 c->cap_packed_uniforms = screen->get_param(screen, PIPE_CAP_PACKED_UNIFORMS);
2410 c->cap_samplers_as_deref = screen->get_param(screen, PIPE_CAP_NIR_SAMPLERS_AS_DEREF);
2411 c->cap_face_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL);
2412 c->cap_position_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL);
2413 c->cap_point_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL);
2414 }
2415
2416 /**
2417 * Initializes a TGSI-to-NIR compiler.
2418 */
2419 static struct ttn_compile *
2420 ttn_compile_init(const void *tgsi_tokens,
2421 const nir_shader_compiler_options *options,
2422 struct pipe_screen *screen)
2423 {
2424 struct ttn_compile *c;
2425 struct nir_shader *s;
2426 struct tgsi_shader_info scan;
2427
2428 assert(options || screen);
2429 c = rzalloc(NULL, struct ttn_compile);
2430
2431 tgsi_scan_shader(tgsi_tokens, &scan);
2432 c->scan = &scan;
2433
2434 if (!options) {
2435 options =
2436 screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR, scan.processor);
2437 }
2438
2439 nir_builder_init_simple_shader(&c->build, NULL,
2440 tgsi_processor_to_shader_stage(scan.processor),
2441 options);
2442
2443 s = c->build.shader;
2444
2445 if (screen) {
2446 ttn_read_pipe_caps(c, screen);
2447 } else {
2448 /* TTN used to be hard coded to always make FACE a sysval,
2449 * so it makes sense to preserve that behavior so users don't break. */
2450 c->cap_face_is_sysval = true;
2451 }
2452
2453 if (s->info.stage == MESA_SHADER_FRAGMENT)
2454 s->info.fs.untyped_color_outputs = true;
2455
2456 s->num_inputs = scan.file_max[TGSI_FILE_INPUT] + 1;
2457 s->num_uniforms = scan.const_file_max[0] + 1;
2458 s->num_outputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
2459
2460 for (unsigned i = 0; i < TGSI_PROPERTY_COUNT; i++) {
2461 unsigned value = scan.properties[i];
2462
2463 switch (i) {
2464 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
2465 break; /* handled in ttn_emit_declaration */
2466 case TGSI_PROPERTY_FS_COORD_ORIGIN:
2467 if (s->info.stage == MESA_SHADER_FRAGMENT)
2468 s->info.fs.origin_upper_left = value == TGSI_FS_COORD_ORIGIN_UPPER_LEFT;
2469 break;
2470 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
2471 if (s->info.stage == MESA_SHADER_FRAGMENT)
2472 s->info.fs.pixel_center_integer = value == TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
2473 break;
2474 case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
2475 if (s->info.stage == MESA_SHADER_FRAGMENT)
2476 s->info.fs.depth_layout = ttn_get_depth_layout(value);
2477 break;
2478 case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION:
2479 if (s->info.stage == MESA_SHADER_VERTEX)
2480 s->info.vs.window_space_position = value;
2481 break;
2482 case TGSI_PROPERTY_NEXT_SHADER:
2483 s->info.next_stage = tgsi_processor_to_shader_stage(value);
2484 break;
2485 case TGSI_PROPERTY_VS_BLIT_SGPRS_AMD:
2486 if (s->info.stage == MESA_SHADER_VERTEX)
2487 s->info.vs.blit_sgprs_amd = value;
2488 break;
2489 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH:
2490 if (s->info.stage == MESA_SHADER_COMPUTE)
2491 s->info.cs.local_size[0] = value;
2492 break;
2493 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT:
2494 if (s->info.stage == MESA_SHADER_COMPUTE)
2495 s->info.cs.local_size[1] = value;
2496 break;
2497 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH:
2498 if (s->info.stage == MESA_SHADER_COMPUTE)
2499 s->info.cs.local_size[2] = value;
2500 break;
2501 case TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD:
2502 if (s->info.stage == MESA_SHADER_COMPUTE)
2503 s->info.cs.user_data_components_amd = value;
2504 break;
2505 default:
2506 if (value) {
2507 fprintf(stderr, "tgsi_to_nir: unhandled TGSI property %u = %u\n",
2508 i, value);
2509 unreachable("unhandled TGSI property");
2510 }
2511 }
2512 }
2513
2514 if (s->info.stage == MESA_SHADER_COMPUTE &&
2515 (!s->info.cs.local_size[0] ||
2516 !s->info.cs.local_size[1] ||
2517 !s->info.cs.local_size[2]))
2518 s->info.cs.local_size_variable = true;
2519
2520 c->inputs = rzalloc_array(c, struct nir_variable *, s->num_inputs);
2521 c->outputs = rzalloc_array(c, struct nir_variable *, s->num_outputs);
2522
2523 c->output_regs = rzalloc_array(c, struct ttn_reg_info,
2524 scan.file_max[TGSI_FILE_OUTPUT] + 1);
2525 c->temp_regs = rzalloc_array(c, struct ttn_reg_info,
2526 scan.file_max[TGSI_FILE_TEMPORARY] + 1);
2527 c->imm_defs = rzalloc_array(c, nir_ssa_def *,
2528 scan.file_max[TGSI_FILE_IMMEDIATE] + 1);
2529
2530 c->num_samp_types = scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1;
2531 c->samp_types = rzalloc_array(c, nir_alu_type, c->num_samp_types);
2532
2533 c->if_stack = rzalloc_array(c, nir_cursor,
2534 (scan.opcode_count[TGSI_OPCODE_IF] +
2535 scan.opcode_count[TGSI_OPCODE_UIF]) * 2);
2536 c->loop_stack = rzalloc_array(c, nir_cursor,
2537 scan.opcode_count[TGSI_OPCODE_BGNLOOP]);
2538
2539
2540 ttn_parse_tgsi(c, tgsi_tokens);
2541 ttn_add_output_stores(c);
2542
2543 nir_validate_shader(c->build.shader, "TTN: after parsing TGSI and creating the NIR shader");
2544
2545 return c;
2546 }
2547
2548 static void
2549 ttn_optimize_nir(nir_shader *nir, bool scalar)
2550 {
2551 bool progress;
2552 do {
2553 progress = false;
2554
2555 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2556
2557 if (scalar) {
2558 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
2559 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
2560 }
2561
2562 NIR_PASS_V(nir, nir_lower_alu);
2563 NIR_PASS_V(nir, nir_lower_pack);
2564 NIR_PASS(progress, nir, nir_copy_prop);
2565 NIR_PASS(progress, nir, nir_opt_remove_phis);
2566 NIR_PASS(progress, nir, nir_opt_dce);
2567
2568 if (nir_opt_trivial_continues(nir)) {
2569 progress = true;
2570 NIR_PASS(progress, nir, nir_copy_prop);
2571 NIR_PASS(progress, nir, nir_opt_dce);
2572 }
2573
2574 NIR_PASS(progress, nir, nir_opt_if, false);
2575 NIR_PASS(progress, nir, nir_opt_dead_cf);
2576 NIR_PASS(progress, nir, nir_opt_cse);
2577 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
2578
2579 NIR_PASS(progress, nir, nir_opt_algebraic);
2580 NIR_PASS(progress, nir, nir_opt_constant_folding);
2581
2582 NIR_PASS(progress, nir, nir_opt_undef);
2583 NIR_PASS(progress, nir, nir_opt_conditional_discard);
2584
2585 if (nir->options->max_unroll_iterations) {
2586 NIR_PASS(progress, nir, nir_opt_loop_unroll, (nir_variable_mode)0);
2587 }
2588
2589 } while (progress);
2590
2591 }
2592
2593 /**
2594 * Finalizes the NIR in a similar way as st_glsl_to_nir does.
2595 *
2596 * Drivers expect that these passes are already performed,
2597 * so we have to do it here too.
2598 */
2599 static void
2600 ttn_finalize_nir(struct ttn_compile *c)
2601 {
2602 struct nir_shader *nir = c->build.shader;
2603
2604 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2605 NIR_PASS_V(nir, nir_lower_regs_to_ssa);
2606
2607 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2608 NIR_PASS_V(nir, nir_split_var_copies);
2609 NIR_PASS_V(nir, nir_lower_var_copies);
2610 NIR_PASS_V(nir, nir_lower_system_values);
2611
2612 if (c->cap_packed_uniforms)
2613 NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, 16);
2614
2615 if (c->cap_samplers_as_deref)
2616 NIR_PASS_V(nir, gl_nir_lower_samplers_as_deref, NULL);
2617 else
2618 NIR_PASS_V(nir, gl_nir_lower_samplers, NULL);
2619
2620 ttn_optimize_nir(nir, c->cap_scalar);
2621 nir_shader_gather_info(nir, c->build.impl);
2622 nir_validate_shader(nir, "TTN: after all optimizations");
2623 }
2624
2625 struct nir_shader *
2626 tgsi_to_nir(const void *tgsi_tokens,
2627 struct pipe_screen *screen)
2628 {
2629 struct ttn_compile *c;
2630 struct nir_shader *s;
2631
2632 c = ttn_compile_init(tgsi_tokens, NULL, screen);
2633 s = c->build.shader;
2634 ttn_finalize_nir(c);
2635 ralloc_free(c);
2636
2637 return s;
2638 }
2639
2640 struct nir_shader *
2641 tgsi_to_nir_noscreen(const void *tgsi_tokens,
2642 const nir_shader_compiler_options *options)
2643 {
2644 struct ttn_compile *c;
2645 struct nir_shader *s;
2646
2647 c = ttn_compile_init(tgsi_tokens, options, NULL);
2648 s = c->build.shader;
2649 ralloc_free(c);
2650
2651 return s;
2652 }
2653