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compiler: add SYSTEM_VALUE_TESS_LEVEL_OUTER/INNER_DEFAULT
[mesa.git] / src / gallium / auxiliary / nir / tgsi_to_nir.c
1 /*
2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/ralloc.h"
26 #include "pipe/p_screen.h"
27
28 #include "compiler/nir/nir.h"
29 #include "compiler/nir/nir_control_flow.h"
30 #include "compiler/nir/nir_builder.h"
31 #include "compiler/glsl/gl_nir.h"
32 #include "compiler/glsl/list.h"
33 #include "compiler/shader_enums.h"
34
35 #include "tgsi_to_nir.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_dump.h"
38 #include "tgsi/tgsi_info.h"
39 #include "tgsi/tgsi_scan.h"
40 #include "tgsi/tgsi_from_mesa.h"
41
42 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
43 TGSI_SWIZZLE_##X, \
44 TGSI_SWIZZLE_##Y, \
45 TGSI_SWIZZLE_##Z, \
46 TGSI_SWIZZLE_##W, \
47 }
48
49 struct ttn_reg_info {
50 /** nir register containing this TGSI index. */
51 nir_register *reg;
52 nir_variable *var;
53 /** Offset (in vec4s) from the start of var for this TGSI index. */
54 int offset;
55 };
56
57 struct ttn_compile {
58 union tgsi_full_token *token;
59 nir_builder build;
60 struct tgsi_shader_info *scan;
61
62 struct ttn_reg_info *output_regs;
63 struct ttn_reg_info *temp_regs;
64 nir_ssa_def **imm_defs;
65
66 unsigned num_samp_types;
67 nir_alu_type *samp_types;
68
69 nir_register *addr_reg;
70
71 nir_variable **inputs;
72 nir_variable **outputs;
73 nir_variable *samplers[PIPE_MAX_SAMPLERS];
74 nir_variable *images[PIPE_MAX_SHADER_IMAGES];
75 nir_variable *ssbo[PIPE_MAX_SHADER_BUFFERS];
76
77 nir_variable *input_var_face;
78 nir_variable *input_var_position;
79 nir_variable *input_var_point;
80
81 /**
82 * Stack of nir_cursors where instructions should be pushed as we pop
83 * back out of the control flow stack.
84 *
85 * For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else
86 * instructions should be placed, and if_stack[if_stack_pos - 1] has where
87 * the next instructions outside of the if/then/else block go.
88 */
89 nir_cursor *if_stack;
90 unsigned if_stack_pos;
91
92 /**
93 * Stack of nir_cursors where instructions should be pushed as we pop
94 * back out of the control flow stack.
95 *
96 * loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside
97 * of the loop.
98 */
99 nir_cursor *loop_stack;
100 unsigned loop_stack_pos;
101
102 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
103 unsigned next_imm;
104
105 bool cap_scalar;
106 bool cap_face_is_sysval;
107 bool cap_position_is_sysval;
108 bool cap_point_is_sysval;
109 bool cap_packed_uniforms;
110 bool cap_samplers_as_deref;
111 };
112
113 #define ttn_swizzle(b, src, x, y, z, w) \
114 nir_swizzle(b, src, SWIZ(x, y, z, w), 4)
115 #define ttn_channel(b, src, swiz) \
116 nir_channel(b, src, TGSI_SWIZZLE_##swiz)
117
118 static gl_varying_slot
119 tgsi_varying_semantic_to_slot(unsigned semantic, unsigned index)
120 {
121 switch (semantic) {
122 case TGSI_SEMANTIC_POSITION:
123 return VARYING_SLOT_POS;
124 case TGSI_SEMANTIC_COLOR:
125 if (index == 0)
126 return VARYING_SLOT_COL0;
127 else
128 return VARYING_SLOT_COL1;
129 case TGSI_SEMANTIC_BCOLOR:
130 if (index == 0)
131 return VARYING_SLOT_BFC0;
132 else
133 return VARYING_SLOT_BFC1;
134 case TGSI_SEMANTIC_FOG:
135 return VARYING_SLOT_FOGC;
136 case TGSI_SEMANTIC_PSIZE:
137 return VARYING_SLOT_PSIZ;
138 case TGSI_SEMANTIC_GENERIC:
139 return VARYING_SLOT_VAR0 + index;
140 case TGSI_SEMANTIC_FACE:
141 return VARYING_SLOT_FACE;
142 case TGSI_SEMANTIC_EDGEFLAG:
143 return VARYING_SLOT_EDGE;
144 case TGSI_SEMANTIC_PRIMID:
145 return VARYING_SLOT_PRIMITIVE_ID;
146 case TGSI_SEMANTIC_CLIPDIST:
147 if (index == 0)
148 return VARYING_SLOT_CLIP_DIST0;
149 else
150 return VARYING_SLOT_CLIP_DIST1;
151 case TGSI_SEMANTIC_CLIPVERTEX:
152 return VARYING_SLOT_CLIP_VERTEX;
153 case TGSI_SEMANTIC_TEXCOORD:
154 return VARYING_SLOT_TEX0 + index;
155 case TGSI_SEMANTIC_PCOORD:
156 return VARYING_SLOT_PNTC;
157 case TGSI_SEMANTIC_VIEWPORT_INDEX:
158 return VARYING_SLOT_VIEWPORT;
159 case TGSI_SEMANTIC_LAYER:
160 return VARYING_SLOT_LAYER;
161 case TGSI_SEMANTIC_TESSINNER:
162 return VARYING_SLOT_TESS_LEVEL_INNER;
163 case TGSI_SEMANTIC_TESSOUTER:
164 return VARYING_SLOT_TESS_LEVEL_OUTER;
165 default:
166 fprintf(stderr, "Bad TGSI semantic: %d/%d\n", semantic, index);
167 abort();
168 }
169 }
170
171 static enum gl_frag_depth_layout
172 ttn_get_depth_layout(unsigned tgsi_fs_depth_layout)
173 {
174 switch (tgsi_fs_depth_layout) {
175 case TGSI_FS_DEPTH_LAYOUT_NONE:
176 return FRAG_DEPTH_LAYOUT_NONE;
177 case TGSI_FS_DEPTH_LAYOUT_ANY:
178 return FRAG_DEPTH_LAYOUT_ANY;
179 case TGSI_FS_DEPTH_LAYOUT_GREATER:
180 return FRAG_DEPTH_LAYOUT_GREATER;
181 case TGSI_FS_DEPTH_LAYOUT_LESS:
182 return FRAG_DEPTH_LAYOUT_LESS;
183 case TGSI_FS_DEPTH_LAYOUT_UNCHANGED:
184 return FRAG_DEPTH_LAYOUT_UNCHANGED;
185 default:
186 unreachable("bad TGSI FS depth layout");
187 }
188 }
189
190 static nir_ssa_def *
191 ttn_src_for_dest(nir_builder *b, nir_alu_dest *dest)
192 {
193 nir_alu_src src;
194 memset(&src, 0, sizeof(src));
195
196 if (dest->dest.is_ssa)
197 src.src = nir_src_for_ssa(&dest->dest.ssa);
198 else {
199 assert(!dest->dest.reg.indirect);
200 src.src = nir_src_for_reg(dest->dest.reg.reg);
201 src.src.reg.base_offset = dest->dest.reg.base_offset;
202 }
203
204 for (int i = 0; i < 4; i++)
205 src.swizzle[i] = i;
206
207 return nir_mov_alu(b, src, 4);
208 }
209
210 static enum glsl_interp_mode
211 ttn_translate_interp_mode(unsigned tgsi_interp)
212 {
213 switch (tgsi_interp) {
214 case TGSI_INTERPOLATE_CONSTANT:
215 return INTERP_MODE_FLAT;
216 case TGSI_INTERPOLATE_LINEAR:
217 return INTERP_MODE_NOPERSPECTIVE;
218 case TGSI_INTERPOLATE_PERSPECTIVE:
219 return INTERP_MODE_SMOOTH;
220 case TGSI_INTERPOLATE_COLOR:
221 return INTERP_MODE_SMOOTH;
222 default:
223 unreachable("bad TGSI interpolation mode");
224 }
225 }
226
227 static void
228 ttn_emit_declaration(struct ttn_compile *c)
229 {
230 nir_builder *b = &c->build;
231 struct tgsi_full_declaration *decl = &c->token->FullDeclaration;
232 unsigned array_size = decl->Range.Last - decl->Range.First + 1;
233 unsigned file = decl->Declaration.File;
234 unsigned i;
235
236 if (file == TGSI_FILE_TEMPORARY) {
237 if (decl->Declaration.Array) {
238 /* for arrays, we create variables instead of registers: */
239 nir_variable *var = rzalloc(b->shader, nir_variable);
240
241 var->type = glsl_array_type(glsl_vec4_type(), array_size, 0);
242 var->data.mode = nir_var_shader_temp;
243 var->name = ralloc_asprintf(var, "arr_%d", decl->Array.ArrayID);
244
245 exec_list_push_tail(&b->shader->globals, &var->node);
246
247 for (i = 0; i < array_size; i++) {
248 /* point all the matching slots to the same var,
249 * with appropriate offset set, mostly just so
250 * we know what to do when tgsi does a non-indirect
251 * access
252 */
253 c->temp_regs[decl->Range.First + i].reg = NULL;
254 c->temp_regs[decl->Range.First + i].var = var;
255 c->temp_regs[decl->Range.First + i].offset = i;
256 }
257 } else {
258 for (i = 0; i < array_size; i++) {
259 nir_register *reg = nir_local_reg_create(b->impl);
260 reg->num_components = 4;
261 c->temp_regs[decl->Range.First + i].reg = reg;
262 c->temp_regs[decl->Range.First + i].var = NULL;
263 c->temp_regs[decl->Range.First + i].offset = 0;
264 }
265 }
266 } else if (file == TGSI_FILE_ADDRESS) {
267 c->addr_reg = nir_local_reg_create(b->impl);
268 c->addr_reg->num_components = 4;
269 } else if (file == TGSI_FILE_SYSTEM_VALUE) {
270 /* Nothing to record for system values. */
271 } else if (file == TGSI_FILE_BUFFER) {
272 /* Nothing to record for buffers. */
273 } else if (file == TGSI_FILE_IMAGE) {
274 /* Nothing to record for images. */
275 } else if (file == TGSI_FILE_SAMPLER) {
276 /* Nothing to record for samplers. */
277 } else if (file == TGSI_FILE_SAMPLER_VIEW) {
278 struct tgsi_declaration_sampler_view *sview = &decl->SamplerView;
279 nir_alu_type type;
280
281 assert((sview->ReturnTypeX == sview->ReturnTypeY) &&
282 (sview->ReturnTypeX == sview->ReturnTypeZ) &&
283 (sview->ReturnTypeX == sview->ReturnTypeW));
284
285 switch (sview->ReturnTypeX) {
286 case TGSI_RETURN_TYPE_SINT:
287 type = nir_type_int;
288 break;
289 case TGSI_RETURN_TYPE_UINT:
290 type = nir_type_uint;
291 break;
292 case TGSI_RETURN_TYPE_FLOAT:
293 default:
294 type = nir_type_float;
295 break;
296 }
297
298 for (i = 0; i < array_size; i++) {
299 c->samp_types[decl->Range.First + i] = type;
300 }
301 } else {
302 bool is_array = (array_size > 1);
303
304 assert(file == TGSI_FILE_INPUT ||
305 file == TGSI_FILE_OUTPUT ||
306 file == TGSI_FILE_CONSTANT);
307
308 /* nothing to do for UBOs: */
309 if ((file == TGSI_FILE_CONSTANT) && decl->Declaration.Dimension &&
310 decl->Dim.Index2D != 0) {
311 b->shader->info.num_ubos =
312 MAX2(b->shader->info.num_ubos, decl->Dim.Index2D);
313 return;
314 }
315
316 if ((file == TGSI_FILE_INPUT) || (file == TGSI_FILE_OUTPUT)) {
317 is_array = (is_array && decl->Declaration.Array &&
318 (decl->Array.ArrayID != 0));
319 }
320
321 for (i = 0; i < array_size; i++) {
322 unsigned idx = decl->Range.First + i;
323 nir_variable *var = rzalloc(b->shader, nir_variable);
324
325 var->data.driver_location = idx;
326
327 var->type = glsl_vec4_type();
328 if (is_array)
329 var->type = glsl_array_type(var->type, array_size, 0);
330
331 switch (file) {
332 case TGSI_FILE_INPUT:
333 var->data.read_only = true;
334 var->data.mode = nir_var_shader_in;
335 var->name = ralloc_asprintf(var, "in_%d", idx);
336
337 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
338 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
339 var->type = glsl_bool_type();
340 if (c->cap_face_is_sysval) {
341 var->data.mode = nir_var_system_value;
342 var->data.location = SYSTEM_VALUE_FRONT_FACE;
343 } else {
344 var->data.location = VARYING_SLOT_FACE;
345 }
346 c->input_var_face = var;
347 } else if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
348 if (c->cap_position_is_sysval) {
349 var->data.mode = nir_var_system_value;
350 var->data.location = SYSTEM_VALUE_FRAG_COORD;
351 } else {
352 var->data.location = VARYING_SLOT_POS;
353 }
354 c->input_var_position = var;
355 } else if (decl->Semantic.Name == TGSI_SEMANTIC_PCOORD) {
356 if (c->cap_point_is_sysval) {
357 var->data.mode = nir_var_system_value;
358 var->data.location = SYSTEM_VALUE_POINT_COORD;
359 } else {
360 var->data.location = VARYING_SLOT_PNTC;
361 }
362 c->input_var_point = var;
363 } else {
364 var->data.location =
365 tgsi_varying_semantic_to_slot(decl->Semantic.Name,
366 decl->Semantic.Index);
367 }
368 } else {
369 assert(!decl->Declaration.Semantic);
370 var->data.location = VERT_ATTRIB_GENERIC0 + idx;
371 }
372 var->data.index = 0;
373 var->data.interpolation =
374 ttn_translate_interp_mode(decl->Interp.Interpolate);
375
376 exec_list_push_tail(&b->shader->inputs, &var->node);
377 c->inputs[idx] = var;
378
379 for (int i = 0; i < array_size; i++)
380 b->shader->info.inputs_read |= 1 << (var->data.location + i);
381
382 break;
383 case TGSI_FILE_OUTPUT: {
384 int semantic_name = decl->Semantic.Name;
385 int semantic_index = decl->Semantic.Index;
386 /* Since we can't load from outputs in the IR, we make temporaries
387 * for the outputs and emit stores to the real outputs at the end of
388 * the shader.
389 */
390 nir_register *reg = nir_local_reg_create(b->impl);
391 reg->num_components = 4;
392 if (is_array)
393 reg->num_array_elems = array_size;
394
395 var->data.mode = nir_var_shader_out;
396 var->name = ralloc_asprintf(var, "out_%d", idx);
397 var->data.index = 0;
398 var->data.interpolation =
399 ttn_translate_interp_mode(decl->Interp.Interpolate);
400 var->data.patch = semantic_name == TGSI_SEMANTIC_TESSINNER ||
401 semantic_name == TGSI_SEMANTIC_TESSOUTER ||
402 semantic_name == TGSI_SEMANTIC_PATCH;
403
404 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
405 switch (semantic_name) {
406 case TGSI_SEMANTIC_COLOR: {
407 /* TODO tgsi loses some information, so we cannot
408 * actually differentiate here between DSB and MRT
409 * at this point. But so far no drivers using tgsi-
410 * to-nir support dual source blend:
411 */
412 bool dual_src_blend = false;
413 if (dual_src_blend && (semantic_index == 1)) {
414 var->data.location = FRAG_RESULT_DATA0;
415 var->data.index = 1;
416 } else {
417 if (c->scan->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
418 var->data.location = FRAG_RESULT_COLOR;
419 else
420 var->data.location = FRAG_RESULT_DATA0 + semantic_index;
421 }
422 break;
423 }
424 case TGSI_SEMANTIC_POSITION:
425 var->data.location = FRAG_RESULT_DEPTH;
426 var->type = glsl_float_type();
427 break;
428 case TGSI_SEMANTIC_STENCIL:
429 var->data.location = FRAG_RESULT_STENCIL;
430 var->type = glsl_int_type();
431 break;
432 default:
433 fprintf(stderr, "Bad TGSI semantic: %d/%d\n",
434 decl->Semantic.Name, decl->Semantic.Index);
435 abort();
436 }
437 } else {
438 var->data.location =
439 tgsi_varying_semantic_to_slot(semantic_name, semantic_index);
440 }
441
442 if (is_array) {
443 unsigned j;
444 for (j = 0; j < array_size; j++) {
445 c->output_regs[idx + j].offset = i + j;
446 c->output_regs[idx + j].reg = reg;
447 }
448 } else {
449 c->output_regs[idx].offset = i;
450 c->output_regs[idx].reg = reg;
451 }
452
453 exec_list_push_tail(&b->shader->outputs, &var->node);
454 c->outputs[idx] = var;
455
456 for (int i = 0; i < array_size; i++)
457 b->shader->info.outputs_written |= 1ull << (var->data.location + i);
458 }
459 break;
460 case TGSI_FILE_CONSTANT:
461 var->data.mode = nir_var_uniform;
462 var->name = ralloc_asprintf(var, "uniform_%d", idx);
463 var->data.location = idx;
464
465 exec_list_push_tail(&b->shader->uniforms, &var->node);
466 break;
467 default:
468 unreachable("bad declaration file");
469 return;
470 }
471
472 if (is_array)
473 break;
474 }
475
476 }
477 }
478
479 static void
480 ttn_emit_immediate(struct ttn_compile *c)
481 {
482 nir_builder *b = &c->build;
483 struct tgsi_full_immediate *tgsi_imm = &c->token->FullImmediate;
484 nir_load_const_instr *load_const;
485 int i;
486
487 load_const = nir_load_const_instr_create(b->shader, 4, 32);
488 c->imm_defs[c->next_imm] = &load_const->def;
489 c->next_imm++;
490
491 for (i = 0; i < load_const->def.num_components; i++)
492 load_const->value[i].u32 = tgsi_imm->u[i].Uint;
493
494 nir_builder_instr_insert(b, &load_const->instr);
495 }
496
497 static nir_ssa_def *
498 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect);
499
500 /* generate either a constant or indirect deref chain for accessing an
501 * array variable.
502 */
503 static nir_deref_instr *
504 ttn_array_deref(struct ttn_compile *c, nir_variable *var, unsigned offset,
505 struct tgsi_ind_register *indirect)
506 {
507 nir_deref_instr *deref = nir_build_deref_var(&c->build, var);
508 nir_ssa_def *index = nir_imm_int(&c->build, offset);
509 if (indirect)
510 index = nir_iadd(&c->build, index, ttn_src_for_indirect(c, indirect));
511 return nir_build_deref_array(&c->build, deref, index);
512 }
513
514 /* Special case: Turn the frontface varying into a load of the
515 * frontface variable, and create the vector as required by TGSI.
516 */
517 static nir_ssa_def *
518 ttn_emulate_tgsi_front_face(struct ttn_compile *c)
519 {
520 nir_ssa_def *tgsi_frontface[4];
521
522 if (c->cap_face_is_sysval) {
523 /* When it's a system value, it should be an integer vector: (F, 0, 0, 1)
524 * F is 0xffffffff if front-facing, 0 if not.
525 */
526
527 nir_ssa_def *frontface = nir_load_front_face(&c->build, 1);
528
529 tgsi_frontface[0] = nir_bcsel(&c->build,
530 frontface,
531 nir_imm_int(&c->build, 0xffffffff),
532 nir_imm_int(&c->build, 0));
533 tgsi_frontface[1] = nir_imm_int(&c->build, 0);
534 tgsi_frontface[2] = nir_imm_int(&c->build, 0);
535 tgsi_frontface[3] = nir_imm_int(&c->build, 1);
536 } else {
537 /* When it's an input, it should be a float vector: (F, 0.0, 0.0, 1.0)
538 * F is positive if front-facing, negative if not.
539 */
540
541 assert(c->input_var_face);
542 nir_ssa_def *frontface = nir_load_var(&c->build, c->input_var_face);
543
544 tgsi_frontface[0] = nir_bcsel(&c->build,
545 frontface,
546 nir_imm_float(&c->build, 1.0),
547 nir_imm_float(&c->build, -1.0));
548 tgsi_frontface[1] = nir_imm_float(&c->build, 0.0);
549 tgsi_frontface[2] = nir_imm_float(&c->build, 0.0);
550 tgsi_frontface[3] = nir_imm_float(&c->build, 1.0);
551 }
552
553 return nir_vec(&c->build, tgsi_frontface, 4);
554 }
555
556 static nir_src
557 ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
558 struct tgsi_ind_register *indirect,
559 struct tgsi_dimension *dim,
560 struct tgsi_ind_register *dimind,
561 bool src_is_float)
562 {
563 nir_builder *b = &c->build;
564 nir_src src;
565
566 memset(&src, 0, sizeof(src));
567
568 switch (file) {
569 case TGSI_FILE_TEMPORARY:
570 if (c->temp_regs[index].var) {
571 unsigned offset = c->temp_regs[index].offset;
572 nir_variable *var = c->temp_regs[index].var;
573 nir_ssa_def *load = nir_load_deref(&c->build,
574 ttn_array_deref(c, var, offset, indirect));
575
576 src = nir_src_for_ssa(load);
577 } else {
578 assert(!indirect);
579 src.reg.reg = c->temp_regs[index].reg;
580 }
581 assert(!dim);
582 break;
583
584 case TGSI_FILE_ADDRESS:
585 src.reg.reg = c->addr_reg;
586 assert(!dim);
587 break;
588
589 case TGSI_FILE_IMMEDIATE:
590 src = nir_src_for_ssa(c->imm_defs[index]);
591 assert(!indirect);
592 assert(!dim);
593 break;
594
595 case TGSI_FILE_SYSTEM_VALUE: {
596 nir_intrinsic_op op;
597 nir_ssa_def *load;
598
599 assert(!indirect);
600 assert(!dim);
601
602 switch (c->scan->system_value_semantic_name[index]) {
603 case TGSI_SEMANTIC_VERTEXID_NOBASE:
604 op = nir_intrinsic_load_vertex_id_zero_base;
605 load = nir_load_vertex_id_zero_base(b);
606 break;
607 case TGSI_SEMANTIC_VERTEXID:
608 op = nir_intrinsic_load_vertex_id;
609 load = nir_load_vertex_id(b);
610 break;
611 case TGSI_SEMANTIC_BASEVERTEX:
612 op = nir_intrinsic_load_base_vertex;
613 load = nir_load_base_vertex(b);
614 break;
615 case TGSI_SEMANTIC_INSTANCEID:
616 op = nir_intrinsic_load_instance_id;
617 load = nir_load_instance_id(b);
618 break;
619 case TGSI_SEMANTIC_FACE:
620 assert(c->cap_face_is_sysval);
621 op = nir_intrinsic_load_front_face;
622 load = ttn_emulate_tgsi_front_face(c);
623 break;
624 case TGSI_SEMANTIC_POSITION:
625 assert(c->cap_position_is_sysval);
626 op = nir_intrinsic_load_frag_coord;
627 load = nir_load_frag_coord(b);
628 break;
629 case TGSI_SEMANTIC_PCOORD:
630 assert(c->cap_point_is_sysval);
631 op = nir_intrinsic_load_point_coord;
632 load = nir_load_point_coord(b);
633 break;
634 case TGSI_SEMANTIC_THREAD_ID:
635 op = nir_intrinsic_load_local_invocation_id;
636 load = nir_load_local_invocation_id(b);
637 break;
638 case TGSI_SEMANTIC_BLOCK_ID:
639 op = nir_intrinsic_load_work_group_id;
640 load = nir_load_work_group_id(b);
641 break;
642 case TGSI_SEMANTIC_CS_USER_DATA_AMD:
643 op = nir_intrinsic_load_user_data_amd;
644 load = nir_load_user_data_amd(b);
645 break;
646 case TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL:
647 op = nir_intrinsic_load_tess_level_inner_default;
648 load = nir_load_tess_level_inner_default(b);
649 break;
650 case TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL:
651 op = nir_intrinsic_load_tess_level_outer_default;
652 load = nir_load_tess_level_outer_default(b);
653 break;
654 default:
655 unreachable("bad system value");
656 }
657
658 src = nir_src_for_ssa(load);
659 b->shader->info.system_values_read |=
660 (1 << nir_system_value_from_intrinsic(op));
661
662 break;
663 }
664
665 case TGSI_FILE_INPUT:
666 if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
667 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_FACE) {
668 assert(!c->cap_face_is_sysval && c->input_var_face);
669 return nir_src_for_ssa(ttn_emulate_tgsi_front_face(c));
670 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
671 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_POSITION) {
672 assert(!c->cap_position_is_sysval && c->input_var_position);
673 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_position));
674 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
675 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_PCOORD) {
676 assert(!c->cap_point_is_sysval && c->input_var_point);
677 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_point));
678 } else {
679 /* Indirection on input arrays isn't supported by TTN. */
680 assert(!dim);
681 nir_deref_instr *deref = nir_build_deref_var(&c->build,
682 c->inputs[index]);
683 return nir_src_for_ssa(nir_load_deref(&c->build, deref));
684 }
685 break;
686
687 case TGSI_FILE_CONSTANT: {
688 nir_intrinsic_instr *load;
689 nir_intrinsic_op op;
690 unsigned srcn = 0;
691
692 if (dim && (dim->Index > 0 || dim->Indirect)) {
693 op = nir_intrinsic_load_ubo;
694 } else {
695 op = nir_intrinsic_load_uniform;
696 }
697
698 load = nir_intrinsic_instr_create(b->shader, op);
699 if (op == nir_intrinsic_load_uniform) {
700 nir_intrinsic_set_type(load, src_is_float ? nir_type_float :
701 nir_type_int);
702 }
703
704 load->num_components = 4;
705 if (dim && (dim->Index > 0 || dim->Indirect)) {
706 if (dimind) {
707 load->src[srcn] =
708 ttn_src_for_file_and_index(c, dimind->File, dimind->Index,
709 NULL, NULL, NULL, false);
710 } else {
711 /* UBOs start at index 1 in TGSI: */
712 load->src[srcn] =
713 nir_src_for_ssa(nir_imm_int(b, dim->Index - 1));
714 }
715 srcn++;
716 }
717
718 nir_ssa_def *offset;
719 if (op == nir_intrinsic_load_ubo) {
720 /* UBO loads don't have a base offset. */
721 offset = nir_imm_int(b, index);
722 if (indirect) {
723 offset = nir_iadd(b, offset, ttn_src_for_indirect(c, indirect));
724 }
725 /* UBO offsets are in bytes, but TGSI gives them to us in vec4's */
726 offset = nir_ishl(b, offset, nir_imm_int(b, 4));
727 } else {
728 nir_intrinsic_set_base(load, index);
729 if (indirect) {
730 offset = ttn_src_for_indirect(c, indirect);
731 } else {
732 offset = nir_imm_int(b, 0);
733 }
734 }
735 load->src[srcn++] = nir_src_for_ssa(offset);
736
737 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
738 nir_builder_instr_insert(b, &load->instr);
739
740 src = nir_src_for_ssa(&load->dest.ssa);
741 break;
742 }
743
744 default:
745 unreachable("bad src file");
746 }
747
748
749 return src;
750 }
751
752 static nir_ssa_def *
753 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect)
754 {
755 nir_builder *b = &c->build;
756 nir_alu_src src;
757 memset(&src, 0, sizeof(src));
758 for (int i = 0; i < 4; i++)
759 src.swizzle[i] = indirect->Swizzle;
760 src.src = ttn_src_for_file_and_index(c,
761 indirect->File,
762 indirect->Index,
763 NULL, NULL, NULL,
764 false);
765 return nir_mov_alu(b, src, 1);
766 }
767
768 static nir_alu_dest
769 ttn_get_dest(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
770 {
771 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
772 nir_alu_dest dest;
773 unsigned index = tgsi_dst->Index;
774
775 memset(&dest, 0, sizeof(dest));
776
777 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
778 if (c->temp_regs[index].var) {
779 nir_register *reg;
780
781 /* this works, because TGSI will give us a base offset
782 * (in case of indirect index) that points back into
783 * the array. Access can be direct or indirect, we
784 * don't really care. Just create a one-shot dst reg
785 * that will get store_var'd back into the array var
786 * at the end of ttn_emit_instruction()
787 */
788 reg = nir_local_reg_create(c->build.impl);
789 reg->num_components = 4;
790 dest.dest.reg.reg = reg;
791 dest.dest.reg.base_offset = 0;
792 } else {
793 assert(!tgsi_dst->Indirect);
794 dest.dest.reg.reg = c->temp_regs[index].reg;
795 dest.dest.reg.base_offset = c->temp_regs[index].offset;
796 }
797 } else if (tgsi_dst->File == TGSI_FILE_OUTPUT) {
798 dest.dest.reg.reg = c->output_regs[index].reg;
799 dest.dest.reg.base_offset = c->output_regs[index].offset;
800 } else if (tgsi_dst->File == TGSI_FILE_ADDRESS) {
801 assert(index == 0);
802 dest.dest.reg.reg = c->addr_reg;
803 }
804
805 dest.write_mask = tgsi_dst->WriteMask;
806 dest.saturate = false;
807
808 if (tgsi_dst->Indirect && (tgsi_dst->File != TGSI_FILE_TEMPORARY)) {
809 nir_src *indirect = ralloc(c->build.shader, nir_src);
810 *indirect = nir_src_for_ssa(ttn_src_for_indirect(c, &tgsi_fdst->Indirect));
811 dest.dest.reg.indirect = indirect;
812 }
813
814 return dest;
815 }
816
817 static nir_variable *
818 ttn_get_var(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
819 {
820 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
821 unsigned index = tgsi_dst->Index;
822
823 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
824 /* we should not have an indirect when there is no var! */
825 if (!c->temp_regs[index].var)
826 assert(!tgsi_dst->Indirect);
827 return c->temp_regs[index].var;
828 }
829
830 return NULL;
831 }
832
833 static nir_ssa_def *
834 ttn_get_src(struct ttn_compile *c, struct tgsi_full_src_register *tgsi_fsrc,
835 int src_idx)
836 {
837 nir_builder *b = &c->build;
838 struct tgsi_src_register *tgsi_src = &tgsi_fsrc->Register;
839 enum tgsi_opcode opcode = c->token->FullInstruction.Instruction.Opcode;
840 unsigned tgsi_src_type = tgsi_opcode_infer_src_type(opcode, src_idx);
841 bool src_is_float = (tgsi_src_type == TGSI_TYPE_FLOAT ||
842 tgsi_src_type == TGSI_TYPE_DOUBLE ||
843 tgsi_src_type == TGSI_TYPE_UNTYPED);
844 nir_alu_src src;
845
846 memset(&src, 0, sizeof(src));
847
848 if (tgsi_src->File == TGSI_FILE_NULL) {
849 return nir_imm_float(b, 0.0);
850 } else if (tgsi_src->File == TGSI_FILE_SAMPLER ||
851 tgsi_src->File == TGSI_FILE_IMAGE ||
852 tgsi_src->File == TGSI_FILE_BUFFER) {
853 /* Only the index of the resource gets used in texturing, and it will
854 * handle looking that up on its own instead of using the nir_alu_src.
855 */
856 assert(!tgsi_src->Indirect);
857 return NULL;
858 } else {
859 struct tgsi_ind_register *ind = NULL;
860 struct tgsi_dimension *dim = NULL;
861 struct tgsi_ind_register *dimind = NULL;
862 if (tgsi_src->Indirect)
863 ind = &tgsi_fsrc->Indirect;
864 if (tgsi_src->Dimension) {
865 dim = &tgsi_fsrc->Dimension;
866 if (dim->Indirect)
867 dimind = &tgsi_fsrc->DimIndirect;
868 }
869 src.src = ttn_src_for_file_and_index(c,
870 tgsi_src->File,
871 tgsi_src->Index,
872 ind, dim, dimind,
873 src_is_float);
874 }
875
876 src.swizzle[0] = tgsi_src->SwizzleX;
877 src.swizzle[1] = tgsi_src->SwizzleY;
878 src.swizzle[2] = tgsi_src->SwizzleZ;
879 src.swizzle[3] = tgsi_src->SwizzleW;
880
881 nir_ssa_def *def = nir_mov_alu(b, src, 4);
882
883 if (tgsi_type_is_64bit(tgsi_src_type))
884 def = nir_bitcast_vector(b, def, 64);
885
886 if (tgsi_src->Absolute) {
887 if (src_is_float)
888 def = nir_fabs(b, def);
889 else
890 def = nir_iabs(b, def);
891 }
892
893 if (tgsi_src->Negate) {
894 if (src_is_float)
895 def = nir_fneg(b, def);
896 else
897 def = nir_ineg(b, def);
898 }
899
900 return def;
901 }
902
903 static void
904 ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
905 nir_ssa_def *def, unsigned write_mask)
906 {
907 if (!(dest.write_mask & write_mask))
908 return;
909
910 nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
911 mov->dest = dest;
912 mov->dest.write_mask &= write_mask;
913 mov->src[0].src = nir_src_for_ssa(def);
914 for (unsigned i = def->num_components; i < 4; i++)
915 mov->src[0].swizzle[i] = def->num_components - 1;
916 nir_builder_instr_insert(b, &mov->instr);
917 }
918
919 static void
920 ttn_move_dest(nir_builder *b, nir_alu_dest dest, nir_ssa_def *def)
921 {
922 ttn_move_dest_masked(b, dest, def, TGSI_WRITEMASK_XYZW);
923 }
924
925 static void
926 ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, unsigned dest_bitsize,
927 nir_ssa_def **src)
928 {
929 nir_ssa_def *def = nir_build_alu_src_arr(b, op, src);
930 if (def->bit_size == 1)
931 def = nir_ineg(b, nir_b2i(b, def, dest_bitsize));
932 assert(def->bit_size == dest_bitsize);
933 if (dest_bitsize == 64) {
934 if (def->num_components > 2) {
935 /* 32 -> 64 bit conversion ops are supposed to only convert the first
936 * two components, and we need to truncate here to avoid creating a
937 * vec8 after bitcasting the destination.
938 */
939 def = nir_channels(b, def, 0x3);
940 }
941 def = nir_bitcast_vector(b, def, 32);
942 }
943 ttn_move_dest(b, dest, def);
944 }
945
946 static void
947 ttn_arl(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
948 {
949 ttn_move_dest(b, dest, nir_f2i32(b, nir_ffloor(b, src[0])));
950 }
951
952 /* EXP - Approximate Exponential Base 2
953 * dst.x = 2^{\lfloor src.x\rfloor}
954 * dst.y = src.x - \lfloor src.x\rfloor
955 * dst.z = 2^{src.x}
956 * dst.w = 1.0
957 */
958 static void
959 ttn_exp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
960 {
961 nir_ssa_def *srcx = ttn_channel(b, src[0], X);
962
963 ttn_move_dest_masked(b, dest, nir_fexp2(b, nir_ffloor(b, srcx)),
964 TGSI_WRITEMASK_X);
965 ttn_move_dest_masked(b, dest, nir_fsub(b, srcx, nir_ffloor(b, srcx)),
966 TGSI_WRITEMASK_Y);
967 ttn_move_dest_masked(b, dest, nir_fexp2(b, srcx), TGSI_WRITEMASK_Z);
968 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
969 }
970
971 /* LOG - Approximate Logarithm Base 2
972 * dst.x = \lfloor\log_2{|src.x|}\rfloor
973 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
974 * dst.z = \log_2{|src.x|}
975 * dst.w = 1.0
976 */
977 static void
978 ttn_log(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
979 {
980 nir_ssa_def *abs_srcx = nir_fabs(b, ttn_channel(b, src[0], X));
981 nir_ssa_def *log2 = nir_flog2(b, abs_srcx);
982
983 ttn_move_dest_masked(b, dest, nir_ffloor(b, log2), TGSI_WRITEMASK_X);
984 ttn_move_dest_masked(b, dest,
985 nir_fdiv(b, abs_srcx, nir_fexp2(b, nir_ffloor(b, log2))),
986 TGSI_WRITEMASK_Y);
987 ttn_move_dest_masked(b, dest, nir_flog2(b, abs_srcx), TGSI_WRITEMASK_Z);
988 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
989 }
990
991 /* DST - Distance Vector
992 * dst.x = 1.0
993 * dst.y = src0.y \times src1.y
994 * dst.z = src0.z
995 * dst.w = src1.w
996 */
997 static void
998 ttn_dst(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
999 {
1000 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_X);
1001 ttn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), TGSI_WRITEMASK_Y);
1002 ttn_move_dest_masked(b, dest, nir_mov(b, src[0]), TGSI_WRITEMASK_Z);
1003 ttn_move_dest_masked(b, dest, nir_mov(b, src[1]), TGSI_WRITEMASK_W);
1004 }
1005
1006 /* LIT - Light Coefficients
1007 * dst.x = 1.0
1008 * dst.y = max(src.x, 0.0)
1009 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
1010 * dst.w = 1.0
1011 */
1012 static void
1013 ttn_lit(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1014 {
1015 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_XW);
1016
1017 ttn_move_dest_masked(b, dest, nir_fmax(b, ttn_channel(b, src[0], X),
1018 nir_imm_float(b, 0.0)), TGSI_WRITEMASK_Y);
1019
1020 if (dest.write_mask & TGSI_WRITEMASK_Z) {
1021 nir_ssa_def *src0_y = ttn_channel(b, src[0], Y);
1022 nir_ssa_def *wclamp = nir_fmax(b, nir_fmin(b, ttn_channel(b, src[0], W),
1023 nir_imm_float(b, 128.0)),
1024 nir_imm_float(b, -128.0));
1025 nir_ssa_def *pow = nir_fpow(b, nir_fmax(b, src0_y, nir_imm_float(b, 0.0)),
1026 wclamp);
1027
1028 ttn_move_dest_masked(b, dest,
1029 nir_bcsel(b,
1030 nir_flt(b,
1031 ttn_channel(b, src[0], X),
1032 nir_imm_float(b, 0.0)),
1033 nir_imm_float(b, 0.0),
1034 pow),
1035 TGSI_WRITEMASK_Z);
1036 }
1037 }
1038
1039 static void
1040 ttn_sle(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1041 {
1042 ttn_move_dest(b, dest, nir_sge(b, src[1], src[0]));
1043 }
1044
1045 static void
1046 ttn_sgt(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1047 {
1048 ttn_move_dest(b, dest, nir_slt(b, src[1], src[0]));
1049 }
1050
1051 static void
1052 ttn_dp2(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1053 {
1054 ttn_move_dest(b, dest, nir_fdot2(b, src[0], src[1]));
1055 }
1056
1057 static void
1058 ttn_dp3(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1059 {
1060 ttn_move_dest(b, dest, nir_fdot3(b, src[0], src[1]));
1061 }
1062
1063 static void
1064 ttn_dp4(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1065 {
1066 ttn_move_dest(b, dest, nir_fdot4(b, src[0], src[1]));
1067 }
1068
1069 static void
1070 ttn_umad(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1071 {
1072 ttn_move_dest(b, dest, nir_iadd(b, nir_imul(b, src[0], src[1]), src[2]));
1073 }
1074
1075 static void
1076 ttn_arr(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1077 {
1078 ttn_move_dest(b, dest, nir_f2i32(b, nir_fround_even(b, src[0])));
1079 }
1080
1081 static void
1082 ttn_cmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1083 {
1084 ttn_move_dest(b, dest, nir_bcsel(b,
1085 nir_flt(b, src[0], nir_imm_float(b, 0.0)),
1086 src[1], src[2]));
1087 }
1088
1089 static void
1090 ttn_ucmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1091 {
1092 ttn_move_dest(b, dest, nir_bcsel(b,
1093 nir_ine(b, src[0], nir_imm_int(b, 0)),
1094 src[1], src[2]));
1095 }
1096
1097 static void
1098 ttn_kill(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1099 {
1100 nir_intrinsic_instr *discard =
1101 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard);
1102 nir_builder_instr_insert(b, &discard->instr);
1103 b->shader->info.fs.uses_discard = true;
1104 }
1105
1106 static void
1107 ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1108 {
1109 nir_ssa_def *cmp = nir_bany(b, nir_flt(b, src[0], nir_imm_float(b, 0.0)));
1110 nir_intrinsic_instr *discard =
1111 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard_if);
1112 discard->src[0] = nir_src_for_ssa(cmp);
1113 nir_builder_instr_insert(b, &discard->instr);
1114 b->shader->info.fs.uses_discard = true;
1115 }
1116
1117 static void
1118 ttn_if(struct ttn_compile *c, nir_ssa_def *src, bool is_uint)
1119 {
1120 nir_builder *b = &c->build;
1121 nir_ssa_def *src_x = ttn_channel(b, src, X);
1122
1123 nir_if *if_stmt = nir_if_create(b->shader);
1124 if (is_uint) {
1125 /* equivalent to TGSI UIF, src is interpreted as integer */
1126 if_stmt->condition = nir_src_for_ssa(nir_ine(b, src_x, nir_imm_int(b, 0)));
1127 } else {
1128 /* equivalent to TGSI IF, src is interpreted as float */
1129 if_stmt->condition = nir_src_for_ssa(nir_fne(b, src_x, nir_imm_float(b, 0.0)));
1130 }
1131 nir_builder_cf_insert(b, &if_stmt->cf_node);
1132
1133 c->if_stack[c->if_stack_pos] = nir_after_cf_node(&if_stmt->cf_node);
1134 c->if_stack_pos++;
1135
1136 b->cursor = nir_after_cf_list(&if_stmt->then_list);
1137
1138 c->if_stack[c->if_stack_pos] = nir_after_cf_list(&if_stmt->else_list);
1139 c->if_stack_pos++;
1140 }
1141
1142 static void
1143 ttn_else(struct ttn_compile *c)
1144 {
1145 nir_builder *b = &c->build;
1146
1147 b->cursor = c->if_stack[c->if_stack_pos - 1];
1148 }
1149
1150 static void
1151 ttn_endif(struct ttn_compile *c)
1152 {
1153 nir_builder *b = &c->build;
1154
1155 c->if_stack_pos -= 2;
1156 b->cursor = c->if_stack[c->if_stack_pos];
1157 }
1158
1159 static void
1160 ttn_bgnloop(struct ttn_compile *c)
1161 {
1162 nir_builder *b = &c->build;
1163
1164 nir_loop *loop = nir_loop_create(b->shader);
1165 nir_builder_cf_insert(b, &loop->cf_node);
1166
1167 c->loop_stack[c->loop_stack_pos] = nir_after_cf_node(&loop->cf_node);
1168 c->loop_stack_pos++;
1169
1170 b->cursor = nir_after_cf_list(&loop->body);
1171 }
1172
1173 static void
1174 ttn_cont(nir_builder *b)
1175 {
1176 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_continue);
1177 nir_builder_instr_insert(b, &instr->instr);
1178 }
1179
1180 static void
1181 ttn_brk(nir_builder *b)
1182 {
1183 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
1184 nir_builder_instr_insert(b, &instr->instr);
1185 }
1186
1187 static void
1188 ttn_endloop(struct ttn_compile *c)
1189 {
1190 nir_builder *b = &c->build;
1191
1192 c->loop_stack_pos--;
1193 b->cursor = c->loop_stack[c->loop_stack_pos];
1194 }
1195
1196 static void
1197 get_texture_info(unsigned texture,
1198 enum glsl_sampler_dim *dim,
1199 bool *is_shadow,
1200 bool *is_array)
1201 {
1202 assert(is_array);
1203 *is_array = false;
1204
1205 if (is_shadow)
1206 *is_shadow = false;
1207
1208 switch (texture) {
1209 case TGSI_TEXTURE_BUFFER:
1210 *dim = GLSL_SAMPLER_DIM_BUF;
1211 break;
1212 case TGSI_TEXTURE_1D:
1213 *dim = GLSL_SAMPLER_DIM_1D;
1214 break;
1215 case TGSI_TEXTURE_1D_ARRAY:
1216 *dim = GLSL_SAMPLER_DIM_1D;
1217 *is_array = true;
1218 break;
1219 case TGSI_TEXTURE_SHADOW1D:
1220 *dim = GLSL_SAMPLER_DIM_1D;
1221 *is_shadow = true;
1222 break;
1223 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1224 *dim = GLSL_SAMPLER_DIM_1D;
1225 *is_shadow = true;
1226 *is_array = true;
1227 break;
1228 case TGSI_TEXTURE_2D:
1229 *dim = GLSL_SAMPLER_DIM_2D;
1230 break;
1231 case TGSI_TEXTURE_2D_ARRAY:
1232 *dim = GLSL_SAMPLER_DIM_2D;
1233 *is_array = true;
1234 break;
1235 case TGSI_TEXTURE_2D_MSAA:
1236 *dim = GLSL_SAMPLER_DIM_MS;
1237 break;
1238 case TGSI_TEXTURE_2D_ARRAY_MSAA:
1239 *dim = GLSL_SAMPLER_DIM_MS;
1240 *is_array = true;
1241 break;
1242 case TGSI_TEXTURE_SHADOW2D:
1243 *dim = GLSL_SAMPLER_DIM_2D;
1244 *is_shadow = true;
1245 break;
1246 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1247 *dim = GLSL_SAMPLER_DIM_2D;
1248 *is_shadow = true;
1249 *is_array = true;
1250 break;
1251 case TGSI_TEXTURE_3D:
1252 *dim = GLSL_SAMPLER_DIM_3D;
1253 break;
1254 case TGSI_TEXTURE_CUBE:
1255 *dim = GLSL_SAMPLER_DIM_CUBE;
1256 break;
1257 case TGSI_TEXTURE_CUBE_ARRAY:
1258 *dim = GLSL_SAMPLER_DIM_CUBE;
1259 *is_array = true;
1260 break;
1261 case TGSI_TEXTURE_SHADOWCUBE:
1262 *dim = GLSL_SAMPLER_DIM_CUBE;
1263 *is_shadow = true;
1264 break;
1265 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1266 *dim = GLSL_SAMPLER_DIM_CUBE;
1267 *is_shadow = true;
1268 *is_array = true;
1269 break;
1270 case TGSI_TEXTURE_RECT:
1271 *dim = GLSL_SAMPLER_DIM_RECT;
1272 break;
1273 case TGSI_TEXTURE_SHADOWRECT:
1274 *dim = GLSL_SAMPLER_DIM_RECT;
1275 *is_shadow = true;
1276 break;
1277 default:
1278 fprintf(stderr, "Unknown TGSI texture target %d\n", texture);
1279 abort();
1280 }
1281 }
1282
1283 static enum glsl_base_type
1284 base_type_for_alu_type(nir_alu_type type)
1285 {
1286 type = nir_alu_type_get_base_type(type);
1287
1288 switch (type) {
1289 case nir_type_float:
1290 return GLSL_TYPE_FLOAT;
1291 case nir_type_int:
1292 return GLSL_TYPE_INT;
1293 case nir_type_uint:
1294 return GLSL_TYPE_UINT;
1295 default:
1296 unreachable("invalid type");
1297 }
1298 }
1299
1300 static nir_variable *
1301 get_sampler_var(struct ttn_compile *c, int binding,
1302 enum glsl_sampler_dim dim,
1303 bool is_shadow,
1304 bool is_array,
1305 enum glsl_base_type base_type)
1306 {
1307 nir_variable *var = c->samplers[binding];
1308 if (!var) {
1309 const struct glsl_type *type =
1310 glsl_sampler_type(dim, is_shadow, is_array, base_type);
1311 var = nir_variable_create(c->build.shader, nir_var_uniform, type,
1312 "sampler");
1313 var->data.binding = binding;
1314 var->data.explicit_binding = true;
1315 c->samplers[binding] = var;
1316 }
1317
1318 return var;
1319 }
1320
1321 static nir_variable *
1322 get_image_var(struct ttn_compile *c, int binding,
1323 enum glsl_sampler_dim dim,
1324 bool is_array,
1325 enum glsl_base_type base_type,
1326 enum gl_access_qualifier access,
1327 GLenum format)
1328 {
1329 nir_variable *var = c->images[binding];
1330
1331 if (!var) {
1332 const struct glsl_type *type = glsl_image_type(dim, is_array, base_type);
1333
1334 var = nir_variable_create(c->build.shader, nir_var_uniform, type, "image");
1335 var->data.binding = binding;
1336 var->data.explicit_binding = true;
1337 var->data.image.access = access;
1338 var->data.image.format = format;
1339 c->images[binding] = var;
1340 }
1341
1342 return var;
1343 }
1344
1345 static void
1346 add_ssbo_var(struct ttn_compile *c, int binding)
1347 {
1348 nir_variable *var = c->ssbo[binding];
1349
1350 if (!var) {
1351 /* A length of 0 is used to denote unsized arrays */
1352 const struct glsl_type *type = glsl_array_type(glsl_uint_type(), 0, 0);
1353
1354 struct glsl_struct_field field = {
1355 .type = type,
1356 .name = "data",
1357 .location = -1,
1358 };
1359
1360 var = nir_variable_create(c->build.shader, nir_var_mem_ssbo, type, "ssbo");
1361 var->data.binding = binding;
1362 var->interface_type =
1363 glsl_interface_type(&field, 1, GLSL_INTERFACE_PACKING_STD430,
1364 false, "data");
1365 c->ssbo[binding] = var;
1366 }
1367 }
1368
1369 static void
1370 ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1371 {
1372 nir_builder *b = &c->build;
1373 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1374 nir_tex_instr *instr;
1375 nir_texop op;
1376 unsigned num_srcs, samp = 1, sview, i;
1377
1378 switch (tgsi_inst->Instruction.Opcode) {
1379 case TGSI_OPCODE_TEX:
1380 op = nir_texop_tex;
1381 num_srcs = 1;
1382 break;
1383 case TGSI_OPCODE_TEX2:
1384 op = nir_texop_tex;
1385 num_srcs = 1;
1386 samp = 2;
1387 break;
1388 case TGSI_OPCODE_TXP:
1389 op = nir_texop_tex;
1390 num_srcs = 2;
1391 break;
1392 case TGSI_OPCODE_TXB:
1393 op = nir_texop_txb;
1394 num_srcs = 2;
1395 break;
1396 case TGSI_OPCODE_TXB2:
1397 op = nir_texop_txb;
1398 num_srcs = 2;
1399 samp = 2;
1400 break;
1401 case TGSI_OPCODE_TXL:
1402 case TGSI_OPCODE_TEX_LZ:
1403 op = nir_texop_txl;
1404 num_srcs = 2;
1405 break;
1406 case TGSI_OPCODE_TXL2:
1407 op = nir_texop_txl;
1408 num_srcs = 2;
1409 samp = 2;
1410 break;
1411 case TGSI_OPCODE_TXF:
1412 case TGSI_OPCODE_TXF_LZ:
1413 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
1414 tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1415 op = nir_texop_txf_ms;
1416 } else {
1417 op = nir_texop_txf;
1418 }
1419 num_srcs = 2;
1420 break;
1421 case TGSI_OPCODE_TXD:
1422 op = nir_texop_txd;
1423 num_srcs = 3;
1424 samp = 3;
1425 break;
1426 case TGSI_OPCODE_LODQ:
1427 op = nir_texop_lod;
1428 num_srcs = 1;
1429 break;
1430
1431 default:
1432 fprintf(stderr, "unknown TGSI tex op %d\n", tgsi_inst->Instruction.Opcode);
1433 abort();
1434 }
1435
1436 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
1437 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1438 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
1439 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1440 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
1441 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
1442 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1443 num_srcs++;
1444 }
1445
1446 /* Deref sources */
1447 num_srcs += 2;
1448
1449 num_srcs += tgsi_inst->Texture.NumOffsets;
1450
1451 instr = nir_tex_instr_create(b->shader, num_srcs);
1452 instr->op = op;
1453
1454 get_texture_info(tgsi_inst->Texture.Texture,
1455 &instr->sampler_dim, &instr->is_shadow, &instr->is_array);
1456
1457 switch (instr->sampler_dim) {
1458 case GLSL_SAMPLER_DIM_1D:
1459 case GLSL_SAMPLER_DIM_BUF:
1460 instr->coord_components = 1;
1461 break;
1462 case GLSL_SAMPLER_DIM_2D:
1463 case GLSL_SAMPLER_DIM_RECT:
1464 case GLSL_SAMPLER_DIM_EXTERNAL:
1465 case GLSL_SAMPLER_DIM_MS:
1466 instr->coord_components = 2;
1467 break;
1468 case GLSL_SAMPLER_DIM_3D:
1469 case GLSL_SAMPLER_DIM_CUBE:
1470 instr->coord_components = 3;
1471 break;
1472 case GLSL_SAMPLER_DIM_SUBPASS:
1473 case GLSL_SAMPLER_DIM_SUBPASS_MS:
1474 unreachable("invalid sampler_dim");
1475 }
1476
1477 if (instr->is_array)
1478 instr->coord_components++;
1479
1480 assert(tgsi_inst->Src[samp].Register.File == TGSI_FILE_SAMPLER);
1481
1482 /* TODO if we supported any opc's which take an explicit SVIEW
1483 * src, we would use that here instead. But for the "legacy"
1484 * texture opc's the SVIEW index is same as SAMP index:
1485 */
1486 sview = tgsi_inst->Src[samp].Register.Index;
1487
1488 if (op == nir_texop_lod) {
1489 instr->dest_type = nir_type_float;
1490 } else if (sview < c->num_samp_types) {
1491 instr->dest_type = c->samp_types[sview];
1492 } else {
1493 instr->dest_type = nir_type_float;
1494 }
1495
1496 nir_variable *var =
1497 get_sampler_var(c, sview, instr->sampler_dim,
1498 instr->is_shadow,
1499 instr->is_array,
1500 base_type_for_alu_type(instr->dest_type));
1501
1502 nir_deref_instr *deref = nir_build_deref_var(b, var);
1503
1504 unsigned src_number = 0;
1505
1506 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1507 instr->src[src_number].src_type = nir_tex_src_texture_deref;
1508 src_number++;
1509 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1510 instr->src[src_number].src_type = nir_tex_src_sampler_deref;
1511 src_number++;
1512
1513 instr->src[src_number].src =
1514 nir_src_for_ssa(nir_swizzle(b, src[0], SWIZ(X, Y, Z, W),
1515 instr->coord_components));
1516 instr->src[src_number].src_type = nir_tex_src_coord;
1517 src_number++;
1518
1519 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1520 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1521 instr->src[src_number].src_type = nir_tex_src_projector;
1522 src_number++;
1523 }
1524
1525 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
1526 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1527 instr->src[src_number].src_type = nir_tex_src_bias;
1528 src_number++;
1529 }
1530
1531 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB2) {
1532 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1533 instr->src[src_number].src_type = nir_tex_src_bias;
1534 src_number++;
1535 }
1536
1537 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
1538 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ) {
1539 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ)
1540 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1541 else
1542 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1543 instr->src[src_number].src_type = nir_tex_src_lod;
1544 src_number++;
1545 }
1546
1547 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
1548 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1549 instr->src[src_number].src_type = nir_tex_src_lod;
1550 src_number++;
1551 }
1552
1553 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF ||
1554 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ) {
1555 if (op == nir_texop_txf_ms) {
1556 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1557 instr->src[src_number].src_type = nir_tex_src_ms_index;
1558 } else {
1559 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ)
1560 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1561 else
1562 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1563 instr->src[src_number].src_type = nir_tex_src_lod;
1564 }
1565 src_number++;
1566 }
1567
1568 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
1569 instr->src[src_number].src_type = nir_tex_src_ddx;
1570 instr->src[src_number].src =
1571 nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1572 nir_tex_instr_src_size(instr, src_number)));
1573 src_number++;
1574 instr->src[src_number].src_type = nir_tex_src_ddy;
1575 instr->src[src_number].src =
1576 nir_src_for_ssa(nir_swizzle(b, src[2], SWIZ(X, Y, Z, W),
1577 nir_tex_instr_src_size(instr, src_number)));
1578 src_number++;
1579 }
1580
1581 if (instr->is_shadow) {
1582 if (instr->coord_components == 4)
1583 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1584 else if (instr->coord_components == 3)
1585 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1586 else
1587 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], Z));
1588
1589 instr->src[src_number].src_type = nir_tex_src_comparator;
1590 src_number++;
1591 }
1592
1593 for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) {
1594 struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i];
1595 /* since TexOffset ins't using tgsi_full_src_register we get to
1596 * do some extra gymnastics:
1597 */
1598 nir_alu_src src;
1599
1600 memset(&src, 0, sizeof(src));
1601
1602 src.src = ttn_src_for_file_and_index(c,
1603 tex_offset->File,
1604 tex_offset->Index,
1605 NULL, NULL, NULL,
1606 true);
1607
1608 src.swizzle[0] = tex_offset->SwizzleX;
1609 src.swizzle[1] = tex_offset->SwizzleY;
1610 src.swizzle[2] = tex_offset->SwizzleZ;
1611 src.swizzle[3] = TGSI_SWIZZLE_W;
1612
1613 instr->src[src_number].src_type = nir_tex_src_offset;
1614 instr->src[src_number].src = nir_src_for_ssa(
1615 nir_mov_alu(b, src, nir_tex_instr_src_size(instr, src_number)));
1616 src_number++;
1617 }
1618
1619 assert(src_number == num_srcs);
1620 assert(src_number == instr->num_srcs);
1621
1622 nir_ssa_dest_init(&instr->instr, &instr->dest,
1623 nir_tex_instr_dest_size(instr),
1624 32, NULL);
1625 nir_builder_instr_insert(b, &instr->instr);
1626
1627 /* Resolve the writemask on the texture op. */
1628 ttn_move_dest(b, dest, &instr->dest.ssa);
1629 }
1630
1631 /* TGSI_OPCODE_TXQ is actually two distinct operations:
1632 *
1633 * dst.x = texture\_width(unit, lod)
1634 * dst.y = texture\_height(unit, lod)
1635 * dst.z = texture\_depth(unit, lod)
1636 * dst.w = texture\_levels(unit)
1637 *
1638 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels
1639 */
1640 static void
1641 ttn_txq(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1642 {
1643 nir_builder *b = &c->build;
1644 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1645 nir_tex_instr *txs, *qlv;
1646
1647 txs = nir_tex_instr_create(b->shader, 2);
1648 txs->op = nir_texop_txs;
1649 get_texture_info(tgsi_inst->Texture.Texture,
1650 &txs->sampler_dim, &txs->is_shadow, &txs->is_array);
1651
1652 qlv = nir_tex_instr_create(b->shader, 1);
1653 qlv->op = nir_texop_query_levels;
1654 get_texture_info(tgsi_inst->Texture.Texture,
1655 &qlv->sampler_dim, &qlv->is_shadow, &qlv->is_array);
1656
1657 assert(tgsi_inst->Src[1].Register.File == TGSI_FILE_SAMPLER);
1658 int tex_index = tgsi_inst->Src[1].Register.Index;
1659
1660 nir_variable *var =
1661 get_sampler_var(c, tex_index, txs->sampler_dim,
1662 txs->is_shadow,
1663 txs->is_array,
1664 base_type_for_alu_type(txs->dest_type));
1665
1666 nir_deref_instr *deref = nir_build_deref_var(b, var);
1667
1668 txs->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1669 txs->src[0].src_type = nir_tex_src_texture_deref;
1670
1671 qlv->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1672 qlv->src[0].src_type = nir_tex_src_texture_deref;
1673
1674 /* lod: */
1675 txs->src[1].src = nir_src_for_ssa(ttn_channel(b, src[0], X));
1676 txs->src[1].src_type = nir_tex_src_lod;
1677
1678 nir_ssa_dest_init(&txs->instr, &txs->dest,
1679 nir_tex_instr_dest_size(txs), 32, NULL);
1680 nir_builder_instr_insert(b, &txs->instr);
1681
1682 nir_ssa_dest_init(&qlv->instr, &qlv->dest, 1, 32, NULL);
1683 nir_builder_instr_insert(b, &qlv->instr);
1684
1685 ttn_move_dest_masked(b, dest, &txs->dest.ssa, TGSI_WRITEMASK_XYZ);
1686 ttn_move_dest_masked(b, dest, &qlv->dest.ssa, TGSI_WRITEMASK_W);
1687 }
1688
1689 static enum glsl_base_type
1690 get_image_base_type(struct tgsi_full_instruction *tgsi_inst)
1691 {
1692 const struct util_format_description *desc =
1693 util_format_description(tgsi_inst->Memory.Format);
1694
1695 if (desc->channel[0].pure_integer) {
1696 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED)
1697 return GLSL_TYPE_INT;
1698 else
1699 return GLSL_TYPE_UINT;
1700 }
1701 return GLSL_TYPE_FLOAT;
1702 }
1703
1704 static enum gl_access_qualifier
1705 get_mem_qualifier(struct tgsi_full_instruction *tgsi_inst)
1706 {
1707 enum gl_access_qualifier access = 0;
1708
1709 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_COHERENT)
1710 access |= ACCESS_COHERENT;
1711 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT)
1712 access |= ACCESS_RESTRICT;
1713 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
1714 access |= ACCESS_VOLATILE;
1715 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
1716 access |= ACCESS_STREAM_CACHE_POLICY;
1717
1718 return access;
1719 }
1720
1721 static GLenum
1722 get_image_format(struct tgsi_full_instruction *tgsi_inst)
1723 {
1724 switch (tgsi_inst->Memory.Format) {
1725 case PIPE_FORMAT_R8_UNORM:
1726 return GL_R8;
1727 case PIPE_FORMAT_R8G8_UNORM:
1728 return GL_RG8;
1729 case PIPE_FORMAT_R8G8B8A8_UNORM:
1730 return GL_RGBA8;
1731 case PIPE_FORMAT_R16_UNORM:
1732 return GL_R16;
1733 case PIPE_FORMAT_R16G16_UNORM:
1734 return GL_RG16;
1735 case PIPE_FORMAT_R16G16B16A16_UNORM:
1736 return GL_RGBA16;
1737
1738 case PIPE_FORMAT_R8_SNORM:
1739 return GL_R8_SNORM;
1740 case PIPE_FORMAT_R8G8_SNORM:
1741 return GL_RG8_SNORM;
1742 case PIPE_FORMAT_R8G8B8A8_SNORM:
1743 return GL_RGBA8_SNORM;
1744 case PIPE_FORMAT_R16_SNORM:
1745 return GL_R16_SNORM;
1746 case PIPE_FORMAT_R16G16_SNORM:
1747 return GL_RG16_SNORM;
1748 case PIPE_FORMAT_R16G16B16A16_SNORM:
1749 return GL_RGBA16_SNORM;
1750
1751 case PIPE_FORMAT_R8_UINT:
1752 return GL_R8UI;
1753 case PIPE_FORMAT_R8G8_UINT:
1754 return GL_RG8UI;
1755 case PIPE_FORMAT_R8G8B8A8_UINT:
1756 return GL_RGBA8UI;
1757 case PIPE_FORMAT_R16_UINT:
1758 return GL_R16UI;
1759 case PIPE_FORMAT_R16G16_UINT:
1760 return GL_RG16UI;
1761 case PIPE_FORMAT_R16G16B16A16_UINT:
1762 return GL_RGBA16UI;
1763 case PIPE_FORMAT_R32_UINT:
1764 return GL_R32UI;
1765 case PIPE_FORMAT_R32G32_UINT:
1766 return GL_RG32UI;
1767 case PIPE_FORMAT_R32G32B32A32_UINT:
1768 return GL_RGBA32UI;
1769
1770 case PIPE_FORMAT_R8_SINT:
1771 return GL_R8I;
1772 case PIPE_FORMAT_R8G8_SINT:
1773 return GL_RG8I;
1774 case PIPE_FORMAT_R8G8B8A8_SINT:
1775 return GL_RGBA8I;
1776 case PIPE_FORMAT_R16_SINT:
1777 return GL_R16I;
1778 case PIPE_FORMAT_R16G16_SINT:
1779 return GL_RG16I;
1780 case PIPE_FORMAT_R16G16B16A16_SINT:
1781 return GL_RGBA16I;
1782 case PIPE_FORMAT_R32_SINT:
1783 return GL_R32I;
1784 case PIPE_FORMAT_R32G32_SINT:
1785 return GL_RG32I;
1786 case PIPE_FORMAT_R32G32B32A32_SINT:
1787 return GL_RGBA32I;
1788
1789 case PIPE_FORMAT_R16_FLOAT:
1790 return GL_R16F;
1791 case PIPE_FORMAT_R16G16_FLOAT:
1792 return GL_RG16F;
1793 case PIPE_FORMAT_R16G16B16A16_FLOAT:
1794 return GL_RGBA16F;
1795 case PIPE_FORMAT_R32_FLOAT:
1796 return GL_R32F;
1797 case PIPE_FORMAT_R32G32_FLOAT:
1798 return GL_RG32F;
1799 case PIPE_FORMAT_R32G32B32A32_FLOAT:
1800 return GL_RGBA32F;
1801
1802 case PIPE_FORMAT_R11G11B10_FLOAT:
1803 return GL_R11F_G11F_B10F;
1804 case PIPE_FORMAT_R10G10B10A2_UINT:
1805 return GL_RGB10_A2UI;
1806 case PIPE_FORMAT_R10G10B10A2_UNORM:
1807 return GL_RGB10_A2;
1808
1809 default:
1810 unreachable("unhandled image format");
1811 }
1812 }
1813
1814 static void
1815 ttn_mem(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1816 {
1817 nir_builder *b = &c->build;
1818 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1819 nir_intrinsic_instr *instr = NULL;
1820 unsigned resource_index, addr_src_index, file;
1821
1822 switch (tgsi_inst->Instruction.Opcode) {
1823 case TGSI_OPCODE_LOAD:
1824 assert(!tgsi_inst->Src[0].Register.Indirect);
1825 resource_index = tgsi_inst->Src[0].Register.Index;
1826 file = tgsi_inst->Src[0].Register.File;
1827 addr_src_index = 1;
1828 break;
1829 case TGSI_OPCODE_STORE:
1830 assert(!tgsi_inst->Dst[0].Register.Indirect);
1831 resource_index = tgsi_inst->Dst[0].Register.Index;
1832 file = tgsi_inst->Dst[0].Register.File;
1833 addr_src_index = 0;
1834 break;
1835 default:
1836 unreachable("unexpected memory opcode");
1837 }
1838
1839 if (file == TGSI_FILE_BUFFER) {
1840 nir_intrinsic_op op;
1841
1842 switch (tgsi_inst->Instruction.Opcode) {
1843 case TGSI_OPCODE_LOAD:
1844 op = nir_intrinsic_load_ssbo;
1845 break;
1846 case TGSI_OPCODE_STORE:
1847 op = nir_intrinsic_store_ssbo;
1848 break;
1849 }
1850
1851 add_ssbo_var(c, resource_index);
1852
1853 instr = nir_intrinsic_instr_create(b->shader, op);
1854 instr->num_components = util_last_bit(tgsi_inst->Dst[0].Register.WriteMask);
1855 nir_intrinsic_set_access(instr, get_mem_qualifier(tgsi_inst));
1856 nir_intrinsic_set_align(instr, 4, 0);
1857
1858 unsigned i = 0;
1859 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1860 instr->src[i++] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1861 instr->num_components));
1862 instr->src[i++] = nir_src_for_ssa(nir_imm_int(b, resource_index));
1863 instr->src[i++] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], X));
1864
1865 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1866 nir_intrinsic_set_write_mask(instr, tgsi_inst->Dst[0].Register.WriteMask);
1867
1868 } else if (file == TGSI_FILE_IMAGE) {
1869 nir_intrinsic_op op;
1870
1871 switch (tgsi_inst->Instruction.Opcode) {
1872 case TGSI_OPCODE_LOAD:
1873 op = nir_intrinsic_image_deref_load;
1874 break;
1875 case TGSI_OPCODE_STORE:
1876 op = nir_intrinsic_image_deref_store;
1877 break;
1878 }
1879
1880 instr = nir_intrinsic_instr_create(b->shader, op);
1881
1882 /* Set the image variable dereference. */
1883 enum glsl_sampler_dim dim;
1884 bool is_array;
1885 get_texture_info(tgsi_inst->Memory.Texture, &dim, NULL, &is_array);
1886
1887 enum glsl_base_type base_type = get_image_base_type(tgsi_inst);
1888 enum gl_access_qualifier access = get_mem_qualifier(tgsi_inst);
1889 GLenum format = get_image_format(tgsi_inst);
1890
1891 nir_variable *image =
1892 get_image_var(c, resource_index,
1893 dim, is_array, base_type, access, format);
1894 nir_deref_instr *image_deref = nir_build_deref_var(b, image);
1895 const struct glsl_type *type = image_deref->type;
1896 unsigned coord_components = glsl_get_sampler_coordinate_components(type);
1897
1898 nir_intrinsic_set_access(instr, image_deref->var->data.image.access);
1899
1900 instr->src[0] = nir_src_for_ssa(&image_deref->dest.ssa);
1901 instr->src[1] = nir_src_for_ssa(nir_swizzle(b, src[addr_src_index],
1902 SWIZ(X, Y, Z, W),
1903 coord_components));
1904
1905 /* Set the sample argument, which is undefined for single-sample images. */
1906 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_MS) {
1907 instr->src[2] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], W));
1908 } else {
1909 instr->src[2] = nir_src_for_ssa(nir_ssa_undef(b, 1, 32));
1910 }
1911
1912 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
1913 instr->src[3] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W), 4));
1914 }
1915
1916 instr->num_components = 4;
1917 } else {
1918 unreachable("unexpected file");
1919 }
1920
1921
1922 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_LOAD) {
1923 nir_ssa_dest_init(&instr->instr, &instr->dest,
1924 util_last_bit(tgsi_inst->Dst[0].Register.WriteMask),
1925 32, NULL);
1926 nir_builder_instr_insert(b, &instr->instr);
1927 ttn_move_dest(b, dest, &instr->dest.ssa);
1928 } else {
1929 nir_builder_instr_insert(b, &instr->instr);
1930 }
1931 }
1932
1933 static const nir_op op_trans[TGSI_OPCODE_LAST] = {
1934 [TGSI_OPCODE_ARL] = 0,
1935 [TGSI_OPCODE_MOV] = nir_op_mov,
1936 [TGSI_OPCODE_LIT] = 0,
1937 [TGSI_OPCODE_RCP] = nir_op_frcp,
1938 [TGSI_OPCODE_RSQ] = nir_op_frsq,
1939 [TGSI_OPCODE_EXP] = 0,
1940 [TGSI_OPCODE_LOG] = 0,
1941 [TGSI_OPCODE_MUL] = nir_op_fmul,
1942 [TGSI_OPCODE_ADD] = nir_op_fadd,
1943 [TGSI_OPCODE_DP3] = 0,
1944 [TGSI_OPCODE_DP4] = 0,
1945 [TGSI_OPCODE_DST] = 0,
1946 [TGSI_OPCODE_MIN] = nir_op_fmin,
1947 [TGSI_OPCODE_MAX] = nir_op_fmax,
1948 [TGSI_OPCODE_SLT] = nir_op_slt,
1949 [TGSI_OPCODE_SGE] = nir_op_sge,
1950 [TGSI_OPCODE_MAD] = nir_op_ffma,
1951 [TGSI_OPCODE_TEX_LZ] = 0,
1952 [TGSI_OPCODE_LRP] = 0,
1953 [TGSI_OPCODE_SQRT] = nir_op_fsqrt,
1954 [TGSI_OPCODE_FRC] = nir_op_ffract,
1955 [TGSI_OPCODE_TXF_LZ] = 0,
1956 [TGSI_OPCODE_FLR] = nir_op_ffloor,
1957 [TGSI_OPCODE_ROUND] = nir_op_fround_even,
1958 [TGSI_OPCODE_EX2] = nir_op_fexp2,
1959 [TGSI_OPCODE_LG2] = nir_op_flog2,
1960 [TGSI_OPCODE_POW] = nir_op_fpow,
1961 [TGSI_OPCODE_COS] = nir_op_fcos,
1962 [TGSI_OPCODE_DDX] = nir_op_fddx,
1963 [TGSI_OPCODE_DDY] = nir_op_fddy,
1964 [TGSI_OPCODE_KILL] = 0,
1965 [TGSI_OPCODE_PK2H] = 0, /* XXX */
1966 [TGSI_OPCODE_PK2US] = 0, /* XXX */
1967 [TGSI_OPCODE_PK4B] = 0, /* XXX */
1968 [TGSI_OPCODE_PK4UB] = 0, /* XXX */
1969 [TGSI_OPCODE_SEQ] = nir_op_seq,
1970 [TGSI_OPCODE_SGT] = 0,
1971 [TGSI_OPCODE_SIN] = nir_op_fsin,
1972 [TGSI_OPCODE_SNE] = nir_op_sne,
1973 [TGSI_OPCODE_SLE] = 0,
1974 [TGSI_OPCODE_TEX] = 0,
1975 [TGSI_OPCODE_TXD] = 0,
1976 [TGSI_OPCODE_TXP] = 0,
1977 [TGSI_OPCODE_UP2H] = 0, /* XXX */
1978 [TGSI_OPCODE_UP2US] = 0, /* XXX */
1979 [TGSI_OPCODE_UP4B] = 0, /* XXX */
1980 [TGSI_OPCODE_UP4UB] = 0, /* XXX */
1981 [TGSI_OPCODE_ARR] = 0,
1982
1983 /* No function calls, yet. */
1984 [TGSI_OPCODE_CAL] = 0, /* XXX */
1985 [TGSI_OPCODE_RET] = 0, /* XXX */
1986
1987 [TGSI_OPCODE_SSG] = nir_op_fsign,
1988 [TGSI_OPCODE_CMP] = 0,
1989 [TGSI_OPCODE_TXB] = 0,
1990 [TGSI_OPCODE_DIV] = nir_op_fdiv,
1991 [TGSI_OPCODE_DP2] = 0,
1992 [TGSI_OPCODE_TXL] = 0,
1993
1994 [TGSI_OPCODE_BRK] = 0,
1995 [TGSI_OPCODE_IF] = 0,
1996 [TGSI_OPCODE_UIF] = 0,
1997 [TGSI_OPCODE_ELSE] = 0,
1998 [TGSI_OPCODE_ENDIF] = 0,
1999
2000 [TGSI_OPCODE_DDX_FINE] = nir_op_fddx_fine,
2001 [TGSI_OPCODE_DDY_FINE] = nir_op_fddy_fine,
2002
2003 [TGSI_OPCODE_CEIL] = nir_op_fceil,
2004 [TGSI_OPCODE_I2F] = nir_op_i2f32,
2005 [TGSI_OPCODE_NOT] = nir_op_inot,
2006 [TGSI_OPCODE_TRUNC] = nir_op_ftrunc,
2007 [TGSI_OPCODE_SHL] = nir_op_ishl,
2008 [TGSI_OPCODE_AND] = nir_op_iand,
2009 [TGSI_OPCODE_OR] = nir_op_ior,
2010 [TGSI_OPCODE_MOD] = nir_op_umod,
2011 [TGSI_OPCODE_XOR] = nir_op_ixor,
2012 [TGSI_OPCODE_TXF] = 0,
2013 [TGSI_OPCODE_TXQ] = 0,
2014
2015 [TGSI_OPCODE_CONT] = 0,
2016
2017 [TGSI_OPCODE_EMIT] = 0, /* XXX */
2018 [TGSI_OPCODE_ENDPRIM] = 0, /* XXX */
2019
2020 [TGSI_OPCODE_BGNLOOP] = 0,
2021 [TGSI_OPCODE_BGNSUB] = 0, /* XXX: no function calls */
2022 [TGSI_OPCODE_ENDLOOP] = 0,
2023 [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */
2024
2025 [TGSI_OPCODE_NOP] = 0,
2026 [TGSI_OPCODE_FSEQ] = nir_op_feq,
2027 [TGSI_OPCODE_FSGE] = nir_op_fge,
2028 [TGSI_OPCODE_FSLT] = nir_op_flt,
2029 [TGSI_OPCODE_FSNE] = nir_op_fne,
2030
2031 [TGSI_OPCODE_KILL_IF] = 0,
2032
2033 [TGSI_OPCODE_END] = 0,
2034
2035 [TGSI_OPCODE_F2I] = nir_op_f2i32,
2036 [TGSI_OPCODE_IDIV] = nir_op_idiv,
2037 [TGSI_OPCODE_IMAX] = nir_op_imax,
2038 [TGSI_OPCODE_IMIN] = nir_op_imin,
2039 [TGSI_OPCODE_INEG] = nir_op_ineg,
2040 [TGSI_OPCODE_ISGE] = nir_op_ige,
2041 [TGSI_OPCODE_ISHR] = nir_op_ishr,
2042 [TGSI_OPCODE_ISLT] = nir_op_ilt,
2043 [TGSI_OPCODE_F2U] = nir_op_f2u32,
2044 [TGSI_OPCODE_U2F] = nir_op_u2f32,
2045 [TGSI_OPCODE_UADD] = nir_op_iadd,
2046 [TGSI_OPCODE_UDIV] = nir_op_udiv,
2047 [TGSI_OPCODE_UMAD] = 0,
2048 [TGSI_OPCODE_UMAX] = nir_op_umax,
2049 [TGSI_OPCODE_UMIN] = nir_op_umin,
2050 [TGSI_OPCODE_UMOD] = nir_op_umod,
2051 [TGSI_OPCODE_UMUL] = nir_op_imul,
2052 [TGSI_OPCODE_USEQ] = nir_op_ieq,
2053 [TGSI_OPCODE_USGE] = nir_op_uge,
2054 [TGSI_OPCODE_USHR] = nir_op_ushr,
2055 [TGSI_OPCODE_USLT] = nir_op_ult,
2056 [TGSI_OPCODE_USNE] = nir_op_ine,
2057
2058 [TGSI_OPCODE_SWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
2059 [TGSI_OPCODE_CASE] = 0, /* not emitted by glsl_to_tgsi.cpp */
2060 [TGSI_OPCODE_DEFAULT] = 0, /* not emitted by glsl_to_tgsi.cpp */
2061 [TGSI_OPCODE_ENDSWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
2062
2063 /* XXX: SAMPLE opcodes */
2064
2065 [TGSI_OPCODE_UARL] = nir_op_mov,
2066 [TGSI_OPCODE_UCMP] = 0,
2067 [TGSI_OPCODE_IABS] = nir_op_iabs,
2068 [TGSI_OPCODE_ISSG] = nir_op_isign,
2069
2070 [TGSI_OPCODE_LOAD] = 0,
2071 [TGSI_OPCODE_STORE] = 0,
2072
2073 /* XXX: atomics */
2074
2075 [TGSI_OPCODE_TEX2] = 0,
2076 [TGSI_OPCODE_TXB2] = 0,
2077 [TGSI_OPCODE_TXL2] = 0,
2078
2079 [TGSI_OPCODE_IMUL_HI] = nir_op_imul_high,
2080 [TGSI_OPCODE_UMUL_HI] = nir_op_umul_high,
2081
2082 [TGSI_OPCODE_TG4] = 0,
2083 [TGSI_OPCODE_LODQ] = 0,
2084
2085 [TGSI_OPCODE_IBFE] = nir_op_ibitfield_extract,
2086 [TGSI_OPCODE_UBFE] = nir_op_ubitfield_extract,
2087 [TGSI_OPCODE_BFI] = nir_op_bitfield_insert,
2088 [TGSI_OPCODE_BREV] = nir_op_bitfield_reverse,
2089 [TGSI_OPCODE_POPC] = nir_op_bit_count,
2090 [TGSI_OPCODE_LSB] = nir_op_find_lsb,
2091 [TGSI_OPCODE_IMSB] = nir_op_ifind_msb,
2092 [TGSI_OPCODE_UMSB] = nir_op_ufind_msb,
2093
2094 [TGSI_OPCODE_INTERP_CENTROID] = 0, /* XXX */
2095 [TGSI_OPCODE_INTERP_SAMPLE] = 0, /* XXX */
2096 [TGSI_OPCODE_INTERP_OFFSET] = 0, /* XXX */
2097
2098 [TGSI_OPCODE_F2D] = nir_op_f2f64,
2099 [TGSI_OPCODE_D2F] = nir_op_f2f32,
2100 [TGSI_OPCODE_DMUL] = nir_op_fmul,
2101 [TGSI_OPCODE_D2U] = nir_op_f2u32,
2102 [TGSI_OPCODE_U2D] = nir_op_u2f64,
2103
2104 [TGSI_OPCODE_U64ADD] = nir_op_iadd,
2105 [TGSI_OPCODE_U64MUL] = nir_op_imul,
2106 [TGSI_OPCODE_U64DIV] = nir_op_udiv,
2107 [TGSI_OPCODE_U64SNE] = nir_op_ine,
2108 };
2109
2110 static void
2111 ttn_emit_instruction(struct ttn_compile *c)
2112 {
2113 nir_builder *b = &c->build;
2114 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
2115 unsigned i;
2116 unsigned tgsi_op = tgsi_inst->Instruction.Opcode;
2117 struct tgsi_full_dst_register *tgsi_dst = &tgsi_inst->Dst[0];
2118
2119 if (tgsi_op == TGSI_OPCODE_END)
2120 return;
2121
2122 nir_ssa_def *src[TGSI_FULL_MAX_SRC_REGISTERS];
2123 for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) {
2124 src[i] = ttn_get_src(c, &tgsi_inst->Src[i], i);
2125 }
2126 nir_alu_dest dest = ttn_get_dest(c, tgsi_dst);
2127
2128 unsigned tgsi_dst_type = tgsi_opcode_infer_dst_type(tgsi_op, 0);
2129
2130 /* The destination bitsize of the NIR opcode (not TGSI, where it's always
2131 * 32 bits). This needs to be passed into ttn_alu() because it can't be
2132 * inferred for comparison opcodes.
2133 */
2134 unsigned dst_bitsize = tgsi_type_is_64bit(tgsi_dst_type) ? 64 : 32;
2135
2136 switch (tgsi_op) {
2137 case TGSI_OPCODE_RSQ:
2138 ttn_move_dest(b, dest, nir_frsq(b, ttn_channel(b, src[0], X)));
2139 break;
2140
2141 case TGSI_OPCODE_SQRT:
2142 ttn_move_dest(b, dest, nir_fsqrt(b, ttn_channel(b, src[0], X)));
2143 break;
2144
2145 case TGSI_OPCODE_RCP:
2146 ttn_move_dest(b, dest, nir_frcp(b, ttn_channel(b, src[0], X)));
2147 break;
2148
2149 case TGSI_OPCODE_EX2:
2150 ttn_move_dest(b, dest, nir_fexp2(b, ttn_channel(b, src[0], X)));
2151 break;
2152
2153 case TGSI_OPCODE_LG2:
2154 ttn_move_dest(b, dest, nir_flog2(b, ttn_channel(b, src[0], X)));
2155 break;
2156
2157 case TGSI_OPCODE_POW:
2158 ttn_move_dest(b, dest, nir_fpow(b,
2159 ttn_channel(b, src[0], X),
2160 ttn_channel(b, src[1], X)));
2161 break;
2162
2163 case TGSI_OPCODE_COS:
2164 ttn_move_dest(b, dest, nir_fcos(b, ttn_channel(b, src[0], X)));
2165 break;
2166
2167 case TGSI_OPCODE_SIN:
2168 ttn_move_dest(b, dest, nir_fsin(b, ttn_channel(b, src[0], X)));
2169 break;
2170
2171 case TGSI_OPCODE_ARL:
2172 ttn_arl(b, op_trans[tgsi_op], dest, src);
2173 break;
2174
2175 case TGSI_OPCODE_EXP:
2176 ttn_exp(b, op_trans[tgsi_op], dest, src);
2177 break;
2178
2179 case TGSI_OPCODE_LOG:
2180 ttn_log(b, op_trans[tgsi_op], dest, src);
2181 break;
2182
2183 case TGSI_OPCODE_DST:
2184 ttn_dst(b, op_trans[tgsi_op], dest, src);
2185 break;
2186
2187 case TGSI_OPCODE_LIT:
2188 ttn_lit(b, op_trans[tgsi_op], dest, src);
2189 break;
2190
2191 case TGSI_OPCODE_DP2:
2192 ttn_dp2(b, op_trans[tgsi_op], dest, src);
2193 break;
2194
2195 case TGSI_OPCODE_DP3:
2196 ttn_dp3(b, op_trans[tgsi_op], dest, src);
2197 break;
2198
2199 case TGSI_OPCODE_DP4:
2200 ttn_dp4(b, op_trans[tgsi_op], dest, src);
2201 break;
2202
2203 case TGSI_OPCODE_UMAD:
2204 ttn_umad(b, op_trans[tgsi_op], dest, src);
2205 break;
2206
2207 case TGSI_OPCODE_LRP:
2208 ttn_move_dest(b, dest, nir_flrp(b, src[2], src[1], src[0]));
2209 break;
2210
2211 case TGSI_OPCODE_KILL:
2212 ttn_kill(b, op_trans[tgsi_op], dest, src);
2213 break;
2214
2215 case TGSI_OPCODE_ARR:
2216 ttn_arr(b, op_trans[tgsi_op], dest, src);
2217 break;
2218
2219 case TGSI_OPCODE_CMP:
2220 ttn_cmp(b, op_trans[tgsi_op], dest, src);
2221 break;
2222
2223 case TGSI_OPCODE_UCMP:
2224 ttn_ucmp(b, op_trans[tgsi_op], dest, src);
2225 break;
2226
2227 case TGSI_OPCODE_SGT:
2228 ttn_sgt(b, op_trans[tgsi_op], dest, src);
2229 break;
2230
2231 case TGSI_OPCODE_SLE:
2232 ttn_sle(b, op_trans[tgsi_op], dest, src);
2233 break;
2234
2235 case TGSI_OPCODE_KILL_IF:
2236 ttn_kill_if(b, op_trans[tgsi_op], dest, src);
2237 break;
2238
2239 case TGSI_OPCODE_TEX:
2240 case TGSI_OPCODE_TEX_LZ:
2241 case TGSI_OPCODE_TXP:
2242 case TGSI_OPCODE_TXL:
2243 case TGSI_OPCODE_TXB:
2244 case TGSI_OPCODE_TXD:
2245 case TGSI_OPCODE_TEX2:
2246 case TGSI_OPCODE_TXL2:
2247 case TGSI_OPCODE_TXB2:
2248 case TGSI_OPCODE_TXF:
2249 case TGSI_OPCODE_TXF_LZ:
2250 case TGSI_OPCODE_TG4:
2251 case TGSI_OPCODE_LODQ:
2252 ttn_tex(c, dest, src);
2253 break;
2254
2255 case TGSI_OPCODE_TXQ:
2256 ttn_txq(c, dest, src);
2257 break;
2258
2259 case TGSI_OPCODE_LOAD:
2260 case TGSI_OPCODE_STORE:
2261 ttn_mem(c, dest, src);
2262 break;
2263
2264 case TGSI_OPCODE_NOP:
2265 break;
2266
2267 case TGSI_OPCODE_IF:
2268 ttn_if(c, src[0], false);
2269 break;
2270
2271 case TGSI_OPCODE_UIF:
2272 ttn_if(c, src[0], true);
2273 break;
2274
2275 case TGSI_OPCODE_ELSE:
2276 ttn_else(c);
2277 break;
2278
2279 case TGSI_OPCODE_ENDIF:
2280 ttn_endif(c);
2281 break;
2282
2283 case TGSI_OPCODE_BGNLOOP:
2284 ttn_bgnloop(c);
2285 break;
2286
2287 case TGSI_OPCODE_BRK:
2288 ttn_brk(b);
2289 break;
2290
2291 case TGSI_OPCODE_CONT:
2292 ttn_cont(b);
2293 break;
2294
2295 case TGSI_OPCODE_ENDLOOP:
2296 ttn_endloop(c);
2297 break;
2298
2299 default:
2300 if (op_trans[tgsi_op] != 0 || tgsi_op == TGSI_OPCODE_MOV) {
2301 ttn_alu(b, op_trans[tgsi_op], dest, dst_bitsize, src);
2302 } else {
2303 fprintf(stderr, "unknown TGSI opcode: %s\n",
2304 tgsi_get_opcode_name(tgsi_op));
2305 abort();
2306 }
2307 break;
2308 }
2309
2310 if (tgsi_inst->Instruction.Saturate) {
2311 assert(!dest.dest.is_ssa);
2312 ttn_move_dest(b, dest, nir_fsat(b, ttn_src_for_dest(b, &dest)));
2313 }
2314
2315 /* if the dst has a matching var, append store_var to move
2316 * output from reg to var
2317 */
2318 nir_variable *var = ttn_get_var(c, tgsi_dst);
2319 if (var) {
2320 unsigned index = tgsi_dst->Register.Index;
2321 unsigned offset = c->temp_regs[index].offset;
2322 struct tgsi_ind_register *indirect = tgsi_dst->Register.Indirect ?
2323 &tgsi_dst->Indirect : NULL;
2324 nir_src val = nir_src_for_reg(dest.dest.reg.reg);
2325 nir_store_deref(b, ttn_array_deref(c, var, offset, indirect),
2326 nir_ssa_for_src(b, val, 4), dest.write_mask);
2327 }
2328 }
2329
2330 /**
2331 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
2332 * variables at the end of the shader.
2333 *
2334 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
2335 * written, because there's no output load intrinsic, which means we couldn't
2336 * handle writemasks.
2337 */
2338 static void
2339 ttn_add_output_stores(struct ttn_compile *c)
2340 {
2341 nir_builder *b = &c->build;
2342
2343 for (int i = 0; i < c->build.shader->num_outputs; i++) {
2344 nir_variable *var = c->outputs[i];
2345 if (!var)
2346 continue;
2347
2348 nir_src src = nir_src_for_reg(c->output_regs[i].reg);
2349 src.reg.base_offset = c->output_regs[i].offset;
2350
2351 nir_ssa_def *store_value = nir_ssa_for_src(b, src, 4);
2352 if (c->build.shader->info.stage == MESA_SHADER_FRAGMENT) {
2353 /* TGSI uses TGSI_SEMANTIC_POSITION.z for the depth output
2354 * and TGSI_SEMANTIC_STENCIL.y for the stencil output,
2355 * while NIR uses a single-component output.
2356 */
2357 if (var->data.location == FRAG_RESULT_DEPTH)
2358 store_value = nir_channel(b, store_value, 2);
2359 else if (var->data.location == FRAG_RESULT_STENCIL)
2360 store_value = nir_channel(b, store_value, 1);
2361 }
2362
2363 nir_store_deref(b, nir_build_deref_var(b, var), store_value,
2364 (1 << store_value->num_components) - 1);
2365 }
2366 }
2367
2368 /**
2369 * Parses the given TGSI tokens.
2370 */
2371 static void
2372 ttn_parse_tgsi(struct ttn_compile *c, const void *tgsi_tokens)
2373 {
2374 struct tgsi_parse_context parser;
2375 int ret;
2376
2377 ret = tgsi_parse_init(&parser, tgsi_tokens);
2378 assert(ret == TGSI_PARSE_OK);
2379
2380 while (!tgsi_parse_end_of_tokens(&parser)) {
2381 tgsi_parse_token(&parser);
2382 c->token = &parser.FullToken;
2383
2384 switch (parser.FullToken.Token.Type) {
2385 case TGSI_TOKEN_TYPE_DECLARATION:
2386 ttn_emit_declaration(c);
2387 break;
2388
2389 case TGSI_TOKEN_TYPE_INSTRUCTION:
2390 ttn_emit_instruction(c);
2391 break;
2392
2393 case TGSI_TOKEN_TYPE_IMMEDIATE:
2394 ttn_emit_immediate(c);
2395 break;
2396 }
2397 }
2398
2399 tgsi_parse_free(&parser);
2400 }
2401
2402 static void
2403 ttn_read_pipe_caps(struct ttn_compile *c,
2404 struct pipe_screen *screen)
2405 {
2406 c->cap_scalar = screen->get_shader_param(screen, c->scan->processor, PIPE_SHADER_CAP_SCALAR_ISA);
2407 c->cap_packed_uniforms = screen->get_param(screen, PIPE_CAP_PACKED_UNIFORMS);
2408 c->cap_samplers_as_deref = screen->get_param(screen, PIPE_CAP_NIR_SAMPLERS_AS_DEREF);
2409 c->cap_face_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL);
2410 c->cap_position_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL);
2411 c->cap_point_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL);
2412 }
2413
2414 /**
2415 * Initializes a TGSI-to-NIR compiler.
2416 */
2417 static struct ttn_compile *
2418 ttn_compile_init(const void *tgsi_tokens,
2419 const nir_shader_compiler_options *options,
2420 struct pipe_screen *screen)
2421 {
2422 struct ttn_compile *c;
2423 struct nir_shader *s;
2424 struct tgsi_shader_info scan;
2425
2426 assert(options || screen);
2427 c = rzalloc(NULL, struct ttn_compile);
2428
2429 tgsi_scan_shader(tgsi_tokens, &scan);
2430 c->scan = &scan;
2431
2432 if (!options) {
2433 options =
2434 screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR, scan.processor);
2435 }
2436
2437 nir_builder_init_simple_shader(&c->build, NULL,
2438 tgsi_processor_to_shader_stage(scan.processor),
2439 options);
2440
2441 s = c->build.shader;
2442
2443 if (screen) {
2444 ttn_read_pipe_caps(c, screen);
2445 } else {
2446 /* TTN used to be hard coded to always make FACE a sysval,
2447 * so it makes sense to preserve that behavior so users don't break. */
2448 c->cap_face_is_sysval = true;
2449 }
2450
2451 if (s->info.stage == MESA_SHADER_FRAGMENT)
2452 s->info.fs.untyped_color_outputs = true;
2453
2454 s->num_inputs = scan.file_max[TGSI_FILE_INPUT] + 1;
2455 s->num_uniforms = scan.const_file_max[0] + 1;
2456 s->num_outputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
2457
2458 for (unsigned i = 0; i < TGSI_PROPERTY_COUNT; i++) {
2459 unsigned value = scan.properties[i];
2460
2461 switch (i) {
2462 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
2463 break; /* handled in ttn_emit_declaration */
2464 case TGSI_PROPERTY_FS_COORD_ORIGIN:
2465 s->info.fs.origin_upper_left = value == TGSI_FS_COORD_ORIGIN_UPPER_LEFT;
2466 break;
2467 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
2468 s->info.fs.pixel_center_integer = value == TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
2469 break;
2470 case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
2471 s->info.fs.depth_layout = ttn_get_depth_layout(value);
2472 break;
2473 case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION:
2474 s->info.vs.window_space_position = value;
2475 break;
2476 case TGSI_PROPERTY_NEXT_SHADER:
2477 s->info.next_stage = tgsi_processor_to_shader_stage(value);
2478 break;
2479 case TGSI_PROPERTY_VS_BLIT_SGPRS_AMD:
2480 s->info.vs.blit_sgprs_amd = value;
2481 break;
2482 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH:
2483 s->info.cs.local_size[0] = value;
2484 break;
2485 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT:
2486 s->info.cs.local_size[1] = value;
2487 break;
2488 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH:
2489 s->info.cs.local_size[2] = value;
2490 break;
2491 case TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD:
2492 s->info.cs.user_data_components_amd = value;
2493 break;
2494 default:
2495 if (value) {
2496 fprintf(stderr, "tgsi_to_nir: unhandled TGSI property %u = %u\n",
2497 i, value);
2498 unreachable("unhandled TGSI property");
2499 }
2500 }
2501 }
2502
2503 if (s->info.stage == MESA_SHADER_COMPUTE &&
2504 (!s->info.cs.local_size[0] ||
2505 !s->info.cs.local_size[1] ||
2506 !s->info.cs.local_size[2]))
2507 s->info.cs.local_size_variable = true;
2508
2509 c->inputs = rzalloc_array(c, struct nir_variable *, s->num_inputs);
2510 c->outputs = rzalloc_array(c, struct nir_variable *, s->num_outputs);
2511
2512 c->output_regs = rzalloc_array(c, struct ttn_reg_info,
2513 scan.file_max[TGSI_FILE_OUTPUT] + 1);
2514 c->temp_regs = rzalloc_array(c, struct ttn_reg_info,
2515 scan.file_max[TGSI_FILE_TEMPORARY] + 1);
2516 c->imm_defs = rzalloc_array(c, nir_ssa_def *,
2517 scan.file_max[TGSI_FILE_IMMEDIATE] + 1);
2518
2519 c->num_samp_types = scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1;
2520 c->samp_types = rzalloc_array(c, nir_alu_type, c->num_samp_types);
2521
2522 c->if_stack = rzalloc_array(c, nir_cursor,
2523 (scan.opcode_count[TGSI_OPCODE_IF] +
2524 scan.opcode_count[TGSI_OPCODE_UIF]) * 2);
2525 c->loop_stack = rzalloc_array(c, nir_cursor,
2526 scan.opcode_count[TGSI_OPCODE_BGNLOOP]);
2527
2528
2529 ttn_parse_tgsi(c, tgsi_tokens);
2530 ttn_add_output_stores(c);
2531
2532 nir_validate_shader(c->build.shader, "TTN: after parsing TGSI and creating the NIR shader");
2533
2534 return c;
2535 }
2536
2537 static void
2538 ttn_optimize_nir(nir_shader *nir, bool scalar)
2539 {
2540 bool progress;
2541 do {
2542 progress = false;
2543
2544 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2545
2546 if (scalar) {
2547 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
2548 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
2549 }
2550
2551 NIR_PASS_V(nir, nir_lower_alu);
2552 NIR_PASS_V(nir, nir_lower_pack);
2553 NIR_PASS(progress, nir, nir_copy_prop);
2554 NIR_PASS(progress, nir, nir_opt_remove_phis);
2555 NIR_PASS(progress, nir, nir_opt_dce);
2556
2557 if (nir_opt_trivial_continues(nir)) {
2558 progress = true;
2559 NIR_PASS(progress, nir, nir_copy_prop);
2560 NIR_PASS(progress, nir, nir_opt_dce);
2561 }
2562
2563 NIR_PASS(progress, nir, nir_opt_if, false);
2564 NIR_PASS(progress, nir, nir_opt_dead_cf);
2565 NIR_PASS(progress, nir, nir_opt_cse);
2566 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
2567
2568 NIR_PASS(progress, nir, nir_opt_algebraic);
2569 NIR_PASS(progress, nir, nir_opt_constant_folding);
2570
2571 NIR_PASS(progress, nir, nir_opt_undef);
2572 NIR_PASS(progress, nir, nir_opt_conditional_discard);
2573
2574 if (nir->options->max_unroll_iterations) {
2575 NIR_PASS(progress, nir, nir_opt_loop_unroll, (nir_variable_mode)0);
2576 }
2577
2578 } while (progress);
2579
2580 }
2581
2582 /**
2583 * Finalizes the NIR in a similar way as st_glsl_to_nir does.
2584 *
2585 * Drivers expect that these passes are already performed,
2586 * so we have to do it here too.
2587 */
2588 static void
2589 ttn_finalize_nir(struct ttn_compile *c)
2590 {
2591 struct nir_shader *nir = c->build.shader;
2592
2593 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2594 NIR_PASS_V(nir, nir_lower_regs_to_ssa);
2595
2596 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2597 NIR_PASS_V(nir, nir_split_var_copies);
2598 NIR_PASS_V(nir, nir_lower_var_copies);
2599 NIR_PASS_V(nir, nir_lower_system_values);
2600
2601 if (c->cap_packed_uniforms)
2602 NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, 16);
2603
2604 if (c->cap_samplers_as_deref)
2605 NIR_PASS_V(nir, gl_nir_lower_samplers_as_deref, NULL);
2606 else
2607 NIR_PASS_V(nir, gl_nir_lower_samplers, NULL);
2608
2609 ttn_optimize_nir(nir, c->cap_scalar);
2610 nir_shader_gather_info(nir, c->build.impl);
2611 nir_validate_shader(nir, "TTN: after all optimizations");
2612 }
2613
2614 struct nir_shader *
2615 tgsi_to_nir(const void *tgsi_tokens,
2616 struct pipe_screen *screen)
2617 {
2618 struct ttn_compile *c;
2619 struct nir_shader *s;
2620
2621 c = ttn_compile_init(tgsi_tokens, NULL, screen);
2622 s = c->build.shader;
2623 ttn_finalize_nir(c);
2624 ralloc_free(c);
2625
2626 return s;
2627 }
2628
2629 struct nir_shader *
2630 tgsi_to_nir_noscreen(const void *tgsi_tokens,
2631 const nir_shader_compiler_options *options)
2632 {
2633 struct ttn_compile *c;
2634 struct nir_shader *s;
2635
2636 c = ttn_compile_init(tgsi_tokens, options, NULL);
2637 s = c->build.shader;
2638 ralloc_free(c);
2639
2640 return s;
2641 }
2642