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tgsi_to_nir: fix masked out image loads
[mesa.git] / src / gallium / auxiliary / nir / tgsi_to_nir.c
1 /*
2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/ralloc.h"
26 #include "pipe/p_screen.h"
27
28 #include "compiler/nir/nir.h"
29 #include "compiler/nir/nir_control_flow.h"
30 #include "compiler/nir/nir_builder.h"
31 #include "compiler/shader_enums.h"
32
33 #include "tgsi_to_nir.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "tgsi/tgsi_info.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_from_mesa.h"
39
40 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
41 TGSI_SWIZZLE_##X, \
42 TGSI_SWIZZLE_##Y, \
43 TGSI_SWIZZLE_##Z, \
44 TGSI_SWIZZLE_##W, \
45 }
46
47 struct ttn_reg_info {
48 /** nir register containing this TGSI index. */
49 nir_register *reg;
50 nir_variable *var;
51 /** Offset (in vec4s) from the start of var for this TGSI index. */
52 int offset;
53 };
54
55 struct ttn_compile {
56 union tgsi_full_token *token;
57 nir_builder build;
58 struct tgsi_shader_info *scan;
59
60 struct ttn_reg_info *output_regs;
61 struct ttn_reg_info *temp_regs;
62 nir_ssa_def **imm_defs;
63
64 unsigned num_samp_types;
65 nir_alu_type *samp_types;
66
67 nir_register *addr_reg;
68
69 nir_variable **inputs;
70 nir_variable **outputs;
71 nir_variable *samplers[PIPE_MAX_SAMPLERS];
72 nir_variable *images[PIPE_MAX_SHADER_IMAGES];
73 nir_variable *ssbo[PIPE_MAX_SHADER_BUFFERS];
74
75 nir_variable *input_var_face;
76 nir_variable *input_var_position;
77 nir_variable *input_var_point;
78
79 /**
80 * Stack of nir_cursors where instructions should be pushed as we pop
81 * back out of the control flow stack.
82 *
83 * For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else
84 * instructions should be placed, and if_stack[if_stack_pos - 1] has where
85 * the next instructions outside of the if/then/else block go.
86 */
87 nir_cursor *if_stack;
88 unsigned if_stack_pos;
89
90 /**
91 * Stack of nir_cursors where instructions should be pushed as we pop
92 * back out of the control flow stack.
93 *
94 * loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside
95 * of the loop.
96 */
97 nir_cursor *loop_stack;
98 unsigned loop_stack_pos;
99
100 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
101 unsigned next_imm;
102
103 bool cap_scalar;
104 bool cap_face_is_sysval;
105 bool cap_position_is_sysval;
106 bool cap_point_is_sysval;
107 bool cap_packed_uniforms;
108 bool cap_samplers_as_deref;
109 };
110
111 #define ttn_swizzle(b, src, x, y, z, w) \
112 nir_swizzle(b, src, SWIZ(x, y, z, w), 4)
113 #define ttn_channel(b, src, swiz) \
114 nir_channel(b, src, TGSI_SWIZZLE_##swiz)
115
116 static gl_varying_slot
117 tgsi_varying_semantic_to_slot(unsigned semantic, unsigned index)
118 {
119 switch (semantic) {
120 case TGSI_SEMANTIC_POSITION:
121 return VARYING_SLOT_POS;
122 case TGSI_SEMANTIC_COLOR:
123 if (index == 0)
124 return VARYING_SLOT_COL0;
125 else
126 return VARYING_SLOT_COL1;
127 case TGSI_SEMANTIC_BCOLOR:
128 if (index == 0)
129 return VARYING_SLOT_BFC0;
130 else
131 return VARYING_SLOT_BFC1;
132 case TGSI_SEMANTIC_FOG:
133 return VARYING_SLOT_FOGC;
134 case TGSI_SEMANTIC_PSIZE:
135 return VARYING_SLOT_PSIZ;
136 case TGSI_SEMANTIC_GENERIC:
137 assert(index < 32);
138 return VARYING_SLOT_VAR0 + index;
139 case TGSI_SEMANTIC_FACE:
140 return VARYING_SLOT_FACE;
141 case TGSI_SEMANTIC_EDGEFLAG:
142 return VARYING_SLOT_EDGE;
143 case TGSI_SEMANTIC_PRIMID:
144 return VARYING_SLOT_PRIMITIVE_ID;
145 case TGSI_SEMANTIC_CLIPDIST:
146 if (index == 0)
147 return VARYING_SLOT_CLIP_DIST0;
148 else
149 return VARYING_SLOT_CLIP_DIST1;
150 case TGSI_SEMANTIC_CLIPVERTEX:
151 return VARYING_SLOT_CLIP_VERTEX;
152 case TGSI_SEMANTIC_TEXCOORD:
153 assert(index < 8);
154 return VARYING_SLOT_TEX0 + index;
155 case TGSI_SEMANTIC_PCOORD:
156 return VARYING_SLOT_PNTC;
157 case TGSI_SEMANTIC_VIEWPORT_INDEX:
158 return VARYING_SLOT_VIEWPORT;
159 case TGSI_SEMANTIC_LAYER:
160 return VARYING_SLOT_LAYER;
161 case TGSI_SEMANTIC_TESSINNER:
162 return VARYING_SLOT_TESS_LEVEL_INNER;
163 case TGSI_SEMANTIC_TESSOUTER:
164 return VARYING_SLOT_TESS_LEVEL_OUTER;
165 default:
166 fprintf(stderr, "Bad TGSI semantic: %d/%d\n", semantic, index);
167 abort();
168 }
169 }
170
171 static enum gl_frag_depth_layout
172 ttn_get_depth_layout(unsigned tgsi_fs_depth_layout)
173 {
174 switch (tgsi_fs_depth_layout) {
175 case TGSI_FS_DEPTH_LAYOUT_NONE:
176 return FRAG_DEPTH_LAYOUT_NONE;
177 case TGSI_FS_DEPTH_LAYOUT_ANY:
178 return FRAG_DEPTH_LAYOUT_ANY;
179 case TGSI_FS_DEPTH_LAYOUT_GREATER:
180 return FRAG_DEPTH_LAYOUT_GREATER;
181 case TGSI_FS_DEPTH_LAYOUT_LESS:
182 return FRAG_DEPTH_LAYOUT_LESS;
183 case TGSI_FS_DEPTH_LAYOUT_UNCHANGED:
184 return FRAG_DEPTH_LAYOUT_UNCHANGED;
185 default:
186 unreachable("bad TGSI FS depth layout");
187 }
188 }
189
190 static nir_ssa_def *
191 ttn_src_for_dest(nir_builder *b, nir_alu_dest *dest)
192 {
193 nir_alu_src src;
194 memset(&src, 0, sizeof(src));
195
196 if (dest->dest.is_ssa)
197 src.src = nir_src_for_ssa(&dest->dest.ssa);
198 else {
199 assert(!dest->dest.reg.indirect);
200 src.src = nir_src_for_reg(dest->dest.reg.reg);
201 src.src.reg.base_offset = dest->dest.reg.base_offset;
202 }
203
204 for (int i = 0; i < 4; i++)
205 src.swizzle[i] = i;
206
207 return nir_mov_alu(b, src, 4);
208 }
209
210 static enum glsl_interp_mode
211 ttn_translate_interp_mode(unsigned tgsi_interp)
212 {
213 switch (tgsi_interp) {
214 case TGSI_INTERPOLATE_CONSTANT:
215 return INTERP_MODE_FLAT;
216 case TGSI_INTERPOLATE_LINEAR:
217 return INTERP_MODE_NOPERSPECTIVE;
218 case TGSI_INTERPOLATE_PERSPECTIVE:
219 return INTERP_MODE_SMOOTH;
220 case TGSI_INTERPOLATE_COLOR:
221 return INTERP_MODE_NONE;
222 default:
223 unreachable("bad TGSI interpolation mode");
224 }
225 }
226
227 static void
228 ttn_emit_declaration(struct ttn_compile *c)
229 {
230 nir_builder *b = &c->build;
231 struct tgsi_full_declaration *decl = &c->token->FullDeclaration;
232 unsigned array_size = decl->Range.Last - decl->Range.First + 1;
233 unsigned file = decl->Declaration.File;
234 unsigned i;
235
236 if (file == TGSI_FILE_TEMPORARY) {
237 if (decl->Declaration.Array) {
238 /* for arrays, we create variables instead of registers: */
239 nir_variable *var = rzalloc(b->shader, nir_variable);
240
241 var->type = glsl_array_type(glsl_vec4_type(), array_size, 0);
242 var->data.mode = nir_var_shader_temp;
243 var->name = ralloc_asprintf(var, "arr_%d", decl->Array.ArrayID);
244
245 exec_list_push_tail(&b->shader->globals, &var->node);
246
247 for (i = 0; i < array_size; i++) {
248 /* point all the matching slots to the same var,
249 * with appropriate offset set, mostly just so
250 * we know what to do when tgsi does a non-indirect
251 * access
252 */
253 c->temp_regs[decl->Range.First + i].reg = NULL;
254 c->temp_regs[decl->Range.First + i].var = var;
255 c->temp_regs[decl->Range.First + i].offset = i;
256 }
257 } else {
258 for (i = 0; i < array_size; i++) {
259 nir_register *reg = nir_local_reg_create(b->impl);
260 reg->num_components = 4;
261 c->temp_regs[decl->Range.First + i].reg = reg;
262 c->temp_regs[decl->Range.First + i].var = NULL;
263 c->temp_regs[decl->Range.First + i].offset = 0;
264 }
265 }
266 } else if (file == TGSI_FILE_ADDRESS) {
267 c->addr_reg = nir_local_reg_create(b->impl);
268 c->addr_reg->num_components = 4;
269 } else if (file == TGSI_FILE_SYSTEM_VALUE) {
270 /* Nothing to record for system values. */
271 } else if (file == TGSI_FILE_BUFFER) {
272 /* Nothing to record for buffers. */
273 } else if (file == TGSI_FILE_IMAGE) {
274 /* Nothing to record for images. */
275 } else if (file == TGSI_FILE_SAMPLER) {
276 /* Nothing to record for samplers. */
277 } else if (file == TGSI_FILE_SAMPLER_VIEW) {
278 struct tgsi_declaration_sampler_view *sview = &decl->SamplerView;
279 nir_alu_type type;
280
281 assert((sview->ReturnTypeX == sview->ReturnTypeY) &&
282 (sview->ReturnTypeX == sview->ReturnTypeZ) &&
283 (sview->ReturnTypeX == sview->ReturnTypeW));
284
285 switch (sview->ReturnTypeX) {
286 case TGSI_RETURN_TYPE_SINT:
287 type = nir_type_int;
288 break;
289 case TGSI_RETURN_TYPE_UINT:
290 type = nir_type_uint;
291 break;
292 case TGSI_RETURN_TYPE_FLOAT:
293 default:
294 type = nir_type_float;
295 break;
296 }
297
298 for (i = 0; i < array_size; i++) {
299 c->samp_types[decl->Range.First + i] = type;
300 }
301 } else {
302 bool is_array = (array_size > 1);
303
304 assert(file == TGSI_FILE_INPUT ||
305 file == TGSI_FILE_OUTPUT ||
306 file == TGSI_FILE_CONSTANT);
307
308 /* nothing to do for UBOs: */
309 if ((file == TGSI_FILE_CONSTANT) && decl->Declaration.Dimension &&
310 decl->Dim.Index2D != 0) {
311 b->shader->info.num_ubos =
312 MAX2(b->shader->info.num_ubos, decl->Dim.Index2D);
313 return;
314 }
315
316 if ((file == TGSI_FILE_INPUT) || (file == TGSI_FILE_OUTPUT)) {
317 is_array = (is_array && decl->Declaration.Array &&
318 (decl->Array.ArrayID != 0));
319 }
320
321 for (i = 0; i < array_size; i++) {
322 unsigned idx = decl->Range.First + i;
323 nir_variable *var = rzalloc(b->shader, nir_variable);
324
325 var->data.driver_location = idx;
326
327 var->type = glsl_vec4_type();
328 if (is_array)
329 var->type = glsl_array_type(var->type, array_size, 0);
330
331 switch (file) {
332 case TGSI_FILE_INPUT:
333 var->data.read_only = true;
334 var->data.mode = nir_var_shader_in;
335 var->name = ralloc_asprintf(var, "in_%d", idx);
336
337 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
338 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
339 var->type = glsl_bool_type();
340 if (c->cap_face_is_sysval) {
341 var->data.mode = nir_var_system_value;
342 var->data.location = SYSTEM_VALUE_FRONT_FACE;
343 } else {
344 var->data.location = VARYING_SLOT_FACE;
345 }
346 c->input_var_face = var;
347 } else if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
348 if (c->cap_position_is_sysval) {
349 var->data.mode = nir_var_system_value;
350 var->data.location = SYSTEM_VALUE_FRAG_COORD;
351 } else {
352 var->data.location = VARYING_SLOT_POS;
353 }
354 c->input_var_position = var;
355 } else if (decl->Semantic.Name == TGSI_SEMANTIC_PCOORD) {
356 if (c->cap_point_is_sysval) {
357 var->data.mode = nir_var_system_value;
358 var->data.location = SYSTEM_VALUE_POINT_COORD;
359 } else {
360 var->data.location = VARYING_SLOT_PNTC;
361 }
362 c->input_var_point = var;
363 } else {
364 var->data.location =
365 tgsi_varying_semantic_to_slot(decl->Semantic.Name,
366 decl->Semantic.Index);
367 }
368 } else {
369 assert(!decl->Declaration.Semantic);
370 var->data.location = VERT_ATTRIB_GENERIC0 + idx;
371 }
372 var->data.index = 0;
373 var->data.interpolation =
374 ttn_translate_interp_mode(decl->Interp.Interpolate);
375
376 exec_list_push_tail(&b->shader->inputs, &var->node);
377 c->inputs[idx] = var;
378
379 for (int i = 0; i < array_size; i++)
380 b->shader->info.inputs_read |= 1 << (var->data.location + i);
381
382 break;
383 case TGSI_FILE_OUTPUT: {
384 int semantic_name = decl->Semantic.Name;
385 int semantic_index = decl->Semantic.Index;
386 /* Since we can't load from outputs in the IR, we make temporaries
387 * for the outputs and emit stores to the real outputs at the end of
388 * the shader.
389 */
390 nir_register *reg = nir_local_reg_create(b->impl);
391 reg->num_components = 4;
392 if (is_array)
393 reg->num_array_elems = array_size;
394
395 var->data.mode = nir_var_shader_out;
396 var->name = ralloc_asprintf(var, "out_%d", idx);
397 var->data.index = 0;
398 var->data.interpolation =
399 ttn_translate_interp_mode(decl->Interp.Interpolate);
400 var->data.patch = semantic_name == TGSI_SEMANTIC_TESSINNER ||
401 semantic_name == TGSI_SEMANTIC_TESSOUTER ||
402 semantic_name == TGSI_SEMANTIC_PATCH;
403
404 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
405 switch (semantic_name) {
406 case TGSI_SEMANTIC_COLOR: {
407 /* TODO tgsi loses some information, so we cannot
408 * actually differentiate here between DSB and MRT
409 * at this point. But so far no drivers using tgsi-
410 * to-nir support dual source blend:
411 */
412 bool dual_src_blend = false;
413 if (dual_src_blend && (semantic_index == 1)) {
414 var->data.location = FRAG_RESULT_DATA0;
415 var->data.index = 1;
416 } else {
417 if (c->scan->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
418 var->data.location = FRAG_RESULT_COLOR;
419 else
420 var->data.location = FRAG_RESULT_DATA0 + semantic_index;
421 }
422 break;
423 }
424 case TGSI_SEMANTIC_POSITION:
425 var->data.location = FRAG_RESULT_DEPTH;
426 var->type = glsl_float_type();
427 break;
428 case TGSI_SEMANTIC_STENCIL:
429 var->data.location = FRAG_RESULT_STENCIL;
430 var->type = glsl_int_type();
431 break;
432 default:
433 fprintf(stderr, "Bad TGSI semantic: %d/%d\n",
434 decl->Semantic.Name, decl->Semantic.Index);
435 abort();
436 }
437 } else {
438 var->data.location =
439 tgsi_varying_semantic_to_slot(semantic_name, semantic_index);
440 if (var->data.location == VARYING_SLOT_FOGC ||
441 var->data.location == VARYING_SLOT_PSIZ) {
442 var->type = glsl_float_type();
443 }
444 }
445
446 if (is_array) {
447 unsigned j;
448 for (j = 0; j < array_size; j++) {
449 c->output_regs[idx + j].offset = i + j;
450 c->output_regs[idx + j].reg = reg;
451 }
452 } else {
453 c->output_regs[idx].offset = i;
454 c->output_regs[idx].reg = reg;
455 }
456
457 exec_list_push_tail(&b->shader->outputs, &var->node);
458 c->outputs[idx] = var;
459
460 for (int i = 0; i < array_size; i++)
461 b->shader->info.outputs_written |= 1ull << (var->data.location + i);
462 }
463 break;
464 case TGSI_FILE_CONSTANT:
465 var->data.mode = nir_var_uniform;
466 var->name = ralloc_asprintf(var, "uniform_%d", idx);
467 var->data.location = idx;
468
469 exec_list_push_tail(&b->shader->uniforms, &var->node);
470 break;
471 default:
472 unreachable("bad declaration file");
473 return;
474 }
475
476 if (is_array)
477 break;
478 }
479
480 }
481 }
482
483 static void
484 ttn_emit_immediate(struct ttn_compile *c)
485 {
486 nir_builder *b = &c->build;
487 struct tgsi_full_immediate *tgsi_imm = &c->token->FullImmediate;
488 nir_load_const_instr *load_const;
489 int i;
490
491 load_const = nir_load_const_instr_create(b->shader, 4, 32);
492 c->imm_defs[c->next_imm] = &load_const->def;
493 c->next_imm++;
494
495 for (i = 0; i < load_const->def.num_components; i++)
496 load_const->value[i].u32 = tgsi_imm->u[i].Uint;
497
498 nir_builder_instr_insert(b, &load_const->instr);
499 }
500
501 static nir_ssa_def *
502 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect);
503
504 /* generate either a constant or indirect deref chain for accessing an
505 * array variable.
506 */
507 static nir_deref_instr *
508 ttn_array_deref(struct ttn_compile *c, nir_variable *var, unsigned offset,
509 struct tgsi_ind_register *indirect)
510 {
511 nir_deref_instr *deref = nir_build_deref_var(&c->build, var);
512 nir_ssa_def *index = nir_imm_int(&c->build, offset);
513 if (indirect)
514 index = nir_iadd(&c->build, index, ttn_src_for_indirect(c, indirect));
515 return nir_build_deref_array(&c->build, deref, index);
516 }
517
518 /* Special case: Turn the frontface varying into a load of the
519 * frontface variable, and create the vector as required by TGSI.
520 */
521 static nir_ssa_def *
522 ttn_emulate_tgsi_front_face(struct ttn_compile *c)
523 {
524 nir_ssa_def *tgsi_frontface[4];
525
526 if (c->cap_face_is_sysval) {
527 /* When it's a system value, it should be an integer vector: (F, 0, 0, 1)
528 * F is 0xffffffff if front-facing, 0 if not.
529 */
530
531 nir_ssa_def *frontface = nir_load_front_face(&c->build, 1);
532
533 tgsi_frontface[0] = nir_bcsel(&c->build,
534 frontface,
535 nir_imm_int(&c->build, 0xffffffff),
536 nir_imm_int(&c->build, 0));
537 tgsi_frontface[1] = nir_imm_int(&c->build, 0);
538 tgsi_frontface[2] = nir_imm_int(&c->build, 0);
539 tgsi_frontface[3] = nir_imm_int(&c->build, 1);
540 } else {
541 /* When it's an input, it should be a float vector: (F, 0.0, 0.0, 1.0)
542 * F is positive if front-facing, negative if not.
543 */
544
545 assert(c->input_var_face);
546 nir_ssa_def *frontface = nir_load_var(&c->build, c->input_var_face);
547
548 tgsi_frontface[0] = nir_bcsel(&c->build,
549 frontface,
550 nir_imm_float(&c->build, 1.0),
551 nir_imm_float(&c->build, -1.0));
552 tgsi_frontface[1] = nir_imm_float(&c->build, 0.0);
553 tgsi_frontface[2] = nir_imm_float(&c->build, 0.0);
554 tgsi_frontface[3] = nir_imm_float(&c->build, 1.0);
555 }
556
557 return nir_vec(&c->build, tgsi_frontface, 4);
558 }
559
560 static nir_src
561 ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
562 struct tgsi_ind_register *indirect,
563 struct tgsi_dimension *dim,
564 struct tgsi_ind_register *dimind,
565 bool src_is_float)
566 {
567 nir_builder *b = &c->build;
568 nir_src src;
569
570 memset(&src, 0, sizeof(src));
571
572 switch (file) {
573 case TGSI_FILE_TEMPORARY:
574 if (c->temp_regs[index].var) {
575 unsigned offset = c->temp_regs[index].offset;
576 nir_variable *var = c->temp_regs[index].var;
577 nir_ssa_def *load = nir_load_deref(&c->build,
578 ttn_array_deref(c, var, offset, indirect));
579
580 src = nir_src_for_ssa(load);
581 } else {
582 assert(!indirect);
583 src.reg.reg = c->temp_regs[index].reg;
584 }
585 assert(!dim);
586 break;
587
588 case TGSI_FILE_ADDRESS:
589 src.reg.reg = c->addr_reg;
590 assert(!dim);
591 break;
592
593 case TGSI_FILE_IMMEDIATE:
594 src = nir_src_for_ssa(c->imm_defs[index]);
595 assert(!indirect);
596 assert(!dim);
597 break;
598
599 case TGSI_FILE_SYSTEM_VALUE: {
600 nir_intrinsic_op op;
601 nir_ssa_def *load;
602
603 assert(!indirect);
604 assert(!dim);
605
606 switch (c->scan->system_value_semantic_name[index]) {
607 case TGSI_SEMANTIC_VERTEXID_NOBASE:
608 op = nir_intrinsic_load_vertex_id_zero_base;
609 load = nir_load_vertex_id_zero_base(b);
610 break;
611 case TGSI_SEMANTIC_VERTEXID:
612 op = nir_intrinsic_load_vertex_id;
613 load = nir_load_vertex_id(b);
614 break;
615 case TGSI_SEMANTIC_BASEVERTEX:
616 op = nir_intrinsic_load_base_vertex;
617 load = nir_load_base_vertex(b);
618 break;
619 case TGSI_SEMANTIC_INSTANCEID:
620 op = nir_intrinsic_load_instance_id;
621 load = nir_load_instance_id(b);
622 break;
623 case TGSI_SEMANTIC_FACE:
624 assert(c->cap_face_is_sysval);
625 op = nir_intrinsic_load_front_face;
626 load = ttn_emulate_tgsi_front_face(c);
627 break;
628 case TGSI_SEMANTIC_POSITION:
629 assert(c->cap_position_is_sysval);
630 op = nir_intrinsic_load_frag_coord;
631 load = nir_load_frag_coord(b);
632 break;
633 case TGSI_SEMANTIC_PCOORD:
634 assert(c->cap_point_is_sysval);
635 op = nir_intrinsic_load_point_coord;
636 load = nir_load_point_coord(b);
637 break;
638 case TGSI_SEMANTIC_THREAD_ID:
639 op = nir_intrinsic_load_local_invocation_id;
640 load = nir_load_local_invocation_id(b);
641 break;
642 case TGSI_SEMANTIC_BLOCK_ID:
643 op = nir_intrinsic_load_work_group_id;
644 load = nir_load_work_group_id(b);
645 break;
646 case TGSI_SEMANTIC_CS_USER_DATA_AMD:
647 op = nir_intrinsic_load_user_data_amd;
648 load = nir_load_user_data_amd(b);
649 break;
650 case TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL:
651 op = nir_intrinsic_load_tess_level_inner_default;
652 load = nir_load_tess_level_inner_default(b);
653 break;
654 case TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL:
655 op = nir_intrinsic_load_tess_level_outer_default;
656 load = nir_load_tess_level_outer_default(b);
657 break;
658 default:
659 unreachable("bad system value");
660 }
661
662 if (load->num_components == 3)
663 load = nir_swizzle(b, load, SWIZ(X, Y, Z, Z), 4);
664
665 src = nir_src_for_ssa(load);
666 b->shader->info.system_values_read |=
667 (1ull << nir_system_value_from_intrinsic(op));
668
669 break;
670 }
671
672 case TGSI_FILE_INPUT:
673 if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
674 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_FACE) {
675 assert(!c->cap_face_is_sysval && c->input_var_face);
676 return nir_src_for_ssa(ttn_emulate_tgsi_front_face(c));
677 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
678 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_POSITION) {
679 assert(!c->cap_position_is_sysval && c->input_var_position);
680 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_position));
681 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
682 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_PCOORD) {
683 assert(!c->cap_point_is_sysval && c->input_var_point);
684 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_point));
685 } else {
686 /* Indirection on input arrays isn't supported by TTN. */
687 assert(!dim);
688 nir_deref_instr *deref = nir_build_deref_var(&c->build,
689 c->inputs[index]);
690 return nir_src_for_ssa(nir_load_deref(&c->build, deref));
691 }
692 break;
693
694 case TGSI_FILE_CONSTANT: {
695 nir_intrinsic_instr *load;
696 nir_intrinsic_op op;
697 unsigned srcn = 0;
698
699 if (dim && (dim->Index > 0 || dim->Indirect)) {
700 op = nir_intrinsic_load_ubo;
701 } else {
702 op = nir_intrinsic_load_uniform;
703 }
704
705 load = nir_intrinsic_instr_create(b->shader, op);
706 if (op == nir_intrinsic_load_uniform) {
707 nir_intrinsic_set_type(load, src_is_float ? nir_type_float :
708 nir_type_int);
709 }
710
711 load->num_components = 4;
712 if (dim && (dim->Index > 0 || dim->Indirect)) {
713 if (dimind) {
714 load->src[srcn] =
715 ttn_src_for_file_and_index(c, dimind->File, dimind->Index,
716 NULL, NULL, NULL, false);
717 } else {
718 /* UBOs start at index 1 in TGSI: */
719 load->src[srcn] =
720 nir_src_for_ssa(nir_imm_int(b, dim->Index - 1));
721 }
722 srcn++;
723 }
724
725 nir_ssa_def *offset;
726 if (op == nir_intrinsic_load_ubo) {
727 /* UBO loads don't have a base offset. */
728 offset = nir_imm_int(b, index);
729 if (indirect) {
730 offset = nir_iadd(b, offset, ttn_src_for_indirect(c, indirect));
731 }
732 /* UBO offsets are in bytes, but TGSI gives them to us in vec4's */
733 offset = nir_ishl(b, offset, nir_imm_int(b, 4));
734 } else {
735 nir_intrinsic_set_base(load, index);
736 if (indirect) {
737 offset = ttn_src_for_indirect(c, indirect);
738 } else {
739 offset = nir_imm_int(b, 0);
740 }
741 }
742 load->src[srcn++] = nir_src_for_ssa(offset);
743
744 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
745 nir_builder_instr_insert(b, &load->instr);
746
747 src = nir_src_for_ssa(&load->dest.ssa);
748 break;
749 }
750
751 default:
752 unreachable("bad src file");
753 }
754
755
756 return src;
757 }
758
759 static nir_ssa_def *
760 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect)
761 {
762 nir_builder *b = &c->build;
763 nir_alu_src src;
764 memset(&src, 0, sizeof(src));
765 for (int i = 0; i < 4; i++)
766 src.swizzle[i] = indirect->Swizzle;
767 src.src = ttn_src_for_file_and_index(c,
768 indirect->File,
769 indirect->Index,
770 NULL, NULL, NULL,
771 false);
772 return nir_mov_alu(b, src, 1);
773 }
774
775 static nir_alu_dest
776 ttn_get_dest(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
777 {
778 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
779 nir_alu_dest dest;
780 unsigned index = tgsi_dst->Index;
781
782 memset(&dest, 0, sizeof(dest));
783
784 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
785 if (c->temp_regs[index].var) {
786 nir_register *reg;
787
788 /* this works, because TGSI will give us a base offset
789 * (in case of indirect index) that points back into
790 * the array. Access can be direct or indirect, we
791 * don't really care. Just create a one-shot dst reg
792 * that will get store_var'd back into the array var
793 * at the end of ttn_emit_instruction()
794 */
795 reg = nir_local_reg_create(c->build.impl);
796 reg->num_components = 4;
797 dest.dest.reg.reg = reg;
798 dest.dest.reg.base_offset = 0;
799 } else {
800 assert(!tgsi_dst->Indirect);
801 dest.dest.reg.reg = c->temp_regs[index].reg;
802 dest.dest.reg.base_offset = c->temp_regs[index].offset;
803 }
804 } else if (tgsi_dst->File == TGSI_FILE_OUTPUT) {
805 dest.dest.reg.reg = c->output_regs[index].reg;
806 dest.dest.reg.base_offset = c->output_regs[index].offset;
807 } else if (tgsi_dst->File == TGSI_FILE_ADDRESS) {
808 assert(index == 0);
809 dest.dest.reg.reg = c->addr_reg;
810 }
811
812 dest.write_mask = tgsi_dst->WriteMask;
813 dest.saturate = false;
814
815 if (tgsi_dst->Indirect && (tgsi_dst->File != TGSI_FILE_TEMPORARY)) {
816 nir_src *indirect = ralloc(c->build.shader, nir_src);
817 *indirect = nir_src_for_ssa(ttn_src_for_indirect(c, &tgsi_fdst->Indirect));
818 dest.dest.reg.indirect = indirect;
819 }
820
821 return dest;
822 }
823
824 static nir_variable *
825 ttn_get_var(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
826 {
827 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
828 unsigned index = tgsi_dst->Index;
829
830 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
831 /* we should not have an indirect when there is no var! */
832 if (!c->temp_regs[index].var)
833 assert(!tgsi_dst->Indirect);
834 return c->temp_regs[index].var;
835 }
836
837 return NULL;
838 }
839
840 static nir_ssa_def *
841 ttn_get_src(struct ttn_compile *c, struct tgsi_full_src_register *tgsi_fsrc,
842 int src_idx)
843 {
844 nir_builder *b = &c->build;
845 struct tgsi_src_register *tgsi_src = &tgsi_fsrc->Register;
846 enum tgsi_opcode opcode = c->token->FullInstruction.Instruction.Opcode;
847 unsigned tgsi_src_type = tgsi_opcode_infer_src_type(opcode, src_idx);
848 bool src_is_float = (tgsi_src_type == TGSI_TYPE_FLOAT ||
849 tgsi_src_type == TGSI_TYPE_DOUBLE ||
850 tgsi_src_type == TGSI_TYPE_UNTYPED);
851 nir_alu_src src;
852
853 memset(&src, 0, sizeof(src));
854
855 if (tgsi_src->File == TGSI_FILE_NULL) {
856 return nir_imm_float(b, 0.0);
857 } else if (tgsi_src->File == TGSI_FILE_SAMPLER ||
858 tgsi_src->File == TGSI_FILE_IMAGE ||
859 tgsi_src->File == TGSI_FILE_BUFFER) {
860 /* Only the index of the resource gets used in texturing, and it will
861 * handle looking that up on its own instead of using the nir_alu_src.
862 */
863 assert(!tgsi_src->Indirect);
864 return NULL;
865 } else {
866 struct tgsi_ind_register *ind = NULL;
867 struct tgsi_dimension *dim = NULL;
868 struct tgsi_ind_register *dimind = NULL;
869 if (tgsi_src->Indirect)
870 ind = &tgsi_fsrc->Indirect;
871 if (tgsi_src->Dimension) {
872 dim = &tgsi_fsrc->Dimension;
873 if (dim->Indirect)
874 dimind = &tgsi_fsrc->DimIndirect;
875 }
876 src.src = ttn_src_for_file_and_index(c,
877 tgsi_src->File,
878 tgsi_src->Index,
879 ind, dim, dimind,
880 src_is_float);
881 }
882
883 src.swizzle[0] = tgsi_src->SwizzleX;
884 src.swizzle[1] = tgsi_src->SwizzleY;
885 src.swizzle[2] = tgsi_src->SwizzleZ;
886 src.swizzle[3] = tgsi_src->SwizzleW;
887
888 nir_ssa_def *def = nir_mov_alu(b, src, 4);
889
890 if (tgsi_type_is_64bit(tgsi_src_type))
891 def = nir_bitcast_vector(b, def, 64);
892
893 if (tgsi_src->Absolute) {
894 if (src_is_float)
895 def = nir_fabs(b, def);
896 else
897 def = nir_iabs(b, def);
898 }
899
900 if (tgsi_src->Negate) {
901 if (src_is_float)
902 def = nir_fneg(b, def);
903 else
904 def = nir_ineg(b, def);
905 }
906
907 return def;
908 }
909
910 static void
911 ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
912 nir_ssa_def *def, unsigned write_mask)
913 {
914 if (!(dest.write_mask & write_mask))
915 return;
916
917 nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
918 mov->dest = dest;
919 mov->dest.write_mask &= write_mask;
920 mov->src[0].src = nir_src_for_ssa(def);
921 for (unsigned i = def->num_components; i < 4; i++)
922 mov->src[0].swizzle[i] = def->num_components - 1;
923 nir_builder_instr_insert(b, &mov->instr);
924 }
925
926 static void
927 ttn_move_dest(nir_builder *b, nir_alu_dest dest, nir_ssa_def *def)
928 {
929 ttn_move_dest_masked(b, dest, def, TGSI_WRITEMASK_XYZW);
930 }
931
932 static void
933 ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, unsigned dest_bitsize,
934 nir_ssa_def **src)
935 {
936 nir_ssa_def *def = nir_build_alu_src_arr(b, op, src);
937 if (def->bit_size == 1)
938 def = nir_ineg(b, nir_b2i(b, def, dest_bitsize));
939 assert(def->bit_size == dest_bitsize);
940 if (dest_bitsize == 64) {
941 if (def->num_components > 2) {
942 /* 32 -> 64 bit conversion ops are supposed to only convert the first
943 * two components, and we need to truncate here to avoid creating a
944 * vec8 after bitcasting the destination.
945 */
946 def = nir_channels(b, def, 0x3);
947 }
948 def = nir_bitcast_vector(b, def, 32);
949 }
950 ttn_move_dest(b, dest, def);
951 }
952
953 static void
954 ttn_arl(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
955 {
956 ttn_move_dest(b, dest, nir_f2i32(b, nir_ffloor(b, src[0])));
957 }
958
959 /* EXP - Approximate Exponential Base 2
960 * dst.x = 2^{\lfloor src.x\rfloor}
961 * dst.y = src.x - \lfloor src.x\rfloor
962 * dst.z = 2^{src.x}
963 * dst.w = 1.0
964 */
965 static void
966 ttn_exp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
967 {
968 nir_ssa_def *srcx = ttn_channel(b, src[0], X);
969
970 ttn_move_dest_masked(b, dest, nir_fexp2(b, nir_ffloor(b, srcx)),
971 TGSI_WRITEMASK_X);
972 ttn_move_dest_masked(b, dest, nir_fsub(b, srcx, nir_ffloor(b, srcx)),
973 TGSI_WRITEMASK_Y);
974 ttn_move_dest_masked(b, dest, nir_fexp2(b, srcx), TGSI_WRITEMASK_Z);
975 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
976 }
977
978 /* LOG - Approximate Logarithm Base 2
979 * dst.x = \lfloor\log_2{|src.x|}\rfloor
980 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
981 * dst.z = \log_2{|src.x|}
982 * dst.w = 1.0
983 */
984 static void
985 ttn_log(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
986 {
987 nir_ssa_def *abs_srcx = nir_fabs(b, ttn_channel(b, src[0], X));
988 nir_ssa_def *log2 = nir_flog2(b, abs_srcx);
989
990 ttn_move_dest_masked(b, dest, nir_ffloor(b, log2), TGSI_WRITEMASK_X);
991 ttn_move_dest_masked(b, dest,
992 nir_fdiv(b, abs_srcx, nir_fexp2(b, nir_ffloor(b, log2))),
993 TGSI_WRITEMASK_Y);
994 ttn_move_dest_masked(b, dest, nir_flog2(b, abs_srcx), TGSI_WRITEMASK_Z);
995 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
996 }
997
998 /* DST - Distance Vector
999 * dst.x = 1.0
1000 * dst.y = src0.y \times src1.y
1001 * dst.z = src0.z
1002 * dst.w = src1.w
1003 */
1004 static void
1005 ttn_dst(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1006 {
1007 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_X);
1008 ttn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), TGSI_WRITEMASK_Y);
1009 ttn_move_dest_masked(b, dest, nir_mov(b, src[0]), TGSI_WRITEMASK_Z);
1010 ttn_move_dest_masked(b, dest, nir_mov(b, src[1]), TGSI_WRITEMASK_W);
1011 }
1012
1013 /* LIT - Light Coefficients
1014 * dst.x = 1.0
1015 * dst.y = max(src.x, 0.0)
1016 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
1017 * dst.w = 1.0
1018 */
1019 static void
1020 ttn_lit(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1021 {
1022 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_XW);
1023
1024 ttn_move_dest_masked(b, dest, nir_fmax(b, ttn_channel(b, src[0], X),
1025 nir_imm_float(b, 0.0)), TGSI_WRITEMASK_Y);
1026
1027 if (dest.write_mask & TGSI_WRITEMASK_Z) {
1028 nir_ssa_def *src0_y = ttn_channel(b, src[0], Y);
1029 nir_ssa_def *wclamp = nir_fmax(b, nir_fmin(b, ttn_channel(b, src[0], W),
1030 nir_imm_float(b, 128.0)),
1031 nir_imm_float(b, -128.0));
1032 nir_ssa_def *pow = nir_fpow(b, nir_fmax(b, src0_y, nir_imm_float(b, 0.0)),
1033 wclamp);
1034
1035 ttn_move_dest_masked(b, dest,
1036 nir_bcsel(b,
1037 nir_flt(b,
1038 ttn_channel(b, src[0], X),
1039 nir_imm_float(b, 0.0)),
1040 nir_imm_float(b, 0.0),
1041 pow),
1042 TGSI_WRITEMASK_Z);
1043 }
1044 }
1045
1046 static void
1047 ttn_sle(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1048 {
1049 ttn_move_dest(b, dest, nir_sge(b, src[1], src[0]));
1050 }
1051
1052 static void
1053 ttn_sgt(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1054 {
1055 ttn_move_dest(b, dest, nir_slt(b, src[1], src[0]));
1056 }
1057
1058 static void
1059 ttn_dp2(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1060 {
1061 ttn_move_dest(b, dest, nir_fdot2(b, src[0], src[1]));
1062 }
1063
1064 static void
1065 ttn_dp3(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1066 {
1067 ttn_move_dest(b, dest, nir_fdot3(b, src[0], src[1]));
1068 }
1069
1070 static void
1071 ttn_dp4(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1072 {
1073 ttn_move_dest(b, dest, nir_fdot4(b, src[0], src[1]));
1074 }
1075
1076 static void
1077 ttn_umad(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1078 {
1079 ttn_move_dest(b, dest, nir_iadd(b, nir_imul(b, src[0], src[1]), src[2]));
1080 }
1081
1082 static void
1083 ttn_arr(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1084 {
1085 ttn_move_dest(b, dest, nir_f2i32(b, nir_fround_even(b, src[0])));
1086 }
1087
1088 static void
1089 ttn_cmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1090 {
1091 ttn_move_dest(b, dest, nir_bcsel(b,
1092 nir_flt(b, src[0], nir_imm_float(b, 0.0)),
1093 src[1], src[2]));
1094 }
1095
1096 static void
1097 ttn_ucmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1098 {
1099 ttn_move_dest(b, dest, nir_bcsel(b,
1100 nir_ine(b, src[0], nir_imm_int(b, 0)),
1101 src[1], src[2]));
1102 }
1103
1104 static void
1105 ttn_kill(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1106 {
1107 nir_intrinsic_instr *discard =
1108 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard);
1109 nir_builder_instr_insert(b, &discard->instr);
1110 b->shader->info.fs.uses_discard = true;
1111 }
1112
1113 static void
1114 ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1115 {
1116 /* flt must be exact, because NaN shouldn't discard. (apps rely on this) */
1117 b->exact = true;
1118 nir_ssa_def *cmp = nir_bany(b, nir_flt(b, src[0], nir_imm_float(b, 0.0)));
1119 b->exact = false;
1120
1121 nir_intrinsic_instr *discard =
1122 nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard_if);
1123 discard->src[0] = nir_src_for_ssa(cmp);
1124 nir_builder_instr_insert(b, &discard->instr);
1125 b->shader->info.fs.uses_discard = true;
1126 }
1127
1128 static void
1129 ttn_if(struct ttn_compile *c, nir_ssa_def *src, bool is_uint)
1130 {
1131 nir_builder *b = &c->build;
1132 nir_ssa_def *src_x = ttn_channel(b, src, X);
1133
1134 nir_if *if_stmt = nir_if_create(b->shader);
1135 if (is_uint) {
1136 /* equivalent to TGSI UIF, src is interpreted as integer */
1137 if_stmt->condition = nir_src_for_ssa(nir_ine(b, src_x, nir_imm_int(b, 0)));
1138 } else {
1139 /* equivalent to TGSI IF, src is interpreted as float */
1140 if_stmt->condition = nir_src_for_ssa(nir_fne(b, src_x, nir_imm_float(b, 0.0)));
1141 }
1142 nir_builder_cf_insert(b, &if_stmt->cf_node);
1143
1144 c->if_stack[c->if_stack_pos] = nir_after_cf_node(&if_stmt->cf_node);
1145 c->if_stack_pos++;
1146
1147 b->cursor = nir_after_cf_list(&if_stmt->then_list);
1148
1149 c->if_stack[c->if_stack_pos] = nir_after_cf_list(&if_stmt->else_list);
1150 c->if_stack_pos++;
1151 }
1152
1153 static void
1154 ttn_else(struct ttn_compile *c)
1155 {
1156 nir_builder *b = &c->build;
1157
1158 b->cursor = c->if_stack[c->if_stack_pos - 1];
1159 }
1160
1161 static void
1162 ttn_endif(struct ttn_compile *c)
1163 {
1164 nir_builder *b = &c->build;
1165
1166 c->if_stack_pos -= 2;
1167 b->cursor = c->if_stack[c->if_stack_pos];
1168 }
1169
1170 static void
1171 ttn_bgnloop(struct ttn_compile *c)
1172 {
1173 nir_builder *b = &c->build;
1174
1175 nir_loop *loop = nir_loop_create(b->shader);
1176 nir_builder_cf_insert(b, &loop->cf_node);
1177
1178 c->loop_stack[c->loop_stack_pos] = nir_after_cf_node(&loop->cf_node);
1179 c->loop_stack_pos++;
1180
1181 b->cursor = nir_after_cf_list(&loop->body);
1182 }
1183
1184 static void
1185 ttn_cont(nir_builder *b)
1186 {
1187 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_continue);
1188 nir_builder_instr_insert(b, &instr->instr);
1189 }
1190
1191 static void
1192 ttn_brk(nir_builder *b)
1193 {
1194 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
1195 nir_builder_instr_insert(b, &instr->instr);
1196 }
1197
1198 static void
1199 ttn_endloop(struct ttn_compile *c)
1200 {
1201 nir_builder *b = &c->build;
1202
1203 c->loop_stack_pos--;
1204 b->cursor = c->loop_stack[c->loop_stack_pos];
1205 }
1206
1207 static void
1208 get_texture_info(unsigned texture,
1209 enum glsl_sampler_dim *dim,
1210 bool *is_shadow,
1211 bool *is_array)
1212 {
1213 assert(is_array);
1214 *is_array = false;
1215
1216 if (is_shadow)
1217 *is_shadow = false;
1218
1219 switch (texture) {
1220 case TGSI_TEXTURE_BUFFER:
1221 *dim = GLSL_SAMPLER_DIM_BUF;
1222 break;
1223 case TGSI_TEXTURE_1D:
1224 *dim = GLSL_SAMPLER_DIM_1D;
1225 break;
1226 case TGSI_TEXTURE_1D_ARRAY:
1227 *dim = GLSL_SAMPLER_DIM_1D;
1228 *is_array = true;
1229 break;
1230 case TGSI_TEXTURE_SHADOW1D:
1231 *dim = GLSL_SAMPLER_DIM_1D;
1232 *is_shadow = true;
1233 break;
1234 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1235 *dim = GLSL_SAMPLER_DIM_1D;
1236 *is_shadow = true;
1237 *is_array = true;
1238 break;
1239 case TGSI_TEXTURE_2D:
1240 *dim = GLSL_SAMPLER_DIM_2D;
1241 break;
1242 case TGSI_TEXTURE_2D_ARRAY:
1243 *dim = GLSL_SAMPLER_DIM_2D;
1244 *is_array = true;
1245 break;
1246 case TGSI_TEXTURE_2D_MSAA:
1247 *dim = GLSL_SAMPLER_DIM_MS;
1248 break;
1249 case TGSI_TEXTURE_2D_ARRAY_MSAA:
1250 *dim = GLSL_SAMPLER_DIM_MS;
1251 *is_array = true;
1252 break;
1253 case TGSI_TEXTURE_SHADOW2D:
1254 *dim = GLSL_SAMPLER_DIM_2D;
1255 *is_shadow = true;
1256 break;
1257 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1258 *dim = GLSL_SAMPLER_DIM_2D;
1259 *is_shadow = true;
1260 *is_array = true;
1261 break;
1262 case TGSI_TEXTURE_3D:
1263 *dim = GLSL_SAMPLER_DIM_3D;
1264 break;
1265 case TGSI_TEXTURE_CUBE:
1266 *dim = GLSL_SAMPLER_DIM_CUBE;
1267 break;
1268 case TGSI_TEXTURE_CUBE_ARRAY:
1269 *dim = GLSL_SAMPLER_DIM_CUBE;
1270 *is_array = true;
1271 break;
1272 case TGSI_TEXTURE_SHADOWCUBE:
1273 *dim = GLSL_SAMPLER_DIM_CUBE;
1274 *is_shadow = true;
1275 break;
1276 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1277 *dim = GLSL_SAMPLER_DIM_CUBE;
1278 *is_shadow = true;
1279 *is_array = true;
1280 break;
1281 case TGSI_TEXTURE_RECT:
1282 *dim = GLSL_SAMPLER_DIM_RECT;
1283 break;
1284 case TGSI_TEXTURE_SHADOWRECT:
1285 *dim = GLSL_SAMPLER_DIM_RECT;
1286 *is_shadow = true;
1287 break;
1288 default:
1289 fprintf(stderr, "Unknown TGSI texture target %d\n", texture);
1290 abort();
1291 }
1292 }
1293
1294 static enum glsl_base_type
1295 base_type_for_alu_type(nir_alu_type type)
1296 {
1297 type = nir_alu_type_get_base_type(type);
1298
1299 switch (type) {
1300 case nir_type_float:
1301 return GLSL_TYPE_FLOAT;
1302 case nir_type_int:
1303 return GLSL_TYPE_INT;
1304 case nir_type_uint:
1305 return GLSL_TYPE_UINT;
1306 default:
1307 unreachable("invalid type");
1308 }
1309 }
1310
1311 static nir_variable *
1312 get_sampler_var(struct ttn_compile *c, int binding,
1313 enum glsl_sampler_dim dim,
1314 bool is_shadow,
1315 bool is_array,
1316 enum glsl_base_type base_type,
1317 nir_texop op)
1318 {
1319 nir_variable *var = c->samplers[binding];
1320 if (!var) {
1321 const struct glsl_type *type =
1322 glsl_sampler_type(dim, is_shadow, is_array, base_type);
1323 var = nir_variable_create(c->build.shader, nir_var_uniform, type,
1324 "sampler");
1325 var->data.binding = binding;
1326 var->data.explicit_binding = true;
1327 c->samplers[binding] = var;
1328
1329 /* Record textures used */
1330 unsigned mask = 1 << binding;
1331 c->build.shader->info.textures_used |= mask;
1332 if (op == nir_texop_txf ||
1333 op == nir_texop_txf_ms ||
1334 op == nir_texop_txf_ms_mcs)
1335 c->build.shader->info.textures_used_by_txf |= mask;
1336 }
1337
1338 return var;
1339 }
1340
1341 static nir_variable *
1342 get_image_var(struct ttn_compile *c, int binding,
1343 enum glsl_sampler_dim dim,
1344 bool is_array,
1345 enum glsl_base_type base_type,
1346 enum gl_access_qualifier access,
1347 GLenum format)
1348 {
1349 nir_variable *var = c->images[binding];
1350
1351 if (!var) {
1352 const struct glsl_type *type = glsl_image_type(dim, is_array, base_type);
1353
1354 var = nir_variable_create(c->build.shader, nir_var_uniform, type, "image");
1355 var->data.binding = binding;
1356 var->data.explicit_binding = true;
1357 var->data.image.access = access;
1358 var->data.image.format = format;
1359 c->images[binding] = var;
1360 }
1361
1362 return var;
1363 }
1364
1365 static void
1366 add_ssbo_var(struct ttn_compile *c, int binding)
1367 {
1368 nir_variable *var = c->ssbo[binding];
1369
1370 if (!var) {
1371 /* A length of 0 is used to denote unsized arrays */
1372 const struct glsl_type *type = glsl_array_type(glsl_uint_type(), 0, 0);
1373
1374 struct glsl_struct_field field = {
1375 .type = type,
1376 .name = "data",
1377 .location = -1,
1378 };
1379
1380 var = nir_variable_create(c->build.shader, nir_var_mem_ssbo, type, "ssbo");
1381 var->data.binding = binding;
1382 var->interface_type =
1383 glsl_interface_type(&field, 1, GLSL_INTERFACE_PACKING_STD430,
1384 false, "data");
1385 c->ssbo[binding] = var;
1386 }
1387 }
1388
1389 static void
1390 ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1391 {
1392 nir_builder *b = &c->build;
1393 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1394 nir_tex_instr *instr;
1395 nir_texop op;
1396 unsigned num_srcs, samp = 1, sview, i;
1397
1398 switch (tgsi_inst->Instruction.Opcode) {
1399 case TGSI_OPCODE_TEX:
1400 op = nir_texop_tex;
1401 num_srcs = 1;
1402 break;
1403 case TGSI_OPCODE_TEX2:
1404 op = nir_texop_tex;
1405 num_srcs = 1;
1406 samp = 2;
1407 break;
1408 case TGSI_OPCODE_TXP:
1409 op = nir_texop_tex;
1410 num_srcs = 2;
1411 break;
1412 case TGSI_OPCODE_TXB:
1413 op = nir_texop_txb;
1414 num_srcs = 2;
1415 break;
1416 case TGSI_OPCODE_TXB2:
1417 op = nir_texop_txb;
1418 num_srcs = 2;
1419 samp = 2;
1420 break;
1421 case TGSI_OPCODE_TXL:
1422 case TGSI_OPCODE_TEX_LZ:
1423 op = nir_texop_txl;
1424 num_srcs = 2;
1425 break;
1426 case TGSI_OPCODE_TXL2:
1427 op = nir_texop_txl;
1428 num_srcs = 2;
1429 samp = 2;
1430 break;
1431 case TGSI_OPCODE_TXF:
1432 case TGSI_OPCODE_TXF_LZ:
1433 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
1434 tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1435 op = nir_texop_txf_ms;
1436 } else {
1437 op = nir_texop_txf;
1438 }
1439 num_srcs = 2;
1440 break;
1441 case TGSI_OPCODE_TXD:
1442 op = nir_texop_txd;
1443 num_srcs = 3;
1444 samp = 3;
1445 break;
1446 case TGSI_OPCODE_LODQ:
1447 op = nir_texop_lod;
1448 num_srcs = 1;
1449 break;
1450
1451 default:
1452 fprintf(stderr, "unknown TGSI tex op %d\n", tgsi_inst->Instruction.Opcode);
1453 abort();
1454 }
1455
1456 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
1457 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1458 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
1459 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1460 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
1461 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
1462 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1463 num_srcs++;
1464 }
1465
1466 /* Deref sources */
1467 num_srcs += 2;
1468
1469 num_srcs += tgsi_inst->Texture.NumOffsets;
1470
1471 instr = nir_tex_instr_create(b->shader, num_srcs);
1472 instr->op = op;
1473
1474 get_texture_info(tgsi_inst->Texture.Texture,
1475 &instr->sampler_dim, &instr->is_shadow, &instr->is_array);
1476
1477 switch (instr->sampler_dim) {
1478 case GLSL_SAMPLER_DIM_1D:
1479 case GLSL_SAMPLER_DIM_BUF:
1480 instr->coord_components = 1;
1481 break;
1482 case GLSL_SAMPLER_DIM_2D:
1483 case GLSL_SAMPLER_DIM_RECT:
1484 case GLSL_SAMPLER_DIM_EXTERNAL:
1485 case GLSL_SAMPLER_DIM_MS:
1486 instr->coord_components = 2;
1487 break;
1488 case GLSL_SAMPLER_DIM_3D:
1489 case GLSL_SAMPLER_DIM_CUBE:
1490 instr->coord_components = 3;
1491 break;
1492 case GLSL_SAMPLER_DIM_SUBPASS:
1493 case GLSL_SAMPLER_DIM_SUBPASS_MS:
1494 unreachable("invalid sampler_dim");
1495 }
1496
1497 if (instr->is_array)
1498 instr->coord_components++;
1499
1500 assert(tgsi_inst->Src[samp].Register.File == TGSI_FILE_SAMPLER);
1501
1502 /* TODO if we supported any opc's which take an explicit SVIEW
1503 * src, we would use that here instead. But for the "legacy"
1504 * texture opc's the SVIEW index is same as SAMP index:
1505 */
1506 sview = tgsi_inst->Src[samp].Register.Index;
1507
1508 if (op == nir_texop_lod) {
1509 instr->dest_type = nir_type_float;
1510 } else if (sview < c->num_samp_types) {
1511 instr->dest_type = c->samp_types[sview];
1512 } else {
1513 instr->dest_type = nir_type_float;
1514 }
1515
1516 nir_variable *var =
1517 get_sampler_var(c, sview, instr->sampler_dim,
1518 instr->is_shadow,
1519 instr->is_array,
1520 base_type_for_alu_type(instr->dest_type),
1521 op);
1522
1523 nir_deref_instr *deref = nir_build_deref_var(b, var);
1524
1525 unsigned src_number = 0;
1526
1527 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1528 instr->src[src_number].src_type = nir_tex_src_texture_deref;
1529 src_number++;
1530 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1531 instr->src[src_number].src_type = nir_tex_src_sampler_deref;
1532 src_number++;
1533
1534 instr->src[src_number].src =
1535 nir_src_for_ssa(nir_swizzle(b, src[0], SWIZ(X, Y, Z, W),
1536 instr->coord_components));
1537 instr->src[src_number].src_type = nir_tex_src_coord;
1538 src_number++;
1539
1540 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1541 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1542 instr->src[src_number].src_type = nir_tex_src_projector;
1543 src_number++;
1544 }
1545
1546 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
1547 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1548 instr->src[src_number].src_type = nir_tex_src_bias;
1549 src_number++;
1550 }
1551
1552 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB2) {
1553 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1554 instr->src[src_number].src_type = nir_tex_src_bias;
1555 src_number++;
1556 }
1557
1558 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
1559 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ) {
1560 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ)
1561 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1562 else
1563 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1564 instr->src[src_number].src_type = nir_tex_src_lod;
1565 src_number++;
1566 }
1567
1568 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
1569 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1570 instr->src[src_number].src_type = nir_tex_src_lod;
1571 src_number++;
1572 }
1573
1574 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF ||
1575 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ) {
1576 if (op == nir_texop_txf_ms) {
1577 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1578 instr->src[src_number].src_type = nir_tex_src_ms_index;
1579 } else {
1580 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ)
1581 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1582 else
1583 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1584 instr->src[src_number].src_type = nir_tex_src_lod;
1585 }
1586 src_number++;
1587 }
1588
1589 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
1590 instr->src[src_number].src_type = nir_tex_src_ddx;
1591 instr->src[src_number].src =
1592 nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1593 nir_tex_instr_src_size(instr, src_number)));
1594 src_number++;
1595 instr->src[src_number].src_type = nir_tex_src_ddy;
1596 instr->src[src_number].src =
1597 nir_src_for_ssa(nir_swizzle(b, src[2], SWIZ(X, Y, Z, W),
1598 nir_tex_instr_src_size(instr, src_number)));
1599 src_number++;
1600 }
1601
1602 if (instr->is_shadow) {
1603 if (instr->coord_components == 4)
1604 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1605 else if (instr->coord_components == 3)
1606 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1607 else
1608 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], Z));
1609
1610 instr->src[src_number].src_type = nir_tex_src_comparator;
1611 src_number++;
1612 }
1613
1614 for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) {
1615 struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i];
1616 /* since TexOffset ins't using tgsi_full_src_register we get to
1617 * do some extra gymnastics:
1618 */
1619 nir_alu_src src;
1620
1621 memset(&src, 0, sizeof(src));
1622
1623 src.src = ttn_src_for_file_and_index(c,
1624 tex_offset->File,
1625 tex_offset->Index,
1626 NULL, NULL, NULL,
1627 true);
1628
1629 src.swizzle[0] = tex_offset->SwizzleX;
1630 src.swizzle[1] = tex_offset->SwizzleY;
1631 src.swizzle[2] = tex_offset->SwizzleZ;
1632 src.swizzle[3] = TGSI_SWIZZLE_W;
1633
1634 instr->src[src_number].src_type = nir_tex_src_offset;
1635 instr->src[src_number].src = nir_src_for_ssa(
1636 nir_mov_alu(b, src, nir_tex_instr_src_size(instr, src_number)));
1637 src_number++;
1638 }
1639
1640 assert(src_number == num_srcs);
1641 assert(src_number == instr->num_srcs);
1642
1643 nir_ssa_dest_init(&instr->instr, &instr->dest,
1644 nir_tex_instr_dest_size(instr),
1645 32, NULL);
1646 nir_builder_instr_insert(b, &instr->instr);
1647
1648 /* Resolve the writemask on the texture op. */
1649 ttn_move_dest(b, dest, &instr->dest.ssa);
1650 }
1651
1652 /* TGSI_OPCODE_TXQ is actually two distinct operations:
1653 *
1654 * dst.x = texture\_width(unit, lod)
1655 * dst.y = texture\_height(unit, lod)
1656 * dst.z = texture\_depth(unit, lod)
1657 * dst.w = texture\_levels(unit)
1658 *
1659 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels
1660 */
1661 static void
1662 ttn_txq(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1663 {
1664 nir_builder *b = &c->build;
1665 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1666 nir_tex_instr *txs, *qlv;
1667
1668 txs = nir_tex_instr_create(b->shader, 2);
1669 txs->op = nir_texop_txs;
1670 get_texture_info(tgsi_inst->Texture.Texture,
1671 &txs->sampler_dim, &txs->is_shadow, &txs->is_array);
1672
1673 qlv = nir_tex_instr_create(b->shader, 1);
1674 qlv->op = nir_texop_query_levels;
1675 get_texture_info(tgsi_inst->Texture.Texture,
1676 &qlv->sampler_dim, &qlv->is_shadow, &qlv->is_array);
1677
1678 assert(tgsi_inst->Src[1].Register.File == TGSI_FILE_SAMPLER);
1679 int tex_index = tgsi_inst->Src[1].Register.Index;
1680
1681 nir_variable *var =
1682 get_sampler_var(c, tex_index, txs->sampler_dim,
1683 txs->is_shadow,
1684 txs->is_array,
1685 base_type_for_alu_type(txs->dest_type),
1686 nir_texop_txs);
1687
1688 nir_deref_instr *deref = nir_build_deref_var(b, var);
1689
1690 txs->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1691 txs->src[0].src_type = nir_tex_src_texture_deref;
1692
1693 qlv->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1694 qlv->src[0].src_type = nir_tex_src_texture_deref;
1695
1696 /* lod: */
1697 txs->src[1].src = nir_src_for_ssa(ttn_channel(b, src[0], X));
1698 txs->src[1].src_type = nir_tex_src_lod;
1699
1700 nir_ssa_dest_init(&txs->instr, &txs->dest,
1701 nir_tex_instr_dest_size(txs), 32, NULL);
1702 nir_builder_instr_insert(b, &txs->instr);
1703
1704 nir_ssa_dest_init(&qlv->instr, &qlv->dest, 1, 32, NULL);
1705 nir_builder_instr_insert(b, &qlv->instr);
1706
1707 ttn_move_dest_masked(b, dest, &txs->dest.ssa, TGSI_WRITEMASK_XYZ);
1708 ttn_move_dest_masked(b, dest, &qlv->dest.ssa, TGSI_WRITEMASK_W);
1709 }
1710
1711 static enum glsl_base_type
1712 get_image_base_type(struct tgsi_full_instruction *tgsi_inst)
1713 {
1714 const struct util_format_description *desc =
1715 util_format_description(tgsi_inst->Memory.Format);
1716
1717 if (desc->channel[0].pure_integer) {
1718 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED)
1719 return GLSL_TYPE_INT;
1720 else
1721 return GLSL_TYPE_UINT;
1722 }
1723 return GLSL_TYPE_FLOAT;
1724 }
1725
1726 static enum gl_access_qualifier
1727 get_mem_qualifier(struct tgsi_full_instruction *tgsi_inst)
1728 {
1729 enum gl_access_qualifier access = 0;
1730
1731 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_COHERENT)
1732 access |= ACCESS_COHERENT;
1733 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT)
1734 access |= ACCESS_RESTRICT;
1735 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
1736 access |= ACCESS_VOLATILE;
1737 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
1738 access |= ACCESS_STREAM_CACHE_POLICY;
1739
1740 return access;
1741 }
1742
1743 static GLenum
1744 get_image_format(struct tgsi_full_instruction *tgsi_inst)
1745 {
1746 switch (tgsi_inst->Memory.Format) {
1747 case PIPE_FORMAT_R8_UNORM:
1748 return GL_R8;
1749 case PIPE_FORMAT_R8G8_UNORM:
1750 return GL_RG8;
1751 case PIPE_FORMAT_R8G8B8A8_UNORM:
1752 return GL_RGBA8;
1753 case PIPE_FORMAT_R16_UNORM:
1754 return GL_R16;
1755 case PIPE_FORMAT_R16G16_UNORM:
1756 return GL_RG16;
1757 case PIPE_FORMAT_R16G16B16A16_UNORM:
1758 return GL_RGBA16;
1759
1760 case PIPE_FORMAT_R8_SNORM:
1761 return GL_R8_SNORM;
1762 case PIPE_FORMAT_R8G8_SNORM:
1763 return GL_RG8_SNORM;
1764 case PIPE_FORMAT_R8G8B8A8_SNORM:
1765 return GL_RGBA8_SNORM;
1766 case PIPE_FORMAT_R16_SNORM:
1767 return GL_R16_SNORM;
1768 case PIPE_FORMAT_R16G16_SNORM:
1769 return GL_RG16_SNORM;
1770 case PIPE_FORMAT_R16G16B16A16_SNORM:
1771 return GL_RGBA16_SNORM;
1772
1773 case PIPE_FORMAT_R8_UINT:
1774 return GL_R8UI;
1775 case PIPE_FORMAT_R8G8_UINT:
1776 return GL_RG8UI;
1777 case PIPE_FORMAT_R8G8B8A8_UINT:
1778 return GL_RGBA8UI;
1779 case PIPE_FORMAT_R16_UINT:
1780 return GL_R16UI;
1781 case PIPE_FORMAT_R16G16_UINT:
1782 return GL_RG16UI;
1783 case PIPE_FORMAT_R16G16B16A16_UINT:
1784 return GL_RGBA16UI;
1785 case PIPE_FORMAT_R32_UINT:
1786 return GL_R32UI;
1787 case PIPE_FORMAT_R32G32_UINT:
1788 return GL_RG32UI;
1789 case PIPE_FORMAT_R32G32B32A32_UINT:
1790 return GL_RGBA32UI;
1791
1792 case PIPE_FORMAT_R8_SINT:
1793 return GL_R8I;
1794 case PIPE_FORMAT_R8G8_SINT:
1795 return GL_RG8I;
1796 case PIPE_FORMAT_R8G8B8A8_SINT:
1797 return GL_RGBA8I;
1798 case PIPE_FORMAT_R16_SINT:
1799 return GL_R16I;
1800 case PIPE_FORMAT_R16G16_SINT:
1801 return GL_RG16I;
1802 case PIPE_FORMAT_R16G16B16A16_SINT:
1803 return GL_RGBA16I;
1804 case PIPE_FORMAT_R32_SINT:
1805 return GL_R32I;
1806 case PIPE_FORMAT_R32G32_SINT:
1807 return GL_RG32I;
1808 case PIPE_FORMAT_R32G32B32A32_SINT:
1809 return GL_RGBA32I;
1810
1811 case PIPE_FORMAT_R16_FLOAT:
1812 return GL_R16F;
1813 case PIPE_FORMAT_R16G16_FLOAT:
1814 return GL_RG16F;
1815 case PIPE_FORMAT_R16G16B16A16_FLOAT:
1816 return GL_RGBA16F;
1817 case PIPE_FORMAT_R32_FLOAT:
1818 return GL_R32F;
1819 case PIPE_FORMAT_R32G32_FLOAT:
1820 return GL_RG32F;
1821 case PIPE_FORMAT_R32G32B32A32_FLOAT:
1822 return GL_RGBA32F;
1823
1824 case PIPE_FORMAT_R11G11B10_FLOAT:
1825 return GL_R11F_G11F_B10F;
1826 case PIPE_FORMAT_R10G10B10A2_UINT:
1827 return GL_RGB10_A2UI;
1828 case PIPE_FORMAT_R10G10B10A2_UNORM:
1829 return GL_RGB10_A2;
1830
1831 default:
1832 unreachable("unhandled image format");
1833 }
1834 }
1835
1836 static void
1837 ttn_mem(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1838 {
1839 nir_builder *b = &c->build;
1840 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1841 nir_intrinsic_instr *instr = NULL;
1842 unsigned resource_index, addr_src_index, file;
1843
1844 switch (tgsi_inst->Instruction.Opcode) {
1845 case TGSI_OPCODE_LOAD:
1846 assert(!tgsi_inst->Src[0].Register.Indirect);
1847 resource_index = tgsi_inst->Src[0].Register.Index;
1848 file = tgsi_inst->Src[0].Register.File;
1849 addr_src_index = 1;
1850 break;
1851 case TGSI_OPCODE_STORE:
1852 assert(!tgsi_inst->Dst[0].Register.Indirect);
1853 resource_index = tgsi_inst->Dst[0].Register.Index;
1854 file = tgsi_inst->Dst[0].Register.File;
1855 addr_src_index = 0;
1856 break;
1857 default:
1858 unreachable("unexpected memory opcode");
1859 }
1860
1861 if (file == TGSI_FILE_BUFFER) {
1862 nir_intrinsic_op op;
1863
1864 switch (tgsi_inst->Instruction.Opcode) {
1865 case TGSI_OPCODE_LOAD:
1866 op = nir_intrinsic_load_ssbo;
1867 break;
1868 case TGSI_OPCODE_STORE:
1869 op = nir_intrinsic_store_ssbo;
1870 break;
1871 }
1872
1873 add_ssbo_var(c, resource_index);
1874
1875 instr = nir_intrinsic_instr_create(b->shader, op);
1876 instr->num_components = util_last_bit(tgsi_inst->Dst[0].Register.WriteMask);
1877 nir_intrinsic_set_access(instr, get_mem_qualifier(tgsi_inst));
1878 nir_intrinsic_set_align(instr, 4, 0);
1879
1880 unsigned i = 0;
1881 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1882 instr->src[i++] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1883 instr->num_components));
1884 instr->src[i++] = nir_src_for_ssa(nir_imm_int(b, resource_index));
1885 instr->src[i++] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], X));
1886
1887 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1888 nir_intrinsic_set_write_mask(instr, tgsi_inst->Dst[0].Register.WriteMask);
1889
1890 } else if (file == TGSI_FILE_IMAGE) {
1891 nir_intrinsic_op op;
1892
1893 switch (tgsi_inst->Instruction.Opcode) {
1894 case TGSI_OPCODE_LOAD:
1895 op = nir_intrinsic_image_deref_load;
1896 break;
1897 case TGSI_OPCODE_STORE:
1898 op = nir_intrinsic_image_deref_store;
1899 break;
1900 }
1901
1902 instr = nir_intrinsic_instr_create(b->shader, op);
1903
1904 /* Set the image variable dereference. */
1905 enum glsl_sampler_dim dim;
1906 bool is_array;
1907 get_texture_info(tgsi_inst->Memory.Texture, &dim, NULL, &is_array);
1908
1909 enum glsl_base_type base_type = get_image_base_type(tgsi_inst);
1910 enum gl_access_qualifier access = get_mem_qualifier(tgsi_inst);
1911 GLenum format = get_image_format(tgsi_inst);
1912
1913 nir_variable *image =
1914 get_image_var(c, resource_index,
1915 dim, is_array, base_type, access, format);
1916 nir_deref_instr *image_deref = nir_build_deref_var(b, image);
1917 const struct glsl_type *type = image_deref->type;
1918
1919 nir_intrinsic_set_access(instr, image_deref->var->data.image.access);
1920
1921 instr->src[0] = nir_src_for_ssa(&image_deref->dest.ssa);
1922 instr->src[1] = nir_src_for_ssa(src[addr_src_index]);
1923
1924 /* Set the sample argument, which is undefined for single-sample images. */
1925 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_MS) {
1926 instr->src[2] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], W));
1927 } else {
1928 instr->src[2] = nir_src_for_ssa(nir_ssa_undef(b, 1, 32));
1929 }
1930
1931 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
1932 instr->src[3] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W), 4));
1933 }
1934
1935 instr->num_components = 4;
1936 } else {
1937 unreachable("unexpected file");
1938 }
1939
1940
1941 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_LOAD) {
1942 nir_ssa_dest_init(&instr->instr, &instr->dest, instr->num_components,
1943 32, NULL);
1944 nir_builder_instr_insert(b, &instr->instr);
1945 ttn_move_dest(b, dest, &instr->dest.ssa);
1946 } else {
1947 nir_builder_instr_insert(b, &instr->instr);
1948 }
1949 }
1950
1951 static const nir_op op_trans[TGSI_OPCODE_LAST] = {
1952 [TGSI_OPCODE_ARL] = 0,
1953 [TGSI_OPCODE_MOV] = nir_op_mov,
1954 [TGSI_OPCODE_LIT] = 0,
1955 [TGSI_OPCODE_RCP] = nir_op_frcp,
1956 [TGSI_OPCODE_RSQ] = nir_op_frsq,
1957 [TGSI_OPCODE_EXP] = 0,
1958 [TGSI_OPCODE_LOG] = 0,
1959 [TGSI_OPCODE_MUL] = nir_op_fmul,
1960 [TGSI_OPCODE_ADD] = nir_op_fadd,
1961 [TGSI_OPCODE_DP3] = 0,
1962 [TGSI_OPCODE_DP4] = 0,
1963 [TGSI_OPCODE_DST] = 0,
1964 [TGSI_OPCODE_MIN] = nir_op_fmin,
1965 [TGSI_OPCODE_MAX] = nir_op_fmax,
1966 [TGSI_OPCODE_SLT] = nir_op_slt,
1967 [TGSI_OPCODE_SGE] = nir_op_sge,
1968 [TGSI_OPCODE_MAD] = nir_op_ffma,
1969 [TGSI_OPCODE_TEX_LZ] = 0,
1970 [TGSI_OPCODE_LRP] = 0,
1971 [TGSI_OPCODE_SQRT] = nir_op_fsqrt,
1972 [TGSI_OPCODE_FRC] = nir_op_ffract,
1973 [TGSI_OPCODE_TXF_LZ] = 0,
1974 [TGSI_OPCODE_FLR] = nir_op_ffloor,
1975 [TGSI_OPCODE_ROUND] = nir_op_fround_even,
1976 [TGSI_OPCODE_EX2] = nir_op_fexp2,
1977 [TGSI_OPCODE_LG2] = nir_op_flog2,
1978 [TGSI_OPCODE_POW] = nir_op_fpow,
1979 [TGSI_OPCODE_COS] = nir_op_fcos,
1980 [TGSI_OPCODE_DDX] = nir_op_fddx,
1981 [TGSI_OPCODE_DDY] = nir_op_fddy,
1982 [TGSI_OPCODE_KILL] = 0,
1983 [TGSI_OPCODE_PK2H] = 0, /* XXX */
1984 [TGSI_OPCODE_PK2US] = 0, /* XXX */
1985 [TGSI_OPCODE_PK4B] = 0, /* XXX */
1986 [TGSI_OPCODE_PK4UB] = 0, /* XXX */
1987 [TGSI_OPCODE_SEQ] = nir_op_seq,
1988 [TGSI_OPCODE_SGT] = 0,
1989 [TGSI_OPCODE_SIN] = nir_op_fsin,
1990 [TGSI_OPCODE_SNE] = nir_op_sne,
1991 [TGSI_OPCODE_SLE] = 0,
1992 [TGSI_OPCODE_TEX] = 0,
1993 [TGSI_OPCODE_TXD] = 0,
1994 [TGSI_OPCODE_TXP] = 0,
1995 [TGSI_OPCODE_UP2H] = 0, /* XXX */
1996 [TGSI_OPCODE_UP2US] = 0, /* XXX */
1997 [TGSI_OPCODE_UP4B] = 0, /* XXX */
1998 [TGSI_OPCODE_UP4UB] = 0, /* XXX */
1999 [TGSI_OPCODE_ARR] = 0,
2000
2001 /* No function calls, yet. */
2002 [TGSI_OPCODE_CAL] = 0, /* XXX */
2003 [TGSI_OPCODE_RET] = 0, /* XXX */
2004
2005 [TGSI_OPCODE_SSG] = nir_op_fsign,
2006 [TGSI_OPCODE_CMP] = 0,
2007 [TGSI_OPCODE_TXB] = 0,
2008 [TGSI_OPCODE_DIV] = nir_op_fdiv,
2009 [TGSI_OPCODE_DP2] = 0,
2010 [TGSI_OPCODE_TXL] = 0,
2011
2012 [TGSI_OPCODE_BRK] = 0,
2013 [TGSI_OPCODE_IF] = 0,
2014 [TGSI_OPCODE_UIF] = 0,
2015 [TGSI_OPCODE_ELSE] = 0,
2016 [TGSI_OPCODE_ENDIF] = 0,
2017
2018 [TGSI_OPCODE_DDX_FINE] = nir_op_fddx_fine,
2019 [TGSI_OPCODE_DDY_FINE] = nir_op_fddy_fine,
2020
2021 [TGSI_OPCODE_CEIL] = nir_op_fceil,
2022 [TGSI_OPCODE_I2F] = nir_op_i2f32,
2023 [TGSI_OPCODE_NOT] = nir_op_inot,
2024 [TGSI_OPCODE_TRUNC] = nir_op_ftrunc,
2025 [TGSI_OPCODE_SHL] = nir_op_ishl,
2026 [TGSI_OPCODE_AND] = nir_op_iand,
2027 [TGSI_OPCODE_OR] = nir_op_ior,
2028 [TGSI_OPCODE_MOD] = nir_op_umod,
2029 [TGSI_OPCODE_XOR] = nir_op_ixor,
2030 [TGSI_OPCODE_TXF] = 0,
2031 [TGSI_OPCODE_TXQ] = 0,
2032
2033 [TGSI_OPCODE_CONT] = 0,
2034
2035 [TGSI_OPCODE_EMIT] = 0, /* XXX */
2036 [TGSI_OPCODE_ENDPRIM] = 0, /* XXX */
2037
2038 [TGSI_OPCODE_BGNLOOP] = 0,
2039 [TGSI_OPCODE_BGNSUB] = 0, /* XXX: no function calls */
2040 [TGSI_OPCODE_ENDLOOP] = 0,
2041 [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */
2042
2043 [TGSI_OPCODE_NOP] = 0,
2044 [TGSI_OPCODE_FSEQ] = nir_op_feq,
2045 [TGSI_OPCODE_FSGE] = nir_op_fge,
2046 [TGSI_OPCODE_FSLT] = nir_op_flt,
2047 [TGSI_OPCODE_FSNE] = nir_op_fne,
2048
2049 [TGSI_OPCODE_KILL_IF] = 0,
2050
2051 [TGSI_OPCODE_END] = 0,
2052
2053 [TGSI_OPCODE_F2I] = nir_op_f2i32,
2054 [TGSI_OPCODE_IDIV] = nir_op_idiv,
2055 [TGSI_OPCODE_IMAX] = nir_op_imax,
2056 [TGSI_OPCODE_IMIN] = nir_op_imin,
2057 [TGSI_OPCODE_INEG] = nir_op_ineg,
2058 [TGSI_OPCODE_ISGE] = nir_op_ige,
2059 [TGSI_OPCODE_ISHR] = nir_op_ishr,
2060 [TGSI_OPCODE_ISLT] = nir_op_ilt,
2061 [TGSI_OPCODE_F2U] = nir_op_f2u32,
2062 [TGSI_OPCODE_U2F] = nir_op_u2f32,
2063 [TGSI_OPCODE_UADD] = nir_op_iadd,
2064 [TGSI_OPCODE_UDIV] = nir_op_udiv,
2065 [TGSI_OPCODE_UMAD] = 0,
2066 [TGSI_OPCODE_UMAX] = nir_op_umax,
2067 [TGSI_OPCODE_UMIN] = nir_op_umin,
2068 [TGSI_OPCODE_UMOD] = nir_op_umod,
2069 [TGSI_OPCODE_UMUL] = nir_op_imul,
2070 [TGSI_OPCODE_USEQ] = nir_op_ieq,
2071 [TGSI_OPCODE_USGE] = nir_op_uge,
2072 [TGSI_OPCODE_USHR] = nir_op_ushr,
2073 [TGSI_OPCODE_USLT] = nir_op_ult,
2074 [TGSI_OPCODE_USNE] = nir_op_ine,
2075
2076 [TGSI_OPCODE_SWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
2077 [TGSI_OPCODE_CASE] = 0, /* not emitted by glsl_to_tgsi.cpp */
2078 [TGSI_OPCODE_DEFAULT] = 0, /* not emitted by glsl_to_tgsi.cpp */
2079 [TGSI_OPCODE_ENDSWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
2080
2081 /* XXX: SAMPLE opcodes */
2082
2083 [TGSI_OPCODE_UARL] = nir_op_mov,
2084 [TGSI_OPCODE_UCMP] = 0,
2085 [TGSI_OPCODE_IABS] = nir_op_iabs,
2086 [TGSI_OPCODE_ISSG] = nir_op_isign,
2087
2088 [TGSI_OPCODE_LOAD] = 0,
2089 [TGSI_OPCODE_STORE] = 0,
2090
2091 /* XXX: atomics */
2092
2093 [TGSI_OPCODE_TEX2] = 0,
2094 [TGSI_OPCODE_TXB2] = 0,
2095 [TGSI_OPCODE_TXL2] = 0,
2096
2097 [TGSI_OPCODE_IMUL_HI] = nir_op_imul_high,
2098 [TGSI_OPCODE_UMUL_HI] = nir_op_umul_high,
2099
2100 [TGSI_OPCODE_TG4] = 0,
2101 [TGSI_OPCODE_LODQ] = 0,
2102
2103 [TGSI_OPCODE_IBFE] = nir_op_ibitfield_extract,
2104 [TGSI_OPCODE_UBFE] = nir_op_ubitfield_extract,
2105 [TGSI_OPCODE_BFI] = nir_op_bitfield_insert,
2106 [TGSI_OPCODE_BREV] = nir_op_bitfield_reverse,
2107 [TGSI_OPCODE_POPC] = nir_op_bit_count,
2108 [TGSI_OPCODE_LSB] = nir_op_find_lsb,
2109 [TGSI_OPCODE_IMSB] = nir_op_ifind_msb,
2110 [TGSI_OPCODE_UMSB] = nir_op_ufind_msb,
2111
2112 [TGSI_OPCODE_INTERP_CENTROID] = 0, /* XXX */
2113 [TGSI_OPCODE_INTERP_SAMPLE] = 0, /* XXX */
2114 [TGSI_OPCODE_INTERP_OFFSET] = 0, /* XXX */
2115
2116 [TGSI_OPCODE_F2D] = nir_op_f2f64,
2117 [TGSI_OPCODE_D2F] = nir_op_f2f32,
2118 [TGSI_OPCODE_DMUL] = nir_op_fmul,
2119 [TGSI_OPCODE_D2U] = nir_op_f2u32,
2120 [TGSI_OPCODE_U2D] = nir_op_u2f64,
2121
2122 [TGSI_OPCODE_U64ADD] = nir_op_iadd,
2123 [TGSI_OPCODE_U64MUL] = nir_op_imul,
2124 [TGSI_OPCODE_U64DIV] = nir_op_udiv,
2125 [TGSI_OPCODE_U64SNE] = nir_op_ine,
2126 };
2127
2128 static void
2129 ttn_emit_instruction(struct ttn_compile *c)
2130 {
2131 nir_builder *b = &c->build;
2132 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
2133 unsigned i;
2134 unsigned tgsi_op = tgsi_inst->Instruction.Opcode;
2135 struct tgsi_full_dst_register *tgsi_dst = &tgsi_inst->Dst[0];
2136
2137 if (tgsi_op == TGSI_OPCODE_END)
2138 return;
2139
2140 nir_ssa_def *src[TGSI_FULL_MAX_SRC_REGISTERS];
2141 for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) {
2142 src[i] = ttn_get_src(c, &tgsi_inst->Src[i], i);
2143 }
2144 nir_alu_dest dest = ttn_get_dest(c, tgsi_dst);
2145
2146 unsigned tgsi_dst_type = tgsi_opcode_infer_dst_type(tgsi_op, 0);
2147
2148 /* The destination bitsize of the NIR opcode (not TGSI, where it's always
2149 * 32 bits). This needs to be passed into ttn_alu() because it can't be
2150 * inferred for comparison opcodes.
2151 */
2152 unsigned dst_bitsize = tgsi_type_is_64bit(tgsi_dst_type) ? 64 : 32;
2153
2154 switch (tgsi_op) {
2155 case TGSI_OPCODE_RSQ:
2156 ttn_move_dest(b, dest, nir_frsq(b, ttn_channel(b, src[0], X)));
2157 break;
2158
2159 case TGSI_OPCODE_SQRT:
2160 ttn_move_dest(b, dest, nir_fsqrt(b, ttn_channel(b, src[0], X)));
2161 break;
2162
2163 case TGSI_OPCODE_RCP:
2164 ttn_move_dest(b, dest, nir_frcp(b, ttn_channel(b, src[0], X)));
2165 break;
2166
2167 case TGSI_OPCODE_EX2:
2168 ttn_move_dest(b, dest, nir_fexp2(b, ttn_channel(b, src[0], X)));
2169 break;
2170
2171 case TGSI_OPCODE_LG2:
2172 ttn_move_dest(b, dest, nir_flog2(b, ttn_channel(b, src[0], X)));
2173 break;
2174
2175 case TGSI_OPCODE_POW:
2176 ttn_move_dest(b, dest, nir_fpow(b,
2177 ttn_channel(b, src[0], X),
2178 ttn_channel(b, src[1], X)));
2179 break;
2180
2181 case TGSI_OPCODE_COS:
2182 ttn_move_dest(b, dest, nir_fcos(b, ttn_channel(b, src[0], X)));
2183 break;
2184
2185 case TGSI_OPCODE_SIN:
2186 ttn_move_dest(b, dest, nir_fsin(b, ttn_channel(b, src[0], X)));
2187 break;
2188
2189 case TGSI_OPCODE_ARL:
2190 ttn_arl(b, op_trans[tgsi_op], dest, src);
2191 break;
2192
2193 case TGSI_OPCODE_EXP:
2194 ttn_exp(b, op_trans[tgsi_op], dest, src);
2195 break;
2196
2197 case TGSI_OPCODE_LOG:
2198 ttn_log(b, op_trans[tgsi_op], dest, src);
2199 break;
2200
2201 case TGSI_OPCODE_DST:
2202 ttn_dst(b, op_trans[tgsi_op], dest, src);
2203 break;
2204
2205 case TGSI_OPCODE_LIT:
2206 ttn_lit(b, op_trans[tgsi_op], dest, src);
2207 break;
2208
2209 case TGSI_OPCODE_DP2:
2210 ttn_dp2(b, op_trans[tgsi_op], dest, src);
2211 break;
2212
2213 case TGSI_OPCODE_DP3:
2214 ttn_dp3(b, op_trans[tgsi_op], dest, src);
2215 break;
2216
2217 case TGSI_OPCODE_DP4:
2218 ttn_dp4(b, op_trans[tgsi_op], dest, src);
2219 break;
2220
2221 case TGSI_OPCODE_UMAD:
2222 ttn_umad(b, op_trans[tgsi_op], dest, src);
2223 break;
2224
2225 case TGSI_OPCODE_LRP:
2226 ttn_move_dest(b, dest, nir_flrp(b, src[2], src[1], src[0]));
2227 break;
2228
2229 case TGSI_OPCODE_KILL:
2230 ttn_kill(b, op_trans[tgsi_op], dest, src);
2231 break;
2232
2233 case TGSI_OPCODE_ARR:
2234 ttn_arr(b, op_trans[tgsi_op], dest, src);
2235 break;
2236
2237 case TGSI_OPCODE_CMP:
2238 ttn_cmp(b, op_trans[tgsi_op], dest, src);
2239 break;
2240
2241 case TGSI_OPCODE_UCMP:
2242 ttn_ucmp(b, op_trans[tgsi_op], dest, src);
2243 break;
2244
2245 case TGSI_OPCODE_SGT:
2246 ttn_sgt(b, op_trans[tgsi_op], dest, src);
2247 break;
2248
2249 case TGSI_OPCODE_SLE:
2250 ttn_sle(b, op_trans[tgsi_op], dest, src);
2251 break;
2252
2253 case TGSI_OPCODE_KILL_IF:
2254 ttn_kill_if(b, op_trans[tgsi_op], dest, src);
2255 break;
2256
2257 case TGSI_OPCODE_TEX:
2258 case TGSI_OPCODE_TEX_LZ:
2259 case TGSI_OPCODE_TXP:
2260 case TGSI_OPCODE_TXL:
2261 case TGSI_OPCODE_TXB:
2262 case TGSI_OPCODE_TXD:
2263 case TGSI_OPCODE_TEX2:
2264 case TGSI_OPCODE_TXL2:
2265 case TGSI_OPCODE_TXB2:
2266 case TGSI_OPCODE_TXF:
2267 case TGSI_OPCODE_TXF_LZ:
2268 case TGSI_OPCODE_TG4:
2269 case TGSI_OPCODE_LODQ:
2270 ttn_tex(c, dest, src);
2271 break;
2272
2273 case TGSI_OPCODE_TXQ:
2274 ttn_txq(c, dest, src);
2275 break;
2276
2277 case TGSI_OPCODE_LOAD:
2278 case TGSI_OPCODE_STORE:
2279 ttn_mem(c, dest, src);
2280 break;
2281
2282 case TGSI_OPCODE_NOP:
2283 break;
2284
2285 case TGSI_OPCODE_IF:
2286 ttn_if(c, src[0], false);
2287 break;
2288
2289 case TGSI_OPCODE_UIF:
2290 ttn_if(c, src[0], true);
2291 break;
2292
2293 case TGSI_OPCODE_ELSE:
2294 ttn_else(c);
2295 break;
2296
2297 case TGSI_OPCODE_ENDIF:
2298 ttn_endif(c);
2299 break;
2300
2301 case TGSI_OPCODE_BGNLOOP:
2302 ttn_bgnloop(c);
2303 break;
2304
2305 case TGSI_OPCODE_BRK:
2306 ttn_brk(b);
2307 break;
2308
2309 case TGSI_OPCODE_CONT:
2310 ttn_cont(b);
2311 break;
2312
2313 case TGSI_OPCODE_ENDLOOP:
2314 ttn_endloop(c);
2315 break;
2316
2317 default:
2318 if (op_trans[tgsi_op] != 0 || tgsi_op == TGSI_OPCODE_MOV) {
2319 ttn_alu(b, op_trans[tgsi_op], dest, dst_bitsize, src);
2320 } else {
2321 fprintf(stderr, "unknown TGSI opcode: %s\n",
2322 tgsi_get_opcode_name(tgsi_op));
2323 abort();
2324 }
2325 break;
2326 }
2327
2328 if (tgsi_inst->Instruction.Saturate) {
2329 assert(!dest.dest.is_ssa);
2330 ttn_move_dest(b, dest, nir_fsat(b, ttn_src_for_dest(b, &dest)));
2331 }
2332
2333 /* if the dst has a matching var, append store_var to move
2334 * output from reg to var
2335 */
2336 nir_variable *var = ttn_get_var(c, tgsi_dst);
2337 if (var) {
2338 unsigned index = tgsi_dst->Register.Index;
2339 unsigned offset = c->temp_regs[index].offset;
2340 struct tgsi_ind_register *indirect = tgsi_dst->Register.Indirect ?
2341 &tgsi_dst->Indirect : NULL;
2342 nir_src val = nir_src_for_reg(dest.dest.reg.reg);
2343 nir_store_deref(b, ttn_array_deref(c, var, offset, indirect),
2344 nir_ssa_for_src(b, val, 4), dest.write_mask);
2345 }
2346 }
2347
2348 /**
2349 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
2350 * variables at the end of the shader.
2351 *
2352 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
2353 * written, because there's no output load intrinsic, which means we couldn't
2354 * handle writemasks.
2355 */
2356 static void
2357 ttn_add_output_stores(struct ttn_compile *c)
2358 {
2359 nir_builder *b = &c->build;
2360
2361 for (int i = 0; i < c->build.shader->num_outputs; i++) {
2362 nir_variable *var = c->outputs[i];
2363 if (!var)
2364 continue;
2365
2366 nir_src src = nir_src_for_reg(c->output_regs[i].reg);
2367 src.reg.base_offset = c->output_regs[i].offset;
2368
2369 nir_ssa_def *store_value = nir_ssa_for_src(b, src, 4);
2370 if (c->build.shader->info.stage == MESA_SHADER_FRAGMENT) {
2371 /* TGSI uses TGSI_SEMANTIC_POSITION.z for the depth output
2372 * and TGSI_SEMANTIC_STENCIL.y for the stencil output,
2373 * while NIR uses a single-component output.
2374 */
2375 if (var->data.location == FRAG_RESULT_DEPTH)
2376 store_value = nir_channel(b, store_value, 2);
2377 else if (var->data.location == FRAG_RESULT_STENCIL)
2378 store_value = nir_channel(b, store_value, 1);
2379 } else {
2380 /* FOGC and PSIZ are scalar values */
2381 if (var->data.location == VARYING_SLOT_FOGC ||
2382 var->data.location == VARYING_SLOT_PSIZ) {
2383 store_value = nir_channel(b, store_value, 0);
2384 }
2385 }
2386
2387 nir_store_deref(b, nir_build_deref_var(b, var), store_value,
2388 (1 << store_value->num_components) - 1);
2389 }
2390 }
2391
2392 /**
2393 * Parses the given TGSI tokens.
2394 */
2395 static void
2396 ttn_parse_tgsi(struct ttn_compile *c, const void *tgsi_tokens)
2397 {
2398 struct tgsi_parse_context parser;
2399 int ret;
2400
2401 ret = tgsi_parse_init(&parser, tgsi_tokens);
2402 assert(ret == TGSI_PARSE_OK);
2403
2404 while (!tgsi_parse_end_of_tokens(&parser)) {
2405 tgsi_parse_token(&parser);
2406 c->token = &parser.FullToken;
2407
2408 switch (parser.FullToken.Token.Type) {
2409 case TGSI_TOKEN_TYPE_DECLARATION:
2410 ttn_emit_declaration(c);
2411 break;
2412
2413 case TGSI_TOKEN_TYPE_INSTRUCTION:
2414 ttn_emit_instruction(c);
2415 break;
2416
2417 case TGSI_TOKEN_TYPE_IMMEDIATE:
2418 ttn_emit_immediate(c);
2419 break;
2420 }
2421 }
2422
2423 tgsi_parse_free(&parser);
2424 }
2425
2426 static void
2427 ttn_read_pipe_caps(struct ttn_compile *c,
2428 struct pipe_screen *screen)
2429 {
2430 c->cap_scalar = screen->get_shader_param(screen, c->scan->processor, PIPE_SHADER_CAP_SCALAR_ISA);
2431 c->cap_packed_uniforms = screen->get_param(screen, PIPE_CAP_PACKED_UNIFORMS);
2432 c->cap_samplers_as_deref = screen->get_param(screen, PIPE_CAP_NIR_SAMPLERS_AS_DEREF);
2433 c->cap_face_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL);
2434 c->cap_position_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL);
2435 c->cap_point_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL);
2436 }
2437
2438 /**
2439 * Initializes a TGSI-to-NIR compiler.
2440 */
2441 static struct ttn_compile *
2442 ttn_compile_init(const void *tgsi_tokens,
2443 const nir_shader_compiler_options *options,
2444 struct pipe_screen *screen)
2445 {
2446 struct ttn_compile *c;
2447 struct nir_shader *s;
2448 struct tgsi_shader_info scan;
2449
2450 assert(options || screen);
2451 c = rzalloc(NULL, struct ttn_compile);
2452
2453 tgsi_scan_shader(tgsi_tokens, &scan);
2454 c->scan = &scan;
2455
2456 if (!options) {
2457 options =
2458 screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR, scan.processor);
2459 }
2460
2461 nir_builder_init_simple_shader(&c->build, NULL,
2462 tgsi_processor_to_shader_stage(scan.processor),
2463 options);
2464
2465 s = c->build.shader;
2466
2467 if (screen) {
2468 ttn_read_pipe_caps(c, screen);
2469 } else {
2470 /* TTN used to be hard coded to always make FACE a sysval,
2471 * so it makes sense to preserve that behavior so users don't break. */
2472 c->cap_face_is_sysval = true;
2473 }
2474
2475 if (s->info.stage == MESA_SHADER_FRAGMENT)
2476 s->info.fs.untyped_color_outputs = true;
2477
2478 s->num_inputs = scan.file_max[TGSI_FILE_INPUT] + 1;
2479 s->num_uniforms = scan.const_file_max[0] + 1;
2480 s->num_outputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
2481 s->info.num_ssbos = util_last_bit(scan.shader_buffers_declared);
2482 s->info.num_ubos = util_last_bit(scan.const_buffers_declared >> 1);
2483 s->info.num_images = util_last_bit(scan.images_declared);
2484 s->info.num_textures = util_last_bit(scan.samplers_declared);
2485
2486 for (unsigned i = 0; i < TGSI_PROPERTY_COUNT; i++) {
2487 unsigned value = scan.properties[i];
2488
2489 switch (i) {
2490 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
2491 break; /* handled in ttn_emit_declaration */
2492 case TGSI_PROPERTY_FS_COORD_ORIGIN:
2493 if (s->info.stage == MESA_SHADER_FRAGMENT)
2494 s->info.fs.origin_upper_left = value == TGSI_FS_COORD_ORIGIN_UPPER_LEFT;
2495 break;
2496 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
2497 if (s->info.stage == MESA_SHADER_FRAGMENT)
2498 s->info.fs.pixel_center_integer = value == TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
2499 break;
2500 case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
2501 if (s->info.stage == MESA_SHADER_FRAGMENT)
2502 s->info.fs.depth_layout = ttn_get_depth_layout(value);
2503 break;
2504 case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION:
2505 if (s->info.stage == MESA_SHADER_VERTEX)
2506 s->info.vs.window_space_position = value;
2507 break;
2508 case TGSI_PROPERTY_NEXT_SHADER:
2509 s->info.next_stage = tgsi_processor_to_shader_stage(value);
2510 break;
2511 case TGSI_PROPERTY_VS_BLIT_SGPRS_AMD:
2512 if (s->info.stage == MESA_SHADER_VERTEX)
2513 s->info.vs.blit_sgprs_amd = value;
2514 break;
2515 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH:
2516 if (s->info.stage == MESA_SHADER_COMPUTE)
2517 s->info.cs.local_size[0] = value;
2518 break;
2519 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT:
2520 if (s->info.stage == MESA_SHADER_COMPUTE)
2521 s->info.cs.local_size[1] = value;
2522 break;
2523 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH:
2524 if (s->info.stage == MESA_SHADER_COMPUTE)
2525 s->info.cs.local_size[2] = value;
2526 break;
2527 case TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD:
2528 if (s->info.stage == MESA_SHADER_COMPUTE)
2529 s->info.cs.user_data_components_amd = value;
2530 break;
2531 default:
2532 if (value) {
2533 fprintf(stderr, "tgsi_to_nir: unhandled TGSI property %u = %u\n",
2534 i, value);
2535 unreachable("unhandled TGSI property");
2536 }
2537 }
2538 }
2539
2540 if (s->info.stage == MESA_SHADER_COMPUTE &&
2541 (!s->info.cs.local_size[0] ||
2542 !s->info.cs.local_size[1] ||
2543 !s->info.cs.local_size[2]))
2544 s->info.cs.local_size_variable = true;
2545
2546 c->inputs = rzalloc_array(c, struct nir_variable *, s->num_inputs);
2547 c->outputs = rzalloc_array(c, struct nir_variable *, s->num_outputs);
2548
2549 c->output_regs = rzalloc_array(c, struct ttn_reg_info,
2550 scan.file_max[TGSI_FILE_OUTPUT] + 1);
2551 c->temp_regs = rzalloc_array(c, struct ttn_reg_info,
2552 scan.file_max[TGSI_FILE_TEMPORARY] + 1);
2553 c->imm_defs = rzalloc_array(c, nir_ssa_def *,
2554 scan.file_max[TGSI_FILE_IMMEDIATE] + 1);
2555
2556 c->num_samp_types = scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1;
2557 c->samp_types = rzalloc_array(c, nir_alu_type, c->num_samp_types);
2558
2559 c->if_stack = rzalloc_array(c, nir_cursor,
2560 (scan.opcode_count[TGSI_OPCODE_IF] +
2561 scan.opcode_count[TGSI_OPCODE_UIF]) * 2);
2562 c->loop_stack = rzalloc_array(c, nir_cursor,
2563 scan.opcode_count[TGSI_OPCODE_BGNLOOP]);
2564
2565
2566 ttn_parse_tgsi(c, tgsi_tokens);
2567 ttn_add_output_stores(c);
2568
2569 nir_validate_shader(c->build.shader, "TTN: after parsing TGSI and creating the NIR shader");
2570
2571 return c;
2572 }
2573
2574 static void
2575 ttn_optimize_nir(nir_shader *nir, bool scalar)
2576 {
2577 bool progress;
2578 do {
2579 progress = false;
2580
2581 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2582
2583 if (scalar) {
2584 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
2585 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
2586 }
2587
2588 NIR_PASS_V(nir, nir_lower_alu);
2589 NIR_PASS_V(nir, nir_lower_pack);
2590 NIR_PASS(progress, nir, nir_copy_prop);
2591 NIR_PASS(progress, nir, nir_opt_remove_phis);
2592 NIR_PASS(progress, nir, nir_opt_dce);
2593
2594 if (nir_opt_trivial_continues(nir)) {
2595 progress = true;
2596 NIR_PASS(progress, nir, nir_copy_prop);
2597 NIR_PASS(progress, nir, nir_opt_dce);
2598 }
2599
2600 NIR_PASS(progress, nir, nir_opt_if, false);
2601 NIR_PASS(progress, nir, nir_opt_dead_cf);
2602 NIR_PASS(progress, nir, nir_opt_cse);
2603 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
2604
2605 NIR_PASS(progress, nir, nir_opt_algebraic);
2606 NIR_PASS(progress, nir, nir_opt_constant_folding);
2607
2608 NIR_PASS(progress, nir, nir_opt_undef);
2609 NIR_PASS(progress, nir, nir_opt_conditional_discard);
2610
2611 if (nir->options->max_unroll_iterations) {
2612 NIR_PASS(progress, nir, nir_opt_loop_unroll, (nir_variable_mode)0);
2613 }
2614
2615 } while (progress);
2616
2617 }
2618
2619 /**
2620 * Finalizes the NIR in a similar way as st_glsl_to_nir does.
2621 *
2622 * Drivers expect that these passes are already performed,
2623 * so we have to do it here too.
2624 */
2625 static void
2626 ttn_finalize_nir(struct ttn_compile *c)
2627 {
2628 struct nir_shader *nir = c->build.shader;
2629
2630 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2631 NIR_PASS_V(nir, nir_lower_regs_to_ssa);
2632
2633 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2634 NIR_PASS_V(nir, nir_split_var_copies);
2635 NIR_PASS_V(nir, nir_lower_var_copies);
2636 NIR_PASS_V(nir, nir_lower_system_values);
2637
2638 if (c->cap_packed_uniforms)
2639 NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, 16);
2640
2641 if (!c->cap_samplers_as_deref)
2642 NIR_PASS_V(nir, nir_lower_samplers);
2643
2644 ttn_optimize_nir(nir, c->cap_scalar);
2645 nir_shader_gather_info(nir, c->build.impl);
2646 nir_validate_shader(nir, "TTN: after all optimizations");
2647 }
2648
2649 struct nir_shader *
2650 tgsi_to_nir(const void *tgsi_tokens,
2651 struct pipe_screen *screen)
2652 {
2653 struct ttn_compile *c;
2654 struct nir_shader *s;
2655
2656 c = ttn_compile_init(tgsi_tokens, NULL, screen);
2657 s = c->build.shader;
2658 ttn_finalize_nir(c);
2659 ralloc_free(c);
2660
2661 return s;
2662 }
2663
2664 struct nir_shader *
2665 tgsi_to_nir_noscreen(const void *tgsi_tokens,
2666 const nir_shader_compiler_options *options)
2667 {
2668 struct ttn_compile *c;
2669 struct nir_shader *s;
2670
2671 c = ttn_compile_init(tgsi_tokens, options, NULL);
2672 s = c->build.shader;
2673 ralloc_free(c);
2674
2675 return s;
2676 }
2677