2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/ralloc.h"
26 #include "glsl/nir/nir.h"
27 #include "glsl/nir/nir_builder.h"
28 #include "glsl/list.h"
29 #include "glsl/shader_enums.h"
31 #include "nir/tgsi_to_nir.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_dump.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_scan.h"
37 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
45 /** nir register containing this TGSI index. */
48 /** Offset (in vec4s) from the start of var for this TGSI index. */
53 union tgsi_full_token
*token
;
55 struct tgsi_shader_info
*scan
;
57 struct ttn_reg_info
*output_regs
;
58 struct ttn_reg_info
*temp_regs
;
59 nir_ssa_def
**imm_defs
;
61 unsigned num_samp_types
;
62 nir_alu_type
*samp_types
;
64 nir_register
*addr_reg
;
67 * Stack of cf_node_lists where instructions should be pushed as we pop
68 * back out of the control flow stack.
70 * For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else
71 * instructions should be placed, and if_stack[if_stack_pos - 1] has where
72 * the next instructions outside of the if/then/else block go.
74 struct exec_list
**if_stack
;
75 unsigned if_stack_pos
;
78 * Stack of cf_node_lists where instructions should be pushed as we pop
79 * back out of the control flow stack.
81 * loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside
84 struct exec_list
**loop_stack
;
85 unsigned loop_stack_pos
;
87 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
91 #define ttn_swizzle(b, src, x, y, z, w) \
92 nir_swizzle(b, src, SWIZ(x, y, z, w), 4, false)
93 #define ttn_channel(b, src, swiz) \
94 nir_swizzle(b, src, SWIZ(swiz, swiz, swiz, swiz), 1, false)
97 ttn_src_for_dest(nir_builder
*b
, nir_alu_dest
*dest
)
100 memset(&src
, 0, sizeof(src
));
102 if (dest
->dest
.is_ssa
)
103 src
.src
= nir_src_for_ssa(&dest
->dest
.ssa
);
105 assert(!dest
->dest
.reg
.indirect
);
106 src
.src
= nir_src_for_reg(dest
->dest
.reg
.reg
);
107 src
.src
.reg
.base_offset
= dest
->dest
.reg
.base_offset
;
110 for (int i
= 0; i
< 4; i
++)
113 return nir_fmov_alu(b
, src
, 4);
117 ttn_emit_declaration(struct ttn_compile
*c
)
119 nir_builder
*b
= &c
->build
;
120 struct tgsi_full_declaration
*decl
= &c
->token
->FullDeclaration
;
121 unsigned array_size
= decl
->Range
.Last
- decl
->Range
.First
+ 1;
122 unsigned file
= decl
->Declaration
.File
;
125 if (file
== TGSI_FILE_TEMPORARY
) {
126 if (decl
->Declaration
.Array
) {
127 /* for arrays, we create variables instead of registers: */
128 nir_variable
*var
= rzalloc(b
->shader
, nir_variable
);
130 var
->type
= glsl_array_type(glsl_vec4_type(), array_size
);
131 var
->data
.mode
= nir_var_global
;
132 var
->name
= ralloc_asprintf(var
, "arr_%d", decl
->Array
.ArrayID
);
134 exec_list_push_tail(&b
->shader
->globals
, &var
->node
);
136 for (i
= 0; i
< array_size
; i
++) {
137 /* point all the matching slots to the same var,
138 * with appropriate offset set, mostly just so
139 * we know what to do when tgsi does a non-indirect
142 c
->temp_regs
[decl
->Range
.First
+ i
].reg
= NULL
;
143 c
->temp_regs
[decl
->Range
.First
+ i
].var
= var
;
144 c
->temp_regs
[decl
->Range
.First
+ i
].offset
= i
;
147 for (i
= 0; i
< array_size
; i
++) {
148 nir_register
*reg
= nir_local_reg_create(b
->impl
);
149 reg
->num_components
= 4;
150 c
->temp_regs
[decl
->Range
.First
+ i
].reg
= reg
;
151 c
->temp_regs
[decl
->Range
.First
+ i
].var
= NULL
;
152 c
->temp_regs
[decl
->Range
.First
+ i
].offset
= 0;
155 } else if (file
== TGSI_FILE_ADDRESS
) {
156 c
->addr_reg
= nir_local_reg_create(b
->impl
);
157 c
->addr_reg
->num_components
= 4;
158 } else if (file
== TGSI_FILE_SYSTEM_VALUE
) {
159 /* Nothing to record for system values. */
160 } else if (file
== TGSI_FILE_SAMPLER
) {
161 /* Nothing to record for samplers. */
162 } else if (file
== TGSI_FILE_SAMPLER_VIEW
) {
163 struct tgsi_declaration_sampler_view
*sview
= &decl
->SamplerView
;
166 assert((sview
->ReturnTypeX
== sview
->ReturnTypeY
) &&
167 (sview
->ReturnTypeX
== sview
->ReturnTypeZ
) &&
168 (sview
->ReturnTypeX
== sview
->ReturnTypeW
));
170 switch (sview
->ReturnTypeX
) {
171 case TGSI_RETURN_TYPE_SINT
:
174 case TGSI_RETURN_TYPE_UINT
:
175 type
= nir_type_unsigned
;
177 case TGSI_RETURN_TYPE_FLOAT
:
179 type
= nir_type_float
;
183 for (i
= 0; i
< array_size
; i
++) {
184 c
->samp_types
[decl
->Range
.First
+ i
] = type
;
187 bool is_array
= (array_size
> 1);
189 assert(file
== TGSI_FILE_INPUT
||
190 file
== TGSI_FILE_OUTPUT
||
191 file
== TGSI_FILE_CONSTANT
);
193 /* nothing to do for UBOs: */
194 if ((file
== TGSI_FILE_CONSTANT
) && decl
->Declaration
.Dimension
)
197 if ((file
== TGSI_FILE_INPUT
) || (file
== TGSI_FILE_OUTPUT
)) {
198 is_array
= (is_array
&& decl
->Declaration
.Array
&&
199 (decl
->Array
.ArrayID
!= 0));
202 for (i
= 0; i
< array_size
; i
++) {
203 unsigned idx
= decl
->Range
.First
+ i
;
204 nir_variable
*var
= rzalloc(b
->shader
, nir_variable
);
206 var
->data
.driver_location
= idx
;
208 var
->type
= glsl_vec4_type();
210 var
->type
= glsl_array_type(var
->type
, array_size
);
213 case TGSI_FILE_INPUT
:
214 var
->data
.read_only
= true;
215 var
->data
.mode
= nir_var_shader_in
;
216 var
->name
= ralloc_asprintf(var
, "in_%d", idx
);
218 /* We should probably translate to a VERT_ATTRIB_* or VARYING_SLOT_*
219 * instead, but nothing in NIR core is looking at the value
220 * currently, and this is less change to drivers.
222 var
->data
.location
= decl
->Semantic
.Name
;
223 var
->data
.index
= decl
->Semantic
.Index
;
225 /* We definitely need to translate the interpolation field, because
226 * nir_print will decode it.
228 switch (decl
->Interp
.Interpolate
) {
229 case TGSI_INTERPOLATE_CONSTANT
:
230 var
->data
.interpolation
= INTERP_QUALIFIER_FLAT
;
232 case TGSI_INTERPOLATE_LINEAR
:
233 var
->data
.interpolation
= INTERP_QUALIFIER_NOPERSPECTIVE
;
235 case TGSI_INTERPOLATE_PERSPECTIVE
:
236 var
->data
.interpolation
= INTERP_QUALIFIER_SMOOTH
;
240 exec_list_push_tail(&b
->shader
->inputs
, &var
->node
);
242 case TGSI_FILE_OUTPUT
: {
243 /* Since we can't load from outputs in the IR, we make temporaries
244 * for the outputs and emit stores to the real outputs at the end of
247 nir_register
*reg
= nir_local_reg_create(b
->impl
);
248 reg
->num_components
= 4;
250 reg
->num_array_elems
= array_size
;
252 var
->data
.mode
= nir_var_shader_out
;
253 var
->name
= ralloc_asprintf(var
, "out_%d", idx
);
255 var
->data
.location
= decl
->Semantic
.Name
;
256 var
->data
.index
= decl
->Semantic
.Index
;
260 for (j
= 0; j
< array_size
; j
++) {
261 c
->output_regs
[idx
+ j
].offset
= i
+ j
;
262 c
->output_regs
[idx
+ j
].reg
= reg
;
265 c
->output_regs
[idx
].offset
= i
;
266 c
->output_regs
[idx
].reg
= reg
;
269 exec_list_push_tail(&b
->shader
->outputs
, &var
->node
);
272 case TGSI_FILE_CONSTANT
:
273 var
->data
.mode
= nir_var_uniform
;
274 var
->name
= ralloc_asprintf(var
, "uniform_%d", idx
);
276 exec_list_push_tail(&b
->shader
->uniforms
, &var
->node
);
279 unreachable("bad declaration file");
291 ttn_emit_immediate(struct ttn_compile
*c
)
293 nir_builder
*b
= &c
->build
;
294 struct tgsi_full_immediate
*tgsi_imm
= &c
->token
->FullImmediate
;
295 nir_load_const_instr
*load_const
;
298 load_const
= nir_load_const_instr_create(b
->shader
, 4);
299 c
->imm_defs
[c
->next_imm
] = &load_const
->def
;
302 for (i
= 0; i
< 4; i
++)
303 load_const
->value
.u
[i
] = tgsi_imm
->u
[i
].Uint
;
305 nir_instr_insert_after_cf_list(b
->cf_node_list
, &load_const
->instr
);
309 ttn_src_for_indirect(struct ttn_compile
*c
, struct tgsi_ind_register
*indirect
);
311 /* generate either a constant or indirect deref chain for accessing an
314 static nir_deref_var
*
315 ttn_array_deref(struct ttn_compile
*c
, nir_intrinsic_instr
*instr
,
316 nir_variable
*var
, unsigned offset
,
317 struct tgsi_ind_register
*indirect
)
319 nir_deref_var
*deref
= nir_deref_var_create(instr
, var
);
320 nir_deref_array
*arr
= nir_deref_array_create(deref
);
322 arr
->base_offset
= offset
;
323 arr
->deref
.type
= glsl_get_array_element(var
->type
);
326 arr
->deref_array_type
= nir_deref_array_type_indirect
;
327 arr
->indirect
= ttn_src_for_indirect(c
, indirect
);
329 arr
->deref_array_type
= nir_deref_array_type_direct
;
332 deref
->deref
.child
= &arr
->deref
;
338 ttn_src_for_file_and_index(struct ttn_compile
*c
, unsigned file
, unsigned index
,
339 struct tgsi_ind_register
*indirect
,
340 struct tgsi_dimension
*dim
,
341 struct tgsi_ind_register
*dimind
)
343 nir_builder
*b
= &c
->build
;
346 memset(&src
, 0, sizeof(src
));
349 case TGSI_FILE_TEMPORARY
:
350 if (c
->temp_regs
[index
].var
) {
351 unsigned offset
= c
->temp_regs
[index
].offset
;
352 nir_variable
*var
= c
->temp_regs
[index
].var
;
353 nir_intrinsic_instr
*load
;
355 load
= nir_intrinsic_instr_create(b
->shader
,
356 nir_intrinsic_load_var
);
357 load
->num_components
= 4;
358 load
->variables
[0] = ttn_array_deref(c
, load
, var
, offset
, indirect
);
360 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, NULL
);
361 nir_instr_insert_after_cf_list(b
->cf_node_list
, &load
->instr
);
363 src
= nir_src_for_ssa(&load
->dest
.ssa
);
367 src
.reg
.reg
= c
->temp_regs
[index
].reg
;
372 case TGSI_FILE_ADDRESS
:
373 src
.reg
.reg
= c
->addr_reg
;
377 case TGSI_FILE_IMMEDIATE
:
378 src
= nir_src_for_ssa(c
->imm_defs
[index
]);
383 case TGSI_FILE_SYSTEM_VALUE
: {
384 nir_intrinsic_instr
*load
;
391 switch (c
->scan
->system_value_semantic_name
[index
]) {
392 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
393 op
= nir_intrinsic_load_vertex_id_zero_base
;
395 case TGSI_SEMANTIC_VERTEXID
:
396 op
= nir_intrinsic_load_vertex_id
;
398 case TGSI_SEMANTIC_BASEVERTEX
:
399 op
= nir_intrinsic_load_base_vertex
;
401 case TGSI_SEMANTIC_INSTANCEID
:
402 op
= nir_intrinsic_load_instance_id
;
405 unreachable("bad system value");
408 load
= nir_intrinsic_instr_create(b
->shader
, op
);
409 load
->num_components
= ncomp
;
411 nir_ssa_dest_init(&load
->instr
, &load
->dest
, ncomp
, NULL
);
412 nir_instr_insert_after_cf_list(b
->cf_node_list
, &load
->instr
);
414 src
= nir_src_for_ssa(&load
->dest
.ssa
);
418 case TGSI_FILE_INPUT
:
419 case TGSI_FILE_CONSTANT
: {
420 nir_intrinsic_instr
*load
;
425 case TGSI_FILE_INPUT
:
426 op
= indirect
? nir_intrinsic_load_input_indirect
:
427 nir_intrinsic_load_input
;
430 case TGSI_FILE_CONSTANT
:
432 op
= indirect
? nir_intrinsic_load_ubo_indirect
:
433 nir_intrinsic_load_ubo
;
434 /* convert index from vec4 to byte: */
437 op
= indirect
? nir_intrinsic_load_uniform_indirect
:
438 nir_intrinsic_load_uniform
;
442 unreachable("No other load files supported");
446 load
= nir_intrinsic_instr_create(b
->shader
, op
);
448 load
->num_components
= 4;
449 load
->const_index
[0] = index
;
453 ttn_src_for_file_and_index(c
, dimind
->File
, dimind
->Index
,
456 /* UBOs start at index 1 in TGSI: */
458 nir_src_for_ssa(nir_imm_int(b
, dim
->Index
- 1));
463 load
->src
[srcn
] = ttn_src_for_indirect(c
, indirect
);
465 assert(load
->src
[srcn
].is_ssa
);
466 /* we also need to covert vec4 to byte here too: */
468 nir_src_for_ssa(nir_ishl(b
, load
->src
[srcn
].ssa
,
473 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, NULL
);
474 nir_instr_insert_after_cf_list(b
->cf_node_list
, &load
->instr
);
476 src
= nir_src_for_ssa(&load
->dest
.ssa
);
481 unreachable("bad src file");
489 ttn_src_for_indirect(struct ttn_compile
*c
, struct tgsi_ind_register
*indirect
)
491 nir_builder
*b
= &c
->build
;
493 memset(&src
, 0, sizeof(src
));
494 for (int i
= 0; i
< 4; i
++)
495 src
.swizzle
[i
] = indirect
->Swizzle
;
496 src
.src
= ttn_src_for_file_and_index(c
,
500 return nir_src_for_ssa(nir_imov_alu(b
, src
, 1));
504 ttn_get_dest(struct ttn_compile
*c
, struct tgsi_full_dst_register
*tgsi_fdst
)
506 struct tgsi_dst_register
*tgsi_dst
= &tgsi_fdst
->Register
;
508 unsigned index
= tgsi_dst
->Index
;
510 memset(&dest
, 0, sizeof(dest
));
512 if (tgsi_dst
->File
== TGSI_FILE_TEMPORARY
) {
513 if (c
->temp_regs
[index
].var
) {
514 nir_builder
*b
= &c
->build
;
515 nir_intrinsic_instr
*load
;
516 struct tgsi_ind_register
*indirect
=
517 tgsi_dst
->Indirect
? &tgsi_fdst
->Indirect
: NULL
;
520 /* this works, because TGSI will give us a base offset
521 * (in case of indirect index) that points back into
522 * the array. Access can be direct or indirect, we
523 * don't really care. Just create a one-shot dst reg
524 * that will get store_var'd back into the array var
525 * at the end of ttn_emit_instruction()
527 reg
= nir_local_reg_create(c
->build
.impl
);
528 reg
->num_components
= 4;
529 dest
.dest
.reg
.reg
= reg
;
530 dest
.dest
.reg
.base_offset
= 0;
532 /* since the alu op might not write to all components
533 * of the temporary, we must first do a load_var to
534 * get the previous array elements into the register.
535 * This is one area that NIR could use a bit of
536 * improvement (or opt pass to clean up the mess
537 * once things are scalarized)
540 load
= nir_intrinsic_instr_create(c
->build
.shader
,
541 nir_intrinsic_load_var
);
542 load
->num_components
= 4;
544 ttn_array_deref(c
, load
, c
->temp_regs
[index
].var
,
545 c
->temp_regs
[index
].offset
,
548 load
->dest
= nir_dest_for_reg(reg
);
550 nir_instr_insert_after_cf_list(b
->cf_node_list
, &load
->instr
);
552 assert(!tgsi_dst
->Indirect
);
553 dest
.dest
.reg
.reg
= c
->temp_regs
[index
].reg
;
554 dest
.dest
.reg
.base_offset
= c
->temp_regs
[index
].offset
;
556 } else if (tgsi_dst
->File
== TGSI_FILE_OUTPUT
) {
557 dest
.dest
.reg
.reg
= c
->output_regs
[index
].reg
;
558 dest
.dest
.reg
.base_offset
= c
->output_regs
[index
].offset
;
559 } else if (tgsi_dst
->File
== TGSI_FILE_ADDRESS
) {
561 dest
.dest
.reg
.reg
= c
->addr_reg
;
564 dest
.write_mask
= tgsi_dst
->WriteMask
;
565 dest
.saturate
= false;
567 if (tgsi_dst
->Indirect
&& (tgsi_dst
->File
!= TGSI_FILE_TEMPORARY
)) {
568 nir_src
*indirect
= ralloc(c
->build
.shader
, nir_src
);
569 *indirect
= ttn_src_for_indirect(c
, &tgsi_fdst
->Indirect
);
570 dest
.dest
.reg
.indirect
= indirect
;
576 static nir_variable
*
577 ttn_get_var(struct ttn_compile
*c
, struct tgsi_full_dst_register
*tgsi_fdst
)
579 struct tgsi_dst_register
*tgsi_dst
= &tgsi_fdst
->Register
;
580 unsigned index
= tgsi_dst
->Index
;
582 if (tgsi_dst
->File
== TGSI_FILE_TEMPORARY
) {
583 /* we should not have an indirect when there is no var! */
584 if (!c
->temp_regs
[index
].var
)
585 assert(!tgsi_dst
->Indirect
);
586 return c
->temp_regs
[index
].var
;
593 ttn_get_src(struct ttn_compile
*c
, struct tgsi_full_src_register
*tgsi_fsrc
)
595 nir_builder
*b
= &c
->build
;
596 struct tgsi_src_register
*tgsi_src
= &tgsi_fsrc
->Register
;
597 unsigned tgsi_opcode
= c
->token
->FullInstruction
.Instruction
.Opcode
;
598 unsigned tgsi_src_type
= tgsi_opcode_infer_src_type(tgsi_opcode
);
599 bool src_is_float
= !(tgsi_src_type
== TGSI_TYPE_SIGNED
||
600 tgsi_src_type
== TGSI_TYPE_UNSIGNED
);
603 memset(&src
, 0, sizeof(src
));
605 if (tgsi_src
->File
== TGSI_FILE_NULL
) {
606 return nir_imm_float(b
, 0.0);
607 } else if (tgsi_src
->File
== TGSI_FILE_SAMPLER
) {
608 /* Only the index of the sampler gets used in texturing, and it will
609 * handle looking that up on its own instead of using the nir_alu_src.
611 assert(!tgsi_src
->Indirect
);
614 struct tgsi_ind_register
*ind
= NULL
;
615 struct tgsi_dimension
*dim
= NULL
;
616 struct tgsi_ind_register
*dimind
= NULL
;
617 if (tgsi_src
->Indirect
)
618 ind
= &tgsi_fsrc
->Indirect
;
619 if (tgsi_src
->Dimension
) {
620 dim
= &tgsi_fsrc
->Dimension
;
622 dimind
= &tgsi_fsrc
->DimIndirect
;
624 src
.src
= ttn_src_for_file_and_index(c
,
630 src
.swizzle
[0] = tgsi_src
->SwizzleX
;
631 src
.swizzle
[1] = tgsi_src
->SwizzleY
;
632 src
.swizzle
[2] = tgsi_src
->SwizzleZ
;
633 src
.swizzle
[3] = tgsi_src
->SwizzleW
;
635 nir_ssa_def
*def
= nir_fmov_alu(b
, src
, 4);
637 if (tgsi_src
->Absolute
) {
639 def
= nir_fabs(b
, def
);
641 def
= nir_iabs(b
, def
);
644 if (tgsi_src
->Negate
) {
646 def
= nir_fneg(b
, def
);
648 def
= nir_ineg(b
, def
);
655 ttn_alu(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
657 unsigned num_srcs
= nir_op_infos
[op
].num_inputs
;
658 nir_alu_instr
*instr
= nir_alu_instr_create(b
->shader
, op
);
661 for (i
= 0; i
< num_srcs
; i
++)
662 instr
->src
[i
].src
= nir_src_for_ssa(src
[i
]);
665 nir_instr_insert_after_cf_list(b
->cf_node_list
, &instr
->instr
);
669 ttn_move_dest_masked(nir_builder
*b
, nir_alu_dest dest
,
670 nir_ssa_def
*def
, unsigned write_mask
)
672 if (!(dest
.write_mask
& write_mask
))
675 nir_alu_instr
*mov
= nir_alu_instr_create(b
->shader
, nir_op_imov
);
677 mov
->dest
.write_mask
&= write_mask
;
678 mov
->src
[0].src
= nir_src_for_ssa(def
);
679 for (unsigned i
= def
->num_components
; i
< 4; i
++)
680 mov
->src
[0].swizzle
[i
] = def
->num_components
- 1;
681 nir_instr_insert_after_cf_list(b
->cf_node_list
, &mov
->instr
);
685 ttn_move_dest(nir_builder
*b
, nir_alu_dest dest
, nir_ssa_def
*def
)
687 ttn_move_dest_masked(b
, dest
, def
, TGSI_WRITEMASK_XYZW
);
691 ttn_arl(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
693 ttn_move_dest(b
, dest
, nir_f2i(b
, nir_ffloor(b
, src
[0])));
696 /* EXP - Approximate Exponential Base 2
697 * dst.x = 2^{\lfloor src.x\rfloor}
698 * dst.y = src.x - \lfloor src.x\rfloor
703 ttn_exp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
705 nir_ssa_def
*srcx
= ttn_channel(b
, src
[0], X
);
707 ttn_move_dest_masked(b
, dest
, nir_fexp2(b
, nir_ffloor(b
, srcx
)),
709 ttn_move_dest_masked(b
, dest
, nir_fsub(b
, srcx
, nir_ffloor(b
, srcx
)),
711 ttn_move_dest_masked(b
, dest
, nir_fexp2(b
, srcx
), TGSI_WRITEMASK_Z
);
712 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
715 /* LOG - Approximate Logarithm Base 2
716 * dst.x = \lfloor\log_2{|src.x|}\rfloor
717 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
718 * dst.z = \log_2{|src.x|}
722 ttn_log(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
724 nir_ssa_def
*abs_srcx
= nir_fabs(b
, ttn_channel(b
, src
[0], X
));
725 nir_ssa_def
*log2
= nir_flog2(b
, abs_srcx
);
727 ttn_move_dest_masked(b
, dest
, nir_ffloor(b
, log2
), TGSI_WRITEMASK_X
);
728 ttn_move_dest_masked(b
, dest
,
729 nir_fdiv(b
, abs_srcx
, nir_fexp2(b
, nir_ffloor(b
, log2
))),
731 ttn_move_dest_masked(b
, dest
, nir_flog2(b
, abs_srcx
), TGSI_WRITEMASK_Z
);
732 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
735 /* DST - Distance Vector
737 * dst.y = src0.y \times src1.y
742 ttn_dst(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
744 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_X
);
745 ttn_move_dest_masked(b
, dest
, nir_fmul(b
, src
[0], src
[1]), TGSI_WRITEMASK_Y
);
746 ttn_move_dest_masked(b
, dest
, nir_fmov(b
, src
[0]), TGSI_WRITEMASK_Z
);
747 ttn_move_dest_masked(b
, dest
, nir_fmov(b
, src
[1]), TGSI_WRITEMASK_W
);
750 /* LIT - Light Coefficients
752 * dst.y = max(src.x, 0.0)
753 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
757 ttn_lit(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
759 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_XW
);
761 ttn_move_dest_masked(b
, dest
, nir_fmax(b
, ttn_channel(b
, src
[0], X
),
762 nir_imm_float(b
, 0.0)), TGSI_WRITEMASK_Y
);
764 if (dest
.write_mask
& TGSI_WRITEMASK_Z
) {
765 nir_ssa_def
*src0_y
= ttn_channel(b
, src
[0], Y
);
766 nir_ssa_def
*wclamp
= nir_fmax(b
, nir_fmin(b
, ttn_channel(b
, src
[0], W
),
767 nir_imm_float(b
, 128.0)),
768 nir_imm_float(b
, -128.0));
769 nir_ssa_def
*pow
= nir_fpow(b
, nir_fmax(b
, src0_y
, nir_imm_float(b
, 0.0)),
772 ttn_move_dest_masked(b
, dest
,
775 nir_imm_float(b
, 0.0),
776 ttn_channel(b
, src
[0], X
)),
777 nir_imm_float(b
, 0.0),
784 * dst.x = \cos{src.x}
785 * dst.y = \sin{src.x}
790 ttn_scs(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
792 ttn_move_dest_masked(b
, dest
, nir_fcos(b
, ttn_channel(b
, src
[0], X
)),
794 ttn_move_dest_masked(b
, dest
, nir_fsin(b
, ttn_channel(b
, src
[0], X
)),
796 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 0.0), TGSI_WRITEMASK_Z
);
797 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
801 ttn_sle(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
803 ttn_move_dest(b
, dest
, nir_sge(b
, src
[1], src
[0]));
807 ttn_sgt(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
809 ttn_move_dest(b
, dest
, nir_slt(b
, src
[1], src
[0]));
813 ttn_clamp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
815 ttn_move_dest(b
, dest
, nir_fmin(b
, nir_fmax(b
, src
[0], src
[1]), src
[2]));
819 ttn_xpd(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
821 ttn_move_dest_masked(b
, dest
,
824 ttn_swizzle(b
, src
[0], Y
, Z
, X
, X
),
825 ttn_swizzle(b
, src
[1], Z
, X
, Y
, X
)),
827 ttn_swizzle(b
, src
[1], Y
, Z
, X
, X
),
828 ttn_swizzle(b
, src
[0], Z
, X
, Y
, X
))),
830 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
834 ttn_dp2a(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
836 ttn_move_dest(b
, dest
,
837 ttn_channel(b
, nir_fadd(b
, nir_fdot2(b
, src
[0], src
[1]),
843 ttn_dp2(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
845 ttn_move_dest(b
, dest
, nir_fdot2(b
, src
[0], src
[1]));
849 ttn_dp3(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
851 ttn_move_dest(b
, dest
, nir_fdot3(b
, src
[0], src
[1]));
855 ttn_dp4(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
857 ttn_move_dest(b
, dest
, nir_fdot4(b
, src
[0], src
[1]));
861 ttn_dph(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
863 ttn_move_dest(b
, dest
, nir_fadd(b
, nir_fdot3(b
, src
[0], src
[1]),
864 ttn_channel(b
, src
[1], W
)));
868 ttn_umad(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
870 ttn_move_dest(b
, dest
, nir_iadd(b
, nir_imul(b
, src
[0], src
[1]), src
[2]));
874 ttn_arr(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
876 ttn_move_dest(b
, dest
, nir_ffloor(b
, nir_fadd(b
, src
[0], nir_imm_float(b
, 0.5))));
880 ttn_cmp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
882 ttn_move_dest(b
, dest
, nir_bcsel(b
,
883 nir_flt(b
, src
[0], nir_imm_float(b
, 0.0)),
888 ttn_ucmp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
890 ttn_move_dest(b
, dest
, nir_bcsel(b
,
891 nir_ine(b
, src
[0], nir_imm_int(b
, 0)),
896 ttn_kill(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
898 nir_intrinsic_instr
*discard
=
899 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard
);
900 nir_instr_insert_after_cf_list(b
->cf_node_list
, &discard
->instr
);
904 ttn_kill_if(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
906 nir_ssa_def
*cmp
= nir_bany4(b
, nir_flt(b
, src
[0], nir_imm_float(b
, 0.0)));
907 nir_intrinsic_instr
*discard
=
908 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
909 discard
->src
[0] = nir_src_for_ssa(cmp
);
910 nir_instr_insert_after_cf_list(b
->cf_node_list
, &discard
->instr
);
914 ttn_if(struct ttn_compile
*c
, nir_ssa_def
*src
, bool is_uint
)
916 nir_builder
*b
= &c
->build
;
918 /* Save the outside-of-the-if-statement node list. */
919 c
->if_stack
[c
->if_stack_pos
] = b
->cf_node_list
;
922 src
= ttn_channel(b
, src
, X
);
924 nir_if
*if_stmt
= nir_if_create(b
->shader
);
926 if_stmt
->condition
= nir_src_for_ssa(nir_ine(b
, src
, nir_imm_int(b
, 0)));
928 if_stmt
->condition
= nir_src_for_ssa(nir_fne(b
, src
, nir_imm_int(b
, 0)));
930 nir_cf_node_insert_end(b
->cf_node_list
, &if_stmt
->cf_node
);
932 nir_builder_insert_after_cf_list(b
, &if_stmt
->then_list
);
934 c
->if_stack
[c
->if_stack_pos
] = &if_stmt
->else_list
;
939 ttn_else(struct ttn_compile
*c
)
941 nir_builder
*b
= &c
->build
;
943 nir_builder_insert_after_cf_list(b
, c
->if_stack
[c
->if_stack_pos
- 1]);
947 ttn_endif(struct ttn_compile
*c
)
949 nir_builder
*b
= &c
->build
;
951 c
->if_stack_pos
-= 2;
952 nir_builder_insert_after_cf_list(b
, c
->if_stack
[c
->if_stack_pos
]);
956 ttn_bgnloop(struct ttn_compile
*c
)
958 nir_builder
*b
= &c
->build
;
960 /* Save the outside-of-the-loop node list. */
961 c
->loop_stack
[c
->loop_stack_pos
] = b
->cf_node_list
;
964 nir_loop
*loop
= nir_loop_create(b
->shader
);
965 nir_cf_node_insert_end(b
->cf_node_list
, &loop
->cf_node
);
967 nir_builder_insert_after_cf_list(b
, &loop
->body
);
971 ttn_cont(nir_builder
*b
)
973 nir_jump_instr
*instr
= nir_jump_instr_create(b
->shader
, nir_jump_continue
);
974 nir_instr_insert_after_cf_list(b
->cf_node_list
, &instr
->instr
);
978 ttn_brk(nir_builder
*b
)
980 nir_jump_instr
*instr
= nir_jump_instr_create(b
->shader
, nir_jump_break
);
981 nir_instr_insert_after_cf_list(b
->cf_node_list
, &instr
->instr
);
985 ttn_endloop(struct ttn_compile
*c
)
987 nir_builder
*b
= &c
->build
;
990 nir_builder_insert_after_cf_list(b
, c
->loop_stack
[c
->loop_stack_pos
]);
994 setup_texture_info(nir_tex_instr
*instr
, unsigned texture
)
997 case TGSI_TEXTURE_1D
:
998 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
1000 case TGSI_TEXTURE_1D_ARRAY
:
1001 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
1002 instr
->is_array
= true;
1004 case TGSI_TEXTURE_SHADOW1D
:
1005 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
1006 instr
->is_shadow
= true;
1008 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1009 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
1010 instr
->is_shadow
= true;
1011 instr
->is_array
= true;
1013 case TGSI_TEXTURE_2D
:
1014 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
1016 case TGSI_TEXTURE_2D_ARRAY
:
1017 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
1018 instr
->is_array
= true;
1020 case TGSI_TEXTURE_2D_MSAA
:
1021 instr
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
1023 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
1024 instr
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
1025 instr
->is_array
= true;
1027 case TGSI_TEXTURE_SHADOW2D
:
1028 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
1029 instr
->is_shadow
= true;
1031 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1032 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
1033 instr
->is_shadow
= true;
1034 instr
->is_array
= true;
1036 case TGSI_TEXTURE_3D
:
1037 instr
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
1039 case TGSI_TEXTURE_CUBE
:
1040 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
1042 case TGSI_TEXTURE_CUBE_ARRAY
:
1043 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
1044 instr
->is_array
= true;
1046 case TGSI_TEXTURE_SHADOWCUBE
:
1047 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
1048 instr
->is_shadow
= true;
1050 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1051 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
1052 instr
->is_shadow
= true;
1053 instr
->is_array
= true;
1055 case TGSI_TEXTURE_RECT
:
1056 instr
->sampler_dim
= GLSL_SAMPLER_DIM_RECT
;
1058 case TGSI_TEXTURE_SHADOWRECT
:
1059 instr
->sampler_dim
= GLSL_SAMPLER_DIM_RECT
;
1060 instr
->is_shadow
= true;
1063 fprintf(stderr
, "Unknown TGSI texture target %d\n", texture
);
1069 ttn_tex(struct ttn_compile
*c
, nir_alu_dest dest
, nir_ssa_def
**src
)
1071 nir_builder
*b
= &c
->build
;
1072 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
1073 nir_tex_instr
*instr
;
1075 unsigned num_srcs
, samp
= 1, sview
, i
;
1077 switch (tgsi_inst
->Instruction
.Opcode
) {
1078 case TGSI_OPCODE_TEX
:
1082 case TGSI_OPCODE_TXP
:
1086 case TGSI_OPCODE_TXB
:
1090 case TGSI_OPCODE_TXB2
:
1095 case TGSI_OPCODE_TXL
:
1099 case TGSI_OPCODE_TXL2
:
1104 case TGSI_OPCODE_TXF
:
1105 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_2D_MSAA
||
1106 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1107 op
= nir_texop_txf_ms
;
1113 case TGSI_OPCODE_TXD
:
1120 fprintf(stderr
, "unknown TGSI tex op %d\n", tgsi_inst
->Instruction
.Opcode
);
1124 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
1125 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
1126 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
1127 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
1128 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
1129 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
1130 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1134 num_srcs
+= tgsi_inst
->Texture
.NumOffsets
;
1136 instr
= nir_tex_instr_create(b
->shader
, num_srcs
);
1139 setup_texture_info(instr
, tgsi_inst
->Texture
.Texture
);
1141 switch (instr
->sampler_dim
) {
1142 case GLSL_SAMPLER_DIM_1D
:
1143 case GLSL_SAMPLER_DIM_BUF
:
1144 instr
->coord_components
= 1;
1146 case GLSL_SAMPLER_DIM_2D
:
1147 case GLSL_SAMPLER_DIM_RECT
:
1148 case GLSL_SAMPLER_DIM_EXTERNAL
:
1149 case GLSL_SAMPLER_DIM_MS
:
1150 instr
->coord_components
= 2;
1152 case GLSL_SAMPLER_DIM_3D
:
1153 case GLSL_SAMPLER_DIM_CUBE
:
1154 instr
->coord_components
= 3;
1158 if (instr
->is_array
)
1159 instr
->coord_components
++;
1161 assert(tgsi_inst
->Src
[samp
].Register
.File
== TGSI_FILE_SAMPLER
);
1162 instr
->sampler_index
= tgsi_inst
->Src
[samp
].Register
.Index
;
1164 /* TODO if we supported any opc's which take an explicit SVIEW
1165 * src, we would use that here instead. But for the "legacy"
1166 * texture opc's the SVIEW index is same as SAMP index:
1168 sview
= instr
->sampler_index
;
1170 if (sview
< c
->num_samp_types
) {
1171 instr
->dest_type
= c
->samp_types
[sview
];
1173 instr
->dest_type
= nir_type_float
;
1176 unsigned src_number
= 0;
1178 instr
->src
[src_number
].src
=
1179 nir_src_for_ssa(nir_swizzle(b
, src
[0], SWIZ(X
, Y
, Z
, W
),
1180 instr
->coord_components
, false));
1181 instr
->src
[src_number
].src_type
= nir_tex_src_coord
;
1184 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1185 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1186 instr
->src
[src_number
].src_type
= nir_tex_src_projector
;
1190 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
) {
1191 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1192 instr
->src
[src_number
].src_type
= nir_tex_src_bias
;
1196 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
) {
1197 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[1], X
));
1198 instr
->src
[src_number
].src_type
= nir_tex_src_bias
;
1202 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
) {
1203 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1204 instr
->src
[src_number
].src_type
= nir_tex_src_lod
;
1208 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
1209 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[1], X
));
1210 instr
->src
[src_number
].src_type
= nir_tex_src_lod
;
1214 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
) {
1215 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1216 if (op
== nir_texop_txf_ms
)
1217 instr
->src
[src_number
].src_type
= nir_tex_src_ms_index
;
1219 instr
->src
[src_number
].src_type
= nir_tex_src_lod
;
1223 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
1224 instr
->src
[src_number
].src
=
1225 nir_src_for_ssa(nir_swizzle(b
, src
[1], SWIZ(X
, Y
, Z
, W
),
1226 instr
->coord_components
, false));
1227 instr
->src
[src_number
].src_type
= nir_tex_src_ddx
;
1229 instr
->src
[src_number
].src
=
1230 nir_src_for_ssa(nir_swizzle(b
, src
[2], SWIZ(X
, Y
, Z
, W
),
1231 instr
->coord_components
, false));
1232 instr
->src
[src_number
].src_type
= nir_tex_src_ddy
;
1236 if (instr
->is_shadow
) {
1237 if (instr
->coord_components
< 3)
1238 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], Z
));
1240 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1242 instr
->src
[src_number
].src_type
= nir_tex_src_comparitor
;
1246 for (i
= 0; i
< tgsi_inst
->Texture
.NumOffsets
; i
++) {
1247 struct tgsi_texture_offset
*tex_offset
= &tgsi_inst
->TexOffsets
[i
];
1248 /* since TexOffset ins't using tgsi_full_src_register we get to
1249 * do some extra gymnastics:
1253 memset(&src
, 0, sizeof(src
));
1255 src
.src
= ttn_src_for_file_and_index(c
,
1260 src
.swizzle
[0] = tex_offset
->SwizzleX
;
1261 src
.swizzle
[1] = tex_offset
->SwizzleY
;
1262 src
.swizzle
[2] = tex_offset
->SwizzleZ
;
1263 src
.swizzle
[3] = TGSI_SWIZZLE_W
;
1265 instr
->src
[src_number
].src_type
= nir_tex_src_offset
;
1266 instr
->src
[src_number
].src
= nir_src_for_ssa(
1267 nir_fmov_alu(b
, src
, nir_tex_instr_src_size(instr
, src_number
)));
1271 assert(src_number
== num_srcs
);
1273 nir_ssa_dest_init(&instr
->instr
, &instr
->dest
, 4, NULL
);
1274 nir_instr_insert_after_cf_list(b
->cf_node_list
, &instr
->instr
);
1276 /* Resolve the writemask on the texture op. */
1277 ttn_move_dest(b
, dest
, &instr
->dest
.ssa
);
1280 /* TGSI_OPCODE_TXQ is actually two distinct operations:
1282 * dst.x = texture\_width(unit, lod)
1283 * dst.y = texture\_height(unit, lod)
1284 * dst.z = texture\_depth(unit, lod)
1285 * dst.w = texture\_levels(unit)
1287 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels
1290 ttn_txq(struct ttn_compile
*c
, nir_alu_dest dest
, nir_ssa_def
**src
)
1292 nir_builder
*b
= &c
->build
;
1293 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
1294 nir_tex_instr
*txs
, *qlv
;
1296 txs
= nir_tex_instr_create(b
->shader
, 1);
1297 txs
->op
= nir_texop_txs
;
1298 setup_texture_info(txs
, tgsi_inst
->Texture
.Texture
);
1300 qlv
= nir_tex_instr_create(b
->shader
, 0);
1301 qlv
->op
= nir_texop_query_levels
;
1302 setup_texture_info(qlv
, tgsi_inst
->Texture
.Texture
);
1304 assert(tgsi_inst
->Src
[1].Register
.File
== TGSI_FILE_SAMPLER
);
1305 txs
->sampler_index
= tgsi_inst
->Src
[1].Register
.Index
;
1306 qlv
->sampler_index
= tgsi_inst
->Src
[1].Register
.Index
;
1308 /* only single src, the lod: */
1309 txs
->src
[0].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], X
));
1310 txs
->src
[0].src_type
= nir_tex_src_lod
;
1312 nir_ssa_dest_init(&txs
->instr
, &txs
->dest
, 3, NULL
);
1313 nir_instr_insert_after_cf_list(b
->cf_node_list
, &txs
->instr
);
1315 nir_ssa_dest_init(&qlv
->instr
, &qlv
->dest
, 1, NULL
);
1316 nir_instr_insert_after_cf_list(b
->cf_node_list
, &qlv
->instr
);
1318 ttn_move_dest_masked(b
, dest
, &txs
->dest
.ssa
, TGSI_WRITEMASK_XYZ
);
1319 ttn_move_dest_masked(b
, dest
, &qlv
->dest
.ssa
, TGSI_WRITEMASK_W
);
1322 static const nir_op op_trans
[TGSI_OPCODE_LAST
] = {
1323 [TGSI_OPCODE_ARL
] = 0,
1324 [TGSI_OPCODE_MOV
] = nir_op_fmov
,
1325 [TGSI_OPCODE_LIT
] = 0,
1326 [TGSI_OPCODE_RCP
] = nir_op_frcp
,
1327 [TGSI_OPCODE_RSQ
] = nir_op_frsq
,
1328 [TGSI_OPCODE_EXP
] = 0,
1329 [TGSI_OPCODE_LOG
] = 0,
1330 [TGSI_OPCODE_MUL
] = nir_op_fmul
,
1331 [TGSI_OPCODE_ADD
] = nir_op_fadd
,
1332 [TGSI_OPCODE_DP3
] = 0,
1333 [TGSI_OPCODE_DP4
] = 0,
1334 [TGSI_OPCODE_DST
] = 0,
1335 [TGSI_OPCODE_MIN
] = nir_op_fmin
,
1336 [TGSI_OPCODE_MAX
] = nir_op_fmax
,
1337 [TGSI_OPCODE_SLT
] = nir_op_slt
,
1338 [TGSI_OPCODE_SGE
] = nir_op_sge
,
1339 [TGSI_OPCODE_MAD
] = nir_op_ffma
,
1340 [TGSI_OPCODE_SUB
] = nir_op_fsub
,
1341 [TGSI_OPCODE_LRP
] = 0,
1342 [TGSI_OPCODE_SQRT
] = nir_op_fsqrt
,
1343 [TGSI_OPCODE_DP2A
] = 0,
1344 [TGSI_OPCODE_FRC
] = nir_op_ffract
,
1345 [TGSI_OPCODE_CLAMP
] = 0,
1346 [TGSI_OPCODE_FLR
] = nir_op_ffloor
,
1347 [TGSI_OPCODE_ROUND
] = nir_op_fround_even
,
1348 [TGSI_OPCODE_EX2
] = nir_op_fexp2
,
1349 [TGSI_OPCODE_LG2
] = nir_op_flog2
,
1350 [TGSI_OPCODE_POW
] = nir_op_fpow
,
1351 [TGSI_OPCODE_XPD
] = 0,
1352 [TGSI_OPCODE_ABS
] = nir_op_fabs
,
1353 [TGSI_OPCODE_DPH
] = 0,
1354 [TGSI_OPCODE_COS
] = nir_op_fcos
,
1355 [TGSI_OPCODE_DDX
] = nir_op_fddx
,
1356 [TGSI_OPCODE_DDY
] = nir_op_fddy
,
1357 [TGSI_OPCODE_KILL
] = 0,
1358 [TGSI_OPCODE_PK2H
] = 0, /* XXX */
1359 [TGSI_OPCODE_PK2US
] = 0, /* XXX */
1360 [TGSI_OPCODE_PK4B
] = 0, /* XXX */
1361 [TGSI_OPCODE_PK4UB
] = 0, /* XXX */
1362 [TGSI_OPCODE_SEQ
] = nir_op_seq
,
1363 [TGSI_OPCODE_SGT
] = 0,
1364 [TGSI_OPCODE_SIN
] = nir_op_fsin
,
1365 [TGSI_OPCODE_SNE
] = nir_op_sne
,
1366 [TGSI_OPCODE_SLE
] = 0,
1367 [TGSI_OPCODE_TEX
] = 0,
1368 [TGSI_OPCODE_TXD
] = 0,
1369 [TGSI_OPCODE_TXP
] = 0,
1370 [TGSI_OPCODE_UP2H
] = 0, /* XXX */
1371 [TGSI_OPCODE_UP2US
] = 0, /* XXX */
1372 [TGSI_OPCODE_UP4B
] = 0, /* XXX */
1373 [TGSI_OPCODE_UP4UB
] = 0, /* XXX */
1374 [TGSI_OPCODE_ARR
] = 0,
1376 /* No function calls, yet. */
1377 [TGSI_OPCODE_CAL
] = 0, /* XXX */
1378 [TGSI_OPCODE_RET
] = 0, /* XXX */
1380 [TGSI_OPCODE_SSG
] = nir_op_fsign
,
1381 [TGSI_OPCODE_CMP
] = 0,
1382 [TGSI_OPCODE_SCS
] = 0,
1383 [TGSI_OPCODE_TXB
] = 0,
1384 [TGSI_OPCODE_DIV
] = nir_op_fdiv
,
1385 [TGSI_OPCODE_DP2
] = 0,
1386 [TGSI_OPCODE_DP2A
] = 0,
1387 [TGSI_OPCODE_TXL
] = 0,
1389 [TGSI_OPCODE_BRK
] = 0,
1390 [TGSI_OPCODE_IF
] = 0,
1391 [TGSI_OPCODE_UIF
] = 0,
1392 [TGSI_OPCODE_ELSE
] = 0,
1393 [TGSI_OPCODE_ENDIF
] = 0,
1395 [TGSI_OPCODE_DDX_FINE
] = nir_op_fddx_fine
,
1396 [TGSI_OPCODE_DDY_FINE
] = nir_op_fddy_fine
,
1398 [TGSI_OPCODE_PUSHA
] = 0, /* XXX */
1399 [TGSI_OPCODE_POPA
] = 0, /* XXX */
1401 [TGSI_OPCODE_CEIL
] = nir_op_fceil
,
1402 [TGSI_OPCODE_I2F
] = nir_op_i2f
,
1403 [TGSI_OPCODE_NOT
] = nir_op_inot
,
1404 [TGSI_OPCODE_TRUNC
] = nir_op_ftrunc
,
1405 [TGSI_OPCODE_SHL
] = nir_op_ishl
,
1406 [TGSI_OPCODE_AND
] = nir_op_iand
,
1407 [TGSI_OPCODE_OR
] = nir_op_ior
,
1408 [TGSI_OPCODE_MOD
] = nir_op_umod
,
1409 [TGSI_OPCODE_XOR
] = nir_op_ixor
,
1410 [TGSI_OPCODE_SAD
] = 0, /* XXX */
1411 [TGSI_OPCODE_TXF
] = 0,
1412 [TGSI_OPCODE_TXQ
] = 0,
1414 [TGSI_OPCODE_CONT
] = 0,
1416 [TGSI_OPCODE_EMIT
] = 0, /* XXX */
1417 [TGSI_OPCODE_ENDPRIM
] = 0, /* XXX */
1419 [TGSI_OPCODE_BGNLOOP
] = 0,
1420 [TGSI_OPCODE_BGNSUB
] = 0, /* XXX: no function calls */
1421 [TGSI_OPCODE_ENDLOOP
] = 0,
1422 [TGSI_OPCODE_ENDSUB
] = 0, /* XXX: no function calls */
1424 [TGSI_OPCODE_TXQ_LZ
] = 0,
1425 [TGSI_OPCODE_NOP
] = 0,
1426 [TGSI_OPCODE_FSEQ
] = nir_op_feq
,
1427 [TGSI_OPCODE_FSGE
] = nir_op_fge
,
1428 [TGSI_OPCODE_FSLT
] = nir_op_flt
,
1429 [TGSI_OPCODE_FSNE
] = nir_op_fne
,
1431 /* No control flow yet */
1432 [TGSI_OPCODE_CALLNZ
] = 0, /* XXX */
1433 [TGSI_OPCODE_BREAKC
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1435 [TGSI_OPCODE_KILL_IF
] = 0,
1437 [TGSI_OPCODE_END
] = 0,
1439 [TGSI_OPCODE_F2I
] = nir_op_f2i
,
1440 [TGSI_OPCODE_IDIV
] = nir_op_idiv
,
1441 [TGSI_OPCODE_IMAX
] = nir_op_imax
,
1442 [TGSI_OPCODE_IMIN
] = nir_op_imin
,
1443 [TGSI_OPCODE_INEG
] = nir_op_ineg
,
1444 [TGSI_OPCODE_ISGE
] = nir_op_ige
,
1445 [TGSI_OPCODE_ISHR
] = nir_op_ishr
,
1446 [TGSI_OPCODE_ISLT
] = nir_op_ilt
,
1447 [TGSI_OPCODE_F2U
] = nir_op_f2u
,
1448 [TGSI_OPCODE_U2F
] = nir_op_u2f
,
1449 [TGSI_OPCODE_UADD
] = nir_op_iadd
,
1450 [TGSI_OPCODE_UDIV
] = nir_op_udiv
,
1451 [TGSI_OPCODE_UMAD
] = 0,
1452 [TGSI_OPCODE_UMAX
] = nir_op_umax
,
1453 [TGSI_OPCODE_UMIN
] = nir_op_umin
,
1454 [TGSI_OPCODE_UMOD
] = nir_op_umod
,
1455 [TGSI_OPCODE_UMUL
] = nir_op_imul
,
1456 [TGSI_OPCODE_USEQ
] = nir_op_ieq
,
1457 [TGSI_OPCODE_USGE
] = nir_op_uge
,
1458 [TGSI_OPCODE_USHR
] = nir_op_ushr
,
1459 [TGSI_OPCODE_USLT
] = nir_op_ult
,
1460 [TGSI_OPCODE_USNE
] = nir_op_ine
,
1462 [TGSI_OPCODE_SWITCH
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1463 [TGSI_OPCODE_CASE
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1464 [TGSI_OPCODE_DEFAULT
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1465 [TGSI_OPCODE_ENDSWITCH
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1467 /* XXX: SAMPLE opcodes */
1469 [TGSI_OPCODE_UARL
] = nir_op_imov
,
1470 [TGSI_OPCODE_UCMP
] = 0,
1471 [TGSI_OPCODE_IABS
] = nir_op_iabs
,
1472 [TGSI_OPCODE_ISSG
] = nir_op_isign
,
1476 [TGSI_OPCODE_TEX2
] = 0,
1477 [TGSI_OPCODE_TXB2
] = 0,
1478 [TGSI_OPCODE_TXL2
] = 0,
1480 [TGSI_OPCODE_IMUL_HI
] = nir_op_imul_high
,
1481 [TGSI_OPCODE_UMUL_HI
] = nir_op_umul_high
,
1483 [TGSI_OPCODE_TG4
] = 0,
1484 [TGSI_OPCODE_LODQ
] = 0, /* XXX */
1486 [TGSI_OPCODE_IBFE
] = nir_op_ibitfield_extract
,
1487 [TGSI_OPCODE_UBFE
] = nir_op_ubitfield_extract
,
1488 [TGSI_OPCODE_BFI
] = nir_op_bitfield_insert
,
1489 [TGSI_OPCODE_BREV
] = nir_op_bitfield_reverse
,
1490 [TGSI_OPCODE_POPC
] = nir_op_bit_count
,
1491 [TGSI_OPCODE_LSB
] = nir_op_find_lsb
,
1492 [TGSI_OPCODE_IMSB
] = nir_op_ifind_msb
,
1493 [TGSI_OPCODE_UMSB
] = nir_op_ifind_msb
, /* XXX: signed vs unsigned */
1495 [TGSI_OPCODE_INTERP_CENTROID
] = 0, /* XXX */
1496 [TGSI_OPCODE_INTERP_SAMPLE
] = 0, /* XXX */
1497 [TGSI_OPCODE_INTERP_OFFSET
] = 0, /* XXX */
1501 ttn_emit_instruction(struct ttn_compile
*c
)
1503 nir_builder
*b
= &c
->build
;
1504 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
1506 unsigned tgsi_op
= tgsi_inst
->Instruction
.Opcode
;
1507 struct tgsi_full_dst_register
*tgsi_dst
= &tgsi_inst
->Dst
[0];
1509 if (tgsi_op
== TGSI_OPCODE_END
)
1512 nir_ssa_def
*src
[TGSI_FULL_MAX_SRC_REGISTERS
];
1513 for (i
= 0; i
< tgsi_inst
->Instruction
.NumSrcRegs
; i
++) {
1514 src
[i
] = ttn_get_src(c
, &tgsi_inst
->Src
[i
]);
1516 nir_alu_dest dest
= ttn_get_dest(c
, tgsi_dst
);
1519 case TGSI_OPCODE_RSQ
:
1520 ttn_move_dest(b
, dest
, nir_frsq(b
, ttn_channel(b
, src
[0], X
)));
1523 case TGSI_OPCODE_SQRT
:
1524 ttn_move_dest(b
, dest
, nir_fsqrt(b
, ttn_channel(b
, src
[0], X
)));
1527 case TGSI_OPCODE_RCP
:
1528 ttn_move_dest(b
, dest
, nir_frcp(b
, ttn_channel(b
, src
[0], X
)));
1531 case TGSI_OPCODE_EX2
:
1532 ttn_move_dest(b
, dest
, nir_fexp2(b
, ttn_channel(b
, src
[0], X
)));
1535 case TGSI_OPCODE_LG2
:
1536 ttn_move_dest(b
, dest
, nir_flog2(b
, ttn_channel(b
, src
[0], X
)));
1539 case TGSI_OPCODE_POW
:
1540 ttn_move_dest(b
, dest
, nir_fpow(b
,
1541 ttn_channel(b
, src
[0], X
),
1542 ttn_channel(b
, src
[1], X
)));
1545 case TGSI_OPCODE_COS
:
1546 ttn_move_dest(b
, dest
, nir_fcos(b
, ttn_channel(b
, src
[0], X
)));
1549 case TGSI_OPCODE_SIN
:
1550 ttn_move_dest(b
, dest
, nir_fsin(b
, ttn_channel(b
, src
[0], X
)));
1553 case TGSI_OPCODE_ARL
:
1554 ttn_arl(b
, op_trans
[tgsi_op
], dest
, src
);
1557 case TGSI_OPCODE_EXP
:
1558 ttn_exp(b
, op_trans
[tgsi_op
], dest
, src
);
1561 case TGSI_OPCODE_LOG
:
1562 ttn_log(b
, op_trans
[tgsi_op
], dest
, src
);
1565 case TGSI_OPCODE_DST
:
1566 ttn_dst(b
, op_trans
[tgsi_op
], dest
, src
);
1569 case TGSI_OPCODE_LIT
:
1570 ttn_lit(b
, op_trans
[tgsi_op
], dest
, src
);
1573 case TGSI_OPCODE_CLAMP
:
1574 ttn_clamp(b
, op_trans
[tgsi_op
], dest
, src
);
1577 case TGSI_OPCODE_XPD
:
1578 ttn_xpd(b
, op_trans
[tgsi_op
], dest
, src
);
1581 case TGSI_OPCODE_DP2
:
1582 ttn_dp2(b
, op_trans
[tgsi_op
], dest
, src
);
1585 case TGSI_OPCODE_DP3
:
1586 ttn_dp3(b
, op_trans
[tgsi_op
], dest
, src
);
1589 case TGSI_OPCODE_DP4
:
1590 ttn_dp4(b
, op_trans
[tgsi_op
], dest
, src
);
1593 case TGSI_OPCODE_DP2A
:
1594 ttn_dp2a(b
, op_trans
[tgsi_op
], dest
, src
);
1597 case TGSI_OPCODE_DPH
:
1598 ttn_dph(b
, op_trans
[tgsi_op
], dest
, src
);
1601 case TGSI_OPCODE_UMAD
:
1602 ttn_umad(b
, op_trans
[tgsi_op
], dest
, src
);
1605 case TGSI_OPCODE_LRP
:
1606 ttn_move_dest(b
, dest
, nir_flrp(b
, src
[2], src
[1], src
[0]));
1609 case TGSI_OPCODE_KILL
:
1610 ttn_kill(b
, op_trans
[tgsi_op
], dest
, src
);
1613 case TGSI_OPCODE_ARR
:
1614 ttn_arr(b
, op_trans
[tgsi_op
], dest
, src
);
1617 case TGSI_OPCODE_CMP
:
1618 ttn_cmp(b
, op_trans
[tgsi_op
], dest
, src
);
1621 case TGSI_OPCODE_UCMP
:
1622 ttn_ucmp(b
, op_trans
[tgsi_op
], dest
, src
);
1625 case TGSI_OPCODE_SCS
:
1626 ttn_scs(b
, op_trans
[tgsi_op
], dest
, src
);
1629 case TGSI_OPCODE_SGT
:
1630 ttn_sgt(b
, op_trans
[tgsi_op
], dest
, src
);
1633 case TGSI_OPCODE_SLE
:
1634 ttn_sle(b
, op_trans
[tgsi_op
], dest
, src
);
1637 case TGSI_OPCODE_KILL_IF
:
1638 ttn_kill_if(b
, op_trans
[tgsi_op
], dest
, src
);
1641 case TGSI_OPCODE_TEX
:
1642 case TGSI_OPCODE_TXP
:
1643 case TGSI_OPCODE_TXL
:
1644 case TGSI_OPCODE_TXB
:
1645 case TGSI_OPCODE_TXD
:
1646 case TGSI_OPCODE_TXL2
:
1647 case TGSI_OPCODE_TXB2
:
1648 case TGSI_OPCODE_TXQ_LZ
:
1649 case TGSI_OPCODE_TXF
:
1650 case TGSI_OPCODE_TG4
:
1651 ttn_tex(c
, dest
, src
);
1654 case TGSI_OPCODE_TXQ
:
1655 ttn_txq(c
, dest
, src
);
1658 case TGSI_OPCODE_NOP
:
1661 case TGSI_OPCODE_IF
:
1662 ttn_if(c
, src
[0], false);
1665 case TGSI_OPCODE_UIF
:
1666 ttn_if(c
, src
[0], true);
1669 case TGSI_OPCODE_ELSE
:
1673 case TGSI_OPCODE_ENDIF
:
1677 case TGSI_OPCODE_BGNLOOP
:
1681 case TGSI_OPCODE_BRK
:
1685 case TGSI_OPCODE_CONT
:
1689 case TGSI_OPCODE_ENDLOOP
:
1694 if (op_trans
[tgsi_op
] != 0 || tgsi_op
== TGSI_OPCODE_MOV
) {
1695 ttn_alu(b
, op_trans
[tgsi_op
], dest
, src
);
1697 fprintf(stderr
, "unknown TGSI opcode: %s\n",
1698 tgsi_get_opcode_name(tgsi_op
));
1704 if (tgsi_inst
->Instruction
.Saturate
) {
1705 assert(!dest
.dest
.is_ssa
);
1706 ttn_move_dest(b
, dest
, nir_fsat(b
, ttn_src_for_dest(b
, &dest
)));
1709 /* if the dst has a matching var, append store_global to move
1710 * output from reg to var
1712 nir_variable
*var
= ttn_get_var(c
, tgsi_dst
);
1714 unsigned index
= tgsi_dst
->Register
.Index
;
1715 unsigned offset
= c
->temp_regs
[index
].offset
;
1716 nir_intrinsic_instr
*store
=
1717 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_var
);
1718 struct tgsi_ind_register
*indirect
= tgsi_dst
->Register
.Indirect
?
1719 &tgsi_dst
->Indirect
: NULL
;
1721 store
->num_components
= 4;
1722 store
->variables
[0] = ttn_array_deref(c
, store
, var
, offset
, indirect
);
1723 store
->src
[0] = nir_src_for_reg(dest
.dest
.reg
.reg
);
1725 nir_instr_insert_after_cf_list(b
->cf_node_list
, &store
->instr
);
1730 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
1731 * variables at the end of the shader.
1733 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
1734 * written, because there's no output load intrinsic, which means we couldn't
1735 * handle writemasks.
1738 ttn_add_output_stores(struct ttn_compile
*c
)
1740 nir_builder
*b
= &c
->build
;
1742 foreach_list_typed(nir_variable
, var
, node
, &b
->shader
->outputs
) {
1743 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1746 for (i
= 0; i
< array_len
; i
++) {
1747 nir_intrinsic_instr
*store
=
1748 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
1749 unsigned loc
= var
->data
.driver_location
+ i
;
1750 store
->num_components
= 4;
1751 store
->const_index
[0] = loc
;
1752 store
->src
[0].reg
.reg
= c
->output_regs
[loc
].reg
;
1753 store
->src
[0].reg
.base_offset
= c
->output_regs
[loc
].offset
;
1754 nir_instr_insert_after_cf_list(b
->cf_node_list
, &store
->instr
);
1760 tgsi_to_nir(const void *tgsi_tokens
,
1761 const nir_shader_compiler_options
*options
)
1763 struct tgsi_parse_context parser
;
1764 struct tgsi_shader_info scan
;
1765 struct ttn_compile
*c
;
1766 struct nir_shader
*s
;
1769 c
= rzalloc(NULL
, struct ttn_compile
);
1770 s
= nir_shader_create(NULL
, options
);
1772 nir_function
*func
= nir_function_create(s
, "main");
1773 nir_function_overload
*overload
= nir_function_overload_create(func
);
1774 nir_function_impl
*impl
= nir_function_impl_create(overload
);
1776 nir_builder_init(&c
->build
, impl
);
1777 nir_builder_insert_after_cf_list(&c
->build
, &impl
->body
);
1779 tgsi_scan_shader(tgsi_tokens
, &scan
);
1782 s
->num_inputs
= scan
.file_max
[TGSI_FILE_INPUT
] + 1;
1783 s
->num_uniforms
= scan
.const_file_max
[0] + 1;
1784 s
->num_outputs
= scan
.file_max
[TGSI_FILE_OUTPUT
] + 1;
1786 c
->output_regs
= rzalloc_array(c
, struct ttn_reg_info
,
1787 scan
.file_max
[TGSI_FILE_OUTPUT
] + 1);
1788 c
->temp_regs
= rzalloc_array(c
, struct ttn_reg_info
,
1789 scan
.file_max
[TGSI_FILE_TEMPORARY
] + 1);
1790 c
->imm_defs
= rzalloc_array(c
, nir_ssa_def
*,
1791 scan
.file_max
[TGSI_FILE_IMMEDIATE
] + 1);
1793 c
->num_samp_types
= scan
.file_max
[TGSI_FILE_SAMPLER_VIEW
] + 1;
1794 c
->samp_types
= rzalloc_array(c
, nir_alu_type
, c
->num_samp_types
);
1796 c
->if_stack
= rzalloc_array(c
, struct exec_list
*,
1797 (scan
.opcode_count
[TGSI_OPCODE_IF
] +
1798 scan
.opcode_count
[TGSI_OPCODE_UIF
]) * 2);
1799 c
->loop_stack
= rzalloc_array(c
, struct exec_list
*,
1800 scan
.opcode_count
[TGSI_OPCODE_BGNLOOP
]);
1802 ret
= tgsi_parse_init(&parser
, tgsi_tokens
);
1803 assert(ret
== TGSI_PARSE_OK
);
1805 while (!tgsi_parse_end_of_tokens(&parser
)) {
1806 tgsi_parse_token(&parser
);
1807 c
->token
= &parser
.FullToken
;
1809 switch (parser
.FullToken
.Token
.Type
) {
1810 case TGSI_TOKEN_TYPE_DECLARATION
:
1811 ttn_emit_declaration(c
);
1814 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1815 ttn_emit_instruction(c
);
1818 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1819 ttn_emit_immediate(c
);
1824 tgsi_parse_free(&parser
);
1826 ttn_add_output_stores(c
);