2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/ralloc.h"
26 #include "glsl/nir/nir.h"
27 #include "glsl/nir/nir_builder.h"
28 #include "glsl/list.h"
29 #include "glsl/shader_enums.h"
31 #include "nir/tgsi_to_nir.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_dump.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_scan.h"
37 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
45 /** nir register containing this TGSI index. */
48 /** Offset (in vec4s) from the start of var for this TGSI index. */
53 union tgsi_full_token
*token
;
55 struct tgsi_shader_info
*scan
;
57 struct ttn_reg_info
*output_regs
;
58 struct ttn_reg_info
*temp_regs
;
59 nir_ssa_def
**imm_defs
;
61 nir_register
*addr_reg
;
64 * Stack of cf_node_lists where instructions should be pushed as we pop
65 * back out of the control flow stack.
67 * For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else
68 * instructions should be placed, and if_stack[if_stack_pos - 1] has where
69 * the next instructions outside of the if/then/else block go.
71 struct exec_list
**if_stack
;
72 unsigned if_stack_pos
;
75 * Stack of cf_node_lists where instructions should be pushed as we pop
76 * back out of the control flow stack.
78 * loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside
81 struct exec_list
**loop_stack
;
82 unsigned loop_stack_pos
;
84 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
88 #define ttn_swizzle(b, src, x, y, z, w) \
89 nir_swizzle(b, src, SWIZ(x, y, z, w), 4, false)
90 #define ttn_channel(b, src, swiz) \
91 nir_swizzle(b, src, SWIZ(swiz, swiz, swiz, swiz), 1, false)
94 ttn_src_for_dest(nir_builder
*b
, nir_alu_dest
*dest
)
97 memset(&src
, 0, sizeof(src
));
99 if (dest
->dest
.is_ssa
)
100 src
.src
= nir_src_for_ssa(&dest
->dest
.ssa
);
102 assert(!dest
->dest
.reg
.indirect
);
103 src
.src
= nir_src_for_reg(dest
->dest
.reg
.reg
);
104 src
.src
.reg
.base_offset
= dest
->dest
.reg
.base_offset
;
107 for (int i
= 0; i
< 4; i
++)
110 return nir_fmov_alu(b
, src
, 4);
114 ttn_emit_declaration(struct ttn_compile
*c
)
116 nir_builder
*b
= &c
->build
;
117 struct tgsi_full_declaration
*decl
= &c
->token
->FullDeclaration
;
118 unsigned array_size
= decl
->Range
.Last
- decl
->Range
.First
+ 1;
119 unsigned file
= decl
->Declaration
.File
;
122 if (file
== TGSI_FILE_TEMPORARY
) {
123 if (decl
->Declaration
.Array
) {
124 /* for arrays, we create variables instead of registers: */
125 nir_variable
*var
= rzalloc(b
->shader
, nir_variable
);
127 var
->type
= glsl_array_type(glsl_vec4_type(), array_size
);
128 var
->data
.mode
= nir_var_global
;
129 var
->name
= ralloc_asprintf(var
, "arr_%d", decl
->Array
.ArrayID
);
131 exec_list_push_tail(&b
->shader
->globals
, &var
->node
);
133 for (i
= 0; i
< array_size
; i
++) {
134 /* point all the matching slots to the same var,
135 * with appropriate offset set, mostly just so
136 * we know what to do when tgsi does a non-indirect
139 c
->temp_regs
[decl
->Range
.First
+ i
].reg
= NULL
;
140 c
->temp_regs
[decl
->Range
.First
+ i
].var
= var
;
141 c
->temp_regs
[decl
->Range
.First
+ i
].offset
= i
;
144 for (i
= 0; i
< array_size
; i
++) {
145 nir_register
*reg
= nir_local_reg_create(b
->impl
);
146 reg
->num_components
= 4;
147 c
->temp_regs
[decl
->Range
.First
+ i
].reg
= reg
;
148 c
->temp_regs
[decl
->Range
.First
+ i
].var
= NULL
;
149 c
->temp_regs
[decl
->Range
.First
+ i
].offset
= 0;
152 } else if (file
== TGSI_FILE_ADDRESS
) {
153 c
->addr_reg
= nir_local_reg_create(b
->impl
);
154 c
->addr_reg
->num_components
= 4;
155 } else if (file
== TGSI_FILE_SYSTEM_VALUE
) {
156 /* Nothing to record for system values. */
157 } else if (file
== TGSI_FILE_SAMPLER
) {
158 /* Nothing to record for samplers. */
161 assert(file
== TGSI_FILE_INPUT
||
162 file
== TGSI_FILE_OUTPUT
||
163 file
== TGSI_FILE_CONSTANT
);
165 var
= rzalloc(b
->shader
, nir_variable
);
166 var
->data
.driver_location
= decl
->Range
.First
;
168 var
->type
= glsl_vec4_type();
170 var
->type
= glsl_array_type(var
->type
, array_size
);
173 case TGSI_FILE_INPUT
:
174 var
->data
.read_only
= true;
175 var
->data
.mode
= nir_var_shader_in
;
176 var
->name
= ralloc_asprintf(var
, "in_%d", decl
->Range
.First
);
178 /* We should probably translate to a VERT_ATTRIB_* or VARYING_SLOT_*
179 * instead, but nothing in NIR core is looking at the value
180 * currently, and this is less change to drivers.
182 var
->data
.location
= decl
->Semantic
.Name
;
183 var
->data
.index
= decl
->Semantic
.Index
;
185 /* We definitely need to translate the interpolation field, because
186 * nir_print will decode it.
188 switch (decl
->Interp
.Interpolate
) {
189 case TGSI_INTERPOLATE_CONSTANT
:
190 var
->data
.interpolation
= INTERP_QUALIFIER_FLAT
;
192 case TGSI_INTERPOLATE_LINEAR
:
193 var
->data
.interpolation
= INTERP_QUALIFIER_NOPERSPECTIVE
;
195 case TGSI_INTERPOLATE_PERSPECTIVE
:
196 var
->data
.interpolation
= INTERP_QUALIFIER_SMOOTH
;
200 exec_list_push_tail(&b
->shader
->inputs
, &var
->node
);
202 case TGSI_FILE_OUTPUT
: {
203 /* Since we can't load from outputs in the IR, we make temporaries
204 * for the outputs and emit stores to the real outputs at the end of
207 nir_register
*reg
= nir_local_reg_create(b
->impl
);
208 reg
->num_components
= 4;
210 reg
->num_array_elems
= array_size
;
212 var
->data
.mode
= nir_var_shader_out
;
213 var
->name
= ralloc_asprintf(var
, "out_%d", decl
->Range
.First
);
215 var
->data
.location
= decl
->Semantic
.Name
;
216 var
->data
.index
= decl
->Semantic
.Index
;
218 for (i
= 0; i
< array_size
; i
++) {
219 c
->output_regs
[decl
->Range
.First
+ i
].offset
= i
;
220 c
->output_regs
[decl
->Range
.First
+ i
].reg
= reg
;
223 exec_list_push_tail(&b
->shader
->outputs
, &var
->node
);
226 case TGSI_FILE_CONSTANT
:
227 var
->data
.mode
= nir_var_uniform
;
228 var
->name
= ralloc_asprintf(var
, "uniform_%d", decl
->Range
.First
);
230 exec_list_push_tail(&b
->shader
->uniforms
, &var
->node
);
233 unreachable("bad declaration file");
241 ttn_emit_immediate(struct ttn_compile
*c
)
243 nir_builder
*b
= &c
->build
;
244 struct tgsi_full_immediate
*tgsi_imm
= &c
->token
->FullImmediate
;
245 nir_load_const_instr
*load_const
;
248 load_const
= nir_load_const_instr_create(b
->shader
, 4);
249 c
->imm_defs
[c
->next_imm
] = &load_const
->def
;
252 for (i
= 0; i
< 4; i
++)
253 load_const
->value
.u
[i
] = tgsi_imm
->u
[i
].Uint
;
255 nir_instr_insert_after_cf_list(b
->cf_node_list
, &load_const
->instr
);
259 ttn_src_for_indirect(struct ttn_compile
*c
, struct tgsi_ind_register
*indirect
);
261 /* generate either a constant or indirect deref chain for accessing an
264 static nir_deref_var
*
265 ttn_array_deref(struct ttn_compile
*c
, nir_intrinsic_instr
*instr
,
266 nir_variable
*var
, unsigned offset
,
267 struct tgsi_ind_register
*indirect
)
269 nir_deref_var
*deref
= nir_deref_var_create(instr
, var
);
270 nir_deref_array
*arr
= nir_deref_array_create(deref
);
272 arr
->base_offset
= offset
;
273 arr
->deref
.type
= glsl_get_array_element(var
->type
);
276 arr
->deref_array_type
= nir_deref_array_type_indirect
;
277 arr
->indirect
= ttn_src_for_indirect(c
, indirect
);
279 arr
->deref_array_type
= nir_deref_array_type_direct
;
282 deref
->deref
.child
= &arr
->deref
;
288 ttn_src_for_file_and_index(struct ttn_compile
*c
, unsigned file
, unsigned index
,
289 struct tgsi_ind_register
*indirect
)
291 nir_builder
*b
= &c
->build
;
294 memset(&src
, 0, sizeof(src
));
297 case TGSI_FILE_TEMPORARY
:
298 if (c
->temp_regs
[index
].var
) {
299 unsigned offset
= c
->temp_regs
[index
].offset
;
300 nir_variable
*var
= c
->temp_regs
[index
].var
;
301 nir_intrinsic_instr
*load
;
303 load
= nir_intrinsic_instr_create(b
->shader
,
304 nir_intrinsic_load_var
);
305 load
->num_components
= 4;
306 load
->variables
[0] = ttn_array_deref(c
, load
, var
, offset
, indirect
);
308 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, NULL
);
309 nir_instr_insert_after_cf_list(b
->cf_node_list
, &load
->instr
);
311 src
= nir_src_for_ssa(&load
->dest
.ssa
);
315 src
.reg
.reg
= c
->temp_regs
[index
].reg
;
319 case TGSI_FILE_ADDRESS
:
320 src
.reg
.reg
= c
->addr_reg
;
323 case TGSI_FILE_IMMEDIATE
:
324 src
= nir_src_for_ssa(c
->imm_defs
[index
]);
328 case TGSI_FILE_SYSTEM_VALUE
: {
329 nir_intrinsic_instr
*load
;
333 switch (c
->scan
->system_value_semantic_name
[index
]) {
334 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
335 op
= nir_intrinsic_load_vertex_id_zero_base
;
337 case TGSI_SEMANTIC_VERTEXID
:
338 op
= nir_intrinsic_load_vertex_id
;
340 case TGSI_SEMANTIC_BASEVERTEX
:
341 op
= nir_intrinsic_load_base_vertex
;
343 case TGSI_SEMANTIC_INSTANCEID
:
344 op
= nir_intrinsic_load_instance_id
;
347 unreachable("bad system value");
350 load
= nir_intrinsic_instr_create(b
->shader
, op
);
351 load
->num_components
= ncomp
;
353 nir_ssa_dest_init(&load
->instr
, &load
->dest
, ncomp
, NULL
);
354 nir_instr_insert_after_cf_list(b
->cf_node_list
, &load
->instr
);
356 src
= nir_src_for_ssa(&load
->dest
.ssa
);
360 case TGSI_FILE_INPUT
:
361 case TGSI_FILE_CONSTANT
: {
362 nir_intrinsic_instr
*load
;
366 case TGSI_FILE_INPUT
:
367 op
= indirect
? nir_intrinsic_load_input_indirect
:
368 nir_intrinsic_load_input
;
370 case TGSI_FILE_CONSTANT
:
371 op
= indirect
? nir_intrinsic_load_uniform_indirect
:
372 nir_intrinsic_load_uniform
;
375 unreachable("No other load files supported");
379 load
= nir_intrinsic_instr_create(b
->shader
, op
);
381 load
->num_components
= 4;
382 load
->const_index
[0] = index
;
383 load
->const_index
[1] = 1;
385 load
->src
[0] = ttn_src_for_indirect(c
, indirect
);
387 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, NULL
);
388 nir_instr_insert_after_cf_list(b
->cf_node_list
, &load
->instr
);
390 src
= nir_src_for_ssa(&load
->dest
.ssa
);
395 unreachable("bad src file");
403 ttn_src_for_indirect(struct ttn_compile
*c
, struct tgsi_ind_register
*indirect
)
405 nir_builder
*b
= &c
->build
;
407 memset(&src
, 0, sizeof(src
));
408 for (int i
= 0; i
< 4; i
++)
409 src
.swizzle
[i
] = indirect
->Swizzle
;
410 src
.src
= ttn_src_for_file_and_index(c
,
412 indirect
->Index
, NULL
);
413 return nir_src_for_ssa(nir_imov_alu(b
, src
, 1));
417 ttn_get_dest(struct ttn_compile
*c
, struct tgsi_full_dst_register
*tgsi_fdst
)
419 struct tgsi_dst_register
*tgsi_dst
= &tgsi_fdst
->Register
;
421 unsigned index
= tgsi_dst
->Index
;
423 memset(&dest
, 0, sizeof(dest
));
425 if (tgsi_dst
->File
== TGSI_FILE_TEMPORARY
) {
426 if (c
->temp_regs
[index
].var
) {
427 nir_builder
*b
= &c
->build
;
428 nir_intrinsic_instr
*load
;
429 struct tgsi_ind_register
*indirect
=
430 tgsi_dst
->Indirect
? &tgsi_fdst
->Indirect
: NULL
;
433 /* this works, because TGSI will give us a base offset
434 * (in case of indirect index) that points back into
435 * the array. Access can be direct or indirect, we
436 * don't really care. Just create a one-shot dst reg
437 * that will get store_var'd back into the array var
438 * at the end of ttn_emit_instruction()
440 reg
= nir_local_reg_create(c
->build
.impl
);
441 reg
->num_components
= 4;
442 dest
.dest
.reg
.reg
= reg
;
443 dest
.dest
.reg
.base_offset
= 0;
445 /* since the alu op might not write to all components
446 * of the temporary, we must first do a load_var to
447 * get the previous array elements into the register.
448 * This is one area that NIR could use a bit of
449 * improvement (or opt pass to clean up the mess
450 * once things are scalarized)
453 load
= nir_intrinsic_instr_create(c
->build
.shader
,
454 nir_intrinsic_load_var
);
455 load
->num_components
= 4;
457 ttn_array_deref(c
, load
, c
->temp_regs
[index
].var
,
458 c
->temp_regs
[index
].offset
,
461 load
->dest
= nir_dest_for_reg(reg
);
463 nir_instr_insert_after_cf_list(b
->cf_node_list
, &load
->instr
);
465 assert(!tgsi_dst
->Indirect
);
466 dest
.dest
.reg
.reg
= c
->temp_regs
[index
].reg
;
467 dest
.dest
.reg
.base_offset
= c
->temp_regs
[index
].offset
;
469 } else if (tgsi_dst
->File
== TGSI_FILE_OUTPUT
) {
470 dest
.dest
.reg
.reg
= c
->output_regs
[index
].reg
;
471 dest
.dest
.reg
.base_offset
= c
->output_regs
[index
].offset
;
472 } else if (tgsi_dst
->File
== TGSI_FILE_ADDRESS
) {
474 dest
.dest
.reg
.reg
= c
->addr_reg
;
477 dest
.write_mask
= tgsi_dst
->WriteMask
;
478 dest
.saturate
= false;
480 if (tgsi_dst
->Indirect
&& (tgsi_dst
->File
!= TGSI_FILE_TEMPORARY
)) {
481 nir_src
*indirect
= ralloc(c
->build
.shader
, nir_src
);
482 *indirect
= ttn_src_for_indirect(c
, &tgsi_fdst
->Indirect
);
483 dest
.dest
.reg
.indirect
= indirect
;
489 static nir_variable
*
490 ttn_get_var(struct ttn_compile
*c
, struct tgsi_full_dst_register
*tgsi_fdst
)
492 struct tgsi_dst_register
*tgsi_dst
= &tgsi_fdst
->Register
;
493 unsigned index
= tgsi_dst
->Index
;
495 if (tgsi_dst
->File
== TGSI_FILE_TEMPORARY
) {
496 /* we should not have an indirect when there is no var! */
497 if (!c
->temp_regs
[index
].var
)
498 assert(!tgsi_dst
->Indirect
);
499 return c
->temp_regs
[index
].var
;
506 ttn_get_src(struct ttn_compile
*c
, struct tgsi_full_src_register
*tgsi_fsrc
)
508 nir_builder
*b
= &c
->build
;
509 struct tgsi_src_register
*tgsi_src
= &tgsi_fsrc
->Register
;
510 unsigned tgsi_opcode
= c
->token
->FullInstruction
.Instruction
.Opcode
;
511 unsigned tgsi_src_type
= tgsi_opcode_infer_src_type(tgsi_opcode
);
512 bool src_is_float
= !(tgsi_src_type
== TGSI_TYPE_SIGNED
||
513 tgsi_src_type
== TGSI_TYPE_UNSIGNED
);
516 memset(&src
, 0, sizeof(src
));
518 if (tgsi_src
->File
== TGSI_FILE_NULL
) {
519 return nir_imm_float(b
, 0.0);
520 } else if (tgsi_src
->File
== TGSI_FILE_SAMPLER
) {
521 /* Only the index of the sampler gets used in texturing, and it will
522 * handle looking that up on its own instead of using the nir_alu_src.
524 assert(!tgsi_src
->Indirect
);
527 src
.src
= ttn_src_for_file_and_index(c
,
530 (tgsi_src
->Indirect
?
531 &tgsi_fsrc
->Indirect
: NULL
));
534 src
.swizzle
[0] = tgsi_src
->SwizzleX
;
535 src
.swizzle
[1] = tgsi_src
->SwizzleY
;
536 src
.swizzle
[2] = tgsi_src
->SwizzleZ
;
537 src
.swizzle
[3] = tgsi_src
->SwizzleW
;
539 nir_ssa_def
*def
= nir_fmov_alu(b
, src
, 4);
541 if (tgsi_src
->Absolute
) {
543 def
= nir_fabs(b
, def
);
545 def
= nir_iabs(b
, def
);
548 if (tgsi_src
->Negate
) {
550 def
= nir_fneg(b
, def
);
552 def
= nir_ineg(b
, def
);
559 ttn_alu(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
561 unsigned num_srcs
= nir_op_infos
[op
].num_inputs
;
562 nir_alu_instr
*instr
= nir_alu_instr_create(b
->shader
, op
);
565 for (i
= 0; i
< num_srcs
; i
++)
566 instr
->src
[i
].src
= nir_src_for_ssa(src
[i
]);
569 nir_instr_insert_after_cf_list(b
->cf_node_list
, &instr
->instr
);
573 ttn_move_dest_masked(nir_builder
*b
, nir_alu_dest dest
,
574 nir_ssa_def
*def
, unsigned write_mask
)
576 if (!(dest
.write_mask
& write_mask
))
579 nir_alu_instr
*mov
= nir_alu_instr_create(b
->shader
, nir_op_imov
);
581 mov
->dest
.write_mask
&= write_mask
;
582 mov
->src
[0].src
= nir_src_for_ssa(def
);
583 for (unsigned i
= def
->num_components
; i
< 4; i
++)
584 mov
->src
[0].swizzle
[i
] = def
->num_components
- 1;
585 nir_instr_insert_after_cf_list(b
->cf_node_list
, &mov
->instr
);
589 ttn_move_dest(nir_builder
*b
, nir_alu_dest dest
, nir_ssa_def
*def
)
591 ttn_move_dest_masked(b
, dest
, def
, TGSI_WRITEMASK_XYZW
);
595 ttn_arl(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
597 ttn_move_dest(b
, dest
, nir_f2i(b
, nir_ffloor(b
, src
[0])));
600 /* EXP - Approximate Exponential Base 2
601 * dst.x = 2^{\lfloor src.x\rfloor}
602 * dst.y = src.x - \lfloor src.x\rfloor
607 ttn_exp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
609 nir_ssa_def
*srcx
= ttn_channel(b
, src
[0], X
);
611 ttn_move_dest_masked(b
, dest
, nir_fexp2(b
, nir_ffloor(b
, srcx
)),
613 ttn_move_dest_masked(b
, dest
, nir_fsub(b
, srcx
, nir_ffloor(b
, srcx
)),
615 ttn_move_dest_masked(b
, dest
, nir_fexp2(b
, srcx
), TGSI_WRITEMASK_Z
);
616 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
619 /* LOG - Approximate Logarithm Base 2
620 * dst.x = \lfloor\log_2{|src.x|}\rfloor
621 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
622 * dst.z = \log_2{|src.x|}
626 ttn_log(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
628 nir_ssa_def
*abs_srcx
= nir_fabs(b
, ttn_channel(b
, src
[0], X
));
629 nir_ssa_def
*log2
= nir_flog2(b
, abs_srcx
);
631 ttn_move_dest_masked(b
, dest
, nir_ffloor(b
, log2
), TGSI_WRITEMASK_X
);
632 ttn_move_dest_masked(b
, dest
,
633 nir_fdiv(b
, abs_srcx
, nir_fexp2(b
, nir_ffloor(b
, log2
))),
635 ttn_move_dest_masked(b
, dest
, nir_flog2(b
, abs_srcx
), TGSI_WRITEMASK_Z
);
636 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
639 /* DST - Distance Vector
641 * dst.y = src0.y \times src1.y
646 ttn_dst(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
648 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_X
);
649 ttn_move_dest_masked(b
, dest
, nir_fmul(b
, src
[0], src
[1]), TGSI_WRITEMASK_Y
);
650 ttn_move_dest_masked(b
, dest
, nir_fmov(b
, src
[0]), TGSI_WRITEMASK_Z
);
651 ttn_move_dest_masked(b
, dest
, nir_fmov(b
, src
[1]), TGSI_WRITEMASK_W
);
654 /* LIT - Light Coefficients
656 * dst.y = max(src.x, 0.0)
657 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
661 ttn_lit(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
663 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_XW
);
665 ttn_move_dest_masked(b
, dest
, nir_fmax(b
, ttn_channel(b
, src
[0], X
),
666 nir_imm_float(b
, 0.0)), TGSI_WRITEMASK_Y
);
668 if (dest
.write_mask
& TGSI_WRITEMASK_Z
) {
669 nir_ssa_def
*src0_y
= ttn_channel(b
, src
[0], Y
);
670 nir_ssa_def
*wclamp
= nir_fmax(b
, nir_fmin(b
, ttn_channel(b
, src
[0], W
),
671 nir_imm_float(b
, 128.0)),
672 nir_imm_float(b
, -128.0));
673 nir_ssa_def
*pow
= nir_fpow(b
, nir_fmax(b
, src0_y
, nir_imm_float(b
, 0.0)),
676 ttn_move_dest_masked(b
, dest
,
679 nir_imm_float(b
, 0.0),
680 ttn_channel(b
, src
[0], X
)),
681 nir_imm_float(b
, 0.0),
688 * dst.x = \cos{src.x}
689 * dst.y = \sin{src.x}
694 ttn_scs(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
696 ttn_move_dest_masked(b
, dest
, nir_fcos(b
, ttn_channel(b
, src
[0], X
)),
698 ttn_move_dest_masked(b
, dest
, nir_fsin(b
, ttn_channel(b
, src
[0], X
)),
700 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 0.0), TGSI_WRITEMASK_Z
);
701 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
705 ttn_sle(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
707 ttn_move_dest(b
, dest
, nir_sge(b
, src
[1], src
[0]));
711 ttn_sgt(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
713 ttn_move_dest(b
, dest
, nir_slt(b
, src
[1], src
[0]));
717 ttn_clamp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
719 ttn_move_dest(b
, dest
, nir_fmin(b
, nir_fmax(b
, src
[0], src
[1]), src
[2]));
723 ttn_xpd(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
725 ttn_move_dest_masked(b
, dest
,
728 ttn_swizzle(b
, src
[0], Y
, Z
, X
, X
),
729 ttn_swizzle(b
, src
[1], Z
, X
, Y
, X
)),
731 ttn_swizzle(b
, src
[1], Y
, Z
, X
, X
),
732 ttn_swizzle(b
, src
[0], Z
, X
, Y
, X
))),
734 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
738 ttn_dp2a(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
740 ttn_move_dest(b
, dest
,
741 ttn_channel(b
, nir_fadd(b
, nir_fdot2(b
, src
[0], src
[1]),
747 ttn_dp2(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
749 ttn_move_dest(b
, dest
, nir_fdot2(b
, src
[0], src
[1]));
753 ttn_dp3(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
755 ttn_move_dest(b
, dest
, nir_fdot3(b
, src
[0], src
[1]));
759 ttn_dp4(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
761 ttn_move_dest(b
, dest
, nir_fdot4(b
, src
[0], src
[1]));
765 ttn_dph(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
767 ttn_move_dest(b
, dest
, nir_fadd(b
, nir_fdot3(b
, src
[0], src
[1]),
768 ttn_channel(b
, src
[1], W
)));
772 ttn_umad(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
774 ttn_move_dest(b
, dest
, nir_iadd(b
, nir_imul(b
, src
[0], src
[1]), src
[2]));
778 ttn_arr(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
780 ttn_move_dest(b
, dest
, nir_ffloor(b
, nir_fadd(b
, src
[0], nir_imm_float(b
, 0.5))));
784 ttn_cmp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
786 ttn_move_dest(b
, dest
, nir_bcsel(b
,
787 nir_flt(b
, src
[0], nir_imm_float(b
, 0.0)),
792 ttn_ucmp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
794 ttn_move_dest(b
, dest
, nir_bcsel(b
,
795 nir_ine(b
, src
[0], nir_imm_int(b
, 0)),
800 ttn_kill(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
802 nir_intrinsic_instr
*discard
=
803 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard
);
804 nir_instr_insert_after_cf_list(b
->cf_node_list
, &discard
->instr
);
808 ttn_kill_if(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
810 nir_ssa_def
*cmp
= nir_bany4(b
, nir_flt(b
, src
[0], nir_imm_float(b
, 0.0)));
811 nir_intrinsic_instr
*discard
=
812 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
813 discard
->src
[0] = nir_src_for_ssa(cmp
);
814 nir_instr_insert_after_cf_list(b
->cf_node_list
, &discard
->instr
);
818 ttn_if(struct ttn_compile
*c
, nir_ssa_def
*src
, bool is_uint
)
820 nir_builder
*b
= &c
->build
;
822 /* Save the outside-of-the-if-statement node list. */
823 c
->if_stack
[c
->if_stack_pos
] = b
->cf_node_list
;
826 src
= ttn_channel(b
, src
, X
);
828 nir_if
*if_stmt
= nir_if_create(b
->shader
);
830 if_stmt
->condition
= nir_src_for_ssa(nir_ine(b
, src
, nir_imm_int(b
, 0)));
832 if_stmt
->condition
= nir_src_for_ssa(nir_fne(b
, src
, nir_imm_int(b
, 0)));
834 nir_cf_node_insert_end(b
->cf_node_list
, &if_stmt
->cf_node
);
836 nir_builder_insert_after_cf_list(b
, &if_stmt
->then_list
);
838 c
->if_stack
[c
->if_stack_pos
] = &if_stmt
->else_list
;
843 ttn_else(struct ttn_compile
*c
)
845 nir_builder
*b
= &c
->build
;
847 nir_builder_insert_after_cf_list(b
, c
->if_stack
[c
->if_stack_pos
- 1]);
851 ttn_endif(struct ttn_compile
*c
)
853 nir_builder
*b
= &c
->build
;
855 c
->if_stack_pos
-= 2;
856 nir_builder_insert_after_cf_list(b
, c
->if_stack
[c
->if_stack_pos
]);
860 ttn_bgnloop(struct ttn_compile
*c
)
862 nir_builder
*b
= &c
->build
;
864 /* Save the outside-of-the-loop node list. */
865 c
->loop_stack
[c
->loop_stack_pos
] = b
->cf_node_list
;
868 nir_loop
*loop
= nir_loop_create(b
->shader
);
869 nir_cf_node_insert_end(b
->cf_node_list
, &loop
->cf_node
);
871 nir_builder_insert_after_cf_list(b
, &loop
->body
);
875 ttn_cont(nir_builder
*b
)
877 nir_jump_instr
*instr
= nir_jump_instr_create(b
->shader
, nir_jump_continue
);
878 nir_instr_insert_after_cf_list(b
->cf_node_list
, &instr
->instr
);
882 ttn_brk(nir_builder
*b
)
884 nir_jump_instr
*instr
= nir_jump_instr_create(b
->shader
, nir_jump_break
);
885 nir_instr_insert_after_cf_list(b
->cf_node_list
, &instr
->instr
);
889 ttn_endloop(struct ttn_compile
*c
)
891 nir_builder
*b
= &c
->build
;
894 nir_builder_insert_after_cf_list(b
, c
->loop_stack
[c
->loop_stack_pos
]);
898 setup_texture_info(nir_tex_instr
*instr
, unsigned texture
)
901 case TGSI_TEXTURE_1D
:
902 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
904 case TGSI_TEXTURE_1D_ARRAY
:
905 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
906 instr
->is_array
= true;
908 case TGSI_TEXTURE_SHADOW1D
:
909 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
910 instr
->is_shadow
= true;
912 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
913 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
914 instr
->is_shadow
= true;
915 instr
->is_array
= true;
917 case TGSI_TEXTURE_2D
:
918 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
920 case TGSI_TEXTURE_2D_ARRAY
:
921 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
922 instr
->is_array
= true;
924 case TGSI_TEXTURE_2D_MSAA
:
925 instr
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
927 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
928 instr
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
929 instr
->is_array
= true;
931 case TGSI_TEXTURE_SHADOW2D
:
932 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
933 instr
->is_shadow
= true;
935 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
936 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
937 instr
->is_shadow
= true;
938 instr
->is_array
= true;
940 case TGSI_TEXTURE_3D
:
941 instr
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
943 case TGSI_TEXTURE_CUBE
:
944 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
946 case TGSI_TEXTURE_CUBE_ARRAY
:
947 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
948 instr
->is_array
= true;
950 case TGSI_TEXTURE_SHADOWCUBE
:
951 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
952 instr
->is_shadow
= true;
954 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
955 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
956 instr
->is_shadow
= true;
957 instr
->is_array
= true;
959 case TGSI_TEXTURE_RECT
:
960 instr
->sampler_dim
= GLSL_SAMPLER_DIM_RECT
;
962 case TGSI_TEXTURE_SHADOWRECT
:
963 instr
->sampler_dim
= GLSL_SAMPLER_DIM_RECT
;
964 instr
->is_shadow
= true;
967 fprintf(stderr
, "Unknown TGSI texture target %d\n", texture
);
973 ttn_tex(struct ttn_compile
*c
, nir_alu_dest dest
, nir_ssa_def
**src
)
975 nir_builder
*b
= &c
->build
;
976 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
977 nir_tex_instr
*instr
;
979 unsigned num_srcs
, samp
= 1, i
;
981 switch (tgsi_inst
->Instruction
.Opcode
) {
982 case TGSI_OPCODE_TEX
:
986 case TGSI_OPCODE_TXP
:
990 case TGSI_OPCODE_TXB
:
994 case TGSI_OPCODE_TXL
:
998 case TGSI_OPCODE_TXL2
:
1003 case TGSI_OPCODE_TXF
:
1007 case TGSI_OPCODE_TXD
:
1014 fprintf(stderr
, "unknown TGSI tex op %d\n", tgsi_inst
->Instruction
.Opcode
);
1018 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
1019 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
1020 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
1021 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
1022 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
1023 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
1024 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1028 num_srcs
+= tgsi_inst
->Texture
.NumOffsets
;
1030 instr
= nir_tex_instr_create(b
->shader
, num_srcs
);
1033 setup_texture_info(instr
, tgsi_inst
->Texture
.Texture
);
1035 switch (instr
->sampler_dim
) {
1036 case GLSL_SAMPLER_DIM_1D
:
1037 case GLSL_SAMPLER_DIM_BUF
:
1038 instr
->coord_components
= 1;
1040 case GLSL_SAMPLER_DIM_2D
:
1041 case GLSL_SAMPLER_DIM_RECT
:
1042 case GLSL_SAMPLER_DIM_EXTERNAL
:
1043 case GLSL_SAMPLER_DIM_MS
:
1044 instr
->coord_components
= 2;
1046 case GLSL_SAMPLER_DIM_3D
:
1047 case GLSL_SAMPLER_DIM_CUBE
:
1048 instr
->coord_components
= 3;
1052 if (instr
->is_array
)
1053 instr
->coord_components
++;
1055 assert(tgsi_inst
->Src
[samp
].Register
.File
== TGSI_FILE_SAMPLER
);
1056 instr
->sampler_index
= tgsi_inst
->Src
[samp
].Register
.Index
;
1058 unsigned src_number
= 0;
1060 instr
->src
[src_number
].src
=
1061 nir_src_for_ssa(nir_swizzle(b
, src
[0], SWIZ(X
, Y
, Z
, W
),
1062 instr
->coord_components
, false));
1063 instr
->src
[src_number
].src_type
= nir_tex_src_coord
;
1066 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1067 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1068 instr
->src
[src_number
].src_type
= nir_tex_src_projector
;
1072 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
) {
1073 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1074 instr
->src
[src_number
].src_type
= nir_tex_src_bias
;
1078 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
) {
1079 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1080 instr
->src
[src_number
].src_type
= nir_tex_src_lod
;
1084 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
1085 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[1], X
));
1086 instr
->src
[src_number
].src_type
= nir_tex_src_lod
;
1090 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
1091 instr
->src
[src_number
].src
=
1092 nir_src_for_ssa(nir_swizzle(b
, src
[1], SWIZ(X
, Y
, Z
, W
),
1093 instr
->coord_components
, false));
1094 instr
->src
[src_number
].src_type
= nir_tex_src_ddx
;
1096 instr
->src
[src_number
].src
=
1097 nir_src_for_ssa(nir_swizzle(b
, src
[2], SWIZ(X
, Y
, Z
, W
),
1098 instr
->coord_components
, false));
1099 instr
->src
[src_number
].src_type
= nir_tex_src_ddy
;
1103 if (instr
->is_shadow
) {
1104 if (instr
->coord_components
< 3)
1105 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], Z
));
1107 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1109 instr
->src
[src_number
].src_type
= nir_tex_src_comparitor
;
1113 for (i
= 0; i
< tgsi_inst
->Texture
.NumOffsets
; i
++) {
1114 struct tgsi_texture_offset
*tex_offset
= &tgsi_inst
->TexOffsets
[i
];
1115 /* since TexOffset ins't using tgsi_full_src_register we get to
1116 * do some extra gymnastics:
1120 memset(&src
, 0, sizeof(src
));
1122 src
.src
= ttn_src_for_file_and_index(c
,
1127 src
.swizzle
[0] = tex_offset
->SwizzleX
;
1128 src
.swizzle
[1] = tex_offset
->SwizzleY
;
1129 src
.swizzle
[2] = tex_offset
->SwizzleZ
;
1130 src
.swizzle
[3] = TGSI_SWIZZLE_W
;
1132 instr
->src
[src_number
].src_type
= nir_tex_src_offset
;
1133 instr
->src
[src_number
].src
= nir_src_for_ssa(
1134 nir_fmov_alu(b
, src
, nir_tex_instr_src_size(instr
, src_number
)));
1138 assert(src_number
== num_srcs
);
1140 nir_ssa_dest_init(&instr
->instr
, &instr
->dest
, 4, NULL
);
1141 nir_instr_insert_after_cf_list(b
->cf_node_list
, &instr
->instr
);
1143 /* Resolve the writemask on the texture op. */
1144 ttn_move_dest(b
, dest
, &instr
->dest
.ssa
);
1147 /* TGSI_OPCODE_TXQ is actually two distinct operations:
1149 * dst.x = texture\_width(unit, lod)
1150 * dst.y = texture\_height(unit, lod)
1151 * dst.z = texture\_depth(unit, lod)
1152 * dst.w = texture\_levels(unit)
1154 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels
1157 ttn_txq(struct ttn_compile
*c
, nir_alu_dest dest
, nir_ssa_def
**src
)
1159 nir_builder
*b
= &c
->build
;
1160 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
1161 nir_tex_instr
*txs
, *qlv
;
1163 txs
= nir_tex_instr_create(b
->shader
, 1);
1164 txs
->op
= nir_texop_txs
;
1165 setup_texture_info(txs
, tgsi_inst
->Texture
.Texture
);
1167 qlv
= nir_tex_instr_create(b
->shader
, 0);
1168 qlv
->op
= nir_texop_query_levels
;
1169 setup_texture_info(qlv
, tgsi_inst
->Texture
.Texture
);
1171 assert(tgsi_inst
->Src
[1].Register
.File
== TGSI_FILE_SAMPLER
);
1172 txs
->sampler_index
= tgsi_inst
->Src
[1].Register
.Index
;
1173 qlv
->sampler_index
= tgsi_inst
->Src
[1].Register
.Index
;
1175 /* only single src, the lod: */
1176 txs
->src
[0].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], X
));
1177 txs
->src
[0].src_type
= nir_tex_src_lod
;
1179 nir_ssa_dest_init(&txs
->instr
, &txs
->dest
, 3, NULL
);
1180 nir_instr_insert_after_cf_list(b
->cf_node_list
, &txs
->instr
);
1182 nir_ssa_dest_init(&qlv
->instr
, &qlv
->dest
, 1, NULL
);
1183 nir_instr_insert_after_cf_list(b
->cf_node_list
, &qlv
->instr
);
1185 ttn_move_dest_masked(b
, dest
, &txs
->dest
.ssa
, TGSI_WRITEMASK_XYZ
);
1186 ttn_move_dest_masked(b
, dest
, &qlv
->dest
.ssa
, TGSI_WRITEMASK_W
);
1189 static const nir_op op_trans
[TGSI_OPCODE_LAST
] = {
1190 [TGSI_OPCODE_ARL
] = 0,
1191 [TGSI_OPCODE_MOV
] = nir_op_fmov
,
1192 [TGSI_OPCODE_LIT
] = 0,
1193 [TGSI_OPCODE_RCP
] = nir_op_frcp
,
1194 [TGSI_OPCODE_RSQ
] = nir_op_frsq
,
1195 [TGSI_OPCODE_EXP
] = 0,
1196 [TGSI_OPCODE_LOG
] = 0,
1197 [TGSI_OPCODE_MUL
] = nir_op_fmul
,
1198 [TGSI_OPCODE_ADD
] = nir_op_fadd
,
1199 [TGSI_OPCODE_DP3
] = 0,
1200 [TGSI_OPCODE_DP4
] = 0,
1201 [TGSI_OPCODE_DST
] = 0,
1202 [TGSI_OPCODE_MIN
] = nir_op_fmin
,
1203 [TGSI_OPCODE_MAX
] = nir_op_fmax
,
1204 [TGSI_OPCODE_SLT
] = nir_op_slt
,
1205 [TGSI_OPCODE_SGE
] = nir_op_sge
,
1206 [TGSI_OPCODE_MAD
] = nir_op_ffma
,
1207 [TGSI_OPCODE_SUB
] = nir_op_fsub
,
1208 [TGSI_OPCODE_LRP
] = 0,
1209 [TGSI_OPCODE_SQRT
] = nir_op_fsqrt
,
1210 [TGSI_OPCODE_DP2A
] = 0,
1211 [TGSI_OPCODE_FRC
] = nir_op_ffract
,
1212 [TGSI_OPCODE_CLAMP
] = 0,
1213 [TGSI_OPCODE_FLR
] = nir_op_ffloor
,
1214 [TGSI_OPCODE_ROUND
] = nir_op_fround_even
,
1215 [TGSI_OPCODE_EX2
] = nir_op_fexp2
,
1216 [TGSI_OPCODE_LG2
] = nir_op_flog2
,
1217 [TGSI_OPCODE_POW
] = nir_op_fpow
,
1218 [TGSI_OPCODE_XPD
] = 0,
1219 [TGSI_OPCODE_ABS
] = nir_op_fabs
,
1220 [TGSI_OPCODE_DPH
] = 0,
1221 [TGSI_OPCODE_COS
] = nir_op_fcos
,
1222 [TGSI_OPCODE_DDX
] = nir_op_fddx
,
1223 [TGSI_OPCODE_DDY
] = nir_op_fddy
,
1224 [TGSI_OPCODE_KILL
] = 0,
1225 [TGSI_OPCODE_PK2H
] = 0, /* XXX */
1226 [TGSI_OPCODE_PK2US
] = 0, /* XXX */
1227 [TGSI_OPCODE_PK4B
] = 0, /* XXX */
1228 [TGSI_OPCODE_PK4UB
] = 0, /* XXX */
1229 [TGSI_OPCODE_SEQ
] = nir_op_seq
,
1230 [TGSI_OPCODE_SGT
] = 0,
1231 [TGSI_OPCODE_SIN
] = nir_op_fsin
,
1232 [TGSI_OPCODE_SLE
] = 0,
1233 [TGSI_OPCODE_TEX
] = 0,
1234 [TGSI_OPCODE_TXD
] = 0,
1235 [TGSI_OPCODE_TXP
] = 0,
1236 [TGSI_OPCODE_UP2H
] = 0, /* XXX */
1237 [TGSI_OPCODE_UP2US
] = 0, /* XXX */
1238 [TGSI_OPCODE_UP4B
] = 0, /* XXX */
1239 [TGSI_OPCODE_UP4UB
] = 0, /* XXX */
1240 [TGSI_OPCODE_ARR
] = 0,
1242 /* No function calls, yet. */
1243 [TGSI_OPCODE_CAL
] = 0, /* XXX */
1244 [TGSI_OPCODE_RET
] = 0, /* XXX */
1246 [TGSI_OPCODE_SSG
] = nir_op_fsign
,
1247 [TGSI_OPCODE_CMP
] = 0,
1248 [TGSI_OPCODE_SCS
] = 0,
1249 [TGSI_OPCODE_TXB
] = 0,
1250 [TGSI_OPCODE_DIV
] = nir_op_fdiv
,
1251 [TGSI_OPCODE_DP2
] = 0,
1252 [TGSI_OPCODE_DP2A
] = 0,
1253 [TGSI_OPCODE_TXL
] = 0,
1255 [TGSI_OPCODE_BRK
] = 0,
1256 [TGSI_OPCODE_IF
] = 0,
1257 [TGSI_OPCODE_UIF
] = 0,
1258 [TGSI_OPCODE_ELSE
] = 0,
1259 [TGSI_OPCODE_ENDIF
] = 0,
1261 [TGSI_OPCODE_DDX_FINE
] = nir_op_fddx_fine
,
1262 [TGSI_OPCODE_DDY_FINE
] = nir_op_fddy_fine
,
1264 [TGSI_OPCODE_PUSHA
] = 0, /* XXX */
1265 [TGSI_OPCODE_POPA
] = 0, /* XXX */
1267 [TGSI_OPCODE_CEIL
] = nir_op_fceil
,
1268 [TGSI_OPCODE_I2F
] = nir_op_i2f
,
1269 [TGSI_OPCODE_NOT
] = nir_op_inot
,
1270 [TGSI_OPCODE_TRUNC
] = nir_op_ftrunc
,
1271 [TGSI_OPCODE_SHL
] = nir_op_ishl
,
1272 [TGSI_OPCODE_AND
] = nir_op_iand
,
1273 [TGSI_OPCODE_OR
] = nir_op_ior
,
1274 [TGSI_OPCODE_MOD
] = nir_op_umod
,
1275 [TGSI_OPCODE_XOR
] = nir_op_ixor
,
1276 [TGSI_OPCODE_SAD
] = 0, /* XXX */
1277 [TGSI_OPCODE_TXF
] = 0,
1278 [TGSI_OPCODE_TXQ
] = 0,
1280 [TGSI_OPCODE_CONT
] = 0,
1282 [TGSI_OPCODE_EMIT
] = 0, /* XXX */
1283 [TGSI_OPCODE_ENDPRIM
] = 0, /* XXX */
1285 [TGSI_OPCODE_BGNLOOP
] = 0,
1286 [TGSI_OPCODE_BGNSUB
] = 0, /* XXX: no function calls */
1287 [TGSI_OPCODE_ENDLOOP
] = 0,
1288 [TGSI_OPCODE_ENDSUB
] = 0, /* XXX: no function calls */
1290 [TGSI_OPCODE_TXQ_LZ
] = 0,
1291 [TGSI_OPCODE_NOP
] = 0,
1292 [TGSI_OPCODE_FSEQ
] = nir_op_feq
,
1293 [TGSI_OPCODE_FSGE
] = nir_op_fge
,
1294 [TGSI_OPCODE_FSLT
] = nir_op_flt
,
1295 [TGSI_OPCODE_FSNE
] = nir_op_fne
,
1297 /* No control flow yet */
1298 [TGSI_OPCODE_CALLNZ
] = 0, /* XXX */
1299 [TGSI_OPCODE_BREAKC
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1301 [TGSI_OPCODE_KILL_IF
] = 0,
1303 [TGSI_OPCODE_END
] = 0,
1305 [TGSI_OPCODE_F2I
] = nir_op_f2i
,
1306 [TGSI_OPCODE_IDIV
] = nir_op_idiv
,
1307 [TGSI_OPCODE_IMAX
] = nir_op_imax
,
1308 [TGSI_OPCODE_IMIN
] = nir_op_imin
,
1309 [TGSI_OPCODE_INEG
] = nir_op_ineg
,
1310 [TGSI_OPCODE_ISGE
] = nir_op_ige
,
1311 [TGSI_OPCODE_ISHR
] = nir_op_ishr
,
1312 [TGSI_OPCODE_ISLT
] = nir_op_ilt
,
1313 [TGSI_OPCODE_F2U
] = nir_op_f2u
,
1314 [TGSI_OPCODE_U2F
] = nir_op_u2f
,
1315 [TGSI_OPCODE_UADD
] = nir_op_iadd
,
1316 [TGSI_OPCODE_UDIV
] = nir_op_udiv
,
1317 [TGSI_OPCODE_UMAD
] = 0,
1318 [TGSI_OPCODE_UMAX
] = nir_op_umax
,
1319 [TGSI_OPCODE_UMIN
] = nir_op_umin
,
1320 [TGSI_OPCODE_UMOD
] = nir_op_umod
,
1321 [TGSI_OPCODE_UMUL
] = nir_op_imul
,
1322 [TGSI_OPCODE_USEQ
] = nir_op_ieq
,
1323 [TGSI_OPCODE_USGE
] = nir_op_uge
,
1324 [TGSI_OPCODE_USHR
] = nir_op_ushr
,
1325 [TGSI_OPCODE_USLT
] = nir_op_ult
,
1326 [TGSI_OPCODE_USNE
] = nir_op_ine
,
1328 [TGSI_OPCODE_SWITCH
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1329 [TGSI_OPCODE_CASE
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1330 [TGSI_OPCODE_DEFAULT
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1331 [TGSI_OPCODE_ENDSWITCH
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1333 /* XXX: SAMPLE opcodes */
1335 [TGSI_OPCODE_UARL
] = nir_op_imov
,
1336 [TGSI_OPCODE_UCMP
] = 0,
1337 [TGSI_OPCODE_IABS
] = nir_op_iabs
,
1338 [TGSI_OPCODE_ISSG
] = nir_op_isign
,
1342 [TGSI_OPCODE_TEX2
] = 0,
1343 [TGSI_OPCODE_TXB2
] = 0,
1344 [TGSI_OPCODE_TXL2
] = 0,
1346 [TGSI_OPCODE_IMUL_HI
] = nir_op_imul_high
,
1347 [TGSI_OPCODE_UMUL_HI
] = nir_op_umul_high
,
1349 [TGSI_OPCODE_TG4
] = 0,
1350 [TGSI_OPCODE_LODQ
] = 0, /* XXX */
1352 [TGSI_OPCODE_IBFE
] = nir_op_ibitfield_extract
,
1353 [TGSI_OPCODE_UBFE
] = nir_op_ubitfield_extract
,
1354 [TGSI_OPCODE_BFI
] = nir_op_bitfield_insert
,
1355 [TGSI_OPCODE_BREV
] = nir_op_bitfield_reverse
,
1356 [TGSI_OPCODE_POPC
] = nir_op_bit_count
,
1357 [TGSI_OPCODE_LSB
] = nir_op_find_lsb
,
1358 [TGSI_OPCODE_IMSB
] = nir_op_ifind_msb
,
1359 [TGSI_OPCODE_UMSB
] = nir_op_ifind_msb
, /* XXX: signed vs unsigned */
1361 [TGSI_OPCODE_INTERP_CENTROID
] = 0, /* XXX */
1362 [TGSI_OPCODE_INTERP_SAMPLE
] = 0, /* XXX */
1363 [TGSI_OPCODE_INTERP_OFFSET
] = 0, /* XXX */
1367 ttn_emit_instruction(struct ttn_compile
*c
)
1369 nir_builder
*b
= &c
->build
;
1370 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
1372 unsigned tgsi_op
= tgsi_inst
->Instruction
.Opcode
;
1373 struct tgsi_full_dst_register
*tgsi_dst
= &tgsi_inst
->Dst
[0];
1375 if (tgsi_op
== TGSI_OPCODE_END
)
1378 nir_ssa_def
*src
[TGSI_FULL_MAX_SRC_REGISTERS
];
1379 for (i
= 0; i
< TGSI_FULL_MAX_SRC_REGISTERS
; i
++) {
1380 src
[i
] = ttn_get_src(c
, &tgsi_inst
->Src
[i
]);
1382 nir_alu_dest dest
= ttn_get_dest(c
, tgsi_dst
);
1385 case TGSI_OPCODE_RSQ
:
1386 ttn_move_dest(b
, dest
, nir_frsq(b
, ttn_channel(b
, src
[0], X
)));
1389 case TGSI_OPCODE_SQRT
:
1390 ttn_move_dest(b
, dest
, nir_fsqrt(b
, ttn_channel(b
, src
[0], X
)));
1393 case TGSI_OPCODE_RCP
:
1394 ttn_move_dest(b
, dest
, nir_frcp(b
, ttn_channel(b
, src
[0], X
)));
1397 case TGSI_OPCODE_EX2
:
1398 ttn_move_dest(b
, dest
, nir_fexp2(b
, ttn_channel(b
, src
[0], X
)));
1401 case TGSI_OPCODE_LG2
:
1402 ttn_move_dest(b
, dest
, nir_flog2(b
, ttn_channel(b
, src
[0], X
)));
1405 case TGSI_OPCODE_POW
:
1406 ttn_move_dest(b
, dest
, nir_fpow(b
,
1407 ttn_channel(b
, src
[0], X
),
1408 ttn_channel(b
, src
[1], X
)));
1411 case TGSI_OPCODE_COS
:
1412 ttn_move_dest(b
, dest
, nir_fcos(b
, ttn_channel(b
, src
[0], X
)));
1415 case TGSI_OPCODE_SIN
:
1416 ttn_move_dest(b
, dest
, nir_fsin(b
, ttn_channel(b
, src
[0], X
)));
1419 case TGSI_OPCODE_ARL
:
1420 ttn_arl(b
, op_trans
[tgsi_op
], dest
, src
);
1423 case TGSI_OPCODE_EXP
:
1424 ttn_exp(b
, op_trans
[tgsi_op
], dest
, src
);
1427 case TGSI_OPCODE_LOG
:
1428 ttn_log(b
, op_trans
[tgsi_op
], dest
, src
);
1431 case TGSI_OPCODE_DST
:
1432 ttn_dst(b
, op_trans
[tgsi_op
], dest
, src
);
1435 case TGSI_OPCODE_LIT
:
1436 ttn_lit(b
, op_trans
[tgsi_op
], dest
, src
);
1439 case TGSI_OPCODE_CLAMP
:
1440 ttn_clamp(b
, op_trans
[tgsi_op
], dest
, src
);
1443 case TGSI_OPCODE_XPD
:
1444 ttn_xpd(b
, op_trans
[tgsi_op
], dest
, src
);
1447 case TGSI_OPCODE_DP2
:
1448 ttn_dp2(b
, op_trans
[tgsi_op
], dest
, src
);
1451 case TGSI_OPCODE_DP3
:
1452 ttn_dp3(b
, op_trans
[tgsi_op
], dest
, src
);
1455 case TGSI_OPCODE_DP4
:
1456 ttn_dp4(b
, op_trans
[tgsi_op
], dest
, src
);
1459 case TGSI_OPCODE_DP2A
:
1460 ttn_dp2a(b
, op_trans
[tgsi_op
], dest
, src
);
1463 case TGSI_OPCODE_DPH
:
1464 ttn_dph(b
, op_trans
[tgsi_op
], dest
, src
);
1467 case TGSI_OPCODE_UMAD
:
1468 ttn_umad(b
, op_trans
[tgsi_op
], dest
, src
);
1471 case TGSI_OPCODE_LRP
:
1472 ttn_move_dest(b
, dest
, nir_flrp(b
, src
[2], src
[1], src
[0]));
1475 case TGSI_OPCODE_KILL
:
1476 ttn_kill(b
, op_trans
[tgsi_op
], dest
, src
);
1479 case TGSI_OPCODE_ARR
:
1480 ttn_arr(b
, op_trans
[tgsi_op
], dest
, src
);
1483 case TGSI_OPCODE_CMP
:
1484 ttn_cmp(b
, op_trans
[tgsi_op
], dest
, src
);
1487 case TGSI_OPCODE_UCMP
:
1488 ttn_ucmp(b
, op_trans
[tgsi_op
], dest
, src
);
1491 case TGSI_OPCODE_SCS
:
1492 ttn_scs(b
, op_trans
[tgsi_op
], dest
, src
);
1495 case TGSI_OPCODE_SGT
:
1496 ttn_sgt(b
, op_trans
[tgsi_op
], dest
, src
);
1499 case TGSI_OPCODE_SLE
:
1500 ttn_sle(b
, op_trans
[tgsi_op
], dest
, src
);
1503 case TGSI_OPCODE_KILL_IF
:
1504 ttn_kill_if(b
, op_trans
[tgsi_op
], dest
, src
);
1507 case TGSI_OPCODE_TEX
:
1508 case TGSI_OPCODE_TXP
:
1509 case TGSI_OPCODE_TXL
:
1510 case TGSI_OPCODE_TXB
:
1511 case TGSI_OPCODE_TXD
:
1512 case TGSI_OPCODE_TXL2
:
1513 case TGSI_OPCODE_TXB2
:
1514 case TGSI_OPCODE_TXQ_LZ
:
1515 case TGSI_OPCODE_TXF
:
1516 case TGSI_OPCODE_TG4
:
1517 ttn_tex(c
, dest
, src
);
1520 case TGSI_OPCODE_TXQ
:
1521 ttn_txq(c
, dest
, src
);
1524 case TGSI_OPCODE_NOP
:
1527 case TGSI_OPCODE_IF
:
1528 ttn_if(c
, src
[0], false);
1531 case TGSI_OPCODE_UIF
:
1532 ttn_if(c
, src
[0], true);
1535 case TGSI_OPCODE_ELSE
:
1539 case TGSI_OPCODE_ENDIF
:
1543 case TGSI_OPCODE_BGNLOOP
:
1547 case TGSI_OPCODE_BRK
:
1551 case TGSI_OPCODE_CONT
:
1555 case TGSI_OPCODE_ENDLOOP
:
1560 if (op_trans
[tgsi_op
] != 0 || tgsi_op
== TGSI_OPCODE_MOV
) {
1561 ttn_alu(b
, op_trans
[tgsi_op
], dest
, src
);
1563 fprintf(stderr
, "unknown TGSI opcode: %s\n",
1564 tgsi_get_opcode_name(tgsi_op
));
1570 if (tgsi_inst
->Instruction
.Saturate
) {
1571 assert(tgsi_inst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
);
1572 assert(!dest
.dest
.is_ssa
);
1573 ttn_move_dest(b
, dest
, nir_fsat(b
, ttn_src_for_dest(b
, &dest
)));
1576 /* if the dst has a matching var, append store_global to move
1577 * output from reg to var
1579 nir_variable
*var
= ttn_get_var(c
, tgsi_dst
);
1581 unsigned index
= tgsi_dst
->Register
.Index
;
1582 unsigned offset
= c
->temp_regs
[index
].offset
;
1583 nir_intrinsic_instr
*store
=
1584 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_var
);
1585 struct tgsi_ind_register
*indirect
= tgsi_dst
->Register
.Indirect
?
1586 &tgsi_dst
->Indirect
: NULL
;
1588 store
->num_components
= 4;
1589 store
->variables
[0] = ttn_array_deref(c
, store
, var
, offset
, indirect
);
1590 store
->src
[0] = nir_src_for_reg(dest
.dest
.reg
.reg
);
1592 nir_instr_insert_after_cf_list(b
->cf_node_list
, &store
->instr
);
1597 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
1598 * variables at the end of the shader.
1600 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
1601 * written, because there's no output load intrinsic, which means we couldn't
1602 * handle writemasks.
1605 ttn_add_output_stores(struct ttn_compile
*c
)
1607 nir_builder
*b
= &c
->build
;
1609 foreach_list_typed(nir_variable
, var
, node
, &b
->shader
->outputs
) {
1610 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1613 for (i
= 0; i
< array_len
; i
++) {
1614 nir_intrinsic_instr
*store
=
1615 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
1616 store
->num_components
= 4;
1617 store
->const_index
[0] = var
->data
.driver_location
+ i
;
1618 store
->const_index
[1] = 1;
1619 store
->src
[0].reg
.reg
= c
->output_regs
[var
->data
.driver_location
].reg
;
1620 nir_instr_insert_after_cf_list(b
->cf_node_list
, &store
->instr
);
1626 tgsi_to_nir(const void *tgsi_tokens
,
1627 const nir_shader_compiler_options
*options
)
1629 struct tgsi_parse_context parser
;
1630 struct tgsi_shader_info scan
;
1631 struct ttn_compile
*c
;
1632 struct nir_shader
*s
;
1635 c
= rzalloc(NULL
, struct ttn_compile
);
1636 s
= nir_shader_create(NULL
, options
);
1638 nir_function
*func
= nir_function_create(s
, "main");
1639 nir_function_overload
*overload
= nir_function_overload_create(func
);
1640 nir_function_impl
*impl
= nir_function_impl_create(overload
);
1642 nir_builder_init(&c
->build
, impl
);
1643 nir_builder_insert_after_cf_list(&c
->build
, &impl
->body
);
1645 tgsi_scan_shader(tgsi_tokens
, &scan
);
1648 s
->num_inputs
= scan
.file_max
[TGSI_FILE_INPUT
] + 1;
1649 s
->num_uniforms
= scan
.file_max
[TGSI_FILE_CONSTANT
] + 1;
1650 s
->num_outputs
= scan
.file_max
[TGSI_FILE_OUTPUT
] + 1;
1652 c
->output_regs
= rzalloc_array(c
, struct ttn_reg_info
,
1653 scan
.file_max
[TGSI_FILE_OUTPUT
] + 1);
1654 c
->temp_regs
= rzalloc_array(c
, struct ttn_reg_info
,
1655 scan
.file_max
[TGSI_FILE_TEMPORARY
] + 1);
1656 c
->imm_defs
= rzalloc_array(c
, nir_ssa_def
*,
1657 scan
.file_max
[TGSI_FILE_IMMEDIATE
] + 1);
1659 c
->if_stack
= rzalloc_array(c
, struct exec_list
*,
1660 (scan
.opcode_count
[TGSI_OPCODE_IF
] +
1661 scan
.opcode_count
[TGSI_OPCODE_UIF
]) * 2);
1662 c
->loop_stack
= rzalloc_array(c
, struct exec_list
*,
1663 scan
.opcode_count
[TGSI_OPCODE_BGNLOOP
]);
1665 ret
= tgsi_parse_init(&parser
, tgsi_tokens
);
1666 assert(ret
== TGSI_PARSE_OK
);
1668 while (!tgsi_parse_end_of_tokens(&parser
)) {
1669 tgsi_parse_token(&parser
);
1670 c
->token
= &parser
.FullToken
;
1672 switch (parser
.FullToken
.Token
.Type
) {
1673 case TGSI_TOKEN_TYPE_DECLARATION
:
1674 ttn_emit_declaration(c
);
1677 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1678 ttn_emit_instruction(c
);
1681 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1682 ttn_emit_immediate(c
);
1687 tgsi_parse_free(&parser
);
1689 ttn_add_output_stores(c
);