2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/ralloc.h"
26 #include "glsl/nir/nir.h"
27 #include "glsl/nir/nir_builder.h"
28 #include "glsl/list.h"
29 #include "glsl/shader_enums.h"
31 #include "nir/tgsi_to_nir.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_dump.h"
34 #include "tgsi/tgsi_info.h"
35 #include "tgsi/tgsi_scan.h"
37 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
45 /** nir register containing this TGSI index. */
47 /** Offset (in vec4s) from the start of var for this TGSI index. */
52 union tgsi_full_token
*token
;
55 struct tgsi_shader_info
*scan
;
57 struct ttn_reg_info
*output_regs
;
58 struct ttn_reg_info
*temp_regs
;
59 nir_ssa_def
**imm_defs
;
61 nir_register
*addr_reg
;
64 * Stack of cf_node_lists where instructions should be pushed as we pop
65 * back out of the control flow stack.
67 * For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else
68 * instructions should be placed, and if_stack[if_stack_pos - 1] has where
69 * the next instructions outside of the if/then/else block go.
71 struct exec_list
**if_stack
;
72 unsigned if_stack_pos
;
75 * Stack of cf_node_lists where instructions should be pushed as we pop
76 * back out of the control flow stack.
78 * loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside
81 struct exec_list
**loop_stack
;
82 unsigned loop_stack_pos
;
84 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
88 #define ttn_swizzle(b, src, x, y, z, w) \
89 nir_swizzle(b, src, SWIZ(x, y, z, w), 4, false)
90 #define ttn_channel(b, src, swiz) \
91 nir_swizzle(b, src, SWIZ(swiz, swiz, swiz, swiz), 1, false)
94 ttn_src_for_dest(nir_builder
*b
, nir_alu_dest
*dest
)
97 memset(&src
, 0, sizeof(src
));
99 if (dest
->dest
.is_ssa
)
100 src
.src
= nir_src_for_ssa(&dest
->dest
.ssa
);
102 assert(!dest
->dest
.reg
.indirect
);
103 src
.src
= nir_src_for_reg(dest
->dest
.reg
.reg
);
104 src
.src
.reg
.base_offset
= dest
->dest
.reg
.base_offset
;
107 for (int i
= 0; i
< 4; i
++)
110 return nir_fmov_alu(b
, src
, 4);
114 ttn_emit_declaration(struct ttn_compile
*c
)
116 nir_builder
*b
= &c
->build
;
117 struct tgsi_full_declaration
*decl
= &c
->token
->FullDeclaration
;
118 unsigned array_size
= decl
->Range
.Last
- decl
->Range
.First
+ 1;
119 unsigned file
= decl
->Declaration
.File
;
122 if (file
== TGSI_FILE_TEMPORARY
) {
124 if (c
->scan
->indirect_files
& (1 << file
)) {
125 reg
= nir_local_reg_create(b
->impl
);
126 reg
->num_components
= 4;
127 reg
->num_array_elems
= array_size
;
129 for (i
= 0; i
< array_size
; i
++) {
130 c
->temp_regs
[decl
->Range
.First
+ i
].reg
= reg
;
131 c
->temp_regs
[decl
->Range
.First
+ i
].offset
= i
;
134 for (i
= 0; i
< array_size
; i
++) {
135 reg
= nir_local_reg_create(b
->impl
);
136 reg
->num_components
= 4;
137 c
->temp_regs
[decl
->Range
.First
+ i
].reg
= reg
;
138 c
->temp_regs
[decl
->Range
.First
+ i
].offset
= 0;
141 } else if (file
== TGSI_FILE_ADDRESS
) {
142 c
->addr_reg
= nir_local_reg_create(b
->impl
);
143 c
->addr_reg
->num_components
= 4;
144 } else if (file
== TGSI_FILE_SAMPLER
) {
145 /* Nothing to record for samplers. */
148 assert(file
== TGSI_FILE_INPUT
||
149 file
== TGSI_FILE_OUTPUT
||
150 file
== TGSI_FILE_CONSTANT
);
152 var
= rzalloc(b
->shader
, nir_variable
);
153 var
->data
.driver_location
= decl
->Range
.First
;
155 var
->type
= glsl_vec4_type();
157 var
->type
= glsl_array_type(var
->type
, array_size
);
160 case TGSI_FILE_INPUT
:
161 var
->data
.read_only
= true;
162 var
->data
.mode
= nir_var_shader_in
;
163 var
->name
= ralloc_asprintf(var
, "in_%d", decl
->Range
.First
);
165 /* We should probably translate to a VERT_ATTRIB_* or VARYING_SLOT_*
166 * instead, but nothing in NIR core is looking at the value
167 * currently, and this is less change to drivers.
169 var
->data
.location
= decl
->Semantic
.Name
;
170 var
->data
.index
= decl
->Semantic
.Index
;
172 /* We definitely need to translate the interpolation field, because
173 * nir_print will decode it.
175 switch (decl
->Interp
.Interpolate
) {
176 case TGSI_INTERPOLATE_CONSTANT
:
177 var
->data
.interpolation
= INTERP_QUALIFIER_FLAT
;
179 case TGSI_INTERPOLATE_LINEAR
:
180 var
->data
.interpolation
= INTERP_QUALIFIER_NOPERSPECTIVE
;
182 case TGSI_INTERPOLATE_PERSPECTIVE
:
183 var
->data
.interpolation
= INTERP_QUALIFIER_SMOOTH
;
187 exec_list_push_tail(&b
->shader
->inputs
, &var
->node
);
189 case TGSI_FILE_OUTPUT
: {
190 /* Since we can't load from outputs in the IR, we make temporaries
191 * for the outputs and emit stores to the real outputs at the end of
194 nir_register
*reg
= nir_local_reg_create(b
->impl
);
195 reg
->num_components
= 4;
197 reg
->num_array_elems
= array_size
;
199 var
->data
.mode
= nir_var_shader_out
;
200 var
->name
= ralloc_asprintf(var
, "out_%d", decl
->Range
.First
);
202 var
->data
.location
= decl
->Semantic
.Name
;
203 var
->data
.index
= decl
->Semantic
.Index
;
205 for (i
= 0; i
< array_size
; i
++) {
206 c
->output_regs
[decl
->Range
.First
+ i
].offset
= i
;
207 c
->output_regs
[decl
->Range
.First
+ i
].reg
= reg
;
210 exec_list_push_tail(&b
->shader
->outputs
, &var
->node
);
213 case TGSI_FILE_CONSTANT
:
214 var
->data
.mode
= nir_var_uniform
;
215 var
->name
= ralloc_asprintf(var
, "uniform_%d", decl
->Range
.First
);
217 exec_list_push_tail(&b
->shader
->uniforms
, &var
->node
);
220 unreachable("bad declaration file");
228 ttn_emit_immediate(struct ttn_compile
*c
)
230 nir_builder
*b
= &c
->build
;
231 struct tgsi_full_immediate
*tgsi_imm
= &c
->token
->FullImmediate
;
232 nir_load_const_instr
*load_const
;
235 load_const
= nir_load_const_instr_create(b
->shader
, 4);
236 c
->imm_defs
[c
->next_imm
] = &load_const
->def
;
239 for (i
= 0; i
< 4; i
++)
240 load_const
->value
.u
[i
] = tgsi_imm
->u
[i
].Uint
;
242 nir_instr_insert_after_cf_list(b
->cf_node_list
, &load_const
->instr
);
246 ttn_src_for_indirect(struct ttn_compile
*c
, struct tgsi_ind_register
*indirect
);
249 ttn_src_for_file_and_index(struct ttn_compile
*c
, unsigned file
, unsigned index
,
250 struct tgsi_ind_register
*indirect
)
252 nir_builder
*b
= &c
->build
;
255 memset(&src
, 0, sizeof(src
));
258 case TGSI_FILE_TEMPORARY
:
259 src
.reg
.reg
= c
->temp_regs
[index
].reg
;
260 src
.reg
.base_offset
= c
->temp_regs
[index
].offset
;
262 src
.reg
.indirect
= ttn_src_for_indirect(c
, indirect
);
265 case TGSI_FILE_ADDRESS
:
266 src
.reg
.reg
= c
->addr_reg
;
269 case TGSI_FILE_IMMEDIATE
:
270 src
= nir_src_for_ssa(c
->imm_defs
[index
]);
274 case TGSI_FILE_INPUT
:
275 case TGSI_FILE_CONSTANT
: {
276 nir_intrinsic_instr
*load
;
279 case TGSI_FILE_INPUT
:
280 load
= nir_intrinsic_instr_create(b
->shader
,
282 nir_intrinsic_load_input_indirect
:
283 nir_intrinsic_load_input
);
285 case TGSI_FILE_CONSTANT
:
286 load
= nir_intrinsic_instr_create(b
->shader
,
288 nir_intrinsic_load_uniform_indirect
:
289 nir_intrinsic_load_uniform
);
292 unreachable("No other load files supported");
296 load
->num_components
= 4;
297 load
->const_index
[0] = index
;
298 load
->const_index
[1] = 1;
300 nir_alu_src indirect_address
;
301 memset(&indirect_address
, 0, sizeof(indirect_address
));
302 indirect_address
.src
= nir_src_for_reg(c
->addr_reg
);
303 for (int i
= 0; i
< 4; i
++)
304 indirect_address
.swizzle
[i
] = indirect
->Swizzle
;
305 load
->src
[0] = nir_src_for_ssa(nir_imov_alu(b
, indirect_address
, 1));
307 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, NULL
);
308 nir_instr_insert_after_cf_list(b
->cf_node_list
, &load
->instr
);
310 src
= nir_src_for_ssa(&load
->dest
.ssa
);
315 unreachable("bad src file");
323 ttn_src_for_indirect(struct ttn_compile
*c
, struct tgsi_ind_register
*indirect
)
325 nir_builder
*b
= &c
->build
;
327 memset(&src
, 0, sizeof(src
));
328 for (int i
= 0; i
< 4; i
++)
329 src
.swizzle
[i
] = indirect
->Swizzle
;
330 src
.src
= ttn_src_for_file_and_index(c
,
332 indirect
->Index
, NULL
);
333 nir_src
*result
= ralloc(b
->shader
, nir_src
);
334 *result
= nir_src_for_ssa(nir_imov_alu(b
, src
, 1));
339 ttn_get_dest(struct ttn_compile
*c
, struct tgsi_full_dst_register
*tgsi_fdst
)
341 struct tgsi_dst_register
*tgsi_dst
= &tgsi_fdst
->Register
;
343 unsigned index
= tgsi_dst
->Index
;
345 memset(&dest
, 0, sizeof(dest
));
347 if (tgsi_dst
->File
== TGSI_FILE_TEMPORARY
) {
348 dest
.dest
.reg
.reg
= c
->temp_regs
[index
].reg
;
349 dest
.dest
.reg
.base_offset
= c
->temp_regs
[index
].offset
;
350 } else if (tgsi_dst
->File
== TGSI_FILE_OUTPUT
) {
351 dest
.dest
.reg
.reg
= c
->output_regs
[index
].reg
;
352 dest
.dest
.reg
.base_offset
= c
->output_regs
[index
].offset
;
353 } else if (tgsi_dst
->File
== TGSI_FILE_ADDRESS
) {
355 dest
.dest
.reg
.reg
= c
->addr_reg
;
358 dest
.write_mask
= tgsi_dst
->WriteMask
;
359 dest
.saturate
= false;
361 if (tgsi_dst
->Indirect
)
362 dest
.dest
.reg
.indirect
= ttn_src_for_indirect(c
, &tgsi_fdst
->Indirect
);
368 ttn_get_src(struct ttn_compile
*c
, struct tgsi_full_src_register
*tgsi_fsrc
)
370 nir_builder
*b
= &c
->build
;
371 struct tgsi_src_register
*tgsi_src
= &tgsi_fsrc
->Register
;
372 unsigned tgsi_opcode
= c
->token
->FullInstruction
.Instruction
.Opcode
;
373 unsigned tgsi_src_type
= tgsi_opcode_infer_src_type(tgsi_opcode
);
374 bool src_is_float
= !(tgsi_src_type
== TGSI_TYPE_SIGNED
||
375 tgsi_src_type
== TGSI_TYPE_UNSIGNED
);
378 memset(&src
, 0, sizeof(src
));
380 if (tgsi_src
->File
== TGSI_FILE_NULL
) {
381 return nir_imm_float(b
, 0.0);
382 } else if (tgsi_src
->File
== TGSI_FILE_SAMPLER
) {
383 /* Only the index of the sampler gets used in texturing, and it will
384 * handle looking that up on its own instead of using the nir_alu_src.
386 assert(!tgsi_src
->Indirect
);
389 src
.src
= ttn_src_for_file_and_index(c
,
392 (tgsi_src
->Indirect
?
393 &tgsi_fsrc
->Indirect
: NULL
));
396 src
.swizzle
[0] = tgsi_src
->SwizzleX
;
397 src
.swizzle
[1] = tgsi_src
->SwizzleY
;
398 src
.swizzle
[2] = tgsi_src
->SwizzleZ
;
399 src
.swizzle
[3] = tgsi_src
->SwizzleW
;
401 nir_ssa_def
*def
= nir_fmov_alu(b
, src
, 4);
403 if (tgsi_src
->Absolute
) {
405 def
= nir_fabs(b
, def
);
407 def
= nir_iabs(b
, def
);
410 if (tgsi_src
->Negate
) {
412 def
= nir_fneg(b
, def
);
414 def
= nir_ineg(b
, def
);
421 ttn_alu(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
423 unsigned num_srcs
= nir_op_infos
[op
].num_inputs
;
424 nir_alu_instr
*instr
= nir_alu_instr_create(b
->shader
, op
);
427 for (i
= 0; i
< num_srcs
; i
++)
428 instr
->src
[i
].src
= nir_src_for_ssa(src
[i
]);
431 nir_instr_insert_after_cf_list(b
->cf_node_list
, &instr
->instr
);
435 ttn_move_dest_masked(nir_builder
*b
, nir_alu_dest dest
,
436 nir_ssa_def
*def
, unsigned write_mask
)
438 if (!(dest
.write_mask
& write_mask
))
441 nir_alu_instr
*mov
= nir_alu_instr_create(b
->shader
, nir_op_imov
);
443 mov
->dest
.write_mask
&= write_mask
;
444 mov
->src
[0].src
= nir_src_for_ssa(def
);
445 for (unsigned i
= def
->num_components
; i
< 4; i
++)
446 mov
->src
[0].swizzle
[i
] = def
->num_components
- 1;
447 nir_instr_insert_after_cf_list(b
->cf_node_list
, &mov
->instr
);
451 ttn_move_dest(nir_builder
*b
, nir_alu_dest dest
, nir_ssa_def
*def
)
453 ttn_move_dest_masked(b
, dest
, def
, TGSI_WRITEMASK_XYZW
);
457 ttn_arl(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
459 ttn_move_dest(b
, dest
, nir_f2i(b
, nir_ffloor(b
, src
[0])));
462 /* EXP - Approximate Exponential Base 2
463 * dst.x = 2^{\lfloor src.x\rfloor}
464 * dst.y = src.x - \lfloor src.x\rfloor
469 ttn_exp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
471 nir_ssa_def
*srcx
= ttn_channel(b
, src
[0], X
);
473 ttn_move_dest_masked(b
, dest
, nir_fexp2(b
, nir_ffloor(b
, srcx
)),
475 ttn_move_dest_masked(b
, dest
, nir_fsub(b
, srcx
, nir_ffloor(b
, srcx
)),
477 ttn_move_dest_masked(b
, dest
, nir_fexp2(b
, srcx
), TGSI_WRITEMASK_Z
);
478 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
481 /* LOG - Approximate Logarithm Base 2
482 * dst.x = \lfloor\log_2{|src.x|}\rfloor
483 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
484 * dst.z = \log_2{|src.x|}
488 ttn_log(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
490 nir_ssa_def
*abs_srcx
= nir_fabs(b
, ttn_channel(b
, src
[0], X
));
491 nir_ssa_def
*log2
= nir_flog2(b
, abs_srcx
);
493 ttn_move_dest_masked(b
, dest
, nir_ffloor(b
, log2
), TGSI_WRITEMASK_X
);
494 ttn_move_dest_masked(b
, dest
,
495 nir_fdiv(b
, abs_srcx
, nir_fexp2(b
, nir_ffloor(b
, log2
))),
497 ttn_move_dest_masked(b
, dest
, nir_flog2(b
, abs_srcx
), TGSI_WRITEMASK_Z
);
498 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
501 /* DST - Distance Vector
503 * dst.y = src0.y \times src1.y
508 ttn_dst(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
510 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_X
);
511 ttn_move_dest_masked(b
, dest
, nir_fmul(b
, src
[0], src
[1]), TGSI_WRITEMASK_Y
);
512 ttn_move_dest_masked(b
, dest
, nir_fmov(b
, src
[0]), TGSI_WRITEMASK_Z
);
513 ttn_move_dest_masked(b
, dest
, nir_fmov(b
, src
[1]), TGSI_WRITEMASK_W
);
516 /* LIT - Light Coefficients
518 * dst.y = max(src.x, 0.0)
519 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
523 ttn_lit(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
525 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_XW
);
527 ttn_move_dest_masked(b
, dest
, nir_fmax(b
, ttn_channel(b
, src
[0], X
),
528 nir_imm_float(b
, 0.0)), TGSI_WRITEMASK_Y
);
530 if (dest
.write_mask
& TGSI_WRITEMASK_Z
) {
531 nir_ssa_def
*src0_y
= ttn_channel(b
, src
[0], Y
);
532 nir_ssa_def
*wclamp
= nir_fmax(b
, nir_fmin(b
, ttn_channel(b
, src
[0], W
),
533 nir_imm_float(b
, 128.0)),
534 nir_imm_float(b
, -128.0));
535 nir_ssa_def
*pow
= nir_fpow(b
, nir_fmax(b
, src0_y
, nir_imm_float(b
, 0.0)),
538 ttn_move_dest_masked(b
, dest
,
541 nir_imm_float(b
, 0.0),
542 ttn_channel(b
, src
[0], X
)),
543 nir_imm_float(b
, 0.0),
550 * dst.x = \cos{src.x}
551 * dst.y = \sin{src.x}
556 ttn_scs(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
558 ttn_move_dest_masked(b
, dest
, nir_fcos(b
, ttn_channel(b
, src
[0], X
)),
560 ttn_move_dest_masked(b
, dest
, nir_fsin(b
, ttn_channel(b
, src
[0], X
)),
562 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 0.0), TGSI_WRITEMASK_Z
);
563 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
567 ttn_sle(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
569 ttn_move_dest(b
, dest
, nir_sge(b
, src
[1], src
[0]));
573 ttn_sgt(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
575 ttn_move_dest(b
, dest
, nir_slt(b
, src
[1], src
[0]));
579 ttn_clamp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
581 ttn_move_dest(b
, dest
, nir_fmin(b
, nir_fmax(b
, src
[0], src
[1]), src
[2]));
585 ttn_xpd(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
587 ttn_move_dest_masked(b
, dest
,
590 ttn_swizzle(b
, src
[0], Y
, Z
, X
, X
),
591 ttn_swizzle(b
, src
[1], Z
, X
, Y
, X
)),
593 ttn_swizzle(b
, src
[1], Y
, Z
, X
, X
),
594 ttn_swizzle(b
, src
[0], Z
, X
, Y
, X
))),
596 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
600 ttn_dp2a(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
602 ttn_move_dest(b
, dest
,
603 ttn_channel(b
, nir_fadd(b
, nir_fdot2(b
, src
[0], src
[1]),
609 ttn_dp2(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
611 ttn_move_dest(b
, dest
, nir_fdot2(b
, src
[0], src
[1]));
615 ttn_dp3(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
617 ttn_move_dest(b
, dest
, nir_fdot3(b
, src
[0], src
[1]));
621 ttn_dp4(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
623 ttn_move_dest(b
, dest
, nir_fdot4(b
, src
[0], src
[1]));
627 ttn_dph(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
629 ttn_move_dest(b
, dest
, nir_fadd(b
, nir_fdot3(b
, src
[0], src
[1]),
630 ttn_channel(b
, src
[1], W
)));
634 ttn_umad(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
636 ttn_move_dest(b
, dest
, nir_iadd(b
, nir_imul(b
, src
[0], src
[1]), src
[2]));
640 ttn_arr(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
642 ttn_move_dest(b
, dest
, nir_ffloor(b
, nir_fadd(b
, src
[0], nir_imm_float(b
, 0.5))));
646 ttn_cmp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
648 ttn_move_dest(b
, dest
, nir_bcsel(b
,
649 nir_flt(b
, src
[0], nir_imm_float(b
, 0.0)),
654 ttn_ucmp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
656 ttn_move_dest(b
, dest
, nir_bcsel(b
,
657 nir_ine(b
, src
[0], nir_imm_int(b
, 0)),
662 ttn_kill(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
664 nir_intrinsic_instr
*discard
=
665 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard
);
666 nir_instr_insert_after_cf_list(b
->cf_node_list
, &discard
->instr
);
670 ttn_kill_if(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
672 nir_ssa_def
*cmp
= nir_bany4(b
, nir_flt(b
, src
[0], nir_imm_float(b
, 0.0)));
673 nir_intrinsic_instr
*discard
=
674 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
675 discard
->src
[0] = nir_src_for_ssa(cmp
);
676 nir_instr_insert_after_cf_list(b
->cf_node_list
, &discard
->instr
);
680 ttn_if(struct ttn_compile
*c
, nir_ssa_def
*src
, bool is_uint
)
682 nir_builder
*b
= &c
->build
;
684 /* Save the outside-of-the-if-statement node list. */
685 c
->if_stack
[c
->if_stack_pos
] = b
->cf_node_list
;
688 src
= ttn_channel(b
, src
, X
);
690 nir_if
*if_stmt
= nir_if_create(b
->shader
);
692 if_stmt
->condition
= nir_src_for_ssa(nir_ine(b
, src
, nir_imm_int(b
, 0)));
694 if_stmt
->condition
= nir_src_for_ssa(nir_fne(b
, src
, nir_imm_int(b
, 0)));
696 nir_cf_node_insert_end(b
->cf_node_list
, &if_stmt
->cf_node
);
698 nir_builder_insert_after_cf_list(b
, &if_stmt
->then_list
);
700 c
->if_stack
[c
->if_stack_pos
] = &if_stmt
->else_list
;
705 ttn_else(struct ttn_compile
*c
)
707 nir_builder
*b
= &c
->build
;
709 nir_builder_insert_after_cf_list(b
, c
->if_stack
[c
->if_stack_pos
- 1]);
713 ttn_endif(struct ttn_compile
*c
)
715 nir_builder
*b
= &c
->build
;
717 c
->if_stack_pos
-= 2;
718 nir_builder_insert_after_cf_list(b
, c
->if_stack
[c
->if_stack_pos
]);
722 ttn_bgnloop(struct ttn_compile
*c
)
724 nir_builder
*b
= &c
->build
;
726 /* Save the outside-of-the-loop node list. */
727 c
->loop_stack
[c
->loop_stack_pos
] = b
->cf_node_list
;
730 nir_loop
*loop
= nir_loop_create(b
->shader
);
731 nir_cf_node_insert_end(b
->cf_node_list
, &loop
->cf_node
);
733 nir_builder_insert_after_cf_list(b
, &loop
->body
);
737 ttn_cont(nir_builder
*b
)
739 nir_jump_instr
*instr
= nir_jump_instr_create(b
->shader
, nir_jump_continue
);
740 nir_instr_insert_after_cf_list(b
->cf_node_list
, &instr
->instr
);
744 ttn_brk(nir_builder
*b
)
746 nir_jump_instr
*instr
= nir_jump_instr_create(b
->shader
, nir_jump_break
);
747 nir_instr_insert_after_cf_list(b
->cf_node_list
, &instr
->instr
);
751 ttn_endloop(struct ttn_compile
*c
)
753 nir_builder
*b
= &c
->build
;
756 nir_builder_insert_after_cf_list(b
, c
->loop_stack
[c
->loop_stack_pos
]);
760 ttn_tex(struct ttn_compile
*c
, nir_alu_dest dest
, nir_ssa_def
**src
)
762 nir_builder
*b
= &c
->build
;
763 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
764 nir_tex_instr
*instr
;
768 switch (tgsi_inst
->Instruction
.Opcode
) {
769 case TGSI_OPCODE_TEX
:
773 case TGSI_OPCODE_TXP
:
777 case TGSI_OPCODE_TXB
:
781 case TGSI_OPCODE_TXL
:
785 case TGSI_OPCODE_TXF
:
789 case TGSI_OPCODE_TXD
:
794 fprintf(stderr
, "unknown TGSI tex op %d\n", tgsi_inst
->Instruction
.Opcode
);
798 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
799 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
800 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
801 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
802 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
803 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
804 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
808 instr
= nir_tex_instr_create(b
->shader
, num_srcs
);
811 switch (tgsi_inst
->Texture
.Texture
) {
812 case TGSI_TEXTURE_1D
:
813 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
815 case TGSI_TEXTURE_1D_ARRAY
:
816 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
817 instr
->is_array
= true;
819 case TGSI_TEXTURE_SHADOW1D
:
820 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
821 instr
->is_shadow
= true;
823 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
824 instr
->sampler_dim
= GLSL_SAMPLER_DIM_1D
;
825 instr
->is_shadow
= true;
826 instr
->is_array
= true;
828 case TGSI_TEXTURE_2D
:
829 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
831 case TGSI_TEXTURE_2D_ARRAY
:
832 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
833 instr
->is_array
= true;
835 case TGSI_TEXTURE_2D_MSAA
:
836 instr
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
838 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
839 instr
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
840 instr
->is_array
= true;
842 case TGSI_TEXTURE_SHADOW2D
:
843 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
844 instr
->is_shadow
= true;
846 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
847 instr
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
848 instr
->is_shadow
= true;
849 instr
->is_array
= true;
851 case TGSI_TEXTURE_3D
:
852 instr
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
854 case TGSI_TEXTURE_CUBE
:
855 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
857 case TGSI_TEXTURE_CUBE_ARRAY
:
858 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
859 instr
->is_array
= true;
861 case TGSI_TEXTURE_SHADOWCUBE
:
862 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
863 instr
->is_shadow
= true;
865 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
866 instr
->sampler_dim
= GLSL_SAMPLER_DIM_CUBE
;
867 instr
->is_shadow
= true;
868 instr
->is_array
= true;
870 case TGSI_TEXTURE_RECT
:
871 instr
->sampler_dim
= GLSL_SAMPLER_DIM_RECT
;
873 case TGSI_TEXTURE_SHADOWRECT
:
874 instr
->sampler_dim
= GLSL_SAMPLER_DIM_RECT
;
875 instr
->is_shadow
= true;
878 fprintf(stderr
, "Unknown TGSI texture target %d\n",
879 tgsi_inst
->Texture
.Texture
);
883 switch (instr
->sampler_dim
) {
884 case GLSL_SAMPLER_DIM_1D
:
885 case GLSL_SAMPLER_DIM_BUF
:
886 instr
->coord_components
= 1;
888 case GLSL_SAMPLER_DIM_2D
:
889 case GLSL_SAMPLER_DIM_RECT
:
890 case GLSL_SAMPLER_DIM_EXTERNAL
:
891 case GLSL_SAMPLER_DIM_MS
:
892 instr
->coord_components
= 2;
894 case GLSL_SAMPLER_DIM_3D
:
895 case GLSL_SAMPLER_DIM_CUBE
:
896 instr
->coord_components
= 3;
901 instr
->coord_components
++;
903 assert(tgsi_inst
->Src
[1].Register
.File
== TGSI_FILE_SAMPLER
);
904 instr
->sampler_index
= tgsi_inst
->Src
[1].Register
.Index
;
906 unsigned src_number
= 0;
908 if (tgsi_inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
) {
909 instr
->src
[src_number
].src
=
910 nir_src_for_ssa(nir_swizzle(b
, src
[0], SWIZ(X
, Y
, Z
, W
),
911 instr
->coord_components
, false));
912 instr
->src
[src_number
].src_type
= nir_tex_src_coord
;
916 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
917 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
918 instr
->src
[src_number
].src_type
= nir_tex_src_projector
;
922 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
) {
923 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
924 instr
->src
[src_number
].src_type
= nir_tex_src_bias
;
928 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
) {
929 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
930 instr
->src
[src_number
].src_type
= nir_tex_src_lod
;
934 if (instr
->is_shadow
) {
935 if (instr
->coord_components
< 3)
936 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], Z
));
938 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
940 instr
->src
[src_number
].src_type
= nir_tex_src_comparitor
;
944 assert(src_number
== num_srcs
);
946 nir_ssa_dest_init(&instr
->instr
, &instr
->dest
, 4, NULL
);
947 nir_instr_insert_after_cf_list(b
->cf_node_list
, &instr
->instr
);
949 /* Resolve the writemask on the texture op. */
950 ttn_move_dest(b
, dest
, &instr
->dest
.ssa
);
953 static const nir_op op_trans
[TGSI_OPCODE_LAST
] = {
954 [TGSI_OPCODE_ARL
] = 0,
955 [TGSI_OPCODE_MOV
] = nir_op_fmov
,
956 [TGSI_OPCODE_LIT
] = 0,
957 [TGSI_OPCODE_RCP
] = nir_op_frcp
,
958 [TGSI_OPCODE_RSQ
] = nir_op_frsq
,
959 [TGSI_OPCODE_EXP
] = 0,
960 [TGSI_OPCODE_LOG
] = 0,
961 [TGSI_OPCODE_MUL
] = nir_op_fmul
,
962 [TGSI_OPCODE_ADD
] = nir_op_fadd
,
963 [TGSI_OPCODE_DP3
] = 0,
964 [TGSI_OPCODE_DP4
] = 0,
965 [TGSI_OPCODE_DST
] = 0,
966 [TGSI_OPCODE_MIN
] = nir_op_fmin
,
967 [TGSI_OPCODE_MAX
] = nir_op_fmax
,
968 [TGSI_OPCODE_SLT
] = nir_op_slt
,
969 [TGSI_OPCODE_SGE
] = nir_op_sge
,
970 [TGSI_OPCODE_MAD
] = nir_op_ffma
,
971 [TGSI_OPCODE_SUB
] = nir_op_fsub
,
972 [TGSI_OPCODE_LRP
] = 0,
973 [TGSI_OPCODE_SQRT
] = nir_op_fsqrt
,
974 [TGSI_OPCODE_DP2A
] = 0,
975 [TGSI_OPCODE_FRC
] = nir_op_ffract
,
976 [TGSI_OPCODE_CLAMP
] = 0,
977 [TGSI_OPCODE_FLR
] = nir_op_ffloor
,
978 [TGSI_OPCODE_ROUND
] = nir_op_fround_even
,
979 [TGSI_OPCODE_EX2
] = nir_op_fexp2
,
980 [TGSI_OPCODE_LG2
] = nir_op_flog2
,
981 [TGSI_OPCODE_POW
] = nir_op_fpow
,
982 [TGSI_OPCODE_XPD
] = 0,
983 [TGSI_OPCODE_ABS
] = nir_op_fabs
,
984 [TGSI_OPCODE_DPH
] = 0,
985 [TGSI_OPCODE_COS
] = nir_op_fcos
,
986 [TGSI_OPCODE_DDX
] = nir_op_fddx
,
987 [TGSI_OPCODE_DDY
] = nir_op_fddy
,
988 [TGSI_OPCODE_KILL
] = 0,
989 [TGSI_OPCODE_PK2H
] = 0, /* XXX */
990 [TGSI_OPCODE_PK2US
] = 0, /* XXX */
991 [TGSI_OPCODE_PK4B
] = 0, /* XXX */
992 [TGSI_OPCODE_PK4UB
] = 0, /* XXX */
993 [TGSI_OPCODE_SEQ
] = nir_op_seq
,
994 [TGSI_OPCODE_SGT
] = 0,
995 [TGSI_OPCODE_SIN
] = nir_op_fsin
,
996 [TGSI_OPCODE_SLE
] = 0,
997 [TGSI_OPCODE_TEX
] = 0,
998 [TGSI_OPCODE_TXD
] = 0,
999 [TGSI_OPCODE_TXP
] = 0,
1000 [TGSI_OPCODE_UP2H
] = 0, /* XXX */
1001 [TGSI_OPCODE_UP2US
] = 0, /* XXX */
1002 [TGSI_OPCODE_UP4B
] = 0, /* XXX */
1003 [TGSI_OPCODE_UP4UB
] = 0, /* XXX */
1004 [TGSI_OPCODE_ARR
] = 0,
1006 /* No function calls, yet. */
1007 [TGSI_OPCODE_CAL
] = 0, /* XXX */
1008 [TGSI_OPCODE_RET
] = 0, /* XXX */
1010 [TGSI_OPCODE_SSG
] = nir_op_fsign
,
1011 [TGSI_OPCODE_CMP
] = 0,
1012 [TGSI_OPCODE_SCS
] = 0,
1013 [TGSI_OPCODE_TXB
] = 0,
1014 [TGSI_OPCODE_DIV
] = nir_op_fdiv
,
1015 [TGSI_OPCODE_DP2
] = 0,
1016 [TGSI_OPCODE_DP2A
] = 0,
1017 [TGSI_OPCODE_TXL
] = 0,
1019 [TGSI_OPCODE_BRK
] = 0,
1020 [TGSI_OPCODE_IF
] = 0,
1021 [TGSI_OPCODE_UIF
] = 0,
1022 [TGSI_OPCODE_ELSE
] = 0,
1023 [TGSI_OPCODE_ENDIF
] = 0,
1025 [TGSI_OPCODE_DDX_FINE
] = nir_op_fddx_fine
,
1026 [TGSI_OPCODE_DDY_FINE
] = nir_op_fddy_fine
,
1028 [TGSI_OPCODE_PUSHA
] = 0, /* XXX */
1029 [TGSI_OPCODE_POPA
] = 0, /* XXX */
1031 [TGSI_OPCODE_CEIL
] = nir_op_fceil
,
1032 [TGSI_OPCODE_I2F
] = nir_op_i2f
,
1033 [TGSI_OPCODE_NOT
] = nir_op_inot
,
1034 [TGSI_OPCODE_TRUNC
] = nir_op_ftrunc
,
1035 [TGSI_OPCODE_SHL
] = nir_op_ishl
,
1036 [TGSI_OPCODE_AND
] = nir_op_iand
,
1037 [TGSI_OPCODE_OR
] = nir_op_ior
,
1038 [TGSI_OPCODE_MOD
] = nir_op_umod
,
1039 [TGSI_OPCODE_XOR
] = nir_op_ixor
,
1040 [TGSI_OPCODE_SAD
] = 0, /* XXX */
1041 [TGSI_OPCODE_TXF
] = 0,
1042 [TGSI_OPCODE_TXQ
] = 0,
1044 [TGSI_OPCODE_CONT
] = 0,
1046 [TGSI_OPCODE_EMIT
] = 0, /* XXX */
1047 [TGSI_OPCODE_ENDPRIM
] = 0, /* XXX */
1049 [TGSI_OPCODE_BGNLOOP
] = 0,
1050 [TGSI_OPCODE_BGNSUB
] = 0, /* XXX: no function calls */
1051 [TGSI_OPCODE_ENDLOOP
] = 0,
1052 [TGSI_OPCODE_ENDSUB
] = 0, /* XXX: no function calls */
1054 [TGSI_OPCODE_TXQ_LZ
] = 0,
1055 [TGSI_OPCODE_NOP
] = 0,
1056 [TGSI_OPCODE_FSEQ
] = nir_op_feq
,
1057 [TGSI_OPCODE_FSGE
] = nir_op_fge
,
1058 [TGSI_OPCODE_FSLT
] = nir_op_flt
,
1059 [TGSI_OPCODE_FSNE
] = nir_op_fne
,
1061 /* No control flow yet */
1062 [TGSI_OPCODE_CALLNZ
] = 0, /* XXX */
1063 [TGSI_OPCODE_BREAKC
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1065 [TGSI_OPCODE_KILL_IF
] = 0,
1067 [TGSI_OPCODE_END
] = 0,
1069 [TGSI_OPCODE_F2I
] = nir_op_f2i
,
1070 [TGSI_OPCODE_IDIV
] = nir_op_idiv
,
1071 [TGSI_OPCODE_IMAX
] = nir_op_imax
,
1072 [TGSI_OPCODE_IMIN
] = nir_op_imin
,
1073 [TGSI_OPCODE_INEG
] = nir_op_ineg
,
1074 [TGSI_OPCODE_ISGE
] = nir_op_ige
,
1075 [TGSI_OPCODE_ISHR
] = nir_op_ishr
,
1076 [TGSI_OPCODE_ISLT
] = nir_op_ilt
,
1077 [TGSI_OPCODE_F2U
] = nir_op_f2u
,
1078 [TGSI_OPCODE_U2F
] = nir_op_u2f
,
1079 [TGSI_OPCODE_UADD
] = nir_op_iadd
,
1080 [TGSI_OPCODE_UDIV
] = nir_op_udiv
,
1081 [TGSI_OPCODE_UMAD
] = 0,
1082 [TGSI_OPCODE_UMAX
] = nir_op_umax
,
1083 [TGSI_OPCODE_UMIN
] = nir_op_umin
,
1084 [TGSI_OPCODE_UMOD
] = nir_op_umod
,
1085 [TGSI_OPCODE_UMUL
] = nir_op_imul
,
1086 [TGSI_OPCODE_USEQ
] = nir_op_ieq
,
1087 [TGSI_OPCODE_USGE
] = nir_op_uge
,
1088 [TGSI_OPCODE_USHR
] = nir_op_ushr
,
1089 [TGSI_OPCODE_USLT
] = nir_op_ult
,
1090 [TGSI_OPCODE_USNE
] = nir_op_ine
,
1092 [TGSI_OPCODE_SWITCH
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1093 [TGSI_OPCODE_CASE
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1094 [TGSI_OPCODE_DEFAULT
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1095 [TGSI_OPCODE_ENDSWITCH
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1097 /* XXX: SAMPLE opcodes */
1099 [TGSI_OPCODE_UARL
] = nir_op_imov
,
1100 [TGSI_OPCODE_UCMP
] = 0,
1101 [TGSI_OPCODE_IABS
] = nir_op_iabs
,
1102 [TGSI_OPCODE_ISSG
] = nir_op_isign
,
1106 [TGSI_OPCODE_TEX2
] = 0,
1107 [TGSI_OPCODE_TXB2
] = 0,
1108 [TGSI_OPCODE_TXL2
] = 0,
1110 [TGSI_OPCODE_IMUL_HI
] = nir_op_imul_high
,
1111 [TGSI_OPCODE_UMUL_HI
] = nir_op_umul_high
,
1113 [TGSI_OPCODE_TG4
] = 0,
1114 [TGSI_OPCODE_LODQ
] = 0, /* XXX */
1116 [TGSI_OPCODE_IBFE
] = nir_op_ibitfield_extract
,
1117 [TGSI_OPCODE_UBFE
] = nir_op_ubitfield_extract
,
1118 [TGSI_OPCODE_BFI
] = nir_op_bitfield_insert
,
1119 [TGSI_OPCODE_BREV
] = nir_op_bitfield_reverse
,
1120 [TGSI_OPCODE_POPC
] = nir_op_bit_count
,
1121 [TGSI_OPCODE_LSB
] = nir_op_find_lsb
,
1122 [TGSI_OPCODE_IMSB
] = nir_op_ifind_msb
,
1123 [TGSI_OPCODE_UMSB
] = nir_op_ifind_msb
, /* XXX: signed vs unsigned */
1125 [TGSI_OPCODE_INTERP_CENTROID
] = 0, /* XXX */
1126 [TGSI_OPCODE_INTERP_SAMPLE
] = 0, /* XXX */
1127 [TGSI_OPCODE_INTERP_OFFSET
] = 0, /* XXX */
1131 ttn_emit_instruction(struct ttn_compile
*c
)
1133 nir_builder
*b
= &c
->build
;
1134 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
1136 unsigned tgsi_op
= tgsi_inst
->Instruction
.Opcode
;
1138 if (tgsi_op
== TGSI_OPCODE_END
)
1141 nir_ssa_def
*src
[TGSI_FULL_MAX_SRC_REGISTERS
];
1142 for (i
= 0; i
< TGSI_FULL_MAX_SRC_REGISTERS
; i
++) {
1143 src
[i
] = ttn_get_src(c
, &tgsi_inst
->Src
[i
]);
1145 nir_alu_dest dest
= ttn_get_dest(c
, &tgsi_inst
->Dst
[0]);
1148 case TGSI_OPCODE_RSQ
:
1149 ttn_move_dest(b
, dest
, nir_frsq(b
, ttn_channel(b
, src
[0], X
)));
1152 case TGSI_OPCODE_SQRT
:
1153 ttn_move_dest(b
, dest
, nir_fsqrt(b
, ttn_channel(b
, src
[0], X
)));
1156 case TGSI_OPCODE_RCP
:
1157 ttn_move_dest(b
, dest
, nir_frcp(b
, ttn_channel(b
, src
[0], X
)));
1160 case TGSI_OPCODE_EX2
:
1161 ttn_move_dest(b
, dest
, nir_fexp2(b
, ttn_channel(b
, src
[0], X
)));
1164 case TGSI_OPCODE_LG2
:
1165 ttn_move_dest(b
, dest
, nir_flog2(b
, ttn_channel(b
, src
[0], X
)));
1168 case TGSI_OPCODE_POW
:
1169 ttn_move_dest(b
, dest
, nir_fpow(b
,
1170 ttn_channel(b
, src
[0], X
),
1171 ttn_channel(b
, src
[1], X
)));
1174 case TGSI_OPCODE_COS
:
1175 ttn_move_dest(b
, dest
, nir_fcos(b
, ttn_channel(b
, src
[0], X
)));
1178 case TGSI_OPCODE_SIN
:
1179 ttn_move_dest(b
, dest
, nir_fsin(b
, ttn_channel(b
, src
[0], X
)));
1182 case TGSI_OPCODE_ARL
:
1183 ttn_arl(b
, op_trans
[tgsi_op
], dest
, src
);
1186 case TGSI_OPCODE_EXP
:
1187 ttn_exp(b
, op_trans
[tgsi_op
], dest
, src
);
1190 case TGSI_OPCODE_LOG
:
1191 ttn_log(b
, op_trans
[tgsi_op
], dest
, src
);
1194 case TGSI_OPCODE_DST
:
1195 ttn_dst(b
, op_trans
[tgsi_op
], dest
, src
);
1198 case TGSI_OPCODE_LIT
:
1199 ttn_lit(b
, op_trans
[tgsi_op
], dest
, src
);
1202 case TGSI_OPCODE_CLAMP
:
1203 ttn_clamp(b
, op_trans
[tgsi_op
], dest
, src
);
1206 case TGSI_OPCODE_XPD
:
1207 ttn_xpd(b
, op_trans
[tgsi_op
], dest
, src
);
1210 case TGSI_OPCODE_DP2
:
1211 ttn_dp2(b
, op_trans
[tgsi_op
], dest
, src
);
1214 case TGSI_OPCODE_DP3
:
1215 ttn_dp3(b
, op_trans
[tgsi_op
], dest
, src
);
1218 case TGSI_OPCODE_DP4
:
1219 ttn_dp4(b
, op_trans
[tgsi_op
], dest
, src
);
1222 case TGSI_OPCODE_DP2A
:
1223 ttn_dp2a(b
, op_trans
[tgsi_op
], dest
, src
);
1226 case TGSI_OPCODE_DPH
:
1227 ttn_dph(b
, op_trans
[tgsi_op
], dest
, src
);
1230 case TGSI_OPCODE_UMAD
:
1231 ttn_umad(b
, op_trans
[tgsi_op
], dest
, src
);
1234 case TGSI_OPCODE_LRP
:
1235 ttn_move_dest(b
, dest
, nir_flrp(b
, src
[2], src
[1], src
[0]));
1238 case TGSI_OPCODE_KILL
:
1239 ttn_kill(b
, op_trans
[tgsi_op
], dest
, src
);
1242 case TGSI_OPCODE_ARR
:
1243 ttn_arr(b
, op_trans
[tgsi_op
], dest
, src
);
1246 case TGSI_OPCODE_CMP
:
1247 ttn_cmp(b
, op_trans
[tgsi_op
], dest
, src
);
1250 case TGSI_OPCODE_UCMP
:
1251 ttn_ucmp(b
, op_trans
[tgsi_op
], dest
, src
);
1254 case TGSI_OPCODE_SCS
:
1255 ttn_scs(b
, op_trans
[tgsi_op
], dest
, src
);
1258 case TGSI_OPCODE_SGT
:
1259 ttn_sgt(b
, op_trans
[tgsi_op
], dest
, src
);
1262 case TGSI_OPCODE_SLE
:
1263 ttn_sle(b
, op_trans
[tgsi_op
], dest
, src
);
1266 case TGSI_OPCODE_KILL_IF
:
1267 ttn_kill_if(b
, op_trans
[tgsi_op
], dest
, src
);
1270 case TGSI_OPCODE_TEX
:
1271 case TGSI_OPCODE_TXP
:
1272 case TGSI_OPCODE_TXL
:
1273 case TGSI_OPCODE_TXB
:
1274 case TGSI_OPCODE_TXD
:
1275 case TGSI_OPCODE_TXQ
:
1276 case TGSI_OPCODE_TXL2
:
1277 case TGSI_OPCODE_TXB2
:
1278 case TGSI_OPCODE_TXQ_LZ
:
1279 case TGSI_OPCODE_TXF
:
1280 case TGSI_OPCODE_TG4
:
1281 ttn_tex(c
, dest
, src
);
1284 case TGSI_OPCODE_NOP
:
1287 case TGSI_OPCODE_IF
:
1288 ttn_if(c
, src
[0], false);
1291 case TGSI_OPCODE_UIF
:
1292 ttn_if(c
, src
[0], true);
1295 case TGSI_OPCODE_ELSE
:
1299 case TGSI_OPCODE_ENDIF
:
1303 case TGSI_OPCODE_BGNLOOP
:
1307 case TGSI_OPCODE_BRK
:
1311 case TGSI_OPCODE_CONT
:
1315 case TGSI_OPCODE_ENDLOOP
:
1320 if (op_trans
[tgsi_op
] != 0 || tgsi_op
== TGSI_OPCODE_MOV
) {
1321 ttn_alu(b
, op_trans
[tgsi_op
], dest
, src
);
1323 fprintf(stderr
, "unknown TGSI opcode: %s\n",
1324 tgsi_get_opcode_name(tgsi_op
));
1330 if (tgsi_inst
->Instruction
.Saturate
) {
1331 assert(tgsi_inst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
);
1332 assert(!dest
.dest
.is_ssa
);
1333 ttn_move_dest(b
, dest
, nir_fsat(b
, ttn_src_for_dest(b
, &dest
)));
1338 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
1339 * variables at the end of the shader.
1341 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
1342 * written, because there's no output load intrinsic, which means we couldn't
1343 * handle writemasks.
1346 ttn_add_output_stores(struct ttn_compile
*c
)
1348 nir_builder
*b
= &c
->build
;
1350 foreach_list_typed(nir_variable
, var
, node
, &b
->shader
->outputs
) {
1351 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1354 for (i
= 0; i
< array_len
; i
++) {
1355 nir_intrinsic_instr
*store
=
1356 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
1357 store
->num_components
= 4;
1358 store
->const_index
[0] = var
->data
.driver_location
+ i
;
1359 store
->const_index
[1] = 1;
1360 store
->src
[0].reg
.reg
= c
->output_regs
[var
->data
.driver_location
].reg
;
1361 nir_instr_insert_after_cf_list(b
->cf_node_list
, &store
->instr
);
1367 tgsi_to_nir(const void *tgsi_tokens
,
1368 const nir_shader_compiler_options
*options
)
1370 struct tgsi_parse_context parser
;
1371 struct tgsi_shader_info scan
;
1372 struct ttn_compile
*c
;
1373 struct nir_shader
*s
;
1376 c
= rzalloc(NULL
, struct ttn_compile
);
1377 s
= nir_shader_create(NULL
, options
);
1379 nir_function
*func
= nir_function_create(s
, "main");
1380 nir_function_overload
*overload
= nir_function_overload_create(func
);
1381 nir_function_impl
*impl
= nir_function_impl_create(overload
);
1383 nir_builder_init(&c
->build
, impl
);
1384 nir_builder_insert_after_cf_list(&c
->build
, &impl
->body
);
1386 tgsi_scan_shader(tgsi_tokens
, &scan
);
1389 s
->num_inputs
= scan
.file_max
[TGSI_FILE_INPUT
] + 1;
1390 s
->num_uniforms
= scan
.file_max
[TGSI_FILE_CONSTANT
] + 1;
1391 s
->num_outputs
= scan
.file_max
[TGSI_FILE_OUTPUT
] + 1;
1393 c
->output_regs
= rzalloc_array(c
, struct ttn_reg_info
,
1394 scan
.file_max
[TGSI_FILE_OUTPUT
] + 1);
1395 c
->temp_regs
= rzalloc_array(c
, struct ttn_reg_info
,
1396 scan
.file_max
[TGSI_FILE_TEMPORARY
] + 1);
1397 c
->imm_defs
= rzalloc_array(c
, nir_ssa_def
*,
1398 scan
.file_max
[TGSI_FILE_IMMEDIATE
] + 1);
1400 c
->if_stack
= rzalloc_array(c
, struct exec_list
*,
1401 (scan
.opcode_count
[TGSI_OPCODE_IF
] +
1402 scan
.opcode_count
[TGSI_OPCODE_UIF
]) * 2);
1403 c
->loop_stack
= rzalloc_array(c
, struct exec_list
*,
1404 scan
.opcode_count
[TGSI_OPCODE_BGNLOOP
]);
1406 ret
= tgsi_parse_init(&parser
, tgsi_tokens
);
1407 assert(ret
== TGSI_PARSE_OK
);
1409 while (!tgsi_parse_end_of_tokens(&parser
)) {
1410 tgsi_parse_token(&parser
);
1411 c
->token
= &parser
.FullToken
;
1413 switch (parser
.FullToken
.Token
.Type
) {
1414 case TGSI_TOKEN_TYPE_DECLARATION
:
1415 ttn_emit_declaration(c
);
1418 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1419 ttn_emit_instruction(c
);
1422 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1423 ttn_emit_immediate(c
);
1428 tgsi_parse_free(&parser
);
1430 ttn_add_output_stores(c
);