src/gallium/auxiliary/rtasm/rtasm_ppc_spe.c

   1 /*
   2  * (C) Copyright IBM Corporation 2008
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  19  * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * \file
  27  * Real-time assembly generation interface for Cell B.E. SPEs.
  28  *
  29  * \author Ian Romanick <idr@us.ibm.com>
  30  * \author Brian Paul
  31  */
  32
  33
  34 #include <stdio.h>
  35 #include "pipe/p_compiler.h"
  36 #include "util/u_memory.h"
  37 #include "rtasm_ppc_spe.h"
  38
  39
  40 #ifdef GALLIUM_CELL
  41 /**
  42  * SPE instruction types
  43  *
  44  * There are 6 primary instruction encodings used on the Cell's SPEs.  Each of
  45  * the following unions encodes one type.
  46  *
  47  * \bug
  48  * If, at some point, we start generating SPE code from a little-endian host
  49  * these unions will not work.
  50  */
  51 /*@{*/
  52 /**
  53  * Encode one output register with two input registers
  54  */
  55 union spe_inst_RR {
  56     uint32_t bits;
  57     struct {
  58         unsigned op:11;
  59         unsigned rB:7;
  60         unsigned rA:7;
  61         unsigned rT:7;
  62     } inst;
  63 };
  64
  65
  66 /**
  67  * Encode one output register with three input registers
  68  */
  69 union spe_inst_RRR {
  70     uint32_t bits;
  71     struct {
  72         unsigned op:4;
  73         unsigned rT:7;
  74         unsigned rB:7;
  75         unsigned rA:7;
  76         unsigned rC:7;
  77     } inst;
  78 };
  79
  80
  81 /**
  82  * Encode one output register with one input reg. and a 7-bit signed immed
  83  */
  84 union spe_inst_RI7 {
  85     uint32_t bits;
  86     struct {
  87         unsigned op:11;
  88         unsigned i7:7;
  89         unsigned rA:7;
  90         unsigned rT:7;
  91     } inst;
  92 };
  93
  94
  95 /**
  96  * Encode one output register with one input reg. and an 8-bit signed immed
  97  */
  98 union spe_inst_RI8 {
  99     uint32_t bits;
 100     struct {
 101         unsigned op:10;
 102         unsigned i8:8;
 103         unsigned rA:7;
 104         unsigned rT:7;
 105     } inst;
 106 };
 107
 108
 109 /**
 110  * Encode one output register with one input reg. and a 10-bit signed immed
 111  */
 112 union spe_inst_RI10 {
 113     uint32_t bits;
 114     struct {
 115         unsigned op:8;
 116         unsigned i10:10;
 117         unsigned rA:7;
 118         unsigned rT:7;
 119     } inst;
 120 };
 121
 122
 123 /**
 124  * Encode one output register with a 16-bit signed immediate
 125  */
 126 union spe_inst_RI16 {
 127     uint32_t bits;
 128     struct {
 129         unsigned op:9;
 130         unsigned i16:16;
 131         unsigned rT:7;
 132     } inst;
 133 };
 134
 135
 136 /**
 137  * Encode one output register with a 18-bit signed immediate
 138  */
 139 union spe_inst_RI18 {
 140     uint32_t bits;
 141     struct {
 142         unsigned op:7;
 143         unsigned i18:18;
 144         unsigned rT:7;
 145     } inst;
 146 };
 147 /*@}*/
 148
 149
 150 static void
 151 indent(const struct spe_function *p)
 152 {
 153    int i;
 154    for (i = 0; i < p->indent; i++) {
 155       putchar(' ');
 156    }
 157 }
 158
 159
 160 static const char *
 161 rem_prefix(const char *longname)
 162 {
 163    return longname + 4;
 164 }
 165
 166
 167 static void emit_RR(struct spe_function *p, unsigned op, unsigned rT,
 168                     unsigned rA, unsigned rB, const char *name)
 169 {
 170     union spe_inst_RR inst;
 171     inst.inst.op = op;
 172     inst.inst.rB = rB;
 173     inst.inst.rA = rA;
 174     inst.inst.rT = rT;
 175     p->store[p->num_inst++] = inst.bits;
 176     assert(p->num_inst <= p->max_inst);
 177     if (p->print) {
 178        indent(p);
 179        printf("%s\t$%d, $%d, $%d\n", rem_prefix(name), rT, rA, rB);
 180     }
 181 }
 182
 183
 184 static void emit_RRR(struct spe_function *p, unsigned op, unsigned rT,
 185                      unsigned rA, unsigned rB, unsigned rC, const char *name)
 186 {
 187     union spe_inst_RRR inst;
 188     inst.inst.op = op;
 189     inst.inst.rT = rT;
 190     inst.inst.rB = rB;
 191     inst.inst.rA = rA;
 192     inst.inst.rC = rC;
 193     p->store[p->num_inst++] = inst.bits;
 194     assert(p->num_inst <= p->max_inst);
 195     if (p->print) {
 196        indent(p);
 197        printf("%s\t$%d, $%d, $%d, $%d\n", rem_prefix(name), rT, rA, rB, rC);
 198     }
 199 }
 200
 201
 202 static void emit_RI7(struct spe_function *p, unsigned op, unsigned rT,
 203                      unsigned rA, int imm, const char *name)
 204 {
 205     union spe_inst_RI7 inst;
 206     inst.inst.op = op;
 207     inst.inst.i7 = imm;
 208     inst.inst.rA = rA;
 209     inst.inst.rT = rT;
 210     p->store[p->num_inst++] = inst.bits;
 211     assert(p->num_inst <= p->max_inst);
 212     if (p->print) {
 213        indent(p);
 214        printf("%s\t$%d, $%d, 0x%x\n", rem_prefix(name), rT, rA, imm);
 215     }
 216 }
 217
 218
 219
 220 static void emit_RI8(struct spe_function *p, unsigned op, unsigned rT,
 221                      unsigned rA, int imm, const char *name)
 222 {
 223     union spe_inst_RI8 inst;
 224     inst.inst.op = op;
 225     inst.inst.i8 = imm;
 226     inst.inst.rA = rA;
 227     inst.inst.rT = rT;
 228     p->store[p->num_inst++] = inst.bits;
 229     assert(p->num_inst <= p->max_inst);
 230     if (p->print) {
 231        indent(p);
 232        printf("%s\t$%d, $%d, 0x%x\n", rem_prefix(name), rT, rA, imm);
 233     }
 234 }
 235
 236
 237
 238 static void emit_RI10(struct spe_function *p, unsigned op, unsigned rT,
 239                       unsigned rA, int imm, const char *name)
 240 {
 241     union spe_inst_RI10 inst;
 242     inst.inst.op = op;
 243     inst.inst.i10 = imm;
 244     inst.inst.rA = rA;
 245     inst.inst.rT = rT;
 246     p->store[p->num_inst++] = inst.bits;
 247     assert(p->num_inst <= p->max_inst);
 248     if (p->print) {
 249        indent(p);
 250        if (strcmp(name, "spe_lqd") == 0 ||
 251            strcmp(name, "spe_stqd") == 0)
 252           printf("%s\t$%d, 0x%x($%d)\n", rem_prefix(name), rT, imm, rA);
 253        else
 254           printf("%s\t$%d, $%d, 0x%x\n", rem_prefix(name), rT, rA, imm);
 255     }
 256 }
 257
 258
 259 static void emit_RI16(struct spe_function *p, unsigned op, unsigned rT,
 260                       int imm, const char *name)
 261 {
 262     union spe_inst_RI16 inst;
 263     inst.inst.op = op;
 264     inst.inst.i16 = imm;
 265     inst.inst.rT = rT;
 266     p->store[p->num_inst++] = inst.bits;
 267     assert(p->num_inst <= p->max_inst);
 268     if (p->print) {
 269        indent(p);
 270        printf("%s\t$%d, 0x%x\n", rem_prefix(name), rT, imm);
 271     }
 272 }
 273
 274
 275 static void emit_RI18(struct spe_function *p, unsigned op, unsigned rT,
 276                       int imm, const char *name)
 277 {
 278     union spe_inst_RI18 inst;
 279     inst.inst.op = op;
 280     inst.inst.i18 = imm;
 281     inst.inst.rT = rT;
 282     p->store[p->num_inst++] = inst.bits;
 283     assert(p->num_inst <= p->max_inst);
 284     if (p->print) {
 285        indent(p);
 286        printf("%s\t$%d, 0x%x\n", rem_prefix(name), rT, imm);
 287     }
 288 }
 289
 290
 291
 292
 293 #define EMIT_(_name, _op) \
 294 void _name (struct spe_function *p, unsigned rT) \
 295 { \
 296    emit_RR(p, _op, rT, 0, 0, __FUNCTION__); \
 297 }
 298
 299 #define EMIT_R(_name, _op) \
 300 void _name (struct spe_function *p, unsigned rT, unsigned rA) \
 301 { \
 302    emit_RR(p, _op, rT, rA, 0, __FUNCTION__);                 \
 303 }
 304
 305 #define EMIT_RR(_name, _op) \
 306 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB) \
 307 { \
 308    emit_RR(p, _op, rT, rA, rB, __FUNCTION__);                \
 309 }
 310
 311 #define EMIT_RRR(_name, _op) \
 312 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB, unsigned rC) \
 313 { \
 314    emit_RRR(p, _op, rT, rA, rB, rC, __FUNCTION__);           \
 315 }
 316
 317 #define EMIT_RI7(_name, _op) \
 318 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
 319 { \
 320    emit_RI7(p, _op, rT, rA, imm, __FUNCTION__);              \
 321 }
 322
 323 #define EMIT_RI8(_name, _op, bias) \
 324 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
 325 { \
 326    emit_RI8(p, _op, rT, rA, bias - imm, __FUNCTION__);       \
 327 }
 328
 329 #define EMIT_RI10(_name, _op) \
 330 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
 331 { \
 332    emit_RI10(p, _op, rT, rA, imm, __FUNCTION__);             \
 333 }
 334
 335 #define EMIT_RI16(_name, _op) \
 336 void _name (struct spe_function *p, unsigned rT, int imm) \
 337 { \
 338    emit_RI16(p, _op, rT, imm, __FUNCTION__);                 \
 339 }
 340
 341 #define EMIT_RI18(_name, _op) \
 342 void _name (struct spe_function *p, unsigned rT, int imm) \
 343 { \
 344    emit_RI18(p, _op, rT, imm, __FUNCTION__);                 \
 345 }
 346
 347 #define EMIT_I16(_name, _op) \
 348 void _name (struct spe_function *p, int imm) \
 349 { \
 350    emit_RI16(p, _op, 0, imm, __FUNCTION__);                  \
 351 }
 352
 353 #include "rtasm_ppc_spe.h"
 354
 355
 356 /**
 357  * Initialize an spe_function.
 358  * \param code_size  size of instruction buffer to allocate, in bytes.
 359  */
 360 void spe_init_func(struct spe_function *p, unsigned code_size)
 361 {
 362     register unsigned int i;
 363
 364     p->store = align_malloc(code_size, 16);
 365     p->num_inst = 0;
 366     p->max_inst = code_size / SPE_INST_SIZE;
 367
 368     p->set_count = 0;
 369     memset(p->regs, 0, SPE_NUM_REGS * sizeof(p->regs[0]));
 370
 371     /* Conservatively treat R0 - R2 and R80 - R127 as non-volatile.
 372      */
 373     p->regs[0] = p->regs[1] = p->regs[2] = 1;
 374     for (i = 80; i <= 127; i++) {
 375       p->regs[i] = 1;
 376     }
 377
 378     p->print = false;
 379     p->indent = 0;
 380 }
 381
 382
 383 void spe_release_func(struct spe_function *p)
 384 {
 385     assert(p->num_inst <= p->max_inst);
 386     if (p->store != NULL) {
 387         align_free(p->store);
 388     }
 389     p->store = NULL;
 390 }
 391
 392
 393 /** Return current code size in bytes. */
 394 unsigned spe_code_size(const struct spe_function *p)
 395 {
 396    return p->num_inst * SPE_INST_SIZE;
 397 }
 398
 399
 400 /**
 401  * Allocate a SPE register.
 402  * \return register index or -1 if none left.
 403  */
 404 int spe_allocate_available_register(struct spe_function *p)
 405 {
 406    unsigned i;
 407    for (i = 0; i < SPE_NUM_REGS; i++) {
 408       if (p->regs[i] == 0) {
 409          p->regs[i] = 1;
 410          return i;
 411       }
 412    }
 413
 414    return -1;
 415 }
 416
 417
 418 /**
 419  * Mark the given SPE register as "allocated".
 420  */
 421 int spe_allocate_register(struct spe_function *p, int reg)
 422 {
 423    assert(reg < SPE_NUM_REGS);
 424    assert(p->regs[reg] == 0);
 425    p->regs[reg] = 1;
 426    return reg;
 427 }
 428
 429
 430 /**
 431  * Mark the given SPE register as "unallocated".  Note that this should
 432  * only be used on registers allocated in the current register set; an
 433  * assertion will fail if an attempt is made to deallocate a register
 434  * allocated in an earlier register set.
 435  */
 436 void spe_release_register(struct spe_function *p, int reg)
 437 {
 438    assert(reg < SPE_NUM_REGS);
 439    assert(p->regs[reg] == 1);
 440
 441    p->regs[reg] = 0;
 442 }
 443
 444 /**
 445  * Start a new set of registers.  This can be called if
 446  * it will be difficult later to determine exactly what
 447  * registers were actually allocated during a code generation
 448  * sequence, and you really just want to deallocate all of them.
 449  */
 450 void spe_allocate_register_set(struct spe_function *p)
 451 {
 452    register unsigned int i;
 453
 454    /* Keep track of the set count.  If it ever wraps around to 0,
 455     * we're in trouble.
 456     */
 457    p->set_count++;
 458    assert(p->set_count > 0);
 459
 460    /* Increment the allocation count of all registers currently
 461     * allocated.  Then any registers that are allocated in this set
 462     * will be the only ones with a count of 1; they'll all be released
 463     * when the register set is released.
 464     */
 465    for (i = 0; i < SPE_NUM_REGS; i++) {
 466       if (p->regs[i] > 0) p->regs[i]++;
 467    }
 468 }
 469
 470 void spe_release_register_set(struct spe_function *p)
 471 {
 472    unsigned int i;
 473
 474    /* If the set count drops below zero, we're in trouble. */
 475    assert(p->set_count > 0);
 476    p->set_count--;
 477
 478    /* Drop the allocation level of all registers.  Any allocated
 479     * during this register set will drop to 0 and then become
 480     * available.
 481     */
 482    for (i = 0; i < SPE_NUM_REGS; i++) {
 483       if (p->regs[i] > 0) p->regs[i]--;
 484    }
 485 }
 486
 487
 488 void
 489 spe_print_code(struct spe_function *p, boolean enable)
 490 {
 491    p->print = enable;
 492 }
 493
 494
 495 void
 496 spe_indent(struct spe_function *p, int spaces)
 497 {
 498    p->indent += spaces;
 499 }
 500
 501
 502 extern void
 503 spe_comment(struct spe_function *p, int rel_indent, const char *s)
 504 {
 505    if (p->print) {
 506       p->indent += rel_indent;
 507       indent(p);
 508       p->indent -= rel_indent;
 509       printf("# %s\n", s);
 510    }
 511 }
 512
 513
 514 /**
 515  * For branch instructions:
 516  * \param d  if 1, disable interupts if branch is taken
 517  * \param e  if 1, enable interupts if branch is taken
 518  * If d and e are both zero, don't change interupt status (right?)
 519  */
 520
 521 /** Branch Indirect to address in rA */
 522 void spe_bi(struct spe_function *p, unsigned rA, int d, int e)
 523 {
 524    emit_RI7(p, 0x1a8, 0, rA, (d << 5) | (e << 4), __FUNCTION__);
 525 }
 526
 527 /** Interupt Return */
 528 void spe_iret(struct spe_function *p, unsigned rA, int d, int e)
 529 {
 530    emit_RI7(p, 0x1aa, 0, rA, (d << 5) | (e << 4), __FUNCTION__);
 531 }
 532
 533 /** Branch indirect and set link on external data */
 534 void spe_bisled(struct spe_function *p, unsigned rT, unsigned rA, int d,
 535                 int e)
 536 {
 537    emit_RI7(p, 0x1ab, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
 538 }
 539
 540 /** Branch indirect and set link.  Save PC in rT, jump to rA. */
 541 void spe_bisl(struct spe_function *p, unsigned rT, unsigned rA, int d,
 542                 int e)
 543 {
 544    emit_RI7(p, 0x1a9, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
 545 }
 546
 547 /** Branch indirect if zero word.  If rT.word[0]==0, jump to rA. */
 548 void spe_biz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
 549 {
 550    emit_RI7(p, 0x128, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
 551 }
 552
 553 /** Branch indirect if non-zero word.  If rT.word[0]!=0, jump to rA. */
 554 void spe_binz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
 555 {
 556    emit_RI7(p, 0x129, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
 557 }
 558
 559 /** Branch indirect if zero halfword.  If rT.halfword[1]==0, jump to rA. */
 560 void spe_bihz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
 561 {
 562    emit_RI7(p, 0x12a, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
 563 }
 564
 565 /** Branch indirect if non-zero halfword.  If rT.halfword[1]!=0, jump to rA. */
 566 void spe_bihnz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
 567 {
 568    emit_RI7(p, 0x12b, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
 569 }
 570
 571
 572 /* Hint-for-branch instructions
 573  */
 574 #if 0
 575 hbr;
 576 hbra;
 577 hbrr;
 578 #endif
 579
 580
 581 /* Control instructions
 582  */
 583 #if 0
 584 stop;
 585 EMIT_RR  (spe_stopd, 0x140);
 586 EMIT_    (spe_lnop,  0x001);
 587 EMIT_    (spe_nop,   0x201);
 588 sync;
 589 EMIT_    (spe_dsync, 0x003);
 590 EMIT_R   (spe_mfspr, 0x00c);
 591 EMIT_R   (spe_mtspr, 0x10c);
 592 #endif
 593
 594
 595 /**
 596  ** Helper / "macro" instructions.
 597  ** Use somewhat verbose names as a reminder that these aren't native
 598  ** SPE instructions.
 599  **/
 600
 601
 602 void
 603 spe_load_float(struct spe_function *p, unsigned rT, float x)
 604 {
 605    if (x == 0.0f) {
 606       spe_il(p, rT, 0x0);
 607    }
 608    else if (x == 0.5f) {
 609       spe_ilhu(p, rT, 0x3f00);
 610    }
 611    else if (x == 1.0f) {
 612       spe_ilhu(p, rT, 0x3f80);
 613    }
 614    else if (x == -1.0f) {
 615       spe_ilhu(p, rT, 0xbf80);
 616    }
 617    else {
 618       union {
 619          float f;
 620          unsigned u;
 621       } bits;
 622       bits.f = x;
 623       spe_ilhu(p, rT, bits.u >> 16);
 624       spe_iohl(p, rT, bits.u & 0xffff);
 625    }
 626 }
 627
 628
 629 void
 630 spe_load_int(struct spe_function *p, unsigned rT, int i)
 631 {
 632    if (-32768 <= i && i <= 32767) {
 633       spe_il(p, rT, i);
 634    }
 635    else {
 636       spe_ilhu(p, rT, i >> 16);
 637       if (i & 0xffff)
 638          spe_iohl(p, rT, i & 0xffff);
 639    }
 640 }
 641
 642 void spe_load_uint(struct spe_function *p, unsigned rT, unsigned int ui)
 643 {
 644    /* If the whole value is in the lower 18 bits, use ila, which
 645     * doesn't sign-extend.  Otherwise, if the two halfwords of
 646     * the constant are identical, use ilh.  Otherwise, if every byte of
 647     * the desired value is 0x00 or 0xff, we can use Form Select Mask for
 648     * Bytes Immediate (fsmbi) to load the value in a single instruction.
 649     * Otherwise, in the general case, we have to use ilhu followed by iohl.
 650     */
 651    if ((ui & 0xfffc0000) == ui) {
 652       spe_ila(p, rT, ui);
 653    }
 654    else if ((ui >> 16) == (ui & 0xffff)) {
 655       spe_ilh(p, rT, ui & 0xffff);
 656    }
 657    else if (
 658       ((ui & 0x000000ff) == 0 || (ui & 0x000000ff) == 0x000000ff) &&
 659       ((ui & 0x0000ff00) == 0 || (ui & 0x0000ff00) == 0x0000ff00) &&
 660       ((ui & 0x00ff0000) == 0 || (ui & 0x00ff0000) == 0x00ff0000) &&
 661       ((ui & 0xff000000) == 0 || (ui & 0xff000000) == 0xff000000)
 662    ) {
 663       unsigned int mask = 0;
 664       /* fsmbi duplicates each bit in the given mask eight times,
 665        * using a 16-bit value to initialize a 16-byte quadword.
 666        * Each 4-bit nybble of the mask corresponds to a full word
 667        * of the result; look at the value and figure out the mask
 668        * (replicated for each word in the quadword), and then
 669        * form the "select mask" to get the value.
 670        */
 671       if ((ui & 0x000000ff) == 0x000000ff) mask |= 0x1111;
 672       if ((ui & 0x0000ff00) == 0x0000ff00) mask |= 0x2222;
 673       if ((ui & 0x00ff0000) == 0x00ff0000) mask |= 0x4444;
 674       if ((ui & 0xff000000) == 0xff000000) mask |= 0x8888;
 675       spe_fsmbi(p, rT, mask);
 676    }
 677    else {
 678       /* The general case: this usually uses two instructions, but
 679        * may use only one if the low-order 16 bits of each word are 0.
 680        */
 681       spe_ilhu(p, rT, ui >> 16);
 682       if (ui & 0xffff)
 683          spe_iohl(p, rT, ui & 0xffff);
 684    }
 685 }
 686
 687 /* This function is constructed identically to spe_sor_uint() below.
 688  * Changes to one should be made in the other.
 689  */
 690 void spe_and_uint(struct spe_function *p, unsigned rT, unsigned rA, unsigned int ui)
 691 {
 692    /* If we can, emit a single instruction, either And Byte Immediate
 693     * (which uses the same constant across each byte), And Halfword Immediate
 694     * (which sign-extends a 10-bit immediate to 16 bits and uses that
 695     * across each halfword), or And Word Immediate (which sign-extends
 696     * a 10-bit immediate to 32 bits).
 697     *
 698     * Otherwise, we'll need to use a temporary register.
 699     */
 700    register unsigned int tmp;
 701
 702    /* If the upper 23 bits are all 0s or all 1s, sign extension
 703     * will work and we can use And Word Immediate
 704     */
 705    tmp = ui & 0xfffffe00;
 706    if (tmp == 0xfffffe00 || tmp  == 0) {
 707       spe_andi(p, rT, rA, ui & 0x000003ff);
 708       return;
 709    }
 710
 711    /* If the ui field is symmetric along halfword boundaries and
 712     * the upper 7 bits of each halfword are all 0s or 1s, we
 713     * can use And Halfword Immediate
 714     */
 715    tmp = ui & 0xfe00fe00;
 716    if ((tmp == 0xfe00fe00 || tmp == 0) && ((ui >> 16) == (ui & 0x0000ffff))) {
 717       spe_andhi(p, rT, rA, ui & 0x000003ff);
 718       return;
 719    }
 720
 721    /* If the ui field is symmetric in each byte, then we can use
 722     * the And Byte Immediate instruction.
 723     */
 724    tmp = ui & 0x000000ff;
 725    if ((ui >> 24) == tmp && ((ui >> 16) & 0xff) == tmp && ((ui >> 8) & 0xff) == tmp) {
 726       spe_andbi(p, rT, rA, tmp);
 727       return;
 728    }
 729
 730    /* Otherwise, we'll have to use a temporary register. */
 731    unsigned int tmp_reg = spe_allocate_available_register(p);
 732    spe_load_uint(p, tmp_reg, ui);
 733    spe_and(p, rT, rA, tmp_reg);
 734    spe_release_register(p, tmp_reg);
 735 }
 736
 737 /* This function is constructed identically to spe_and_uint() above.
 738  * Changes to one should be made in the other.
 739  */
 740 void spe_xor_uint(struct spe_function *p, unsigned rT, unsigned rA, unsigned int ui)
 741 {
 742    /* If we can, emit a single instruction, either Exclusive Or Byte
 743     * Immediate (which uses the same constant across each byte), Exclusive
 744     * Or Halfword Immediate (which sign-extends a 10-bit immediate to
 745     * 16 bits and uses that across each halfword), or Exclusive Or Word
 746     * Immediate (which sign-extends a 10-bit immediate to 32 bits).
 747     *
 748     * Otherwise, we'll need to use a temporary register.
 749     */
 750    register unsigned int tmp;
 751
 752    /* If the upper 23 bits are all 0s or all 1s, sign extension
 753     * will work and we can use Exclusive Or Word Immediate
 754     */
 755    tmp = ui & 0xfffffe00;
 756    if (tmp == 0xfffffe00 || tmp  == 0) {
 757       spe_xori(p, rT, rA, ui & 0x000003ff);
 758       return;
 759    }
 760
 761    /* If the ui field is symmetric along halfword boundaries and
 762     * the upper 7 bits of each halfword are all 0s or 1s, we
 763     * can use Exclusive Or Halfword Immediate
 764     */
 765    tmp = ui & 0xfe00fe00;
 766    if ((tmp == 0xfe00fe00 || tmp == 0) && ((ui >> 16) == (ui & 0x0000ffff))) {
 767       spe_xorhi(p, rT, rA, ui & 0x000003ff);
 768       return;
 769    }
 770
 771    /* If the ui field is symmetric in each byte, then we can use
 772     * the Exclusive Or Byte Immediate instruction.
 773     */
 774    tmp = ui & 0x000000ff;
 775    if ((ui >> 24) == tmp && ((ui >> 16) & 0xff) == tmp && ((ui >> 8) & 0xff) == tmp) {
 776       spe_xorbi(p, rT, rA, tmp);
 777       return;
 778    }
 779
 780    /* Otherwise, we'll have to use a temporary register. */
 781    unsigned int tmp_reg = spe_allocate_available_register(p);
 782    spe_load_uint(p, tmp_reg, ui);
 783    spe_xor(p, rT, rA, tmp_reg);
 784    spe_release_register(p, tmp_reg);
 785 }
 786
 787 void
 788 spe_compare_equal_uint(struct spe_function *p, unsigned rT, unsigned rA, unsigned int ui)
 789 {
 790    /* If the comparison value is 9 bits or less, it fits inside a
 791     * Compare Equal Word Immediate instruction.
 792     */
 793    if ((ui & 0x000001ff) == ui) {
 794       spe_ceqi(p, rT, rA, ui);
 795    }
 796    /* Otherwise, we're going to have to load a word first. */
 797    else {
 798       unsigned int tmp_reg = spe_allocate_available_register(p);
 799       spe_load_uint(p, tmp_reg, ui);
 800       spe_ceq(p, rT, rA, tmp_reg);
 801       spe_release_register(p, tmp_reg);
 802    }
 803 }
 804
 805 void
 806 spe_compare_greater_uint(struct spe_function *p, unsigned rT, unsigned rA, unsigned int ui)
 807 {
 808    /* If the comparison value is 10 bits or less, it fits inside a
 809     * Compare Logical Greater Than Word Immediate instruction.
 810     */
 811    if ((ui & 0x000003ff) == ui) {
 812       spe_clgti(p, rT, rA, ui);
 813    }
 814    /* Otherwise, we're going to have to load a word first. */
 815    else {
 816       unsigned int tmp_reg = spe_allocate_available_register(p);
 817       spe_load_uint(p, tmp_reg, ui);
 818       spe_clgt(p, rT, rA, tmp_reg);
 819       spe_release_register(p, tmp_reg);
 820    }
 821 }
 822
 823 void
 824 spe_splat(struct spe_function *p, unsigned rT, unsigned rA)
 825 {
 826    /* Duplicate bytes 0, 1, 2, and 3 across the whole register */
 827    spe_ila(p, rT, 0x00010203);
 828    spe_shufb(p, rT, rA, rA, rT);
 829 }
 830
 831
 832 void
 833 spe_complement(struct spe_function *p, unsigned rT, unsigned rA)
 834 {
 835    spe_nor(p, rT, rA, rA);
 836 }
 837
 838
 839 void
 840 spe_move(struct spe_function *p, unsigned rT, unsigned rA)
 841 {
 842    /* Use different instructions depending on the instruction address
 843     * to take advantage of the dual pipelines.
 844     */
 845    if (p->num_inst & 1)
 846       spe_shlqbyi(p, rT, rA, 0);  /* odd pipe */
 847    else
 848       spe_ori(p, rT, rA, 0);  /* even pipe */
 849 }
 850
 851
 852 void
 853 spe_zero(struct spe_function *p, unsigned rT)
 854 {
 855    spe_xor(p, rT, rT, rT);
 856 }
 857
 858
 859 void
 860 spe_splat_word(struct spe_function *p, unsigned rT, unsigned rA, int word)
 861 {
 862    assert(word >= 0);
 863    assert(word <= 3);
 864
 865    if (word == 0) {
 866       int tmp1 = rT;
 867       spe_ila(p, tmp1, 66051);
 868       spe_shufb(p, rT, rA, rA, tmp1);
 869    }
 870    else {
 871       /* XXX review this, we may not need the rotqbyi instruction */
 872       int tmp1 = rT;
 873       int tmp2 = spe_allocate_available_register(p);
 874
 875       spe_ila(p, tmp1, 66051);
 876       spe_rotqbyi(p, tmp2, rA, 4 * word);
 877       spe_shufb(p, rT, tmp2, tmp2, tmp1);
 878
 879       spe_release_register(p, tmp2);
 880    }
 881 }
 882
 883 /**
 884  * For each 32-bit float element of rA and rB, choose the smaller of the
 885  * two, compositing them into the rT register.
 886  *
 887  * The Float Compare Greater Than (fcgt) instruction will put 1s into
 888  * compare_reg where rA > rB, and 0s where rA <= rB.
 889  *
 890  * Then the Select Bits (selb) instruction will take bits from rA where
 891  * compare_reg is 0, and from rB where compare_reg is 1; i.e., from rA
 892  * where rA <= rB and from rB where rB > rA, which is exactly the
 893  * "min" operation.
 894  *
 895  * The compare_reg could in many cases be the same as rT, unless
 896  * rT == rA || rt == rB.  But since this is common in constructions
 897  * like "x = min(x, a)", we always allocate a new register to be safe.
 898  */
 899 void
 900 spe_float_min(struct spe_function *p, unsigned rT, unsigned rA, unsigned rB)
 901 {
 902    unsigned int compare_reg = spe_allocate_available_register(p);
 903    spe_fcgt(p, compare_reg, rA, rB);
 904    spe_selb(p, rT, rA, rB, compare_reg);
 905    spe_release_register(p, compare_reg);
 906 }
 907
 908 /**
 909  * For each 32-bit float element of rA and rB, choose the greater of the
 910  * two, compositing them into the rT register.
 911  *
 912  * The logic is similar to that of spe_float_min() above; the only
 913  * difference is that the registers on spe_selb() have been reversed,
 914  * so that the larger of the two is selected instead of the smaller.
 915  */
 916 void
 917 spe_float_max(struct spe_function *p, unsigned rT, unsigned rA, unsigned rB)
 918 {
 919    unsigned int compare_reg = spe_allocate_available_register(p);
 920    spe_fcgt(p, compare_reg, rA, rB);
 921    spe_selb(p, rT, rB, rA, compare_reg);
 922    spe_release_register(p, compare_reg);
 923 }
 924
 925 #endif /* GALLIUM_CELL */