cc35f0ba5b0a68347defca0b9061b9f1275a32af
2 * (C) Copyright IBM Corporation 2008
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
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10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * Real-time assembly generation interface for Cell B.E. SPEs.
29 * \author Ian Romanick <idr@us.ibm.com>
35 #include "pipe/p_compiler.h"
36 #include "util/u_memory.h"
37 #include "rtasm_ppc_spe.h"
42 * SPE instruction types
44 * There are 6 primary instruction encodings used on the Cell's SPEs. Each of
45 * the following unions encodes one type.
48 * If, at some point, we start generating SPE code from a little-endian host
49 * these unions will not work.
53 * Encode one output register with two input registers
67 * Encode one output register with three input registers
82 * Encode one output register with one input reg. and a 7-bit signed immed
96 * Encode one output register with one input reg. and an 8-bit signed immed
110 * Encode one output register with one input reg. and a 10-bit signed immed
112 union spe_inst_RI10
{
124 * Encode one output register with a 16-bit signed immediate
126 union spe_inst_RI16
{
137 * Encode one output register with a 18-bit signed immediate
139 union spe_inst_RI18
{
151 indent(const struct spe_function
*p
)
154 for (i
= 0; i
< p
->indent
; i
++) {
161 rem_prefix(const char *longname
)
177 /* cycle through four buffers to handle multiple calls per printf */
178 static char buf
[4][10];
181 sprintf(buf
[b
], "$%d", reg
);
188 static void emit_RR(struct spe_function
*p
, unsigned op
, unsigned rT
,
189 unsigned rA
, unsigned rB
, const char *name
)
191 union spe_inst_RR inst
;
196 p
->store
[p
->num_inst
++] = inst
.bits
;
197 assert(p
->num_inst
<= p
->max_inst
);
200 printf("%s\t%s, %s, %s\n",
201 rem_prefix(name
), reg_name(rT
), reg_name(rA
), reg_name(rB
));
206 static void emit_RRR(struct spe_function
*p
, unsigned op
, unsigned rT
,
207 unsigned rA
, unsigned rB
, unsigned rC
, const char *name
)
209 union spe_inst_RRR inst
;
215 p
->store
[p
->num_inst
++] = inst
.bits
;
216 assert(p
->num_inst
<= p
->max_inst
);
219 printf("%s\t%s, %s, %s, %s\n", rem_prefix(name
), reg_name(rT
),
220 reg_name(rA
), reg_name(rB
), reg_name(rC
));
225 static void emit_RI7(struct spe_function
*p
, unsigned op
, unsigned rT
,
226 unsigned rA
, int imm
, const char *name
)
228 union spe_inst_RI7 inst
;
233 p
->store
[p
->num_inst
++] = inst
.bits
;
234 assert(p
->num_inst
<= p
->max_inst
);
237 printf("%s\t%s, %s, 0x%x\n",
238 rem_prefix(name
), reg_name(rT
), reg_name(rA
), imm
);
244 static void emit_RI8(struct spe_function
*p
, unsigned op
, unsigned rT
,
245 unsigned rA
, int imm
, const char *name
)
247 union spe_inst_RI8 inst
;
252 p
->store
[p
->num_inst
++] = inst
.bits
;
253 assert(p
->num_inst
<= p
->max_inst
);
256 printf("%s\t%s, %s, 0x%x\n",
257 rem_prefix(name
), reg_name(rT
), reg_name(rA
), imm
);
263 static void emit_RI10(struct spe_function
*p
, unsigned op
, unsigned rT
,
264 unsigned rA
, int imm
, const char *name
)
266 union spe_inst_RI10 inst
;
271 p
->store
[p
->num_inst
++] = inst
.bits
;
272 assert(p
->num_inst
<= p
->max_inst
);
275 printf("%s\t%s, %s, 0x%x\n",
276 rem_prefix(name
), reg_name(rT
), reg_name(rA
), imm
);
281 static void emit_RI16(struct spe_function
*p
, unsigned op
, unsigned rT
,
282 int imm
, const char *name
)
284 union spe_inst_RI16 inst
;
288 p
->store
[p
->num_inst
++] = inst
.bits
;
289 assert(p
->num_inst
<= p
->max_inst
);
292 printf("%s\t%s, 0x%x\n", rem_prefix(name
), reg_name(rT
), imm
);
297 static void emit_RI18(struct spe_function
*p
, unsigned op
, unsigned rT
,
298 int imm
, const char *name
)
300 union spe_inst_RI18 inst
;
304 p
->store
[p
->num_inst
++] = inst
.bits
;
305 assert(p
->num_inst
<= p
->max_inst
);
308 printf("%s\t%s, 0x%x\n", rem_prefix(name
), reg_name(rT
), imm
);
315 #define EMIT_(_name, _op) \
316 void _name (struct spe_function *p, unsigned rT) \
318 emit_RR(p, _op, rT, 0, 0, __FUNCTION__); \
321 #define EMIT_R(_name, _op) \
322 void _name (struct spe_function *p, unsigned rT, unsigned rA) \
324 emit_RR(p, _op, rT, rA, 0, __FUNCTION__); \
327 #define EMIT_RR(_name, _op) \
328 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB) \
330 emit_RR(p, _op, rT, rA, rB, __FUNCTION__); \
333 #define EMIT_RRR(_name, _op) \
334 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB, unsigned rC) \
336 emit_RRR(p, _op, rT, rA, rB, rC, __FUNCTION__); \
339 #define EMIT_RI7(_name, _op) \
340 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
342 emit_RI7(p, _op, rT, rA, imm, __FUNCTION__); \
345 #define EMIT_RI8(_name, _op, bias) \
346 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
348 emit_RI8(p, _op, rT, rA, bias - imm, __FUNCTION__); \
351 #define EMIT_RI10(_name, _op) \
352 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
354 emit_RI10(p, _op, rT, rA, imm, __FUNCTION__); \
357 #define EMIT_RI16(_name, _op) \
358 void _name (struct spe_function *p, unsigned rT, int imm) \
360 emit_RI16(p, _op, rT, imm, __FUNCTION__); \
363 #define EMIT_RI18(_name, _op) \
364 void _name (struct spe_function *p, unsigned rT, int imm) \
366 emit_RI18(p, _op, rT, imm, __FUNCTION__); \
369 #define EMIT_I16(_name, _op) \
370 void _name (struct spe_function *p, int imm) \
372 emit_RI16(p, _op, 0, imm, __FUNCTION__); \
375 #include "rtasm_ppc_spe.h"
380 * Initialize an spe_function.
381 * \param code_size size of instruction buffer to allocate, in bytes.
383 void spe_init_func(struct spe_function
*p
, unsigned code_size
)
387 p
->store
= align_malloc(code_size
, 16);
389 p
->max_inst
= code_size
/ SPE_INST_SIZE
;
392 memset(p
->regs
, 0, SPE_NUM_REGS
* sizeof(p
->regs
[0]));
394 /* Conservatively treat R0 - R2 and R80 - R127 as non-volatile.
396 p
->regs
[0] = p
->regs
[1] = p
->regs
[2] = 1;
397 for (i
= 80; i
<= 127; i
++) {
406 void spe_release_func(struct spe_function
*p
)
408 assert(p
->num_inst
<= p
->max_inst
);
409 if (p
->store
!= NULL
) {
410 align_free(p
->store
);
416 /** Return current code size in bytes. */
417 unsigned spe_code_size(const struct spe_function
*p
)
419 return p
->num_inst
* SPE_INST_SIZE
;
424 * Allocate a SPE register.
425 * \return register index or -1 if none left.
427 int spe_allocate_available_register(struct spe_function
*p
)
430 for (i
= 0; i
< SPE_NUM_REGS
; i
++) {
431 if (p
->regs
[i
] == 0) {
442 * Mark the given SPE register as "allocated".
444 int spe_allocate_register(struct spe_function
*p
, int reg
)
446 assert(reg
< SPE_NUM_REGS
);
447 assert(p
->regs
[reg
] == 0);
454 * Mark the given SPE register as "unallocated". Note that this should
455 * only be used on registers allocated in the current register set; an
456 * assertion will fail if an attempt is made to deallocate a register
457 * allocated in an earlier register set.
459 void spe_release_register(struct spe_function
*p
, int reg
)
461 assert(reg
< SPE_NUM_REGS
);
462 assert(p
->regs
[reg
] == 1);
468 * Start a new set of registers. This can be called if
469 * it will be difficult later to determine exactly what
470 * registers were actually allocated during a code generation
471 * sequence, and you really just want to deallocate all of them.
473 void spe_allocate_register_set(struct spe_function
*p
)
477 /* Keep track of the set count. If it ever wraps around to 0,
481 assert(p
->set_count
> 0);
483 /* Increment the allocation count of all registers currently
484 * allocated. Then any registers that are allocated in this set
485 * will be the only ones with a count of 1; they'll all be released
486 * when the register set is released.
488 for (i
= 0; i
< SPE_NUM_REGS
; i
++) {
494 void spe_release_register_set(struct spe_function
*p
)
498 /* If the set count drops below zero, we're in trouble. */
499 assert(p
->set_count
> 0);
502 /* Drop the allocation level of all registers. Any allocated
503 * during this register set will drop to 0 and then become
506 for (i
= 0; i
< SPE_NUM_REGS
; i
++) {
514 spe_get_registers_used(const struct spe_function
*p
, ubyte used
[])
517 /* only count registers in the range available to callers */
518 for (i
= 2; i
< 80; i
++) {
528 spe_print_code(struct spe_function
*p
, boolean enable
)
535 spe_indent(struct spe_function
*p
, int spaces
)
542 spe_comment(struct spe_function
*p
, int rel_indent
, const char *s
)
545 p
->indent
+= rel_indent
;
547 p
->indent
-= rel_indent
;
555 * NOTE: imm is in bytes and the least significant 4 bits must be zero!
557 void spe_lqd(struct spe_function
*p
, unsigned rT
, unsigned rA
, int offset
)
559 const boolean pSave
= p
->print
;
562 assert(offset
% 4 == 0);
563 emit_RI10(p
, 0x034, rT
, rA
, offset
>> 4, "spe_lqd");
568 printf("lqd\t%s, %d(%s)\n", reg_name(rT
), offset
, reg_name(rA
));
575 * NOTE: imm is in bytes and the least significant 4 bits must be zero!
577 void spe_stqd(struct spe_function
*p
, unsigned rT
, unsigned rA
, int offset
)
579 const boolean pSave
= p
->print
;
582 assert(offset
% 4 == 0);
583 emit_RI10(p
, 0x024, rT
, rA
, offset
>> 4, "spe_stqd");
588 printf("stqd\t%s, %d(%s)\n", reg_name(rT
), offset
, reg_name(rA
));
594 * For branch instructions:
595 * \param d if 1, disable interupts if branch is taken
596 * \param e if 1, enable interupts if branch is taken
597 * If d and e are both zero, don't change interupt status (right?)
600 /** Branch Indirect to address in rA */
601 void spe_bi(struct spe_function
*p
, unsigned rA
, int d
, int e
)
603 emit_RI7(p
, 0x1a8, 0, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
606 /** Interupt Return */
607 void spe_iret(struct spe_function
*p
, unsigned rA
, int d
, int e
)
609 emit_RI7(p
, 0x1aa, 0, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
612 /** Branch indirect and set link on external data */
613 void spe_bisled(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
,
616 emit_RI7(p
, 0x1ab, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
619 /** Branch indirect and set link. Save PC in rT, jump to rA. */
620 void spe_bisl(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
,
623 emit_RI7(p
, 0x1a9, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
626 /** Branch indirect if zero word. If rT.word[0]==0, jump to rA. */
627 void spe_biz(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
, int e
)
629 emit_RI7(p
, 0x128, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
632 /** Branch indirect if non-zero word. If rT.word[0]!=0, jump to rA. */
633 void spe_binz(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
, int e
)
635 emit_RI7(p
, 0x129, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
638 /** Branch indirect if zero halfword. If rT.halfword[1]==0, jump to rA. */
639 void spe_bihz(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
, int e
)
641 emit_RI7(p
, 0x12a, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
644 /** Branch indirect if non-zero halfword. If rT.halfword[1]!=0, jump to rA. */
645 void spe_bihnz(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
, int e
)
647 emit_RI7(p
, 0x12b, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
651 /* Hint-for-branch instructions
660 /* Control instructions
664 EMIT_RR (spe_stopd
, 0x140);
665 EMIT_ (spe_lnop
, 0x001);
666 EMIT_ (spe_nop
, 0x201);
668 EMIT_ (spe_dsync
, 0x003);
669 EMIT_R (spe_mfspr
, 0x00c);
670 EMIT_R (spe_mtspr
, 0x10c);
675 ** Helper / "macro" instructions.
676 ** Use somewhat verbose names as a reminder that these aren't native
682 spe_load_float(struct spe_function
*p
, unsigned rT
, float x
)
687 else if (x
== 0.5f
) {
688 spe_ilhu(p
, rT
, 0x3f00);
690 else if (x
== 1.0f
) {
691 spe_ilhu(p
, rT
, 0x3f80);
693 else if (x
== -1.0f
) {
694 spe_ilhu(p
, rT
, 0xbf80);
702 spe_ilhu(p
, rT
, bits
.u
>> 16);
703 spe_iohl(p
, rT
, bits
.u
& 0xffff);
709 spe_load_int(struct spe_function
*p
, unsigned rT
, int i
)
711 if (-32768 <= i
&& i
<= 32767) {
715 spe_ilhu(p
, rT
, i
>> 16);
717 spe_iohl(p
, rT
, i
& 0xffff);
721 void spe_load_uint(struct spe_function
*p
, unsigned rT
, unsigned int ui
)
723 /* If the whole value is in the lower 18 bits, use ila, which
724 * doesn't sign-extend. Otherwise, if the two halfwords of
725 * the constant are identical, use ilh. Otherwise, if every byte of
726 * the desired value is 0x00 or 0xff, we can use Form Select Mask for
727 * Bytes Immediate (fsmbi) to load the value in a single instruction.
728 * Otherwise, in the general case, we have to use ilhu followed by iohl.
730 if ((ui
& 0x3ffff) == ui
) {
733 else if ((ui
>> 16) == (ui
& 0xffff)) {
734 spe_ilh(p
, rT
, ui
& 0xffff);
737 ((ui
& 0x000000ff) == 0 || (ui
& 0x000000ff) == 0x000000ff) &&
738 ((ui
& 0x0000ff00) == 0 || (ui
& 0x0000ff00) == 0x0000ff00) &&
739 ((ui
& 0x00ff0000) == 0 || (ui
& 0x00ff0000) == 0x00ff0000) &&
740 ((ui
& 0xff000000) == 0 || (ui
& 0xff000000) == 0xff000000)
742 unsigned int mask
= 0;
743 /* fsmbi duplicates each bit in the given mask eight times,
744 * using a 16-bit value to initialize a 16-byte quadword.
745 * Each 4-bit nybble of the mask corresponds to a full word
746 * of the result; look at the value and figure out the mask
747 * (replicated for each word in the quadword), and then
748 * form the "select mask" to get the value.
750 if ((ui
& 0x000000ff) == 0x000000ff) mask
|= 0x1111;
751 if ((ui
& 0x0000ff00) == 0x0000ff00) mask
|= 0x2222;
752 if ((ui
& 0x00ff0000) == 0x00ff0000) mask
|= 0x4444;
753 if ((ui
& 0xff000000) == 0xff000000) mask
|= 0x8888;
754 spe_fsmbi(p
, rT
, mask
);
757 /* The general case: this usually uses two instructions, but
758 * may use only one if the low-order 16 bits of each word are 0.
760 spe_ilhu(p
, rT
, ui
>> 16);
762 spe_iohl(p
, rT
, ui
& 0xffff);
767 * This function is constructed identically to spe_sor_uint() below.
768 * Changes to one should be made in the other.
771 spe_and_uint(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned int ui
)
773 /* If we can, emit a single instruction, either And Byte Immediate
774 * (which uses the same constant across each byte), And Halfword Immediate
775 * (which sign-extends a 10-bit immediate to 16 bits and uses that
776 * across each halfword), or And Word Immediate (which sign-extends
777 * a 10-bit immediate to 32 bits).
779 * Otherwise, we'll need to use a temporary register.
783 /* If the upper 23 bits are all 0s or all 1s, sign extension
784 * will work and we can use And Word Immediate
786 tmp
= ui
& 0xfffffe00;
787 if (tmp
== 0xfffffe00 || tmp
== 0) {
788 spe_andi(p
, rT
, rA
, ui
& 0x000003ff);
792 /* If the ui field is symmetric along halfword boundaries and
793 * the upper 7 bits of each halfword are all 0s or 1s, we
794 * can use And Halfword Immediate
796 tmp
= ui
& 0xfe00fe00;
797 if ((tmp
== 0xfe00fe00 || tmp
== 0) && ((ui
>> 16) == (ui
& 0x0000ffff))) {
798 spe_andhi(p
, rT
, rA
, ui
& 0x000003ff);
802 /* If the ui field is symmetric in each byte, then we can use
803 * the And Byte Immediate instruction.
805 tmp
= ui
& 0x000000ff;
806 if ((ui
>> 24) == tmp
&& ((ui
>> 16) & 0xff) == tmp
&& ((ui
>> 8) & 0xff) == tmp
) {
807 spe_andbi(p
, rT
, rA
, tmp
);
811 /* Otherwise, we'll have to use a temporary register. */
812 unsigned int tmp_reg
= spe_allocate_available_register(p
);
813 spe_load_uint(p
, tmp_reg
, ui
);
814 spe_and(p
, rT
, rA
, tmp_reg
);
815 spe_release_register(p
, tmp_reg
);
820 * This function is constructed identically to spe_and_uint() above.
821 * Changes to one should be made in the other.
824 spe_xor_uint(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned int ui
)
826 /* If we can, emit a single instruction, either Exclusive Or Byte
827 * Immediate (which uses the same constant across each byte), Exclusive
828 * Or Halfword Immediate (which sign-extends a 10-bit immediate to
829 * 16 bits and uses that across each halfword), or Exclusive Or Word
830 * Immediate (which sign-extends a 10-bit immediate to 32 bits).
832 * Otherwise, we'll need to use a temporary register.
836 /* If the upper 23 bits are all 0s or all 1s, sign extension
837 * will work and we can use Exclusive Or Word Immediate
839 tmp
= ui
& 0xfffffe00;
840 if (tmp
== 0xfffffe00 || tmp
== 0) {
841 spe_xori(p
, rT
, rA
, ui
& 0x000003ff);
845 /* If the ui field is symmetric along halfword boundaries and
846 * the upper 7 bits of each halfword are all 0s or 1s, we
847 * can use Exclusive Or Halfword Immediate
849 tmp
= ui
& 0xfe00fe00;
850 if ((tmp
== 0xfe00fe00 || tmp
== 0) && ((ui
>> 16) == (ui
& 0x0000ffff))) {
851 spe_xorhi(p
, rT
, rA
, ui
& 0x000003ff);
855 /* If the ui field is symmetric in each byte, then we can use
856 * the Exclusive Or Byte Immediate instruction.
858 tmp
= ui
& 0x000000ff;
859 if ((ui
>> 24) == tmp
&& ((ui
>> 16) & 0xff) == tmp
&& ((ui
>> 8) & 0xff) == tmp
) {
860 spe_xorbi(p
, rT
, rA
, tmp
);
864 /* Otherwise, we'll have to use a temporary register. */
865 unsigned int tmp_reg
= spe_allocate_available_register(p
);
866 spe_load_uint(p
, tmp_reg
, ui
);
867 spe_xor(p
, rT
, rA
, tmp_reg
);
868 spe_release_register(p
, tmp_reg
);
872 spe_compare_equal_uint(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned int ui
)
874 /* If the comparison value is 9 bits or less, it fits inside a
875 * Compare Equal Word Immediate instruction.
877 if ((ui
& 0x000001ff) == ui
) {
878 spe_ceqi(p
, rT
, rA
, ui
);
880 /* Otherwise, we're going to have to load a word first. */
882 unsigned int tmp_reg
= spe_allocate_available_register(p
);
883 spe_load_uint(p
, tmp_reg
, ui
);
884 spe_ceq(p
, rT
, rA
, tmp_reg
);
885 spe_release_register(p
, tmp_reg
);
890 spe_compare_greater_uint(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned int ui
)
892 /* If the comparison value is 10 bits or less, it fits inside a
893 * Compare Logical Greater Than Word Immediate instruction.
895 if ((ui
& 0x000003ff) == ui
) {
896 spe_clgti(p
, rT
, rA
, ui
);
898 /* Otherwise, we're going to have to load a word first. */
900 unsigned int tmp_reg
= spe_allocate_available_register(p
);
901 spe_load_uint(p
, tmp_reg
, ui
);
902 spe_clgt(p
, rT
, rA
, tmp_reg
);
903 spe_release_register(p
, tmp_reg
);
908 spe_splat(struct spe_function
*p
, unsigned rT
, unsigned rA
)
910 /* Duplicate bytes 0, 1, 2, and 3 across the whole register */
911 spe_ila(p
, rT
, 0x00010203);
912 spe_shufb(p
, rT
, rA
, rA
, rT
);
917 spe_complement(struct spe_function
*p
, unsigned rT
, unsigned rA
)
919 spe_nor(p
, rT
, rA
, rA
);
924 spe_move(struct spe_function
*p
, unsigned rT
, unsigned rA
)
926 /* Use different instructions depending on the instruction address
927 * to take advantage of the dual pipelines.
930 spe_shlqbyi(p
, rT
, rA
, 0); /* odd pipe */
932 spe_ori(p
, rT
, rA
, 0); /* even pipe */
937 spe_zero(struct spe_function
*p
, unsigned rT
)
939 spe_xor(p
, rT
, rT
, rT
);
944 spe_splat_word(struct spe_function
*p
, unsigned rT
, unsigned rA
, int word
)
951 spe_ila(p
, tmp1
, 66051);
952 spe_shufb(p
, rT
, rA
, rA
, tmp1
);
955 /* XXX review this, we may not need the rotqbyi instruction */
957 int tmp2
= spe_allocate_available_register(p
);
959 spe_ila(p
, tmp1
, 66051);
960 spe_rotqbyi(p
, tmp2
, rA
, 4 * word
);
961 spe_shufb(p
, rT
, tmp2
, tmp2
, tmp1
);
963 spe_release_register(p
, tmp2
);
968 * For each 32-bit float element of rA and rB, choose the smaller of the
969 * two, compositing them into the rT register.
971 * The Float Compare Greater Than (fcgt) instruction will put 1s into
972 * compare_reg where rA > rB, and 0s where rA <= rB.
974 * Then the Select Bits (selb) instruction will take bits from rA where
975 * compare_reg is 0, and from rB where compare_reg is 1; i.e., from rA
976 * where rA <= rB and from rB where rB > rA, which is exactly the
979 * The compare_reg could in many cases be the same as rT, unless
980 * rT == rA || rt == rB. But since this is common in constructions
981 * like "x = min(x, a)", we always allocate a new register to be safe.
984 spe_float_min(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned rB
)
986 unsigned int compare_reg
= spe_allocate_available_register(p
);
987 spe_fcgt(p
, compare_reg
, rA
, rB
);
988 spe_selb(p
, rT
, rA
, rB
, compare_reg
);
989 spe_release_register(p
, compare_reg
);
993 * For each 32-bit float element of rA and rB, choose the greater of the
994 * two, compositing them into the rT register.
996 * The logic is similar to that of spe_float_min() above; the only
997 * difference is that the registers on spe_selb() have been reversed,
998 * so that the larger of the two is selected instead of the smaller.
1001 spe_float_max(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned rB
)
1003 unsigned int compare_reg
= spe_allocate_available_register(p
);
1004 spe_fcgt(p
, compare_reg
, rA
, rB
);
1005 spe_selb(p
, rT
, rB
, rA
, compare_reg
);
1006 spe_release_register(p
, compare_reg
);
1009 #endif /* GALLIUM_CELL */