2 * (C) Copyright IBM Corporation 2008
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
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10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * Real-time assembly generation interface for Cell B.E. SPEs.
29 * \author Ian Romanick <idr@us.ibm.com>
35 #include "pipe/p_compiler.h"
36 #include "util/u_memory.h"
37 #include "rtasm_ppc_spe.h"
42 * SPE instruction types
44 * There are 6 primary instruction encodings used on the Cell's SPEs. Each of
45 * the following unions encodes one type.
48 * If, at some point, we start generating SPE code from a little-endian host
49 * these unions will not work.
53 * Encode one output register with two input registers
67 * Encode one output register with three input registers
82 * Encode one output register with one input reg. and a 7-bit signed immed
96 * Encode one output register with one input reg. and an 8-bit signed immed
110 * Encode one output register with one input reg. and a 10-bit signed immed
112 union spe_inst_RI10
{
124 * Encode one output register with a 16-bit signed immediate
126 union spe_inst_RI16
{
137 * Encode one output register with a 18-bit signed immediate
139 union spe_inst_RI18
{
151 indent(const struct spe_function
*p
)
154 for (i
= 0; i
< p
->indent
; i
++) {
161 rem_prefix(const char *longname
)
167 static void emit_RR(struct spe_function
*p
, unsigned op
, unsigned rT
,
168 unsigned rA
, unsigned rB
, const char *name
)
170 union spe_inst_RR inst
;
175 p
->store
[p
->num_inst
++] = inst
.bits
;
176 assert(p
->num_inst
<= p
->max_inst
);
179 printf("%s\t$%d, $%d, $%d\n", rem_prefix(name
), rT
, rA
, rB
);
184 static void emit_RRR(struct spe_function
*p
, unsigned op
, unsigned rT
,
185 unsigned rA
, unsigned rB
, unsigned rC
, const char *name
)
187 union spe_inst_RRR inst
;
193 p
->store
[p
->num_inst
++] = inst
.bits
;
194 assert(p
->num_inst
<= p
->max_inst
);
197 printf("%s\t$%d, $%d, $%d, $%d\n", rem_prefix(name
), rT
, rA
, rB
, rC
);
202 static void emit_RI7(struct spe_function
*p
, unsigned op
, unsigned rT
,
203 unsigned rA
, int imm
, const char *name
)
205 union spe_inst_RI7 inst
;
210 p
->store
[p
->num_inst
++] = inst
.bits
;
211 assert(p
->num_inst
<= p
->max_inst
);
214 printf("%s\t$%d, $%d, 0x%x\n", rem_prefix(name
), rT
, rA
, imm
);
220 static void emit_RI8(struct spe_function
*p
, unsigned op
, unsigned rT
,
221 unsigned rA
, int imm
, const char *name
)
223 union spe_inst_RI8 inst
;
228 p
->store
[p
->num_inst
++] = inst
.bits
;
229 assert(p
->num_inst
<= p
->max_inst
);
232 printf("%s\t$%d, $%d, 0x%x\n", rem_prefix(name
), rT
, rA
, imm
);
238 static void emit_RI10(struct spe_function
*p
, unsigned op
, unsigned rT
,
239 unsigned rA
, int imm
, const char *name
)
241 union spe_inst_RI10 inst
;
246 p
->store
[p
->num_inst
++] = inst
.bits
;
247 assert(p
->num_inst
<= p
->max_inst
);
250 if (strcmp(name
, "spe_lqd") == 0 ||
251 strcmp(name
, "spe_stqd") == 0)
252 printf("%s\t$%d, 0x%x($%d)\n", rem_prefix(name
), rT
, imm
, rA
);
254 printf("%s\t$%d, $%d, 0x%x\n", rem_prefix(name
), rT
, rA
, imm
);
259 static void emit_RI16(struct spe_function
*p
, unsigned op
, unsigned rT
,
260 int imm
, const char *name
)
262 union spe_inst_RI16 inst
;
266 p
->store
[p
->num_inst
++] = inst
.bits
;
267 assert(p
->num_inst
<= p
->max_inst
);
270 printf("%s\t$%d, 0x%x\n", rem_prefix(name
), rT
, imm
);
275 static void emit_RI18(struct spe_function
*p
, unsigned op
, unsigned rT
,
276 int imm
, const char *name
)
278 union spe_inst_RI18 inst
;
282 p
->store
[p
->num_inst
++] = inst
.bits
;
283 assert(p
->num_inst
<= p
->max_inst
);
286 printf("%s\t$%d, 0x%x\n", rem_prefix(name
), rT
, imm
);
293 #define EMIT_(_name, _op) \
294 void _name (struct spe_function *p, unsigned rT) \
296 emit_RR(p, _op, rT, 0, 0, __FUNCTION__); \
299 #define EMIT_R(_name, _op) \
300 void _name (struct spe_function *p, unsigned rT, unsigned rA) \
302 emit_RR(p, _op, rT, rA, 0, __FUNCTION__); \
305 #define EMIT_RR(_name, _op) \
306 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB) \
308 emit_RR(p, _op, rT, rA, rB, __FUNCTION__); \
311 #define EMIT_RRR(_name, _op) \
312 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB, unsigned rC) \
314 emit_RRR(p, _op, rT, rA, rB, rC, __FUNCTION__); \
317 #define EMIT_RI7(_name, _op) \
318 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
320 emit_RI7(p, _op, rT, rA, imm, __FUNCTION__); \
323 #define EMIT_RI8(_name, _op, bias) \
324 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
326 emit_RI8(p, _op, rT, rA, bias - imm, __FUNCTION__); \
329 #define EMIT_RI10(_name, _op) \
330 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
332 emit_RI10(p, _op, rT, rA, imm, __FUNCTION__); \
335 #define EMIT_RI16(_name, _op) \
336 void _name (struct spe_function *p, unsigned rT, int imm) \
338 emit_RI16(p, _op, rT, imm, __FUNCTION__); \
341 #define EMIT_RI18(_name, _op) \
342 void _name (struct spe_function *p, unsigned rT, int imm) \
344 emit_RI18(p, _op, rT, imm, __FUNCTION__); \
347 #define EMIT_I16(_name, _op) \
348 void _name (struct spe_function *p, int imm) \
350 emit_RI16(p, _op, 0, imm, __FUNCTION__); \
353 #include "rtasm_ppc_spe.h"
357 * Initialize an spe_function.
358 * \param code_size size of instruction buffer to allocate, in bytes.
360 void spe_init_func(struct spe_function
*p
, unsigned code_size
)
362 p
->store
= align_malloc(code_size
, 16);
364 p
->max_inst
= code_size
/ SPE_INST_SIZE
;
366 /* Conservatively treat R0 - R2 and R80 - R127 as non-volatile.
369 p
->regs
[1] = (1U << (80 - 64)) - 1;
376 void spe_release_func(struct spe_function
*p
)
378 assert(p
->num_inst
<= p
->max_inst
);
379 if (p
->store
!= NULL
) {
380 align_free(p
->store
);
386 /** Return current code size in bytes. */
387 unsigned spe_code_size(const struct spe_function
*p
)
389 return p
->num_inst
* SPE_INST_SIZE
;
394 * Allocate a SPE register.
395 * \return register index or -1 if none left.
397 int spe_allocate_available_register(struct spe_function
*p
)
400 for (i
= 0; i
< SPE_NUM_REGS
; i
++) {
401 const uint64_t mask
= (1ULL << (i
% 64));
402 const unsigned idx
= i
/ 64;
405 if ((p
->regs
[idx
] & mask
) != 0) {
406 p
->regs
[idx
] &= ~mask
;
416 * Mark the given SPE register as "allocated".
418 int spe_allocate_register(struct spe_function
*p
, int reg
)
420 const unsigned idx
= reg
/ 64;
421 const unsigned bit
= reg
% 64;
423 assert(reg
< SPE_NUM_REGS
);
424 assert((p
->regs
[idx
] & (1ULL << bit
)) != 0);
426 p
->regs
[idx
] &= ~(1ULL << bit
);
432 * Mark the given SPE register as "unallocated".
434 void spe_release_register(struct spe_function
*p
, int reg
)
436 const unsigned idx
= reg
/ 64;
437 const unsigned bit
= reg
% 64;
441 assert(reg
< SPE_NUM_REGS
);
442 assert((p
->regs
[idx
] & (1ULL << bit
)) == 0);
444 p
->regs
[idx
] |= (1ULL << bit
);
449 spe_print_code(struct spe_function
*p
, boolean enable
)
456 spe_indent(struct spe_function
*p
, int spaces
)
463 spe_comment(struct spe_function
*p
, int rel_indent
, const char *s
)
466 p
->indent
+= rel_indent
;
468 p
->indent
-= rel_indent
;
475 * For branch instructions:
476 * \param d if 1, disable interupts if branch is taken
477 * \param e if 1, enable interupts if branch is taken
478 * If d and e are both zero, don't change interupt status (right?)
481 /** Branch Indirect to address in rA */
482 void spe_bi(struct spe_function
*p
, unsigned rA
, int d
, int e
)
484 emit_RI7(p
, 0x1a8, 0, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
487 /** Interupt Return */
488 void spe_iret(struct spe_function
*p
, unsigned rA
, int d
, int e
)
490 emit_RI7(p
, 0x1aa, 0, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
493 /** Branch indirect and set link on external data */
494 void spe_bisled(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
,
497 emit_RI7(p
, 0x1ab, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
500 /** Branch indirect and set link. Save PC in rT, jump to rA. */
501 void spe_bisl(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
,
504 emit_RI7(p
, 0x1a9, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
507 /** Branch indirect if zero word. If rT.word[0]==0, jump to rA. */
508 void spe_biz(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
, int e
)
510 emit_RI7(p
, 0x128, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
513 /** Branch indirect if non-zero word. If rT.word[0]!=0, jump to rA. */
514 void spe_binz(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
, int e
)
516 emit_RI7(p
, 0x129, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
519 /** Branch indirect if zero halfword. If rT.halfword[1]==0, jump to rA. */
520 void spe_bihz(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
, int e
)
522 emit_RI7(p
, 0x12a, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
525 /** Branch indirect if non-zero halfword. If rT.halfword[1]!=0, jump to rA. */
526 void spe_bihnz(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
, int e
)
528 emit_RI7(p
, 0x12b, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
532 /* Hint-for-branch instructions
541 /* Control instructions
545 EMIT_RR (spe_stopd
, 0x140);
546 EMIT_ (spe_lnop
, 0x001);
547 EMIT_ (spe_nop
, 0x201);
549 EMIT_ (spe_dsync
, 0x003);
550 EMIT_R (spe_mfspr
, 0x00c);
551 EMIT_R (spe_mtspr
, 0x10c);
556 ** Helper / "macro" instructions.
557 ** Use somewhat verbose names as a reminder that these aren't native
563 spe_load_float(struct spe_function
*p
, unsigned rT
, float x
)
568 else if (x
== 0.5f
) {
569 spe_ilhu(p
, rT
, 0x3f00);
571 else if (x
== 1.0f
) {
572 spe_ilhu(p
, rT
, 0x3f80);
574 else if (x
== -1.0f
) {
575 spe_ilhu(p
, rT
, 0xbf80);
583 spe_ilhu(p
, rT
, bits
.u
>> 16);
584 spe_iohl(p
, rT
, bits
.u
& 0xffff);
590 spe_load_int(struct spe_function
*p
, unsigned rT
, int i
)
592 if (-32768 <= i
&& i
<= 32767) {
596 spe_ilhu(p
, rT
, i
>> 16);
598 spe_iohl(p
, rT
, i
& 0xffff);
602 void spe_load_uint(struct spe_function
*p
, unsigned rT
, unsigned int ui
)
604 /* If the whole value is in the lower 18 bits, use ila, which
605 * doesn't sign-extend. Otherwise, if the two halfwords of
606 * the constant are identical, use ilh. Otherwise, we have
607 * to use ilhu followed by iohl.
609 if ((ui
& 0xfffc0000) == ui
) {
612 else if ((ui
>> 16) == (ui
& 0xffff)) {
613 spe_ilh(p
, rT
, ui
& 0xffff);
616 spe_ilhu(p
, rT
, ui
>> 16);
618 spe_iohl(p
, rT
, ui
& 0xffff);
624 spe_splat(struct spe_function
*p
, unsigned rT
, unsigned rA
)
626 /* Duplicate bytes 0, 1, 2, and 3 across the whole register */
627 spe_ila(p
, rT
, 0x00010203);
628 spe_shufb(p
, rT
, rA
, rA
, rT
);
633 spe_complement(struct spe_function
*p
, unsigned rT
, unsigned rA
)
635 spe_nor(p
, rT
, rA
, rA
);
640 spe_move(struct spe_function
*p
, unsigned rT
, unsigned rA
)
642 /* Use different instructions depending on the instruction address
643 * to take advantage of the dual pipelines.
646 spe_shlqbyi(p
, rT
, rA
, 0); /* odd pipe */
648 spe_ori(p
, rT
, rA
, 0); /* even pipe */
653 spe_zero(struct spe_function
*p
, unsigned rT
)
655 spe_xor(p
, rT
, rT
, rT
);
660 spe_splat_word(struct spe_function
*p
, unsigned rT
, unsigned rA
, int word
)
667 spe_ila(p
, tmp1
, 66051);
668 spe_shufb(p
, rT
, rA
, rA
, tmp1
);
671 /* XXX review this, we may not need the rotqbyi instruction */
673 int tmp2
= spe_allocate_available_register(p
);
675 spe_ila(p
, tmp1
, 66051);
676 spe_rotqbyi(p
, tmp2
, rA
, 4 * word
);
677 spe_shufb(p
, rT
, tmp2
, tmp2
, tmp1
);
679 spe_release_register(p
, tmp2
);
684 * For each 32-bit float element of rA and rB, choose the smaller of the
685 * two, compositing them into the rT register.
687 * The Float Compare Greater Than (fcgt) instruction will put 1s into
688 * compare_reg where rA > rB, and 0s where rA <= rB.
690 * Then the Select Bits (selb) instruction will take bits from rA where
691 * compare_reg is 0, and from rB where compare_reg is 1; i.e., from rA
692 * where rA <= rB and from rB where rB > rA, which is exactly the
695 * The compare_reg could in many cases be the same as rT, unless
696 * rT == rA || rt == rB. But since this is common in constructions
697 * like "x = min(x, a)", we always allocate a new register to be safe.
700 spe_float_min(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned rB
)
702 unsigned int compare_reg
= spe_allocate_available_register(p
);
703 spe_fcgt(p
, compare_reg
, rA
, rB
);
704 spe_selb(p
, rT
, rA
, rB
, compare_reg
);
705 spe_release_register(p
, compare_reg
);
709 * For each 32-bit float element of rA and rB, choose the greater of the
710 * two, compositing them into the rT register.
712 * The logic is similar to that of spe_float_min() above; the only
713 * difference is that the registers on spe_selb() have been reversed,
714 * so that the larger of the two is selected instead of the smaller.
717 spe_float_max(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned rB
)
719 unsigned int compare_reg
= spe_allocate_available_register(p
);
720 spe_fcgt(p
, compare_reg
, rA
, rB
);
721 spe_selb(p
, rT
, rB
, rA
, compare_reg
);
722 spe_release_register(p
, compare_reg
);
725 #endif /* GALLIUM_CELL */