src/gallium/auxiliary/rtasm/rtasm_ppc_spe.c

   1 /*
   2  * (C) Copyright IBM Corporation 2008
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  19  * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * \file
  27  * Real-time assembly generation interface for Cell B.E. SPEs.
  28  *
  29  * \author Ian Romanick <idr@us.ibm.com>
  30  */
  31
  32 #include "pipe/p_compiler.h"
  33 #include "util/u_memory.h"
  34 #include "rtasm_ppc_spe.h"
  35
  36 #ifdef GALLIUM_CELL
  37 /**
  38  * SPE instruction types
  39  *
  40  * There are 6 primary instruction encodings used on the Cell's SPEs.  Each of
  41  * the following unions encodes one type.
  42  *
  43  * \bug
  44  * If, at some point, we start generating SPE code from a little-endian host
  45  * these unions will not work.
  46  */
  47 /*@{*/
  48 /**
  49  * Encode one output register with two input registers
  50  */
  51 union spe_inst_RR {
  52     uint32_t bits;
  53     struct {
  54         unsigned op:11;
  55         unsigned rB:7;
  56         unsigned rA:7;
  57         unsigned rT:7;
  58     } inst;
  59 };
  60
  61
  62 /**
  63  * Encode one output register with three input registers
  64  */
  65 union spe_inst_RRR {
  66     uint32_t bits;
  67     struct {
  68         unsigned op:4;
  69         unsigned rT:7;
  70         unsigned rB:7;
  71         unsigned rA:7;
  72         unsigned rC:7;
  73     } inst;
  74 };
  75
  76
  77 /**
  78  * Encode one output register with one input reg. and a 7-bit signed immed
  79  */
  80 union spe_inst_RI7 {
  81     uint32_t bits;
  82     struct {
  83         unsigned op:11;
  84         unsigned i7:7;
  85         unsigned rA:7;
  86         unsigned rT:7;
  87     } inst;
  88 };
  89
  90
  91 /**
  92  * Encode one output register with one input reg. and an 8-bit signed immed
  93  */
  94 union spe_inst_RI8 {
  95     uint32_t bits;
  96     struct {
  97         unsigned op:10;
  98         unsigned i8:8;
  99         unsigned rA:7;
 100         unsigned rT:7;
 101     } inst;
 102 };
 103
 104
 105 /**
 106  * Encode one output register with one input reg. and a 10-bit signed immed
 107  */
 108 union spe_inst_RI10 {
 109     uint32_t bits;
 110     struct {
 111         unsigned op:8;
 112         unsigned i10:10;
 113         unsigned rA:7;
 114         unsigned rT:7;
 115     } inst;
 116 };
 117
 118
 119 /**
 120  * Encode one output register with a 16-bit signed immediate
 121  */
 122 union spe_inst_RI16 {
 123     uint32_t bits;
 124     struct {
 125         unsigned op:9;
 126         unsigned i16:16;
 127         unsigned rT:7;
 128     } inst;
 129 };
 130
 131
 132 /**
 133  * Encode one output register with a 18-bit signed immediate
 134  */
 135 union spe_inst_RI18 {
 136     uint32_t bits;
 137     struct {
 138         unsigned op:7;
 139         unsigned i18:18;
 140         unsigned rT:7;
 141     } inst;
 142 };
 143 /*@}*/
 144
 145
 146 static void emit_RR(struct spe_function *p, unsigned op, unsigned rT,
 147                     unsigned rA, unsigned rB)
 148 {
 149     union spe_inst_RR inst;
 150     inst.inst.op = op;
 151     inst.inst.rB = rB;
 152     inst.inst.rA = rA;
 153     inst.inst.rT = rT;
 154     *p->csr = inst.bits;
 155     p->csr++;
 156 }
 157
 158
 159 static void emit_RRR(struct spe_function *p, unsigned op, unsigned rT,
 160                     unsigned rA, unsigned rB, unsigned rC)
 161 {
 162     union spe_inst_RRR inst;
 163     inst.inst.op = op;
 164     inst.inst.rT = rT;
 165     inst.inst.rB = rB;
 166     inst.inst.rA = rA;
 167     inst.inst.rC = rC;
 168     *p->csr = inst.bits;
 169     p->csr++;
 170 }
 171
 172
 173 static void emit_RI7(struct spe_function *p, unsigned op, unsigned rT,
 174                      unsigned rA, int imm)
 175 {
 176     union spe_inst_RI7 inst;
 177     inst.inst.op = op;
 178     inst.inst.i7 = imm;
 179     inst.inst.rA = rA;
 180     inst.inst.rT = rT;
 181     *p->csr = inst.bits;
 182     p->csr++;
 183 }
 184
 185
 186
 187 static void emit_RI8(struct spe_function *p, unsigned op, unsigned rT,
 188                      unsigned rA, int imm)
 189 {
 190     union spe_inst_RI8 inst;
 191     inst.inst.op = op;
 192     inst.inst.i8 = imm;
 193     inst.inst.rA = rA;
 194     inst.inst.rT = rT;
 195     *p->csr = inst.bits;
 196     p->csr++;
 197 }
 198
 199
 200
 201 static void emit_RI10(struct spe_function *p, unsigned op, unsigned rT,
 202                       unsigned rA, int imm)
 203 {
 204     union spe_inst_RI10 inst;
 205     inst.inst.op = op;
 206     inst.inst.i10 = imm;
 207     inst.inst.rA = rA;
 208     inst.inst.rT = rT;
 209     *p->csr = inst.bits;
 210     p->csr++;
 211 }
 212
 213
 214 static void emit_RI16(struct spe_function *p, unsigned op, unsigned rT,
 215                       int imm)
 216 {
 217     union spe_inst_RI16 inst;
 218     inst.inst.op = op;
 219     inst.inst.i16 = imm;
 220     inst.inst.rT = rT;
 221     *p->csr = inst.bits;
 222     p->csr++;
 223 }
 224
 225
 226 static void emit_RI18(struct spe_function *p, unsigned op, unsigned rT,
 227                       int imm)
 228 {
 229     union spe_inst_RI18 inst;
 230     inst.inst.op = op;
 231     inst.inst.i18 = imm;
 232     inst.inst.rT = rT;
 233     *p->csr = inst.bits;
 234     p->csr++;
 235 }
 236
 237
 238
 239
 240 #define EMIT_(_name, _op) \
 241 void _name (struct spe_function *p, unsigned rT) \
 242 { \
 243     emit_RR(p, _op, rT, 0, 0); \
 244 }
 245
 246 #define EMIT_R(_name, _op) \
 247 void _name (struct spe_function *p, unsigned rT, unsigned rA) \
 248 { \
 249     emit_RR(p, _op, rT, rA, 0); \
 250 }
 251
 252 #define EMIT_RR(_name, _op) \
 253 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB) \
 254 { \
 255     emit_RR(p, _op, rT, rA, rB); \
 256 }
 257
 258 #define EMIT_RRR(_name, _op) \
 259 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB, unsigned rC) \
 260 { \
 261     emit_RRR(p, _op, rT, rA, rB, rC); \
 262 }
 263
 264 #define EMIT_RI7(_name, _op) \
 265 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
 266 { \
 267     emit_RI7(p, _op, rT, rA, imm); \
 268 }
 269
 270 #define EMIT_RI8(_name, _op, bias) \
 271 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
 272 { \
 273     emit_RI8(p, _op, rT, rA, bias - imm); \
 274 }
 275
 276 #define EMIT_RI10(_name, _op) \
 277 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
 278 { \
 279     emit_RI10(p, _op, rT, rA, imm); \
 280 }
 281
 282 #define EMIT_RI16(_name, _op) \
 283 void _name (struct spe_function *p, unsigned rT, int imm) \
 284 { \
 285     emit_RI16(p, _op, rT, imm); \
 286 }
 287
 288 #define EMIT_RI18(_name, _op) \
 289 void _name (struct spe_function *p, unsigned rT, int imm) \
 290 { \
 291     emit_RI18(p, _op, rT, imm); \
 292 }
 293
 294 #define EMIT_I16(_name, _op) \
 295 void _name (struct spe_function *p, int imm) \
 296 { \
 297     emit_RI16(p, _op, 0, imm); \
 298 }
 299
 300 #include "rtasm_ppc_spe.h"
 301
 302
 303 /**
 304  * Initialize an spe_function.
 305  * \param code_size  size of instruction buffer to allocate, in bytes.
 306  */
 307 void spe_init_func(struct spe_function *p, unsigned code_size)
 308 {
 309     p->store = align_malloc(code_size, 16);
 310     p->csr = p->store;
 311
 312     /* Conservatively treat R0 - R2 and R80 - R127 as non-volatile.
 313      */
 314     p->regs[0] = ~7;
 315     p->regs[1] = (1U << (80 - 64)) - 1;
 316 }
 317
 318
 319 void spe_release_func(struct spe_function *p)
 320 {
 321     if (p->store != NULL) {
 322         align_free(p->store);
 323     }
 324     p->store = NULL;
 325     p->csr = NULL;
 326 }
 327
 328
 329 /**
 330  * Alloate a SPE register.
 331  * \return register index or -1 if none left.
 332  */
 333 int spe_allocate_available_register(struct spe_function *p)
 334 {
 335    unsigned i;
 336    for (i = 0; i < SPE_NUM_REGS; i++) {
 337       const uint64_t mask = (1ULL << (i % 64));
 338       const unsigned idx = i / 64;
 339
 340       if ((p->regs[idx] & mask) != 0) {
 341          p->regs[idx] &= ~mask;
 342          return i;
 343       }
 344    }
 345
 346    return -1;
 347 }
 348
 349
 350 /**
 351  * Mark the given SPE register as "allocated".
 352  */
 353 int spe_allocate_register(struct spe_function *p, int reg)
 354 {
 355    const unsigned idx = reg / 64;
 356    const unsigned bit = reg % 64;
 357
 358    assert(reg < SPE_NUM_REGS);
 359    assert((p->regs[idx] & (1ULL << bit)) != 0);
 360
 361    p->regs[idx] &= ~(1ULL << bit);
 362    return reg;
 363 }
 364
 365
 366 /**
 367  * Mark the given SPE register as "unallocated".
 368  */
 369 void spe_release_register(struct spe_function *p, int reg)
 370 {
 371    const unsigned idx = reg / 64;
 372    const unsigned bit = reg % 64;
 373
 374    assert(reg < SPE_NUM_REGS);
 375    assert((p->regs[idx] & (1ULL << bit)) == 0);
 376
 377    p->regs[idx] |= (1ULL << bit);
 378 }
 379
 380
 381 /**
 382  * For branch instructions:
 383  * \param d  if 1, disable interupts if branch is taken
 384  * \param e  if 1, enable interupts if branch is taken
 385  * If d and e are both zero, don't change interupt status (right?)
 386  */
 387
 388 /** Branch Indirect to address in rA */
 389 void spe_bi(struct spe_function *p, unsigned rA, int d, int e)
 390 {
 391     emit_RI7(p, 0x1a8, 0, rA, (d << 5) | (e << 4));
 392 }
 393
 394 /** Interupt Return */
 395 void spe_iret(struct spe_function *p, unsigned rA, int d, int e)
 396 {
 397     emit_RI7(p, 0x1aa, 0, rA, (d << 5) | (e << 4));
 398 }
 399
 400 /** Branch indirect and set link on external data */
 401 void spe_bisled(struct spe_function *p, unsigned rT, unsigned rA, int d,
 402                 int e)
 403 {
 404     emit_RI7(p, 0x1ab, rT, rA, (d << 5) | (e << 4));
 405 }
 406
 407 /** Branch indirect and set link.  Save PC in rT, jump to rA. */
 408 void spe_bisl(struct spe_function *p, unsigned rT, unsigned rA, int d,
 409                 int e)
 410 {
 411     emit_RI7(p, 0x1a9, rT, rA, (d << 5) | (e << 4));
 412 }
 413
 414 /** Branch indirect if zero word.  If rT.word[0]==0, jump to rA. */
 415 void spe_biz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
 416 {
 417     emit_RI7(p, 0x128, rT, rA, (d << 5) | (e << 4));
 418 }
 419
 420 /** Branch indirect if non-zero word.  If rT.word[0]!=0, jump to rA. */
 421 void spe_binz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
 422 {
 423     emit_RI7(p, 0x129, rT, rA, (d << 5) | (e << 4));
 424 }
 425
 426 /** Branch indirect if zero halfword.  If rT.halfword[1]==0, jump to rA. */
 427 void spe_bihz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
 428 {
 429     emit_RI7(p, 0x12a, rT, rA, (d << 5) | (e << 4));
 430 }
 431
 432 /** Branch indirect if non-zero halfword.  If rT.halfword[1]!=0, jump to rA. */
 433 void spe_bihnz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
 434 {
 435     emit_RI7(p, 0x12b, rT, rA, (d << 5) | (e << 4));
 436 }
 437
 438
 439 /* Hint-for-branch instructions
 440  */
 441 #if 0
 442 hbr;
 443 hbra;
 444 hbrr;
 445 #endif
 446
 447
 448 /* Control instructions
 449  */
 450 #if 0
 451 stop;
 452 EMIT_RR  (spe_stopd, 0x140);
 453 EMIT_    (spe_lnop,  0x001);
 454 EMIT_    (spe_nop,   0x201);
 455 sync;
 456 EMIT_    (spe_dsync, 0x003);
 457 EMIT_R   (spe_mfspr, 0x00c);
 458 EMIT_R   (spe_mtspr, 0x10c);
 459 #endif
 460
 461 #endif /* GALLIUM_CELL */