2 * (C) Copyright IBM Corporation 2008
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * Real-time assembly generation interface for Cell B.E. SPEs.
29 * \author Ian Romanick <idr@us.ibm.com>
35 #include "pipe/p_compiler.h"
36 #include "util/u_memory.h"
37 #include "rtasm_ppc_spe.h"
42 * SPE instruction types
44 * There are 6 primary instruction encodings used on the Cell's SPEs. Each of
45 * the following unions encodes one type.
48 * If, at some point, we start generating SPE code from a little-endian host
49 * these unions will not work.
53 * Encode one output register with two input registers
67 * Encode one output register with three input registers
82 * Encode one output register with one input reg. and a 7-bit signed immed
96 * Encode one output register with one input reg. and an 8-bit signed immed
110 * Encode one output register with one input reg. and a 10-bit signed immed
112 union spe_inst_RI10
{
124 * Encode one output register with a 16-bit signed immediate
126 union spe_inst_RI16
{
137 * Encode one output register with a 18-bit signed immediate
139 union spe_inst_RI18
{
151 indent(const struct spe_function
*p
)
154 for (i
= 0; i
< p
->indent
; i
++) {
161 rem_prefix(const char *longname
)
177 /* cycle through four buffers to handle multiple calls per printf */
178 static char buf
[4][10];
181 sprintf(buf
[b
], "$%d", reg
);
189 emit_instruction(struct spe_function
*p
, uint32_t inst_bits
)
192 return; /* out of memory, drop the instruction */
194 if (p
->num_inst
== p
->max_inst
) {
195 /* allocate larger buffer */
197 p
->max_inst
*= 2; /* 2x larger */
198 newbuf
= align_malloc(p
->max_inst
* SPE_INST_SIZE
, 16);
200 memcpy(newbuf
, p
->store
, p
->num_inst
* SPE_INST_SIZE
);
202 align_free(p
->store
);
211 p
->store
[p
->num_inst
++] = inst_bits
;
216 static void emit_RR(struct spe_function
*p
, unsigned op
, unsigned rT
,
217 unsigned rA
, unsigned rB
, const char *name
)
219 union spe_inst_RR inst
;
224 emit_instruction(p
, inst
.bits
);
227 printf("%s\t%s, %s, %s\n",
228 rem_prefix(name
), reg_name(rT
), reg_name(rA
), reg_name(rB
));
233 static void emit_RRR(struct spe_function
*p
, unsigned op
, unsigned rT
,
234 unsigned rA
, unsigned rB
, unsigned rC
, const char *name
)
236 union spe_inst_RRR inst
;
242 emit_instruction(p
, inst
.bits
);
245 printf("%s\t%s, %s, %s, %s\n", rem_prefix(name
), reg_name(rT
),
246 reg_name(rA
), reg_name(rB
), reg_name(rC
));
251 static void emit_RI7(struct spe_function
*p
, unsigned op
, unsigned rT
,
252 unsigned rA
, int imm
, const char *name
)
254 union spe_inst_RI7 inst
;
259 emit_instruction(p
, inst
.bits
);
262 printf("%s\t%s, %s, 0x%x\n",
263 rem_prefix(name
), reg_name(rT
), reg_name(rA
), imm
);
269 static void emit_RI8(struct spe_function
*p
, unsigned op
, unsigned rT
,
270 unsigned rA
, int imm
, const char *name
)
272 union spe_inst_RI8 inst
;
277 emit_instruction(p
, inst
.bits
);
280 printf("%s\t%s, %s, 0x%x\n",
281 rem_prefix(name
), reg_name(rT
), reg_name(rA
), imm
);
287 static void emit_RI10(struct spe_function
*p
, unsigned op
, unsigned rT
,
288 unsigned rA
, int imm
, const char *name
)
290 union spe_inst_RI10 inst
;
295 emit_instruction(p
, inst
.bits
);
298 printf("%s\t%s, %s, 0x%x\n",
299 rem_prefix(name
), reg_name(rT
), reg_name(rA
), imm
);
304 /** As above, but do range checking on signed immediate value */
305 static void emit_RI10s(struct spe_function
*p
, unsigned op
, unsigned rT
,
306 unsigned rA
, int imm
, const char *name
)
310 emit_RI10(p
, op
, rT
, rA
, imm
, name
);
314 static void emit_RI16(struct spe_function
*p
, unsigned op
, unsigned rT
,
315 int imm
, const char *name
)
317 union spe_inst_RI16 inst
;
321 emit_instruction(p
, inst
.bits
);
324 printf("%s\t%s, 0x%x\n", rem_prefix(name
), reg_name(rT
), imm
);
329 static void emit_RI18(struct spe_function
*p
, unsigned op
, unsigned rT
,
330 int imm
, const char *name
)
332 union spe_inst_RI18 inst
;
336 emit_instruction(p
, inst
.bits
);
339 printf("%s\t%s, 0x%x\n", rem_prefix(name
), reg_name(rT
), imm
);
344 #define EMIT(_name, _op) \
345 void _name (struct spe_function *p) \
347 emit_RR(p, _op, 0, 0, 0, __FUNCTION__); \
350 #define EMIT_(_name, _op) \
351 void _name (struct spe_function *p, unsigned rT) \
353 emit_RR(p, _op, rT, 0, 0, __FUNCTION__); \
356 #define EMIT_R(_name, _op) \
357 void _name (struct spe_function *p, unsigned rT, unsigned rA) \
359 emit_RR(p, _op, rT, rA, 0, __FUNCTION__); \
362 #define EMIT_RR(_name, _op) \
363 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB) \
365 emit_RR(p, _op, rT, rA, rB, __FUNCTION__); \
368 #define EMIT_RRR(_name, _op) \
369 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB, unsigned rC) \
371 emit_RRR(p, _op, rT, rA, rB, rC, __FUNCTION__); \
374 #define EMIT_RI7(_name, _op) \
375 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
377 emit_RI7(p, _op, rT, rA, imm, __FUNCTION__); \
380 #define EMIT_RI8(_name, _op, bias) \
381 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
383 emit_RI8(p, _op, rT, rA, bias - imm, __FUNCTION__); \
386 #define EMIT_RI10(_name, _op) \
387 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
389 emit_RI10(p, _op, rT, rA, imm, __FUNCTION__); \
392 #define EMIT_RI10s(_name, _op) \
393 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
395 emit_RI10s(p, _op, rT, rA, imm, __FUNCTION__); \
398 #define EMIT_RI16(_name, _op) \
399 void _name (struct spe_function *p, unsigned rT, int imm) \
401 emit_RI16(p, _op, rT, imm, __FUNCTION__); \
404 #define EMIT_RI18(_name, _op) \
405 void _name (struct spe_function *p, unsigned rT, int imm) \
407 emit_RI18(p, _op, rT, imm, __FUNCTION__); \
410 #define EMIT_I16(_name, _op) \
411 void _name (struct spe_function *p, int imm) \
413 emit_RI16(p, _op, 0, imm, __FUNCTION__); \
416 #include "rtasm_ppc_spe.h"
421 * Initialize an spe_function.
422 * \param code_size initial size of instruction buffer to allocate, in bytes.
423 * If zero, use a default.
425 void spe_init_func(struct spe_function
*p
, unsigned code_size
)
433 p
->max_inst
= code_size
/ SPE_INST_SIZE
;
434 p
->store
= align_malloc(code_size
, 16);
437 memset(p
->regs
, 0, SPE_NUM_REGS
* sizeof(p
->regs
[0]));
439 /* Conservatively treat R0 - R2 and R80 - R127 as non-volatile.
441 p
->regs
[0] = p
->regs
[1] = p
->regs
[2] = 1;
442 for (i
= 80; i
<= 127; i
++) {
451 void spe_release_func(struct spe_function
*p
)
453 assert(p
->num_inst
<= p
->max_inst
);
454 if (p
->store
!= NULL
) {
455 align_free(p
->store
);
461 /** Return current code size in bytes. */
462 unsigned spe_code_size(const struct spe_function
*p
)
464 return p
->num_inst
* SPE_INST_SIZE
;
469 * Allocate a SPE register.
470 * \return register index or -1 if none left.
472 int spe_allocate_available_register(struct spe_function
*p
)
475 for (i
= 0; i
< SPE_NUM_REGS
; i
++) {
476 if (p
->regs
[i
] == 0) {
487 * Mark the given SPE register as "allocated".
489 int spe_allocate_register(struct spe_function
*p
, int reg
)
491 assert(reg
< SPE_NUM_REGS
);
492 assert(p
->regs
[reg
] == 0);
499 * Mark the given SPE register as "unallocated". Note that this should
500 * only be used on registers allocated in the current register set; an
501 * assertion will fail if an attempt is made to deallocate a register
502 * allocated in an earlier register set.
504 void spe_release_register(struct spe_function
*p
, int reg
)
506 assert(reg
< SPE_NUM_REGS
);
507 assert(p
->regs
[reg
] == 1);
513 * Start a new set of registers. This can be called if
514 * it will be difficult later to determine exactly what
515 * registers were actually allocated during a code generation
516 * sequence, and you really just want to deallocate all of them.
518 void spe_allocate_register_set(struct spe_function
*p
)
522 /* Keep track of the set count. If it ever wraps around to 0,
526 assert(p
->set_count
> 0);
528 /* Increment the allocation count of all registers currently
529 * allocated. Then any registers that are allocated in this set
530 * will be the only ones with a count of 1; they'll all be released
531 * when the register set is released.
533 for (i
= 0; i
< SPE_NUM_REGS
; i
++) {
539 void spe_release_register_set(struct spe_function
*p
)
543 /* If the set count drops below zero, we're in trouble. */
544 assert(p
->set_count
> 0);
547 /* Drop the allocation level of all registers. Any allocated
548 * during this register set will drop to 0 and then become
551 for (i
= 0; i
< SPE_NUM_REGS
; i
++) {
559 spe_get_registers_used(const struct spe_function
*p
, ubyte used
[])
562 /* only count registers in the range available to callers */
563 for (i
= 2; i
< 80; i
++) {
573 spe_print_code(struct spe_function
*p
, boolean enable
)
580 spe_indent(struct spe_function
*p
, int spaces
)
587 spe_comment(struct spe_function
*p
, int rel_indent
, const char *s
)
590 p
->indent
+= rel_indent
;
592 p
->indent
-= rel_indent
;
600 * NOTE: offset is in bytes and the least significant 4 bits must be zero!
602 void spe_lqd(struct spe_function
*p
, unsigned rT
, unsigned rA
, int offset
)
604 const boolean pSave
= p
->print
;
606 /* offset must be a multiple of 16 */
607 assert(offset
% 16 == 0);
608 /* offset must fit in 10-bit signed int field, after shifting */
609 assert((offset
>> 4) <= 511);
610 assert((offset
>> 4) >= -512);
613 emit_RI10(p
, 0x034, rT
, rA
, offset
>> 4, "spe_lqd");
618 printf("lqd\t%s, %d(%s)\n", reg_name(rT
), offset
, reg_name(rA
));
625 * NOTE: offset is in bytes and the least significant 4 bits must be zero!
627 void spe_stqd(struct spe_function
*p
, unsigned rT
, unsigned rA
, int offset
)
629 const boolean pSave
= p
->print
;
631 /* offset must be a multiple of 16 */
632 assert(offset
% 16 == 0);
633 /* offset must fit in 10-bit signed int field, after shifting */
634 assert((offset
>> 4) <= 511);
635 assert((offset
>> 4) >= -512);
638 emit_RI10(p
, 0x024, rT
, rA
, offset
>> 4, "spe_stqd");
643 printf("stqd\t%s, %d(%s)\n", reg_name(rT
), offset
, reg_name(rA
));
649 * For branch instructions:
650 * \param d if 1, disable interupts if branch is taken
651 * \param e if 1, enable interupts if branch is taken
652 * If d and e are both zero, don't change interupt status (right?)
655 /** Branch Indirect to address in rA */
656 void spe_bi(struct spe_function
*p
, unsigned rA
, int d
, int e
)
658 emit_RI7(p
, 0x1a8, 0, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
661 /** Interupt Return */
662 void spe_iret(struct spe_function
*p
, unsigned rA
, int d
, int e
)
664 emit_RI7(p
, 0x1aa, 0, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
667 /** Branch indirect and set link on external data */
668 void spe_bisled(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
,
671 emit_RI7(p
, 0x1ab, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
674 /** Branch indirect and set link. Save PC in rT, jump to rA. */
675 void spe_bisl(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
,
678 emit_RI7(p
, 0x1a9, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
681 /** Branch indirect if zero word. If rT.word[0]==0, jump to rA. */
682 void spe_biz(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
, int e
)
684 emit_RI7(p
, 0x128, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
687 /** Branch indirect if non-zero word. If rT.word[0]!=0, jump to rA. */
688 void spe_binz(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
, int e
)
690 emit_RI7(p
, 0x129, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
693 /** Branch indirect if zero halfword. If rT.halfword[1]==0, jump to rA. */
694 void spe_bihz(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
, int e
)
696 emit_RI7(p
, 0x12a, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
699 /** Branch indirect if non-zero halfword. If rT.halfword[1]!=0, jump to rA. */
700 void spe_bihnz(struct spe_function
*p
, unsigned rT
, unsigned rA
, int d
, int e
)
702 emit_RI7(p
, 0x12b, rT
, rA
, (d
<< 5) | (e
<< 4), __FUNCTION__
);
706 /* Hint-for-branch instructions
715 /* Control instructions
719 EMIT_RR (spe_stopd
, 0x140);
720 EMIT_ (spe_nop
, 0x201);
722 EMIT_ (spe_dsync
, 0x003);
723 EMIT_R (spe_mfspr
, 0x00c);
724 EMIT_R (spe_mtspr
, 0x10c);
729 ** Helper / "macro" instructions.
730 ** Use somewhat verbose names as a reminder that these aren't native
736 spe_load_float(struct spe_function
*p
, unsigned rT
, float x
)
741 else if (x
== 0.5f
) {
742 spe_ilhu(p
, rT
, 0x3f00);
744 else if (x
== 1.0f
) {
745 spe_ilhu(p
, rT
, 0x3f80);
747 else if (x
== -1.0f
) {
748 spe_ilhu(p
, rT
, 0xbf80);
756 spe_ilhu(p
, rT
, bits
.u
>> 16);
757 spe_iohl(p
, rT
, bits
.u
& 0xffff);
763 spe_load_int(struct spe_function
*p
, unsigned rT
, int i
)
765 if (-32768 <= i
&& i
<= 32767) {
769 spe_ilhu(p
, rT
, i
>> 16);
771 spe_iohl(p
, rT
, i
& 0xffff);
775 void spe_load_uint(struct spe_function
*p
, unsigned rT
, unsigned int ui
)
777 /* If the whole value is in the lower 18 bits, use ila, which
778 * doesn't sign-extend. Otherwise, if the two halfwords of
779 * the constant are identical, use ilh. Otherwise, if every byte of
780 * the desired value is 0x00 or 0xff, we can use Form Select Mask for
781 * Bytes Immediate (fsmbi) to load the value in a single instruction.
782 * Otherwise, in the general case, we have to use ilhu followed by iohl.
784 if ((ui
& 0x0003ffff) == ui
) {
787 else if ((ui
>> 16) == (ui
& 0xffff)) {
788 spe_ilh(p
, rT
, ui
& 0xffff);
791 ((ui
& 0x000000ff) == 0 || (ui
& 0x000000ff) == 0x000000ff) &&
792 ((ui
& 0x0000ff00) == 0 || (ui
& 0x0000ff00) == 0x0000ff00) &&
793 ((ui
& 0x00ff0000) == 0 || (ui
& 0x00ff0000) == 0x00ff0000) &&
794 ((ui
& 0xff000000) == 0 || (ui
& 0xff000000) == 0xff000000)
796 unsigned int mask
= 0;
797 /* fsmbi duplicates each bit in the given mask eight times,
798 * using a 16-bit value to initialize a 16-byte quadword.
799 * Each 4-bit nybble of the mask corresponds to a full word
800 * of the result; look at the value and figure out the mask
801 * (replicated for each word in the quadword), and then
802 * form the "select mask" to get the value.
804 if ((ui
& 0x000000ff) == 0x000000ff) mask
|= 0x1111;
805 if ((ui
& 0x0000ff00) == 0x0000ff00) mask
|= 0x2222;
806 if ((ui
& 0x00ff0000) == 0x00ff0000) mask
|= 0x4444;
807 if ((ui
& 0xff000000) == 0xff000000) mask
|= 0x8888;
808 spe_fsmbi(p
, rT
, mask
);
811 /* The general case: this usually uses two instructions, but
812 * may use only one if the low-order 16 bits of each word are 0.
814 spe_ilhu(p
, rT
, ui
>> 16);
816 spe_iohl(p
, rT
, ui
& 0xffff);
821 * This function is constructed identically to spe_xor_uint() below.
822 * Changes to one should be made in the other.
825 spe_and_uint(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned int ui
)
827 /* If we can, emit a single instruction, either And Byte Immediate
828 * (which uses the same constant across each byte), And Halfword Immediate
829 * (which sign-extends a 10-bit immediate to 16 bits and uses that
830 * across each halfword), or And Word Immediate (which sign-extends
831 * a 10-bit immediate to 32 bits).
833 * Otherwise, we'll need to use a temporary register.
837 /* If the upper 23 bits are all 0s or all 1s, sign extension
838 * will work and we can use And Word Immediate
840 tmp
= ui
& 0xfffffe00;
841 if (tmp
== 0xfffffe00 || tmp
== 0) {
842 spe_andi(p
, rT
, rA
, ui
& 0x000003ff);
846 /* If the ui field is symmetric along halfword boundaries and
847 * the upper 7 bits of each halfword are all 0s or 1s, we
848 * can use And Halfword Immediate
850 tmp
= ui
& 0xfe00fe00;
851 if ((tmp
== 0xfe00fe00 || tmp
== 0) && ((ui
>> 16) == (ui
& 0x0000ffff))) {
852 spe_andhi(p
, rT
, rA
, ui
& 0x000003ff);
856 /* If the ui field is symmetric in each byte, then we can use
857 * the And Byte Immediate instruction.
859 tmp
= ui
& 0x000000ff;
860 if ((ui
>> 24) == tmp
&& ((ui
>> 16) & 0xff) == tmp
&& ((ui
>> 8) & 0xff) == tmp
) {
861 spe_andbi(p
, rT
, rA
, tmp
);
865 /* Otherwise, we'll have to use a temporary register. */
866 unsigned int tmp_reg
= spe_allocate_available_register(p
);
867 spe_load_uint(p
, tmp_reg
, ui
);
868 spe_and(p
, rT
, rA
, tmp_reg
);
869 spe_release_register(p
, tmp_reg
);
874 * This function is constructed identically to spe_and_uint() above.
875 * Changes to one should be made in the other.
878 spe_xor_uint(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned int ui
)
880 /* If we can, emit a single instruction, either Exclusive Or Byte
881 * Immediate (which uses the same constant across each byte), Exclusive
882 * Or Halfword Immediate (which sign-extends a 10-bit immediate to
883 * 16 bits and uses that across each halfword), or Exclusive Or Word
884 * Immediate (which sign-extends a 10-bit immediate to 32 bits).
886 * Otherwise, we'll need to use a temporary register.
890 /* If the upper 23 bits are all 0s or all 1s, sign extension
891 * will work and we can use Exclusive Or Word Immediate
893 tmp
= ui
& 0xfffffe00;
894 if (tmp
== 0xfffffe00 || tmp
== 0) {
895 spe_xori(p
, rT
, rA
, ui
& 0x000003ff);
899 /* If the ui field is symmetric along halfword boundaries and
900 * the upper 7 bits of each halfword are all 0s or 1s, we
901 * can use Exclusive Or Halfword Immediate
903 tmp
= ui
& 0xfe00fe00;
904 if ((tmp
== 0xfe00fe00 || tmp
== 0) && ((ui
>> 16) == (ui
& 0x0000ffff))) {
905 spe_xorhi(p
, rT
, rA
, ui
& 0x000003ff);
909 /* If the ui field is symmetric in each byte, then we can use
910 * the Exclusive Or Byte Immediate instruction.
912 tmp
= ui
& 0x000000ff;
913 if ((ui
>> 24) == tmp
&& ((ui
>> 16) & 0xff) == tmp
&& ((ui
>> 8) & 0xff) == tmp
) {
914 spe_xorbi(p
, rT
, rA
, tmp
);
918 /* Otherwise, we'll have to use a temporary register. */
919 unsigned int tmp_reg
= spe_allocate_available_register(p
);
920 spe_load_uint(p
, tmp_reg
, ui
);
921 spe_xor(p
, rT
, rA
, tmp_reg
);
922 spe_release_register(p
, tmp_reg
);
926 spe_compare_equal_uint(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned int ui
)
928 /* If the comparison value is 9 bits or less, it fits inside a
929 * Compare Equal Word Immediate instruction.
931 if ((ui
& 0x000001ff) == ui
) {
932 spe_ceqi(p
, rT
, rA
, ui
);
934 /* Otherwise, we're going to have to load a word first. */
936 unsigned int tmp_reg
= spe_allocate_available_register(p
);
937 spe_load_uint(p
, tmp_reg
, ui
);
938 spe_ceq(p
, rT
, rA
, tmp_reg
);
939 spe_release_register(p
, tmp_reg
);
944 spe_compare_greater_uint(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned int ui
)
946 /* If the comparison value is 10 bits or less, it fits inside a
947 * Compare Logical Greater Than Word Immediate instruction.
949 if ((ui
& 0x000003ff) == ui
) {
950 spe_clgti(p
, rT
, rA
, ui
);
952 /* Otherwise, we're going to have to load a word first. */
954 unsigned int tmp_reg
= spe_allocate_available_register(p
);
955 spe_load_uint(p
, tmp_reg
, ui
);
956 spe_clgt(p
, rT
, rA
, tmp_reg
);
957 spe_release_register(p
, tmp_reg
);
962 spe_splat(struct spe_function
*p
, unsigned rT
, unsigned rA
)
964 /* Use a temporary, just in case rT == rA */
965 unsigned int tmp_reg
= spe_allocate_available_register(p
);
966 /* Duplicate bytes 0, 1, 2, and 3 across the whole register */
967 spe_ila(p
, tmp_reg
, 0x00010203);
968 spe_shufb(p
, rT
, rA
, rA
, tmp_reg
);
969 spe_release_register(p
, tmp_reg
);
974 spe_complement(struct spe_function
*p
, unsigned rT
, unsigned rA
)
976 spe_nor(p
, rT
, rA
, rA
);
981 spe_move(struct spe_function
*p
, unsigned rT
, unsigned rA
)
983 /* Use different instructions depending on the instruction address
984 * to take advantage of the dual pipelines.
987 spe_shlqbyi(p
, rT
, rA
, 0); /* odd pipe */
989 spe_ori(p
, rT
, rA
, 0); /* even pipe */
994 spe_zero(struct spe_function
*p
, unsigned rT
)
996 spe_xor(p
, rT
, rT
, rT
);
1001 spe_splat_word(struct spe_function
*p
, unsigned rT
, unsigned rA
, int word
)
1008 spe_ila(p
, tmp1
, 66051);
1009 spe_shufb(p
, rT
, rA
, rA
, tmp1
);
1012 /* XXX review this, we may not need the rotqbyi instruction */
1014 int tmp2
= spe_allocate_available_register(p
);
1016 spe_ila(p
, tmp1
, 66051);
1017 spe_rotqbyi(p
, tmp2
, rA
, 4 * word
);
1018 spe_shufb(p
, rT
, tmp2
, tmp2
, tmp1
);
1020 spe_release_register(p
, tmp2
);
1025 * For each 32-bit float element of rA and rB, choose the smaller of the
1026 * two, compositing them into the rT register.
1028 * The Float Compare Greater Than (fcgt) instruction will put 1s into
1029 * compare_reg where rA > rB, and 0s where rA <= rB.
1031 * Then the Select Bits (selb) instruction will take bits from rA where
1032 * compare_reg is 0, and from rB where compare_reg is 1; i.e., from rA
1033 * where rA <= rB and from rB where rB > rA, which is exactly the
1036 * The compare_reg could in many cases be the same as rT, unless
1037 * rT == rA || rt == rB. But since this is common in constructions
1038 * like "x = min(x, a)", we always allocate a new register to be safe.
1041 spe_float_min(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned rB
)
1043 unsigned int compare_reg
= spe_allocate_available_register(p
);
1044 spe_fcgt(p
, compare_reg
, rA
, rB
);
1045 spe_selb(p
, rT
, rA
, rB
, compare_reg
);
1046 spe_release_register(p
, compare_reg
);
1050 * For each 32-bit float element of rA and rB, choose the greater of the
1051 * two, compositing them into the rT register.
1053 * The logic is similar to that of spe_float_min() above; the only
1054 * difference is that the registers on spe_selb() have been reversed,
1055 * so that the larger of the two is selected instead of the smaller.
1058 spe_float_max(struct spe_function
*p
, unsigned rT
, unsigned rA
, unsigned rB
)
1060 unsigned int compare_reg
= spe_allocate_available_register(p
);
1061 spe_fcgt(p
, compare_reg
, rA
, rB
);
1062 spe_selb(p
, rT
, rB
, rA
, compare_reg
);
1063 spe_release_register(p
, compare_reg
);
1066 #endif /* GALLIUM_CELL */