src/gallium/auxiliary/rtasm/rtasm_ppc_spe.c

   1 /*
   2  * (C) Copyright IBM Corporation 2008
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  19  * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * \file
  27  * Real-time assembly generation interface for Cell B.E. SPEs.
  28  *
  29  * \author Ian Romanick <idr@us.ibm.com>
  30  * \author Brian Paul
  31  */
  32
  33
  34 #include <stdio.h>
  35 #include "pipe/p_compiler.h"
  36 #include "util/u_memory.h"
  37 #include "rtasm_ppc_spe.h"
  38
  39
  40 #ifdef GALLIUM_CELL
  41 /**
  42  * SPE instruction types
  43  *
  44  * There are 6 primary instruction encodings used on the Cell's SPEs.  Each of
  45  * the following unions encodes one type.
  46  *
  47  * \bug
  48  * If, at some point, we start generating SPE code from a little-endian host
  49  * these unions will not work.
  50  */
  51 /*@{*/
  52 /**
  53  * Encode one output register with two input registers
  54  */
  55 union spe_inst_RR {
  56     uint32_t bits;
  57     struct {
  58         unsigned op:11;
  59         unsigned rB:7;
  60         unsigned rA:7;
  61         unsigned rT:7;
  62     } inst;
  63 };
  64
  65
  66 /**
  67  * Encode one output register with three input registers
  68  */
  69 union spe_inst_RRR {
  70     uint32_t bits;
  71     struct {
  72         unsigned op:4;
  73         unsigned rT:7;
  74         unsigned rB:7;
  75         unsigned rA:7;
  76         unsigned rC:7;
  77     } inst;
  78 };
  79
  80
  81 /**
  82  * Encode one output register with one input reg. and a 7-bit signed immed
  83  */
  84 union spe_inst_RI7 {
  85     uint32_t bits;
  86     struct {
  87         unsigned op:11;
  88         unsigned i7:7;
  89         unsigned rA:7;
  90         unsigned rT:7;
  91     } inst;
  92 };
  93
  94
  95 /**
  96  * Encode one output register with one input reg. and an 8-bit signed immed
  97  */
  98 union spe_inst_RI8 {
  99     uint32_t bits;
 100     struct {
 101         unsigned op:10;
 102         unsigned i8:8;
 103         unsigned rA:7;
 104         unsigned rT:7;
 105     } inst;
 106 };
 107
 108
 109 /**
 110  * Encode one output register with one input reg. and a 10-bit signed immed
 111  */
 112 union spe_inst_RI10 {
 113     uint32_t bits;
 114     struct {
 115         unsigned op:8;
 116         unsigned i10:10;
 117         unsigned rA:7;
 118         unsigned rT:7;
 119     } inst;
 120 };
 121
 122
 123 /**
 124  * Encode one output register with a 16-bit signed immediate
 125  */
 126 union spe_inst_RI16 {
 127     uint32_t bits;
 128     struct {
 129         unsigned op:9;
 130         unsigned i16:16;
 131         unsigned rT:7;
 132     } inst;
 133 };
 134
 135
 136 /**
 137  * Encode one output register with a 18-bit signed immediate
 138  */
 139 union spe_inst_RI18 {
 140     uint32_t bits;
 141     struct {
 142         unsigned op:7;
 143         unsigned i18:18;
 144         unsigned rT:7;
 145     } inst;
 146 };
 147 /*@}*/
 148
 149
 150 static void
 151 indent(const struct spe_function *p)
 152 {
 153    int i;
 154    for (i = 0; i < p->indent; i++) {
 155       putchar(' ');
 156    }
 157 }
 158
 159
 160 static const char *
 161 rem_prefix(const char *longname)
 162 {
 163    return longname + 4;
 164 }
 165
 166
 167 static const char *
 168 reg_name(int reg)
 169 {
 170    switch (reg) {
 171    case SPE_REG_SP:
 172       return "$sp";
 173    case SPE_REG_RA:
 174       return "$lr";
 175    default:
 176       {
 177          /* cycle through four buffers to handle multiple calls per printf */
 178          static char buf[4][10];
 179          static int b = 0;
 180          b = (b + 1) % 4;
 181          sprintf(buf[b], "$%d", reg);
 182          return buf[b];
 183       }
 184    }
 185 }
 186
 187
 188 static void
 189 emit_instruction(struct spe_function *p, uint32_t inst_bits)
 190 {
 191    if (!p->store)
 192       return;  /* out of memory, drop the instruction */
 193
 194    if (p->num_inst == p->max_inst) {
 195       /* allocate larger buffer */
 196       uint32_t *newbuf;
 197       p->max_inst *= 2;  /* 2x larger */
 198       newbuf = align_malloc(p->max_inst * SPE_INST_SIZE, 16);
 199       if (newbuf) {
 200          memcpy(newbuf, p->store, p->num_inst * SPE_INST_SIZE);
 201       }
 202       align_free(p->store);
 203       p->store = newbuf;
 204       if (!p->store) {
 205          /* out of memory */
 206          p->num_inst = 0;
 207          return;
 208       }
 209    }
 210
 211    p->store[p->num_inst++] = inst_bits;
 212 }
 213
 214
 215
 216 static void emit_RR(struct spe_function *p, unsigned op, unsigned rT,
 217                     unsigned rA, unsigned rB, const char *name)
 218 {
 219     union spe_inst_RR inst;
 220     inst.inst.op = op;
 221     inst.inst.rB = rB;
 222     inst.inst.rA = rA;
 223     inst.inst.rT = rT;
 224     emit_instruction(p, inst.bits);
 225     if (p->print) {
 226        indent(p);
 227        printf("%s\t%s, %s, %s\n",
 228               rem_prefix(name), reg_name(rT), reg_name(rA), reg_name(rB));
 229     }
 230 }
 231
 232
 233 static void emit_RRR(struct spe_function *p, unsigned op, unsigned rT,
 234                      unsigned rA, unsigned rB, unsigned rC, const char *name)
 235 {
 236     union spe_inst_RRR inst;
 237     inst.inst.op = op;
 238     inst.inst.rT = rT;
 239     inst.inst.rB = rB;
 240     inst.inst.rA = rA;
 241     inst.inst.rC = rC;
 242     emit_instruction(p, inst.bits);
 243     if (p->print) {
 244        indent(p);
 245        printf("%s\t%s, %s, %s, %s\n", rem_prefix(name), reg_name(rT),
 246               reg_name(rA), reg_name(rB), reg_name(rC));
 247     }
 248 }
 249
 250
 251 static void emit_RI7(struct spe_function *p, unsigned op, unsigned rT,
 252                      unsigned rA, int imm, const char *name)
 253 {
 254     union spe_inst_RI7 inst;
 255     inst.inst.op = op;
 256     inst.inst.i7 = imm;
 257     inst.inst.rA = rA;
 258     inst.inst.rT = rT;
 259     emit_instruction(p, inst.bits);
 260     if (p->print) {
 261        indent(p);
 262        printf("%s\t%s, %s, 0x%x\n",
 263               rem_prefix(name), reg_name(rT), reg_name(rA), imm);
 264     }
 265 }
 266
 267
 268
 269 static void emit_RI8(struct spe_function *p, unsigned op, unsigned rT,
 270                      unsigned rA, int imm, const char *name)
 271 {
 272     union spe_inst_RI8 inst;
 273     inst.inst.op = op;
 274     inst.inst.i8 = imm;
 275     inst.inst.rA = rA;
 276     inst.inst.rT = rT;
 277     emit_instruction(p, inst.bits);
 278     if (p->print) {
 279        indent(p);
 280        printf("%s\t%s, %s, 0x%x\n",
 281               rem_prefix(name), reg_name(rT), reg_name(rA), imm);
 282     }
 283 }
 284
 285
 286
 287 static void emit_RI10(struct spe_function *p, unsigned op, unsigned rT,
 288                       unsigned rA, int imm, const char *name)
 289 {
 290     union spe_inst_RI10 inst;
 291     inst.inst.op = op;
 292     inst.inst.i10 = imm;
 293     inst.inst.rA = rA;
 294     inst.inst.rT = rT;
 295     emit_instruction(p, inst.bits);
 296     if (p->print) {
 297        indent(p);
 298        printf("%s\t%s, %s, 0x%x\n",
 299               rem_prefix(name), reg_name(rT), reg_name(rA), imm);
 300     }
 301 }
 302
 303
 304 /** As above, but do range checking on signed immediate value */
 305 static void emit_RI10s(struct spe_function *p, unsigned op, unsigned rT,
 306                        unsigned rA, int imm, const char *name)
 307 {
 308     assert(imm <= 511);
 309     assert(imm >= -512);
 310     emit_RI10(p, op, rT, rA, imm, name);
 311 }
 312
 313
 314 static void emit_RI16(struct spe_function *p, unsigned op, unsigned rT,
 315                       int imm, const char *name)
 316 {
 317     union spe_inst_RI16 inst;
 318     inst.inst.op = op;
 319     inst.inst.i16 = imm;
 320     inst.inst.rT = rT;
 321     emit_instruction(p, inst.bits);
 322     if (p->print) {
 323        indent(p);
 324        printf("%s\t%s, 0x%x\n", rem_prefix(name), reg_name(rT), imm);
 325     }
 326 }
 327
 328
 329 static void emit_RI18(struct spe_function *p, unsigned op, unsigned rT,
 330                       int imm, const char *name)
 331 {
 332     union spe_inst_RI18 inst;
 333     inst.inst.op = op;
 334     inst.inst.i18 = imm;
 335     inst.inst.rT = rT;
 336     emit_instruction(p, inst.bits);
 337     if (p->print) {
 338        indent(p);
 339        printf("%s\t%s, 0x%x\n", rem_prefix(name), reg_name(rT), imm);
 340     }
 341 }
 342
 343
 344
 345
 346 #define EMIT_(_name, _op) \
 347 void _name (struct spe_function *p, unsigned rT) \
 348 { \
 349    emit_RR(p, _op, rT, 0, 0, __FUNCTION__); \
 350 }
 351
 352 #define EMIT_R(_name, _op) \
 353 void _name (struct spe_function *p, unsigned rT, unsigned rA) \
 354 { \
 355    emit_RR(p, _op, rT, rA, 0, __FUNCTION__);                 \
 356 }
 357
 358 #define EMIT_RR(_name, _op) \
 359 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB) \
 360 { \
 361    emit_RR(p, _op, rT, rA, rB, __FUNCTION__);                \
 362 }
 363
 364 #define EMIT_RRR(_name, _op) \
 365 void _name (struct spe_function *p, unsigned rT, unsigned rA, unsigned rB, unsigned rC) \
 366 { \
 367    emit_RRR(p, _op, rT, rA, rB, rC, __FUNCTION__);           \
 368 }
 369
 370 #define EMIT_RI7(_name, _op) \
 371 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
 372 { \
 373    emit_RI7(p, _op, rT, rA, imm, __FUNCTION__);              \
 374 }
 375
 376 #define EMIT_RI8(_name, _op, bias) \
 377 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
 378 { \
 379    emit_RI8(p, _op, rT, rA, bias - imm, __FUNCTION__);       \
 380 }
 381
 382 #define EMIT_RI10(_name, _op) \
 383 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
 384 { \
 385    emit_RI10(p, _op, rT, rA, imm, __FUNCTION__);             \
 386 }
 387
 388 #define EMIT_RI10s(_name, _op) \
 389 void _name (struct spe_function *p, unsigned rT, unsigned rA, int imm) \
 390 { \
 391    emit_RI10s(p, _op, rT, rA, imm, __FUNCTION__);             \
 392 }
 393
 394 #define EMIT_RI16(_name, _op) \
 395 void _name (struct spe_function *p, unsigned rT, int imm) \
 396 { \
 397    emit_RI16(p, _op, rT, imm, __FUNCTION__);                 \
 398 }
 399
 400 #define EMIT_RI18(_name, _op) \
 401 void _name (struct spe_function *p, unsigned rT, int imm) \
 402 { \
 403    emit_RI18(p, _op, rT, imm, __FUNCTION__);                 \
 404 }
 405
 406 #define EMIT_I16(_name, _op) \
 407 void _name (struct spe_function *p, int imm) \
 408 { \
 409    emit_RI16(p, _op, 0, imm, __FUNCTION__);                  \
 410 }
 411
 412 #include "rtasm_ppc_spe.h"
 413
 414
 415
 416 /**
 417  * Initialize an spe_function.
 418  * \param code_size  initial size of instruction buffer to allocate, in bytes.
 419  *                   If zero, use a default.
 420  */
 421 void spe_init_func(struct spe_function *p, unsigned code_size)
 422 {
 423     unsigned int i;
 424
 425     if (!code_size)
 426        code_size = 64;
 427
 428     p->num_inst = 0;
 429     p->max_inst = code_size / SPE_INST_SIZE;
 430     p->store = align_malloc(code_size, 16);
 431
 432     p->set_count = 0;
 433     memset(p->regs, 0, SPE_NUM_REGS * sizeof(p->regs[0]));
 434
 435     /* Conservatively treat R0 - R2 and R80 - R127 as non-volatile.
 436      */
 437     p->regs[0] = p->regs[1] = p->regs[2] = 1;
 438     for (i = 80; i <= 127; i++) {
 439       p->regs[i] = 1;
 440     }
 441
 442     p->print = false;
 443     p->indent = 0;
 444 }
 445
 446
 447 void spe_release_func(struct spe_function *p)
 448 {
 449     assert(p->num_inst <= p->max_inst);
 450     if (p->store != NULL) {
 451         align_free(p->store);
 452     }
 453     p->store = NULL;
 454 }
 455
 456
 457 /** Return current code size in bytes. */
 458 unsigned spe_code_size(const struct spe_function *p)
 459 {
 460    return p->num_inst * SPE_INST_SIZE;
 461 }
 462
 463
 464 /**
 465  * Allocate a SPE register.
 466  * \return register index or -1 if none left.
 467  */
 468 int spe_allocate_available_register(struct spe_function *p)
 469 {
 470    unsigned i;
 471    for (i = 0; i < SPE_NUM_REGS; i++) {
 472       if (p->regs[i] == 0) {
 473          p->regs[i] = 1;
 474          return i;
 475       }
 476    }
 477
 478    return -1;
 479 }
 480
 481
 482 /**
 483  * Mark the given SPE register as "allocated".
 484  */
 485 int spe_allocate_register(struct spe_function *p, int reg)
 486 {
 487    assert(reg < SPE_NUM_REGS);
 488    assert(p->regs[reg] == 0);
 489    p->regs[reg] = 1;
 490    return reg;
 491 }
 492
 493
 494 /**
 495  * Mark the given SPE register as "unallocated".  Note that this should
 496  * only be used on registers allocated in the current register set; an
 497  * assertion will fail if an attempt is made to deallocate a register
 498  * allocated in an earlier register set.
 499  */
 500 void spe_release_register(struct spe_function *p, int reg)
 501 {
 502    assert(reg < SPE_NUM_REGS);
 503    assert(p->regs[reg] == 1);
 504
 505    p->regs[reg] = 0;
 506 }
 507
 508 /**
 509  * Start a new set of registers.  This can be called if
 510  * it will be difficult later to determine exactly what
 511  * registers were actually allocated during a code generation
 512  * sequence, and you really just want to deallocate all of them.
 513  */
 514 void spe_allocate_register_set(struct spe_function *p)
 515 {
 516    unsigned int i;
 517
 518    /* Keep track of the set count.  If it ever wraps around to 0,
 519     * we're in trouble.
 520     */
 521    p->set_count++;
 522    assert(p->set_count > 0);
 523
 524    /* Increment the allocation count of all registers currently
 525     * allocated.  Then any registers that are allocated in this set
 526     * will be the only ones with a count of 1; they'll all be released
 527     * when the register set is released.
 528     */
 529    for (i = 0; i < SPE_NUM_REGS; i++) {
 530       if (p->regs[i] > 0)
 531          p->regs[i]++;
 532    }
 533 }
 534
 535 void spe_release_register_set(struct spe_function *p)
 536 {
 537    unsigned int i;
 538
 539    /* If the set count drops below zero, we're in trouble. */
 540    assert(p->set_count > 0);
 541    p->set_count--;
 542
 543    /* Drop the allocation level of all registers.  Any allocated
 544     * during this register set will drop to 0 and then become
 545     * available.
 546     */
 547    for (i = 0; i < SPE_NUM_REGS; i++) {
 548       if (p->regs[i] > 0)
 549          p->regs[i]--;
 550    }
 551 }
 552
 553
 554 unsigned
 555 spe_get_registers_used(const struct spe_function *p, ubyte used[])
 556 {
 557    unsigned i, num = 0;
 558    /* only count registers in the range available to callers */
 559    for (i = 2; i < 80; i++) {
 560       if (p->regs[i]) {
 561          used[num++] = i;
 562       }
 563    }
 564    return num;
 565 }
 566
 567
 568 void
 569 spe_print_code(struct spe_function *p, boolean enable)
 570 {
 571    p->print = enable;
 572 }
 573
 574
 575 void
 576 spe_indent(struct spe_function *p, int spaces)
 577 {
 578    p->indent += spaces;
 579 }
 580
 581
 582 void
 583 spe_comment(struct spe_function *p, int rel_indent, const char *s)
 584 {
 585    if (p->print) {
 586       p->indent += rel_indent;
 587       indent(p);
 588       p->indent -= rel_indent;
 589       printf("# %s\n", s);
 590    }
 591 }
 592
 593
 594 /**
 595  * Load quad word.
 596  * NOTE: offset is in bytes and the least significant 4 bits must be zero!
 597  */
 598 void spe_lqd(struct spe_function *p, unsigned rT, unsigned rA, int offset)
 599 {
 600    const boolean pSave = p->print;
 601
 602    /* offset must be a multiple of 16 */
 603    assert(offset % 16 == 0);
 604    /* offset must fit in 10-bit signed int field, after shifting */
 605    assert((offset >> 4) <= 511);
 606    assert((offset >> 4) >= -512);
 607
 608    p->print = FALSE;
 609    emit_RI10(p, 0x034, rT, rA, offset >> 4, "spe_lqd");
 610    p->print = pSave;
 611
 612    if (p->print) {
 613       indent(p);
 614       printf("lqd\t%s, %d(%s)\n", reg_name(rT), offset, reg_name(rA));
 615    }
 616 }
 617
 618
 619 /**
 620  * Store quad word.
 621  * NOTE: offset is in bytes and the least significant 4 bits must be zero!
 622  */
 623 void spe_stqd(struct spe_function *p, unsigned rT, unsigned rA, int offset)
 624 {
 625    const boolean pSave = p->print;
 626
 627    /* offset must be a multiple of 16 */
 628    assert(offset % 16 == 0);
 629    /* offset must fit in 10-bit signed int field, after shifting */
 630    assert((offset >> 4) <= 511);
 631    assert((offset >> 4) >= -512);
 632
 633    p->print = FALSE;
 634    emit_RI10(p, 0x024, rT, rA, offset >> 4, "spe_stqd");
 635    p->print = pSave;
 636
 637    if (p->print) {
 638       indent(p);
 639       printf("stqd\t%s, %d(%s)\n", reg_name(rT), offset, reg_name(rA));
 640    }
 641 }
 642
 643
 644 /**
 645  * For branch instructions:
 646  * \param d  if 1, disable interupts if branch is taken
 647  * \param e  if 1, enable interupts if branch is taken
 648  * If d and e are both zero, don't change interupt status (right?)
 649  */
 650
 651 /** Branch Indirect to address in rA */
 652 void spe_bi(struct spe_function *p, unsigned rA, int d, int e)
 653 {
 654    emit_RI7(p, 0x1a8, 0, rA, (d << 5) | (e << 4), __FUNCTION__);
 655 }
 656
 657 /** Interupt Return */
 658 void spe_iret(struct spe_function *p, unsigned rA, int d, int e)
 659 {
 660    emit_RI7(p, 0x1aa, 0, rA, (d << 5) | (e << 4), __FUNCTION__);
 661 }
 662
 663 /** Branch indirect and set link on external data */
 664 void spe_bisled(struct spe_function *p, unsigned rT, unsigned rA, int d,
 665                 int e)
 666 {
 667    emit_RI7(p, 0x1ab, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
 668 }
 669
 670 /** Branch indirect and set link.  Save PC in rT, jump to rA. */
 671 void spe_bisl(struct spe_function *p, unsigned rT, unsigned rA, int d,
 672                 int e)
 673 {
 674    emit_RI7(p, 0x1a9, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
 675 }
 676
 677 /** Branch indirect if zero word.  If rT.word[0]==0, jump to rA. */
 678 void spe_biz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
 679 {
 680    emit_RI7(p, 0x128, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
 681 }
 682
 683 /** Branch indirect if non-zero word.  If rT.word[0]!=0, jump to rA. */
 684 void spe_binz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
 685 {
 686    emit_RI7(p, 0x129, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
 687 }
 688
 689 /** Branch indirect if zero halfword.  If rT.halfword[1]==0, jump to rA. */
 690 void spe_bihz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
 691 {
 692    emit_RI7(p, 0x12a, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
 693 }
 694
 695 /** Branch indirect if non-zero halfword.  If rT.halfword[1]!=0, jump to rA. */
 696 void spe_bihnz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e)
 697 {
 698    emit_RI7(p, 0x12b, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
 699 }
 700
 701
 702 /* Hint-for-branch instructions
 703  */
 704 #if 0
 705 hbr;
 706 hbra;
 707 hbrr;
 708 #endif
 709
 710
 711 /* Control instructions
 712  */
 713 #if 0
 714 stop;
 715 EMIT_RR  (spe_stopd, 0x140);
 716 EMIT_    (spe_lnop,  0x001);
 717 EMIT_    (spe_nop,   0x201);
 718 sync;
 719 EMIT_    (spe_dsync, 0x003);
 720 EMIT_R   (spe_mfspr, 0x00c);
 721 EMIT_R   (spe_mtspr, 0x10c);
 722 #endif
 723
 724
 725 /**
 726  ** Helper / "macro" instructions.
 727  ** Use somewhat verbose names as a reminder that these aren't native
 728  ** SPE instructions.
 729  **/
 730
 731
 732 void
 733 spe_load_float(struct spe_function *p, unsigned rT, float x)
 734 {
 735    if (x == 0.0f) {
 736       spe_il(p, rT, 0x0);
 737    }
 738    else if (x == 0.5f) {
 739       spe_ilhu(p, rT, 0x3f00);
 740    }
 741    else if (x == 1.0f) {
 742       spe_ilhu(p, rT, 0x3f80);
 743    }
 744    else if (x == -1.0f) {
 745       spe_ilhu(p, rT, 0xbf80);
 746    }
 747    else {
 748       union {
 749          float f;
 750          unsigned u;
 751       } bits;
 752       bits.f = x;
 753       spe_ilhu(p, rT, bits.u >> 16);
 754       spe_iohl(p, rT, bits.u & 0xffff);
 755    }
 756 }
 757
 758
 759 void
 760 spe_load_int(struct spe_function *p, unsigned rT, int i)
 761 {
 762    if (-32768 <= i && i <= 32767) {
 763       spe_il(p, rT, i);
 764    }
 765    else {
 766       spe_ilhu(p, rT, i >> 16);
 767       if (i & 0xffff)
 768          spe_iohl(p, rT, i & 0xffff);
 769    }
 770 }
 771
 772 void spe_load_uint(struct spe_function *p, unsigned rT, unsigned int ui)
 773 {
 774    /* If the whole value is in the lower 18 bits, use ila, which
 775     * doesn't sign-extend.  Otherwise, if the two halfwords of
 776     * the constant are identical, use ilh.  Otherwise, if every byte of
 777     * the desired value is 0x00 or 0xff, we can use Form Select Mask for
 778     * Bytes Immediate (fsmbi) to load the value in a single instruction.
 779     * Otherwise, in the general case, we have to use ilhu followed by iohl.
 780     */
 781    if ((ui & 0x0003ffff) == ui) {
 782       spe_ila(p, rT, ui);
 783    }
 784    else if ((ui >> 16) == (ui & 0xffff)) {
 785       spe_ilh(p, rT, ui & 0xffff);
 786    }
 787    else if (
 788       ((ui & 0x000000ff) == 0 || (ui & 0x000000ff) == 0x000000ff) &&
 789       ((ui & 0x0000ff00) == 0 || (ui & 0x0000ff00) == 0x0000ff00) &&
 790       ((ui & 0x00ff0000) == 0 || (ui & 0x00ff0000) == 0x00ff0000) &&
 791       ((ui & 0xff000000) == 0 || (ui & 0xff000000) == 0xff000000)
 792    ) {
 793       unsigned int mask = 0;
 794       /* fsmbi duplicates each bit in the given mask eight times,
 795        * using a 16-bit value to initialize a 16-byte quadword.
 796        * Each 4-bit nybble of the mask corresponds to a full word
 797        * of the result; look at the value and figure out the mask
 798        * (replicated for each word in the quadword), and then
 799        * form the "select mask" to get the value.
 800        */
 801       if ((ui & 0x000000ff) == 0x000000ff) mask |= 0x1111;
 802       if ((ui & 0x0000ff00) == 0x0000ff00) mask |= 0x2222;
 803       if ((ui & 0x00ff0000) == 0x00ff0000) mask |= 0x4444;
 804       if ((ui & 0xff000000) == 0xff000000) mask |= 0x8888;
 805       spe_fsmbi(p, rT, mask);
 806    }
 807    else {
 808       /* The general case: this usually uses two instructions, but
 809        * may use only one if the low-order 16 bits of each word are 0.
 810        */
 811       spe_ilhu(p, rT, ui >> 16);
 812       if (ui & 0xffff)
 813          spe_iohl(p, rT, ui & 0xffff);
 814    }
 815 }
 816
 817 /**
 818  * This function is constructed identically to spe_xor_uint() below.
 819  * Changes to one should be made in the other.
 820  */
 821 void
 822 spe_and_uint(struct spe_function *p, unsigned rT, unsigned rA, unsigned int ui)
 823 {
 824    /* If we can, emit a single instruction, either And Byte Immediate
 825     * (which uses the same constant across each byte), And Halfword Immediate
 826     * (which sign-extends a 10-bit immediate to 16 bits and uses that
 827     * across each halfword), or And Word Immediate (which sign-extends
 828     * a 10-bit immediate to 32 bits).
 829     *
 830     * Otherwise, we'll need to use a temporary register.
 831     */
 832    unsigned int tmp;
 833
 834    /* If the upper 23 bits are all 0s or all 1s, sign extension
 835     * will work and we can use And Word Immediate
 836     */
 837    tmp = ui & 0xfffffe00;
 838    if (tmp == 0xfffffe00 || tmp  == 0) {
 839       spe_andi(p, rT, rA, ui & 0x000003ff);
 840       return;
 841    }
 842
 843    /* If the ui field is symmetric along halfword boundaries and
 844     * the upper 7 bits of each halfword are all 0s or 1s, we
 845     * can use And Halfword Immediate
 846     */
 847    tmp = ui & 0xfe00fe00;
 848    if ((tmp == 0xfe00fe00 || tmp == 0) && ((ui >> 16) == (ui & 0x0000ffff))) {
 849       spe_andhi(p, rT, rA, ui & 0x000003ff);
 850       return;
 851    }
 852
 853    /* If the ui field is symmetric in each byte, then we can use
 854     * the And Byte Immediate instruction.
 855     */
 856    tmp = ui & 0x000000ff;
 857    if ((ui >> 24) == tmp && ((ui >> 16) & 0xff) == tmp && ((ui >> 8) & 0xff) == tmp) {
 858       spe_andbi(p, rT, rA, tmp);
 859       return;
 860    }
 861
 862    /* Otherwise, we'll have to use a temporary register. */
 863    unsigned int tmp_reg = spe_allocate_available_register(p);
 864    spe_load_uint(p, tmp_reg, ui);
 865    spe_and(p, rT, rA, tmp_reg);
 866    spe_release_register(p, tmp_reg);
 867 }
 868
 869
 870 /**
 871  * This function is constructed identically to spe_and_uint() above.
 872  * Changes to one should be made in the other.
 873  */
 874 void
 875 spe_xor_uint(struct spe_function *p, unsigned rT, unsigned rA, unsigned int ui)
 876 {
 877    /* If we can, emit a single instruction, either Exclusive Or Byte
 878     * Immediate (which uses the same constant across each byte), Exclusive
 879     * Or Halfword Immediate (which sign-extends a 10-bit immediate to
 880     * 16 bits and uses that across each halfword), or Exclusive Or Word
 881     * Immediate (which sign-extends a 10-bit immediate to 32 bits).
 882     *
 883     * Otherwise, we'll need to use a temporary register.
 884     */
 885    unsigned int tmp;
 886
 887    /* If the upper 23 bits are all 0s or all 1s, sign extension
 888     * will work and we can use Exclusive Or Word Immediate
 889     */
 890    tmp = ui & 0xfffffe00;
 891    if (tmp == 0xfffffe00 || tmp  == 0) {
 892       spe_xori(p, rT, rA, ui & 0x000003ff);
 893       return;
 894    }
 895
 896    /* If the ui field is symmetric along halfword boundaries and
 897     * the upper 7 bits of each halfword are all 0s or 1s, we
 898     * can use Exclusive Or Halfword Immediate
 899     */
 900    tmp = ui & 0xfe00fe00;
 901    if ((tmp == 0xfe00fe00 || tmp == 0) && ((ui >> 16) == (ui & 0x0000ffff))) {
 902       spe_xorhi(p, rT, rA, ui & 0x000003ff);
 903       return;
 904    }
 905
 906    /* If the ui field is symmetric in each byte, then we can use
 907     * the Exclusive Or Byte Immediate instruction.
 908     */
 909    tmp = ui & 0x000000ff;
 910    if ((ui >> 24) == tmp && ((ui >> 16) & 0xff) == tmp && ((ui >> 8) & 0xff) == tmp) {
 911       spe_xorbi(p, rT, rA, tmp);
 912       return;
 913    }
 914
 915    /* Otherwise, we'll have to use a temporary register. */
 916    unsigned int tmp_reg = spe_allocate_available_register(p);
 917    spe_load_uint(p, tmp_reg, ui);
 918    spe_xor(p, rT, rA, tmp_reg);
 919    spe_release_register(p, tmp_reg);
 920 }
 921
 922 void
 923 spe_compare_equal_uint(struct spe_function *p, unsigned rT, unsigned rA, unsigned int ui)
 924 {
 925    /* If the comparison value is 9 bits or less, it fits inside a
 926     * Compare Equal Word Immediate instruction.
 927     */
 928    if ((ui & 0x000001ff) == ui) {
 929       spe_ceqi(p, rT, rA, ui);
 930    }
 931    /* Otherwise, we're going to have to load a word first. */
 932    else {
 933       unsigned int tmp_reg = spe_allocate_available_register(p);
 934       spe_load_uint(p, tmp_reg, ui);
 935       spe_ceq(p, rT, rA, tmp_reg);
 936       spe_release_register(p, tmp_reg);
 937    }
 938 }
 939
 940 void
 941 spe_compare_greater_uint(struct spe_function *p, unsigned rT, unsigned rA, unsigned int ui)
 942 {
 943    /* If the comparison value is 10 bits or less, it fits inside a
 944     * Compare Logical Greater Than Word Immediate instruction.
 945     */
 946    if ((ui & 0x000003ff) == ui) {
 947       spe_clgti(p, rT, rA, ui);
 948    }
 949    /* Otherwise, we're going to have to load a word first. */
 950    else {
 951       unsigned int tmp_reg = spe_allocate_available_register(p);
 952       spe_load_uint(p, tmp_reg, ui);
 953       spe_clgt(p, rT, rA, tmp_reg);
 954       spe_release_register(p, tmp_reg);
 955    }
 956 }
 957
 958 void
 959 spe_splat(struct spe_function *p, unsigned rT, unsigned rA)
 960 {
 961    /* Use a temporary, just in case rT == rA */
 962    unsigned int tmp_reg = spe_allocate_available_register(p);
 963    /* Duplicate bytes 0, 1, 2, and 3 across the whole register */
 964    spe_ila(p, tmp_reg, 0x00010203);
 965    spe_shufb(p, rT, rA, rA, tmp_reg);
 966    spe_release_register(p, tmp_reg);
 967 }
 968
 969
 970 void
 971 spe_complement(struct spe_function *p, unsigned rT, unsigned rA)
 972 {
 973    spe_nor(p, rT, rA, rA);
 974 }
 975
 976
 977 void
 978 spe_move(struct spe_function *p, unsigned rT, unsigned rA)
 979 {
 980    /* Use different instructions depending on the instruction address
 981     * to take advantage of the dual pipelines.
 982     */
 983    if (p->num_inst & 1)
 984       spe_shlqbyi(p, rT, rA, 0);  /* odd pipe */
 985    else
 986       spe_ori(p, rT, rA, 0);  /* even pipe */
 987 }
 988
 989
 990 void
 991 spe_zero(struct spe_function *p, unsigned rT)
 992 {
 993    spe_xor(p, rT, rT, rT);
 994 }
 995
 996
 997 void
 998 spe_splat_word(struct spe_function *p, unsigned rT, unsigned rA, int word)
 999 {
1000    assert(word >= 0);
1001    assert(word <= 3);
1002
1003    if (word == 0) {
1004       int tmp1 = rT;
1005       spe_ila(p, tmp1, 66051);
1006       spe_shufb(p, rT, rA, rA, tmp1);
1007    }
1008    else {
1009       /* XXX review this, we may not need the rotqbyi instruction */
1010       int tmp1 = rT;
1011       int tmp2 = spe_allocate_available_register(p);
1012
1013       spe_ila(p, tmp1, 66051);
1014       spe_rotqbyi(p, tmp2, rA, 4 * word);
1015       spe_shufb(p, rT, tmp2, tmp2, tmp1);
1016
1017       spe_release_register(p, tmp2);
1018    }
1019 }
1020
1021 /**
1022  * For each 32-bit float element of rA and rB, choose the smaller of the
1023  * two, compositing them into the rT register.
1024  *
1025  * The Float Compare Greater Than (fcgt) instruction will put 1s into
1026  * compare_reg where rA > rB, and 0s where rA <= rB.
1027  *
1028  * Then the Select Bits (selb) instruction will take bits from rA where
1029  * compare_reg is 0, and from rB where compare_reg is 1; i.e., from rA
1030  * where rA <= rB and from rB where rB > rA, which is exactly the
1031  * "min" operation.
1032  *
1033  * The compare_reg could in many cases be the same as rT, unless
1034  * rT == rA || rt == rB.  But since this is common in constructions
1035  * like "x = min(x, a)", we always allocate a new register to be safe.
1036  */
1037 void
1038 spe_float_min(struct spe_function *p, unsigned rT, unsigned rA, unsigned rB)
1039 {
1040    unsigned int compare_reg = spe_allocate_available_register(p);
1041    spe_fcgt(p, compare_reg, rA, rB);
1042    spe_selb(p, rT, rA, rB, compare_reg);
1043    spe_release_register(p, compare_reg);
1044 }
1045
1046 /**
1047  * For each 32-bit float element of rA and rB, choose the greater of the
1048  * two, compositing them into the rT register.
1049  *
1050  * The logic is similar to that of spe_float_min() above; the only
1051  * difference is that the registers on spe_selb() have been reversed,
1052  * so that the larger of the two is selected instead of the smaller.
1053  */
1054 void
1055 spe_float_max(struct spe_function *p, unsigned rT, unsigned rA, unsigned rB)
1056 {
1057    unsigned int compare_reg = spe_allocate_available_register(p);
1058    spe_fcgt(p, compare_reg, rA, rB);
1059    spe_selb(p, rT, rB, rA, compare_reg);
1060    spe_release_register(p, compare_reg);
1061 }
1062
1063 #endif /* GALLIUM_CELL */