src/gallium/auxiliary/rtasm/rtasm_ppc_spe.h

   1 /*
   2  * (C) Copyright IBM Corporation 2008
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  19  * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * \file
  27  * Real-time assembly generation interface for Cell B.E. SPEs.
  28  * For details, see /opt/cell/sdk/docs/arch/SPU_ISA_v1.2_27Jan2007_pub.pdf
  29  *
  30  * \author Ian Romanick <idr@us.ibm.com>
  31  * \author Brian Paul
  32  */
  33
  34 #ifndef RTASM_PPC_SPE_H
  35 #define RTASM_PPC_SPE_H
  36
  37 /** 4 bytes per instruction */
  38 #define SPE_INST_SIZE 4
  39
  40 /** number of general-purpose SIMD registers */
  41 #define SPE_NUM_REGS  128
  42
  43 /** Return Address register */
  44 #define SPE_REG_RA  0
  45
  46 /** Stack Pointer register */
  47 #define SPE_REG_SP  1
  48
  49
  50 struct spe_function
  51 {
  52    uint32_t *store;  /**< instruction buffer */
  53    uint num_inst;
  54    uint max_inst;
  55
  56     /**
  57      * Mask of used / unused registers
  58      *
  59      * Each set bit corresponds to an available register.  Each cleared bit
  60      * corresponds to an allocated register.
  61      *
  62      * \sa
  63      * spe_allocate_register, spe_allocate_available_register,
  64      * spe_release_register
  65      */
  66     uint64_t regs[SPE_NUM_REGS / 64];
  67
  68     boolean print; /**< print/dump instructions as they're emitted? */
  69     int indent;    /**< number of spaces to indent */
  70 };
  71
  72
  73 extern void spe_init_func(struct spe_function *p, unsigned code_size);
  74 extern void spe_release_func(struct spe_function *p);
  75 extern unsigned spe_code_size(const struct spe_function *p);
  76
  77 extern int spe_allocate_available_register(struct spe_function *p);
  78 extern int spe_allocate_register(struct spe_function *p, int reg);
  79 extern void spe_release_register(struct spe_function *p, int reg);
  80
  81 extern void spe_print_code(struct spe_function *p, boolean enable);
  82 extern void spe_indent(struct spe_function *p, int spaces);
  83 extern void spe_comment(struct spe_function *p, int rel_indent, const char *s);
  84
  85
  86 #endif /* RTASM_PPC_SPE_H */
  87
  88 #ifndef EMIT_
  89 #define EMIT_(name, _op) \
  90     extern void _name (struct spe_function *p, unsigned rT)
  91 #define EMIT_R(_name, _op) \
  92     extern void _name (struct spe_function *p, unsigned rT, unsigned rA)
  93 #define EMIT_RR(_name, _op) \
  94     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
  95                            unsigned rB)
  96 #define EMIT_RRR(_name, _op) \
  97     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
  98                            unsigned rB, unsigned rC)
  99 #define EMIT_RI7(_name, _op) \
 100     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
 101                            int imm)
 102 #define EMIT_RI8(_name, _op, bias) \
 103     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
 104                            int imm)
 105 #define EMIT_RI10(_name, _op) \
 106     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
 107                            int imm)
 108 #define EMIT_RI16(_name, _op) \
 109     extern void _name (struct spe_function *p, unsigned rT, int imm)
 110 #define EMIT_RI18(_name, _op) \
 111     extern void _name (struct spe_function *p, unsigned rT, int imm)
 112 #define EMIT_I16(_name, _op) \
 113     extern void _name (struct spe_function *p, int imm)
 114 #define UNDEF_EMIT_MACROS
 115 #endif /* EMIT_ */
 116
 117
 118 /* Memory load / store instructions
 119  */
 120 EMIT_RI10(spe_lqd,  0x034);
 121 EMIT_RR  (spe_lqx,  0x1c4);
 122 EMIT_RI16(spe_lqa,  0x061);
 123 EMIT_RI16(spe_lqr,  0x067);
 124 EMIT_RI10(spe_stqd, 0x024);
 125 EMIT_RR  (spe_stqx, 0x144);
 126 EMIT_RI16(spe_stqa, 0x041);
 127 EMIT_RI16(spe_stqr, 0x047);
 128 EMIT_RI7 (spe_cbd,  0x1f4);
 129 EMIT_RR  (spe_cbx,  0x1d4);
 130 EMIT_RI7 (spe_chd,  0x1f5);
 131 EMIT_RI7 (spe_chx,  0x1d5);
 132 EMIT_RI7 (spe_cwd,  0x1f6);
 133 EMIT_RI7 (spe_cwx,  0x1d6);
 134 EMIT_RI7 (spe_cdd,  0x1f7);
 135 EMIT_RI7 (spe_cdx,  0x1d7);
 136
 137
 138 /* Constant formation instructions
 139  */
 140 EMIT_RI16(spe_ilh,   0x083);
 141 EMIT_RI16(spe_ilhu,  0x082);
 142 EMIT_RI16(spe_il,    0x081);
 143 EMIT_RI18(spe_ila,   0x021);
 144 EMIT_RI16(spe_iohl,  0x0c1);
 145 EMIT_RI16(spe_fsmbi, 0x065);
 146
 147
 148
 149 /* Integer and logical instructions
 150  */
 151 EMIT_RR  (spe_ah,      0x0c8);
 152 EMIT_RI10(spe_ahi,     0x01d);
 153 EMIT_RR  (spe_a,       0x0c0);
 154 EMIT_RI10(spe_ai,      0x01c);
 155 EMIT_RR  (spe_sfh,     0x048);
 156 EMIT_RI10(spe_sfhi,    0x00d);
 157 EMIT_RR  (spe_sf,      0x040);
 158 EMIT_RI10(spe_sfi,     0x00c);
 159 EMIT_RR  (spe_addx,    0x340);
 160 EMIT_RR  (spe_cg,      0x0c2);
 161 EMIT_RR  (spe_cgx,     0x342);
 162 EMIT_RR  (spe_sfx,     0x341);
 163 EMIT_RR  (spe_bg,      0x042);
 164 EMIT_RR  (spe_bgx,     0x343);
 165 EMIT_RR  (spe_mpy,     0x3c4);
 166 EMIT_RR  (spe_mpyu,    0x3cc);
 167 EMIT_RI10(spe_mpyi,    0x074);
 168 EMIT_RI10(spe_mpyui,   0x075);
 169 EMIT_RRR (spe_mpya,    0x00c);
 170 EMIT_RR  (spe_mpyh,    0x3c5);
 171 EMIT_RR  (spe_mpys,    0x3c7);
 172 EMIT_RR  (spe_mpyhh,   0x3c6);
 173 EMIT_RR  (spe_mpyhha,  0x346);
 174 EMIT_RR  (spe_mpyhhu,  0x3ce);
 175 EMIT_RR  (spe_mpyhhau, 0x34e);
 176 EMIT_R   (spe_clz,     0x2a5);
 177 EMIT_R   (spe_cntb,    0x2b4);
 178 EMIT_R   (spe_fsmb,    0x1b6);
 179 EMIT_R   (spe_fsmh,    0x1b5);
 180 EMIT_R   (spe_fsm,     0x1b4);
 181 EMIT_R   (spe_gbb,     0x1b2);
 182 EMIT_R   (spe_gbh,     0x1b1);
 183 EMIT_R   (spe_gb,      0x1b0);
 184 EMIT_RR  (spe_avgb,    0x0d3);
 185 EMIT_RR  (spe_absdb,   0x053);
 186 EMIT_RR  (spe_sumb,    0x253);
 187 EMIT_R   (spe_xsbh,    0x2b6);
 188 EMIT_R   (spe_xshw,    0x2ae);
 189 EMIT_R   (spe_xswd,    0x2a6);
 190 EMIT_RR  (spe_and,     0x0c1);
 191 EMIT_RR  (spe_andc,    0x2c1);
 192 EMIT_RI10(spe_andbi,   0x016);
 193 EMIT_RI10(spe_andhi,   0x015);
 194 EMIT_RI10(spe_andi,    0x014);
 195 EMIT_RR  (spe_or,      0x041);
 196 EMIT_RR  (spe_orc,     0x2c9);
 197 EMIT_RI10(spe_orbi,    0x006);
 198 EMIT_RI10(spe_orhi,    0x005);
 199 EMIT_RI10(spe_ori,     0x004);
 200 EMIT_R   (spe_orx,     0x1f0);
 201 EMIT_RR  (spe_xor,     0x241);
 202 EMIT_RI10(spe_xorbi,   0x026);
 203 EMIT_RI10(spe_xorhi,   0x025);
 204 EMIT_RI10(spe_xori,    0x024);
 205 EMIT_RR  (spe_nand,    0x0c9);
 206 EMIT_RR  (spe_nor,     0x049);
 207 EMIT_RR  (spe_eqv,     0x249);
 208 EMIT_RRR (spe_selb,    0x008);
 209 EMIT_RRR (spe_shufb,   0x00b);
 210
 211
 212 /* Shift and rotate instructions
 213  */
 214 EMIT_RR  (spe_shlh,      0x05f);
 215 EMIT_RI7 (spe_shlhi,     0x07f);
 216 EMIT_RR  (spe_shl,       0x05b);
 217 EMIT_RI7 (spe_shli,      0x07b);
 218 EMIT_RR  (spe_shlqbi,    0x1db);
 219 EMIT_RI7 (spe_shlqbii,   0x1fb);
 220 EMIT_RR  (spe_shlqby,    0x1df);
 221 EMIT_RI7 (spe_shlqbyi,   0x1ff);
 222 EMIT_RR  (spe_shlqbybi,  0x1cf);
 223 EMIT_RR  (spe_roth,      0x05c);
 224 EMIT_RI7 (spe_rothi,     0x07c);
 225 EMIT_RR  (spe_rot,       0x058);
 226 EMIT_RI7 (spe_roti,      0x078);
 227 EMIT_RR  (spe_rotqby,    0x1dc);
 228 EMIT_RI7 (spe_rotqbyi,   0x1fc);
 229 EMIT_RR  (spe_rotqbybi,  0x1cc);
 230 EMIT_RR  (spe_rotqbi,    0x1d8);
 231 EMIT_RI7 (spe_rotqbii,   0x1f8);
 232 EMIT_RR  (spe_rothm,     0x05d);
 233 EMIT_RI7 (spe_rothmi,    0x07d);
 234 EMIT_RR  (spe_rotm,      0x059);
 235 EMIT_RI7 (spe_rotmi,     0x079);
 236 EMIT_RR  (spe_rotqmby,   0x1dd);
 237 EMIT_RI7 (spe_rotqmbyi,  0x1fd);
 238 EMIT_RR  (spe_rotqmbybi, 0x1cd);
 239 EMIT_RR  (spe_rotqmbi,   0x1c9);
 240 EMIT_RI7 (spe_rotqmbii,  0x1f9);
 241 EMIT_RR  (spe_rotmah,    0x05e);
 242 EMIT_RI7 (spe_rotmahi,   0x07e);
 243 EMIT_RR  (spe_rotma,     0x05a);
 244 EMIT_RI7 (spe_rotmai,    0x07a);
 245
 246
 247 /* Compare, branch, and halt instructions
 248  */
 249 EMIT_RR  (spe_heq,       0x3d8);
 250 EMIT_RI10(spe_heqi,      0x07f);
 251 EMIT_RR  (spe_hgt,       0x258);
 252 EMIT_RI10(spe_hgti,      0x04f);
 253 EMIT_RR  (spe_hlgt,      0x2d8);
 254 EMIT_RI10(spe_hlgti,     0x05f);
 255 EMIT_RR  (spe_ceqb,      0x3d0);
 256 EMIT_RI10(spe_ceqbi,     0x07e);
 257 EMIT_RR  (spe_ceqh,      0x3c8);
 258 EMIT_RI10(spe_ceqhi,     0x07d);
 259 EMIT_RR  (spe_ceq,       0x3c0);
 260 EMIT_RI10(spe_ceqi,      0x07c);
 261 EMIT_RR  (spe_cgtb,      0x250);
 262 EMIT_RI10(spe_cgtbi,     0x04e);
 263 EMIT_RR  (spe_cgth,      0x248);
 264 EMIT_RI10(spe_cgthi,     0x04d);
 265 EMIT_RR  (spe_cgt,       0x240);
 266 EMIT_RI10(spe_cgti,      0x04c);
 267 EMIT_RR  (spe_clgtb,     0x2d0);
 268 EMIT_RI10(spe_clgtbi,    0x05e);
 269 EMIT_RR  (spe_clgth,     0x2c8);
 270 EMIT_RI10(spe_clgthi,    0x05d);
 271 EMIT_RR  (spe_clgt,      0x2c0);
 272 EMIT_RI10(spe_clgti,     0x05c);
 273 EMIT_I16 (spe_br,        0x064);
 274 EMIT_I16 (spe_bra,       0x060);
 275 EMIT_RI16(spe_brsl,      0x066);
 276 EMIT_RI16(spe_brasl,     0x062);
 277 EMIT_RI16(spe_brnz,      0x042);
 278 EMIT_RI16(spe_brz,       0x040);
 279 EMIT_RI16(spe_brhnz,     0x046);
 280 EMIT_RI16(spe_brhz,      0x044);
 281
 282 extern void spe_bi(struct spe_function *p, unsigned rA, int d, int e);
 283 extern void spe_iret(struct spe_function *p, unsigned rA, int d, int e);
 284 extern void spe_bisled(struct spe_function *p, unsigned rT, unsigned rA,
 285     int d, int e);
 286 extern void spe_bisl(struct spe_function *p, unsigned rT, unsigned rA,
 287     int d, int e);
 288 extern void spe_biz(struct spe_function *p, unsigned rT, unsigned rA,
 289     int d, int e);
 290 extern void spe_binz(struct spe_function *p, unsigned rT, unsigned rA,
 291     int d, int e);
 292 extern void spe_bihz(struct spe_function *p, unsigned rT, unsigned rA,
 293     int d, int e);
 294 extern void spe_bihnz(struct spe_function *p, unsigned rT, unsigned rA,
 295     int d, int e);
 296
 297
 298 /** Load/splat immediate float into rT. */
 299 extern void
 300 spe_load_float(struct spe_function *p, unsigned rT, float x);
 301
 302 /** Load/splat immediate int into rT. */
 303 extern void
 304 spe_load_int(struct spe_function *p, unsigned rT, int i);
 305
 306 /** Load/splat immediate unsigned int into rT. */
 307 extern void
 308 spe_load_uint(struct spe_function *p, unsigned rT, unsigned int ui);
 309
 310 /** Replicate word 0 of rA across rT. */
 311 extern void
 312 spe_splat(struct spe_function *p, unsigned rT, unsigned rA);
 313
 314 /** rT = complement_all_bits(rA). */
 315 extern void
 316 spe_complement(struct spe_function *p, unsigned rT, unsigned rA);
 317
 318 /** rT = rA. */
 319 extern void
 320 spe_move(struct spe_function *p, unsigned rT, unsigned rA);
 321
 322 /** rT = {0,0,0,0}. */
 323 extern void
 324 spe_zero(struct spe_function *p, unsigned rT);
 325
 326 /** rT = splat(rA, word) */
 327 extern void
 328 spe_splat_word(struct spe_function *p, unsigned rT, unsigned rA, int word);
 329
 330 /** rT = float min(rA, rB) */
 331 extern void
 332 spe_float_min(struct spe_function *p, unsigned rT, unsigned rA, unsigned rB);
 333
 334 /** rT = float max(rA, rB) */
 335 extern void
 336 spe_float_max(struct spe_function *p, unsigned rT, unsigned rA, unsigned rB);
 337
 338
 339 /* Floating-point instructions
 340  */
 341 EMIT_RR  (spe_fa,         0x2c4);
 342 EMIT_RR  (spe_dfa,        0x2cc);
 343 EMIT_RR  (spe_fs,         0x2c5);
 344 EMIT_RR  (spe_dfs,        0x2cd);
 345 EMIT_RR  (spe_fm,         0x2c6);
 346 EMIT_RR  (spe_dfm,        0x2ce);
 347 EMIT_RRR (spe_fma,        0x00e);
 348 EMIT_RR  (spe_dfma,       0x35c);
 349 EMIT_RRR (spe_fnms,       0x00d);
 350 EMIT_RR  (spe_dfnms,      0x35e);
 351 EMIT_RRR (spe_fms,        0x00f);
 352 EMIT_RR  (spe_dfms,       0x35d);
 353 EMIT_RR  (spe_dfnma,      0x35f);
 354 EMIT_R   (spe_frest,      0x1b8);
 355 EMIT_R   (spe_frsqest,    0x1b9);
 356 EMIT_RR  (spe_fi,         0x3d4);
 357 EMIT_RI8 (spe_csflt,      0x1da, 155);
 358 EMIT_RI8 (spe_cflts,      0x1d8, 173);
 359 EMIT_RI8 (spe_cuflt,      0x1db, 155);
 360 EMIT_RI8 (spe_cfltu,      0x1d9, 173);
 361 EMIT_R   (spe_frds,       0x3b9);
 362 EMIT_R   (spe_fesd,       0x3b8);
 363 EMIT_RR  (spe_dfceq,      0x3c3);
 364 EMIT_RR  (spe_dfcmeq,     0x3cb);
 365 EMIT_RR  (spe_dfcgt,      0x2c3);
 366 EMIT_RR  (spe_dfcmgt,     0x2cb);
 367 EMIT_RI7 (spe_dftsv,      0x3bf);
 368 EMIT_RR  (spe_fceq,       0x3c2);
 369 EMIT_RR  (spe_fcmeq,      0x3ca);
 370 EMIT_RR  (spe_fcgt,       0x2c2);
 371 EMIT_RR  (spe_fcmgt,      0x2ca);
 372 EMIT_R   (spe_fscrwr,     0x3ba);
 373 EMIT_    (spe_fscrrd,     0x398);
 374
 375
 376 /* Channel instructions
 377  */
 378 EMIT_R   (spe_rdch,       0x00d);
 379 EMIT_R   (spe_rdchcnt,    0x00f);
 380 EMIT_R   (spe_wrch,       0x10d);
 381
 382
 383 #ifdef UNDEF_EMIT_MACROS
 384 #undef EMIT_
 385 #undef EMIT_R
 386 #undef EMIT_RR
 387 #undef EMIT_RRR
 388 #undef EMIT_RI7
 389 #undef EMIT_RI8
 390 #undef EMIT_RI10
 391 #undef EMIT_RI16
 392 #undef EMIT_RI18
 393 #undef EMIT_I16
 394 #undef UNDEF_EMIT_MACROS
 395 #endif /* EMIT_ */