src/gallium/auxiliary/rtasm/rtasm_ppc_spe.h

   1 /*
   2  * (C) Copyright IBM Corporation 2008
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  19  * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * \file
  27  * Real-time assembly generation interface for Cell B.E. SPEs.
  28  * For details, see /opt/cell/sdk/docs/arch/SPU_ISA_v1.2_27Jan2007_pub.pdf
  29  *
  30  * \author Ian Romanick <idr@us.ibm.com>
  31  */
  32
  33 #ifndef RTASM_PPC_SPE_H
  34 #define RTASM_PPC_SPE_H
  35
  36 /** 4 bytes per instruction */
  37 #define SPE_INST_SIZE 4
  38
  39 /** number of general-purpose SIMD registers */
  40 #define SPE_NUM_REGS  128
  41
  42 /** Return Address register */
  43 #define SPE_REG_RA  0
  44
  45 /** Stack Pointer register */
  46 #define SPE_REG_SP  1
  47
  48
  49 struct spe_function
  50 {
  51    uint32_t *store;  /**< instruction buffer */
  52    uint num_inst;
  53    uint max_inst;
  54
  55     /**
  56      * Mask of used / unused registers
  57      *
  58      * Each set bit corresponds to an available register.  Each cleared bit
  59      * corresponds to an allocated register.
  60      *
  61      * \sa
  62      * spe_allocate_register, spe_allocate_available_register,
  63      * spe_release_register
  64      */
  65     uint64_t regs[SPE_NUM_REGS / 64];
  66 };
  67
  68 extern void spe_init_func(struct spe_function *p, unsigned code_size);
  69 extern void spe_release_func(struct spe_function *p);
  70
  71 extern int spe_allocate_available_register(struct spe_function *p);
  72 extern int spe_allocate_register(struct spe_function *p, int reg);
  73 extern void spe_release_register(struct spe_function *p, int reg);
  74
  75 #endif /* RTASM_PPC_SPE_H */
  76
  77 #ifndef EMIT_
  78 #define EMIT_(name, _op) \
  79     extern void _name (struct spe_function *p, unsigned rT)
  80 #define EMIT_R(_name, _op) \
  81     extern void _name (struct spe_function *p, unsigned rT, unsigned rA)
  82 #define EMIT_RR(_name, _op) \
  83     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
  84                            unsigned rB)
  85 #define EMIT_RRR(_name, _op) \
  86     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
  87                            unsigned rB, unsigned rC)
  88 #define EMIT_RI7(_name, _op) \
  89     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
  90                            int imm)
  91 #define EMIT_RI8(_name, _op, bias) \
  92     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
  93                            int imm)
  94 #define EMIT_RI10(_name, _op) \
  95     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
  96                            int imm)
  97 #define EMIT_RI16(_name, _op) \
  98     extern void _name (struct spe_function *p, unsigned rT, int imm)
  99 #define EMIT_RI18(_name, _op) \
 100     extern void _name (struct spe_function *p, unsigned rT, int imm)
 101 #define EMIT_I16(_name, _op) \
 102     extern void _name (struct spe_function *p, int imm)
 103 #define UNDEF_EMIT_MACROS
 104 #endif /* EMIT_ */
 105
 106
 107 /* Memory load / store instructions
 108  */
 109 EMIT_RI10(spe_lqd,  0x034);
 110 EMIT_RR  (spe_lqx,  0x1c4);
 111 EMIT_RI16(spe_lqa,  0x061);
 112 EMIT_RI16(spe_lqr,  0x067);
 113 EMIT_RI10(spe_stqd, 0x024);
 114 EMIT_RR  (spe_stqx, 0x144);
 115 EMIT_RI16(spe_stqa, 0x041);
 116 EMIT_RI16(spe_stqr, 0x047);
 117 EMIT_RI7 (spe_cbd,  0x1f4);
 118 EMIT_RR  (spe_cbx,  0x1d4);
 119 EMIT_RI7 (spe_chd,  0x1f5);
 120 EMIT_RI7 (spe_chx,  0x1d5);
 121 EMIT_RI7 (spe_cwd,  0x1f6);
 122 EMIT_RI7 (spe_cwx,  0x1d6);
 123 EMIT_RI7 (spe_cdd,  0x1f7);
 124 EMIT_RI7 (spe_cdx,  0x1d7);
 125
 126
 127 /* Constant formation instructions
 128  */
 129 EMIT_RI16(spe_ilh,   0x083);
 130 EMIT_RI16(spe_ilhu,  0x082);
 131 EMIT_RI16(spe_il,    0x081);
 132 EMIT_RI18(spe_ila,   0x021);
 133 EMIT_RI16(spe_iohl,  0x0c1);
 134 EMIT_RI16(spe_fsmbi, 0x065);
 135
 136
 137
 138 /* Integer and logical instructions
 139  */
 140 EMIT_RR  (spe_ah,      0x0c8);
 141 EMIT_RI10(spe_ahi,     0x01d);
 142 EMIT_RR  (spe_a,       0x0c0);
 143 EMIT_RI10(spe_ai,      0x01c);
 144 EMIT_RR  (spe_sfh,     0x048);
 145 EMIT_RI10(spe_sfhi,    0x00d);
 146 EMIT_RR  (spe_sf,      0x040);
 147 EMIT_RI10(spe_sfi,     0x00c);
 148 EMIT_RR  (spe_addx,    0x340);
 149 EMIT_RR  (spe_cg,      0x0c2);
 150 EMIT_RR  (spe_cgx,     0x342);
 151 EMIT_RR  (spe_sfx,     0x341);
 152 EMIT_RR  (spe_bg,      0x042);
 153 EMIT_RR  (spe_bgx,     0x343);
 154 EMIT_RR  (spe_mpy,     0x3c4);
 155 EMIT_RR  (spe_mpyu,    0x3cc);
 156 EMIT_RI10(spe_mpyi,    0x074);
 157 EMIT_RI10(spe_mpyui,   0x075);
 158 EMIT_RRR (spe_mpya,    0x00c);
 159 EMIT_RR  (spe_mpyh,    0x3c5);
 160 EMIT_RR  (spe_mpys,    0x3c7);
 161 EMIT_RR  (spe_mpyhh,   0x3c6);
 162 EMIT_RR  (spe_mpyhha,  0x346);
 163 EMIT_RR  (spe_mpyhhu,  0x3ce);
 164 EMIT_RR  (spe_mpyhhau, 0x34e);
 165 EMIT_R   (spe_clz,     0x2a5);
 166 EMIT_R   (spe_cntb,    0x2b4);
 167 EMIT_R   (spe_fsmb,    0x1b6);
 168 EMIT_R   (spe_fsmh,    0x1b5);
 169 EMIT_R   (spe_fsm,     0x1b4);
 170 EMIT_R   (spe_gbb,     0x1b2);
 171 EMIT_R   (spe_gbh,     0x1b1);
 172 EMIT_R   (spe_gb,      0x1b0);
 173 EMIT_RR  (spe_avgb,    0x0d3);
 174 EMIT_RR  (spe_absdb,   0x053);
 175 EMIT_RR  (spe_sumb,    0x253);
 176 EMIT_R   (spe_xsbh,    0x2b6);
 177 EMIT_R   (spe_xshw,    0x2ae);
 178 EMIT_R   (spe_xswd,    0x2a6);
 179 EMIT_RR  (spe_and,     0x0c1);
 180 EMIT_RR  (spe_andc,    0x2c1);
 181 EMIT_RI10(spe_andbi,   0x016);
 182 EMIT_RI10(spe_andhi,   0x015);
 183 EMIT_RI10(spe_andi,    0x014);
 184 EMIT_RR  (spe_or,      0x041);
 185 EMIT_RR  (spe_orc,     0x2c9);
 186 EMIT_RI10(spe_orbi,    0x006);
 187 EMIT_RI10(spe_orhi,    0x005);
 188 EMIT_RI10(spe_ori,     0x004);
 189 EMIT_R   (spe_orx,     0x1f0);
 190 EMIT_RR  (spe_xor,     0x241);
 191 EMIT_RI10(spe_xorbi,   0x026);
 192 EMIT_RI10(spe_xorhi,   0x025);
 193 EMIT_RI10(spe_xori,    0x024);
 194 EMIT_RR  (spe_nand,    0x0c9);
 195 EMIT_RR  (spe_nor,     0x049);
 196 EMIT_RR  (spe_eqv,     0x249);
 197 EMIT_RRR (spe_selb,    0x008);
 198 EMIT_RRR (spe_shufb,   0x00b);
 199
 200
 201 /* Shift and rotate instructions
 202  */
 203 EMIT_RR  (spe_shlh,      0x05f);
 204 EMIT_RI7 (spe_shlhi,     0x07f);
 205 EMIT_RR  (spe_shl,       0x05b);
 206 EMIT_RI7 (spe_shli,      0x07b);
 207 EMIT_RR  (spe_shlqbi,    0x1db);
 208 EMIT_RI7 (spe_shlqbii,   0x1fb);
 209 EMIT_RR  (spe_shlqby,    0x1df);
 210 EMIT_RI7 (spe_shlqbyi,   0x1ff);
 211 EMIT_RR  (spe_shlqbybi,  0x1cf);
 212 EMIT_RR  (spe_roth,      0x05c);
 213 EMIT_RI7 (spe_rothi,     0x07c);
 214 EMIT_RR  (spe_rot,       0x058);
 215 EMIT_RI7 (spe_roti,      0x078);
 216 EMIT_RR  (spe_rotqby,    0x1dc);
 217 EMIT_RI7 (spe_rotqbyi,   0x1fc);
 218 EMIT_RR  (spe_rotqbybi,  0x1cc);
 219 EMIT_RR  (spe_rotqbi,    0x1d8);
 220 EMIT_RI7 (spe_rotqbii,   0x1f8);
 221 EMIT_RR  (spe_rothm,     0x05d);
 222 EMIT_RI7 (spe_rothmi,    0x07d);
 223 EMIT_RR  (spe_rotm,      0x059);
 224 EMIT_RI7 (spe_rotmi,     0x079);
 225 EMIT_RR  (spe_rotqmby,   0x1dd);
 226 EMIT_RI7 (spe_rotqmbyi,  0x1fd);
 227 EMIT_RR  (spe_rotqmbybi, 0x1cd);
 228 EMIT_RR  (spe_rotqmbi,   0x1c9);
 229 EMIT_RI7 (spe_rotqmbii,  0x1f9);
 230 EMIT_RR  (spe_rotmah,    0x05e);
 231 EMIT_RI7 (spe_rotmahi,   0x07e);
 232 EMIT_RR  (spe_rotma,     0x05a);
 233 EMIT_RI7 (spe_rotmai,    0x07a);
 234
 235
 236 /* Compare, branch, and halt instructions
 237  */
 238 EMIT_RR  (spe_heq,       0x3d8);
 239 EMIT_RI10(spe_heqi,      0x07f);
 240 EMIT_RR  (spe_hgt,       0x258);
 241 EMIT_RI10(spe_hgti,      0x04f);
 242 EMIT_RR  (spe_hlgt,      0x2d8);
 243 EMIT_RI10(spe_hlgti,     0x05f);
 244 EMIT_RR  (spe_ceqb,      0x3d0);
 245 EMIT_RI10(spe_ceqbi,     0x07e);
 246 EMIT_RR  (spe_ceqh,      0x3c8);
 247 EMIT_RI10(spe_ceqhi,     0x07d);
 248 EMIT_RR  (spe_ceq,       0x3c0);
 249 EMIT_RI10(spe_ceqi,      0x07c);
 250 EMIT_RR  (spe_cgtb,      0x250);
 251 EMIT_RI10(spe_cgtbi,     0x04e);
 252 EMIT_RR  (spe_cgth,      0x248);
 253 EMIT_RI10(spe_cgthi,     0x04d);
 254 EMIT_RR  (spe_cgt,       0x240);
 255 EMIT_RI10(spe_cgti,      0x04c);
 256 EMIT_RR  (spe_clgtb,     0x2d0);
 257 EMIT_RI10(spe_clgtbi,    0x05e);
 258 EMIT_RR  (spe_clgth,     0x2c8);
 259 EMIT_RI10(spe_clgthi,    0x05d);
 260 EMIT_RR  (spe_clgt,      0x2c0);
 261 EMIT_RI10(spe_clgti,     0x05c);
 262 EMIT_I16 (spe_br,        0x064);
 263 EMIT_I16 (spe_bra,       0x060);
 264 EMIT_RI16(spe_brsl,      0x066);
 265 EMIT_RI16(spe_brasl,     0x062);
 266 EMIT_RI16(spe_brnz,      0x042);
 267 EMIT_RI16(spe_brz,       0x040);
 268 EMIT_RI16(spe_brhnz,     0x046);
 269 EMIT_RI16(spe_brhz,      0x044);
 270
 271 extern void spe_bi(struct spe_function *p, unsigned rA, int d, int e);
 272 extern void spe_iret(struct spe_function *p, unsigned rA, int d, int e);
 273 extern void spe_bisled(struct spe_function *p, unsigned rT, unsigned rA,
 274     int d, int e);
 275 extern void spe_bisl(struct spe_function *p, unsigned rT, unsigned rA,
 276     int d, int e);
 277 extern void spe_biz(struct spe_function *p, unsigned rT, unsigned rA,
 278     int d, int e);
 279 extern void spe_binz(struct spe_function *p, unsigned rT, unsigned rA,
 280     int d, int e);
 281 extern void spe_bihz(struct spe_function *p, unsigned rT, unsigned rA,
 282     int d, int e);
 283 extern void spe_bihnz(struct spe_function *p, unsigned rT, unsigned rA,
 284     int d, int e);
 285
 286
 287 /** Load/splat immediate float into rT. */
 288 extern void
 289 spe_load_float(struct spe_function *p, unsigned rT, float x);
 290
 291 /** Load/splat immediate int into rT. */
 292 extern void
 293 spe_load_int(struct spe_function *p, unsigned rT, int i);
 294
 295 /** Replicate word 0 of rA across rT. */
 296 extern void
 297 spe_splat(struct spe_function *p, unsigned rT, unsigned rA);
 298
 299 /** Complement/invert all bits in rT. */
 300 extern void
 301 spe_complement(struct spe_function *p, unsigned rT);
 302
 303 /** rT = rA. */
 304 extern void
 305 spe_move(struct spe_function *p, unsigned rT, unsigned rA);
 306
 307 /** rT = {0,0,0,0}. */
 308 extern void
 309 spe_zero(struct spe_function *p, unsigned rT);
 310
 311
 312 /* Floating-point instructions
 313  */
 314 EMIT_RR  (spe_fa,         0x2c4);
 315 EMIT_RR  (spe_dfa,        0x2cc);
 316 EMIT_RR  (spe_fs,         0x2c5);
 317 EMIT_RR  (spe_dfs,        0x2cd);
 318 EMIT_RR  (spe_fm,         0x2c6);
 319 EMIT_RR  (spe_dfm,        0x2ce);
 320 EMIT_RRR (spe_fma,        0x00e);
 321 EMIT_RR  (spe_dfma,       0x35c);
 322 EMIT_RRR (spe_fnms,       0x00d);
 323 EMIT_RR  (spe_dfnms,      0x35e);
 324 EMIT_RRR (spe_fms,        0x00f);
 325 EMIT_RR  (spe_dfms,       0x35d);
 326 EMIT_RR  (spe_dfnma,      0x35f);
 327 EMIT_R   (spe_frest,      0x1b8);
 328 EMIT_R   (spe_frsqest,    0x1b9);
 329 EMIT_RR  (spe_fi,         0x3d4);
 330 EMIT_RI8 (spe_csflt,      0x1da, 155);
 331 EMIT_RI8 (spe_cflts,      0x1d8, 173);
 332 EMIT_RI8 (spe_cuflt,      0x1db, 155);
 333 EMIT_RI8 (spe_cfltu,      0x1d9, 173);
 334 EMIT_R   (spe_frds,       0x3b9);
 335 EMIT_R   (spe_fesd,       0x3b8);
 336 EMIT_RR  (spe_dfceq,      0x3c3);
 337 EMIT_RR  (spe_dfcmeq,     0x3cb);
 338 EMIT_RR  (spe_dfcgt,      0x2c3);
 339 EMIT_RR  (spe_dfcmgt,     0x2cb);
 340 EMIT_RI7 (spe_dftsv,      0x3bf);
 341 EMIT_RR  (spe_fceq,       0x3c2);
 342 EMIT_RR  (spe_fcmeq,      0x3ca);
 343 EMIT_RR  (spe_fcgt,       0x2c2);
 344 EMIT_RR  (spe_fcmgt,      0x2ca);
 345 EMIT_R   (spe_fscrwr,     0x3ba);
 346 EMIT_    (spe_fscrrd,     0x398);
 347
 348
 349 /* Channel instructions
 350  */
 351 EMIT_R   (spe_rdch,       0x00d);
 352 EMIT_R   (spe_rdchcnt,    0x00f);
 353 EMIT_R   (spe_wrch,       0x10d);
 354
 355
 356 #ifdef UNDEF_EMIT_MACROS
 357 #undef EMIT_
 358 #undef EMIT_R
 359 #undef EMIT_RR
 360 #undef EMIT_RRR
 361 #undef EMIT_RI7
 362 #undef EMIT_RI8
 363 #undef EMIT_RI10
 364 #undef EMIT_RI16
 365 #undef EMIT_RI18
 366 #undef EMIT_I16
 367 #undef UNDEF_EMIT_MACROS
 368 #endif /* EMIT_ */