src/gallium/auxiliary/rtasm/rtasm_ppc_spe.h

   1 /*
   2  * (C) Copyright IBM Corporation 2008
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  19  * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * \file
  27  * Real-time assembly generation interface for Cell B.E. SPEs.
  28  * For details, see /opt/cell/sdk/docs/arch/SPU_ISA_v1.2_27Jan2007_pub.pdf
  29  *
  30  * \author Ian Romanick <idr@us.ibm.com>
  31  * \author Brian Paul
  32  */
  33
  34 #ifndef RTASM_PPC_SPE_H
  35 #define RTASM_PPC_SPE_H
  36
  37 /** 4 bytes per instruction */
  38 #define SPE_INST_SIZE 4
  39
  40 /** number of general-purpose SIMD registers */
  41 #define SPE_NUM_REGS  128
  42
  43 /** Return Address register (aka $lr / Link Register) */
  44 #define SPE_REG_RA  0
  45
  46 /** Stack Pointer register (aka $sp) */
  47 #define SPE_REG_SP  1
  48
  49
  50 struct spe_function
  51 {
  52    uint32_t *store;  /**< instruction buffer */
  53    uint num_inst;
  54    uint max_inst;
  55
  56    /**
  57     * The "set count" reflects the number of nested register sets
  58     * are allowed.  In the unlikely case that we exceed the set count,
  59     * register allocation will start to be confused, which is critical
  60     * enough that we check for it.
  61     */
  62    unsigned char set_count;
  63
  64    /**
  65     * Flags for used and unused registers.  Each byte corresponds to a
  66     * register; a 0 in that byte means that the register is available.
  67     * A value of 1 means that the register was allocated in the current
  68     * register set.  Any other value N means that the register was allocated
  69     * N register sets ago.
  70      *
  71      * \sa
  72      * spe_allocate_register, spe_allocate_available_register,
  73      * spe_allocate_register_set, spe_release_register_set, spe_release_register,
  74      */
  75     unsigned char regs[SPE_NUM_REGS];
  76
  77     boolean print; /**< print/dump instructions as they're emitted? */
  78     int indent;    /**< number of spaces to indent */
  79 };
  80
  81
  82 extern void spe_init_func(struct spe_function *p, unsigned code_size);
  83 extern void spe_release_func(struct spe_function *p);
  84 extern unsigned spe_code_size(const struct spe_function *p);
  85
  86 extern int spe_allocate_available_register(struct spe_function *p);
  87 extern int spe_allocate_register(struct spe_function *p, int reg);
  88 extern void spe_release_register(struct spe_function *p, int reg);
  89 extern void spe_allocate_register_set(struct spe_function *p);
  90 extern void spe_release_register_set(struct spe_function *p);
  91
  92 extern unsigned
  93 spe_get_registers_used(const struct spe_function *p, ubyte used[]);
  94
  95 extern void spe_print_code(struct spe_function *p, boolean enable);
  96 extern void spe_indent(struct spe_function *p, int spaces);
  97 extern void spe_comment(struct spe_function *p, int rel_indent, const char *s);
  98
  99
 100 #endif /* RTASM_PPC_SPE_H */
 101
 102 #ifndef EMIT
 103 #define EMIT(_name, _op) \
 104     extern void _name (struct spe_function *p);
 105 #define EMIT_(_name, _op) \
 106     extern void _name (struct spe_function *p, unsigned rT);
 107 #define EMIT_R(_name, _op) \
 108     extern void _name (struct spe_function *p, unsigned rT, unsigned rA);
 109 #define EMIT_RR(_name, _op) \
 110     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
 111                        unsigned rB);
 112 #define EMIT_RRR(_name, _op) \
 113     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
 114                        unsigned rB, unsigned rC);
 115 #define EMIT_RI7(_name, _op) \
 116     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
 117                        int imm);
 118 #define EMIT_RI8(_name, _op, bias) \
 119     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
 120                        int imm);
 121 #define EMIT_RI10(_name, _op) \
 122     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
 123                        int imm);
 124 #define EMIT_RI10s(_name, _op) \
 125     extern void _name (struct spe_function *p, unsigned rT, unsigned rA, \
 126                        int imm);
 127 #define EMIT_RI16(_name, _op) \
 128     extern void _name (struct spe_function *p, unsigned rT, int imm);
 129 #define EMIT_RI18(_name, _op) \
 130     extern void _name (struct spe_function *p, unsigned rT, int imm);
 131 #define EMIT_I16(_name, _op) \
 132     extern void _name (struct spe_function *p, int imm);
 133 #define UNDEF_EMIT_MACROS
 134 #endif /* EMIT */
 135
 136
 137 /* Memory load / store instructions
 138  */
 139 EMIT_RR  (spe_lqx,  0x1c4)
 140 EMIT_RI16(spe_lqa,  0x061)
 141 EMIT_RI16(spe_lqr,  0x067)
 142 EMIT_RR  (spe_stqx, 0x144)
 143 EMIT_RI16(spe_stqa, 0x041)
 144 EMIT_RI16(spe_stqr, 0x047)
 145 EMIT_RI7 (spe_cbd,  0x1f4)
 146 EMIT_RR  (spe_cbx,  0x1d4)
 147 EMIT_RI7 (spe_chd,  0x1f5)
 148 EMIT_RI7 (spe_chx,  0x1d5)
 149 EMIT_RI7 (spe_cwd,  0x1f6)
 150 EMIT_RI7 (spe_cwx,  0x1d6)
 151 EMIT_RI7 (spe_cdd,  0x1f7)
 152 EMIT_RI7 (spe_cdx,  0x1d7)
 153
 154
 155 /* Constant formation instructions
 156  */
 157 EMIT_RI16(spe_ilh,   0x083)
 158 EMIT_RI16(spe_ilhu,  0x082)
 159 EMIT_RI16(spe_il,    0x081)
 160 EMIT_RI18(spe_ila,   0x021)
 161 EMIT_RI16(spe_iohl,  0x0c1)
 162 EMIT_RI16(spe_fsmbi, 0x065)
 163
 164
 165
 166 /* Integer and logical instructions
 167  */
 168 EMIT_RR  (spe_ah,      0x0c8)
 169 EMIT_RI10(spe_ahi,     0x01d)
 170 EMIT_RR  (spe_a,       0x0c0)
 171 EMIT_RI10s(spe_ai,      0x01c)
 172 EMIT_RR  (spe_sfh,     0x048)
 173 EMIT_RI10(spe_sfhi,    0x00d)
 174 EMIT_RR  (spe_sf,      0x040)
 175 EMIT_RI10(spe_sfi,     0x00c)
 176 EMIT_RR  (spe_addx,    0x340)
 177 EMIT_RR  (spe_cg,      0x0c2)
 178 EMIT_RR  (spe_cgx,     0x342)
 179 EMIT_RR  (spe_sfx,     0x341)
 180 EMIT_RR  (spe_bg,      0x042)
 181 EMIT_RR  (spe_bgx,     0x343)
 182 EMIT_RR  (spe_mpy,     0x3c4)
 183 EMIT_RR  (spe_mpyu,    0x3cc)
 184 EMIT_RI10(spe_mpyi,    0x074)
 185 EMIT_RI10(spe_mpyui,   0x075)
 186 EMIT_RRR (spe_mpya,    0x00c)
 187 EMIT_RR  (spe_mpyh,    0x3c5)
 188 EMIT_RR  (spe_mpys,    0x3c7)
 189 EMIT_RR  (spe_mpyhh,   0x3c6)
 190 EMIT_RR  (spe_mpyhha,  0x346)
 191 EMIT_RR  (spe_mpyhhu,  0x3ce)
 192 EMIT_RR  (spe_mpyhhau, 0x34e)
 193 EMIT_R   (spe_clz,     0x2a5)
 194 EMIT_R   (spe_cntb,    0x2b4)
 195 EMIT_R   (spe_fsmb,    0x1b6)
 196 EMIT_R   (spe_fsmh,    0x1b5)
 197 EMIT_R   (spe_fsm,     0x1b4)
 198 EMIT_R   (spe_gbb,     0x1b2)
 199 EMIT_R   (spe_gbh,     0x1b1)
 200 EMIT_R   (spe_gb,      0x1b0)
 201 EMIT_RR  (spe_avgb,    0x0d3)
 202 EMIT_RR  (spe_absdb,   0x053)
 203 EMIT_RR  (spe_sumb,    0x253)
 204 EMIT_R   (spe_xsbh,    0x2b6)
 205 EMIT_R   (spe_xshw,    0x2ae)
 206 EMIT_R   (spe_xswd,    0x2a6)
 207 EMIT_RR  (spe_and,     0x0c1)
 208 EMIT_RR  (spe_andc,    0x2c1)
 209 EMIT_RI10s(spe_andbi,   0x016)
 210 EMIT_RI10s(spe_andhi,   0x015)
 211 EMIT_RI10s(spe_andi,    0x014)
 212 EMIT_RR  (spe_or,      0x041)
 213 EMIT_RR  (spe_orc,     0x2c9)
 214 EMIT_RI10s(spe_orbi,    0x006)
 215 EMIT_RI10s(spe_orhi,    0x005)
 216 EMIT_RI10s(spe_ori,     0x004)
 217 EMIT_R   (spe_orx,     0x1f0)
 218 EMIT_RR  (spe_xor,     0x241)
 219 EMIT_RI10s(spe_xorbi,   0x046)
 220 EMIT_RI10s(spe_xorhi,   0x045)
 221 EMIT_RI10s(spe_xori,    0x044)
 222 EMIT_RR  (spe_nand,    0x0c9)
 223 EMIT_RR  (spe_nor,     0x049)
 224 EMIT_RR  (spe_eqv,     0x249)
 225 EMIT_RRR (spe_selb,    0x008)
 226 EMIT_RRR (spe_shufb,   0x00b)
 227
 228
 229 /* Shift and rotate instructions
 230  */
 231 EMIT_RR  (spe_shlh,      0x05f)
 232 EMIT_RI7 (spe_shlhi,     0x07f)
 233 EMIT_RR  (spe_shl,       0x05b)
 234 EMIT_RI7 (spe_shli,      0x07b)
 235 EMIT_RR  (spe_shlqbi,    0x1db)
 236 EMIT_RI7 (spe_shlqbii,   0x1fb)
 237 EMIT_RR  (spe_shlqby,    0x1df)
 238 EMIT_RI7 (spe_shlqbyi,   0x1ff)
 239 EMIT_RR  (spe_shlqbybi,  0x1cf)
 240 EMIT_RR  (spe_roth,      0x05c)
 241 EMIT_RI7 (spe_rothi,     0x07c)
 242 EMIT_RR  (spe_rot,       0x058)
 243 EMIT_RI7 (spe_roti,      0x078)
 244 EMIT_RR  (spe_rotqby,    0x1dc)
 245 EMIT_RI7 (spe_rotqbyi,   0x1fc)
 246 EMIT_RR  (spe_rotqbybi,  0x1cc)
 247 EMIT_RR  (spe_rotqbi,    0x1d8)
 248 EMIT_RI7 (spe_rotqbii,   0x1f8)
 249 EMIT_RR  (spe_rothm,     0x05d)
 250 EMIT_RI7 (spe_rothmi,    0x07d)
 251 EMIT_RR  (spe_rotm,      0x059)
 252 EMIT_RI7 (spe_rotmi,     0x079)
 253 EMIT_RR  (spe_rotqmby,   0x1dd)
 254 EMIT_RI7 (spe_rotqmbyi,  0x1fd)
 255 EMIT_RR  (spe_rotqmbybi, 0x1cd)
 256 EMIT_RR  (spe_rotqmbi,   0x1c9)
 257 EMIT_RI7 (spe_rotqmbii,  0x1f9)
 258 EMIT_RR  (spe_rotmah,    0x05e)
 259 EMIT_RI7 (spe_rotmahi,   0x07e)
 260 EMIT_RR  (spe_rotma,     0x05a)
 261 EMIT_RI7 (spe_rotmai,    0x07a)
 262
 263
 264 /* Compare, branch, and halt instructions
 265  */
 266 EMIT_RR  (spe_heq,       0x3d8)
 267 EMIT_RI10(spe_heqi,      0x07f)
 268 EMIT_RR  (spe_hgt,       0x258)
 269 EMIT_RI10(spe_hgti,      0x04f)
 270 EMIT_RR  (spe_hlgt,      0x2d8)
 271 EMIT_RI10(spe_hlgti,     0x05f)
 272 EMIT_RR  (spe_ceqb,      0x3d0)
 273 EMIT_RI10(spe_ceqbi,     0x07e)
 274 EMIT_RR  (spe_ceqh,      0x3c8)
 275 EMIT_RI10(spe_ceqhi,     0x07d)
 276 EMIT_RR  (spe_ceq,       0x3c0)
 277 EMIT_RI10(spe_ceqi,      0x07c)
 278 EMIT_RR  (spe_cgtb,      0x250)
 279 EMIT_RI10(spe_cgtbi,     0x04e)
 280 EMIT_RR  (spe_cgth,      0x248)
 281 EMIT_RI10(spe_cgthi,     0x04d)
 282 EMIT_RR  (spe_cgt,       0x240)
 283 EMIT_RI10(spe_cgti,      0x04c)
 284 EMIT_RR  (spe_clgtb,     0x2d0)
 285 EMIT_RI10(spe_clgtbi,    0x05e)
 286 EMIT_RR  (spe_clgth,     0x2c8)
 287 EMIT_RI10(spe_clgthi,    0x05d)
 288 EMIT_RR  (spe_clgt,      0x2c0)
 289 EMIT_RI10(spe_clgti,     0x05c)
 290 EMIT_I16 (spe_br,        0x064)
 291 EMIT_I16 (spe_bra,       0x060)
 292 EMIT_RI16(spe_brsl,      0x066)
 293 EMIT_RI16(spe_brasl,     0x062)
 294 EMIT_RI16(spe_brnz,      0x042)
 295 EMIT_RI16(spe_brz,       0x040)
 296 EMIT_RI16(spe_brhnz,     0x046)
 297 EMIT_RI16(spe_brhz,      0x044)
 298
 299 /* Control instructions
 300  */
 301 EMIT     (spe_lnop,      0x001)
 302
 303 extern void
 304 spe_lqd(struct spe_function *p, unsigned rT, unsigned rA, int offset);
 305
 306 extern void
 307 spe_stqd(struct spe_function *p, unsigned rT, unsigned rA, int offset);
 308
 309 extern void spe_bi(struct spe_function *p, unsigned rA, int d, int e);
 310 extern void spe_iret(struct spe_function *p, unsigned rA, int d, int e);
 311 extern void spe_bisled(struct spe_function *p, unsigned rT, unsigned rA,
 312     int d, int e);
 313 extern void spe_bisl(struct spe_function *p, unsigned rT, unsigned rA,
 314     int d, int e);
 315 extern void spe_biz(struct spe_function *p, unsigned rT, unsigned rA,
 316     int d, int e);
 317 extern void spe_binz(struct spe_function *p, unsigned rT, unsigned rA,
 318     int d, int e);
 319 extern void spe_bihz(struct spe_function *p, unsigned rT, unsigned rA,
 320     int d, int e);
 321 extern void spe_bihnz(struct spe_function *p, unsigned rT, unsigned rA,
 322     int d, int e);
 323
 324
 325 /** Load/splat immediate float into rT. */
 326 extern void
 327 spe_load_float(struct spe_function *p, unsigned rT, float x);
 328
 329 /** Load/splat immediate int into rT. */
 330 extern void
 331 spe_load_int(struct spe_function *p, unsigned rT, int i);
 332
 333 /** Load/splat immediate unsigned int into rT. */
 334 extern void
 335 spe_load_uint(struct spe_function *p, unsigned rT, unsigned int ui);
 336
 337 /** And immediate value into rT. */
 338 extern void
 339 spe_and_uint(struct spe_function *p, unsigned rT, unsigned rA, unsigned int ui);
 340
 341 /** Xor immediate value into rT. */
 342 extern void
 343 spe_xor_uint(struct spe_function *p, unsigned rT, unsigned rA, unsigned int ui);
 344
 345 /** Compare equal with immediate value. */
 346 extern void
 347 spe_compare_equal_uint(struct spe_function *p, unsigned rT, unsigned rA, unsigned int ui);
 348
 349 /** Compare greater with immediate value. */
 350 extern void
 351 spe_compare_greater_uint(struct spe_function *p, unsigned rT, unsigned rA, unsigned int ui);
 352
 353 /** Replicate word 0 of rA across rT. */
 354 extern void
 355 spe_splat(struct spe_function *p, unsigned rT, unsigned rA);
 356
 357 /** rT = complement_all_bits(rA). */
 358 extern void
 359 spe_complement(struct spe_function *p, unsigned rT, unsigned rA);
 360
 361 /** rT = rA. */
 362 extern void
 363 spe_move(struct spe_function *p, unsigned rT, unsigned rA);
 364
 365 /** rT = {0,0,0,0}. */
 366 extern void
 367 spe_zero(struct spe_function *p, unsigned rT);
 368
 369 /** rT = splat(rA, word) */
 370 extern void
 371 spe_splat_word(struct spe_function *p, unsigned rT, unsigned rA, int word);
 372
 373 /** rT = float min(rA, rB) */
 374 extern void
 375 spe_float_min(struct spe_function *p, unsigned rT, unsigned rA, unsigned rB);
 376
 377 /** rT = float max(rA, rB) */
 378 extern void
 379 spe_float_max(struct spe_function *p, unsigned rT, unsigned rA, unsigned rB);
 380
 381
 382 /* Floating-point instructions
 383  */
 384 EMIT_RR  (spe_fa,         0x2c4)
 385 EMIT_RR  (spe_dfa,        0x2cc)
 386 EMIT_RR  (spe_fs,         0x2c5)
 387 EMIT_RR  (spe_dfs,        0x2cd)
 388 EMIT_RR  (spe_fm,         0x2c6)
 389 EMIT_RR  (spe_dfm,        0x2ce)
 390 EMIT_RRR (spe_fma,        0x00e)
 391 EMIT_RR  (spe_dfma,       0x35c)
 392 EMIT_RRR (spe_fnms,       0x00d)
 393 EMIT_RR  (spe_dfnms,      0x35e)
 394 EMIT_RRR (spe_fms,        0x00f)
 395 EMIT_RR  (spe_dfms,       0x35d)
 396 EMIT_RR  (spe_dfnma,      0x35f)
 397 EMIT_R   (spe_frest,      0x1b8)
 398 EMIT_R   (spe_frsqest,    0x1b9)
 399 EMIT_RR  (spe_fi,         0x3d4)
 400 EMIT_RI8 (spe_csflt,      0x1da, 155)
 401 EMIT_RI8 (spe_cflts,      0x1d8, 173)
 402 EMIT_RI8 (spe_cuflt,      0x1db, 155)
 403 EMIT_RI8 (spe_cfltu,      0x1d9, 173)
 404 EMIT_R   (spe_frds,       0x3b9)
 405 EMIT_R   (spe_fesd,       0x3b8)
 406 EMIT_RR  (spe_dfceq,      0x3c3)
 407 EMIT_RR  (spe_dfcmeq,     0x3cb)
 408 EMIT_RR  (spe_dfcgt,      0x2c3)
 409 EMIT_RR  (spe_dfcmgt,     0x2cb)
 410 EMIT_RI7 (spe_dftsv,      0x3bf)
 411 EMIT_RR  (spe_fceq,       0x3c2)
 412 EMIT_RR  (spe_fcmeq,      0x3ca)
 413 EMIT_RR  (spe_fcgt,       0x2c2)
 414 EMIT_RR  (spe_fcmgt,      0x2ca)
 415 EMIT_R   (spe_fscrwr,     0x3ba)
 416 EMIT_    (spe_fscrrd,     0x398)
 417
 418
 419 /* Channel instructions
 420  */
 421 EMIT_R   (spe_rdch,       0x00d)
 422 EMIT_R   (spe_rdchcnt,    0x00f)
 423 EMIT_R   (spe_wrch,       0x10d)
 424
 425
 426 #ifdef UNDEF_EMIT_MACROS
 427 #undef EMIT
 428 #undef EMIT_
 429 #undef EMIT_R
 430 #undef EMIT_RR
 431 #undef EMIT_RRR
 432 #undef EMIT_RI7
 433 #undef EMIT_RI8
 434 #undef EMIT_RI10
 435 #undef EMIT_RI10s
 436 #undef EMIT_RI16
 437 #undef EMIT_RI18
 438 #undef EMIT_I16
 439 #undef UNDEF_EMIT_MACROS
 440 #endif /* EMIT_ */