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[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /**
29 * TGSI interpreter/executor.
30 *
31 * Flow control information:
32 *
33 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
34 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
35 * care since a condition may be true for some quad components but false
36 * for other components.
37 *
38 * We basically execute all statements (even if they're in the part of
39 * an IF/ELSE clause that's "not taken") and use a special mask to
40 * control writing to destination registers. This is the ExecMask.
41 * See store_dest().
42 *
43 * The ExecMask is computed from three other masks (CondMask, LoopMask and
44 * ContMask) which are controlled by the flow control instructions (namely:
45 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
46 *
47 *
48 * Authors:
49 * Michal Krol
50 * Brian Paul
51 */
52
53 #include "pipe/p_compiler.h"
54 #include "pipe/p_state.h"
55 #include "pipe/p_shader_tokens.h"
56 #include "tgsi/tgsi_parse.h"
57 #include "tgsi/tgsi_util.h"
58 #include "tgsi_exec.h"
59 #include "util/u_memory.h"
60 #include "util/u_math.h"
61
62 #define FAST_MATH 1
63
64 #define TILE_TOP_LEFT 0
65 #define TILE_TOP_RIGHT 1
66 #define TILE_BOTTOM_LEFT 2
67 #define TILE_BOTTOM_RIGHT 3
68
69 #define CHAN_X 0
70 #define CHAN_Y 1
71 #define CHAN_Z 2
72 #define CHAN_W 3
73
74 /*
75 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
76 */
77 #define TEMP_0_I TGSI_EXEC_TEMP_00000000_I
78 #define TEMP_0_C TGSI_EXEC_TEMP_00000000_C
79 #define TEMP_7F_I TGSI_EXEC_TEMP_7FFFFFFF_I
80 #define TEMP_7F_C TGSI_EXEC_TEMP_7FFFFFFF_C
81 #define TEMP_80_I TGSI_EXEC_TEMP_80000000_I
82 #define TEMP_80_C TGSI_EXEC_TEMP_80000000_C
83 #define TEMP_FF_I TGSI_EXEC_TEMP_FFFFFFFF_I
84 #define TEMP_FF_C TGSI_EXEC_TEMP_FFFFFFFF_C
85 #define TEMP_1_I TGSI_EXEC_TEMP_ONE_I
86 #define TEMP_1_C TGSI_EXEC_TEMP_ONE_C
87 #define TEMP_2_I TGSI_EXEC_TEMP_TWO_I
88 #define TEMP_2_C TGSI_EXEC_TEMP_TWO_C
89 #define TEMP_128_I TGSI_EXEC_TEMP_128_I
90 #define TEMP_128_C TGSI_EXEC_TEMP_128_C
91 #define TEMP_M128_I TGSI_EXEC_TEMP_MINUS_128_I
92 #define TEMP_M128_C TGSI_EXEC_TEMP_MINUS_128_C
93 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
94 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
95 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
96 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
97 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
98 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
99 #define TEMP_CC_I TGSI_EXEC_TEMP_CC_I
100 #define TEMP_CC_C TGSI_EXEC_TEMP_CC_C
101 #define TEMP_3_I TGSI_EXEC_TEMP_THREE_I
102 #define TEMP_3_C TGSI_EXEC_TEMP_THREE_C
103 #define TEMP_HALF_I TGSI_EXEC_TEMP_HALF_I
104 #define TEMP_HALF_C TGSI_EXEC_TEMP_HALF_C
105 #define TEMP_R0 TGSI_EXEC_TEMP_R0
106
107 #define IS_CHANNEL_ENABLED(INST, CHAN)\
108 ((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
109
110 #define IS_CHANNEL_ENABLED2(INST, CHAN)\
111 ((INST).FullDstRegisters[1].DstRegister.WriteMask & (1 << (CHAN)))
112
113 #define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
114 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
115 if (IS_CHANNEL_ENABLED( INST, CHAN ))
116
117 #define FOR_EACH_ENABLED_CHANNEL2(INST, CHAN)\
118 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
119 if (IS_CHANNEL_ENABLED2( INST, CHAN ))
120
121
122 /** The execution mask depends on the conditional mask and the loop mask */
123 #define UPDATE_EXEC_MASK(MACH) \
124 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->FuncMask
125
126 /**
127 * Initialize machine state by expanding tokens to full instructions,
128 * allocating temporary storage, setting up constants, etc.
129 * After this, we can call tgsi_exec_machine_run() many times.
130 */
131 void
132 tgsi_exec_machine_bind_shader(
133 struct tgsi_exec_machine *mach,
134 const struct tgsi_token *tokens,
135 uint numSamplers,
136 struct tgsi_sampler *samplers)
137 {
138 uint k;
139 struct tgsi_parse_context parse;
140 struct tgsi_exec_labels *labels = &mach->Labels;
141 struct tgsi_full_instruction *instructions;
142 struct tgsi_full_declaration *declarations;
143 uint maxInstructions = 10, numInstructions = 0;
144 uint maxDeclarations = 10, numDeclarations = 0;
145 uint instno = 0;
146
147 #if 0
148 tgsi_dump(tokens, 0);
149 #endif
150
151 util_init_math();
152
153 mach->Tokens = tokens;
154 mach->Samplers = samplers;
155
156 k = tgsi_parse_init (&parse, mach->Tokens);
157 if (k != TGSI_PARSE_OK) {
158 debug_printf( "Problem parsing!\n" );
159 return;
160 }
161
162 mach->Processor = parse.FullHeader.Processor.Processor;
163 mach->ImmLimit = 0;
164 labels->count = 0;
165
166 declarations = (struct tgsi_full_declaration *)
167 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
168
169 if (!declarations) {
170 return;
171 }
172
173 instructions = (struct tgsi_full_instruction *)
174 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
175
176 if (!instructions) {
177 FREE( declarations );
178 return;
179 }
180
181 while( !tgsi_parse_end_of_tokens( &parse ) ) {
182 uint pointer = parse.Position;
183 uint i;
184
185 tgsi_parse_token( &parse );
186 switch( parse.FullToken.Token.Type ) {
187 case TGSI_TOKEN_TYPE_DECLARATION:
188 /* save expanded declaration */
189 if (numDeclarations == maxDeclarations) {
190 declarations = REALLOC(declarations,
191 maxDeclarations
192 * sizeof(struct tgsi_full_declaration),
193 (maxDeclarations + 10)
194 * sizeof(struct tgsi_full_declaration));
195 maxDeclarations += 10;
196 }
197 memcpy(declarations + numDeclarations,
198 &parse.FullToken.FullDeclaration,
199 sizeof(declarations[0]));
200 numDeclarations++;
201 break;
202
203 case TGSI_TOKEN_TYPE_IMMEDIATE:
204 {
205 uint size = parse.FullToken.FullImmediate.Immediate.Size - 1;
206 assert( size % 4 == 0 );
207 assert( mach->ImmLimit + size / 4 <= TGSI_EXEC_NUM_IMMEDIATES );
208
209 for( i = 0; i < size; i++ ) {
210 mach->Imms[mach->ImmLimit + i / 4][i % 4] =
211 parse.FullToken.FullImmediate.u.ImmediateFloat32[i].Float;
212 }
213 mach->ImmLimit += size / 4;
214 }
215 break;
216
217 case TGSI_TOKEN_TYPE_INSTRUCTION:
218 assert( labels->count < MAX_LABELS );
219
220 labels->labels[labels->count][0] = instno;
221 labels->labels[labels->count][1] = pointer;
222 labels->count++;
223
224 /* save expanded instruction */
225 if (numInstructions == maxInstructions) {
226 instructions = REALLOC(instructions,
227 maxInstructions
228 * sizeof(struct tgsi_full_instruction),
229 (maxInstructions + 10)
230 * sizeof(struct tgsi_full_instruction));
231 maxInstructions += 10;
232 }
233 memcpy(instructions + numInstructions,
234 &parse.FullToken.FullInstruction,
235 sizeof(instructions[0]));
236 numInstructions++;
237 break;
238
239 default:
240 assert( 0 );
241 }
242 }
243 tgsi_parse_free (&parse);
244
245 if (mach->Declarations) {
246 FREE( mach->Declarations );
247 }
248 mach->Declarations = declarations;
249 mach->NumDeclarations = numDeclarations;
250
251 if (mach->Instructions) {
252 FREE( mach->Instructions );
253 }
254 mach->Instructions = instructions;
255 mach->NumInstructions = numInstructions;
256 }
257
258
259 void
260 tgsi_exec_machine_init(
261 struct tgsi_exec_machine *mach )
262 {
263 uint i;
264
265 mach->Temps = (struct tgsi_exec_vector *) tgsi_align_128bit( mach->_Temps);
266 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
267
268 /* Setup constants. */
269 for( i = 0; i < 4; i++ ) {
270 mach->Temps[TEMP_0_I].xyzw[TEMP_0_C].u[i] = 0x00000000;
271 mach->Temps[TEMP_7F_I].xyzw[TEMP_7F_C].u[i] = 0x7FFFFFFF;
272 mach->Temps[TEMP_80_I].xyzw[TEMP_80_C].u[i] = 0x80000000;
273 mach->Temps[TEMP_FF_I].xyzw[TEMP_FF_C].u[i] = 0xFFFFFFFF;
274 mach->Temps[TEMP_1_I].xyzw[TEMP_1_C].f[i] = 1.0f;
275 mach->Temps[TEMP_2_I].xyzw[TEMP_2_C].f[i] = 2.0f;
276 mach->Temps[TEMP_128_I].xyzw[TEMP_128_C].f[i] = 128.0f;
277 mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C].f[i] = -128.0f;
278 mach->Temps[TEMP_3_I].xyzw[TEMP_3_C].f[i] = 3.0f;
279 mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C].f[i] = 0.5f;
280 }
281 }
282
283
284 void
285 tgsi_exec_machine_free_data(struct tgsi_exec_machine *mach)
286 {
287 if (mach->Instructions) {
288 FREE(mach->Instructions);
289 mach->Instructions = NULL;
290 mach->NumInstructions = 0;
291 }
292 if (mach->Declarations) {
293 FREE(mach->Declarations);
294 mach->Declarations = NULL;
295 mach->NumDeclarations = 0;
296 }
297 }
298
299
300 static void
301 micro_abs(
302 union tgsi_exec_channel *dst,
303 const union tgsi_exec_channel *src )
304 {
305 dst->f[0] = fabsf( src->f[0] );
306 dst->f[1] = fabsf( src->f[1] );
307 dst->f[2] = fabsf( src->f[2] );
308 dst->f[3] = fabsf( src->f[3] );
309 }
310
311 static void
312 micro_add(
313 union tgsi_exec_channel *dst,
314 const union tgsi_exec_channel *src0,
315 const union tgsi_exec_channel *src1 )
316 {
317 dst->f[0] = src0->f[0] + src1->f[0];
318 dst->f[1] = src0->f[1] + src1->f[1];
319 dst->f[2] = src0->f[2] + src1->f[2];
320 dst->f[3] = src0->f[3] + src1->f[3];
321 }
322
323 static void
324 micro_iadd(
325 union tgsi_exec_channel *dst,
326 const union tgsi_exec_channel *src0,
327 const union tgsi_exec_channel *src1 )
328 {
329 dst->i[0] = src0->i[0] + src1->i[0];
330 dst->i[1] = src0->i[1] + src1->i[1];
331 dst->i[2] = src0->i[2] + src1->i[2];
332 dst->i[3] = src0->i[3] + src1->i[3];
333 }
334
335 static void
336 micro_and(
337 union tgsi_exec_channel *dst,
338 const union tgsi_exec_channel *src0,
339 const union tgsi_exec_channel *src1 )
340 {
341 dst->u[0] = src0->u[0] & src1->u[0];
342 dst->u[1] = src0->u[1] & src1->u[1];
343 dst->u[2] = src0->u[2] & src1->u[2];
344 dst->u[3] = src0->u[3] & src1->u[3];
345 }
346
347 static void
348 micro_ceil(
349 union tgsi_exec_channel *dst,
350 const union tgsi_exec_channel *src )
351 {
352 dst->f[0] = ceilf( src->f[0] );
353 dst->f[1] = ceilf( src->f[1] );
354 dst->f[2] = ceilf( src->f[2] );
355 dst->f[3] = ceilf( src->f[3] );
356 }
357
358 static void
359 micro_cos(
360 union tgsi_exec_channel *dst,
361 const union tgsi_exec_channel *src )
362 {
363 dst->f[0] = cosf( src->f[0] );
364 dst->f[1] = cosf( src->f[1] );
365 dst->f[2] = cosf( src->f[2] );
366 dst->f[3] = cosf( src->f[3] );
367 }
368
369 static void
370 micro_ddx(
371 union tgsi_exec_channel *dst,
372 const union tgsi_exec_channel *src )
373 {
374 dst->f[0] =
375 dst->f[1] =
376 dst->f[2] =
377 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
378 }
379
380 static void
381 micro_ddy(
382 union tgsi_exec_channel *dst,
383 const union tgsi_exec_channel *src )
384 {
385 dst->f[0] =
386 dst->f[1] =
387 dst->f[2] =
388 dst->f[3] = src->f[TILE_TOP_LEFT] - src->f[TILE_BOTTOM_LEFT];
389 }
390
391 static void
392 micro_div(
393 union tgsi_exec_channel *dst,
394 const union tgsi_exec_channel *src0,
395 const union tgsi_exec_channel *src1 )
396 {
397 if (src1->f[0] != 0) {
398 dst->f[0] = src0->f[0] / src1->f[0];
399 }
400 if (src1->f[1] != 0) {
401 dst->f[1] = src0->f[1] / src1->f[1];
402 }
403 if (src1->f[2] != 0) {
404 dst->f[2] = src0->f[2] / src1->f[2];
405 }
406 if (src1->f[3] != 0) {
407 dst->f[3] = src0->f[3] / src1->f[3];
408 }
409 }
410
411 static void
412 micro_udiv(
413 union tgsi_exec_channel *dst,
414 const union tgsi_exec_channel *src0,
415 const union tgsi_exec_channel *src1 )
416 {
417 dst->u[0] = src0->u[0] / src1->u[0];
418 dst->u[1] = src0->u[1] / src1->u[1];
419 dst->u[2] = src0->u[2] / src1->u[2];
420 dst->u[3] = src0->u[3] / src1->u[3];
421 }
422
423 static void
424 micro_eq(
425 union tgsi_exec_channel *dst,
426 const union tgsi_exec_channel *src0,
427 const union tgsi_exec_channel *src1,
428 const union tgsi_exec_channel *src2,
429 const union tgsi_exec_channel *src3 )
430 {
431 dst->f[0] = src0->f[0] == src1->f[0] ? src2->f[0] : src3->f[0];
432 dst->f[1] = src0->f[1] == src1->f[1] ? src2->f[1] : src3->f[1];
433 dst->f[2] = src0->f[2] == src1->f[2] ? src2->f[2] : src3->f[2];
434 dst->f[3] = src0->f[3] == src1->f[3] ? src2->f[3] : src3->f[3];
435 }
436
437 static void
438 micro_ieq(
439 union tgsi_exec_channel *dst,
440 const union tgsi_exec_channel *src0,
441 const union tgsi_exec_channel *src1,
442 const union tgsi_exec_channel *src2,
443 const union tgsi_exec_channel *src3 )
444 {
445 dst->i[0] = src0->i[0] == src1->i[0] ? src2->i[0] : src3->i[0];
446 dst->i[1] = src0->i[1] == src1->i[1] ? src2->i[1] : src3->i[1];
447 dst->i[2] = src0->i[2] == src1->i[2] ? src2->i[2] : src3->i[2];
448 dst->i[3] = src0->i[3] == src1->i[3] ? src2->i[3] : src3->i[3];
449 }
450
451 static void
452 micro_exp2(
453 union tgsi_exec_channel *dst,
454 const union tgsi_exec_channel *src)
455 {
456 #if FAST_MATH
457 dst->f[0] = util_fast_exp2( src->f[0] );
458 dst->f[1] = util_fast_exp2( src->f[1] );
459 dst->f[2] = util_fast_exp2( src->f[2] );
460 dst->f[3] = util_fast_exp2( src->f[3] );
461 #else
462 dst->f[0] = powf( 2.0f, src->f[0] );
463 dst->f[1] = powf( 2.0f, src->f[1] );
464 dst->f[2] = powf( 2.0f, src->f[2] );
465 dst->f[3] = powf( 2.0f, src->f[3] );
466 #endif
467 }
468
469 static void
470 micro_f2ut(
471 union tgsi_exec_channel *dst,
472 const union tgsi_exec_channel *src )
473 {
474 dst->u[0] = (uint) src->f[0];
475 dst->u[1] = (uint) src->f[1];
476 dst->u[2] = (uint) src->f[2];
477 dst->u[3] = (uint) src->f[3];
478 }
479
480 static void
481 micro_flr(
482 union tgsi_exec_channel *dst,
483 const union tgsi_exec_channel *src )
484 {
485 dst->f[0] = floorf( src->f[0] );
486 dst->f[1] = floorf( src->f[1] );
487 dst->f[2] = floorf( src->f[2] );
488 dst->f[3] = floorf( src->f[3] );
489 }
490
491 static void
492 micro_frc(
493 union tgsi_exec_channel *dst,
494 const union tgsi_exec_channel *src )
495 {
496 dst->f[0] = src->f[0] - floorf( src->f[0] );
497 dst->f[1] = src->f[1] - floorf( src->f[1] );
498 dst->f[2] = src->f[2] - floorf( src->f[2] );
499 dst->f[3] = src->f[3] - floorf( src->f[3] );
500 }
501
502 static void
503 micro_ge(
504 union tgsi_exec_channel *dst,
505 const union tgsi_exec_channel *src0,
506 const union tgsi_exec_channel *src1,
507 const union tgsi_exec_channel *src2,
508 const union tgsi_exec_channel *src3 )
509 {
510 dst->f[0] = src0->f[0] >= src1->f[0] ? src2->f[0] : src3->f[0];
511 dst->f[1] = src0->f[1] >= src1->f[1] ? src2->f[1] : src3->f[1];
512 dst->f[2] = src0->f[2] >= src1->f[2] ? src2->f[2] : src3->f[2];
513 dst->f[3] = src0->f[3] >= src1->f[3] ? src2->f[3] : src3->f[3];
514 }
515
516 static void
517 micro_i2f(
518 union tgsi_exec_channel *dst,
519 const union tgsi_exec_channel *src )
520 {
521 dst->f[0] = (float) src->i[0];
522 dst->f[1] = (float) src->i[1];
523 dst->f[2] = (float) src->i[2];
524 dst->f[3] = (float) src->i[3];
525 }
526
527 static void
528 micro_lg2(
529 union tgsi_exec_channel *dst,
530 const union tgsi_exec_channel *src )
531 {
532 #if FAST_MATH
533 dst->f[0] = util_fast_log2( src->f[0] );
534 dst->f[1] = util_fast_log2( src->f[1] );
535 dst->f[2] = util_fast_log2( src->f[2] );
536 dst->f[3] = util_fast_log2( src->f[3] );
537 #else
538 dst->f[0] = logf( src->f[0] ) * 1.442695f;
539 dst->f[1] = logf( src->f[1] ) * 1.442695f;
540 dst->f[2] = logf( src->f[2] ) * 1.442695f;
541 dst->f[3] = logf( src->f[3] ) * 1.442695f;
542 #endif
543 }
544
545 static void
546 micro_le(
547 union tgsi_exec_channel *dst,
548 const union tgsi_exec_channel *src0,
549 const union tgsi_exec_channel *src1,
550 const union tgsi_exec_channel *src2,
551 const union tgsi_exec_channel *src3 )
552 {
553 dst->f[0] = src0->f[0] <= src1->f[0] ? src2->f[0] : src3->f[0];
554 dst->f[1] = src0->f[1] <= src1->f[1] ? src2->f[1] : src3->f[1];
555 dst->f[2] = src0->f[2] <= src1->f[2] ? src2->f[2] : src3->f[2];
556 dst->f[3] = src0->f[3] <= src1->f[3] ? src2->f[3] : src3->f[3];
557 }
558
559 static void
560 micro_lt(
561 union tgsi_exec_channel *dst,
562 const union tgsi_exec_channel *src0,
563 const union tgsi_exec_channel *src1,
564 const union tgsi_exec_channel *src2,
565 const union tgsi_exec_channel *src3 )
566 {
567 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
568 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
569 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
570 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
571 }
572
573 static void
574 micro_ilt(
575 union tgsi_exec_channel *dst,
576 const union tgsi_exec_channel *src0,
577 const union tgsi_exec_channel *src1,
578 const union tgsi_exec_channel *src2,
579 const union tgsi_exec_channel *src3 )
580 {
581 dst->i[0] = src0->i[0] < src1->i[0] ? src2->i[0] : src3->i[0];
582 dst->i[1] = src0->i[1] < src1->i[1] ? src2->i[1] : src3->i[1];
583 dst->i[2] = src0->i[2] < src1->i[2] ? src2->i[2] : src3->i[2];
584 dst->i[3] = src0->i[3] < src1->i[3] ? src2->i[3] : src3->i[3];
585 }
586
587 static void
588 micro_ult(
589 union tgsi_exec_channel *dst,
590 const union tgsi_exec_channel *src0,
591 const union tgsi_exec_channel *src1,
592 const union tgsi_exec_channel *src2,
593 const union tgsi_exec_channel *src3 )
594 {
595 dst->u[0] = src0->u[0] < src1->u[0] ? src2->u[0] : src3->u[0];
596 dst->u[1] = src0->u[1] < src1->u[1] ? src2->u[1] : src3->u[1];
597 dst->u[2] = src0->u[2] < src1->u[2] ? src2->u[2] : src3->u[2];
598 dst->u[3] = src0->u[3] < src1->u[3] ? src2->u[3] : src3->u[3];
599 }
600
601 static void
602 micro_max(
603 union tgsi_exec_channel *dst,
604 const union tgsi_exec_channel *src0,
605 const union tgsi_exec_channel *src1 )
606 {
607 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
608 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
609 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
610 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
611 }
612
613 static void
614 micro_imax(
615 union tgsi_exec_channel *dst,
616 const union tgsi_exec_channel *src0,
617 const union tgsi_exec_channel *src1 )
618 {
619 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
620 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
621 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
622 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
623 }
624
625 static void
626 micro_umax(
627 union tgsi_exec_channel *dst,
628 const union tgsi_exec_channel *src0,
629 const union tgsi_exec_channel *src1 )
630 {
631 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
632 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
633 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
634 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
635 }
636
637 static void
638 micro_min(
639 union tgsi_exec_channel *dst,
640 const union tgsi_exec_channel *src0,
641 const union tgsi_exec_channel *src1 )
642 {
643 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
644 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
645 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
646 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
647 }
648
649 static void
650 micro_imin(
651 union tgsi_exec_channel *dst,
652 const union tgsi_exec_channel *src0,
653 const union tgsi_exec_channel *src1 )
654 {
655 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
656 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
657 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
658 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
659 }
660
661 static void
662 micro_umin(
663 union tgsi_exec_channel *dst,
664 const union tgsi_exec_channel *src0,
665 const union tgsi_exec_channel *src1 )
666 {
667 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
668 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
669 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
670 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
671 }
672
673 static void
674 micro_umod(
675 union tgsi_exec_channel *dst,
676 const union tgsi_exec_channel *src0,
677 const union tgsi_exec_channel *src1 )
678 {
679 dst->u[0] = src0->u[0] % src1->u[0];
680 dst->u[1] = src0->u[1] % src1->u[1];
681 dst->u[2] = src0->u[2] % src1->u[2];
682 dst->u[3] = src0->u[3] % src1->u[3];
683 }
684
685 static void
686 micro_mul(
687 union tgsi_exec_channel *dst,
688 const union tgsi_exec_channel *src0,
689 const union tgsi_exec_channel *src1 )
690 {
691 dst->f[0] = src0->f[0] * src1->f[0];
692 dst->f[1] = src0->f[1] * src1->f[1];
693 dst->f[2] = src0->f[2] * src1->f[2];
694 dst->f[3] = src0->f[3] * src1->f[3];
695 }
696
697 static void
698 micro_imul(
699 union tgsi_exec_channel *dst,
700 const union tgsi_exec_channel *src0,
701 const union tgsi_exec_channel *src1 )
702 {
703 dst->i[0] = src0->i[0] * src1->i[0];
704 dst->i[1] = src0->i[1] * src1->i[1];
705 dst->i[2] = src0->i[2] * src1->i[2];
706 dst->i[3] = src0->i[3] * src1->i[3];
707 }
708
709 static void
710 micro_imul64(
711 union tgsi_exec_channel *dst0,
712 union tgsi_exec_channel *dst1,
713 const union tgsi_exec_channel *src0,
714 const union tgsi_exec_channel *src1 )
715 {
716 dst1->i[0] = src0->i[0] * src1->i[0];
717 dst1->i[1] = src0->i[1] * src1->i[1];
718 dst1->i[2] = src0->i[2] * src1->i[2];
719 dst1->i[3] = src0->i[3] * src1->i[3];
720 dst0->i[0] = 0;
721 dst0->i[1] = 0;
722 dst0->i[2] = 0;
723 dst0->i[3] = 0;
724 }
725
726 static void
727 micro_umul64(
728 union tgsi_exec_channel *dst0,
729 union tgsi_exec_channel *dst1,
730 const union tgsi_exec_channel *src0,
731 const union tgsi_exec_channel *src1 )
732 {
733 dst1->u[0] = src0->u[0] * src1->u[0];
734 dst1->u[1] = src0->u[1] * src1->u[1];
735 dst1->u[2] = src0->u[2] * src1->u[2];
736 dst1->u[3] = src0->u[3] * src1->u[3];
737 dst0->u[0] = 0;
738 dst0->u[1] = 0;
739 dst0->u[2] = 0;
740 dst0->u[3] = 0;
741 }
742
743 static void
744 micro_movc(
745 union tgsi_exec_channel *dst,
746 const union tgsi_exec_channel *src0,
747 const union tgsi_exec_channel *src1,
748 const union tgsi_exec_channel *src2 )
749 {
750 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
751 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
752 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
753 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
754 }
755
756 static void
757 micro_neg(
758 union tgsi_exec_channel *dst,
759 const union tgsi_exec_channel *src )
760 {
761 dst->f[0] = -src->f[0];
762 dst->f[1] = -src->f[1];
763 dst->f[2] = -src->f[2];
764 dst->f[3] = -src->f[3];
765 }
766
767 static void
768 micro_ineg(
769 union tgsi_exec_channel *dst,
770 const union tgsi_exec_channel *src )
771 {
772 dst->i[0] = -src->i[0];
773 dst->i[1] = -src->i[1];
774 dst->i[2] = -src->i[2];
775 dst->i[3] = -src->i[3];
776 }
777
778 static void
779 micro_not(
780 union tgsi_exec_channel *dst,
781 const union tgsi_exec_channel *src )
782 {
783 dst->u[0] = ~src->u[0];
784 dst->u[1] = ~src->u[1];
785 dst->u[2] = ~src->u[2];
786 dst->u[3] = ~src->u[3];
787 }
788
789 static void
790 micro_or(
791 union tgsi_exec_channel *dst,
792 const union tgsi_exec_channel *src0,
793 const union tgsi_exec_channel *src1 )
794 {
795 dst->u[0] = src0->u[0] | src1->u[0];
796 dst->u[1] = src0->u[1] | src1->u[1];
797 dst->u[2] = src0->u[2] | src1->u[2];
798 dst->u[3] = src0->u[3] | src1->u[3];
799 }
800
801 static void
802 micro_pow(
803 union tgsi_exec_channel *dst,
804 const union tgsi_exec_channel *src0,
805 const union tgsi_exec_channel *src1 )
806 {
807 #if FAST_MATH
808 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
809 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
810 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
811 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
812 #else
813 dst->f[0] = powf( src0->f[0], src1->f[0] );
814 dst->f[1] = powf( src0->f[1], src1->f[1] );
815 dst->f[2] = powf( src0->f[2], src1->f[2] );
816 dst->f[3] = powf( src0->f[3], src1->f[3] );
817 #endif
818 }
819
820 static void
821 micro_rnd(
822 union tgsi_exec_channel *dst,
823 const union tgsi_exec_channel *src )
824 {
825 dst->f[0] = floorf( src->f[0] + 0.5f );
826 dst->f[1] = floorf( src->f[1] + 0.5f );
827 dst->f[2] = floorf( src->f[2] + 0.5f );
828 dst->f[3] = floorf( src->f[3] + 0.5f );
829 }
830
831 static void
832 micro_shl(
833 union tgsi_exec_channel *dst,
834 const union tgsi_exec_channel *src0,
835 const union tgsi_exec_channel *src1 )
836 {
837 dst->i[0] = src0->i[0] << src1->i[0];
838 dst->i[1] = src0->i[1] << src1->i[1];
839 dst->i[2] = src0->i[2] << src1->i[2];
840 dst->i[3] = src0->i[3] << src1->i[3];
841 }
842
843 static void
844 micro_ishr(
845 union tgsi_exec_channel *dst,
846 const union tgsi_exec_channel *src0,
847 const union tgsi_exec_channel *src1 )
848 {
849 dst->i[0] = src0->i[0] >> src1->i[0];
850 dst->i[1] = src0->i[1] >> src1->i[1];
851 dst->i[2] = src0->i[2] >> src1->i[2];
852 dst->i[3] = src0->i[3] >> src1->i[3];
853 }
854
855 static void
856 micro_trunc(
857 union tgsi_exec_channel *dst,
858 const union tgsi_exec_channel *src0 )
859 {
860 dst->f[0] = (float) (int) src0->f[0];
861 dst->f[1] = (float) (int) src0->f[1];
862 dst->f[2] = (float) (int) src0->f[2];
863 dst->f[3] = (float) (int) src0->f[3];
864 }
865
866 static void
867 micro_ushr(
868 union tgsi_exec_channel *dst,
869 const union tgsi_exec_channel *src0,
870 const union tgsi_exec_channel *src1 )
871 {
872 dst->u[0] = src0->u[0] >> src1->u[0];
873 dst->u[1] = src0->u[1] >> src1->u[1];
874 dst->u[2] = src0->u[2] >> src1->u[2];
875 dst->u[3] = src0->u[3] >> src1->u[3];
876 }
877
878 static void
879 micro_sin(
880 union tgsi_exec_channel *dst,
881 const union tgsi_exec_channel *src )
882 {
883 dst->f[0] = sinf( src->f[0] );
884 dst->f[1] = sinf( src->f[1] );
885 dst->f[2] = sinf( src->f[2] );
886 dst->f[3] = sinf( src->f[3] );
887 }
888
889 static void
890 micro_sqrt( union tgsi_exec_channel *dst,
891 const union tgsi_exec_channel *src )
892 {
893 dst->f[0] = sqrtf( src->f[0] );
894 dst->f[1] = sqrtf( src->f[1] );
895 dst->f[2] = sqrtf( src->f[2] );
896 dst->f[3] = sqrtf( src->f[3] );
897 }
898
899 static void
900 micro_sub(
901 union tgsi_exec_channel *dst,
902 const union tgsi_exec_channel *src0,
903 const union tgsi_exec_channel *src1 )
904 {
905 dst->f[0] = src0->f[0] - src1->f[0];
906 dst->f[1] = src0->f[1] - src1->f[1];
907 dst->f[2] = src0->f[2] - src1->f[2];
908 dst->f[3] = src0->f[3] - src1->f[3];
909 }
910
911 static void
912 micro_u2f(
913 union tgsi_exec_channel *dst,
914 const union tgsi_exec_channel *src )
915 {
916 dst->f[0] = (float) src->u[0];
917 dst->f[1] = (float) src->u[1];
918 dst->f[2] = (float) src->u[2];
919 dst->f[3] = (float) src->u[3];
920 }
921
922 static void
923 micro_xor(
924 union tgsi_exec_channel *dst,
925 const union tgsi_exec_channel *src0,
926 const union tgsi_exec_channel *src1 )
927 {
928 dst->u[0] = src0->u[0] ^ src1->u[0];
929 dst->u[1] = src0->u[1] ^ src1->u[1];
930 dst->u[2] = src0->u[2] ^ src1->u[2];
931 dst->u[3] = src0->u[3] ^ src1->u[3];
932 }
933
934 static void
935 fetch_src_file_channel(
936 const struct tgsi_exec_machine *mach,
937 const uint file,
938 const uint swizzle,
939 const union tgsi_exec_channel *index,
940 union tgsi_exec_channel *chan )
941 {
942 switch( swizzle ) {
943 case TGSI_EXTSWIZZLE_X:
944 case TGSI_EXTSWIZZLE_Y:
945 case TGSI_EXTSWIZZLE_Z:
946 case TGSI_EXTSWIZZLE_W:
947 switch( file ) {
948 case TGSI_FILE_CONSTANT:
949 assert(mach->Consts);
950 assert(index->i[0] >= 0);
951 assert(index->i[1] >= 0);
952 assert(index->i[2] >= 0);
953 assert(index->i[3] >= 0);
954 chan->f[0] = mach->Consts[index->i[0]][swizzle];
955 chan->f[1] = mach->Consts[index->i[1]][swizzle];
956 chan->f[2] = mach->Consts[index->i[2]][swizzle];
957 chan->f[3] = mach->Consts[index->i[3]][swizzle];
958 break;
959
960 case TGSI_FILE_INPUT:
961 chan->u[0] = mach->Inputs[index->i[0]].xyzw[swizzle].u[0];
962 chan->u[1] = mach->Inputs[index->i[1]].xyzw[swizzle].u[1];
963 chan->u[2] = mach->Inputs[index->i[2]].xyzw[swizzle].u[2];
964 chan->u[3] = mach->Inputs[index->i[3]].xyzw[swizzle].u[3];
965 break;
966
967 case TGSI_FILE_TEMPORARY:
968 assert(index->i[0] < TGSI_EXEC_NUM_TEMPS);
969 chan->u[0] = mach->Temps[index->i[0]].xyzw[swizzle].u[0];
970 chan->u[1] = mach->Temps[index->i[1]].xyzw[swizzle].u[1];
971 chan->u[2] = mach->Temps[index->i[2]].xyzw[swizzle].u[2];
972 chan->u[3] = mach->Temps[index->i[3]].xyzw[swizzle].u[3];
973 break;
974
975 case TGSI_FILE_IMMEDIATE:
976 assert( index->i[0] < (int) mach->ImmLimit );
977 chan->f[0] = mach->Imms[index->i[0]][swizzle];
978 assert( index->i[1] < (int) mach->ImmLimit );
979 chan->f[1] = mach->Imms[index->i[1]][swizzle];
980 assert( index->i[2] < (int) mach->ImmLimit );
981 chan->f[2] = mach->Imms[index->i[2]][swizzle];
982 assert( index->i[3] < (int) mach->ImmLimit );
983 chan->f[3] = mach->Imms[index->i[3]][swizzle];
984 break;
985
986 case TGSI_FILE_ADDRESS:
987 chan->u[0] = mach->Addrs[index->i[0]].xyzw[swizzle].u[0];
988 chan->u[1] = mach->Addrs[index->i[1]].xyzw[swizzle].u[1];
989 chan->u[2] = mach->Addrs[index->i[2]].xyzw[swizzle].u[2];
990 chan->u[3] = mach->Addrs[index->i[3]].xyzw[swizzle].u[3];
991 break;
992
993 case TGSI_FILE_OUTPUT:
994 /* vertex/fragment output vars can be read too */
995 chan->u[0] = mach->Outputs[index->i[0]].xyzw[swizzle].u[0];
996 chan->u[1] = mach->Outputs[index->i[1]].xyzw[swizzle].u[1];
997 chan->u[2] = mach->Outputs[index->i[2]].xyzw[swizzle].u[2];
998 chan->u[3] = mach->Outputs[index->i[3]].xyzw[swizzle].u[3];
999 break;
1000
1001 default:
1002 assert( 0 );
1003 }
1004 break;
1005
1006 case TGSI_EXTSWIZZLE_ZERO:
1007 *chan = mach->Temps[TEMP_0_I].xyzw[TEMP_0_C];
1008 break;
1009
1010 case TGSI_EXTSWIZZLE_ONE:
1011 *chan = mach->Temps[TEMP_1_I].xyzw[TEMP_1_C];
1012 break;
1013
1014 default:
1015 assert( 0 );
1016 }
1017 }
1018
1019 static void
1020 fetch_source(
1021 const struct tgsi_exec_machine *mach,
1022 union tgsi_exec_channel *chan,
1023 const struct tgsi_full_src_register *reg,
1024 const uint chan_index )
1025 {
1026 union tgsi_exec_channel index;
1027 uint swizzle;
1028
1029 /* We start with a direct index into a register file.
1030 *
1031 * file[1],
1032 * where:
1033 * file = SrcRegister.File
1034 * [1] = SrcRegister.Index
1035 */
1036 index.i[0] =
1037 index.i[1] =
1038 index.i[2] =
1039 index.i[3] = reg->SrcRegister.Index;
1040
1041 /* There is an extra source register that indirectly subscripts
1042 * a register file. The direct index now becomes an offset
1043 * that is being added to the indirect register.
1044 *
1045 * file[ind[2].x+1],
1046 * where:
1047 * ind = SrcRegisterInd.File
1048 * [2] = SrcRegisterInd.Index
1049 * .x = SrcRegisterInd.SwizzleX
1050 */
1051 if (reg->SrcRegister.Indirect) {
1052 union tgsi_exec_channel index2;
1053 union tgsi_exec_channel indir_index;
1054 const uint execmask = mach->ExecMask;
1055 uint i;
1056
1057 /* which address register (always zero now) */
1058 index2.i[0] =
1059 index2.i[1] =
1060 index2.i[2] =
1061 index2.i[3] = reg->SrcRegisterInd.Index;
1062
1063 /* get current value of address register[swizzle] */
1064 swizzle = tgsi_util_get_src_register_swizzle( &reg->SrcRegisterInd, CHAN_X );
1065 fetch_src_file_channel(
1066 mach,
1067 reg->SrcRegisterInd.File,
1068 swizzle,
1069 &index2,
1070 &indir_index );
1071
1072 /* add value of address register to the offset */
1073 index.i[0] += (int) indir_index.f[0];
1074 index.i[1] += (int) indir_index.f[1];
1075 index.i[2] += (int) indir_index.f[2];
1076 index.i[3] += (int) indir_index.f[3];
1077
1078 /* for disabled execution channels, zero-out the index to
1079 * avoid using a potential garbage value.
1080 */
1081 for (i = 0; i < QUAD_SIZE; i++) {
1082 if ((execmask & (1 << i)) == 0)
1083 index.i[i] = 0;
1084 }
1085 }
1086
1087 /* There is an extra source register that is a second
1088 * subscript to a register file. Effectively it means that
1089 * the register file is actually a 2D array of registers.
1090 *
1091 * file[1][3] == file[1*sizeof(file[1])+3],
1092 * where:
1093 * [3] = SrcRegisterDim.Index
1094 */
1095 if (reg->SrcRegister.Dimension) {
1096 /* The size of the first-order array depends on the register file type.
1097 * We need to multiply the index to the first array to get an effective,
1098 * "flat" index that points to the beginning of the second-order array.
1099 */
1100 switch (reg->SrcRegister.File) {
1101 case TGSI_FILE_INPUT:
1102 index.i[0] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1103 index.i[1] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1104 index.i[2] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1105 index.i[3] *= TGSI_EXEC_MAX_INPUT_ATTRIBS;
1106 break;
1107 case TGSI_FILE_CONSTANT:
1108 index.i[0] *= TGSI_EXEC_MAX_CONST_BUFFER;
1109 index.i[1] *= TGSI_EXEC_MAX_CONST_BUFFER;
1110 index.i[2] *= TGSI_EXEC_MAX_CONST_BUFFER;
1111 index.i[3] *= TGSI_EXEC_MAX_CONST_BUFFER;
1112 break;
1113 default:
1114 assert( 0 );
1115 }
1116
1117 index.i[0] += reg->SrcRegisterDim.Index;
1118 index.i[1] += reg->SrcRegisterDim.Index;
1119 index.i[2] += reg->SrcRegisterDim.Index;
1120 index.i[3] += reg->SrcRegisterDim.Index;
1121
1122 /* Again, the second subscript index can be addressed indirectly
1123 * identically to the first one.
1124 * Nothing stops us from indirectly addressing the indirect register,
1125 * but there is no need for that, so we won't exercise it.
1126 *
1127 * file[1][ind[4].y+3],
1128 * where:
1129 * ind = SrcRegisterDimInd.File
1130 * [4] = SrcRegisterDimInd.Index
1131 * .y = SrcRegisterDimInd.SwizzleX
1132 */
1133 if (reg->SrcRegisterDim.Indirect) {
1134 union tgsi_exec_channel index2;
1135 union tgsi_exec_channel indir_index;
1136 const uint execmask = mach->ExecMask;
1137 uint i;
1138
1139 index2.i[0] =
1140 index2.i[1] =
1141 index2.i[2] =
1142 index2.i[3] = reg->SrcRegisterDimInd.Index;
1143
1144 swizzle = tgsi_util_get_src_register_swizzle( &reg->SrcRegisterDimInd, CHAN_X );
1145 fetch_src_file_channel(
1146 mach,
1147 reg->SrcRegisterDimInd.File,
1148 swizzle,
1149 &index2,
1150 &indir_index );
1151
1152 index.i[0] += (int) indir_index.f[0];
1153 index.i[1] += (int) indir_index.f[1];
1154 index.i[2] += (int) indir_index.f[2];
1155 index.i[3] += (int) indir_index.f[3];
1156
1157 /* for disabled execution channels, zero-out the index to
1158 * avoid using a potential garbage value.
1159 */
1160 for (i = 0; i < QUAD_SIZE; i++) {
1161 if ((execmask & (1 << i)) == 0)
1162 index.i[i] = 0;
1163 }
1164 }
1165
1166 /* If by any chance there was a need for a 3D array of register
1167 * files, we would have to check whether SrcRegisterDim is followed
1168 * by a dimension register and continue the saga.
1169 */
1170 }
1171
1172 swizzle = tgsi_util_get_full_src_register_extswizzle( reg, chan_index );
1173 fetch_src_file_channel(
1174 mach,
1175 reg->SrcRegister.File,
1176 swizzle,
1177 &index,
1178 chan );
1179
1180 switch (tgsi_util_get_full_src_register_sign_mode( reg, chan_index )) {
1181 case TGSI_UTIL_SIGN_CLEAR:
1182 micro_abs( chan, chan );
1183 break;
1184
1185 case TGSI_UTIL_SIGN_SET:
1186 micro_abs( chan, chan );
1187 micro_neg( chan, chan );
1188 break;
1189
1190 case TGSI_UTIL_SIGN_TOGGLE:
1191 micro_neg( chan, chan );
1192 break;
1193
1194 case TGSI_UTIL_SIGN_KEEP:
1195 break;
1196 }
1197
1198 if (reg->SrcRegisterExtMod.Complement) {
1199 micro_sub( chan, &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], chan );
1200 }
1201 }
1202
1203 static void
1204 store_dest(
1205 struct tgsi_exec_machine *mach,
1206 const union tgsi_exec_channel *chan,
1207 const struct tgsi_full_dst_register *reg,
1208 const struct tgsi_full_instruction *inst,
1209 uint chan_index )
1210 {
1211 uint i;
1212 union tgsi_exec_channel null;
1213 union tgsi_exec_channel *dst;
1214 uint execmask = mach->ExecMask;
1215
1216 switch (reg->DstRegister.File) {
1217 case TGSI_FILE_NULL:
1218 dst = &null;
1219 break;
1220
1221 case TGSI_FILE_OUTPUT:
1222 dst = &mach->Outputs[mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1223 + reg->DstRegister.Index].xyzw[chan_index];
1224 break;
1225
1226 case TGSI_FILE_TEMPORARY:
1227 assert( reg->DstRegister.Index < TGSI_EXEC_NUM_TEMPS );
1228 dst = &mach->Temps[reg->DstRegister.Index].xyzw[chan_index];
1229 break;
1230
1231 case TGSI_FILE_ADDRESS:
1232 dst = &mach->Addrs[reg->DstRegister.Index].xyzw[chan_index];
1233 break;
1234
1235 default:
1236 assert( 0 );
1237 return;
1238 }
1239
1240 if (inst->InstructionExtNv.CondFlowEnable) {
1241 union tgsi_exec_channel *cc = &mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C];
1242 uint swizzle;
1243 uint shift;
1244 uint mask;
1245 uint test;
1246
1247 /* Only CC0 supported.
1248 */
1249 assert( inst->InstructionExtNv.CondFlowIndex < 1 );
1250
1251 switch (chan_index) {
1252 case CHAN_X:
1253 swizzle = inst->InstructionExtNv.CondSwizzleX;
1254 break;
1255 case CHAN_Y:
1256 swizzle = inst->InstructionExtNv.CondSwizzleY;
1257 break;
1258 case CHAN_Z:
1259 swizzle = inst->InstructionExtNv.CondSwizzleZ;
1260 break;
1261 case CHAN_W:
1262 swizzle = inst->InstructionExtNv.CondSwizzleW;
1263 break;
1264 default:
1265 assert( 0 );
1266 return;
1267 }
1268
1269 switch (swizzle) {
1270 case TGSI_SWIZZLE_X:
1271 shift = TGSI_EXEC_CC_X_SHIFT;
1272 mask = TGSI_EXEC_CC_X_MASK;
1273 break;
1274 case TGSI_SWIZZLE_Y:
1275 shift = TGSI_EXEC_CC_Y_SHIFT;
1276 mask = TGSI_EXEC_CC_Y_MASK;
1277 break;
1278 case TGSI_SWIZZLE_Z:
1279 shift = TGSI_EXEC_CC_Z_SHIFT;
1280 mask = TGSI_EXEC_CC_Z_MASK;
1281 break;
1282 case TGSI_SWIZZLE_W:
1283 shift = TGSI_EXEC_CC_W_SHIFT;
1284 mask = TGSI_EXEC_CC_W_MASK;
1285 break;
1286 default:
1287 assert( 0 );
1288 return;
1289 }
1290
1291 switch (inst->InstructionExtNv.CondMask) {
1292 case TGSI_CC_GT:
1293 test = ~(TGSI_EXEC_CC_GT << shift) & mask;
1294 for (i = 0; i < QUAD_SIZE; i++)
1295 if (cc->u[i] & test)
1296 execmask &= ~(1 << i);
1297 break;
1298
1299 case TGSI_CC_EQ:
1300 test = ~(TGSI_EXEC_CC_EQ << shift) & mask;
1301 for (i = 0; i < QUAD_SIZE; i++)
1302 if (cc->u[i] & test)
1303 execmask &= ~(1 << i);
1304 break;
1305
1306 case TGSI_CC_LT:
1307 test = ~(TGSI_EXEC_CC_LT << shift) & mask;
1308 for (i = 0; i < QUAD_SIZE; i++)
1309 if (cc->u[i] & test)
1310 execmask &= ~(1 << i);
1311 break;
1312
1313 case TGSI_CC_GE:
1314 test = ~((TGSI_EXEC_CC_GT | TGSI_EXEC_CC_EQ) << shift) & mask;
1315 for (i = 0; i < QUAD_SIZE; i++)
1316 if (cc->u[i] & test)
1317 execmask &= ~(1 << i);
1318 break;
1319
1320 case TGSI_CC_LE:
1321 test = ~((TGSI_EXEC_CC_LT | TGSI_EXEC_CC_EQ) << shift) & mask;
1322 for (i = 0; i < QUAD_SIZE; i++)
1323 if (cc->u[i] & test)
1324 execmask &= ~(1 << i);
1325 break;
1326
1327 case TGSI_CC_NE:
1328 test = ~((TGSI_EXEC_CC_GT | TGSI_EXEC_CC_LT | TGSI_EXEC_CC_UN) << shift) & mask;
1329 for (i = 0; i < QUAD_SIZE; i++)
1330 if (cc->u[i] & test)
1331 execmask &= ~(1 << i);
1332 break;
1333
1334 case TGSI_CC_TR:
1335 break;
1336
1337 case TGSI_CC_FL:
1338 for (i = 0; i < QUAD_SIZE; i++)
1339 execmask &= ~(1 << i);
1340 break;
1341
1342 default:
1343 assert( 0 );
1344 return;
1345 }
1346 }
1347
1348 switch (inst->Instruction.Saturate) {
1349 case TGSI_SAT_NONE:
1350 for (i = 0; i < QUAD_SIZE; i++)
1351 if (execmask & (1 << i))
1352 dst->i[i] = chan->i[i];
1353 break;
1354
1355 case TGSI_SAT_ZERO_ONE:
1356 for (i = 0; i < QUAD_SIZE; i++)
1357 if (execmask & (1 << i)) {
1358 if (chan->f[i] < 0.0f)
1359 dst->f[i] = 0.0f;
1360 else if (chan->f[i] > 1.0f)
1361 dst->f[i] = 1.0f;
1362 else
1363 dst->i[i] = chan->i[i];
1364 }
1365 break;
1366
1367 case TGSI_SAT_MINUS_PLUS_ONE:
1368 for (i = 0; i < QUAD_SIZE; i++)
1369 if (execmask & (1 << i)) {
1370 if (chan->f[i] < -1.0f)
1371 dst->f[i] = -1.0f;
1372 else if (chan->f[i] > 1.0f)
1373 dst->f[i] = 1.0f;
1374 else
1375 dst->i[i] = chan->i[i];
1376 }
1377 break;
1378
1379 default:
1380 assert( 0 );
1381 }
1382
1383 if (inst->InstructionExtNv.CondDstUpdate) {
1384 union tgsi_exec_channel *cc = &mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C];
1385 uint shift;
1386 uint mask;
1387
1388 /* Only CC0 supported.
1389 */
1390 assert( inst->InstructionExtNv.CondDstIndex < 1 );
1391
1392 switch (chan_index) {
1393 case CHAN_X:
1394 shift = TGSI_EXEC_CC_X_SHIFT;
1395 mask = ~TGSI_EXEC_CC_X_MASK;
1396 break;
1397 case CHAN_Y:
1398 shift = TGSI_EXEC_CC_Y_SHIFT;
1399 mask = ~TGSI_EXEC_CC_Y_MASK;
1400 break;
1401 case CHAN_Z:
1402 shift = TGSI_EXEC_CC_Z_SHIFT;
1403 mask = ~TGSI_EXEC_CC_Z_MASK;
1404 break;
1405 case CHAN_W:
1406 shift = TGSI_EXEC_CC_W_SHIFT;
1407 mask = ~TGSI_EXEC_CC_W_MASK;
1408 break;
1409 default:
1410 assert( 0 );
1411 return;
1412 }
1413
1414 for (i = 0; i < QUAD_SIZE; i++)
1415 if (execmask & (1 << i)) {
1416 cc->u[i] &= mask;
1417 if (dst->f[i] < 0.0f)
1418 cc->u[i] |= TGSI_EXEC_CC_LT << shift;
1419 else if (dst->f[i] > 0.0f)
1420 cc->u[i] |= TGSI_EXEC_CC_GT << shift;
1421 else if (dst->f[i] == 0.0f)
1422 cc->u[i] |= TGSI_EXEC_CC_EQ << shift;
1423 else
1424 cc->u[i] |= TGSI_EXEC_CC_UN << shift;
1425 }
1426 }
1427 }
1428
1429 #define FETCH(VAL,INDEX,CHAN)\
1430 fetch_source (mach, VAL, &inst->FullSrcRegisters[INDEX], CHAN)
1431
1432 #define STORE(VAL,INDEX,CHAN)\
1433 store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN )
1434
1435
1436 /**
1437 * Execute ARB-style KIL which is predicated by a src register.
1438 * Kill fragment if any of the four values is less than zero.
1439 */
1440 static void
1441 exec_kil(struct tgsi_exec_machine *mach,
1442 const struct tgsi_full_instruction *inst)
1443 {
1444 uint uniquemask;
1445 uint chan_index;
1446 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1447 union tgsi_exec_channel r[1];
1448
1449 /* This mask stores component bits that were already tested. Note that
1450 * we test if the value is less than zero, so 1.0 and 0.0 need not to be
1451 * tested. */
1452 uniquemask = (1 << TGSI_EXTSWIZZLE_ZERO) | (1 << TGSI_EXTSWIZZLE_ONE);
1453
1454 for (chan_index = 0; chan_index < 4; chan_index++)
1455 {
1456 uint swizzle;
1457 uint i;
1458
1459 /* unswizzle channel */
1460 swizzle = tgsi_util_get_full_src_register_extswizzle (
1461 &inst->FullSrcRegisters[0],
1462 chan_index);
1463
1464 /* check if the component has not been already tested */
1465 if (uniquemask & (1 << swizzle))
1466 continue;
1467 uniquemask |= 1 << swizzle;
1468
1469 FETCH(&r[0], 0, chan_index);
1470 for (i = 0; i < 4; i++)
1471 if (r[0].f[i] < 0.0f)
1472 kilmask |= 1 << i;
1473 }
1474
1475 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1476 }
1477
1478 /**
1479 * Execute NVIDIA-style KIL which is predicated by a condition code.
1480 * Kill fragment if the condition code is TRUE.
1481 */
1482 static void
1483 exec_kilp(struct tgsi_exec_machine *mach,
1484 const struct tgsi_full_instruction *inst)
1485 {
1486 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1487
1488 if (inst->InstructionExtNv.CondFlowEnable) {
1489 uint swizzle[4];
1490 uint chan_index;
1491
1492 kilmask = 0x0;
1493
1494 swizzle[0] = inst->InstructionExtNv.CondSwizzleX;
1495 swizzle[1] = inst->InstructionExtNv.CondSwizzleY;
1496 swizzle[2] = inst->InstructionExtNv.CondSwizzleZ;
1497 swizzle[3] = inst->InstructionExtNv.CondSwizzleW;
1498
1499 for (chan_index = 0; chan_index < 4; chan_index++)
1500 {
1501 uint i;
1502
1503 for (i = 0; i < 4; i++) {
1504 /* TODO: evaluate the condition code */
1505 if (0)
1506 kilmask |= 1 << i;
1507 }
1508 }
1509 }
1510 else {
1511 /* "unconditional" kil */
1512 kilmask = mach->ExecMask;
1513 }
1514 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1515 }
1516
1517
1518 /*
1519 * Fetch a texel using STR texture coordinates.
1520 */
1521 static void
1522 fetch_texel( struct tgsi_sampler *sampler,
1523 const union tgsi_exec_channel *s,
1524 const union tgsi_exec_channel *t,
1525 const union tgsi_exec_channel *p,
1526 float lodbias, /* XXX should be float[4] */
1527 union tgsi_exec_channel *r,
1528 union tgsi_exec_channel *g,
1529 union tgsi_exec_channel *b,
1530 union tgsi_exec_channel *a )
1531 {
1532 uint j;
1533 float rgba[NUM_CHANNELS][QUAD_SIZE];
1534
1535 sampler->get_samples(sampler, s->f, t->f, p->f, lodbias, rgba);
1536
1537 for (j = 0; j < 4; j++) {
1538 r->f[j] = rgba[0][j];
1539 g->f[j] = rgba[1][j];
1540 b->f[j] = rgba[2][j];
1541 a->f[j] = rgba[3][j];
1542 }
1543 }
1544
1545
1546 static void
1547 exec_tex(struct tgsi_exec_machine *mach,
1548 const struct tgsi_full_instruction *inst,
1549 boolean biasLod,
1550 boolean projected)
1551 {
1552 const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
1553 union tgsi_exec_channel r[8];
1554 uint chan_index;
1555 float lodBias;
1556
1557 /* debug_printf("Sampler %u unit %u\n", sampler, unit); */
1558
1559 switch (inst->InstructionExtTexture.Texture) {
1560 case TGSI_TEXTURE_1D:
1561
1562 FETCH(&r[0], 0, CHAN_X);
1563
1564 if (projected) {
1565 FETCH(&r[1], 0, CHAN_W);
1566 micro_div( &r[0], &r[0], &r[1] );
1567 }
1568
1569 if (biasLod) {
1570 FETCH(&r[1], 0, CHAN_W);
1571 lodBias = r[2].f[0];
1572 }
1573 else
1574 lodBias = 0.0;
1575
1576 fetch_texel(&mach->Samplers[unit],
1577 &r[0], NULL, NULL, lodBias, /* S, T, P, BIAS */
1578 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1579 break;
1580
1581 case TGSI_TEXTURE_2D:
1582 case TGSI_TEXTURE_RECT:
1583
1584 FETCH(&r[0], 0, CHAN_X);
1585 FETCH(&r[1], 0, CHAN_Y);
1586 FETCH(&r[2], 0, CHAN_Z);
1587
1588 if (projected) {
1589 FETCH(&r[3], 0, CHAN_W);
1590 micro_div( &r[0], &r[0], &r[3] );
1591 micro_div( &r[1], &r[1], &r[3] );
1592 micro_div( &r[2], &r[2], &r[3] );
1593 }
1594
1595 if (biasLod) {
1596 FETCH(&r[3], 0, CHAN_W);
1597 lodBias = r[3].f[0];
1598 }
1599 else
1600 lodBias = 0.0;
1601
1602 fetch_texel(&mach->Samplers[unit],
1603 &r[0], &r[1], &r[2], lodBias, /* inputs */
1604 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1605 break;
1606
1607 case TGSI_TEXTURE_3D:
1608 case TGSI_TEXTURE_CUBE:
1609
1610 FETCH(&r[0], 0, CHAN_X);
1611 FETCH(&r[1], 0, CHAN_Y);
1612 FETCH(&r[2], 0, CHAN_Z);
1613
1614 if (projected) {
1615 FETCH(&r[3], 0, CHAN_W);
1616 micro_div( &r[0], &r[0], &r[3] );
1617 micro_div( &r[1], &r[1], &r[3] );
1618 micro_div( &r[2], &r[2], &r[3] );
1619 }
1620
1621 if (biasLod) {
1622 FETCH(&r[3], 0, CHAN_W);
1623 lodBias = r[3].f[0];
1624 }
1625 else
1626 lodBias = 0.0;
1627
1628 fetch_texel(&mach->Samplers[unit],
1629 &r[0], &r[1], &r[2], lodBias,
1630 &r[0], &r[1], &r[2], &r[3]);
1631 break;
1632
1633 default:
1634 assert (0);
1635 }
1636
1637 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1638 STORE( &r[chan_index], 0, chan_index );
1639 }
1640 }
1641
1642
1643 /**
1644 * Evaluate a constant-valued coefficient at the position of the
1645 * current quad.
1646 */
1647 static void
1648 eval_constant_coef(
1649 struct tgsi_exec_machine *mach,
1650 unsigned attrib,
1651 unsigned chan )
1652 {
1653 unsigned i;
1654
1655 for( i = 0; i < QUAD_SIZE; i++ ) {
1656 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
1657 }
1658 }
1659
1660 /**
1661 * Evaluate a linear-valued coefficient at the position of the
1662 * current quad.
1663 */
1664 static void
1665 eval_linear_coef(
1666 struct tgsi_exec_machine *mach,
1667 unsigned attrib,
1668 unsigned chan )
1669 {
1670 const float x = mach->QuadPos.xyzw[0].f[0];
1671 const float y = mach->QuadPos.xyzw[1].f[0];
1672 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1673 const float dady = mach->InterpCoefs[attrib].dady[chan];
1674 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1675 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
1676 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
1677 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
1678 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
1679 }
1680
1681 /**
1682 * Evaluate a perspective-valued coefficient at the position of the
1683 * current quad.
1684 */
1685 static void
1686 eval_perspective_coef(
1687 struct tgsi_exec_machine *mach,
1688 unsigned attrib,
1689 unsigned chan )
1690 {
1691 const float x = mach->QuadPos.xyzw[0].f[0];
1692 const float y = mach->QuadPos.xyzw[1].f[0];
1693 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1694 const float dady = mach->InterpCoefs[attrib].dady[chan];
1695 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1696 const float *w = mach->QuadPos.xyzw[3].f;
1697 /* divide by W here */
1698 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
1699 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
1700 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
1701 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
1702 }
1703
1704
1705 typedef void (* eval_coef_func)(
1706 struct tgsi_exec_machine *mach,
1707 unsigned attrib,
1708 unsigned chan );
1709
1710 static void
1711 exec_declaration(
1712 struct tgsi_exec_machine *mach,
1713 const struct tgsi_full_declaration *decl )
1714 {
1715 if( mach->Processor == TGSI_PROCESSOR_FRAGMENT ) {
1716 if( decl->Declaration.File == TGSI_FILE_INPUT ) {
1717 unsigned first, last, mask;
1718 eval_coef_func eval;
1719
1720 first = decl->DeclarationRange.First;
1721 last = decl->DeclarationRange.Last;
1722 mask = decl->Declaration.UsageMask;
1723
1724 switch( decl->Declaration.Interpolate ) {
1725 case TGSI_INTERPOLATE_CONSTANT:
1726 eval = eval_constant_coef;
1727 break;
1728
1729 case TGSI_INTERPOLATE_LINEAR:
1730 eval = eval_linear_coef;
1731 break;
1732
1733 case TGSI_INTERPOLATE_PERSPECTIVE:
1734 eval = eval_perspective_coef;
1735 break;
1736
1737 default:
1738 eval = NULL;
1739 assert( 0 );
1740 }
1741
1742 if( mask == TGSI_WRITEMASK_XYZW ) {
1743 unsigned i, j;
1744
1745 for( i = first; i <= last; i++ ) {
1746 for( j = 0; j < NUM_CHANNELS; j++ ) {
1747 eval( mach, i, j );
1748 }
1749 }
1750 }
1751 else {
1752 unsigned i, j;
1753
1754 for( j = 0; j < NUM_CHANNELS; j++ ) {
1755 if( mask & (1 << j) ) {
1756 for( i = first; i <= last; i++ ) {
1757 eval( mach, i, j );
1758 }
1759 }
1760 }
1761 }
1762 }
1763 }
1764 }
1765
1766 static void
1767 exec_instruction(
1768 struct tgsi_exec_machine *mach,
1769 const struct tgsi_full_instruction *inst,
1770 int *pc )
1771 {
1772 uint chan_index;
1773 union tgsi_exec_channel r[8];
1774
1775 (*pc)++;
1776
1777 switch (inst->Instruction.Opcode) {
1778 case TGSI_OPCODE_ARL:
1779 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1780 FETCH( &r[0], 0, chan_index );
1781 micro_trunc( &r[0], &r[0] );
1782 STORE( &r[0], 0, chan_index );
1783 }
1784 break;
1785
1786 case TGSI_OPCODE_MOV:
1787 case TGSI_OPCODE_SWZ:
1788 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1789 FETCH( &r[0], 0, chan_index );
1790 STORE( &r[0], 0, chan_index );
1791 }
1792 break;
1793
1794 case TGSI_OPCODE_LIT:
1795 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
1796 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X );
1797 }
1798
1799 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y ) || IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1800 FETCH( &r[0], 0, CHAN_X );
1801 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
1802 micro_max( &r[0], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
1803 STORE( &r[0], 0, CHAN_Y );
1804 }
1805
1806 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1807 FETCH( &r[1], 0, CHAN_Y );
1808 micro_max( &r[1], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
1809
1810 FETCH( &r[2], 0, CHAN_W );
1811 micro_min( &r[2], &r[2], &mach->Temps[TEMP_128_I].xyzw[TEMP_128_C] );
1812 micro_max( &r[2], &r[2], &mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C] );
1813 micro_pow( &r[1], &r[1], &r[2] );
1814 micro_lt( &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
1815 STORE( &r[0], 0, CHAN_Z );
1816 }
1817 }
1818
1819 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
1820 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
1821 }
1822 break;
1823
1824 case TGSI_OPCODE_RCP:
1825 /* TGSI_OPCODE_RECIP */
1826 FETCH( &r[0], 0, CHAN_X );
1827 micro_div( &r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0] );
1828 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1829 STORE( &r[0], 0, chan_index );
1830 }
1831 break;
1832
1833 case TGSI_OPCODE_RSQ:
1834 /* TGSI_OPCODE_RECIPSQRT */
1835 FETCH( &r[0], 0, CHAN_X );
1836 micro_sqrt( &r[0], &r[0] );
1837 micro_div( &r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0] );
1838 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1839 STORE( &r[0], 0, chan_index );
1840 }
1841 break;
1842
1843 case TGSI_OPCODE_EXP:
1844 FETCH( &r[0], 0, CHAN_X );
1845 micro_flr( &r[1], &r[0] ); /* r1 = floor(r0) */
1846 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
1847 micro_exp2( &r[2], &r[1] ); /* r2 = 2 ^ r1 */
1848 STORE( &r[2], 0, CHAN_X ); /* store r2 */
1849 }
1850 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
1851 micro_sub( &r[2], &r[0], &r[1] ); /* r2 = r0 - r1 */
1852 STORE( &r[2], 0, CHAN_Y ); /* store r2 */
1853 }
1854 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1855 micro_exp2( &r[2], &r[0] ); /* r2 = 2 ^ r0 */
1856 STORE( &r[2], 0, CHAN_Z ); /* store r2 */
1857 }
1858 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
1859 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
1860 }
1861 break;
1862
1863 case TGSI_OPCODE_LOG:
1864 FETCH( &r[0], 0, CHAN_X );
1865 micro_abs( &r[2], &r[0] ); /* r2 = abs(r0) */
1866 micro_lg2( &r[1], &r[2] ); /* r1 = lg2(r2) */
1867 micro_flr( &r[0], &r[1] ); /* r0 = floor(r1) */
1868 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
1869 STORE( &r[0], 0, CHAN_X );
1870 }
1871 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
1872 micro_exp2( &r[0], &r[0] ); /* r0 = 2 ^ r0 */
1873 micro_div( &r[0], &r[2], &r[0] ); /* r0 = r2 / r0 */
1874 STORE( &r[0], 0, CHAN_Y );
1875 }
1876 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1877 STORE( &r[1], 0, CHAN_Z );
1878 }
1879 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
1880 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
1881 }
1882 break;
1883
1884 case TGSI_OPCODE_MUL:
1885 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index )
1886 {
1887 FETCH(&r[0], 0, chan_index);
1888 FETCH(&r[1], 1, chan_index);
1889
1890 micro_mul( &r[0], &r[0], &r[1] );
1891
1892 STORE(&r[0], 0, chan_index);
1893 }
1894 break;
1895
1896 case TGSI_OPCODE_ADD:
1897 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1898 FETCH( &r[0], 0, chan_index );
1899 FETCH( &r[1], 1, chan_index );
1900 micro_add( &r[0], &r[0], &r[1] );
1901 STORE( &r[0], 0, chan_index );
1902 }
1903 break;
1904
1905 case TGSI_OPCODE_DP3:
1906 /* TGSI_OPCODE_DOT3 */
1907 FETCH( &r[0], 0, CHAN_X );
1908 FETCH( &r[1], 1, CHAN_X );
1909 micro_mul( &r[0], &r[0], &r[1] );
1910
1911 FETCH( &r[1], 0, CHAN_Y );
1912 FETCH( &r[2], 1, CHAN_Y );
1913 micro_mul( &r[1], &r[1], &r[2] );
1914 micro_add( &r[0], &r[0], &r[1] );
1915
1916 FETCH( &r[1], 0, CHAN_Z );
1917 FETCH( &r[2], 1, CHAN_Z );
1918 micro_mul( &r[1], &r[1], &r[2] );
1919 micro_add( &r[0], &r[0], &r[1] );
1920
1921 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1922 STORE( &r[0], 0, chan_index );
1923 }
1924 break;
1925
1926 case TGSI_OPCODE_DP4:
1927 /* TGSI_OPCODE_DOT4 */
1928 FETCH(&r[0], 0, CHAN_X);
1929 FETCH(&r[1], 1, CHAN_X);
1930
1931 micro_mul( &r[0], &r[0], &r[1] );
1932
1933 FETCH(&r[1], 0, CHAN_Y);
1934 FETCH(&r[2], 1, CHAN_Y);
1935
1936 micro_mul( &r[1], &r[1], &r[2] );
1937 micro_add( &r[0], &r[0], &r[1] );
1938
1939 FETCH(&r[1], 0, CHAN_Z);
1940 FETCH(&r[2], 1, CHAN_Z);
1941
1942 micro_mul( &r[1], &r[1], &r[2] );
1943 micro_add( &r[0], &r[0], &r[1] );
1944
1945 FETCH(&r[1], 0, CHAN_W);
1946 FETCH(&r[2], 1, CHAN_W);
1947
1948 micro_mul( &r[1], &r[1], &r[2] );
1949 micro_add( &r[0], &r[0], &r[1] );
1950
1951 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1952 STORE( &r[0], 0, chan_index );
1953 }
1954 break;
1955
1956 case TGSI_OPCODE_DST:
1957 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
1958 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X );
1959 }
1960
1961 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
1962 FETCH( &r[0], 0, CHAN_Y );
1963 FETCH( &r[1], 1, CHAN_Y);
1964 micro_mul( &r[0], &r[0], &r[1] );
1965 STORE( &r[0], 0, CHAN_Y );
1966 }
1967
1968 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
1969 FETCH( &r[0], 0, CHAN_Z );
1970 STORE( &r[0], 0, CHAN_Z );
1971 }
1972
1973 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
1974 FETCH( &r[0], 1, CHAN_W );
1975 STORE( &r[0], 0, CHAN_W );
1976 }
1977 break;
1978
1979 case TGSI_OPCODE_MIN:
1980 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1981 FETCH(&r[0], 0, chan_index);
1982 FETCH(&r[1], 1, chan_index);
1983
1984 /* XXX use micro_min()?? */
1985 micro_lt( &r[0], &r[0], &r[1], &r[0], &r[1] );
1986
1987 STORE(&r[0], 0, chan_index);
1988 }
1989 break;
1990
1991 case TGSI_OPCODE_MAX:
1992 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
1993 FETCH(&r[0], 0, chan_index);
1994 FETCH(&r[1], 1, chan_index);
1995
1996 /* XXX use micro_max()?? */
1997 micro_lt( &r[0], &r[0], &r[1], &r[1], &r[0] );
1998
1999 STORE(&r[0], 0, chan_index );
2000 }
2001 break;
2002
2003 case TGSI_OPCODE_SLT:
2004 /* TGSI_OPCODE_SETLT */
2005 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2006 FETCH( &r[0], 0, chan_index );
2007 FETCH( &r[1], 1, chan_index );
2008 micro_lt( &r[0], &r[0], &r[1], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2009 STORE( &r[0], 0, chan_index );
2010 }
2011 break;
2012
2013 case TGSI_OPCODE_SGE:
2014 /* TGSI_OPCODE_SETGE */
2015 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2016 FETCH( &r[0], 0, chan_index );
2017 FETCH( &r[1], 1, chan_index );
2018 micro_ge( &r[0], &r[0], &r[1], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2019 STORE( &r[0], 0, chan_index );
2020 }
2021 break;
2022
2023 case TGSI_OPCODE_MAD:
2024 /* TGSI_OPCODE_MADD */
2025 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2026 FETCH( &r[0], 0, chan_index );
2027 FETCH( &r[1], 1, chan_index );
2028 micro_mul( &r[0], &r[0], &r[1] );
2029 FETCH( &r[1], 2, chan_index );
2030 micro_add( &r[0], &r[0], &r[1] );
2031 STORE( &r[0], 0, chan_index );
2032 }
2033 break;
2034
2035 case TGSI_OPCODE_SUB:
2036 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2037 FETCH(&r[0], 0, chan_index);
2038 FETCH(&r[1], 1, chan_index);
2039
2040 micro_sub( &r[0], &r[0], &r[1] );
2041
2042 STORE(&r[0], 0, chan_index);
2043 }
2044 break;
2045
2046 case TGSI_OPCODE_LERP:
2047 /* TGSI_OPCODE_LRP */
2048 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2049 FETCH(&r[0], 0, chan_index);
2050 FETCH(&r[1], 1, chan_index);
2051 FETCH(&r[2], 2, chan_index);
2052
2053 micro_sub( &r[1], &r[1], &r[2] );
2054 micro_mul( &r[0], &r[0], &r[1] );
2055 micro_add( &r[0], &r[0], &r[2] );
2056
2057 STORE(&r[0], 0, chan_index);
2058 }
2059 break;
2060
2061 case TGSI_OPCODE_CND:
2062 assert (0);
2063 break;
2064
2065 case TGSI_OPCODE_CND0:
2066 assert (0);
2067 break;
2068
2069 case TGSI_OPCODE_DOT2ADD:
2070 /* TGSI_OPCODE_DP2A */
2071 FETCH( &r[0], 0, CHAN_X );
2072 FETCH( &r[1], 1, CHAN_X );
2073 micro_mul( &r[0], &r[0], &r[1] );
2074
2075 FETCH( &r[1], 0, CHAN_Y );
2076 FETCH( &r[2], 1, CHAN_Y );
2077 micro_mul( &r[1], &r[1], &r[2] );
2078 micro_add( &r[0], &r[0], &r[1] );
2079
2080 FETCH( &r[2], 2, CHAN_X );
2081 micro_add( &r[0], &r[0], &r[2] );
2082
2083 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2084 STORE( &r[0], 0, chan_index );
2085 }
2086 break;
2087
2088 case TGSI_OPCODE_INDEX:
2089 assert (0);
2090 break;
2091
2092 case TGSI_OPCODE_NEGATE:
2093 assert (0);
2094 break;
2095
2096 case TGSI_OPCODE_FRAC:
2097 /* TGSI_OPCODE_FRC */
2098 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2099 FETCH( &r[0], 0, chan_index );
2100 micro_frc( &r[0], &r[0] );
2101 STORE( &r[0], 0, chan_index );
2102 }
2103 break;
2104
2105 case TGSI_OPCODE_CLAMP:
2106 assert (0);
2107 break;
2108
2109 case TGSI_OPCODE_FLOOR:
2110 /* TGSI_OPCODE_FLR */
2111 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2112 FETCH( &r[0], 0, chan_index );
2113 micro_flr( &r[0], &r[0] );
2114 STORE( &r[0], 0, chan_index );
2115 }
2116 break;
2117
2118 case TGSI_OPCODE_ROUND:
2119 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2120 FETCH( &r[0], 0, chan_index );
2121 micro_rnd( &r[0], &r[0] );
2122 STORE( &r[0], 0, chan_index );
2123 }
2124 break;
2125
2126 case TGSI_OPCODE_EXPBASE2:
2127 /* TGSI_OPCODE_EX2 */
2128 FETCH(&r[0], 0, CHAN_X);
2129
2130 #if FAST_MATH
2131 micro_exp2( &r[0], &r[0] );
2132 #else
2133 micro_pow( &r[0], &mach->Temps[TEMP_2_I].xyzw[TEMP_2_C], &r[0] );
2134 #endif
2135
2136 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2137 STORE( &r[0], 0, chan_index );
2138 }
2139 break;
2140
2141 case TGSI_OPCODE_LOGBASE2:
2142 /* TGSI_OPCODE_LG2 */
2143 FETCH( &r[0], 0, CHAN_X );
2144 micro_lg2( &r[0], &r[0] );
2145 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2146 STORE( &r[0], 0, chan_index );
2147 }
2148 break;
2149
2150 case TGSI_OPCODE_POWER:
2151 /* TGSI_OPCODE_POW */
2152 FETCH(&r[0], 0, CHAN_X);
2153 FETCH(&r[1], 1, CHAN_X);
2154
2155 micro_pow( &r[0], &r[0], &r[1] );
2156
2157 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2158 STORE( &r[0], 0, chan_index );
2159 }
2160 break;
2161
2162 case TGSI_OPCODE_CROSSPRODUCT:
2163 /* TGSI_OPCODE_XPD */
2164 FETCH(&r[0], 0, CHAN_Y);
2165 FETCH(&r[1], 1, CHAN_Z);
2166
2167 micro_mul( &r[2], &r[0], &r[1] );
2168
2169 FETCH(&r[3], 0, CHAN_Z);
2170 FETCH(&r[4], 1, CHAN_Y);
2171
2172 micro_mul( &r[5], &r[3], &r[4] );
2173 micro_sub( &r[2], &r[2], &r[5] );
2174
2175 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2176 STORE( &r[2], 0, CHAN_X );
2177 }
2178
2179 FETCH(&r[2], 1, CHAN_X);
2180
2181 micro_mul( &r[3], &r[3], &r[2] );
2182
2183 FETCH(&r[5], 0, CHAN_X);
2184
2185 micro_mul( &r[1], &r[1], &r[5] );
2186 micro_sub( &r[3], &r[3], &r[1] );
2187
2188 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2189 STORE( &r[3], 0, CHAN_Y );
2190 }
2191
2192 micro_mul( &r[5], &r[5], &r[4] );
2193 micro_mul( &r[0], &r[0], &r[2] );
2194 micro_sub( &r[5], &r[5], &r[0] );
2195
2196 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2197 STORE( &r[5], 0, CHAN_Z );
2198 }
2199
2200 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2201 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2202 }
2203 break;
2204
2205 case TGSI_OPCODE_MULTIPLYMATRIX:
2206 assert (0);
2207 break;
2208
2209 case TGSI_OPCODE_ABS:
2210 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2211 FETCH(&r[0], 0, chan_index);
2212
2213 micro_abs( &r[0], &r[0] );
2214
2215 STORE(&r[0], 0, chan_index);
2216 }
2217 break;
2218
2219 case TGSI_OPCODE_RCC:
2220 assert (0);
2221 break;
2222
2223 case TGSI_OPCODE_DPH:
2224 FETCH(&r[0], 0, CHAN_X);
2225 FETCH(&r[1], 1, CHAN_X);
2226
2227 micro_mul( &r[0], &r[0], &r[1] );
2228
2229 FETCH(&r[1], 0, CHAN_Y);
2230 FETCH(&r[2], 1, CHAN_Y);
2231
2232 micro_mul( &r[1], &r[1], &r[2] );
2233 micro_add( &r[0], &r[0], &r[1] );
2234
2235 FETCH(&r[1], 0, CHAN_Z);
2236 FETCH(&r[2], 1, CHAN_Z);
2237
2238 micro_mul( &r[1], &r[1], &r[2] );
2239 micro_add( &r[0], &r[0], &r[1] );
2240
2241 FETCH(&r[1], 1, CHAN_W);
2242
2243 micro_add( &r[0], &r[0], &r[1] );
2244
2245 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2246 STORE( &r[0], 0, chan_index );
2247 }
2248 break;
2249
2250 case TGSI_OPCODE_COS:
2251 FETCH(&r[0], 0, CHAN_X);
2252
2253 micro_cos( &r[0], &r[0] );
2254
2255 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2256 STORE( &r[0], 0, chan_index );
2257 }
2258 break;
2259
2260 case TGSI_OPCODE_DDX:
2261 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2262 FETCH( &r[0], 0, chan_index );
2263 micro_ddx( &r[0], &r[0] );
2264 STORE( &r[0], 0, chan_index );
2265 }
2266 break;
2267
2268 case TGSI_OPCODE_DDY:
2269 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2270 FETCH( &r[0], 0, chan_index );
2271 micro_ddy( &r[0], &r[0] );
2272 STORE( &r[0], 0, chan_index );
2273 }
2274 break;
2275
2276 case TGSI_OPCODE_KILP:
2277 exec_kilp (mach, inst);
2278 break;
2279
2280 case TGSI_OPCODE_KIL:
2281 exec_kil (mach, inst);
2282 break;
2283
2284 case TGSI_OPCODE_PK2H:
2285 assert (0);
2286 break;
2287
2288 case TGSI_OPCODE_PK2US:
2289 assert (0);
2290 break;
2291
2292 case TGSI_OPCODE_PK4B:
2293 assert (0);
2294 break;
2295
2296 case TGSI_OPCODE_PK4UB:
2297 assert (0);
2298 break;
2299
2300 case TGSI_OPCODE_RFL:
2301 assert (0);
2302 break;
2303
2304 case TGSI_OPCODE_SEQ:
2305 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2306 FETCH( &r[0], 0, chan_index );
2307 FETCH( &r[1], 1, chan_index );
2308 micro_eq( &r[0], &r[0], &r[1],
2309 &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C],
2310 &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2311 STORE( &r[0], 0, chan_index );
2312 }
2313 break;
2314
2315 case TGSI_OPCODE_SFL:
2316 assert (0);
2317 break;
2318
2319 case TGSI_OPCODE_SGT:
2320 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2321 FETCH( &r[0], 0, chan_index );
2322 FETCH( &r[1], 1, chan_index );
2323 micro_le( &r[0], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C] );
2324 STORE( &r[0], 0, chan_index );
2325 }
2326 break;
2327
2328 case TGSI_OPCODE_SIN:
2329 FETCH( &r[0], 0, CHAN_X );
2330 micro_sin( &r[0], &r[0] );
2331 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2332 STORE( &r[0], 0, chan_index );
2333 }
2334 break;
2335
2336 case TGSI_OPCODE_SLE:
2337 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2338 FETCH( &r[0], 0, chan_index );
2339 FETCH( &r[1], 1, chan_index );
2340 micro_le( &r[0], &r[0], &r[1], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2341 STORE( &r[0], 0, chan_index );
2342 }
2343 break;
2344
2345 case TGSI_OPCODE_SNE:
2346 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2347 FETCH( &r[0], 0, chan_index );
2348 FETCH( &r[1], 1, chan_index );
2349 micro_eq( &r[0], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C] );
2350 STORE( &r[0], 0, chan_index );
2351 }
2352 break;
2353
2354 case TGSI_OPCODE_STR:
2355 assert (0);
2356 break;
2357
2358 case TGSI_OPCODE_TEX:
2359 /* simple texture lookup */
2360 /* src[0] = texcoord */
2361 /* src[1] = sampler unit */
2362 exec_tex(mach, inst, FALSE, FALSE);
2363 break;
2364
2365 case TGSI_OPCODE_TXB:
2366 /* Texture lookup with lod bias */
2367 /* src[0] = texcoord (src[0].w = LOD bias) */
2368 /* src[1] = sampler unit */
2369 exec_tex(mach, inst, TRUE, FALSE);
2370 break;
2371
2372 case TGSI_OPCODE_TXD:
2373 /* Texture lookup with explict partial derivatives */
2374 /* src[0] = texcoord */
2375 /* src[1] = d[strq]/dx */
2376 /* src[2] = d[strq]/dy */
2377 /* src[3] = sampler unit */
2378 assert (0);
2379 break;
2380
2381 case TGSI_OPCODE_TXL:
2382 /* Texture lookup with explit LOD */
2383 /* src[0] = texcoord (src[0].w = LOD) */
2384 /* src[1] = sampler unit */
2385 exec_tex(mach, inst, TRUE, FALSE);
2386 break;
2387
2388 case TGSI_OPCODE_TXP:
2389 /* Texture lookup with projection */
2390 /* src[0] = texcoord (src[0].w = projection) */
2391 /* src[1] = sampler unit */
2392 exec_tex(mach, inst, FALSE, TRUE);
2393 break;
2394
2395 case TGSI_OPCODE_UP2H:
2396 assert (0);
2397 break;
2398
2399 case TGSI_OPCODE_UP2US:
2400 assert (0);
2401 break;
2402
2403 case TGSI_OPCODE_UP4B:
2404 assert (0);
2405 break;
2406
2407 case TGSI_OPCODE_UP4UB:
2408 assert (0);
2409 break;
2410
2411 case TGSI_OPCODE_X2D:
2412 assert (0);
2413 break;
2414
2415 case TGSI_OPCODE_ARA:
2416 assert (0);
2417 break;
2418
2419 case TGSI_OPCODE_ARR:
2420 assert (0);
2421 break;
2422
2423 case TGSI_OPCODE_BRA:
2424 assert (0);
2425 break;
2426
2427 case TGSI_OPCODE_CAL:
2428 /* skip the call if no execution channels are enabled */
2429 if (mach->ExecMask) {
2430 /* do the call */
2431
2432 /* push the Cond, Loop, Cont stacks */
2433 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
2434 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
2435 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2436 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
2437 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2438 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
2439
2440 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
2441 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
2442
2443 /* note that PC was already incremented above */
2444 mach->CallStack[mach->CallStackTop++] = *pc;
2445 *pc = inst->InstructionExtLabel.Label;
2446 }
2447 break;
2448
2449 case TGSI_OPCODE_RET:
2450 mach->FuncMask &= ~mach->ExecMask;
2451 UPDATE_EXEC_MASK(mach);
2452
2453 if (mach->FuncMask == 0x0) {
2454 /* really return now (otherwise, keep executing */
2455
2456 if (mach->CallStackTop == 0) {
2457 /* returning from main() */
2458 *pc = -1;
2459 return;
2460 }
2461 *pc = mach->CallStack[--mach->CallStackTop];
2462
2463 /* pop the Cond, Loop, Cont stacks */
2464 assert(mach->CondStackTop > 0);
2465 mach->CondMask = mach->CondStack[--mach->CondStackTop];
2466 assert(mach->LoopStackTop > 0);
2467 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
2468 assert(mach->ContStackTop > 0);
2469 mach->ContMask = mach->ContStack[--mach->ContStackTop];
2470 assert(mach->FuncStackTop > 0);
2471 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
2472
2473 UPDATE_EXEC_MASK(mach);
2474 }
2475 break;
2476
2477 case TGSI_OPCODE_SSG:
2478 assert (0);
2479 break;
2480
2481 case TGSI_OPCODE_CMP:
2482 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2483 FETCH(&r[0], 0, chan_index);
2484 FETCH(&r[1], 1, chan_index);
2485 FETCH(&r[2], 2, chan_index);
2486
2487 micro_lt( &r[0], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[1], &r[2] );
2488
2489 STORE(&r[0], 0, chan_index);
2490 }
2491 break;
2492
2493 case TGSI_OPCODE_SCS:
2494 if( IS_CHANNEL_ENABLED( *inst, CHAN_X ) || IS_CHANNEL_ENABLED( *inst, CHAN_Y ) ) {
2495 FETCH( &r[0], 0, CHAN_X );
2496 }
2497 if( IS_CHANNEL_ENABLED( *inst, CHAN_X ) ) {
2498 micro_cos( &r[1], &r[0] );
2499 STORE( &r[1], 0, CHAN_X );
2500 }
2501 if( IS_CHANNEL_ENABLED( *inst, CHAN_Y ) ) {
2502 micro_sin( &r[1], &r[0] );
2503 STORE( &r[1], 0, CHAN_Y );
2504 }
2505 if( IS_CHANNEL_ENABLED( *inst, CHAN_Z ) ) {
2506 STORE( &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, CHAN_Z );
2507 }
2508 if( IS_CHANNEL_ENABLED( *inst, CHAN_W ) ) {
2509 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2510 }
2511 break;
2512
2513 case TGSI_OPCODE_NRM:
2514 /* 3-component vector normalize */
2515 {
2516 union tgsi_exec_channel tmp, dot;
2517
2518 /* tmp = dp3(src0, src0): */
2519 FETCH( &r[0], 0, CHAN_X );
2520 micro_mul( &tmp, &r[0], &r[0] );
2521
2522 FETCH( &r[1], 0, CHAN_Y );
2523 micro_mul( &dot, &r[1], &r[1] );
2524 micro_add( &tmp, &tmp, &dot );
2525
2526 FETCH( &r[2], 0, CHAN_Z );
2527 micro_mul( &dot, &r[2], &r[2] );
2528 micro_add( &tmp, &tmp, &dot );
2529
2530 /* tmp = 1 / sqrt(tmp) */
2531 micro_sqrt( &tmp, &tmp );
2532 micro_div( &tmp, &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &tmp );
2533
2534 /* note: w channel is undefined */
2535 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2536 /* chan = chan * tmp */
2537 micro_mul( &r[chan_index], &tmp, &r[chan_index] );
2538 STORE( &r[chan_index], 0, chan_index );
2539 }
2540 }
2541 break;
2542
2543 case TGSI_OPCODE_NRM4:
2544 /* 4-component vector normalize */
2545 {
2546 union tgsi_exec_channel tmp, dot;
2547
2548 /* tmp = dp4(src0, src0): */
2549 FETCH( &r[0], 0, CHAN_X );
2550 micro_mul( &tmp, &r[0], &r[0] );
2551
2552 FETCH( &r[1], 0, CHAN_Y );
2553 micro_mul( &dot, &r[1], &r[1] );
2554 micro_add( &tmp, &tmp, &dot );
2555
2556 FETCH( &r[2], 0, CHAN_Z );
2557 micro_mul( &dot, &r[2], &r[2] );
2558 micro_add( &tmp, &tmp, &dot );
2559
2560 FETCH( &r[3], 0, CHAN_W );
2561 micro_mul( &dot, &r[3], &r[3] );
2562 micro_add( &tmp, &tmp, &dot );
2563
2564 /* tmp = 1 / sqrt(tmp) */
2565 micro_sqrt( &tmp, &tmp );
2566 micro_div( &tmp, &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &tmp );
2567
2568 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2569 /* chan = chan * tmp */
2570 micro_mul( &r[chan_index], &tmp, &r[chan_index] );
2571 STORE( &r[chan_index], 0, chan_index );
2572 }
2573 }
2574 break;
2575
2576 case TGSI_OPCODE_DIV:
2577 assert( 0 );
2578 break;
2579
2580 case TGSI_OPCODE_DP2:
2581 FETCH( &r[0], 0, CHAN_X );
2582 FETCH( &r[1], 1, CHAN_X );
2583 micro_mul( &r[0], &r[0], &r[1] );
2584
2585 FETCH( &r[1], 0, CHAN_Y );
2586 FETCH( &r[2], 1, CHAN_Y );
2587 micro_mul( &r[1], &r[1], &r[2] );
2588 micro_add( &r[0], &r[0], &r[1] );
2589
2590 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2591 STORE( &r[0], 0, chan_index );
2592 }
2593 break;
2594
2595 case TGSI_OPCODE_IF:
2596 /* push CondMask */
2597 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
2598 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
2599 FETCH( &r[0], 0, CHAN_X );
2600 /* update CondMask */
2601 if( ! r[0].u[0] ) {
2602 mach->CondMask &= ~0x1;
2603 }
2604 if( ! r[0].u[1] ) {
2605 mach->CondMask &= ~0x2;
2606 }
2607 if( ! r[0].u[2] ) {
2608 mach->CondMask &= ~0x4;
2609 }
2610 if( ! r[0].u[3] ) {
2611 mach->CondMask &= ~0x8;
2612 }
2613 UPDATE_EXEC_MASK(mach);
2614 /* Todo: If CondMask==0, jump to ELSE */
2615 break;
2616
2617 case TGSI_OPCODE_ELSE:
2618 /* invert CondMask wrt previous mask */
2619 {
2620 uint prevMask;
2621 assert(mach->CondStackTop > 0);
2622 prevMask = mach->CondStack[mach->CondStackTop - 1];
2623 mach->CondMask = ~mach->CondMask & prevMask;
2624 UPDATE_EXEC_MASK(mach);
2625 /* Todo: If CondMask==0, jump to ENDIF */
2626 }
2627 break;
2628
2629 case TGSI_OPCODE_ENDIF:
2630 /* pop CondMask */
2631 assert(mach->CondStackTop > 0);
2632 mach->CondMask = mach->CondStack[--mach->CondStackTop];
2633 UPDATE_EXEC_MASK(mach);
2634 break;
2635
2636 case TGSI_OPCODE_END:
2637 /* halt execution */
2638 *pc = -1;
2639 break;
2640
2641 case TGSI_OPCODE_REP:
2642 assert (0);
2643 break;
2644
2645 case TGSI_OPCODE_ENDREP:
2646 assert (0);
2647 break;
2648
2649 case TGSI_OPCODE_PUSHA:
2650 assert (0);
2651 break;
2652
2653 case TGSI_OPCODE_POPA:
2654 assert (0);
2655 break;
2656
2657 case TGSI_OPCODE_CEIL:
2658 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2659 FETCH( &r[0], 0, chan_index );
2660 micro_ceil( &r[0], &r[0] );
2661 STORE( &r[0], 0, chan_index );
2662 }
2663 break;
2664
2665 case TGSI_OPCODE_I2F:
2666 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2667 FETCH( &r[0], 0, chan_index );
2668 micro_i2f( &r[0], &r[0] );
2669 STORE( &r[0], 0, chan_index );
2670 }
2671 break;
2672
2673 case TGSI_OPCODE_NOT:
2674 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2675 FETCH( &r[0], 0, chan_index );
2676 micro_not( &r[0], &r[0] );
2677 STORE( &r[0], 0, chan_index );
2678 }
2679 break;
2680
2681 case TGSI_OPCODE_TRUNC:
2682 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2683 FETCH( &r[0], 0, chan_index );
2684 micro_trunc( &r[0], &r[0] );
2685 STORE( &r[0], 0, chan_index );
2686 }
2687 break;
2688
2689 case TGSI_OPCODE_SHL:
2690 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2691 FETCH( &r[0], 0, chan_index );
2692 FETCH( &r[1], 1, chan_index );
2693 micro_shl( &r[0], &r[0], &r[1] );
2694 STORE( &r[0], 0, chan_index );
2695 }
2696 break;
2697
2698 case TGSI_OPCODE_SHR:
2699 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2700 FETCH( &r[0], 0, chan_index );
2701 FETCH( &r[1], 1, chan_index );
2702 micro_ishr( &r[0], &r[0], &r[1] );
2703 STORE( &r[0], 0, chan_index );
2704 }
2705 break;
2706
2707 case TGSI_OPCODE_AND:
2708 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2709 FETCH( &r[0], 0, chan_index );
2710 FETCH( &r[1], 1, chan_index );
2711 micro_and( &r[0], &r[0], &r[1] );
2712 STORE( &r[0], 0, chan_index );
2713 }
2714 break;
2715
2716 case TGSI_OPCODE_OR:
2717 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2718 FETCH( &r[0], 0, chan_index );
2719 FETCH( &r[1], 1, chan_index );
2720 micro_or( &r[0], &r[0], &r[1] );
2721 STORE( &r[0], 0, chan_index );
2722 }
2723 break;
2724
2725 case TGSI_OPCODE_MOD:
2726 assert (0);
2727 break;
2728
2729 case TGSI_OPCODE_XOR:
2730 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2731 FETCH( &r[0], 0, chan_index );
2732 FETCH( &r[1], 1, chan_index );
2733 micro_xor( &r[0], &r[0], &r[1] );
2734 STORE( &r[0], 0, chan_index );
2735 }
2736 break;
2737
2738 case TGSI_OPCODE_SAD:
2739 assert (0);
2740 break;
2741
2742 case TGSI_OPCODE_TXF:
2743 assert (0);
2744 break;
2745
2746 case TGSI_OPCODE_TXQ:
2747 assert (0);
2748 break;
2749
2750 case TGSI_OPCODE_EMIT:
2751 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += 16;
2752 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
2753 break;
2754
2755 case TGSI_OPCODE_ENDPRIM:
2756 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]++;
2757 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] = 0;
2758 break;
2759
2760 case TGSI_OPCODE_LOOP:
2761 /* fall-through (for now) */
2762 case TGSI_OPCODE_BGNLOOP2:
2763 /* push LoopMask and ContMasks */
2764 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2765 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
2766 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
2767 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
2768 break;
2769
2770 case TGSI_OPCODE_ENDLOOP:
2771 /* fall-through (for now at least) */
2772 case TGSI_OPCODE_ENDLOOP2:
2773 /* Restore ContMask, but don't pop */
2774 assert(mach->ContStackTop > 0);
2775 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
2776 UPDATE_EXEC_MASK(mach);
2777 if (mach->ExecMask) {
2778 /* repeat loop: jump to instruction just past BGNLOOP */
2779 *pc = inst->InstructionExtLabel.Label + 1;
2780 }
2781 else {
2782 /* exit loop: pop LoopMask */
2783 assert(mach->LoopStackTop > 0);
2784 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
2785 /* pop ContMask */
2786 assert(mach->ContStackTop > 0);
2787 mach->ContMask = mach->ContStack[--mach->ContStackTop];
2788 }
2789 UPDATE_EXEC_MASK(mach);
2790 break;
2791
2792 case TGSI_OPCODE_BRK:
2793 /* turn off loop channels for each enabled exec channel */
2794 mach->LoopMask &= ~mach->ExecMask;
2795 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2796 UPDATE_EXEC_MASK(mach);
2797 break;
2798
2799 case TGSI_OPCODE_CONT:
2800 /* turn off cont channels for each enabled exec channel */
2801 mach->ContMask &= ~mach->ExecMask;
2802 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2803 UPDATE_EXEC_MASK(mach);
2804 break;
2805
2806 case TGSI_OPCODE_BGNSUB:
2807 /* no-op */
2808 break;
2809
2810 case TGSI_OPCODE_ENDSUB:
2811 /* no-op */
2812 break;
2813
2814 case TGSI_OPCODE_NOISE1:
2815 assert( 0 );
2816 break;
2817
2818 case TGSI_OPCODE_NOISE2:
2819 assert( 0 );
2820 break;
2821
2822 case TGSI_OPCODE_NOISE3:
2823 assert( 0 );
2824 break;
2825
2826 case TGSI_OPCODE_NOISE4:
2827 assert( 0 );
2828 break;
2829
2830 case TGSI_OPCODE_NOP:
2831 break;
2832
2833 default:
2834 assert( 0 );
2835 }
2836 }
2837
2838
2839 /**
2840 * Run TGSI interpreter.
2841 * \return bitmask of "alive" quad components
2842 */
2843 uint
2844 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
2845 {
2846 uint i;
2847 int pc = 0;
2848
2849 mach->CondMask = 0xf;
2850 mach->LoopMask = 0xf;
2851 mach->ContMask = 0xf;
2852 mach->FuncMask = 0xf;
2853 mach->ExecMask = 0xf;
2854
2855 mach->CondStackTop = 0; /* temporarily subvert this assertion */
2856 assert(mach->CondStackTop == 0);
2857 assert(mach->LoopStackTop == 0);
2858 assert(mach->ContStackTop == 0);
2859 assert(mach->CallStackTop == 0);
2860
2861 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
2862 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
2863
2864 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
2865 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
2866 mach->Primitives[0] = 0;
2867 }
2868
2869 for (i = 0; i < QUAD_SIZE; i++) {
2870 mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C].u[i] =
2871 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_X_SHIFT) |
2872 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Y_SHIFT) |
2873 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Z_SHIFT) |
2874 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_W_SHIFT);
2875 }
2876
2877 /* execute declarations (interpolants) */
2878 for (i = 0; i < mach->NumDeclarations; i++) {
2879 exec_declaration( mach, mach->Declarations+i );
2880 }
2881
2882 /* execute instructions, until pc is set to -1 */
2883 while (pc != -1) {
2884 assert(pc < (int) mach->NumInstructions);
2885 exec_instruction( mach, mach->Instructions + pc, &pc );
2886 }
2887
2888 #if 0
2889 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
2890 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2891 /*
2892 * Scale back depth component.
2893 */
2894 for (i = 0; i < 4; i++)
2895 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
2896 }
2897 #endif
2898
2899 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
2900 }
2901
2902