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gallium/tgsi: add support for 64-bit integer immediates.
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
65
66
67 #define DEBUG_EXECUTION 0
68
69
70 #define FAST_MATH 0
71
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
76
77 union tgsi_double_channel {
78 double d[TGSI_QUAD_SIZE];
79 unsigned u[TGSI_QUAD_SIZE][2];
80 uint64_t u64[TGSI_QUAD_SIZE];
81 int64_t i64[TGSI_QUAD_SIZE];
82 };
83
84 struct tgsi_double_vector {
85 union tgsi_double_channel xy;
86 union tgsi_double_channel zw;
87 };
88
89 static void
90 micro_abs(union tgsi_exec_channel *dst,
91 const union tgsi_exec_channel *src)
92 {
93 dst->f[0] = fabsf(src->f[0]);
94 dst->f[1] = fabsf(src->f[1]);
95 dst->f[2] = fabsf(src->f[2]);
96 dst->f[3] = fabsf(src->f[3]);
97 }
98
99 static void
100 micro_arl(union tgsi_exec_channel *dst,
101 const union tgsi_exec_channel *src)
102 {
103 dst->i[0] = (int)floorf(src->f[0]);
104 dst->i[1] = (int)floorf(src->f[1]);
105 dst->i[2] = (int)floorf(src->f[2]);
106 dst->i[3] = (int)floorf(src->f[3]);
107 }
108
109 static void
110 micro_arr(union tgsi_exec_channel *dst,
111 const union tgsi_exec_channel *src)
112 {
113 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
114 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
115 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
116 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
117 }
118
119 static void
120 micro_ceil(union tgsi_exec_channel *dst,
121 const union tgsi_exec_channel *src)
122 {
123 dst->f[0] = ceilf(src->f[0]);
124 dst->f[1] = ceilf(src->f[1]);
125 dst->f[2] = ceilf(src->f[2]);
126 dst->f[3] = ceilf(src->f[3]);
127 }
128
129 static void
130 micro_clamp(union tgsi_exec_channel *dst,
131 const union tgsi_exec_channel *src0,
132 const union tgsi_exec_channel *src1,
133 const union tgsi_exec_channel *src2)
134 {
135 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
136 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
137 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
138 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
139 }
140
141 static void
142 micro_cmp(union tgsi_exec_channel *dst,
143 const union tgsi_exec_channel *src0,
144 const union tgsi_exec_channel *src1,
145 const union tgsi_exec_channel *src2)
146 {
147 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
148 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
149 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
150 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
151 }
152
153 static void
154 micro_cos(union tgsi_exec_channel *dst,
155 const union tgsi_exec_channel *src)
156 {
157 dst->f[0] = cosf(src->f[0]);
158 dst->f[1] = cosf(src->f[1]);
159 dst->f[2] = cosf(src->f[2]);
160 dst->f[3] = cosf(src->f[3]);
161 }
162
163 static void
164 micro_d2f(union tgsi_exec_channel *dst,
165 const union tgsi_double_channel *src)
166 {
167 dst->f[0] = (float)src->d[0];
168 dst->f[1] = (float)src->d[1];
169 dst->f[2] = (float)src->d[2];
170 dst->f[3] = (float)src->d[3];
171 }
172
173 static void
174 micro_d2i(union tgsi_exec_channel *dst,
175 const union tgsi_double_channel *src)
176 {
177 dst->i[0] = (int)src->d[0];
178 dst->i[1] = (int)src->d[1];
179 dst->i[2] = (int)src->d[2];
180 dst->i[3] = (int)src->d[3];
181 }
182
183 static void
184 micro_d2u(union tgsi_exec_channel *dst,
185 const union tgsi_double_channel *src)
186 {
187 dst->u[0] = (unsigned)src->d[0];
188 dst->u[1] = (unsigned)src->d[1];
189 dst->u[2] = (unsigned)src->d[2];
190 dst->u[3] = (unsigned)src->d[3];
191 }
192 static void
193 micro_dabs(union tgsi_double_channel *dst,
194 const union tgsi_double_channel *src)
195 {
196 dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
197 dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
198 dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
199 dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
200 }
201
202 static void
203 micro_dadd(union tgsi_double_channel *dst,
204 const union tgsi_double_channel *src)
205 {
206 dst->d[0] = src[0].d[0] + src[1].d[0];
207 dst->d[1] = src[0].d[1] + src[1].d[1];
208 dst->d[2] = src[0].d[2] + src[1].d[2];
209 dst->d[3] = src[0].d[3] + src[1].d[3];
210 }
211
212 static void
213 micro_ddx(union tgsi_exec_channel *dst,
214 const union tgsi_exec_channel *src)
215 {
216 dst->f[0] =
217 dst->f[1] =
218 dst->f[2] =
219 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
220 }
221
222 static void
223 micro_ddy(union tgsi_exec_channel *dst,
224 const union tgsi_exec_channel *src)
225 {
226 dst->f[0] =
227 dst->f[1] =
228 dst->f[2] =
229 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
230 }
231
232 static void
233 micro_dmul(union tgsi_double_channel *dst,
234 const union tgsi_double_channel *src)
235 {
236 dst->d[0] = src[0].d[0] * src[1].d[0];
237 dst->d[1] = src[0].d[1] * src[1].d[1];
238 dst->d[2] = src[0].d[2] * src[1].d[2];
239 dst->d[3] = src[0].d[3] * src[1].d[3];
240 }
241
242 static void
243 micro_dmax(union tgsi_double_channel *dst,
244 const union tgsi_double_channel *src)
245 {
246 dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
247 dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
248 dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
249 dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
250 }
251
252 static void
253 micro_dmin(union tgsi_double_channel *dst,
254 const union tgsi_double_channel *src)
255 {
256 dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
257 dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
258 dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
259 dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
260 }
261
262 static void
263 micro_dneg(union tgsi_double_channel *dst,
264 const union tgsi_double_channel *src)
265 {
266 dst->d[0] = -src->d[0];
267 dst->d[1] = -src->d[1];
268 dst->d[2] = -src->d[2];
269 dst->d[3] = -src->d[3];
270 }
271
272 static void
273 micro_dslt(union tgsi_double_channel *dst,
274 const union tgsi_double_channel *src)
275 {
276 dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
277 dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
278 dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
279 dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
280 }
281
282 static void
283 micro_dsne(union tgsi_double_channel *dst,
284 const union tgsi_double_channel *src)
285 {
286 dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
287 dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
288 dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
289 dst->u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
290 }
291
292 static void
293 micro_dsge(union tgsi_double_channel *dst,
294 const union tgsi_double_channel *src)
295 {
296 dst->u[0][0] = src[0].d[0] >= src[1].d[0] ? ~0U : 0U;
297 dst->u[1][0] = src[0].d[1] >= src[1].d[1] ? ~0U : 0U;
298 dst->u[2][0] = src[0].d[2] >= src[1].d[2] ? ~0U : 0U;
299 dst->u[3][0] = src[0].d[3] >= src[1].d[3] ? ~0U : 0U;
300 }
301
302 static void
303 micro_dseq(union tgsi_double_channel *dst,
304 const union tgsi_double_channel *src)
305 {
306 dst->u[0][0] = src[0].d[0] == src[1].d[0] ? ~0U : 0U;
307 dst->u[1][0] = src[0].d[1] == src[1].d[1] ? ~0U : 0U;
308 dst->u[2][0] = src[0].d[2] == src[1].d[2] ? ~0U : 0U;
309 dst->u[3][0] = src[0].d[3] == src[1].d[3] ? ~0U : 0U;
310 }
311
312 static void
313 micro_drcp(union tgsi_double_channel *dst,
314 const union tgsi_double_channel *src)
315 {
316 dst->d[0] = 1.0 / src->d[0];
317 dst->d[1] = 1.0 / src->d[1];
318 dst->d[2] = 1.0 / src->d[2];
319 dst->d[3] = 1.0 / src->d[3];
320 }
321
322 static void
323 micro_dsqrt(union tgsi_double_channel *dst,
324 const union tgsi_double_channel *src)
325 {
326 dst->d[0] = sqrt(src->d[0]);
327 dst->d[1] = sqrt(src->d[1]);
328 dst->d[2] = sqrt(src->d[2]);
329 dst->d[3] = sqrt(src->d[3]);
330 }
331
332 static void
333 micro_drsq(union tgsi_double_channel *dst,
334 const union tgsi_double_channel *src)
335 {
336 dst->d[0] = 1.0 / sqrt(src->d[0]);
337 dst->d[1] = 1.0 / sqrt(src->d[1]);
338 dst->d[2] = 1.0 / sqrt(src->d[2]);
339 dst->d[3] = 1.0 / sqrt(src->d[3]);
340 }
341
342 static void
343 micro_dmad(union tgsi_double_channel *dst,
344 const union tgsi_double_channel *src)
345 {
346 dst->d[0] = src[0].d[0] * src[1].d[0] + src[2].d[0];
347 dst->d[1] = src[0].d[1] * src[1].d[1] + src[2].d[1];
348 dst->d[2] = src[0].d[2] * src[1].d[2] + src[2].d[2];
349 dst->d[3] = src[0].d[3] * src[1].d[3] + src[2].d[3];
350 }
351
352 static void
353 micro_dfrac(union tgsi_double_channel *dst,
354 const union tgsi_double_channel *src)
355 {
356 dst->d[0] = src->d[0] - floor(src->d[0]);
357 dst->d[1] = src->d[1] - floor(src->d[1]);
358 dst->d[2] = src->d[2] - floor(src->d[2]);
359 dst->d[3] = src->d[3] - floor(src->d[3]);
360 }
361
362 static void
363 micro_dldexp(union tgsi_double_channel *dst,
364 const union tgsi_double_channel *src0,
365 union tgsi_exec_channel *src1)
366 {
367 dst->d[0] = ldexp(src0->d[0], src1->i[0]);
368 dst->d[1] = ldexp(src0->d[1], src1->i[1]);
369 dst->d[2] = ldexp(src0->d[2], src1->i[2]);
370 dst->d[3] = ldexp(src0->d[3], src1->i[3]);
371 }
372
373 static void
374 micro_dfracexp(union tgsi_double_channel *dst,
375 union tgsi_exec_channel *dst_exp,
376 const union tgsi_double_channel *src)
377 {
378 dst->d[0] = frexp(src->d[0], &dst_exp->i[0]);
379 dst->d[1] = frexp(src->d[1], &dst_exp->i[1]);
380 dst->d[2] = frexp(src->d[2], &dst_exp->i[2]);
381 dst->d[3] = frexp(src->d[3], &dst_exp->i[3]);
382 }
383
384 static void
385 micro_exp2(union tgsi_exec_channel *dst,
386 const union tgsi_exec_channel *src)
387 {
388 #if FAST_MATH
389 dst->f[0] = util_fast_exp2(src->f[0]);
390 dst->f[1] = util_fast_exp2(src->f[1]);
391 dst->f[2] = util_fast_exp2(src->f[2]);
392 dst->f[3] = util_fast_exp2(src->f[3]);
393 #else
394 #if DEBUG
395 /* Inf is okay for this instruction, so clamp it to silence assertions. */
396 uint i;
397 union tgsi_exec_channel clamped;
398
399 for (i = 0; i < 4; i++) {
400 if (src->f[i] > 127.99999f) {
401 clamped.f[i] = 127.99999f;
402 } else if (src->f[i] < -126.99999f) {
403 clamped.f[i] = -126.99999f;
404 } else {
405 clamped.f[i] = src->f[i];
406 }
407 }
408 src = &clamped;
409 #endif /* DEBUG */
410
411 dst->f[0] = powf(2.0f, src->f[0]);
412 dst->f[1] = powf(2.0f, src->f[1]);
413 dst->f[2] = powf(2.0f, src->f[2]);
414 dst->f[3] = powf(2.0f, src->f[3]);
415 #endif /* FAST_MATH */
416 }
417
418 static void
419 micro_f2d(union tgsi_double_channel *dst,
420 const union tgsi_exec_channel *src)
421 {
422 dst->d[0] = (double)src->f[0];
423 dst->d[1] = (double)src->f[1];
424 dst->d[2] = (double)src->f[2];
425 dst->d[3] = (double)src->f[3];
426 }
427
428 static void
429 micro_flr(union tgsi_exec_channel *dst,
430 const union tgsi_exec_channel *src)
431 {
432 dst->f[0] = floorf(src->f[0]);
433 dst->f[1] = floorf(src->f[1]);
434 dst->f[2] = floorf(src->f[2]);
435 dst->f[3] = floorf(src->f[3]);
436 }
437
438 static void
439 micro_frc(union tgsi_exec_channel *dst,
440 const union tgsi_exec_channel *src)
441 {
442 dst->f[0] = src->f[0] - floorf(src->f[0]);
443 dst->f[1] = src->f[1] - floorf(src->f[1]);
444 dst->f[2] = src->f[2] - floorf(src->f[2]);
445 dst->f[3] = src->f[3] - floorf(src->f[3]);
446 }
447
448 static void
449 micro_i2d(union tgsi_double_channel *dst,
450 const union tgsi_exec_channel *src)
451 {
452 dst->d[0] = (double)src->i[0];
453 dst->d[1] = (double)src->i[1];
454 dst->d[2] = (double)src->i[2];
455 dst->d[3] = (double)src->i[3];
456 }
457
458 static void
459 micro_iabs(union tgsi_exec_channel *dst,
460 const union tgsi_exec_channel *src)
461 {
462 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
463 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
464 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
465 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
466 }
467
468 static void
469 micro_ineg(union tgsi_exec_channel *dst,
470 const union tgsi_exec_channel *src)
471 {
472 dst->i[0] = -src->i[0];
473 dst->i[1] = -src->i[1];
474 dst->i[2] = -src->i[2];
475 dst->i[3] = -src->i[3];
476 }
477
478 static void
479 micro_lg2(union tgsi_exec_channel *dst,
480 const union tgsi_exec_channel *src)
481 {
482 #if FAST_MATH
483 dst->f[0] = util_fast_log2(src->f[0]);
484 dst->f[1] = util_fast_log2(src->f[1]);
485 dst->f[2] = util_fast_log2(src->f[2]);
486 dst->f[3] = util_fast_log2(src->f[3]);
487 #else
488 dst->f[0] = logf(src->f[0]) * 1.442695f;
489 dst->f[1] = logf(src->f[1]) * 1.442695f;
490 dst->f[2] = logf(src->f[2]) * 1.442695f;
491 dst->f[3] = logf(src->f[3]) * 1.442695f;
492 #endif
493 }
494
495 static void
496 micro_lrp(union tgsi_exec_channel *dst,
497 const union tgsi_exec_channel *src0,
498 const union tgsi_exec_channel *src1,
499 const union tgsi_exec_channel *src2)
500 {
501 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
502 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
503 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
504 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
505 }
506
507 static void
508 micro_mad(union tgsi_exec_channel *dst,
509 const union tgsi_exec_channel *src0,
510 const union tgsi_exec_channel *src1,
511 const union tgsi_exec_channel *src2)
512 {
513 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
514 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
515 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
516 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
517 }
518
519 static void
520 micro_mov(union tgsi_exec_channel *dst,
521 const union tgsi_exec_channel *src)
522 {
523 dst->u[0] = src->u[0];
524 dst->u[1] = src->u[1];
525 dst->u[2] = src->u[2];
526 dst->u[3] = src->u[3];
527 }
528
529 static void
530 micro_rcp(union tgsi_exec_channel *dst,
531 const union tgsi_exec_channel *src)
532 {
533 #if 0 /* for debugging */
534 assert(src->f[0] != 0.0f);
535 assert(src->f[1] != 0.0f);
536 assert(src->f[2] != 0.0f);
537 assert(src->f[3] != 0.0f);
538 #endif
539 dst->f[0] = 1.0f / src->f[0];
540 dst->f[1] = 1.0f / src->f[1];
541 dst->f[2] = 1.0f / src->f[2];
542 dst->f[3] = 1.0f / src->f[3];
543 }
544
545 static void
546 micro_rnd(union tgsi_exec_channel *dst,
547 const union tgsi_exec_channel *src)
548 {
549 dst->f[0] = _mesa_roundevenf(src->f[0]);
550 dst->f[1] = _mesa_roundevenf(src->f[1]);
551 dst->f[2] = _mesa_roundevenf(src->f[2]);
552 dst->f[3] = _mesa_roundevenf(src->f[3]);
553 }
554
555 static void
556 micro_rsq(union tgsi_exec_channel *dst,
557 const union tgsi_exec_channel *src)
558 {
559 #if 0 /* for debugging */
560 assert(src->f[0] != 0.0f);
561 assert(src->f[1] != 0.0f);
562 assert(src->f[2] != 0.0f);
563 assert(src->f[3] != 0.0f);
564 #endif
565 dst->f[0] = 1.0f / sqrtf(src->f[0]);
566 dst->f[1] = 1.0f / sqrtf(src->f[1]);
567 dst->f[2] = 1.0f / sqrtf(src->f[2]);
568 dst->f[3] = 1.0f / sqrtf(src->f[3]);
569 }
570
571 static void
572 micro_sqrt(union tgsi_exec_channel *dst,
573 const union tgsi_exec_channel *src)
574 {
575 dst->f[0] = sqrtf(src->f[0]);
576 dst->f[1] = sqrtf(src->f[1]);
577 dst->f[2] = sqrtf(src->f[2]);
578 dst->f[3] = sqrtf(src->f[3]);
579 }
580
581 static void
582 micro_seq(union tgsi_exec_channel *dst,
583 const union tgsi_exec_channel *src0,
584 const union tgsi_exec_channel *src1)
585 {
586 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
587 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
588 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
589 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
590 }
591
592 static void
593 micro_sge(union tgsi_exec_channel *dst,
594 const union tgsi_exec_channel *src0,
595 const union tgsi_exec_channel *src1)
596 {
597 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
598 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
599 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
600 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
601 }
602
603 static void
604 micro_sgn(union tgsi_exec_channel *dst,
605 const union tgsi_exec_channel *src)
606 {
607 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
608 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
609 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
610 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
611 }
612
613 static void
614 micro_isgn(union tgsi_exec_channel *dst,
615 const union tgsi_exec_channel *src)
616 {
617 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
618 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
619 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
620 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
621 }
622
623 static void
624 micro_sgt(union tgsi_exec_channel *dst,
625 const union tgsi_exec_channel *src0,
626 const union tgsi_exec_channel *src1)
627 {
628 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
629 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
630 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
631 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
632 }
633
634 static void
635 micro_sin(union tgsi_exec_channel *dst,
636 const union tgsi_exec_channel *src)
637 {
638 dst->f[0] = sinf(src->f[0]);
639 dst->f[1] = sinf(src->f[1]);
640 dst->f[2] = sinf(src->f[2]);
641 dst->f[3] = sinf(src->f[3]);
642 }
643
644 static void
645 micro_sle(union tgsi_exec_channel *dst,
646 const union tgsi_exec_channel *src0,
647 const union tgsi_exec_channel *src1)
648 {
649 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
650 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
651 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
652 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
653 }
654
655 static void
656 micro_slt(union tgsi_exec_channel *dst,
657 const union tgsi_exec_channel *src0,
658 const union tgsi_exec_channel *src1)
659 {
660 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
661 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
662 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
663 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
664 }
665
666 static void
667 micro_sne(union tgsi_exec_channel *dst,
668 const union tgsi_exec_channel *src0,
669 const union tgsi_exec_channel *src1)
670 {
671 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
672 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
673 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
674 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
675 }
676
677 static void
678 micro_trunc(union tgsi_exec_channel *dst,
679 const union tgsi_exec_channel *src)
680 {
681 dst->f[0] = truncf(src->f[0]);
682 dst->f[1] = truncf(src->f[1]);
683 dst->f[2] = truncf(src->f[2]);
684 dst->f[3] = truncf(src->f[3]);
685 }
686
687 static void
688 micro_u2d(union tgsi_double_channel *dst,
689 const union tgsi_exec_channel *src)
690 {
691 dst->d[0] = (double)src->u[0];
692 dst->d[1] = (double)src->u[1];
693 dst->d[2] = (double)src->u[2];
694 dst->d[3] = (double)src->u[3];
695 }
696
697 enum tgsi_exec_datatype {
698 TGSI_EXEC_DATA_FLOAT,
699 TGSI_EXEC_DATA_INT,
700 TGSI_EXEC_DATA_UINT,
701 TGSI_EXEC_DATA_DOUBLE
702 };
703
704 /*
705 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
706 */
707 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
708 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
709 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
710 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
711 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
712 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
713
714
715 /** The execution mask depends on the conditional mask and the loop mask */
716 #define UPDATE_EXEC_MASK(MACH) \
717 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
718
719
720 static const union tgsi_exec_channel ZeroVec =
721 { { 0.0, 0.0, 0.0, 0.0 } };
722
723 static const union tgsi_exec_channel OneVec = {
724 {1.0f, 1.0f, 1.0f, 1.0f}
725 };
726
727 static const union tgsi_exec_channel P128Vec = {
728 {128.0f, 128.0f, 128.0f, 128.0f}
729 };
730
731 static const union tgsi_exec_channel M128Vec = {
732 {-128.0f, -128.0f, -128.0f, -128.0f}
733 };
734
735
736 /**
737 * Assert that none of the float values in 'chan' are infinite or NaN.
738 * NaN and Inf may occur normally during program execution and should
739 * not lead to crashes, etc. But when debugging, it's helpful to catch
740 * them.
741 */
742 static inline void
743 check_inf_or_nan(const union tgsi_exec_channel *chan)
744 {
745 assert(!util_is_inf_or_nan((chan)->f[0]));
746 assert(!util_is_inf_or_nan((chan)->f[1]));
747 assert(!util_is_inf_or_nan((chan)->f[2]));
748 assert(!util_is_inf_or_nan((chan)->f[3]));
749 }
750
751
752 #ifdef DEBUG
753 static void
754 print_chan(const char *msg, const union tgsi_exec_channel *chan)
755 {
756 debug_printf("%s = {%f, %f, %f, %f}\n",
757 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
758 }
759 #endif
760
761
762 #ifdef DEBUG
763 static void
764 print_temp(const struct tgsi_exec_machine *mach, uint index)
765 {
766 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
767 int i;
768 debug_printf("Temp[%u] =\n", index);
769 for (i = 0; i < 4; i++) {
770 debug_printf(" %c: { %f, %f, %f, %f }\n",
771 "XYZW"[i],
772 tmp->xyzw[i].f[0],
773 tmp->xyzw[i].f[1],
774 tmp->xyzw[i].f[2],
775 tmp->xyzw[i].f[3]);
776 }
777 }
778 #endif
779
780
781 void
782 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
783 unsigned num_bufs,
784 const void **bufs,
785 const unsigned *buf_sizes)
786 {
787 unsigned i;
788
789 for (i = 0; i < num_bufs; i++) {
790 mach->Consts[i] = bufs[i];
791 mach->ConstsSize[i] = buf_sizes[i];
792 }
793 }
794
795
796 /**
797 * Check if there's a potential src/dst register data dependency when
798 * using SOA execution.
799 * Example:
800 * MOV T, T.yxwz;
801 * This would expand into:
802 * MOV t0, t1;
803 * MOV t1, t0;
804 * MOV t2, t3;
805 * MOV t3, t2;
806 * The second instruction will have the wrong value for t0 if executed as-is.
807 */
808 boolean
809 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
810 {
811 uint i, chan;
812
813 uint writemask = inst->Dst[0].Register.WriteMask;
814 if (writemask == TGSI_WRITEMASK_X ||
815 writemask == TGSI_WRITEMASK_Y ||
816 writemask == TGSI_WRITEMASK_Z ||
817 writemask == TGSI_WRITEMASK_W ||
818 writemask == TGSI_WRITEMASK_NONE) {
819 /* no chance of data dependency */
820 return FALSE;
821 }
822
823 /* loop over src regs */
824 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
825 if ((inst->Src[i].Register.File ==
826 inst->Dst[0].Register.File) &&
827 ((inst->Src[i].Register.Index ==
828 inst->Dst[0].Register.Index) ||
829 inst->Src[i].Register.Indirect ||
830 inst->Dst[0].Register.Indirect)) {
831 /* loop over dest channels */
832 uint channelsWritten = 0x0;
833 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
834 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
835 /* check if we're reading a channel that's been written */
836 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
837 if (channelsWritten & (1 << swizzle)) {
838 return TRUE;
839 }
840
841 channelsWritten |= (1 << chan);
842 }
843 }
844 }
845 }
846 return FALSE;
847 }
848
849
850 /**
851 * Initialize machine state by expanding tokens to full instructions,
852 * allocating temporary storage, setting up constants, etc.
853 * After this, we can call tgsi_exec_machine_run() many times.
854 */
855 void
856 tgsi_exec_machine_bind_shader(
857 struct tgsi_exec_machine *mach,
858 const struct tgsi_token *tokens,
859 struct tgsi_sampler *sampler,
860 struct tgsi_image *image,
861 struct tgsi_buffer *buffer)
862 {
863 uint k;
864 struct tgsi_parse_context parse;
865 struct tgsi_full_instruction *instructions;
866 struct tgsi_full_declaration *declarations;
867 uint maxInstructions = 10, numInstructions = 0;
868 uint maxDeclarations = 10, numDeclarations = 0;
869
870 #if 0
871 tgsi_dump(tokens, 0);
872 #endif
873
874 util_init_math();
875
876
877 mach->Tokens = tokens;
878 mach->Sampler = sampler;
879 mach->Image = image;
880 mach->Buffer = buffer;
881
882 if (!tokens) {
883 /* unbind and free all */
884 FREE(mach->Declarations);
885 mach->Declarations = NULL;
886 mach->NumDeclarations = 0;
887
888 FREE(mach->Instructions);
889 mach->Instructions = NULL;
890 mach->NumInstructions = 0;
891
892 return;
893 }
894
895 k = tgsi_parse_init (&parse, mach->Tokens);
896 if (k != TGSI_PARSE_OK) {
897 debug_printf( "Problem parsing!\n" );
898 return;
899 }
900
901 mach->ImmLimit = 0;
902 mach->NumOutputs = 0;
903
904 for (k = 0; k < TGSI_SEMANTIC_COUNT; k++)
905 mach->SysSemanticToIndex[k] = -1;
906
907 if (mach->ShaderType == PIPE_SHADER_GEOMETRY &&
908 !mach->UsedGeometryShader) {
909 struct tgsi_exec_vector *inputs;
910 struct tgsi_exec_vector *outputs;
911
912 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
913 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
914 16);
915
916 if (!inputs)
917 return;
918
919 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
920 TGSI_MAX_TOTAL_VERTICES, 16);
921
922 if (!outputs) {
923 align_free(inputs);
924 return;
925 }
926
927 align_free(mach->Inputs);
928 align_free(mach->Outputs);
929
930 mach->Inputs = inputs;
931 mach->Outputs = outputs;
932 mach->UsedGeometryShader = TRUE;
933 }
934
935 declarations = (struct tgsi_full_declaration *)
936 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
937
938 if (!declarations) {
939 return;
940 }
941
942 instructions = (struct tgsi_full_instruction *)
943 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
944
945 if (!instructions) {
946 FREE( declarations );
947 return;
948 }
949
950 while( !tgsi_parse_end_of_tokens( &parse ) ) {
951 uint i;
952
953 tgsi_parse_token( &parse );
954 switch( parse.FullToken.Token.Type ) {
955 case TGSI_TOKEN_TYPE_DECLARATION:
956 /* save expanded declaration */
957 if (numDeclarations == maxDeclarations) {
958 declarations = REALLOC(declarations,
959 maxDeclarations
960 * sizeof(struct tgsi_full_declaration),
961 (maxDeclarations + 10)
962 * sizeof(struct tgsi_full_declaration));
963 maxDeclarations += 10;
964 }
965 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
966 unsigned reg;
967 for (reg = parse.FullToken.FullDeclaration.Range.First;
968 reg <= parse.FullToken.FullDeclaration.Range.Last;
969 ++reg) {
970 ++mach->NumOutputs;
971 }
972 }
973 else if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
974 const struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
975 mach->SysSemanticToIndex[decl->Semantic.Name] = decl->Range.First;
976 }
977
978 memcpy(declarations + numDeclarations,
979 &parse.FullToken.FullDeclaration,
980 sizeof(declarations[0]));
981 numDeclarations++;
982 break;
983
984 case TGSI_TOKEN_TYPE_IMMEDIATE:
985 {
986 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
987 assert( size <= 4 );
988 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
989
990 for( i = 0; i < size; i++ ) {
991 mach->Imms[mach->ImmLimit][i] =
992 parse.FullToken.FullImmediate.u[i].Float;
993 }
994 mach->ImmLimit += 1;
995 }
996 break;
997
998 case TGSI_TOKEN_TYPE_INSTRUCTION:
999
1000 /* save expanded instruction */
1001 if (numInstructions == maxInstructions) {
1002 instructions = REALLOC(instructions,
1003 maxInstructions
1004 * sizeof(struct tgsi_full_instruction),
1005 (maxInstructions + 10)
1006 * sizeof(struct tgsi_full_instruction));
1007 maxInstructions += 10;
1008 }
1009
1010 memcpy(instructions + numInstructions,
1011 &parse.FullToken.FullInstruction,
1012 sizeof(instructions[0]));
1013
1014 numInstructions++;
1015 break;
1016
1017 case TGSI_TOKEN_TYPE_PROPERTY:
1018 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
1019 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
1020 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
1021 }
1022 }
1023 break;
1024
1025 default:
1026 assert( 0 );
1027 }
1028 }
1029 tgsi_parse_free (&parse);
1030
1031 FREE(mach->Declarations);
1032 mach->Declarations = declarations;
1033 mach->NumDeclarations = numDeclarations;
1034
1035 FREE(mach->Instructions);
1036 mach->Instructions = instructions;
1037 mach->NumInstructions = numInstructions;
1038 }
1039
1040
1041 struct tgsi_exec_machine *
1042 tgsi_exec_machine_create(enum pipe_shader_type shader_type)
1043 {
1044 struct tgsi_exec_machine *mach;
1045 uint i;
1046
1047 mach = align_malloc( sizeof *mach, 16 );
1048 if (!mach)
1049 goto fail;
1050
1051 memset(mach, 0, sizeof(*mach));
1052
1053 mach->ShaderType = shader_type;
1054 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
1055 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
1056 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
1057
1058 if (shader_type != PIPE_SHADER_COMPUTE) {
1059 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
1060 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
1061 if (!mach->Inputs || !mach->Outputs)
1062 goto fail;
1063 }
1064
1065 /* Setup constants needed by the SSE2 executor. */
1066 for( i = 0; i < 4; i++ ) {
1067 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
1068 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
1069 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
1070 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
1071 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
1072 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
1073 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
1074 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
1075 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
1076 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
1077 }
1078
1079 #ifdef DEBUG
1080 /* silence warnings */
1081 (void) print_chan;
1082 (void) print_temp;
1083 #endif
1084
1085 return mach;
1086
1087 fail:
1088 if (mach) {
1089 align_free(mach->Inputs);
1090 align_free(mach->Outputs);
1091 align_free(mach);
1092 }
1093 return NULL;
1094 }
1095
1096
1097 void
1098 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
1099 {
1100 if (mach) {
1101 FREE(mach->Instructions);
1102 FREE(mach->Declarations);
1103
1104 align_free(mach->Inputs);
1105 align_free(mach->Outputs);
1106
1107 align_free(mach);
1108 }
1109 }
1110
1111 static void
1112 micro_add(union tgsi_exec_channel *dst,
1113 const union tgsi_exec_channel *src0,
1114 const union tgsi_exec_channel *src1)
1115 {
1116 dst->f[0] = src0->f[0] + src1->f[0];
1117 dst->f[1] = src0->f[1] + src1->f[1];
1118 dst->f[2] = src0->f[2] + src1->f[2];
1119 dst->f[3] = src0->f[3] + src1->f[3];
1120 }
1121
1122 static void
1123 micro_div(
1124 union tgsi_exec_channel *dst,
1125 const union tgsi_exec_channel *src0,
1126 const union tgsi_exec_channel *src1 )
1127 {
1128 if (src1->f[0] != 0) {
1129 dst->f[0] = src0->f[0] / src1->f[0];
1130 }
1131 if (src1->f[1] != 0) {
1132 dst->f[1] = src0->f[1] / src1->f[1];
1133 }
1134 if (src1->f[2] != 0) {
1135 dst->f[2] = src0->f[2] / src1->f[2];
1136 }
1137 if (src1->f[3] != 0) {
1138 dst->f[3] = src0->f[3] / src1->f[3];
1139 }
1140 }
1141
1142 static void
1143 micro_lt(
1144 union tgsi_exec_channel *dst,
1145 const union tgsi_exec_channel *src0,
1146 const union tgsi_exec_channel *src1,
1147 const union tgsi_exec_channel *src2,
1148 const union tgsi_exec_channel *src3 )
1149 {
1150 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
1151 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
1152 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
1153 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
1154 }
1155
1156 static void
1157 micro_max(union tgsi_exec_channel *dst,
1158 const union tgsi_exec_channel *src0,
1159 const union tgsi_exec_channel *src1)
1160 {
1161 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
1162 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
1163 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
1164 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
1165 }
1166
1167 static void
1168 micro_min(union tgsi_exec_channel *dst,
1169 const union tgsi_exec_channel *src0,
1170 const union tgsi_exec_channel *src1)
1171 {
1172 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
1173 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
1174 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
1175 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
1176 }
1177
1178 static void
1179 micro_mul(union tgsi_exec_channel *dst,
1180 const union tgsi_exec_channel *src0,
1181 const union tgsi_exec_channel *src1)
1182 {
1183 dst->f[0] = src0->f[0] * src1->f[0];
1184 dst->f[1] = src0->f[1] * src1->f[1];
1185 dst->f[2] = src0->f[2] * src1->f[2];
1186 dst->f[3] = src0->f[3] * src1->f[3];
1187 }
1188
1189 static void
1190 micro_neg(
1191 union tgsi_exec_channel *dst,
1192 const union tgsi_exec_channel *src )
1193 {
1194 dst->f[0] = -src->f[0];
1195 dst->f[1] = -src->f[1];
1196 dst->f[2] = -src->f[2];
1197 dst->f[3] = -src->f[3];
1198 }
1199
1200 static void
1201 micro_pow(
1202 union tgsi_exec_channel *dst,
1203 const union tgsi_exec_channel *src0,
1204 const union tgsi_exec_channel *src1 )
1205 {
1206 #if FAST_MATH
1207 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1208 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1209 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1210 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1211 #else
1212 dst->f[0] = powf( src0->f[0], src1->f[0] );
1213 dst->f[1] = powf( src0->f[1], src1->f[1] );
1214 dst->f[2] = powf( src0->f[2], src1->f[2] );
1215 dst->f[3] = powf( src0->f[3], src1->f[3] );
1216 #endif
1217 }
1218
1219 static void
1220 micro_sub(union tgsi_exec_channel *dst,
1221 const union tgsi_exec_channel *src0,
1222 const union tgsi_exec_channel *src1)
1223 {
1224 dst->f[0] = src0->f[0] - src1->f[0];
1225 dst->f[1] = src0->f[1] - src1->f[1];
1226 dst->f[2] = src0->f[2] - src1->f[2];
1227 dst->f[3] = src0->f[3] - src1->f[3];
1228 }
1229
1230 static void
1231 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1232 const uint chan_index,
1233 const uint file,
1234 const uint swizzle,
1235 const union tgsi_exec_channel *index,
1236 const union tgsi_exec_channel *index2D,
1237 union tgsi_exec_channel *chan)
1238 {
1239 uint i;
1240
1241 assert(swizzle < 4);
1242
1243 switch (file) {
1244 case TGSI_FILE_CONSTANT:
1245 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1246 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1247 assert(mach->Consts[index2D->i[i]]);
1248
1249 if (index->i[i] < 0) {
1250 chan->u[i] = 0;
1251 } else {
1252 /* NOTE: copying the const value as a uint instead of float */
1253 const uint constbuf = index2D->i[i];
1254 const uint *buf = (const uint *)mach->Consts[constbuf];
1255 const int pos = index->i[i] * 4 + swizzle;
1256 /* const buffer bounds check */
1257 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1258 if (0) {
1259 /* Debug: print warning */
1260 static int count = 0;
1261 if (count++ < 100)
1262 debug_printf("TGSI Exec: const buffer index %d"
1263 " out of bounds\n", pos);
1264 }
1265 chan->u[i] = 0;
1266 }
1267 else
1268 chan->u[i] = buf[pos];
1269 }
1270 }
1271 break;
1272
1273 case TGSI_FILE_INPUT:
1274 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1275 /*
1276 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1277 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1278 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1279 index2D->i[i], index->i[i]);
1280 }*/
1281 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1282 assert(pos >= 0);
1283 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1284 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1285 }
1286 break;
1287
1288 case TGSI_FILE_SYSTEM_VALUE:
1289 /* XXX no swizzling at this point. Will be needed if we put
1290 * gl_FragCoord, for example, in a sys value register.
1291 */
1292 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1293 chan->u[i] = mach->SystemValue[index->i[i]].xyzw[swizzle].u[i];
1294 }
1295 break;
1296
1297 case TGSI_FILE_TEMPORARY:
1298 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1299 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1300 assert(index2D->i[i] == 0);
1301
1302 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1303 }
1304 break;
1305
1306 case TGSI_FILE_IMMEDIATE:
1307 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1308 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1309 assert(index2D->i[i] == 0);
1310
1311 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1312 }
1313 break;
1314
1315 case TGSI_FILE_ADDRESS:
1316 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1317 assert(index->i[i] >= 0);
1318 assert(index2D->i[i] == 0);
1319
1320 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1321 }
1322 break;
1323
1324 case TGSI_FILE_PREDICATE:
1325 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1326 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1327 assert(index2D->i[i] == 0);
1328
1329 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1330 }
1331 break;
1332
1333 case TGSI_FILE_OUTPUT:
1334 /* vertex/fragment output vars can be read too */
1335 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1336 assert(index->i[i] >= 0);
1337 assert(index2D->i[i] == 0);
1338
1339 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1340 }
1341 break;
1342
1343 default:
1344 assert(0);
1345 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1346 chan->u[i] = 0;
1347 }
1348 }
1349 }
1350
1351 static void
1352 fetch_source_d(const struct tgsi_exec_machine *mach,
1353 union tgsi_exec_channel *chan,
1354 const struct tgsi_full_src_register *reg,
1355 const uint chan_index,
1356 enum tgsi_exec_datatype src_datatype)
1357 {
1358 union tgsi_exec_channel index;
1359 union tgsi_exec_channel index2D;
1360 uint swizzle;
1361
1362 /* We start with a direct index into a register file.
1363 *
1364 * file[1],
1365 * where:
1366 * file = Register.File
1367 * [1] = Register.Index
1368 */
1369 index.i[0] =
1370 index.i[1] =
1371 index.i[2] =
1372 index.i[3] = reg->Register.Index;
1373
1374 /* There is an extra source register that indirectly subscripts
1375 * a register file. The direct index now becomes an offset
1376 * that is being added to the indirect register.
1377 *
1378 * file[ind[2].x+1],
1379 * where:
1380 * ind = Indirect.File
1381 * [2] = Indirect.Index
1382 * .x = Indirect.SwizzleX
1383 */
1384 if (reg->Register.Indirect) {
1385 union tgsi_exec_channel index2;
1386 union tgsi_exec_channel indir_index;
1387 const uint execmask = mach->ExecMask;
1388 uint i;
1389
1390 /* which address register (always zero now) */
1391 index2.i[0] =
1392 index2.i[1] =
1393 index2.i[2] =
1394 index2.i[3] = reg->Indirect.Index;
1395 /* get current value of address register[swizzle] */
1396 swizzle = reg->Indirect.Swizzle;
1397 fetch_src_file_channel(mach,
1398 chan_index,
1399 reg->Indirect.File,
1400 swizzle,
1401 &index2,
1402 &ZeroVec,
1403 &indir_index);
1404
1405 /* add value of address register to the offset */
1406 index.i[0] += indir_index.i[0];
1407 index.i[1] += indir_index.i[1];
1408 index.i[2] += indir_index.i[2];
1409 index.i[3] += indir_index.i[3];
1410
1411 /* for disabled execution channels, zero-out the index to
1412 * avoid using a potential garbage value.
1413 */
1414 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1415 if ((execmask & (1 << i)) == 0)
1416 index.i[i] = 0;
1417 }
1418 }
1419
1420 /* There is an extra source register that is a second
1421 * subscript to a register file. Effectively it means that
1422 * the register file is actually a 2D array of registers.
1423 *
1424 * file[3][1],
1425 * where:
1426 * [3] = Dimension.Index
1427 */
1428 if (reg->Register.Dimension) {
1429 index2D.i[0] =
1430 index2D.i[1] =
1431 index2D.i[2] =
1432 index2D.i[3] = reg->Dimension.Index;
1433
1434 /* Again, the second subscript index can be addressed indirectly
1435 * identically to the first one.
1436 * Nothing stops us from indirectly addressing the indirect register,
1437 * but there is no need for that, so we won't exercise it.
1438 *
1439 * file[ind[4].y+3][1],
1440 * where:
1441 * ind = DimIndirect.File
1442 * [4] = DimIndirect.Index
1443 * .y = DimIndirect.SwizzleX
1444 */
1445 if (reg->Dimension.Indirect) {
1446 union tgsi_exec_channel index2;
1447 union tgsi_exec_channel indir_index;
1448 const uint execmask = mach->ExecMask;
1449 uint i;
1450
1451 index2.i[0] =
1452 index2.i[1] =
1453 index2.i[2] =
1454 index2.i[3] = reg->DimIndirect.Index;
1455
1456 swizzle = reg->DimIndirect.Swizzle;
1457 fetch_src_file_channel(mach,
1458 chan_index,
1459 reg->DimIndirect.File,
1460 swizzle,
1461 &index2,
1462 &ZeroVec,
1463 &indir_index);
1464
1465 index2D.i[0] += indir_index.i[0];
1466 index2D.i[1] += indir_index.i[1];
1467 index2D.i[2] += indir_index.i[2];
1468 index2D.i[3] += indir_index.i[3];
1469
1470 /* for disabled execution channels, zero-out the index to
1471 * avoid using a potential garbage value.
1472 */
1473 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1474 if ((execmask & (1 << i)) == 0) {
1475 index2D.i[i] = 0;
1476 }
1477 }
1478 }
1479
1480 /* If by any chance there was a need for a 3D array of register
1481 * files, we would have to check whether Dimension is followed
1482 * by a dimension register and continue the saga.
1483 */
1484 } else {
1485 index2D.i[0] =
1486 index2D.i[1] =
1487 index2D.i[2] =
1488 index2D.i[3] = 0;
1489 }
1490
1491 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1492 fetch_src_file_channel(mach,
1493 chan_index,
1494 reg->Register.File,
1495 swizzle,
1496 &index,
1497 &index2D,
1498 chan);
1499 }
1500
1501 static void
1502 fetch_source(const struct tgsi_exec_machine *mach,
1503 union tgsi_exec_channel *chan,
1504 const struct tgsi_full_src_register *reg,
1505 const uint chan_index,
1506 enum tgsi_exec_datatype src_datatype)
1507 {
1508 fetch_source_d(mach, chan, reg, chan_index, src_datatype);
1509
1510 if (reg->Register.Absolute) {
1511 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1512 micro_abs(chan, chan);
1513 } else {
1514 micro_iabs(chan, chan);
1515 }
1516 }
1517
1518 if (reg->Register.Negate) {
1519 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1520 micro_neg(chan, chan);
1521 } else {
1522 micro_ineg(chan, chan);
1523 }
1524 }
1525 }
1526
1527 static union tgsi_exec_channel *
1528 store_dest_dstret(struct tgsi_exec_machine *mach,
1529 const union tgsi_exec_channel *chan,
1530 const struct tgsi_full_dst_register *reg,
1531 const struct tgsi_full_instruction *inst,
1532 uint chan_index,
1533 enum tgsi_exec_datatype dst_datatype)
1534 {
1535 uint i;
1536 static union tgsi_exec_channel null;
1537 union tgsi_exec_channel *dst;
1538 union tgsi_exec_channel index2D;
1539 uint execmask = mach->ExecMask;
1540 int offset = 0; /* indirection offset */
1541 int index;
1542
1543 /* for debugging */
1544 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1545 check_inf_or_nan(chan);
1546 }
1547
1548 /* There is an extra source register that indirectly subscripts
1549 * a register file. The direct index now becomes an offset
1550 * that is being added to the indirect register.
1551 *
1552 * file[ind[2].x+1],
1553 * where:
1554 * ind = Indirect.File
1555 * [2] = Indirect.Index
1556 * .x = Indirect.SwizzleX
1557 */
1558 if (reg->Register.Indirect) {
1559 union tgsi_exec_channel index;
1560 union tgsi_exec_channel indir_index;
1561 uint swizzle;
1562
1563 /* which address register (always zero for now) */
1564 index.i[0] =
1565 index.i[1] =
1566 index.i[2] =
1567 index.i[3] = reg->Indirect.Index;
1568
1569 /* get current value of address register[swizzle] */
1570 swizzle = reg->Indirect.Swizzle;
1571
1572 /* fetch values from the address/indirection register */
1573 fetch_src_file_channel(mach,
1574 chan_index,
1575 reg->Indirect.File,
1576 swizzle,
1577 &index,
1578 &ZeroVec,
1579 &indir_index);
1580
1581 /* save indirection offset */
1582 offset = indir_index.i[0];
1583 }
1584
1585 /* There is an extra source register that is a second
1586 * subscript to a register file. Effectively it means that
1587 * the register file is actually a 2D array of registers.
1588 *
1589 * file[3][1],
1590 * where:
1591 * [3] = Dimension.Index
1592 */
1593 if (reg->Register.Dimension) {
1594 index2D.i[0] =
1595 index2D.i[1] =
1596 index2D.i[2] =
1597 index2D.i[3] = reg->Dimension.Index;
1598
1599 /* Again, the second subscript index can be addressed indirectly
1600 * identically to the first one.
1601 * Nothing stops us from indirectly addressing the indirect register,
1602 * but there is no need for that, so we won't exercise it.
1603 *
1604 * file[ind[4].y+3][1],
1605 * where:
1606 * ind = DimIndirect.File
1607 * [4] = DimIndirect.Index
1608 * .y = DimIndirect.SwizzleX
1609 */
1610 if (reg->Dimension.Indirect) {
1611 union tgsi_exec_channel index2;
1612 union tgsi_exec_channel indir_index;
1613 const uint execmask = mach->ExecMask;
1614 unsigned swizzle;
1615 uint i;
1616
1617 index2.i[0] =
1618 index2.i[1] =
1619 index2.i[2] =
1620 index2.i[3] = reg->DimIndirect.Index;
1621
1622 swizzle = reg->DimIndirect.Swizzle;
1623 fetch_src_file_channel(mach,
1624 chan_index,
1625 reg->DimIndirect.File,
1626 swizzle,
1627 &index2,
1628 &ZeroVec,
1629 &indir_index);
1630
1631 index2D.i[0] += indir_index.i[0];
1632 index2D.i[1] += indir_index.i[1];
1633 index2D.i[2] += indir_index.i[2];
1634 index2D.i[3] += indir_index.i[3];
1635
1636 /* for disabled execution channels, zero-out the index to
1637 * avoid using a potential garbage value.
1638 */
1639 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1640 if ((execmask & (1 << i)) == 0) {
1641 index2D.i[i] = 0;
1642 }
1643 }
1644 }
1645
1646 /* If by any chance there was a need for a 3D array of register
1647 * files, we would have to check whether Dimension is followed
1648 * by a dimension register and continue the saga.
1649 */
1650 } else {
1651 index2D.i[0] =
1652 index2D.i[1] =
1653 index2D.i[2] =
1654 index2D.i[3] = 0;
1655 }
1656
1657 switch (reg->Register.File) {
1658 case TGSI_FILE_NULL:
1659 dst = &null;
1660 break;
1661
1662 case TGSI_FILE_OUTPUT:
1663 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1664 + reg->Register.Index;
1665 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1666 #if 0
1667 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1668 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1669 reg->Register.Index);
1670 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1671 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1672 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1673 if (execmask & (1 << i))
1674 debug_printf("%f, ", chan->f[i]);
1675 debug_printf(")\n");
1676 }
1677 #endif
1678 break;
1679
1680 case TGSI_FILE_TEMPORARY:
1681 index = reg->Register.Index;
1682 assert( index < TGSI_EXEC_NUM_TEMPS );
1683 dst = &mach->Temps[offset + index].xyzw[chan_index];
1684 break;
1685
1686 case TGSI_FILE_ADDRESS:
1687 index = reg->Register.Index;
1688 dst = &mach->Addrs[index].xyzw[chan_index];
1689 break;
1690
1691 case TGSI_FILE_PREDICATE:
1692 index = reg->Register.Index;
1693 assert(index < TGSI_EXEC_NUM_PREDS);
1694 dst = &mach->Predicates[index].xyzw[chan_index];
1695 break;
1696
1697 default:
1698 assert( 0 );
1699 return NULL;
1700 }
1701
1702 if (inst->Instruction.Predicate) {
1703 uint swizzle;
1704 union tgsi_exec_channel *pred;
1705
1706 switch (chan_index) {
1707 case TGSI_CHAN_X:
1708 swizzle = inst->Predicate.SwizzleX;
1709 break;
1710 case TGSI_CHAN_Y:
1711 swizzle = inst->Predicate.SwizzleY;
1712 break;
1713 case TGSI_CHAN_Z:
1714 swizzle = inst->Predicate.SwizzleZ;
1715 break;
1716 case TGSI_CHAN_W:
1717 swizzle = inst->Predicate.SwizzleW;
1718 break;
1719 default:
1720 assert(0);
1721 return NULL;
1722 }
1723
1724 assert(inst->Predicate.Index == 0);
1725
1726 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1727
1728 if (inst->Predicate.Negate) {
1729 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1730 if (pred->u[i]) {
1731 execmask &= ~(1 << i);
1732 }
1733 }
1734 } else {
1735 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1736 if (!pred->u[i]) {
1737 execmask &= ~(1 << i);
1738 }
1739 }
1740 }
1741 }
1742
1743 return dst;
1744 }
1745
1746 static void
1747 store_dest_double(struct tgsi_exec_machine *mach,
1748 const union tgsi_exec_channel *chan,
1749 const struct tgsi_full_dst_register *reg,
1750 const struct tgsi_full_instruction *inst,
1751 uint chan_index,
1752 enum tgsi_exec_datatype dst_datatype)
1753 {
1754 union tgsi_exec_channel *dst;
1755 const uint execmask = mach->ExecMask;
1756 int i;
1757
1758 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1759 dst_datatype);
1760 if (!dst)
1761 return;
1762
1763 /* doubles path */
1764 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1765 if (execmask & (1 << i))
1766 dst->i[i] = chan->i[i];
1767 }
1768
1769 static void
1770 store_dest(struct tgsi_exec_machine *mach,
1771 const union tgsi_exec_channel *chan,
1772 const struct tgsi_full_dst_register *reg,
1773 const struct tgsi_full_instruction *inst,
1774 uint chan_index,
1775 enum tgsi_exec_datatype dst_datatype)
1776 {
1777 union tgsi_exec_channel *dst;
1778 const uint execmask = mach->ExecMask;
1779 int i;
1780
1781 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1782 dst_datatype);
1783 if (!dst)
1784 return;
1785
1786 if (!inst->Instruction.Saturate) {
1787 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1788 if (execmask & (1 << i))
1789 dst->i[i] = chan->i[i];
1790 }
1791 else {
1792 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1793 if (execmask & (1 << i)) {
1794 if (chan->f[i] < 0.0f)
1795 dst->f[i] = 0.0f;
1796 else if (chan->f[i] > 1.0f)
1797 dst->f[i] = 1.0f;
1798 else
1799 dst->i[i] = chan->i[i];
1800 }
1801 }
1802 }
1803
1804 #define FETCH(VAL,INDEX,CHAN)\
1805 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1806
1807 #define IFETCH(VAL,INDEX,CHAN)\
1808 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1809
1810
1811 /**
1812 * Execute ARB-style KIL which is predicated by a src register.
1813 * Kill fragment if any of the four values is less than zero.
1814 */
1815 static void
1816 exec_kill_if(struct tgsi_exec_machine *mach,
1817 const struct tgsi_full_instruction *inst)
1818 {
1819 uint uniquemask;
1820 uint chan_index;
1821 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1822 union tgsi_exec_channel r[1];
1823
1824 /* This mask stores component bits that were already tested. */
1825 uniquemask = 0;
1826
1827 for (chan_index = 0; chan_index < 4; chan_index++)
1828 {
1829 uint swizzle;
1830 uint i;
1831
1832 /* unswizzle channel */
1833 swizzle = tgsi_util_get_full_src_register_swizzle (
1834 &inst->Src[0],
1835 chan_index);
1836
1837 /* check if the component has not been already tested */
1838 if (uniquemask & (1 << swizzle))
1839 continue;
1840 uniquemask |= 1 << swizzle;
1841
1842 FETCH(&r[0], 0, chan_index);
1843 for (i = 0; i < 4; i++)
1844 if (r[0].f[i] < 0.0f)
1845 kilmask |= 1 << i;
1846 }
1847
1848 /* restrict to fragments currently executing */
1849 kilmask &= mach->ExecMask;
1850
1851 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1852 }
1853
1854 /**
1855 * Unconditional fragment kill/discard.
1856 */
1857 static void
1858 exec_kill(struct tgsi_exec_machine *mach,
1859 const struct tgsi_full_instruction *inst)
1860 {
1861 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1862
1863 /* kill fragment for all fragments currently executing */
1864 kilmask = mach->ExecMask;
1865 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1866 }
1867
1868 static void
1869 emit_vertex(struct tgsi_exec_machine *mach)
1870 {
1871 /* FIXME: check for exec mask correctly
1872 unsigned i;
1873 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1874 if ((mach->ExecMask & (1 << i)))
1875 */
1876 if (mach->ExecMask) {
1877 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1878 return;
1879
1880 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1881 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1882 }
1883 }
1884
1885 static void
1886 emit_primitive(struct tgsi_exec_machine *mach)
1887 {
1888 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1889 /* FIXME: check for exec mask correctly
1890 unsigned i;
1891 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1892 if ((mach->ExecMask & (1 << i)))
1893 */
1894 if (mach->ExecMask) {
1895 ++(*prim_count);
1896 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1897 mach->Primitives[*prim_count] = 0;
1898 }
1899 }
1900
1901 static void
1902 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1903 {
1904 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1905 int emitted_verts =
1906 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1907 if (emitted_verts) {
1908 emit_primitive(mach);
1909 }
1910 }
1911 }
1912
1913
1914 /*
1915 * Fetch four texture samples using STR texture coordinates.
1916 */
1917 static void
1918 fetch_texel( struct tgsi_sampler *sampler,
1919 const unsigned sview_idx,
1920 const unsigned sampler_idx,
1921 const union tgsi_exec_channel *s,
1922 const union tgsi_exec_channel *t,
1923 const union tgsi_exec_channel *p,
1924 const union tgsi_exec_channel *c0,
1925 const union tgsi_exec_channel *c1,
1926 float derivs[3][2][TGSI_QUAD_SIZE],
1927 const int8_t offset[3],
1928 enum tgsi_sampler_control control,
1929 union tgsi_exec_channel *r,
1930 union tgsi_exec_channel *g,
1931 union tgsi_exec_channel *b,
1932 union tgsi_exec_channel *a )
1933 {
1934 uint j;
1935 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1936
1937 /* FIXME: handle explicit derivs, offsets */
1938 sampler->get_samples(sampler, sview_idx, sampler_idx,
1939 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1940
1941 for (j = 0; j < 4; j++) {
1942 r->f[j] = rgba[0][j];
1943 g->f[j] = rgba[1][j];
1944 b->f[j] = rgba[2][j];
1945 a->f[j] = rgba[3][j];
1946 }
1947 }
1948
1949
1950 #define TEX_MODIFIER_NONE 0
1951 #define TEX_MODIFIER_PROJECTED 1
1952 #define TEX_MODIFIER_LOD_BIAS 2
1953 #define TEX_MODIFIER_EXPLICIT_LOD 3
1954 #define TEX_MODIFIER_LEVEL_ZERO 4
1955 #define TEX_MODIFIER_GATHER 5
1956
1957 /*
1958 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1959 */
1960 static void
1961 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1962 const struct tgsi_full_instruction *inst,
1963 int8_t offsets[3])
1964 {
1965 if (inst->Texture.NumOffsets == 1) {
1966 union tgsi_exec_channel index;
1967 union tgsi_exec_channel offset[3];
1968 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1969 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1970 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1971 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1972 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1973 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1974 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1975 offsets[0] = offset[0].i[0];
1976 offsets[1] = offset[1].i[0];
1977 offsets[2] = offset[2].i[0];
1978 } else {
1979 assert(inst->Texture.NumOffsets == 0);
1980 offsets[0] = offsets[1] = offsets[2] = 0;
1981 }
1982 }
1983
1984
1985 /*
1986 * Fetch dx and dy values for one channel (s, t or r).
1987 * Put dx values into one float array, dy values into another.
1988 */
1989 static void
1990 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1991 const struct tgsi_full_instruction *inst,
1992 unsigned regdsrcx,
1993 unsigned chan,
1994 float derivs[2][TGSI_QUAD_SIZE])
1995 {
1996 union tgsi_exec_channel d;
1997 FETCH(&d, regdsrcx, chan);
1998 derivs[0][0] = d.f[0];
1999 derivs[0][1] = d.f[1];
2000 derivs[0][2] = d.f[2];
2001 derivs[0][3] = d.f[3];
2002 FETCH(&d, regdsrcx + 1, chan);
2003 derivs[1][0] = d.f[0];
2004 derivs[1][1] = d.f[1];
2005 derivs[1][2] = d.f[2];
2006 derivs[1][3] = d.f[3];
2007 }
2008
2009 static uint
2010 fetch_sampler_unit(struct tgsi_exec_machine *mach,
2011 const struct tgsi_full_instruction *inst,
2012 uint sampler)
2013 {
2014 uint unit = 0;
2015 int i;
2016 if (inst->Src[sampler].Register.Indirect) {
2017 const struct tgsi_full_src_register *reg = &inst->Src[sampler];
2018 union tgsi_exec_channel indir_index, index2;
2019 const uint execmask = mach->ExecMask;
2020 index2.i[0] =
2021 index2.i[1] =
2022 index2.i[2] =
2023 index2.i[3] = reg->Indirect.Index;
2024
2025 fetch_src_file_channel(mach,
2026 0,
2027 reg->Indirect.File,
2028 reg->Indirect.Swizzle,
2029 &index2,
2030 &ZeroVec,
2031 &indir_index);
2032 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2033 if (execmask & (1 << i)) {
2034 unit = inst->Src[sampler].Register.Index + indir_index.i[i];
2035 break;
2036 }
2037 }
2038
2039 } else {
2040 unit = inst->Src[sampler].Register.Index;
2041 }
2042 return unit;
2043 }
2044
2045 /*
2046 * execute a texture instruction.
2047 *
2048 * modifier is used to control the channel routing for the
2049 * instruction variants like proj, lod, and texture with lod bias.
2050 * sampler indicates which src register the sampler is contained in.
2051 */
2052 static void
2053 exec_tex(struct tgsi_exec_machine *mach,
2054 const struct tgsi_full_instruction *inst,
2055 uint modifier, uint sampler)
2056 {
2057 const union tgsi_exec_channel *args[5], *proj = NULL;
2058 union tgsi_exec_channel r[5];
2059 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2060 uint chan;
2061 uint unit;
2062 int8_t offsets[3];
2063 int dim, shadow_ref, i;
2064
2065 unit = fetch_sampler_unit(mach, inst, sampler);
2066 /* always fetch all 3 offsets, overkill but keeps code simple */
2067 fetch_texel_offsets(mach, inst, offsets);
2068
2069 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
2070 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
2071
2072 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2073 shadow_ref = tgsi_util_get_shadow_ref_src_index(inst->Texture.Texture);
2074
2075 assert(dim <= 4);
2076 if (shadow_ref >= 0)
2077 assert(shadow_ref >= dim && shadow_ref < ARRAY_SIZE(args));
2078
2079 /* fetch modifier to the last argument */
2080 if (modifier != TEX_MODIFIER_NONE) {
2081 const int last = ARRAY_SIZE(args) - 1;
2082
2083 /* fetch modifier from src0.w or src1.x */
2084 if (sampler == 1) {
2085 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
2086 FETCH(&r[last], 0, TGSI_CHAN_W);
2087 }
2088 else {
2089 assert(shadow_ref != 4);
2090 FETCH(&r[last], 1, TGSI_CHAN_X);
2091 }
2092
2093 if (modifier != TEX_MODIFIER_PROJECTED) {
2094 args[last] = &r[last];
2095 }
2096 else {
2097 proj = &r[last];
2098 args[last] = &ZeroVec;
2099 }
2100
2101 /* point unused arguments to zero vector */
2102 for (i = dim; i < last; i++)
2103 args[i] = &ZeroVec;
2104
2105 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
2106 control = TGSI_SAMPLER_LOD_EXPLICIT;
2107 else if (modifier == TEX_MODIFIER_LOD_BIAS)
2108 control = TGSI_SAMPLER_LOD_BIAS;
2109 else if (modifier == TEX_MODIFIER_GATHER)
2110 control = TGSI_SAMPLER_GATHER;
2111 }
2112 else {
2113 for (i = dim; i < ARRAY_SIZE(args); i++)
2114 args[i] = &ZeroVec;
2115 }
2116
2117 /* fetch coordinates */
2118 for (i = 0; i < dim; i++) {
2119 FETCH(&r[i], 0, TGSI_CHAN_X + i);
2120
2121 if (proj)
2122 micro_div(&r[i], &r[i], proj);
2123
2124 args[i] = &r[i];
2125 }
2126
2127 /* fetch reference value */
2128 if (shadow_ref >= 0) {
2129 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
2130
2131 if (proj)
2132 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
2133
2134 args[shadow_ref] = &r[shadow_ref];
2135 }
2136
2137 fetch_texel(mach->Sampler, unit, unit,
2138 args[0], args[1], args[2], args[3], args[4],
2139 NULL, offsets, control,
2140 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2141
2142 #if 0
2143 debug_printf("fetch r: %g %g %g %g\n",
2144 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2145 debug_printf("fetch g: %g %g %g %g\n",
2146 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2147 debug_printf("fetch b: %g %g %g %g\n",
2148 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2149 debug_printf("fetch a: %g %g %g %g\n",
2150 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2151 #endif
2152
2153 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2154 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2155 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2156 }
2157 }
2158 }
2159
2160 static void
2161 exec_lodq(struct tgsi_exec_machine *mach,
2162 const struct tgsi_full_instruction *inst)
2163 {
2164 uint unit;
2165 int dim;
2166 int i;
2167 union tgsi_exec_channel coords[4];
2168 const union tgsi_exec_channel *args[ARRAY_SIZE(coords)];
2169 union tgsi_exec_channel r[2];
2170
2171 unit = fetch_sampler_unit(mach, inst, 1);
2172 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2173 assert(dim <= ARRAY_SIZE(coords));
2174 /* fetch coordinates */
2175 for (i = 0; i < dim; i++) {
2176 FETCH(&coords[i], 0, TGSI_CHAN_X + i);
2177 args[i] = &coords[i];
2178 }
2179 for (i = dim; i < ARRAY_SIZE(coords); i++) {
2180 args[i] = &ZeroVec;
2181 }
2182 mach->Sampler->query_lod(mach->Sampler, unit, unit,
2183 args[0]->f,
2184 args[1]->f,
2185 args[2]->f,
2186 args[3]->f,
2187 TGSI_SAMPLER_LOD_NONE,
2188 r[0].f,
2189 r[1].f);
2190
2191 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2192 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X,
2193 TGSI_EXEC_DATA_FLOAT);
2194 }
2195 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2196 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Y,
2197 TGSI_EXEC_DATA_FLOAT);
2198 }
2199 }
2200
2201 static void
2202 exec_txd(struct tgsi_exec_machine *mach,
2203 const struct tgsi_full_instruction *inst)
2204 {
2205 union tgsi_exec_channel r[4];
2206 float derivs[3][2][TGSI_QUAD_SIZE];
2207 uint chan;
2208 uint unit;
2209 int8_t offsets[3];
2210
2211 unit = fetch_sampler_unit(mach, inst, 3);
2212 /* always fetch all 3 offsets, overkill but keeps code simple */
2213 fetch_texel_offsets(mach, inst, offsets);
2214
2215 switch (inst->Texture.Texture) {
2216 case TGSI_TEXTURE_1D:
2217 FETCH(&r[0], 0, TGSI_CHAN_X);
2218
2219 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2220
2221 fetch_texel(mach->Sampler, unit, unit,
2222 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2223 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2224 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2225 break;
2226
2227 case TGSI_TEXTURE_SHADOW1D:
2228 case TGSI_TEXTURE_1D_ARRAY:
2229 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2230 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2231 FETCH(&r[0], 0, TGSI_CHAN_X);
2232 FETCH(&r[1], 0, TGSI_CHAN_Y);
2233 FETCH(&r[2], 0, TGSI_CHAN_Z);
2234
2235 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2236
2237 fetch_texel(mach->Sampler, unit, unit,
2238 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2239 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2240 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2241 break;
2242
2243 case TGSI_TEXTURE_2D:
2244 case TGSI_TEXTURE_RECT:
2245 FETCH(&r[0], 0, TGSI_CHAN_X);
2246 FETCH(&r[1], 0, TGSI_CHAN_Y);
2247
2248 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2249 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2250
2251 fetch_texel(mach->Sampler, unit, unit,
2252 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2253 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2254 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2255 break;
2256
2257
2258 case TGSI_TEXTURE_SHADOW2D:
2259 case TGSI_TEXTURE_SHADOWRECT:
2260 case TGSI_TEXTURE_2D_ARRAY:
2261 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2262 /* only SHADOW2D_ARRAY actually needs W */
2263 FETCH(&r[0], 0, TGSI_CHAN_X);
2264 FETCH(&r[1], 0, TGSI_CHAN_Y);
2265 FETCH(&r[2], 0, TGSI_CHAN_Z);
2266 FETCH(&r[3], 0, TGSI_CHAN_W);
2267
2268 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2269 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2270
2271 fetch_texel(mach->Sampler, unit, unit,
2272 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2273 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2274 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2275 break;
2276
2277 case TGSI_TEXTURE_3D:
2278 case TGSI_TEXTURE_CUBE:
2279 case TGSI_TEXTURE_CUBE_ARRAY:
2280 case TGSI_TEXTURE_SHADOWCUBE:
2281 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2282 FETCH(&r[0], 0, TGSI_CHAN_X);
2283 FETCH(&r[1], 0, TGSI_CHAN_Y);
2284 FETCH(&r[2], 0, TGSI_CHAN_Z);
2285 FETCH(&r[3], 0, TGSI_CHAN_W);
2286
2287 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2288 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2289 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2290
2291 fetch_texel(mach->Sampler, unit, unit,
2292 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2293 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2294 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2295 break;
2296
2297 default:
2298 assert(0);
2299 }
2300
2301 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2302 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2303 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2304 }
2305 }
2306 }
2307
2308
2309 static void
2310 exec_txf(struct tgsi_exec_machine *mach,
2311 const struct tgsi_full_instruction *inst)
2312 {
2313 union tgsi_exec_channel r[4];
2314 uint chan;
2315 uint unit;
2316 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2317 int j;
2318 int8_t offsets[3];
2319 unsigned target;
2320
2321 unit = fetch_sampler_unit(mach, inst, 1);
2322 /* always fetch all 3 offsets, overkill but keeps code simple */
2323 fetch_texel_offsets(mach, inst, offsets);
2324
2325 IFETCH(&r[3], 0, TGSI_CHAN_W);
2326
2327 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2328 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2329 target = mach->SamplerViews[unit].Resource;
2330 }
2331 else {
2332 target = inst->Texture.Texture;
2333 }
2334 switch(target) {
2335 case TGSI_TEXTURE_3D:
2336 case TGSI_TEXTURE_2D_ARRAY:
2337 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2338 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2339 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2340 /* fallthrough */
2341 case TGSI_TEXTURE_2D:
2342 case TGSI_TEXTURE_RECT:
2343 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2344 case TGSI_TEXTURE_SHADOW2D:
2345 case TGSI_TEXTURE_SHADOWRECT:
2346 case TGSI_TEXTURE_1D_ARRAY:
2347 case TGSI_TEXTURE_2D_MSAA:
2348 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2349 /* fallthrough */
2350 case TGSI_TEXTURE_BUFFER:
2351 case TGSI_TEXTURE_1D:
2352 case TGSI_TEXTURE_SHADOW1D:
2353 IFETCH(&r[0], 0, TGSI_CHAN_X);
2354 break;
2355 default:
2356 assert(0);
2357 break;
2358 }
2359
2360 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2361 offsets, rgba);
2362
2363 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2364 r[0].f[j] = rgba[0][j];
2365 r[1].f[j] = rgba[1][j];
2366 r[2].f[j] = rgba[2][j];
2367 r[3].f[j] = rgba[3][j];
2368 }
2369
2370 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2371 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2372 unsigned char swizzles[4];
2373 swizzles[0] = inst->Src[1].Register.SwizzleX;
2374 swizzles[1] = inst->Src[1].Register.SwizzleY;
2375 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2376 swizzles[3] = inst->Src[1].Register.SwizzleW;
2377
2378 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2379 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2380 store_dest(mach, &r[swizzles[chan]],
2381 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2382 }
2383 }
2384 }
2385 else {
2386 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2387 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2388 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2389 }
2390 }
2391 }
2392 }
2393
2394 static void
2395 exec_txq(struct tgsi_exec_machine *mach,
2396 const struct tgsi_full_instruction *inst)
2397 {
2398 int result[4];
2399 union tgsi_exec_channel r[4], src;
2400 uint chan;
2401 uint unit;
2402 int i,j;
2403
2404 unit = fetch_sampler_unit(mach, inst, 1);
2405
2406 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2407
2408 /* XXX: This interface can't return per-pixel values */
2409 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2410
2411 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2412 for (j = 0; j < 4; j++) {
2413 r[j].i[i] = result[j];
2414 }
2415 }
2416
2417 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2418 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2419 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2420 TGSI_EXEC_DATA_INT);
2421 }
2422 }
2423 }
2424
2425 static void
2426 exec_sample(struct tgsi_exec_machine *mach,
2427 const struct tgsi_full_instruction *inst,
2428 uint modifier, boolean compare)
2429 {
2430 const uint resource_unit = inst->Src[1].Register.Index;
2431 const uint sampler_unit = inst->Src[2].Register.Index;
2432 union tgsi_exec_channel r[5], c1;
2433 const union tgsi_exec_channel *lod = &ZeroVec;
2434 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2435 uint chan;
2436 unsigned char swizzles[4];
2437 int8_t offsets[3];
2438
2439 /* always fetch all 3 offsets, overkill but keeps code simple */
2440 fetch_texel_offsets(mach, inst, offsets);
2441
2442 assert(modifier != TEX_MODIFIER_PROJECTED);
2443
2444 if (modifier != TEX_MODIFIER_NONE) {
2445 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2446 FETCH(&c1, 3, TGSI_CHAN_X);
2447 lod = &c1;
2448 control = TGSI_SAMPLER_LOD_BIAS;
2449 }
2450 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2451 FETCH(&c1, 3, TGSI_CHAN_X);
2452 lod = &c1;
2453 control = TGSI_SAMPLER_LOD_EXPLICIT;
2454 }
2455 else {
2456 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2457 control = TGSI_SAMPLER_LOD_ZERO;
2458 }
2459 }
2460
2461 FETCH(&r[0], 0, TGSI_CHAN_X);
2462
2463 switch (mach->SamplerViews[resource_unit].Resource) {
2464 case TGSI_TEXTURE_1D:
2465 if (compare) {
2466 FETCH(&r[2], 3, TGSI_CHAN_X);
2467 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2468 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2469 NULL, offsets, control,
2470 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2471 }
2472 else {
2473 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2474 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2475 NULL, offsets, control,
2476 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2477 }
2478 break;
2479
2480 case TGSI_TEXTURE_1D_ARRAY:
2481 case TGSI_TEXTURE_2D:
2482 case TGSI_TEXTURE_RECT:
2483 FETCH(&r[1], 0, TGSI_CHAN_Y);
2484 if (compare) {
2485 FETCH(&r[2], 3, TGSI_CHAN_X);
2486 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2487 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2488 NULL, offsets, control,
2489 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2490 }
2491 else {
2492 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2493 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2494 NULL, offsets, control,
2495 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2496 }
2497 break;
2498
2499 case TGSI_TEXTURE_2D_ARRAY:
2500 case TGSI_TEXTURE_3D:
2501 case TGSI_TEXTURE_CUBE:
2502 FETCH(&r[1], 0, TGSI_CHAN_Y);
2503 FETCH(&r[2], 0, TGSI_CHAN_Z);
2504 if(compare) {
2505 FETCH(&r[3], 3, TGSI_CHAN_X);
2506 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2507 &r[0], &r[1], &r[2], &r[3], lod,
2508 NULL, offsets, control,
2509 &r[0], &r[1], &r[2], &r[3]);
2510 }
2511 else {
2512 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2513 &r[0], &r[1], &r[2], &ZeroVec, lod,
2514 NULL, offsets, control,
2515 &r[0], &r[1], &r[2], &r[3]);
2516 }
2517 break;
2518
2519 case TGSI_TEXTURE_CUBE_ARRAY:
2520 FETCH(&r[1], 0, TGSI_CHAN_Y);
2521 FETCH(&r[2], 0, TGSI_CHAN_Z);
2522 FETCH(&r[3], 0, TGSI_CHAN_W);
2523 if(compare) {
2524 FETCH(&r[4], 3, TGSI_CHAN_X);
2525 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2526 &r[0], &r[1], &r[2], &r[3], &r[4],
2527 NULL, offsets, control,
2528 &r[0], &r[1], &r[2], &r[3]);
2529 }
2530 else {
2531 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2532 &r[0], &r[1], &r[2], &r[3], lod,
2533 NULL, offsets, control,
2534 &r[0], &r[1], &r[2], &r[3]);
2535 }
2536 break;
2537
2538
2539 default:
2540 assert(0);
2541 }
2542
2543 swizzles[0] = inst->Src[1].Register.SwizzleX;
2544 swizzles[1] = inst->Src[1].Register.SwizzleY;
2545 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2546 swizzles[3] = inst->Src[1].Register.SwizzleW;
2547
2548 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2549 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2550 store_dest(mach, &r[swizzles[chan]],
2551 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2552 }
2553 }
2554 }
2555
2556 static void
2557 exec_sample_d(struct tgsi_exec_machine *mach,
2558 const struct tgsi_full_instruction *inst)
2559 {
2560 const uint resource_unit = inst->Src[1].Register.Index;
2561 const uint sampler_unit = inst->Src[2].Register.Index;
2562 union tgsi_exec_channel r[4];
2563 float derivs[3][2][TGSI_QUAD_SIZE];
2564 uint chan;
2565 unsigned char swizzles[4];
2566 int8_t offsets[3];
2567
2568 /* always fetch all 3 offsets, overkill but keeps code simple */
2569 fetch_texel_offsets(mach, inst, offsets);
2570
2571 FETCH(&r[0], 0, TGSI_CHAN_X);
2572
2573 switch (mach->SamplerViews[resource_unit].Resource) {
2574 case TGSI_TEXTURE_1D:
2575 case TGSI_TEXTURE_1D_ARRAY:
2576 /* only 1D array actually needs Y */
2577 FETCH(&r[1], 0, TGSI_CHAN_Y);
2578
2579 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2580
2581 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2582 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2583 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2584 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2585 break;
2586
2587 case TGSI_TEXTURE_2D:
2588 case TGSI_TEXTURE_RECT:
2589 case TGSI_TEXTURE_2D_ARRAY:
2590 /* only 2D array actually needs Z */
2591 FETCH(&r[1], 0, TGSI_CHAN_Y);
2592 FETCH(&r[2], 0, TGSI_CHAN_Z);
2593
2594 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2595 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2596
2597 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2598 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2599 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2600 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2601 break;
2602
2603 case TGSI_TEXTURE_3D:
2604 case TGSI_TEXTURE_CUBE:
2605 case TGSI_TEXTURE_CUBE_ARRAY:
2606 /* only cube array actually needs W */
2607 FETCH(&r[1], 0, TGSI_CHAN_Y);
2608 FETCH(&r[2], 0, TGSI_CHAN_Z);
2609 FETCH(&r[3], 0, TGSI_CHAN_W);
2610
2611 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2612 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2613 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2614
2615 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2616 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2617 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2618 &r[0], &r[1], &r[2], &r[3]);
2619 break;
2620
2621 default:
2622 assert(0);
2623 }
2624
2625 swizzles[0] = inst->Src[1].Register.SwizzleX;
2626 swizzles[1] = inst->Src[1].Register.SwizzleY;
2627 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2628 swizzles[3] = inst->Src[1].Register.SwizzleW;
2629
2630 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2631 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2632 store_dest(mach, &r[swizzles[chan]],
2633 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2634 }
2635 }
2636 }
2637
2638
2639 /**
2640 * Evaluate a constant-valued coefficient at the position of the
2641 * current quad.
2642 */
2643 static void
2644 eval_constant_coef(
2645 struct tgsi_exec_machine *mach,
2646 unsigned attrib,
2647 unsigned chan )
2648 {
2649 unsigned i;
2650
2651 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2652 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2653 }
2654 }
2655
2656 /**
2657 * Evaluate a linear-valued coefficient at the position of the
2658 * current quad.
2659 */
2660 static void
2661 eval_linear_coef(
2662 struct tgsi_exec_machine *mach,
2663 unsigned attrib,
2664 unsigned chan )
2665 {
2666 const float x = mach->QuadPos.xyzw[0].f[0];
2667 const float y = mach->QuadPos.xyzw[1].f[0];
2668 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2669 const float dady = mach->InterpCoefs[attrib].dady[chan];
2670 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2671 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2672 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2673 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2674 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2675 }
2676
2677 /**
2678 * Evaluate a perspective-valued coefficient at the position of the
2679 * current quad.
2680 */
2681 static void
2682 eval_perspective_coef(
2683 struct tgsi_exec_machine *mach,
2684 unsigned attrib,
2685 unsigned chan )
2686 {
2687 const float x = mach->QuadPos.xyzw[0].f[0];
2688 const float y = mach->QuadPos.xyzw[1].f[0];
2689 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2690 const float dady = mach->InterpCoefs[attrib].dady[chan];
2691 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2692 const float *w = mach->QuadPos.xyzw[3].f;
2693 /* divide by W here */
2694 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2695 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2696 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2697 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2698 }
2699
2700
2701 typedef void (* eval_coef_func)(
2702 struct tgsi_exec_machine *mach,
2703 unsigned attrib,
2704 unsigned chan );
2705
2706 static void
2707 exec_declaration(struct tgsi_exec_machine *mach,
2708 const struct tgsi_full_declaration *decl)
2709 {
2710 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2711 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2712 return;
2713 }
2714
2715 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
2716 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2717 uint first, last, mask;
2718
2719 first = decl->Range.First;
2720 last = decl->Range.Last;
2721 mask = decl->Declaration.UsageMask;
2722
2723 /* XXX we could remove this special-case code since
2724 * mach->InterpCoefs[first].a0 should already have the
2725 * front/back-face value. But we should first update the
2726 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2727 * Then, we could remove the tgsi_exec_machine::Face field.
2728 */
2729 /* XXX make FACE a system value */
2730 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2731 uint i;
2732
2733 assert(decl->Semantic.Index == 0);
2734 assert(first == last);
2735
2736 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2737 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2738 }
2739 } else {
2740 eval_coef_func eval;
2741 uint i, j;
2742
2743 switch (decl->Interp.Interpolate) {
2744 case TGSI_INTERPOLATE_CONSTANT:
2745 eval = eval_constant_coef;
2746 break;
2747
2748 case TGSI_INTERPOLATE_LINEAR:
2749 eval = eval_linear_coef;
2750 break;
2751
2752 case TGSI_INTERPOLATE_PERSPECTIVE:
2753 eval = eval_perspective_coef;
2754 break;
2755
2756 case TGSI_INTERPOLATE_COLOR:
2757 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2758 break;
2759
2760 default:
2761 assert(0);
2762 return;
2763 }
2764
2765 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2766 if (mask & (1 << j)) {
2767 for (i = first; i <= last; i++) {
2768 eval(mach, i, j);
2769 }
2770 }
2771 }
2772 }
2773
2774 if (DEBUG_EXECUTION) {
2775 uint i, j;
2776 for (i = first; i <= last; ++i) {
2777 debug_printf("IN[%2u] = ", i);
2778 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2779 if (j > 0) {
2780 debug_printf(" ");
2781 }
2782 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2783 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2784 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2785 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2786 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2787 }
2788 }
2789 }
2790 }
2791 }
2792
2793 }
2794
2795 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2796 const union tgsi_exec_channel *src);
2797
2798 static void
2799 exec_scalar_unary(struct tgsi_exec_machine *mach,
2800 const struct tgsi_full_instruction *inst,
2801 micro_unary_op op,
2802 enum tgsi_exec_datatype dst_datatype,
2803 enum tgsi_exec_datatype src_datatype)
2804 {
2805 unsigned int chan;
2806 union tgsi_exec_channel src;
2807 union tgsi_exec_channel dst;
2808
2809 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2810 op(&dst, &src);
2811 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2812 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2813 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2814 }
2815 }
2816 }
2817
2818 static void
2819 exec_vector_unary(struct tgsi_exec_machine *mach,
2820 const struct tgsi_full_instruction *inst,
2821 micro_unary_op op,
2822 enum tgsi_exec_datatype dst_datatype,
2823 enum tgsi_exec_datatype src_datatype)
2824 {
2825 unsigned int chan;
2826 struct tgsi_exec_vector dst;
2827
2828 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2829 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2830 union tgsi_exec_channel src;
2831
2832 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2833 op(&dst.xyzw[chan], &src);
2834 }
2835 }
2836 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2837 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2838 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2839 }
2840 }
2841 }
2842
2843 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2844 const union tgsi_exec_channel *src0,
2845 const union tgsi_exec_channel *src1);
2846
2847 static void
2848 exec_scalar_binary(struct tgsi_exec_machine *mach,
2849 const struct tgsi_full_instruction *inst,
2850 micro_binary_op op,
2851 enum tgsi_exec_datatype dst_datatype,
2852 enum tgsi_exec_datatype src_datatype)
2853 {
2854 unsigned int chan;
2855 union tgsi_exec_channel src[2];
2856 union tgsi_exec_channel dst;
2857
2858 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2859 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2860 op(&dst, &src[0], &src[1]);
2861 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2862 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2863 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2864 }
2865 }
2866 }
2867
2868 static void
2869 exec_vector_binary(struct tgsi_exec_machine *mach,
2870 const struct tgsi_full_instruction *inst,
2871 micro_binary_op op,
2872 enum tgsi_exec_datatype dst_datatype,
2873 enum tgsi_exec_datatype src_datatype)
2874 {
2875 unsigned int chan;
2876 struct tgsi_exec_vector dst;
2877
2878 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2879 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2880 union tgsi_exec_channel src[2];
2881
2882 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2883 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2884 op(&dst.xyzw[chan], &src[0], &src[1]);
2885 }
2886 }
2887 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2888 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2889 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2890 }
2891 }
2892 }
2893
2894 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2895 const union tgsi_exec_channel *src0,
2896 const union tgsi_exec_channel *src1,
2897 const union tgsi_exec_channel *src2);
2898
2899 static void
2900 exec_vector_trinary(struct tgsi_exec_machine *mach,
2901 const struct tgsi_full_instruction *inst,
2902 micro_trinary_op op,
2903 enum tgsi_exec_datatype dst_datatype,
2904 enum tgsi_exec_datatype src_datatype)
2905 {
2906 unsigned int chan;
2907 struct tgsi_exec_vector dst;
2908
2909 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2910 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2911 union tgsi_exec_channel src[3];
2912
2913 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2914 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2915 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2916 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2917 }
2918 }
2919 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2920 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2921 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2922 }
2923 }
2924 }
2925
2926 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2927 const union tgsi_exec_channel *src0,
2928 const union tgsi_exec_channel *src1,
2929 const union tgsi_exec_channel *src2,
2930 const union tgsi_exec_channel *src3);
2931
2932 static void
2933 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2934 const struct tgsi_full_instruction *inst,
2935 micro_quaternary_op op,
2936 enum tgsi_exec_datatype dst_datatype,
2937 enum tgsi_exec_datatype src_datatype)
2938 {
2939 unsigned int chan;
2940 struct tgsi_exec_vector dst;
2941
2942 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2943 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2944 union tgsi_exec_channel src[4];
2945
2946 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2947 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2948 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2949 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2950 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2951 }
2952 }
2953 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2954 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2955 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2956 }
2957 }
2958 }
2959
2960 static void
2961 exec_dp3(struct tgsi_exec_machine *mach,
2962 const struct tgsi_full_instruction *inst)
2963 {
2964 unsigned int chan;
2965 union tgsi_exec_channel arg[3];
2966
2967 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2968 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2969 micro_mul(&arg[2], &arg[0], &arg[1]);
2970
2971 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2972 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2973 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2974 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2975 }
2976
2977 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2978 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2979 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2980 }
2981 }
2982 }
2983
2984 static void
2985 exec_dp4(struct tgsi_exec_machine *mach,
2986 const struct tgsi_full_instruction *inst)
2987 {
2988 unsigned int chan;
2989 union tgsi_exec_channel arg[3];
2990
2991 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2992 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2993 micro_mul(&arg[2], &arg[0], &arg[1]);
2994
2995 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2996 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2997 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2998 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2999 }
3000
3001 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3002 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3003 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3004 }
3005 }
3006 }
3007
3008 static void
3009 exec_dp2a(struct tgsi_exec_machine *mach,
3010 const struct tgsi_full_instruction *inst)
3011 {
3012 unsigned int chan;
3013 union tgsi_exec_channel arg[3];
3014
3015 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3016 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3017 micro_mul(&arg[2], &arg[0], &arg[1]);
3018
3019 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3020 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3021 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3022
3023 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3024 micro_add(&arg[0], &arg[0], &arg[1]);
3025
3026 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3027 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3028 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3029 }
3030 }
3031 }
3032
3033 static void
3034 exec_dph(struct tgsi_exec_machine *mach,
3035 const struct tgsi_full_instruction *inst)
3036 {
3037 unsigned int chan;
3038 union tgsi_exec_channel arg[3];
3039
3040 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3041 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3042 micro_mul(&arg[2], &arg[0], &arg[1]);
3043
3044 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3045 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3046 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3047
3048 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3049 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3050 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3051
3052 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3053 micro_add(&arg[0], &arg[0], &arg[1]);
3054
3055 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3056 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3057 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3058 }
3059 }
3060 }
3061
3062 static void
3063 exec_dp2(struct tgsi_exec_machine *mach,
3064 const struct tgsi_full_instruction *inst)
3065 {
3066 unsigned int chan;
3067 union tgsi_exec_channel arg[3];
3068
3069 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3070 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3071 micro_mul(&arg[2], &arg[0], &arg[1]);
3072
3073 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3074 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3075 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3076
3077 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3078 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3079 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3080 }
3081 }
3082 }
3083
3084 static void
3085 exec_pk2h(struct tgsi_exec_machine *mach,
3086 const struct tgsi_full_instruction *inst)
3087 {
3088 unsigned chan;
3089 union tgsi_exec_channel arg[2], dst;
3090
3091 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3092 fetch_source(mach, &arg[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3093 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3094 dst.u[chan] = util_float_to_half(arg[0].f[chan]) |
3095 (util_float_to_half(arg[1].f[chan]) << 16);
3096 }
3097 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3098 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3099 store_dest(mach, &dst, &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_UINT);
3100 }
3101 }
3102 }
3103
3104 static void
3105 exec_up2h(struct tgsi_exec_machine *mach,
3106 const struct tgsi_full_instruction *inst)
3107 {
3108 unsigned chan;
3109 union tgsi_exec_channel arg, dst[2];
3110
3111 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3112 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3113 dst[0].f[chan] = util_half_to_float(arg.u[chan] & 0xffff);
3114 dst[1].f[chan] = util_half_to_float(arg.u[chan] >> 16);
3115 }
3116 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3117 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3118 store_dest(mach, &dst[chan & 1], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3119 }
3120 }
3121 }
3122
3123 static void
3124 exec_scs(struct tgsi_exec_machine *mach,
3125 const struct tgsi_full_instruction *inst)
3126 {
3127 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
3128 union tgsi_exec_channel arg;
3129 union tgsi_exec_channel result;
3130
3131 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3132
3133 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3134 micro_cos(&result, &arg);
3135 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3136 }
3137 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3138 micro_sin(&result, &arg);
3139 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3140 }
3141 }
3142 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3143 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3144 }
3145 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3146 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3147 }
3148 }
3149
3150 static void
3151 exec_xpd(struct tgsi_exec_machine *mach,
3152 const struct tgsi_full_instruction *inst)
3153 {
3154 union tgsi_exec_channel r[6];
3155 union tgsi_exec_channel d[3];
3156
3157 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3158 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3159
3160 micro_mul(&r[2], &r[0], &r[1]);
3161
3162 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3163 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3164
3165 micro_mul(&r[5], &r[3], &r[4] );
3166 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
3167
3168 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3169
3170 micro_mul(&r[3], &r[3], &r[2]);
3171
3172 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3173
3174 micro_mul(&r[1], &r[1], &r[5]);
3175 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
3176
3177 micro_mul(&r[5], &r[5], &r[4]);
3178 micro_mul(&r[0], &r[0], &r[2]);
3179 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
3180
3181 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3182 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3183 }
3184 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3185 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3186 }
3187 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3188 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3189 }
3190 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3191 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3192 }
3193 }
3194
3195 static void
3196 exec_dst(struct tgsi_exec_machine *mach,
3197 const struct tgsi_full_instruction *inst)
3198 {
3199 union tgsi_exec_channel r[2];
3200 union tgsi_exec_channel d[4];
3201
3202 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3203 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3204 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3205 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3206 }
3207 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3208 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3209 }
3210 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3211 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3212 }
3213
3214 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3215 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3216 }
3217 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3218 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3219 }
3220 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3221 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3222 }
3223 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3224 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3225 }
3226 }
3227
3228 static void
3229 exec_log(struct tgsi_exec_machine *mach,
3230 const struct tgsi_full_instruction *inst)
3231 {
3232 union tgsi_exec_channel r[3];
3233
3234 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3235 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3236 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3237 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3238 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3239 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3240 }
3241 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3242 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3243 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3244 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3245 }
3246 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3247 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3248 }
3249 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3250 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3251 }
3252 }
3253
3254 static void
3255 exec_exp(struct tgsi_exec_machine *mach,
3256 const struct tgsi_full_instruction *inst)
3257 {
3258 union tgsi_exec_channel r[3];
3259
3260 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3261 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3262 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3263 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3264 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3265 }
3266 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3267 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3268 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3269 }
3270 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3271 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3272 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3273 }
3274 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3275 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3276 }
3277 }
3278
3279 static void
3280 exec_lit(struct tgsi_exec_machine *mach,
3281 const struct tgsi_full_instruction *inst)
3282 {
3283 union tgsi_exec_channel r[3];
3284 union tgsi_exec_channel d[3];
3285
3286 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3287 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3288 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3289 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3290 micro_max(&r[1], &r[1], &ZeroVec);
3291
3292 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3293 micro_min(&r[2], &r[2], &P128Vec);
3294 micro_max(&r[2], &r[2], &M128Vec);
3295 micro_pow(&r[1], &r[1], &r[2]);
3296 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3297 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3298 }
3299 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3300 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3301 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3302 }
3303 }
3304 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3305 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3306 }
3307
3308 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3309 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3310 }
3311 }
3312
3313 static void
3314 exec_break(struct tgsi_exec_machine *mach)
3315 {
3316 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3317 /* turn off loop channels for each enabled exec channel */
3318 mach->LoopMask &= ~mach->ExecMask;
3319 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3320 UPDATE_EXEC_MASK(mach);
3321 } else {
3322 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3323
3324 mach->Switch.mask = 0x0;
3325
3326 UPDATE_EXEC_MASK(mach);
3327 }
3328 }
3329
3330 static void
3331 exec_switch(struct tgsi_exec_machine *mach,
3332 const struct tgsi_full_instruction *inst)
3333 {
3334 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3335 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3336
3337 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3338 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3339 mach->Switch.mask = 0x0;
3340 mach->Switch.defaultMask = 0x0;
3341
3342 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3343 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3344
3345 UPDATE_EXEC_MASK(mach);
3346 }
3347
3348 static void
3349 exec_case(struct tgsi_exec_machine *mach,
3350 const struct tgsi_full_instruction *inst)
3351 {
3352 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3353 union tgsi_exec_channel src;
3354 uint mask = 0;
3355
3356 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3357
3358 if (mach->Switch.selector.u[0] == src.u[0]) {
3359 mask |= 0x1;
3360 }
3361 if (mach->Switch.selector.u[1] == src.u[1]) {
3362 mask |= 0x2;
3363 }
3364 if (mach->Switch.selector.u[2] == src.u[2]) {
3365 mask |= 0x4;
3366 }
3367 if (mach->Switch.selector.u[3] == src.u[3]) {
3368 mask |= 0x8;
3369 }
3370
3371 mach->Switch.defaultMask |= mask;
3372
3373 mach->Switch.mask |= mask & prevMask;
3374
3375 UPDATE_EXEC_MASK(mach);
3376 }
3377
3378 /* FIXME: this will only work if default is last */
3379 static void
3380 exec_default(struct tgsi_exec_machine *mach)
3381 {
3382 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3383
3384 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3385
3386 UPDATE_EXEC_MASK(mach);
3387 }
3388
3389 static void
3390 exec_endswitch(struct tgsi_exec_machine *mach)
3391 {
3392 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3393 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3394
3395 UPDATE_EXEC_MASK(mach);
3396 }
3397
3398 typedef void (* micro_dop)(union tgsi_double_channel *dst,
3399 const union tgsi_double_channel *src);
3400
3401 static void
3402 fetch_double_channel(struct tgsi_exec_machine *mach,
3403 union tgsi_double_channel *chan,
3404 const struct tgsi_full_src_register *reg,
3405 uint chan_0,
3406 uint chan_1)
3407 {
3408 union tgsi_exec_channel src[2];
3409 uint i;
3410
3411 fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
3412 fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
3413
3414 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3415 chan->u[i][0] = src[0].u[i];
3416 chan->u[i][1] = src[1].u[i];
3417 }
3418 if (reg->Register.Absolute) {
3419 micro_dabs(chan, chan);
3420 }
3421 if (reg->Register.Negate) {
3422 micro_dneg(chan, chan);
3423 }
3424 }
3425
3426 static void
3427 store_double_channel(struct tgsi_exec_machine *mach,
3428 const union tgsi_double_channel *chan,
3429 const struct tgsi_full_dst_register *reg,
3430 const struct tgsi_full_instruction *inst,
3431 uint chan_0,
3432 uint chan_1)
3433 {
3434 union tgsi_exec_channel dst[2];
3435 uint i;
3436 union tgsi_double_channel temp;
3437 const uint execmask = mach->ExecMask;
3438
3439 if (!inst->Instruction.Saturate) {
3440 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3441 if (execmask & (1 << i)) {
3442 dst[0].u[i] = chan->u[i][0];
3443 dst[1].u[i] = chan->u[i][1];
3444 }
3445 }
3446 else {
3447 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3448 if (execmask & (1 << i)) {
3449 if (chan->d[i] < 0.0)
3450 temp.d[i] = 0.0;
3451 else if (chan->d[i] > 1.0)
3452 temp.d[i] = 1.0;
3453 else
3454 temp.d[i] = chan->d[i];
3455
3456 dst[0].u[i] = temp.u[i][0];
3457 dst[1].u[i] = temp.u[i][1];
3458 }
3459 }
3460
3461 store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
3462 if (chan_1 != -1)
3463 store_dest_double(mach, &dst[1], reg, inst, chan_1, TGSI_EXEC_DATA_UINT);
3464 }
3465
3466 static void
3467 exec_double_unary(struct tgsi_exec_machine *mach,
3468 const struct tgsi_full_instruction *inst,
3469 micro_dop op)
3470 {
3471 union tgsi_double_channel src;
3472 union tgsi_double_channel dst;
3473
3474 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3475 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3476 op(&dst, &src);
3477 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3478 }
3479 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3480 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3481 op(&dst, &src);
3482 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3483 }
3484 }
3485
3486 static void
3487 exec_double_binary(struct tgsi_exec_machine *mach,
3488 const struct tgsi_full_instruction *inst,
3489 micro_dop op,
3490 enum tgsi_exec_datatype dst_datatype)
3491 {
3492 union tgsi_double_channel src[2];
3493 union tgsi_double_channel dst;
3494 int first_dest_chan, second_dest_chan;
3495 int wmask;
3496
3497 wmask = inst->Dst[0].Register.WriteMask;
3498 /* these are & because of the way DSLT etc store their destinations */
3499 if (wmask & TGSI_WRITEMASK_XY) {
3500 first_dest_chan = TGSI_CHAN_X;
3501 second_dest_chan = TGSI_CHAN_Y;
3502 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3503 first_dest_chan = (wmask & TGSI_WRITEMASK_X) ? TGSI_CHAN_X : TGSI_CHAN_Y;
3504 second_dest_chan = -1;
3505 }
3506
3507 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3508 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3509 op(&dst, src);
3510 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3511 }
3512
3513 if (wmask & TGSI_WRITEMASK_ZW) {
3514 first_dest_chan = TGSI_CHAN_Z;
3515 second_dest_chan = TGSI_CHAN_W;
3516 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3517 first_dest_chan = (wmask & TGSI_WRITEMASK_Z) ? TGSI_CHAN_Z : TGSI_CHAN_W;
3518 second_dest_chan = -1;
3519 }
3520
3521 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3522 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3523 op(&dst, src);
3524 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3525 }
3526 }
3527
3528 static void
3529 exec_double_trinary(struct tgsi_exec_machine *mach,
3530 const struct tgsi_full_instruction *inst,
3531 micro_dop op)
3532 {
3533 union tgsi_double_channel src[3];
3534 union tgsi_double_channel dst;
3535
3536 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3537 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3538 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3539 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_X, TGSI_CHAN_Y);
3540 op(&dst, src);
3541 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3542 }
3543 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3544 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3545 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3546 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_CHAN_W);
3547 op(&dst, src);
3548 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3549 }
3550 }
3551
3552 static void
3553 exec_f2d(struct tgsi_exec_machine *mach,
3554 const struct tgsi_full_instruction *inst)
3555 {
3556 union tgsi_exec_channel src;
3557 union tgsi_double_channel dst;
3558
3559 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3560 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3561 micro_f2d(&dst, &src);
3562 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3563 }
3564 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3565 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3566 micro_f2d(&dst, &src);
3567 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3568 }
3569 }
3570
3571 static void
3572 exec_d2f(struct tgsi_exec_machine *mach,
3573 const struct tgsi_full_instruction *inst)
3574 {
3575 union tgsi_double_channel src;
3576 union tgsi_exec_channel dst;
3577 int wm = inst->Dst[0].Register.WriteMask;
3578 int i;
3579 int bit;
3580 for (i = 0; i < 2; i++) {
3581 bit = ffs(wm);
3582 if (bit) {
3583 wm &= ~(1 << (bit - 1));
3584 if (i == 0)
3585 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3586 else
3587 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3588 micro_d2f(&dst, &src);
3589 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_FLOAT);
3590 }
3591 }
3592 }
3593
3594 static void
3595 exec_i2d(struct tgsi_exec_machine *mach,
3596 const struct tgsi_full_instruction *inst)
3597 {
3598 union tgsi_exec_channel src;
3599 union tgsi_double_channel dst;
3600
3601 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3602 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3603 micro_i2d(&dst, &src);
3604 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3605 }
3606 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3607 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_INT);
3608 micro_i2d(&dst, &src);
3609 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3610 }
3611 }
3612
3613 static void
3614 exec_d2i(struct tgsi_exec_machine *mach,
3615 const struct tgsi_full_instruction *inst)
3616 {
3617 union tgsi_double_channel src;
3618 union tgsi_exec_channel dst;
3619 int wm = inst->Dst[0].Register.WriteMask;
3620 int i;
3621 int bit;
3622 for (i = 0; i < 2; i++) {
3623 bit = ffs(wm);
3624 if (bit) {
3625 wm &= ~(1 << (bit - 1));
3626 if (i == 0)
3627 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3628 else
3629 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3630 micro_d2i(&dst, &src);
3631 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_INT);
3632 }
3633 }
3634 }
3635 static void
3636 exec_u2d(struct tgsi_exec_machine *mach,
3637 const struct tgsi_full_instruction *inst)
3638 {
3639 union tgsi_exec_channel src;
3640 union tgsi_double_channel dst;
3641
3642 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3643 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3644 micro_u2d(&dst, &src);
3645 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3646 }
3647 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3648 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_UINT);
3649 micro_u2d(&dst, &src);
3650 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3651 }
3652 }
3653
3654 static void
3655 exec_d2u(struct tgsi_exec_machine *mach,
3656 const struct tgsi_full_instruction *inst)
3657 {
3658 union tgsi_double_channel src;
3659 union tgsi_exec_channel dst;
3660 int wm = inst->Dst[0].Register.WriteMask;
3661 int i;
3662 int bit;
3663 for (i = 0; i < 2; i++) {
3664 bit = ffs(wm);
3665 if (bit) {
3666 wm &= ~(1 << (bit - 1));
3667 if (i == 0)
3668 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3669 else
3670 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3671 micro_d2u(&dst, &src);
3672 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_UINT);
3673 }
3674 }
3675 }
3676
3677 static void
3678 exec_dldexp(struct tgsi_exec_machine *mach,
3679 const struct tgsi_full_instruction *inst)
3680 {
3681 union tgsi_double_channel src0;
3682 union tgsi_exec_channel src1;
3683 union tgsi_double_channel dst;
3684 int wmask;
3685
3686 wmask = inst->Dst[0].Register.WriteMask;
3687 if (wmask & TGSI_WRITEMASK_XY) {
3688 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3689 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3690 micro_dldexp(&dst, &src0, &src1);
3691 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3692 }
3693
3694 if (wmask & TGSI_WRITEMASK_ZW) {
3695 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3696 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3697 micro_dldexp(&dst, &src0, &src1);
3698 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3699 }
3700 }
3701
3702 static void
3703 exec_dfracexp(struct tgsi_exec_machine *mach,
3704 const struct tgsi_full_instruction *inst)
3705 {
3706 union tgsi_double_channel src;
3707 union tgsi_double_channel dst;
3708 union tgsi_exec_channel dst_exp;
3709
3710 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY)) {
3711 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3712 micro_dfracexp(&dst, &dst_exp, &src);
3713 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3714 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3715 }
3716 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW)) {
3717 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3718 micro_dfracexp(&dst, &dst_exp, &src);
3719 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3720 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3721 }
3722 }
3723
3724 static int
3725 get_image_coord_dim(unsigned tgsi_tex)
3726 {
3727 int dim;
3728 switch (tgsi_tex) {
3729 case TGSI_TEXTURE_BUFFER:
3730 case TGSI_TEXTURE_1D:
3731 dim = 1;
3732 break;
3733 case TGSI_TEXTURE_2D:
3734 case TGSI_TEXTURE_RECT:
3735 case TGSI_TEXTURE_1D_ARRAY:
3736 case TGSI_TEXTURE_2D_MSAA:
3737 dim = 2;
3738 break;
3739 case TGSI_TEXTURE_3D:
3740 case TGSI_TEXTURE_CUBE:
3741 case TGSI_TEXTURE_2D_ARRAY:
3742 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3743 case TGSI_TEXTURE_CUBE_ARRAY:
3744 dim = 3;
3745 break;
3746 default:
3747 assert(!"unknown texture target");
3748 dim = 0;
3749 break;
3750 }
3751
3752 return dim;
3753 }
3754
3755 static int
3756 get_image_coord_sample(unsigned tgsi_tex)
3757 {
3758 int sample = 0;
3759 switch (tgsi_tex) {
3760 case TGSI_TEXTURE_2D_MSAA:
3761 sample = 3;
3762 break;
3763 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3764 sample = 4;
3765 break;
3766 default:
3767 break;
3768 }
3769 return sample;
3770 }
3771
3772 static void
3773 exec_load_img(struct tgsi_exec_machine *mach,
3774 const struct tgsi_full_instruction *inst)
3775 {
3776 union tgsi_exec_channel r[4], sample_r;
3777 uint unit;
3778 int sample;
3779 int i, j;
3780 int dim;
3781 uint chan;
3782 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3783 struct tgsi_image_params params;
3784 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3785
3786 unit = fetch_sampler_unit(mach, inst, 0);
3787 dim = get_image_coord_dim(inst->Memory.Texture);
3788 sample = get_image_coord_sample(inst->Memory.Texture);
3789 assert(dim <= 3);
3790
3791 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3792 params.unit = unit;
3793 params.tgsi_tex_instr = inst->Memory.Texture;
3794 params.format = inst->Memory.Format;
3795
3796 for (i = 0; i < dim; i++) {
3797 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
3798 }
3799
3800 if (sample)
3801 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
3802
3803 mach->Image->load(mach->Image, &params,
3804 r[0].i, r[1].i, r[2].i, sample_r.i,
3805 rgba);
3806 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3807 r[0].f[j] = rgba[0][j];
3808 r[1].f[j] = rgba[1][j];
3809 r[2].f[j] = rgba[2][j];
3810 r[3].f[j] = rgba[3][j];
3811 }
3812 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3813 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3814 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3815 }
3816 }
3817 }
3818
3819 static void
3820 exec_load_buf(struct tgsi_exec_machine *mach,
3821 const struct tgsi_full_instruction *inst)
3822 {
3823 union tgsi_exec_channel r[4];
3824 uint unit;
3825 int j;
3826 uint chan;
3827 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3828 struct tgsi_buffer_params params;
3829 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3830
3831 unit = fetch_sampler_unit(mach, inst, 0);
3832
3833 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3834 params.unit = unit;
3835 IFETCH(&r[0], 1, TGSI_CHAN_X);
3836
3837 mach->Buffer->load(mach->Buffer, &params,
3838 r[0].i, rgba);
3839 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3840 r[0].f[j] = rgba[0][j];
3841 r[1].f[j] = rgba[1][j];
3842 r[2].f[j] = rgba[2][j];
3843 r[3].f[j] = rgba[3][j];
3844 }
3845 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3846 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3847 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3848 }
3849 }
3850 }
3851
3852 static void
3853 exec_load_mem(struct tgsi_exec_machine *mach,
3854 const struct tgsi_full_instruction *inst)
3855 {
3856 union tgsi_exec_channel r[4];
3857 uint chan;
3858 char *ptr = mach->LocalMem;
3859 uint32_t offset;
3860 int j;
3861
3862 IFETCH(&r[0], 1, TGSI_CHAN_X);
3863 if (r[0].u[0] >= mach->LocalMemSize)
3864 return;
3865
3866 offset = r[0].u[0];
3867 ptr += offset;
3868
3869 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3870 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3871 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3872 memcpy(&r[chan].u[j], ptr + (4 * chan), 4);
3873 }
3874 }
3875 }
3876
3877 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3878 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3879 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3880 }
3881 }
3882 }
3883
3884 static void
3885 exec_load(struct tgsi_exec_machine *mach,
3886 const struct tgsi_full_instruction *inst)
3887 {
3888 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
3889 exec_load_img(mach, inst);
3890 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
3891 exec_load_buf(mach, inst);
3892 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
3893 exec_load_mem(mach, inst);
3894 }
3895
3896 static void
3897 exec_store_img(struct tgsi_exec_machine *mach,
3898 const struct tgsi_full_instruction *inst)
3899 {
3900 union tgsi_exec_channel r[3], sample_r;
3901 union tgsi_exec_channel value[4];
3902 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3903 struct tgsi_image_params params;
3904 int dim;
3905 int sample;
3906 int i, j;
3907 uint unit;
3908 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3909 unit = inst->Dst[0].Register.Index;
3910 dim = get_image_coord_dim(inst->Memory.Texture);
3911 sample = get_image_coord_sample(inst->Memory.Texture);
3912 assert(dim <= 3);
3913
3914 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3915 params.unit = unit;
3916 params.tgsi_tex_instr = inst->Memory.Texture;
3917 params.format = inst->Memory.Format;
3918
3919 for (i = 0; i < dim; i++) {
3920 IFETCH(&r[i], 0, TGSI_CHAN_X + i);
3921 }
3922
3923 for (i = 0; i < 4; i++) {
3924 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3925 }
3926 if (sample)
3927 IFETCH(&sample_r, 0, TGSI_CHAN_X + sample);
3928
3929 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3930 rgba[0][j] = value[0].f[j];
3931 rgba[1][j] = value[1].f[j];
3932 rgba[2][j] = value[2].f[j];
3933 rgba[3][j] = value[3].f[j];
3934 }
3935
3936 mach->Image->store(mach->Image, &params,
3937 r[0].i, r[1].i, r[2].i, sample_r.i,
3938 rgba);
3939 }
3940
3941 static void
3942 exec_store_buf(struct tgsi_exec_machine *mach,
3943 const struct tgsi_full_instruction *inst)
3944 {
3945 union tgsi_exec_channel r[3];
3946 union tgsi_exec_channel value[4];
3947 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3948 struct tgsi_buffer_params params;
3949 int i, j;
3950 uint unit;
3951 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3952
3953 unit = inst->Dst[0].Register.Index;
3954
3955 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3956 params.unit = unit;
3957 params.writemask = inst->Dst[0].Register.WriteMask;
3958
3959 IFETCH(&r[0], 0, TGSI_CHAN_X);
3960 for (i = 0; i < 4; i++) {
3961 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3962 }
3963
3964 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3965 rgba[0][j] = value[0].f[j];
3966 rgba[1][j] = value[1].f[j];
3967 rgba[2][j] = value[2].f[j];
3968 rgba[3][j] = value[3].f[j];
3969 }
3970
3971 mach->Buffer->store(mach->Buffer, &params,
3972 r[0].i,
3973 rgba);
3974 }
3975
3976 static void
3977 exec_store_mem(struct tgsi_exec_machine *mach,
3978 const struct tgsi_full_instruction *inst)
3979 {
3980 union tgsi_exec_channel r[3];
3981 union tgsi_exec_channel value[4];
3982 uint i, chan;
3983 char *ptr = mach->LocalMem;
3984 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3985 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3986
3987 IFETCH(&r[0], 0, TGSI_CHAN_X);
3988
3989 for (i = 0; i < 4; i++) {
3990 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3991 }
3992
3993 if (r[0].u[0] >= mach->LocalMemSize)
3994 return;
3995 ptr += r[0].u[0];
3996
3997 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3998 if (execmask & (1 << i)) {
3999 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4000 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4001 memcpy(ptr + (chan * 4), &value[chan].u[0], 4);
4002 }
4003 }
4004 }
4005 }
4006 }
4007
4008 static void
4009 exec_store(struct tgsi_exec_machine *mach,
4010 const struct tgsi_full_instruction *inst)
4011 {
4012 if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE)
4013 exec_store_img(mach, inst);
4014 else if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
4015 exec_store_buf(mach, inst);
4016 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
4017 exec_store_mem(mach, inst);
4018 }
4019
4020 static void
4021 exec_atomop_img(struct tgsi_exec_machine *mach,
4022 const struct tgsi_full_instruction *inst)
4023 {
4024 union tgsi_exec_channel r[4], sample_r;
4025 union tgsi_exec_channel value[4], value2[4];
4026 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4027 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4028 struct tgsi_image_params params;
4029 int dim;
4030 int sample;
4031 int i, j;
4032 uint unit, chan;
4033 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4034 unit = fetch_sampler_unit(mach, inst, 0);
4035 dim = get_image_coord_dim(inst->Memory.Texture);
4036 sample = get_image_coord_sample(inst->Memory.Texture);
4037 assert(dim <= 3);
4038
4039 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4040 params.unit = unit;
4041 params.tgsi_tex_instr = inst->Memory.Texture;
4042 params.format = inst->Memory.Format;
4043
4044 for (i = 0; i < dim; i++) {
4045 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
4046 }
4047
4048 for (i = 0; i < 4; i++) {
4049 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4050 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4051 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4052 }
4053 if (sample)
4054 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
4055
4056 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4057 rgba[0][j] = value[0].f[j];
4058 rgba[1][j] = value[1].f[j];
4059 rgba[2][j] = value[2].f[j];
4060 rgba[3][j] = value[3].f[j];
4061 }
4062 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4063 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4064 rgba2[0][j] = value2[0].f[j];
4065 rgba2[1][j] = value2[1].f[j];
4066 rgba2[2][j] = value2[2].f[j];
4067 rgba2[3][j] = value2[3].f[j];
4068 }
4069 }
4070
4071 mach->Image->op(mach->Image, &params, inst->Instruction.Opcode,
4072 r[0].i, r[1].i, r[2].i, sample_r.i,
4073 rgba, rgba2);
4074
4075 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4076 r[0].f[j] = rgba[0][j];
4077 r[1].f[j] = rgba[1][j];
4078 r[2].f[j] = rgba[2][j];
4079 r[3].f[j] = rgba[3][j];
4080 }
4081 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4082 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4083 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4084 }
4085 }
4086 }
4087
4088 static void
4089 exec_atomop_buf(struct tgsi_exec_machine *mach,
4090 const struct tgsi_full_instruction *inst)
4091 {
4092 union tgsi_exec_channel r[4];
4093 union tgsi_exec_channel value[4], value2[4];
4094 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4095 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4096 struct tgsi_buffer_params params;
4097 int i, j;
4098 uint unit, chan;
4099 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4100
4101 unit = fetch_sampler_unit(mach, inst, 0);
4102
4103 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4104 params.unit = unit;
4105 params.writemask = inst->Dst[0].Register.WriteMask;
4106
4107 IFETCH(&r[0], 1, TGSI_CHAN_X);
4108
4109 for (i = 0; i < 4; i++) {
4110 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4111 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4112 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4113 }
4114
4115 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4116 rgba[0][j] = value[0].f[j];
4117 rgba[1][j] = value[1].f[j];
4118 rgba[2][j] = value[2].f[j];
4119 rgba[3][j] = value[3].f[j];
4120 }
4121 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4122 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4123 rgba2[0][j] = value2[0].f[j];
4124 rgba2[1][j] = value2[1].f[j];
4125 rgba2[2][j] = value2[2].f[j];
4126 rgba2[3][j] = value2[3].f[j];
4127 }
4128 }
4129
4130 mach->Buffer->op(mach->Buffer, &params, inst->Instruction.Opcode,
4131 r[0].i,
4132 rgba, rgba2);
4133
4134 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4135 r[0].f[j] = rgba[0][j];
4136 r[1].f[j] = rgba[1][j];
4137 r[2].f[j] = rgba[2][j];
4138 r[3].f[j] = rgba[3][j];
4139 }
4140 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4141 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4142 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4143 }
4144 }
4145 }
4146
4147 static void
4148 exec_atomop_mem(struct tgsi_exec_machine *mach,
4149 const struct tgsi_full_instruction *inst)
4150 {
4151 union tgsi_exec_channel r[4];
4152 union tgsi_exec_channel value[4], value2[4];
4153 char *ptr = mach->LocalMem;
4154 uint32_t val;
4155 uint chan, i;
4156 uint32_t offset;
4157 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4158 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4159 IFETCH(&r[0], 1, TGSI_CHAN_X);
4160
4161 if (r[0].u[0] >= mach->LocalMemSize)
4162 return;
4163
4164 offset = r[0].u[0];
4165 ptr += offset;
4166 for (i = 0; i < 4; i++) {
4167 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4168 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4169 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4170 }
4171
4172 memcpy(&r[0].u[0], ptr, 4);
4173 val = r[0].u[0];
4174 switch (inst->Instruction.Opcode) {
4175 case TGSI_OPCODE_ATOMUADD:
4176 val += value[0].u[0];
4177 break;
4178 case TGSI_OPCODE_ATOMXOR:
4179 val ^= value[0].u[0];
4180 break;
4181 case TGSI_OPCODE_ATOMOR:
4182 val |= value[0].u[0];
4183 break;
4184 case TGSI_OPCODE_ATOMAND:
4185 val &= value[0].u[0];
4186 break;
4187 case TGSI_OPCODE_ATOMUMIN:
4188 val = MIN2(val, value[0].u[0]);
4189 break;
4190 case TGSI_OPCODE_ATOMUMAX:
4191 val = MAX2(val, value[0].u[0]);
4192 break;
4193 case TGSI_OPCODE_ATOMIMIN:
4194 val = MIN2(r[0].i[0], value[0].i[0]);
4195 break;
4196 case TGSI_OPCODE_ATOMIMAX:
4197 val = MAX2(r[0].i[0], value[0].i[0]);
4198 break;
4199 case TGSI_OPCODE_ATOMXCHG:
4200 val = value[0].i[0];
4201 break;
4202 case TGSI_OPCODE_ATOMCAS:
4203 if (val == value[0].u[0])
4204 val = value2[0].u[0];
4205 break;
4206 default:
4207 break;
4208 }
4209 for (i = 0; i < TGSI_QUAD_SIZE; i++)
4210 if (execmask & (1 << i))
4211 memcpy(ptr, &val, 4);
4212
4213 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4214 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4215 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4216 }
4217 }
4218 }
4219
4220 static void
4221 exec_atomop(struct tgsi_exec_machine *mach,
4222 const struct tgsi_full_instruction *inst)
4223 {
4224 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4225 exec_atomop_img(mach, inst);
4226 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
4227 exec_atomop_buf(mach, inst);
4228 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
4229 exec_atomop_mem(mach, inst);
4230 }
4231
4232 static void
4233 exec_resq_img(struct tgsi_exec_machine *mach,
4234 const struct tgsi_full_instruction *inst)
4235 {
4236 int result[4];
4237 union tgsi_exec_channel r[4];
4238 uint unit;
4239 int i, chan, j;
4240 struct tgsi_image_params params;
4241 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4242
4243 unit = fetch_sampler_unit(mach, inst, 0);
4244
4245 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4246 params.unit = unit;
4247 params.tgsi_tex_instr = inst->Memory.Texture;
4248 params.format = inst->Memory.Format;
4249
4250 mach->Image->get_dims(mach->Image, &params, result);
4251
4252 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4253 for (j = 0; j < 4; j++) {
4254 r[j].i[i] = result[j];
4255 }
4256 }
4257
4258 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4259 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4260 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4261 TGSI_EXEC_DATA_INT);
4262 }
4263 }
4264 }
4265
4266 static void
4267 exec_resq_buf(struct tgsi_exec_machine *mach,
4268 const struct tgsi_full_instruction *inst)
4269 {
4270 int result;
4271 union tgsi_exec_channel r[4];
4272 uint unit;
4273 int i, chan;
4274 struct tgsi_buffer_params params;
4275 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4276
4277 unit = fetch_sampler_unit(mach, inst, 0);
4278
4279 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4280 params.unit = unit;
4281
4282 mach->Buffer->get_dims(mach->Buffer, &params, &result);
4283
4284 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4285 r[0].i[i] = result;
4286 }
4287
4288 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4289 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4290 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4291 TGSI_EXEC_DATA_INT);
4292 }
4293 }
4294 }
4295
4296 static void
4297 exec_resq(struct tgsi_exec_machine *mach,
4298 const struct tgsi_full_instruction *inst)
4299 {
4300 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4301 exec_resq_img(mach, inst);
4302 else
4303 exec_resq_buf(mach, inst);
4304 }
4305
4306 static void
4307 micro_i2f(union tgsi_exec_channel *dst,
4308 const union tgsi_exec_channel *src)
4309 {
4310 dst->f[0] = (float)src->i[0];
4311 dst->f[1] = (float)src->i[1];
4312 dst->f[2] = (float)src->i[2];
4313 dst->f[3] = (float)src->i[3];
4314 }
4315
4316 static void
4317 micro_not(union tgsi_exec_channel *dst,
4318 const union tgsi_exec_channel *src)
4319 {
4320 dst->u[0] = ~src->u[0];
4321 dst->u[1] = ~src->u[1];
4322 dst->u[2] = ~src->u[2];
4323 dst->u[3] = ~src->u[3];
4324 }
4325
4326 static void
4327 micro_shl(union tgsi_exec_channel *dst,
4328 const union tgsi_exec_channel *src0,
4329 const union tgsi_exec_channel *src1)
4330 {
4331 unsigned masked_count;
4332 masked_count = src1->u[0] & 0x1f;
4333 dst->u[0] = src0->u[0] << masked_count;
4334 masked_count = src1->u[1] & 0x1f;
4335 dst->u[1] = src0->u[1] << masked_count;
4336 masked_count = src1->u[2] & 0x1f;
4337 dst->u[2] = src0->u[2] << masked_count;
4338 masked_count = src1->u[3] & 0x1f;
4339 dst->u[3] = src0->u[3] << masked_count;
4340 }
4341
4342 static void
4343 micro_and(union tgsi_exec_channel *dst,
4344 const union tgsi_exec_channel *src0,
4345 const union tgsi_exec_channel *src1)
4346 {
4347 dst->u[0] = src0->u[0] & src1->u[0];
4348 dst->u[1] = src0->u[1] & src1->u[1];
4349 dst->u[2] = src0->u[2] & src1->u[2];
4350 dst->u[3] = src0->u[3] & src1->u[3];
4351 }
4352
4353 static void
4354 micro_or(union tgsi_exec_channel *dst,
4355 const union tgsi_exec_channel *src0,
4356 const union tgsi_exec_channel *src1)
4357 {
4358 dst->u[0] = src0->u[0] | src1->u[0];
4359 dst->u[1] = src0->u[1] | src1->u[1];
4360 dst->u[2] = src0->u[2] | src1->u[2];
4361 dst->u[3] = src0->u[3] | src1->u[3];
4362 }
4363
4364 static void
4365 micro_xor(union tgsi_exec_channel *dst,
4366 const union tgsi_exec_channel *src0,
4367 const union tgsi_exec_channel *src1)
4368 {
4369 dst->u[0] = src0->u[0] ^ src1->u[0];
4370 dst->u[1] = src0->u[1] ^ src1->u[1];
4371 dst->u[2] = src0->u[2] ^ src1->u[2];
4372 dst->u[3] = src0->u[3] ^ src1->u[3];
4373 }
4374
4375 static void
4376 micro_mod(union tgsi_exec_channel *dst,
4377 const union tgsi_exec_channel *src0,
4378 const union tgsi_exec_channel *src1)
4379 {
4380 dst->i[0] = src0->i[0] % src1->i[0];
4381 dst->i[1] = src0->i[1] % src1->i[1];
4382 dst->i[2] = src0->i[2] % src1->i[2];
4383 dst->i[3] = src0->i[3] % src1->i[3];
4384 }
4385
4386 static void
4387 micro_f2i(union tgsi_exec_channel *dst,
4388 const union tgsi_exec_channel *src)
4389 {
4390 dst->i[0] = (int)src->f[0];
4391 dst->i[1] = (int)src->f[1];
4392 dst->i[2] = (int)src->f[2];
4393 dst->i[3] = (int)src->f[3];
4394 }
4395
4396 static void
4397 micro_fseq(union tgsi_exec_channel *dst,
4398 const union tgsi_exec_channel *src0,
4399 const union tgsi_exec_channel *src1)
4400 {
4401 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
4402 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
4403 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
4404 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
4405 }
4406
4407 static void
4408 micro_fsge(union tgsi_exec_channel *dst,
4409 const union tgsi_exec_channel *src0,
4410 const union tgsi_exec_channel *src1)
4411 {
4412 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
4413 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
4414 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
4415 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
4416 }
4417
4418 static void
4419 micro_fslt(union tgsi_exec_channel *dst,
4420 const union tgsi_exec_channel *src0,
4421 const union tgsi_exec_channel *src1)
4422 {
4423 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
4424 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
4425 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
4426 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
4427 }
4428
4429 static void
4430 micro_fsne(union tgsi_exec_channel *dst,
4431 const union tgsi_exec_channel *src0,
4432 const union tgsi_exec_channel *src1)
4433 {
4434 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
4435 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
4436 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
4437 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
4438 }
4439
4440 static void
4441 micro_idiv(union tgsi_exec_channel *dst,
4442 const union tgsi_exec_channel *src0,
4443 const union tgsi_exec_channel *src1)
4444 {
4445 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
4446 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
4447 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
4448 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
4449 }
4450
4451 static void
4452 micro_imax(union tgsi_exec_channel *dst,
4453 const union tgsi_exec_channel *src0,
4454 const union tgsi_exec_channel *src1)
4455 {
4456 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
4457 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
4458 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
4459 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
4460 }
4461
4462 static void
4463 micro_imin(union tgsi_exec_channel *dst,
4464 const union tgsi_exec_channel *src0,
4465 const union tgsi_exec_channel *src1)
4466 {
4467 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
4468 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
4469 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
4470 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
4471 }
4472
4473 static void
4474 micro_isge(union tgsi_exec_channel *dst,
4475 const union tgsi_exec_channel *src0,
4476 const union tgsi_exec_channel *src1)
4477 {
4478 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
4479 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
4480 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
4481 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
4482 }
4483
4484 static void
4485 micro_ishr(union tgsi_exec_channel *dst,
4486 const union tgsi_exec_channel *src0,
4487 const union tgsi_exec_channel *src1)
4488 {
4489 unsigned masked_count;
4490 masked_count = src1->i[0] & 0x1f;
4491 dst->i[0] = src0->i[0] >> masked_count;
4492 masked_count = src1->i[1] & 0x1f;
4493 dst->i[1] = src0->i[1] >> masked_count;
4494 masked_count = src1->i[2] & 0x1f;
4495 dst->i[2] = src0->i[2] >> masked_count;
4496 masked_count = src1->i[3] & 0x1f;
4497 dst->i[3] = src0->i[3] >> masked_count;
4498 }
4499
4500 static void
4501 micro_islt(union tgsi_exec_channel *dst,
4502 const union tgsi_exec_channel *src0,
4503 const union tgsi_exec_channel *src1)
4504 {
4505 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
4506 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
4507 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
4508 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
4509 }
4510
4511 static void
4512 micro_f2u(union tgsi_exec_channel *dst,
4513 const union tgsi_exec_channel *src)
4514 {
4515 dst->u[0] = (uint)src->f[0];
4516 dst->u[1] = (uint)src->f[1];
4517 dst->u[2] = (uint)src->f[2];
4518 dst->u[3] = (uint)src->f[3];
4519 }
4520
4521 static void
4522 micro_u2f(union tgsi_exec_channel *dst,
4523 const union tgsi_exec_channel *src)
4524 {
4525 dst->f[0] = (float)src->u[0];
4526 dst->f[1] = (float)src->u[1];
4527 dst->f[2] = (float)src->u[2];
4528 dst->f[3] = (float)src->u[3];
4529 }
4530
4531 static void
4532 micro_uadd(union tgsi_exec_channel *dst,
4533 const union tgsi_exec_channel *src0,
4534 const union tgsi_exec_channel *src1)
4535 {
4536 dst->u[0] = src0->u[0] + src1->u[0];
4537 dst->u[1] = src0->u[1] + src1->u[1];
4538 dst->u[2] = src0->u[2] + src1->u[2];
4539 dst->u[3] = src0->u[3] + src1->u[3];
4540 }
4541
4542 static void
4543 micro_udiv(union tgsi_exec_channel *dst,
4544 const union tgsi_exec_channel *src0,
4545 const union tgsi_exec_channel *src1)
4546 {
4547 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
4548 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
4549 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
4550 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
4551 }
4552
4553 static void
4554 micro_umad(union tgsi_exec_channel *dst,
4555 const union tgsi_exec_channel *src0,
4556 const union tgsi_exec_channel *src1,
4557 const union tgsi_exec_channel *src2)
4558 {
4559 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
4560 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
4561 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
4562 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
4563 }
4564
4565 static void
4566 micro_umax(union tgsi_exec_channel *dst,
4567 const union tgsi_exec_channel *src0,
4568 const union tgsi_exec_channel *src1)
4569 {
4570 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
4571 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
4572 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
4573 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
4574 }
4575
4576 static void
4577 micro_umin(union tgsi_exec_channel *dst,
4578 const union tgsi_exec_channel *src0,
4579 const union tgsi_exec_channel *src1)
4580 {
4581 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
4582 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
4583 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
4584 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
4585 }
4586
4587 static void
4588 micro_umod(union tgsi_exec_channel *dst,
4589 const union tgsi_exec_channel *src0,
4590 const union tgsi_exec_channel *src1)
4591 {
4592 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
4593 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
4594 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
4595 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
4596 }
4597
4598 static void
4599 micro_umul(union tgsi_exec_channel *dst,
4600 const union tgsi_exec_channel *src0,
4601 const union tgsi_exec_channel *src1)
4602 {
4603 dst->u[0] = src0->u[0] * src1->u[0];
4604 dst->u[1] = src0->u[1] * src1->u[1];
4605 dst->u[2] = src0->u[2] * src1->u[2];
4606 dst->u[3] = src0->u[3] * src1->u[3];
4607 }
4608
4609 static void
4610 micro_imul_hi(union tgsi_exec_channel *dst,
4611 const union tgsi_exec_channel *src0,
4612 const union tgsi_exec_channel *src1)
4613 {
4614 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4615 dst->i[0] = I64M(src0->i[0], src1->i[0]);
4616 dst->i[1] = I64M(src0->i[1], src1->i[1]);
4617 dst->i[2] = I64M(src0->i[2], src1->i[2]);
4618 dst->i[3] = I64M(src0->i[3], src1->i[3]);
4619 #undef I64M
4620 }
4621
4622 static void
4623 micro_umul_hi(union tgsi_exec_channel *dst,
4624 const union tgsi_exec_channel *src0,
4625 const union tgsi_exec_channel *src1)
4626 {
4627 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4628 dst->u[0] = U64M(src0->u[0], src1->u[0]);
4629 dst->u[1] = U64M(src0->u[1], src1->u[1]);
4630 dst->u[2] = U64M(src0->u[2], src1->u[2]);
4631 dst->u[3] = U64M(src0->u[3], src1->u[3]);
4632 #undef U64M
4633 }
4634
4635 static void
4636 micro_useq(union tgsi_exec_channel *dst,
4637 const union tgsi_exec_channel *src0,
4638 const union tgsi_exec_channel *src1)
4639 {
4640 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
4641 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
4642 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
4643 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
4644 }
4645
4646 static void
4647 micro_usge(union tgsi_exec_channel *dst,
4648 const union tgsi_exec_channel *src0,
4649 const union tgsi_exec_channel *src1)
4650 {
4651 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
4652 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
4653 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
4654 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
4655 }
4656
4657 static void
4658 micro_ushr(union tgsi_exec_channel *dst,
4659 const union tgsi_exec_channel *src0,
4660 const union tgsi_exec_channel *src1)
4661 {
4662 unsigned masked_count;
4663 masked_count = src1->u[0] & 0x1f;
4664 dst->u[0] = src0->u[0] >> masked_count;
4665 masked_count = src1->u[1] & 0x1f;
4666 dst->u[1] = src0->u[1] >> masked_count;
4667 masked_count = src1->u[2] & 0x1f;
4668 dst->u[2] = src0->u[2] >> masked_count;
4669 masked_count = src1->u[3] & 0x1f;
4670 dst->u[3] = src0->u[3] >> masked_count;
4671 }
4672
4673 static void
4674 micro_uslt(union tgsi_exec_channel *dst,
4675 const union tgsi_exec_channel *src0,
4676 const union tgsi_exec_channel *src1)
4677 {
4678 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
4679 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
4680 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
4681 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
4682 }
4683
4684 static void
4685 micro_usne(union tgsi_exec_channel *dst,
4686 const union tgsi_exec_channel *src0,
4687 const union tgsi_exec_channel *src1)
4688 {
4689 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
4690 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
4691 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
4692 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
4693 }
4694
4695 static void
4696 micro_uarl(union tgsi_exec_channel *dst,
4697 const union tgsi_exec_channel *src)
4698 {
4699 dst->i[0] = src->u[0];
4700 dst->i[1] = src->u[1];
4701 dst->i[2] = src->u[2];
4702 dst->i[3] = src->u[3];
4703 }
4704
4705 static void
4706 micro_ucmp(union tgsi_exec_channel *dst,
4707 const union tgsi_exec_channel *src0,
4708 const union tgsi_exec_channel *src1,
4709 const union tgsi_exec_channel *src2)
4710 {
4711 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
4712 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
4713 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
4714 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
4715 }
4716
4717 /**
4718 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4719 */
4720 static void
4721 micro_ibfe(union tgsi_exec_channel *dst,
4722 const union tgsi_exec_channel *src0,
4723 const union tgsi_exec_channel *src1,
4724 const union tgsi_exec_channel *src2)
4725 {
4726 int i;
4727 for (i = 0; i < 4; i++) {
4728 int width = src2->i[i] & 0x1f;
4729 int offset = src1->i[i] & 0x1f;
4730 if (width == 0)
4731 dst->i[i] = 0;
4732 else if (width + offset < 32)
4733 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
4734 else
4735 dst->i[i] = src0->i[i] >> offset;
4736 }
4737 }
4738
4739 /**
4740 * Unsigned bitfield extract
4741 */
4742 static void
4743 micro_ubfe(union tgsi_exec_channel *dst,
4744 const union tgsi_exec_channel *src0,
4745 const union tgsi_exec_channel *src1,
4746 const union tgsi_exec_channel *src2)
4747 {
4748 int i;
4749 for (i = 0; i < 4; i++) {
4750 int width = src2->u[i] & 0x1f;
4751 int offset = src1->u[i] & 0x1f;
4752 if (width == 0)
4753 dst->u[i] = 0;
4754 else if (width + offset < 32)
4755 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
4756 else
4757 dst->u[i] = src0->u[i] >> offset;
4758 }
4759 }
4760
4761 /**
4762 * Bitfield insert: copy low bits from src1 into a region of src0.
4763 */
4764 static void
4765 micro_bfi(union tgsi_exec_channel *dst,
4766 const union tgsi_exec_channel *src0,
4767 const union tgsi_exec_channel *src1,
4768 const union tgsi_exec_channel *src2,
4769 const union tgsi_exec_channel *src3)
4770 {
4771 int i;
4772 for (i = 0; i < 4; i++) {
4773 int width = src3->u[i] & 0x1f;
4774 int offset = src2->u[i] & 0x1f;
4775 int bitmask = ((1 << width) - 1) << offset;
4776 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
4777 }
4778 }
4779
4780 static void
4781 micro_brev(union tgsi_exec_channel *dst,
4782 const union tgsi_exec_channel *src)
4783 {
4784 dst->u[0] = util_bitreverse(src->u[0]);
4785 dst->u[1] = util_bitreverse(src->u[1]);
4786 dst->u[2] = util_bitreverse(src->u[2]);
4787 dst->u[3] = util_bitreverse(src->u[3]);
4788 }
4789
4790 static void
4791 micro_popc(union tgsi_exec_channel *dst,
4792 const union tgsi_exec_channel *src)
4793 {
4794 dst->u[0] = util_bitcount(src->u[0]);
4795 dst->u[1] = util_bitcount(src->u[1]);
4796 dst->u[2] = util_bitcount(src->u[2]);
4797 dst->u[3] = util_bitcount(src->u[3]);
4798 }
4799
4800 static void
4801 micro_lsb(union tgsi_exec_channel *dst,
4802 const union tgsi_exec_channel *src)
4803 {
4804 dst->i[0] = ffs(src->u[0]) - 1;
4805 dst->i[1] = ffs(src->u[1]) - 1;
4806 dst->i[2] = ffs(src->u[2]) - 1;
4807 dst->i[3] = ffs(src->u[3]) - 1;
4808 }
4809
4810 static void
4811 micro_imsb(union tgsi_exec_channel *dst,
4812 const union tgsi_exec_channel *src)
4813 {
4814 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
4815 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
4816 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
4817 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
4818 }
4819
4820 static void
4821 micro_umsb(union tgsi_exec_channel *dst,
4822 const union tgsi_exec_channel *src)
4823 {
4824 dst->i[0] = util_last_bit(src->u[0]) - 1;
4825 dst->i[1] = util_last_bit(src->u[1]) - 1;
4826 dst->i[2] = util_last_bit(src->u[2]) - 1;
4827 dst->i[3] = util_last_bit(src->u[3]) - 1;
4828 }
4829
4830 /**
4831 * Execute a TGSI instruction.
4832 * Returns TRUE if a barrier instruction is hit,
4833 * otherwise FALSE.
4834 */
4835 static boolean
4836 exec_instruction(
4837 struct tgsi_exec_machine *mach,
4838 const struct tgsi_full_instruction *inst,
4839 int *pc )
4840 {
4841 union tgsi_exec_channel r[10];
4842
4843 (*pc)++;
4844
4845 switch (inst->Instruction.Opcode) {
4846 case TGSI_OPCODE_ARL:
4847 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4848 break;
4849
4850 case TGSI_OPCODE_MOV:
4851 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4852 break;
4853
4854 case TGSI_OPCODE_LIT:
4855 exec_lit(mach, inst);
4856 break;
4857
4858 case TGSI_OPCODE_RCP:
4859 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4860 break;
4861
4862 case TGSI_OPCODE_RSQ:
4863 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4864 break;
4865
4866 case TGSI_OPCODE_EXP:
4867 exec_exp(mach, inst);
4868 break;
4869
4870 case TGSI_OPCODE_LOG:
4871 exec_log(mach, inst);
4872 break;
4873
4874 case TGSI_OPCODE_MUL:
4875 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4876 break;
4877
4878 case TGSI_OPCODE_ADD:
4879 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4880 break;
4881
4882 case TGSI_OPCODE_DP3:
4883 exec_dp3(mach, inst);
4884 break;
4885
4886 case TGSI_OPCODE_DP4:
4887 exec_dp4(mach, inst);
4888 break;
4889
4890 case TGSI_OPCODE_DST:
4891 exec_dst(mach, inst);
4892 break;
4893
4894 case TGSI_OPCODE_MIN:
4895 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4896 break;
4897
4898 case TGSI_OPCODE_MAX:
4899 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4900 break;
4901
4902 case TGSI_OPCODE_SLT:
4903 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4904 break;
4905
4906 case TGSI_OPCODE_SGE:
4907 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4908 break;
4909
4910 case TGSI_OPCODE_MAD:
4911 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4912 break;
4913
4914 case TGSI_OPCODE_SUB:
4915 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4916 break;
4917
4918 case TGSI_OPCODE_LRP:
4919 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4920 break;
4921
4922 case TGSI_OPCODE_SQRT:
4923 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4924 break;
4925
4926 case TGSI_OPCODE_DP2A:
4927 exec_dp2a(mach, inst);
4928 break;
4929
4930 case TGSI_OPCODE_FRC:
4931 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4932 break;
4933
4934 case TGSI_OPCODE_CLAMP:
4935 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4936 break;
4937
4938 case TGSI_OPCODE_FLR:
4939 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4940 break;
4941
4942 case TGSI_OPCODE_ROUND:
4943 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4944 break;
4945
4946 case TGSI_OPCODE_EX2:
4947 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4948 break;
4949
4950 case TGSI_OPCODE_LG2:
4951 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4952 break;
4953
4954 case TGSI_OPCODE_POW:
4955 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4956 break;
4957
4958 case TGSI_OPCODE_XPD:
4959 exec_xpd(mach, inst);
4960 break;
4961
4962 case TGSI_OPCODE_ABS:
4963 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4964 break;
4965
4966 case TGSI_OPCODE_DPH:
4967 exec_dph(mach, inst);
4968 break;
4969
4970 case TGSI_OPCODE_COS:
4971 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4972 break;
4973
4974 case TGSI_OPCODE_DDX:
4975 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4976 break;
4977
4978 case TGSI_OPCODE_DDY:
4979 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4980 break;
4981
4982 case TGSI_OPCODE_KILL:
4983 exec_kill (mach, inst);
4984 break;
4985
4986 case TGSI_OPCODE_KILL_IF:
4987 exec_kill_if (mach, inst);
4988 break;
4989
4990 case TGSI_OPCODE_PK2H:
4991 exec_pk2h(mach, inst);
4992 break;
4993
4994 case TGSI_OPCODE_PK2US:
4995 assert (0);
4996 break;
4997
4998 case TGSI_OPCODE_PK4B:
4999 assert (0);
5000 break;
5001
5002 case TGSI_OPCODE_PK4UB:
5003 assert (0);
5004 break;
5005
5006 case TGSI_OPCODE_SEQ:
5007 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5008 break;
5009
5010 case TGSI_OPCODE_SGT:
5011 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5012 break;
5013
5014 case TGSI_OPCODE_SIN:
5015 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5016 break;
5017
5018 case TGSI_OPCODE_SLE:
5019 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5020 break;
5021
5022 case TGSI_OPCODE_SNE:
5023 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5024 break;
5025
5026 case TGSI_OPCODE_TEX:
5027 /* simple texture lookup */
5028 /* src[0] = texcoord */
5029 /* src[1] = sampler unit */
5030 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
5031 break;
5032
5033 case TGSI_OPCODE_TXB:
5034 /* Texture lookup with lod bias */
5035 /* src[0] = texcoord (src[0].w = LOD bias) */
5036 /* src[1] = sampler unit */
5037 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
5038 break;
5039
5040 case TGSI_OPCODE_TXD:
5041 /* Texture lookup with explict partial derivatives */
5042 /* src[0] = texcoord */
5043 /* src[1] = d[strq]/dx */
5044 /* src[2] = d[strq]/dy */
5045 /* src[3] = sampler unit */
5046 exec_txd(mach, inst);
5047 break;
5048
5049 case TGSI_OPCODE_TXL:
5050 /* Texture lookup with explit LOD */
5051 /* src[0] = texcoord (src[0].w = LOD) */
5052 /* src[1] = sampler unit */
5053 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
5054 break;
5055
5056 case TGSI_OPCODE_TXP:
5057 /* Texture lookup with projection */
5058 /* src[0] = texcoord (src[0].w = projection) */
5059 /* src[1] = sampler unit */
5060 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
5061 break;
5062
5063 case TGSI_OPCODE_TG4:
5064 /* src[0] = texcoord */
5065 /* src[1] = component */
5066 /* src[2] = sampler unit */
5067 exec_tex(mach, inst, TEX_MODIFIER_GATHER, 2);
5068 break;
5069
5070 case TGSI_OPCODE_LODQ:
5071 /* src[0] = texcoord */
5072 /* src[1] = sampler unit */
5073 exec_lodq(mach, inst);
5074 break;
5075
5076 case TGSI_OPCODE_UP2H:
5077 exec_up2h(mach, inst);
5078 break;
5079
5080 case TGSI_OPCODE_UP2US:
5081 assert (0);
5082 break;
5083
5084 case TGSI_OPCODE_UP4B:
5085 assert (0);
5086 break;
5087
5088 case TGSI_OPCODE_UP4UB:
5089 assert (0);
5090 break;
5091
5092 case TGSI_OPCODE_ARR:
5093 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5094 break;
5095
5096 case TGSI_OPCODE_CAL:
5097 /* skip the call if no execution channels are enabled */
5098 if (mach->ExecMask) {
5099 /* do the call */
5100
5101 /* First, record the depths of the execution stacks.
5102 * This is important for deeply nested/looped return statements.
5103 * We have to unwind the stacks by the correct amount. For a
5104 * real code generator, we could determine the number of entries
5105 * to pop off each stack with simple static analysis and avoid
5106 * implementing this data structure at run time.
5107 */
5108 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
5109 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
5110 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
5111 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
5112 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
5113 /* note that PC was already incremented above */
5114 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
5115
5116 mach->CallStackTop++;
5117
5118 /* Second, push the Cond, Loop, Cont, Func stacks */
5119 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5120 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5121 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5122 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
5123 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5124 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
5125
5126 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5127 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5128 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5129 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
5130 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5131 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
5132
5133 /* Finally, jump to the subroutine. The label is a pointer
5134 * (an instruction number) to the BGNSUB instruction.
5135 */
5136 *pc = inst->Label.Label;
5137 assert(mach->Instructions[*pc].Instruction.Opcode
5138 == TGSI_OPCODE_BGNSUB);
5139 }
5140 break;
5141
5142 case TGSI_OPCODE_RET:
5143 mach->FuncMask &= ~mach->ExecMask;
5144 UPDATE_EXEC_MASK(mach);
5145
5146 if (mach->FuncMask == 0x0) {
5147 /* really return now (otherwise, keep executing */
5148
5149 if (mach->CallStackTop == 0) {
5150 /* returning from main() */
5151 mach->CondStackTop = 0;
5152 mach->LoopStackTop = 0;
5153 mach->ContStackTop = 0;
5154 mach->LoopLabelStackTop = 0;
5155 mach->SwitchStackTop = 0;
5156 mach->BreakStackTop = 0;
5157 *pc = -1;
5158 return FALSE;
5159 }
5160
5161 assert(mach->CallStackTop > 0);
5162 mach->CallStackTop--;
5163
5164 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5165 mach->CondMask = mach->CondStack[mach->CondStackTop];
5166
5167 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5168 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5169
5170 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5171 mach->ContMask = mach->ContStack[mach->ContStackTop];
5172
5173 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5174 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5175
5176 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5177 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5178
5179 assert(mach->FuncStackTop > 0);
5180 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5181
5182 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5183
5184 UPDATE_EXEC_MASK(mach);
5185 }
5186 break;
5187
5188 case TGSI_OPCODE_SSG:
5189 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5190 break;
5191
5192 case TGSI_OPCODE_CMP:
5193 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5194 break;
5195
5196 case TGSI_OPCODE_SCS:
5197 exec_scs(mach, inst);
5198 break;
5199
5200 case TGSI_OPCODE_DIV:
5201 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5202 break;
5203
5204 case TGSI_OPCODE_DP2:
5205 exec_dp2(mach, inst);
5206 break;
5207
5208 case TGSI_OPCODE_IF:
5209 /* push CondMask */
5210 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5211 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5212 FETCH( &r[0], 0, TGSI_CHAN_X );
5213 /* update CondMask */
5214 if( ! r[0].f[0] ) {
5215 mach->CondMask &= ~0x1;
5216 }
5217 if( ! r[0].f[1] ) {
5218 mach->CondMask &= ~0x2;
5219 }
5220 if( ! r[0].f[2] ) {
5221 mach->CondMask &= ~0x4;
5222 }
5223 if( ! r[0].f[3] ) {
5224 mach->CondMask &= ~0x8;
5225 }
5226 UPDATE_EXEC_MASK(mach);
5227 /* Todo: If CondMask==0, jump to ELSE */
5228 break;
5229
5230 case TGSI_OPCODE_UIF:
5231 /* push CondMask */
5232 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5233 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5234 IFETCH( &r[0], 0, TGSI_CHAN_X );
5235 /* update CondMask */
5236 if( ! r[0].u[0] ) {
5237 mach->CondMask &= ~0x1;
5238 }
5239 if( ! r[0].u[1] ) {
5240 mach->CondMask &= ~0x2;
5241 }
5242 if( ! r[0].u[2] ) {
5243 mach->CondMask &= ~0x4;
5244 }
5245 if( ! r[0].u[3] ) {
5246 mach->CondMask &= ~0x8;
5247 }
5248 UPDATE_EXEC_MASK(mach);
5249 /* Todo: If CondMask==0, jump to ELSE */
5250 break;
5251
5252 case TGSI_OPCODE_ELSE:
5253 /* invert CondMask wrt previous mask */
5254 {
5255 uint prevMask;
5256 assert(mach->CondStackTop > 0);
5257 prevMask = mach->CondStack[mach->CondStackTop - 1];
5258 mach->CondMask = ~mach->CondMask & prevMask;
5259 UPDATE_EXEC_MASK(mach);
5260 /* Todo: If CondMask==0, jump to ENDIF */
5261 }
5262 break;
5263
5264 case TGSI_OPCODE_ENDIF:
5265 /* pop CondMask */
5266 assert(mach->CondStackTop > 0);
5267 mach->CondMask = mach->CondStack[--mach->CondStackTop];
5268 UPDATE_EXEC_MASK(mach);
5269 break;
5270
5271 case TGSI_OPCODE_END:
5272 /* make sure we end primitives which haven't
5273 * been explicitly emitted */
5274 conditional_emit_primitive(mach);
5275 /* halt execution */
5276 *pc = -1;
5277 break;
5278
5279 case TGSI_OPCODE_PUSHA:
5280 assert (0);
5281 break;
5282
5283 case TGSI_OPCODE_POPA:
5284 assert (0);
5285 break;
5286
5287 case TGSI_OPCODE_CEIL:
5288 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5289 break;
5290
5291 case TGSI_OPCODE_I2F:
5292 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
5293 break;
5294
5295 case TGSI_OPCODE_NOT:
5296 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5297 break;
5298
5299 case TGSI_OPCODE_TRUNC:
5300 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5301 break;
5302
5303 case TGSI_OPCODE_SHL:
5304 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5305 break;
5306
5307 case TGSI_OPCODE_AND:
5308 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5309 break;
5310
5311 case TGSI_OPCODE_OR:
5312 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5313 break;
5314
5315 case TGSI_OPCODE_MOD:
5316 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5317 break;
5318
5319 case TGSI_OPCODE_XOR:
5320 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5321 break;
5322
5323 case TGSI_OPCODE_SAD:
5324 assert (0);
5325 break;
5326
5327 case TGSI_OPCODE_TXF:
5328 exec_txf(mach, inst);
5329 break;
5330
5331 case TGSI_OPCODE_TXQ:
5332 exec_txq(mach, inst);
5333 break;
5334
5335 case TGSI_OPCODE_EMIT:
5336 emit_vertex(mach);
5337 break;
5338
5339 case TGSI_OPCODE_ENDPRIM:
5340 emit_primitive(mach);
5341 break;
5342
5343 case TGSI_OPCODE_BGNLOOP:
5344 /* push LoopMask and ContMasks */
5345 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5346 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5347 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5348 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5349
5350 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5351 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5352 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
5353 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5354 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
5355 break;
5356
5357 case TGSI_OPCODE_ENDLOOP:
5358 /* Restore ContMask, but don't pop */
5359 assert(mach->ContStackTop > 0);
5360 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
5361 UPDATE_EXEC_MASK(mach);
5362 if (mach->ExecMask) {
5363 /* repeat loop: jump to instruction just past BGNLOOP */
5364 assert(mach->LoopLabelStackTop > 0);
5365 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
5366 }
5367 else {
5368 /* exit loop: pop LoopMask */
5369 assert(mach->LoopStackTop > 0);
5370 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
5371 /* pop ContMask */
5372 assert(mach->ContStackTop > 0);
5373 mach->ContMask = mach->ContStack[--mach->ContStackTop];
5374 assert(mach->LoopLabelStackTop > 0);
5375 --mach->LoopLabelStackTop;
5376
5377 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
5378 }
5379 UPDATE_EXEC_MASK(mach);
5380 break;
5381
5382 case TGSI_OPCODE_BRK:
5383 exec_break(mach);
5384 break;
5385
5386 case TGSI_OPCODE_CONT:
5387 /* turn off cont channels for each enabled exec channel */
5388 mach->ContMask &= ~mach->ExecMask;
5389 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5390 UPDATE_EXEC_MASK(mach);
5391 break;
5392
5393 case TGSI_OPCODE_BGNSUB:
5394 /* no-op */
5395 break;
5396
5397 case TGSI_OPCODE_ENDSUB:
5398 /*
5399 * XXX: This really should be a no-op. We should never reach this opcode.
5400 */
5401
5402 assert(mach->CallStackTop > 0);
5403 mach->CallStackTop--;
5404
5405 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5406 mach->CondMask = mach->CondStack[mach->CondStackTop];
5407
5408 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5409 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5410
5411 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5412 mach->ContMask = mach->ContStack[mach->ContStackTop];
5413
5414 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5415 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5416
5417 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5418 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5419
5420 assert(mach->FuncStackTop > 0);
5421 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5422
5423 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5424
5425 UPDATE_EXEC_MASK(mach);
5426 break;
5427
5428 case TGSI_OPCODE_NOP:
5429 break;
5430
5431 case TGSI_OPCODE_BREAKC:
5432 IFETCH(&r[0], 0, TGSI_CHAN_X);
5433 /* update CondMask */
5434 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
5435 mach->LoopMask &= ~0x1;
5436 }
5437 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
5438 mach->LoopMask &= ~0x2;
5439 }
5440 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
5441 mach->LoopMask &= ~0x4;
5442 }
5443 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
5444 mach->LoopMask &= ~0x8;
5445 }
5446 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5447 UPDATE_EXEC_MASK(mach);
5448 break;
5449
5450 case TGSI_OPCODE_F2I:
5451 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5452 break;
5453
5454 case TGSI_OPCODE_FSEQ:
5455 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5456 break;
5457
5458 case TGSI_OPCODE_FSGE:
5459 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5460 break;
5461
5462 case TGSI_OPCODE_FSLT:
5463 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5464 break;
5465
5466 case TGSI_OPCODE_FSNE:
5467 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5468 break;
5469
5470 case TGSI_OPCODE_IDIV:
5471 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5472 break;
5473
5474 case TGSI_OPCODE_IMAX:
5475 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5476 break;
5477
5478 case TGSI_OPCODE_IMIN:
5479 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5480 break;
5481
5482 case TGSI_OPCODE_INEG:
5483 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5484 break;
5485
5486 case TGSI_OPCODE_ISGE:
5487 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5488 break;
5489
5490 case TGSI_OPCODE_ISHR:
5491 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5492 break;
5493
5494 case TGSI_OPCODE_ISLT:
5495 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5496 break;
5497
5498 case TGSI_OPCODE_F2U:
5499 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5500 break;
5501
5502 case TGSI_OPCODE_U2F:
5503 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
5504 break;
5505
5506 case TGSI_OPCODE_UADD:
5507 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5508 break;
5509
5510 case TGSI_OPCODE_UDIV:
5511 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5512 break;
5513
5514 case TGSI_OPCODE_UMAD:
5515 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5516 break;
5517
5518 case TGSI_OPCODE_UMAX:
5519 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5520 break;
5521
5522 case TGSI_OPCODE_UMIN:
5523 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5524 break;
5525
5526 case TGSI_OPCODE_UMOD:
5527 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5528 break;
5529
5530 case TGSI_OPCODE_UMUL:
5531 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5532 break;
5533
5534 case TGSI_OPCODE_IMUL_HI:
5535 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5536 break;
5537
5538 case TGSI_OPCODE_UMUL_HI:
5539 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5540 break;
5541
5542 case TGSI_OPCODE_USEQ:
5543 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5544 break;
5545
5546 case TGSI_OPCODE_USGE:
5547 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5548 break;
5549
5550 case TGSI_OPCODE_USHR:
5551 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5552 break;
5553
5554 case TGSI_OPCODE_USLT:
5555 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5556 break;
5557
5558 case TGSI_OPCODE_USNE:
5559 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5560 break;
5561
5562 case TGSI_OPCODE_SWITCH:
5563 exec_switch(mach, inst);
5564 break;
5565
5566 case TGSI_OPCODE_CASE:
5567 exec_case(mach, inst);
5568 break;
5569
5570 case TGSI_OPCODE_DEFAULT:
5571 exec_default(mach);
5572 break;
5573
5574 case TGSI_OPCODE_ENDSWITCH:
5575 exec_endswitch(mach);
5576 break;
5577
5578 case TGSI_OPCODE_SAMPLE_I:
5579 exec_txf(mach, inst);
5580 break;
5581
5582 case TGSI_OPCODE_SAMPLE_I_MS:
5583 exec_txf(mach, inst);
5584 break;
5585
5586 case TGSI_OPCODE_SAMPLE:
5587 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
5588 break;
5589
5590 case TGSI_OPCODE_SAMPLE_B:
5591 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
5592 break;
5593
5594 case TGSI_OPCODE_SAMPLE_C:
5595 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
5596 break;
5597
5598 case TGSI_OPCODE_SAMPLE_C_LZ:
5599 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
5600 break;
5601
5602 case TGSI_OPCODE_SAMPLE_D:
5603 exec_sample_d(mach, inst);
5604 break;
5605
5606 case TGSI_OPCODE_SAMPLE_L:
5607 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
5608 break;
5609
5610 case TGSI_OPCODE_GATHER4:
5611 assert(0);
5612 break;
5613
5614 case TGSI_OPCODE_SVIEWINFO:
5615 exec_txq(mach, inst);
5616 break;
5617
5618 case TGSI_OPCODE_SAMPLE_POS:
5619 assert(0);
5620 break;
5621
5622 case TGSI_OPCODE_SAMPLE_INFO:
5623 assert(0);
5624 break;
5625
5626 case TGSI_OPCODE_UARL:
5627 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5628 break;
5629
5630 case TGSI_OPCODE_UCMP:
5631 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5632 break;
5633
5634 case TGSI_OPCODE_IABS:
5635 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5636 break;
5637
5638 case TGSI_OPCODE_ISSG:
5639 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5640 break;
5641
5642 case TGSI_OPCODE_TEX2:
5643 /* simple texture lookup */
5644 /* src[0] = texcoord */
5645 /* src[1] = compare */
5646 /* src[2] = sampler unit */
5647 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
5648 break;
5649 case TGSI_OPCODE_TXB2:
5650 /* simple texture lookup */
5651 /* src[0] = texcoord */
5652 /* src[1] = bias */
5653 /* src[2] = sampler unit */
5654 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
5655 break;
5656 case TGSI_OPCODE_TXL2:
5657 /* simple texture lookup */
5658 /* src[0] = texcoord */
5659 /* src[1] = lod */
5660 /* src[2] = sampler unit */
5661 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
5662 break;
5663
5664 case TGSI_OPCODE_IBFE:
5665 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5666 break;
5667 case TGSI_OPCODE_UBFE:
5668 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5669 break;
5670 case TGSI_OPCODE_BFI:
5671 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5672 break;
5673 case TGSI_OPCODE_BREV:
5674 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5675 break;
5676 case TGSI_OPCODE_POPC:
5677 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5678 break;
5679 case TGSI_OPCODE_LSB:
5680 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5681 break;
5682 case TGSI_OPCODE_IMSB:
5683 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5684 break;
5685 case TGSI_OPCODE_UMSB:
5686 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5687 break;
5688
5689 case TGSI_OPCODE_F2D:
5690 exec_f2d(mach, inst);
5691 break;
5692
5693 case TGSI_OPCODE_D2F:
5694 exec_d2f(mach, inst);
5695 break;
5696
5697 case TGSI_OPCODE_DABS:
5698 exec_double_unary(mach, inst, micro_dabs);
5699 break;
5700
5701 case TGSI_OPCODE_DNEG:
5702 exec_double_unary(mach, inst, micro_dneg);
5703 break;
5704
5705 case TGSI_OPCODE_DADD:
5706 exec_double_binary(mach, inst, micro_dadd, TGSI_EXEC_DATA_DOUBLE);
5707 break;
5708
5709 case TGSI_OPCODE_DMUL:
5710 exec_double_binary(mach, inst, micro_dmul, TGSI_EXEC_DATA_DOUBLE);
5711 break;
5712
5713 case TGSI_OPCODE_DMAX:
5714 exec_double_binary(mach, inst, micro_dmax, TGSI_EXEC_DATA_DOUBLE);
5715 break;
5716
5717 case TGSI_OPCODE_DMIN:
5718 exec_double_binary(mach, inst, micro_dmin, TGSI_EXEC_DATA_DOUBLE);
5719 break;
5720
5721 case TGSI_OPCODE_DSLT:
5722 exec_double_binary(mach, inst, micro_dslt, TGSI_EXEC_DATA_UINT);
5723 break;
5724
5725 case TGSI_OPCODE_DSGE:
5726 exec_double_binary(mach, inst, micro_dsge, TGSI_EXEC_DATA_UINT);
5727 break;
5728
5729 case TGSI_OPCODE_DSEQ:
5730 exec_double_binary(mach, inst, micro_dseq, TGSI_EXEC_DATA_UINT);
5731 break;
5732
5733 case TGSI_OPCODE_DSNE:
5734 exec_double_binary(mach, inst, micro_dsne, TGSI_EXEC_DATA_UINT);
5735 break;
5736
5737 case TGSI_OPCODE_DRCP:
5738 exec_double_unary(mach, inst, micro_drcp);
5739 break;
5740
5741 case TGSI_OPCODE_DSQRT:
5742 exec_double_unary(mach, inst, micro_dsqrt);
5743 break;
5744
5745 case TGSI_OPCODE_DRSQ:
5746 exec_double_unary(mach, inst, micro_drsq);
5747 break;
5748
5749 case TGSI_OPCODE_DMAD:
5750 exec_double_trinary(mach, inst, micro_dmad);
5751 break;
5752
5753 case TGSI_OPCODE_DFRAC:
5754 exec_double_unary(mach, inst, micro_dfrac);
5755 break;
5756
5757 case TGSI_OPCODE_DLDEXP:
5758 exec_dldexp(mach, inst);
5759 break;
5760
5761 case TGSI_OPCODE_DFRACEXP:
5762 exec_dfracexp(mach, inst);
5763 break;
5764
5765 case TGSI_OPCODE_I2D:
5766 exec_i2d(mach, inst);
5767 break;
5768
5769 case TGSI_OPCODE_D2I:
5770 exec_d2i(mach, inst);
5771 break;
5772
5773 case TGSI_OPCODE_U2D:
5774 exec_u2d(mach, inst);
5775 break;
5776
5777 case TGSI_OPCODE_D2U:
5778 exec_d2u(mach, inst);
5779 break;
5780
5781 case TGSI_OPCODE_LOAD:
5782 exec_load(mach, inst);
5783 break;
5784
5785 case TGSI_OPCODE_STORE:
5786 exec_store(mach, inst);
5787 break;
5788
5789 case TGSI_OPCODE_ATOMUADD:
5790 case TGSI_OPCODE_ATOMXCHG:
5791 case TGSI_OPCODE_ATOMCAS:
5792 case TGSI_OPCODE_ATOMAND:
5793 case TGSI_OPCODE_ATOMOR:
5794 case TGSI_OPCODE_ATOMXOR:
5795 case TGSI_OPCODE_ATOMUMIN:
5796 case TGSI_OPCODE_ATOMUMAX:
5797 case TGSI_OPCODE_ATOMIMIN:
5798 case TGSI_OPCODE_ATOMIMAX:
5799 exec_atomop(mach, inst);
5800 break;
5801
5802 case TGSI_OPCODE_RESQ:
5803 exec_resq(mach, inst);
5804 break;
5805 case TGSI_OPCODE_BARRIER:
5806 case TGSI_OPCODE_MEMBAR:
5807 return TRUE;
5808 break;
5809 default:
5810 assert( 0 );
5811 }
5812 return FALSE;
5813 }
5814
5815 static void
5816 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine *mach)
5817 {
5818 uint default_mask = 0xf;
5819
5820 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
5821 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
5822
5823 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
5824 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
5825 mach->Primitives[0] = 0;
5826 /* GS runs on a single primitive for now */
5827 default_mask = 0x1;
5828 }
5829
5830 if (mach->NonHelperMask == 0)
5831 mach->NonHelperMask = default_mask;
5832 mach->CondMask = default_mask;
5833 mach->LoopMask = default_mask;
5834 mach->ContMask = default_mask;
5835 mach->FuncMask = default_mask;
5836 mach->ExecMask = default_mask;
5837
5838 mach->Switch.mask = default_mask;
5839
5840 assert(mach->CondStackTop == 0);
5841 assert(mach->LoopStackTop == 0);
5842 assert(mach->ContStackTop == 0);
5843 assert(mach->SwitchStackTop == 0);
5844 assert(mach->BreakStackTop == 0);
5845 assert(mach->CallStackTop == 0);
5846 }
5847
5848 /**
5849 * Run TGSI interpreter.
5850 * \return bitmask of "alive" quad components
5851 */
5852 uint
5853 tgsi_exec_machine_run( struct tgsi_exec_machine *mach, int start_pc )
5854 {
5855 uint i;
5856
5857 mach->pc = start_pc;
5858
5859 if (!start_pc) {
5860 tgsi_exec_machine_setup_masks(mach);
5861
5862 /* execute declarations (interpolants) */
5863 for (i = 0; i < mach->NumDeclarations; i++) {
5864 exec_declaration( mach, mach->Declarations+i );
5865 }
5866 }
5867
5868 {
5869 #if DEBUG_EXECUTION
5870 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
5871 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
5872 uint inst = 1;
5873
5874 if (!start_pc) {
5875 memset(mach->Temps, 0, sizeof(temps));
5876 if (mach->Outputs)
5877 memset(mach->Outputs, 0, sizeof(outputs));
5878 memset(temps, 0, sizeof(temps));
5879 memset(outputs, 0, sizeof(outputs));
5880 }
5881 #endif
5882
5883 /* execute instructions, until pc is set to -1 */
5884 while (mach->pc != -1) {
5885 boolean barrier_hit;
5886 #if DEBUG_EXECUTION
5887 uint i;
5888
5889 tgsi_dump_instruction(&mach->Instructions[mach->pc], inst++);
5890 #endif
5891
5892 assert(mach->pc < (int) mach->NumInstructions);
5893 barrier_hit = exec_instruction(mach, mach->Instructions + mach->pc, &mach->pc);
5894
5895 /* for compute shaders if we hit a barrier return now for later rescheduling */
5896 if (barrier_hit && mach->ShaderType == PIPE_SHADER_COMPUTE)
5897 return 0;
5898
5899 #if DEBUG_EXECUTION
5900 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
5901 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
5902 uint j;
5903
5904 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
5905 debug_printf("TEMP[%2u] = ", i);
5906 for (j = 0; j < 4; j++) {
5907 if (j > 0) {
5908 debug_printf(" ");
5909 }
5910 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5911 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
5912 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
5913 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
5914 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
5915 }
5916 }
5917 }
5918 if (mach->Outputs) {
5919 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
5920 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
5921 uint j;
5922
5923 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
5924 debug_printf("OUT[%2u] = ", i);
5925 for (j = 0; j < 4; j++) {
5926 if (j > 0) {
5927 debug_printf(" ");
5928 }
5929 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5930 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
5931 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
5932 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
5933 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
5934 }
5935 }
5936 }
5937 }
5938 #endif
5939 }
5940 }
5941
5942 #if 0
5943 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5944 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
5945 /*
5946 * Scale back depth component.
5947 */
5948 for (i = 0; i < 4; i++)
5949 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
5950 }
5951 #endif
5952
5953 /* Strictly speaking, these assertions aren't really needed but they
5954 * can potentially catch some bugs in the control flow code.
5955 */
5956 assert(mach->CondStackTop == 0);
5957 assert(mach->LoopStackTop == 0);
5958 assert(mach->ContStackTop == 0);
5959 assert(mach->SwitchStackTop == 0);
5960 assert(mach->BreakStackTop == 0);
5961 assert(mach->CallStackTop == 0);
5962
5963 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
5964 }