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[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define FAST_MATH 1
66
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
71
72 static void
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
75 {
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
80 }
81
82 static void
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
85 {
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
90 }
91
92 static void
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
95 {
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
100 }
101
102 static void
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
105 {
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
110 }
111
112 static void
113 micro_cos(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src)
115 {
116 dst->f[0] = cosf(src->f[0]);
117 dst->f[1] = cosf(src->f[1]);
118 dst->f[2] = cosf(src->f[2]);
119 dst->f[3] = cosf(src->f[3]);
120 }
121
122 static void
123 micro_ddx(union tgsi_exec_channel *dst,
124 const union tgsi_exec_channel *src)
125 {
126 dst->f[0] =
127 dst->f[1] =
128 dst->f[2] =
129 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
130 }
131
132 static void
133 micro_ddy(union tgsi_exec_channel *dst,
134 const union tgsi_exec_channel *src)
135 {
136 dst->f[0] =
137 dst->f[1] =
138 dst->f[2] =
139 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
140 }
141
142 static void
143 micro_exp2(union tgsi_exec_channel *dst,
144 const union tgsi_exec_channel *src)
145 {
146 #if FAST_MATH
147 dst->f[0] = util_fast_exp2(src->f[0]);
148 dst->f[1] = util_fast_exp2(src->f[1]);
149 dst->f[2] = util_fast_exp2(src->f[2]);
150 dst->f[3] = util_fast_exp2(src->f[3]);
151 #else
152 #if DEBUG
153 /* Inf is okay for this instruction, so clamp it to silence assertions. */
154 uint i;
155 union tgsi_exec_channel clamped;
156
157 for (i = 0; i < 4; i++) {
158 if (src->f[i] > 127.99999f) {
159 clamped.f[i] = 127.99999f;
160 } else if (src->f[i] < -126.99999f) {
161 clamped.f[i] = -126.99999f;
162 } else {
163 clamped.f[i] = src->f[i];
164 }
165 }
166 src = &clamped;
167 #endif /* DEBUG */
168
169 dst->f[0] = powf(2.0f, src->f[0]);
170 dst->f[1] = powf(2.0f, src->f[1]);
171 dst->f[2] = powf(2.0f, src->f[2]);
172 dst->f[3] = powf(2.0f, src->f[3]);
173 #endif /* FAST_MATH */
174 }
175
176 static void
177 micro_flr(union tgsi_exec_channel *dst,
178 const union tgsi_exec_channel *src)
179 {
180 dst->f[0] = floorf(src->f[0]);
181 dst->f[1] = floorf(src->f[1]);
182 dst->f[2] = floorf(src->f[2]);
183 dst->f[3] = floorf(src->f[3]);
184 }
185
186 static void
187 micro_frc(union tgsi_exec_channel *dst,
188 const union tgsi_exec_channel *src)
189 {
190 dst->f[0] = src->f[0] - floorf(src->f[0]);
191 dst->f[1] = src->f[1] - floorf(src->f[1]);
192 dst->f[2] = src->f[2] - floorf(src->f[2]);
193 dst->f[3] = src->f[3] - floorf(src->f[3]);
194 }
195
196 static void
197 micro_iabs(union tgsi_exec_channel *dst,
198 const union tgsi_exec_channel *src)
199 {
200 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
201 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
202 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
203 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
204 }
205
206 static void
207 micro_ineg(union tgsi_exec_channel *dst,
208 const union tgsi_exec_channel *src)
209 {
210 dst->i[0] = -src->i[0];
211 dst->i[1] = -src->i[1];
212 dst->i[2] = -src->i[2];
213 dst->i[3] = -src->i[3];
214 }
215
216 static void
217 micro_lg2(union tgsi_exec_channel *dst,
218 const union tgsi_exec_channel *src)
219 {
220 #if FAST_MATH
221 dst->f[0] = util_fast_log2(src->f[0]);
222 dst->f[1] = util_fast_log2(src->f[1]);
223 dst->f[2] = util_fast_log2(src->f[2]);
224 dst->f[3] = util_fast_log2(src->f[3]);
225 #else
226 dst->f[0] = logf(src->f[0]) * 1.442695f;
227 dst->f[1] = logf(src->f[1]) * 1.442695f;
228 dst->f[2] = logf(src->f[2]) * 1.442695f;
229 dst->f[3] = logf(src->f[3]) * 1.442695f;
230 #endif
231 }
232
233 static void
234 micro_lrp(union tgsi_exec_channel *dst,
235 const union tgsi_exec_channel *src0,
236 const union tgsi_exec_channel *src1,
237 const union tgsi_exec_channel *src2)
238 {
239 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
240 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
241 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
242 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
243 }
244
245 static void
246 micro_mad(union tgsi_exec_channel *dst,
247 const union tgsi_exec_channel *src0,
248 const union tgsi_exec_channel *src1,
249 const union tgsi_exec_channel *src2)
250 {
251 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
252 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
253 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
254 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
255 }
256
257 static void
258 micro_mov(union tgsi_exec_channel *dst,
259 const union tgsi_exec_channel *src)
260 {
261 dst->u[0] = src->u[0];
262 dst->u[1] = src->u[1];
263 dst->u[2] = src->u[2];
264 dst->u[3] = src->u[3];
265 }
266
267 static void
268 micro_rcp(union tgsi_exec_channel *dst,
269 const union tgsi_exec_channel *src)
270 {
271 #if 0 /* for debugging */
272 assert(src->f[0] != 0.0f);
273 assert(src->f[1] != 0.0f);
274 assert(src->f[2] != 0.0f);
275 assert(src->f[3] != 0.0f);
276 #endif
277 dst->f[0] = 1.0f / src->f[0];
278 dst->f[1] = 1.0f / src->f[1];
279 dst->f[2] = 1.0f / src->f[2];
280 dst->f[3] = 1.0f / src->f[3];
281 }
282
283 static void
284 micro_rnd(union tgsi_exec_channel *dst,
285 const union tgsi_exec_channel *src)
286 {
287 dst->f[0] = floorf(src->f[0] + 0.5f);
288 dst->f[1] = floorf(src->f[1] + 0.5f);
289 dst->f[2] = floorf(src->f[2] + 0.5f);
290 dst->f[3] = floorf(src->f[3] + 0.5f);
291 }
292
293 static void
294 micro_rsq(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
296 {
297 #if 0 /* for debugging */
298 assert(src->f[0] != 0.0f);
299 assert(src->f[1] != 0.0f);
300 assert(src->f[2] != 0.0f);
301 assert(src->f[3] != 0.0f);
302 #endif
303 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
304 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
305 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
306 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
307 }
308
309 static void
310 micro_seq(union tgsi_exec_channel *dst,
311 const union tgsi_exec_channel *src0,
312 const union tgsi_exec_channel *src1)
313 {
314 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
315 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
316 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
317 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
318 }
319
320 static void
321 micro_sge(union tgsi_exec_channel *dst,
322 const union tgsi_exec_channel *src0,
323 const union tgsi_exec_channel *src1)
324 {
325 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
326 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
327 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
328 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
329 }
330
331 static void
332 micro_sgn(union tgsi_exec_channel *dst,
333 const union tgsi_exec_channel *src)
334 {
335 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
336 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
337 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
338 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
339 }
340
341 static void
342 micro_sgt(union tgsi_exec_channel *dst,
343 const union tgsi_exec_channel *src0,
344 const union tgsi_exec_channel *src1)
345 {
346 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
347 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
348 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
349 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
350 }
351
352 static void
353 micro_sin(union tgsi_exec_channel *dst,
354 const union tgsi_exec_channel *src)
355 {
356 dst->f[0] = sinf(src->f[0]);
357 dst->f[1] = sinf(src->f[1]);
358 dst->f[2] = sinf(src->f[2]);
359 dst->f[3] = sinf(src->f[3]);
360 }
361
362 static void
363 micro_sle(union tgsi_exec_channel *dst,
364 const union tgsi_exec_channel *src0,
365 const union tgsi_exec_channel *src1)
366 {
367 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
368 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
369 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
370 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
371 }
372
373 static void
374 micro_slt(union tgsi_exec_channel *dst,
375 const union tgsi_exec_channel *src0,
376 const union tgsi_exec_channel *src1)
377 {
378 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
379 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
380 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
381 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
382 }
383
384 static void
385 micro_sne(union tgsi_exec_channel *dst,
386 const union tgsi_exec_channel *src0,
387 const union tgsi_exec_channel *src1)
388 {
389 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
390 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
391 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
392 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
393 }
394
395 static void
396 micro_trunc(union tgsi_exec_channel *dst,
397 const union tgsi_exec_channel *src)
398 {
399 dst->f[0] = (float)(int)src->f[0];
400 dst->f[1] = (float)(int)src->f[1];
401 dst->f[2] = (float)(int)src->f[2];
402 dst->f[3] = (float)(int)src->f[3];
403 }
404
405
406 #define CHAN_X 0
407 #define CHAN_Y 1
408 #define CHAN_Z 2
409 #define CHAN_W 3
410
411 enum tgsi_exec_datatype {
412 TGSI_EXEC_DATA_FLOAT,
413 TGSI_EXEC_DATA_INT,
414 TGSI_EXEC_DATA_UINT
415 };
416
417 /*
418 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
419 */
420 #define TEMP_0_I TGSI_EXEC_TEMP_00000000_I
421 #define TEMP_0_C TGSI_EXEC_TEMP_00000000_C
422 #define TEMP_7F_I TGSI_EXEC_TEMP_7FFFFFFF_I
423 #define TEMP_7F_C TGSI_EXEC_TEMP_7FFFFFFF_C
424 #define TEMP_80_I TGSI_EXEC_TEMP_80000000_I
425 #define TEMP_80_C TGSI_EXEC_TEMP_80000000_C
426 #define TEMP_FF_I TGSI_EXEC_TEMP_FFFFFFFF_I
427 #define TEMP_FF_C TGSI_EXEC_TEMP_FFFFFFFF_C
428 #define TEMP_1_I TGSI_EXEC_TEMP_ONE_I
429 #define TEMP_1_C TGSI_EXEC_TEMP_ONE_C
430 #define TEMP_2_I TGSI_EXEC_TEMP_TWO_I
431 #define TEMP_2_C TGSI_EXEC_TEMP_TWO_C
432 #define TEMP_128_I TGSI_EXEC_TEMP_128_I
433 #define TEMP_128_C TGSI_EXEC_TEMP_128_C
434 #define TEMP_M128_I TGSI_EXEC_TEMP_MINUS_128_I
435 #define TEMP_M128_C TGSI_EXEC_TEMP_MINUS_128_C
436 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
437 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
438 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
439 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
440 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
441 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
442 #define TEMP_CC_I TGSI_EXEC_TEMP_CC_I
443 #define TEMP_CC_C TGSI_EXEC_TEMP_CC_C
444 #define TEMP_3_I TGSI_EXEC_TEMP_THREE_I
445 #define TEMP_3_C TGSI_EXEC_TEMP_THREE_C
446 #define TEMP_HALF_I TGSI_EXEC_TEMP_HALF_I
447 #define TEMP_HALF_C TGSI_EXEC_TEMP_HALF_C
448 #define TEMP_R0 TGSI_EXEC_TEMP_R0
449 #define TEMP_P0 TGSI_EXEC_TEMP_P0
450
451 #define IS_CHANNEL_ENABLED(INST, CHAN)\
452 ((INST).Dst[0].Register.WriteMask & (1 << (CHAN)))
453
454 #define IS_CHANNEL_ENABLED2(INST, CHAN)\
455 ((INST).Dst[1].Register.WriteMask & (1 << (CHAN)))
456
457 #define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
458 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
459 if (IS_CHANNEL_ENABLED( INST, CHAN ))
460
461 #define FOR_EACH_ENABLED_CHANNEL2(INST, CHAN)\
462 for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
463 if (IS_CHANNEL_ENABLED2( INST, CHAN ))
464
465
466 /** The execution mask depends on the conditional mask and the loop mask */
467 #define UPDATE_EXEC_MASK(MACH) \
468 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
469
470
471 static const union tgsi_exec_channel ZeroVec =
472 { { 0.0, 0.0, 0.0, 0.0 } };
473
474 static const union tgsi_exec_channel OneVec = {
475 {1.0f, 1.0f, 1.0f, 1.0f}
476 };
477
478
479 /**
480 * Assert that none of the float values in 'chan' are infinite or NaN.
481 * NaN and Inf may occur normally during program execution and should
482 * not lead to crashes, etc. But when debugging, it's helpful to catch
483 * them.
484 */
485 static INLINE void
486 check_inf_or_nan(const union tgsi_exec_channel *chan)
487 {
488 assert(!util_is_inf_or_nan((chan)->f[0]));
489 assert(!util_is_inf_or_nan((chan)->f[1]));
490 assert(!util_is_inf_or_nan((chan)->f[2]));
491 assert(!util_is_inf_or_nan((chan)->f[3]));
492 }
493
494
495 #ifdef DEBUG
496 static void
497 print_chan(const char *msg, const union tgsi_exec_channel *chan)
498 {
499 debug_printf("%s = {%f, %f, %f, %f}\n",
500 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
501 }
502 #endif
503
504
505 #ifdef DEBUG
506 static void
507 print_temp(const struct tgsi_exec_machine *mach, uint index)
508 {
509 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
510 int i;
511 debug_printf("Temp[%u] =\n", index);
512 for (i = 0; i < 4; i++) {
513 debug_printf(" %c: { %f, %f, %f, %f }\n",
514 "XYZW"[i],
515 tmp->xyzw[i].f[0],
516 tmp->xyzw[i].f[1],
517 tmp->xyzw[i].f[2],
518 tmp->xyzw[i].f[3]);
519 }
520 }
521 #endif
522
523
524 /**
525 * Check if there's a potential src/dst register data dependency when
526 * using SOA execution.
527 * Example:
528 * MOV T, T.yxwz;
529 * This would expand into:
530 * MOV t0, t1;
531 * MOV t1, t0;
532 * MOV t2, t3;
533 * MOV t3, t2;
534 * The second instruction will have the wrong value for t0 if executed as-is.
535 */
536 boolean
537 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
538 {
539 uint i, chan;
540
541 uint writemask = inst->Dst[0].Register.WriteMask;
542 if (writemask == TGSI_WRITEMASK_X ||
543 writemask == TGSI_WRITEMASK_Y ||
544 writemask == TGSI_WRITEMASK_Z ||
545 writemask == TGSI_WRITEMASK_W ||
546 writemask == TGSI_WRITEMASK_NONE) {
547 /* no chance of data dependency */
548 return FALSE;
549 }
550
551 /* loop over src regs */
552 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
553 if ((inst->Src[i].Register.File ==
554 inst->Dst[0].Register.File) &&
555 (inst->Src[i].Register.Index ==
556 inst->Dst[0].Register.Index)) {
557 /* loop over dest channels */
558 uint channelsWritten = 0x0;
559 FOR_EACH_ENABLED_CHANNEL(*inst, chan) {
560 /* check if we're reading a channel that's been written */
561 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
562 if (channelsWritten & (1 << swizzle)) {
563 return TRUE;
564 }
565
566 channelsWritten |= (1 << chan);
567 }
568 }
569 }
570 return FALSE;
571 }
572
573
574 /**
575 * Initialize machine state by expanding tokens to full instructions,
576 * allocating temporary storage, setting up constants, etc.
577 * After this, we can call tgsi_exec_machine_run() many times.
578 */
579 void
580 tgsi_exec_machine_bind_shader(
581 struct tgsi_exec_machine *mach,
582 const struct tgsi_token *tokens,
583 uint numSamplers,
584 struct tgsi_sampler **samplers)
585 {
586 uint k;
587 struct tgsi_parse_context parse;
588 struct tgsi_exec_labels *labels = &mach->Labels;
589 struct tgsi_full_instruction *instructions;
590 struct tgsi_full_declaration *declarations;
591 uint maxInstructions = 10, numInstructions = 0;
592 uint maxDeclarations = 10, numDeclarations = 0;
593 uint instno = 0;
594
595 #if 0
596 tgsi_dump(tokens, 0);
597 #endif
598
599 util_init_math();
600
601 mach->Tokens = tokens;
602 mach->Samplers = samplers;
603
604 k = tgsi_parse_init (&parse, mach->Tokens);
605 if (k != TGSI_PARSE_OK) {
606 debug_printf( "Problem parsing!\n" );
607 return;
608 }
609
610 mach->Processor = parse.FullHeader.Processor.Processor;
611 mach->ImmLimit = 0;
612 labels->count = 0;
613
614 declarations = (struct tgsi_full_declaration *)
615 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
616
617 if (!declarations) {
618 return;
619 }
620
621 instructions = (struct tgsi_full_instruction *)
622 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
623
624 if (!instructions) {
625 FREE( declarations );
626 return;
627 }
628
629 while( !tgsi_parse_end_of_tokens( &parse ) ) {
630 uint pointer = parse.Position;
631 uint i;
632
633 tgsi_parse_token( &parse );
634 switch( parse.FullToken.Token.Type ) {
635 case TGSI_TOKEN_TYPE_DECLARATION:
636 /* save expanded declaration */
637 if (numDeclarations == maxDeclarations) {
638 declarations = REALLOC(declarations,
639 maxDeclarations
640 * sizeof(struct tgsi_full_declaration),
641 (maxDeclarations + 10)
642 * sizeof(struct tgsi_full_declaration));
643 maxDeclarations += 10;
644 }
645 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
646 unsigned reg;
647 for (reg = parse.FullToken.FullDeclaration.Range.First;
648 reg <= parse.FullToken.FullDeclaration.Range.Last;
649 ++reg) {
650 ++mach->NumOutputs;
651 }
652 }
653 memcpy(declarations + numDeclarations,
654 &parse.FullToken.FullDeclaration,
655 sizeof(declarations[0]));
656 numDeclarations++;
657 break;
658
659 case TGSI_TOKEN_TYPE_IMMEDIATE:
660 {
661 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
662 assert( size <= 4 );
663 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
664
665 for( i = 0; i < size; i++ ) {
666 mach->Imms[mach->ImmLimit][i] =
667 parse.FullToken.FullImmediate.u[i].Float;
668 }
669 mach->ImmLimit += 1;
670 }
671 break;
672
673 case TGSI_TOKEN_TYPE_INSTRUCTION:
674 assert( labels->count < MAX_LABELS );
675
676 labels->labels[labels->count][0] = instno;
677 labels->labels[labels->count][1] = pointer;
678 labels->count++;
679
680 /* save expanded instruction */
681 if (numInstructions == maxInstructions) {
682 instructions = REALLOC(instructions,
683 maxInstructions
684 * sizeof(struct tgsi_full_instruction),
685 (maxInstructions + 10)
686 * sizeof(struct tgsi_full_instruction));
687 maxInstructions += 10;
688 }
689
690 memcpy(instructions + numInstructions,
691 &parse.FullToken.FullInstruction,
692 sizeof(instructions[0]));
693
694 numInstructions++;
695 break;
696
697 case TGSI_TOKEN_TYPE_PROPERTY:
698 break;
699
700 default:
701 assert( 0 );
702 }
703 }
704 tgsi_parse_free (&parse);
705
706 if (mach->Declarations) {
707 FREE( mach->Declarations );
708 }
709 mach->Declarations = declarations;
710 mach->NumDeclarations = numDeclarations;
711
712 if (mach->Instructions) {
713 FREE( mach->Instructions );
714 }
715 mach->Instructions = instructions;
716 mach->NumInstructions = numInstructions;
717 }
718
719
720 struct tgsi_exec_machine *
721 tgsi_exec_machine_create( void )
722 {
723 struct tgsi_exec_machine *mach;
724 uint i;
725
726 mach = align_malloc( sizeof *mach, 16 );
727 if (!mach)
728 goto fail;
729
730 memset(mach, 0, sizeof(*mach));
731
732 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
733 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
734 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
735
736 /* Setup constants. */
737 for( i = 0; i < 4; i++ ) {
738 mach->Temps[TEMP_0_I].xyzw[TEMP_0_C].u[i] = 0x00000000;
739 mach->Temps[TEMP_7F_I].xyzw[TEMP_7F_C].u[i] = 0x7FFFFFFF;
740 mach->Temps[TEMP_80_I].xyzw[TEMP_80_C].u[i] = 0x80000000;
741 mach->Temps[TEMP_FF_I].xyzw[TEMP_FF_C].u[i] = 0xFFFFFFFF;
742 mach->Temps[TEMP_1_I].xyzw[TEMP_1_C].f[i] = 1.0f;
743 mach->Temps[TEMP_2_I].xyzw[TEMP_2_C].f[i] = 2.0f;
744 mach->Temps[TEMP_128_I].xyzw[TEMP_128_C].f[i] = 128.0f;
745 mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C].f[i] = -128.0f;
746 mach->Temps[TEMP_3_I].xyzw[TEMP_3_C].f[i] = 3.0f;
747 mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C].f[i] = 0.5f;
748 }
749
750 #ifdef DEBUG
751 /* silence warnings */
752 (void) print_chan;
753 (void) print_temp;
754 #endif
755
756 return mach;
757
758 fail:
759 align_free(mach);
760 return NULL;
761 }
762
763
764 void
765 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
766 {
767 if (mach) {
768 FREE(mach->Instructions);
769 FREE(mach->Declarations);
770 }
771
772 align_free(mach);
773 }
774
775 static void
776 micro_add(union tgsi_exec_channel *dst,
777 const union tgsi_exec_channel *src0,
778 const union tgsi_exec_channel *src1)
779 {
780 dst->f[0] = src0->f[0] + src1->f[0];
781 dst->f[1] = src0->f[1] + src1->f[1];
782 dst->f[2] = src0->f[2] + src1->f[2];
783 dst->f[3] = src0->f[3] + src1->f[3];
784 }
785
786 static void
787 micro_div(
788 union tgsi_exec_channel *dst,
789 const union tgsi_exec_channel *src0,
790 const union tgsi_exec_channel *src1 )
791 {
792 if (src1->f[0] != 0) {
793 dst->f[0] = src0->f[0] / src1->f[0];
794 }
795 if (src1->f[1] != 0) {
796 dst->f[1] = src0->f[1] / src1->f[1];
797 }
798 if (src1->f[2] != 0) {
799 dst->f[2] = src0->f[2] / src1->f[2];
800 }
801 if (src1->f[3] != 0) {
802 dst->f[3] = src0->f[3] / src1->f[3];
803 }
804 }
805
806 static void
807 micro_float_clamp(union tgsi_exec_channel *dst,
808 const union tgsi_exec_channel *src)
809 {
810 uint i;
811
812 for (i = 0; i < 4; i++) {
813 if (src->f[i] > 0.0f) {
814 if (src->f[i] > 1.884467e+019f)
815 dst->f[i] = 1.884467e+019f;
816 else if (src->f[i] < 5.42101e-020f)
817 dst->f[i] = 5.42101e-020f;
818 else
819 dst->f[i] = src->f[i];
820 }
821 else {
822 if (src->f[i] < -1.884467e+019f)
823 dst->f[i] = -1.884467e+019f;
824 else if (src->f[i] > -5.42101e-020f)
825 dst->f[i] = -5.42101e-020f;
826 else
827 dst->f[i] = src->f[i];
828 }
829 }
830 }
831
832 static void
833 micro_lt(
834 union tgsi_exec_channel *dst,
835 const union tgsi_exec_channel *src0,
836 const union tgsi_exec_channel *src1,
837 const union tgsi_exec_channel *src2,
838 const union tgsi_exec_channel *src3 )
839 {
840 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
841 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
842 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
843 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
844 }
845
846 static void
847 micro_max(union tgsi_exec_channel *dst,
848 const union tgsi_exec_channel *src0,
849 const union tgsi_exec_channel *src1)
850 {
851 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
852 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
853 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
854 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
855 }
856
857 static void
858 micro_min(union tgsi_exec_channel *dst,
859 const union tgsi_exec_channel *src0,
860 const union tgsi_exec_channel *src1)
861 {
862 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
863 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
864 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
865 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
866 }
867
868 static void
869 micro_mul(union tgsi_exec_channel *dst,
870 const union tgsi_exec_channel *src0,
871 const union tgsi_exec_channel *src1)
872 {
873 dst->f[0] = src0->f[0] * src1->f[0];
874 dst->f[1] = src0->f[1] * src1->f[1];
875 dst->f[2] = src0->f[2] * src1->f[2];
876 dst->f[3] = src0->f[3] * src1->f[3];
877 }
878
879 #if 0
880 static void
881 micro_imul64(
882 union tgsi_exec_channel *dst0,
883 union tgsi_exec_channel *dst1,
884 const union tgsi_exec_channel *src0,
885 const union tgsi_exec_channel *src1 )
886 {
887 dst1->i[0] = src0->i[0] * src1->i[0];
888 dst1->i[1] = src0->i[1] * src1->i[1];
889 dst1->i[2] = src0->i[2] * src1->i[2];
890 dst1->i[3] = src0->i[3] * src1->i[3];
891 dst0->i[0] = 0;
892 dst0->i[1] = 0;
893 dst0->i[2] = 0;
894 dst0->i[3] = 0;
895 }
896 #endif
897
898 #if 0
899 static void
900 micro_umul64(
901 union tgsi_exec_channel *dst0,
902 union tgsi_exec_channel *dst1,
903 const union tgsi_exec_channel *src0,
904 const union tgsi_exec_channel *src1 )
905 {
906 dst1->u[0] = src0->u[0] * src1->u[0];
907 dst1->u[1] = src0->u[1] * src1->u[1];
908 dst1->u[2] = src0->u[2] * src1->u[2];
909 dst1->u[3] = src0->u[3] * src1->u[3];
910 dst0->u[0] = 0;
911 dst0->u[1] = 0;
912 dst0->u[2] = 0;
913 dst0->u[3] = 0;
914 }
915 #endif
916
917
918 #if 0
919 static void
920 micro_movc(
921 union tgsi_exec_channel *dst,
922 const union tgsi_exec_channel *src0,
923 const union tgsi_exec_channel *src1,
924 const union tgsi_exec_channel *src2 )
925 {
926 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
927 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
928 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
929 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
930 }
931 #endif
932
933 static void
934 micro_neg(
935 union tgsi_exec_channel *dst,
936 const union tgsi_exec_channel *src )
937 {
938 dst->f[0] = -src->f[0];
939 dst->f[1] = -src->f[1];
940 dst->f[2] = -src->f[2];
941 dst->f[3] = -src->f[3];
942 }
943
944 static void
945 micro_pow(
946 union tgsi_exec_channel *dst,
947 const union tgsi_exec_channel *src0,
948 const union tgsi_exec_channel *src1 )
949 {
950 #if FAST_MATH
951 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
952 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
953 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
954 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
955 #else
956 dst->f[0] = powf( src0->f[0], src1->f[0] );
957 dst->f[1] = powf( src0->f[1], src1->f[1] );
958 dst->f[2] = powf( src0->f[2], src1->f[2] );
959 dst->f[3] = powf( src0->f[3], src1->f[3] );
960 #endif
961 }
962
963 static void
964 micro_sub(union tgsi_exec_channel *dst,
965 const union tgsi_exec_channel *src0,
966 const union tgsi_exec_channel *src1)
967 {
968 dst->f[0] = src0->f[0] - src1->f[0];
969 dst->f[1] = src0->f[1] - src1->f[1];
970 dst->f[2] = src0->f[2] - src1->f[2];
971 dst->f[3] = src0->f[3] - src1->f[3];
972 }
973
974 static void
975 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
976 const uint file,
977 const uint swizzle,
978 const union tgsi_exec_channel *index,
979 const union tgsi_exec_channel *index2D,
980 union tgsi_exec_channel *chan)
981 {
982 uint i;
983
984 switch (file) {
985 case TGSI_FILE_CONSTANT:
986 for (i = 0; i < QUAD_SIZE; i++) {
987 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
988 assert(mach->Consts[index2D->i[i]]);
989
990 if (index->i[i] < 0) {
991 chan->u[i] = 0;
992 } else {
993 const uint *p = (const uint *)mach->Consts[index2D->i[i]];
994
995 chan->u[i] = p[index->i[i] * 4 + swizzle];
996 }
997 }
998 break;
999
1000 case TGSI_FILE_INPUT:
1001 case TGSI_FILE_SYSTEM_VALUE:
1002 for (i = 0; i < QUAD_SIZE; i++) {
1003 /* XXX: 2D indexing */
1004 chan->u[i] = mach->Inputs[index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i]].xyzw[swizzle].u[i];
1005 }
1006 break;
1007
1008 case TGSI_FILE_TEMPORARY:
1009 for (i = 0; i < QUAD_SIZE; i++) {
1010 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1011 assert(index2D->i[i] == 0);
1012
1013 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1014 }
1015 break;
1016
1017 case TGSI_FILE_IMMEDIATE:
1018 for (i = 0; i < QUAD_SIZE; i++) {
1019 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1020 assert(index2D->i[i] == 0);
1021
1022 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1023 }
1024 break;
1025
1026 case TGSI_FILE_ADDRESS:
1027 for (i = 0; i < QUAD_SIZE; i++) {
1028 assert(index->i[i] >= 0);
1029 assert(index2D->i[i] == 0);
1030
1031 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1032 }
1033 break;
1034
1035 case TGSI_FILE_PREDICATE:
1036 for (i = 0; i < QUAD_SIZE; i++) {
1037 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1038 assert(index2D->i[i] == 0);
1039
1040 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1041 }
1042 break;
1043
1044 case TGSI_FILE_OUTPUT:
1045 /* vertex/fragment output vars can be read too */
1046 for (i = 0; i < QUAD_SIZE; i++) {
1047 assert(index->i[i] >= 0);
1048 assert(index2D->i[i] == 0);
1049
1050 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1051 }
1052 break;
1053
1054 default:
1055 assert(0);
1056 for (i = 0; i < QUAD_SIZE; i++) {
1057 chan->u[i] = 0;
1058 }
1059 }
1060 }
1061
1062 static void
1063 fetch_source(const struct tgsi_exec_machine *mach,
1064 union tgsi_exec_channel *chan,
1065 const struct tgsi_full_src_register *reg,
1066 const uint chan_index,
1067 enum tgsi_exec_datatype src_datatype)
1068 {
1069 union tgsi_exec_channel index;
1070 union tgsi_exec_channel index2D;
1071 uint swizzle;
1072
1073 /* We start with a direct index into a register file.
1074 *
1075 * file[1],
1076 * where:
1077 * file = Register.File
1078 * [1] = Register.Index
1079 */
1080 index.i[0] =
1081 index.i[1] =
1082 index.i[2] =
1083 index.i[3] = reg->Register.Index;
1084
1085 /* There is an extra source register that indirectly subscripts
1086 * a register file. The direct index now becomes an offset
1087 * that is being added to the indirect register.
1088 *
1089 * file[ind[2].x+1],
1090 * where:
1091 * ind = Indirect.File
1092 * [2] = Indirect.Index
1093 * .x = Indirect.SwizzleX
1094 */
1095 if (reg->Register.Indirect) {
1096 union tgsi_exec_channel index2;
1097 union tgsi_exec_channel indir_index;
1098 const uint execmask = mach->ExecMask;
1099 uint i;
1100
1101 /* which address register (always zero now) */
1102 index2.i[0] =
1103 index2.i[1] =
1104 index2.i[2] =
1105 index2.i[3] = reg->Indirect.Index;
1106
1107 /* get current value of address register[swizzle] */
1108 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1109 fetch_src_file_channel(mach,
1110 reg->Indirect.File,
1111 swizzle,
1112 &index2,
1113 &ZeroVec,
1114 &indir_index);
1115
1116 /* add value of address register to the offset */
1117 index.i[0] += indir_index.i[0];
1118 index.i[1] += indir_index.i[1];
1119 index.i[2] += indir_index.i[2];
1120 index.i[3] += indir_index.i[3];
1121
1122 /* for disabled execution channels, zero-out the index to
1123 * avoid using a potential garbage value.
1124 */
1125 for (i = 0; i < QUAD_SIZE; i++) {
1126 if ((execmask & (1 << i)) == 0)
1127 index.i[i] = 0;
1128 }
1129 }
1130
1131 /* There is an extra source register that is a second
1132 * subscript to a register file. Effectively it means that
1133 * the register file is actually a 2D array of registers.
1134 *
1135 * file[3][1],
1136 * where:
1137 * [3] = Dimension.Index
1138 */
1139 if (reg->Register.Dimension) {
1140 index2D.i[0] =
1141 index2D.i[1] =
1142 index2D.i[2] =
1143 index2D.i[3] = reg->Dimension.Index;
1144
1145 /* Again, the second subscript index can be addressed indirectly
1146 * identically to the first one.
1147 * Nothing stops us from indirectly addressing the indirect register,
1148 * but there is no need for that, so we won't exercise it.
1149 *
1150 * file[ind[4].y+3][1],
1151 * where:
1152 * ind = DimIndirect.File
1153 * [4] = DimIndirect.Index
1154 * .y = DimIndirect.SwizzleX
1155 */
1156 if (reg->Dimension.Indirect) {
1157 union tgsi_exec_channel index2;
1158 union tgsi_exec_channel indir_index;
1159 const uint execmask = mach->ExecMask;
1160 uint i;
1161
1162 index2.i[0] =
1163 index2.i[1] =
1164 index2.i[2] =
1165 index2.i[3] = reg->DimIndirect.Index;
1166
1167 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, CHAN_X );
1168 fetch_src_file_channel(mach,
1169 reg->DimIndirect.File,
1170 swizzle,
1171 &index2,
1172 &ZeroVec,
1173 &indir_index);
1174
1175 index2D.i[0] += indir_index.i[0];
1176 index2D.i[1] += indir_index.i[1];
1177 index2D.i[2] += indir_index.i[2];
1178 index2D.i[3] += indir_index.i[3];
1179
1180 /* for disabled execution channels, zero-out the index to
1181 * avoid using a potential garbage value.
1182 */
1183 for (i = 0; i < QUAD_SIZE; i++) {
1184 if ((execmask & (1 << i)) == 0) {
1185 index2D.i[i] = 0;
1186 }
1187 }
1188 }
1189
1190 /* If by any chance there was a need for a 3D array of register
1191 * files, we would have to check whether Dimension is followed
1192 * by a dimension register and continue the saga.
1193 */
1194 } else {
1195 index2D.i[0] =
1196 index2D.i[1] =
1197 index2D.i[2] =
1198 index2D.i[3] = 0;
1199 }
1200
1201 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1202 fetch_src_file_channel(mach,
1203 reg->Register.File,
1204 swizzle,
1205 &index,
1206 &index2D,
1207 chan);
1208
1209 if (reg->Register.Absolute) {
1210 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1211 micro_abs(chan, chan);
1212 } else {
1213 micro_iabs(chan, chan);
1214 }
1215 }
1216
1217 if (reg->Register.Negate) {
1218 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1219 micro_neg(chan, chan);
1220 } else {
1221 micro_ineg(chan, chan);
1222 }
1223 }
1224 }
1225
1226 static void
1227 store_dest(struct tgsi_exec_machine *mach,
1228 const union tgsi_exec_channel *chan,
1229 const struct tgsi_full_dst_register *reg,
1230 const struct tgsi_full_instruction *inst,
1231 uint chan_index,
1232 enum tgsi_exec_datatype dst_datatype)
1233 {
1234 uint i;
1235 union tgsi_exec_channel null;
1236 union tgsi_exec_channel *dst;
1237 uint execmask = mach->ExecMask;
1238 int offset = 0; /* indirection offset */
1239 int index;
1240
1241 /* for debugging */
1242 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1243 check_inf_or_nan(chan);
1244 }
1245
1246 /* There is an extra source register that indirectly subscripts
1247 * a register file. The direct index now becomes an offset
1248 * that is being added to the indirect register.
1249 *
1250 * file[ind[2].x+1],
1251 * where:
1252 * ind = Indirect.File
1253 * [2] = Indirect.Index
1254 * .x = Indirect.SwizzleX
1255 */
1256 if (reg->Register.Indirect) {
1257 union tgsi_exec_channel index;
1258 union tgsi_exec_channel indir_index;
1259 uint swizzle;
1260
1261 /* which address register (always zero for now) */
1262 index.i[0] =
1263 index.i[1] =
1264 index.i[2] =
1265 index.i[3] = reg->Indirect.Index;
1266
1267 /* get current value of address register[swizzle] */
1268 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, CHAN_X );
1269
1270 /* fetch values from the address/indirection register */
1271 fetch_src_file_channel(mach,
1272 reg->Indirect.File,
1273 swizzle,
1274 &index,
1275 &ZeroVec,
1276 &indir_index);
1277
1278 /* save indirection offset */
1279 offset = indir_index.i[0];
1280 }
1281
1282 switch (reg->Register.File) {
1283 case TGSI_FILE_NULL:
1284 dst = &null;
1285 break;
1286
1287 case TGSI_FILE_OUTPUT:
1288 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1289 + reg->Register.Index;
1290 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1291 #if 0
1292 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1293 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1294 for (i = 0; i < QUAD_SIZE; i++)
1295 if (execmask & (1 << i))
1296 fprintf(stderr, "%f, ", chan->f[i]);
1297 fprintf(stderr, ")\n");
1298 }
1299 #endif
1300 break;
1301
1302 case TGSI_FILE_TEMPORARY:
1303 index = reg->Register.Index;
1304 assert( index < TGSI_EXEC_NUM_TEMPS );
1305 dst = &mach->Temps[offset + index].xyzw[chan_index];
1306 break;
1307
1308 case TGSI_FILE_ADDRESS:
1309 index = reg->Register.Index;
1310 dst = &mach->Addrs[index].xyzw[chan_index];
1311 break;
1312
1313 case TGSI_FILE_LOOP:
1314 assert(reg->Register.Index == 0);
1315 assert(mach->LoopCounterStackTop > 0);
1316 assert(chan_index == CHAN_X);
1317 dst = &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[chan_index];
1318 break;
1319
1320 case TGSI_FILE_PREDICATE:
1321 index = reg->Register.Index;
1322 assert(index < TGSI_EXEC_NUM_PREDS);
1323 dst = &mach->Predicates[index].xyzw[chan_index];
1324 break;
1325
1326 default:
1327 assert( 0 );
1328 return;
1329 }
1330
1331 if (inst->Instruction.Predicate) {
1332 uint swizzle;
1333 union tgsi_exec_channel *pred;
1334
1335 switch (chan_index) {
1336 case CHAN_X:
1337 swizzle = inst->Predicate.SwizzleX;
1338 break;
1339 case CHAN_Y:
1340 swizzle = inst->Predicate.SwizzleY;
1341 break;
1342 case CHAN_Z:
1343 swizzle = inst->Predicate.SwizzleZ;
1344 break;
1345 case CHAN_W:
1346 swizzle = inst->Predicate.SwizzleW;
1347 break;
1348 default:
1349 assert(0);
1350 return;
1351 }
1352
1353 assert(inst->Predicate.Index == 0);
1354
1355 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1356
1357 if (inst->Predicate.Negate) {
1358 for (i = 0; i < QUAD_SIZE; i++) {
1359 if (pred->u[i]) {
1360 execmask &= ~(1 << i);
1361 }
1362 }
1363 } else {
1364 for (i = 0; i < QUAD_SIZE; i++) {
1365 if (!pred->u[i]) {
1366 execmask &= ~(1 << i);
1367 }
1368 }
1369 }
1370 }
1371
1372 switch (inst->Instruction.Saturate) {
1373 case TGSI_SAT_NONE:
1374 for (i = 0; i < QUAD_SIZE; i++)
1375 if (execmask & (1 << i))
1376 dst->i[i] = chan->i[i];
1377 break;
1378
1379 case TGSI_SAT_ZERO_ONE:
1380 for (i = 0; i < QUAD_SIZE; i++)
1381 if (execmask & (1 << i)) {
1382 if (chan->f[i] < 0.0f)
1383 dst->f[i] = 0.0f;
1384 else if (chan->f[i] > 1.0f)
1385 dst->f[i] = 1.0f;
1386 else
1387 dst->i[i] = chan->i[i];
1388 }
1389 break;
1390
1391 case TGSI_SAT_MINUS_PLUS_ONE:
1392 for (i = 0; i < QUAD_SIZE; i++)
1393 if (execmask & (1 << i)) {
1394 if (chan->f[i] < -1.0f)
1395 dst->f[i] = -1.0f;
1396 else if (chan->f[i] > 1.0f)
1397 dst->f[i] = 1.0f;
1398 else
1399 dst->i[i] = chan->i[i];
1400 }
1401 break;
1402
1403 default:
1404 assert( 0 );
1405 }
1406 }
1407
1408 #define FETCH(VAL,INDEX,CHAN)\
1409 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1410
1411 #define STORE(VAL,INDEX,CHAN)\
1412 store_dest(mach, VAL, &inst->Dst[INDEX], inst, CHAN, TGSI_EXEC_DATA_FLOAT)
1413
1414
1415 /**
1416 * Execute ARB-style KIL which is predicated by a src register.
1417 * Kill fragment if any of the four values is less than zero.
1418 */
1419 static void
1420 exec_kil(struct tgsi_exec_machine *mach,
1421 const struct tgsi_full_instruction *inst)
1422 {
1423 uint uniquemask;
1424 uint chan_index;
1425 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1426 union tgsi_exec_channel r[1];
1427
1428 /* This mask stores component bits that were already tested. */
1429 uniquemask = 0;
1430
1431 for (chan_index = 0; chan_index < 4; chan_index++)
1432 {
1433 uint swizzle;
1434 uint i;
1435
1436 /* unswizzle channel */
1437 swizzle = tgsi_util_get_full_src_register_swizzle (
1438 &inst->Src[0],
1439 chan_index);
1440
1441 /* check if the component has not been already tested */
1442 if (uniquemask & (1 << swizzle))
1443 continue;
1444 uniquemask |= 1 << swizzle;
1445
1446 FETCH(&r[0], 0, chan_index);
1447 for (i = 0; i < 4; i++)
1448 if (r[0].f[i] < 0.0f)
1449 kilmask |= 1 << i;
1450 }
1451
1452 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1453 }
1454
1455 /**
1456 * Execute NVIDIA-style KIL which is predicated by a condition code.
1457 * Kill fragment if the condition code is TRUE.
1458 */
1459 static void
1460 exec_kilp(struct tgsi_exec_machine *mach,
1461 const struct tgsi_full_instruction *inst)
1462 {
1463 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1464
1465 /* "unconditional" kil */
1466 kilmask = mach->ExecMask;
1467 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1468 }
1469
1470 static void
1471 emit_vertex(struct tgsi_exec_machine *mach)
1472 {
1473 /* FIXME: check for exec mask correctly
1474 unsigned i;
1475 for (i = 0; i < QUAD_SIZE; ++i) {
1476 if ((mach->ExecMask & (1 << i)))
1477 */
1478 if (mach->ExecMask) {
1479 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1480 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1481 }
1482 }
1483
1484 static void
1485 emit_primitive(struct tgsi_exec_machine *mach)
1486 {
1487 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1488 /* FIXME: check for exec mask correctly
1489 unsigned i;
1490 for (i = 0; i < QUAD_SIZE; ++i) {
1491 if ((mach->ExecMask & (1 << i)))
1492 */
1493 if (mach->ExecMask) {
1494 ++(*prim_count);
1495 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1496 mach->Primitives[*prim_count] = 0;
1497 }
1498 }
1499
1500 /*
1501 * Fetch four texture samples using STR texture coordinates.
1502 */
1503 static void
1504 fetch_texel( struct tgsi_sampler *sampler,
1505 const union tgsi_exec_channel *s,
1506 const union tgsi_exec_channel *t,
1507 const union tgsi_exec_channel *p,
1508 const union tgsi_exec_channel *c0,
1509 enum tgsi_sampler_control control,
1510 union tgsi_exec_channel *r,
1511 union tgsi_exec_channel *g,
1512 union tgsi_exec_channel *b,
1513 union tgsi_exec_channel *a )
1514 {
1515 uint j;
1516 float rgba[NUM_CHANNELS][QUAD_SIZE];
1517
1518 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, control, rgba);
1519
1520 for (j = 0; j < 4; j++) {
1521 r->f[j] = rgba[0][j];
1522 g->f[j] = rgba[1][j];
1523 b->f[j] = rgba[2][j];
1524 a->f[j] = rgba[3][j];
1525 }
1526 }
1527
1528
1529 #define TEX_MODIFIER_NONE 0
1530 #define TEX_MODIFIER_PROJECTED 1
1531 #define TEX_MODIFIER_LOD_BIAS 2
1532 #define TEX_MODIFIER_EXPLICIT_LOD 3
1533
1534
1535 static void
1536 exec_tex(struct tgsi_exec_machine *mach,
1537 const struct tgsi_full_instruction *inst,
1538 uint modifier)
1539 {
1540 const uint unit = inst->Src[1].Register.Index;
1541 union tgsi_exec_channel r[4];
1542 const union tgsi_exec_channel *lod = &ZeroVec;
1543 enum tgsi_sampler_control control;
1544 uint chan_index;
1545
1546 if (modifier != TEX_MODIFIER_NONE) {
1547 FETCH(&r[3], 0, CHAN_W);
1548 if (modifier != TEX_MODIFIER_PROJECTED) {
1549 lod = &r[3];
1550 }
1551 }
1552
1553 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1554 control = tgsi_sampler_lod_explicit;
1555 } else {
1556 control = tgsi_sampler_lod_bias;
1557 }
1558
1559 switch (inst->Texture.Texture) {
1560 case TGSI_TEXTURE_1D:
1561 case TGSI_TEXTURE_SHADOW1D:
1562 FETCH(&r[0], 0, CHAN_X);
1563
1564 if (modifier == TEX_MODIFIER_PROJECTED) {
1565 micro_div(&r[0], &r[0], &r[3]);
1566 }
1567
1568 fetch_texel(mach->Samplers[unit],
1569 &r[0], &ZeroVec, &ZeroVec, lod, /* S, T, P, LOD */
1570 control,
1571 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1572 break;
1573
1574 case TGSI_TEXTURE_2D:
1575 case TGSI_TEXTURE_RECT:
1576 case TGSI_TEXTURE_SHADOW2D:
1577 case TGSI_TEXTURE_SHADOWRECT:
1578 FETCH(&r[0], 0, CHAN_X);
1579 FETCH(&r[1], 0, CHAN_Y);
1580 FETCH(&r[2], 0, CHAN_Z);
1581
1582 if (modifier == TEX_MODIFIER_PROJECTED) {
1583 micro_div(&r[0], &r[0], &r[3]);
1584 micro_div(&r[1], &r[1], &r[3]);
1585 micro_div(&r[2], &r[2], &r[3]);
1586 }
1587
1588 fetch_texel(mach->Samplers[unit],
1589 &r[0], &r[1], &r[2], lod, /* S, T, P, LOD */
1590 control,
1591 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1592 break;
1593
1594 case TGSI_TEXTURE_3D:
1595 case TGSI_TEXTURE_CUBE:
1596 FETCH(&r[0], 0, CHAN_X);
1597 FETCH(&r[1], 0, CHAN_Y);
1598 FETCH(&r[2], 0, CHAN_Z);
1599
1600 if (modifier == TEX_MODIFIER_PROJECTED) {
1601 micro_div(&r[0], &r[0], &r[3]);
1602 micro_div(&r[1], &r[1], &r[3]);
1603 micro_div(&r[2], &r[2], &r[3]);
1604 }
1605
1606 fetch_texel(mach->Samplers[unit],
1607 &r[0], &r[1], &r[2], lod,
1608 control,
1609 &r[0], &r[1], &r[2], &r[3]);
1610 break;
1611
1612 default:
1613 assert(0);
1614 }
1615
1616 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
1617 STORE(&r[chan_index], 0, chan_index);
1618 }
1619 }
1620
1621 static void
1622 exec_txd(struct tgsi_exec_machine *mach,
1623 const struct tgsi_full_instruction *inst)
1624 {
1625 const uint unit = inst->Src[3].Register.Index;
1626 union tgsi_exec_channel r[4];
1627 uint chan_index;
1628
1629 /*
1630 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1631 */
1632
1633 switch (inst->Texture.Texture) {
1634 case TGSI_TEXTURE_1D:
1635 case TGSI_TEXTURE_SHADOW1D:
1636
1637 FETCH(&r[0], 0, CHAN_X);
1638
1639 fetch_texel(mach->Samplers[unit],
1640 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1641 tgsi_sampler_lod_bias,
1642 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1643 break;
1644
1645 case TGSI_TEXTURE_2D:
1646 case TGSI_TEXTURE_RECT:
1647 case TGSI_TEXTURE_SHADOW2D:
1648 case TGSI_TEXTURE_SHADOWRECT:
1649
1650 FETCH(&r[0], 0, CHAN_X);
1651 FETCH(&r[1], 0, CHAN_Y);
1652 FETCH(&r[2], 0, CHAN_Z);
1653
1654 fetch_texel(mach->Samplers[unit],
1655 &r[0], &r[1], &r[2], &ZeroVec, /* inputs */
1656 tgsi_sampler_lod_bias,
1657 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1658 break;
1659
1660 case TGSI_TEXTURE_3D:
1661 case TGSI_TEXTURE_CUBE:
1662
1663 FETCH(&r[0], 0, CHAN_X);
1664 FETCH(&r[1], 0, CHAN_Y);
1665 FETCH(&r[2], 0, CHAN_Z);
1666
1667 fetch_texel(mach->Samplers[unit],
1668 &r[0], &r[1], &r[2], &ZeroVec,
1669 tgsi_sampler_lod_bias,
1670 &r[0], &r[1], &r[2], &r[3]);
1671 break;
1672
1673 default:
1674 assert(0);
1675 }
1676
1677 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
1678 STORE(&r[chan_index], 0, chan_index);
1679 }
1680 }
1681
1682
1683 /**
1684 * Evaluate a constant-valued coefficient at the position of the
1685 * current quad.
1686 */
1687 static void
1688 eval_constant_coef(
1689 struct tgsi_exec_machine *mach,
1690 unsigned attrib,
1691 unsigned chan )
1692 {
1693 unsigned i;
1694
1695 for( i = 0; i < QUAD_SIZE; i++ ) {
1696 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
1697 }
1698 }
1699
1700 /**
1701 * Evaluate a linear-valued coefficient at the position of the
1702 * current quad.
1703 */
1704 static void
1705 eval_linear_coef(
1706 struct tgsi_exec_machine *mach,
1707 unsigned attrib,
1708 unsigned chan )
1709 {
1710 const float x = mach->QuadPos.xyzw[0].f[0];
1711 const float y = mach->QuadPos.xyzw[1].f[0];
1712 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1713 const float dady = mach->InterpCoefs[attrib].dady[chan];
1714 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1715 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
1716 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
1717 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
1718 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
1719 }
1720
1721 /**
1722 * Evaluate a perspective-valued coefficient at the position of the
1723 * current quad.
1724 */
1725 static void
1726 eval_perspective_coef(
1727 struct tgsi_exec_machine *mach,
1728 unsigned attrib,
1729 unsigned chan )
1730 {
1731 const float x = mach->QuadPos.xyzw[0].f[0];
1732 const float y = mach->QuadPos.xyzw[1].f[0];
1733 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
1734 const float dady = mach->InterpCoefs[attrib].dady[chan];
1735 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
1736 const float *w = mach->QuadPos.xyzw[3].f;
1737 /* divide by W here */
1738 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
1739 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
1740 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
1741 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
1742 }
1743
1744
1745 typedef void (* eval_coef_func)(
1746 struct tgsi_exec_machine *mach,
1747 unsigned attrib,
1748 unsigned chan );
1749
1750 static void
1751 exec_declaration(struct tgsi_exec_machine *mach,
1752 const struct tgsi_full_declaration *decl)
1753 {
1754 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
1755 if (decl->Declaration.File == TGSI_FILE_INPUT ||
1756 decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1757 uint first, last, mask;
1758
1759 first = decl->Range.First;
1760 last = decl->Range.Last;
1761 mask = decl->Declaration.UsageMask;
1762
1763 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1764 uint i;
1765
1766 assert(decl->Semantic.Index == 0);
1767 assert(first == last);
1768
1769 for (i = 0; i < QUAD_SIZE; i++) {
1770 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
1771 }
1772 } else {
1773 eval_coef_func eval;
1774 uint i, j;
1775
1776 switch (decl->Declaration.Interpolate) {
1777 case TGSI_INTERPOLATE_CONSTANT:
1778 eval = eval_constant_coef;
1779 break;
1780
1781 case TGSI_INTERPOLATE_LINEAR:
1782 eval = eval_linear_coef;
1783 break;
1784
1785 case TGSI_INTERPOLATE_PERSPECTIVE:
1786 eval = eval_perspective_coef;
1787 break;
1788
1789 default:
1790 assert(0);
1791 return;
1792 }
1793
1794 for (j = 0; j < NUM_CHANNELS; j++) {
1795 if (mask & (1 << j)) {
1796 for (i = first; i <= last; i++) {
1797 eval(mach, i, j);
1798 }
1799 }
1800 }
1801 }
1802 }
1803 }
1804 }
1805
1806 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
1807 const union tgsi_exec_channel *src);
1808
1809 static void
1810 exec_scalar_unary(struct tgsi_exec_machine *mach,
1811 const struct tgsi_full_instruction *inst,
1812 micro_unary_op op,
1813 enum tgsi_exec_datatype dst_datatype,
1814 enum tgsi_exec_datatype src_datatype)
1815 {
1816 unsigned int chan;
1817 union tgsi_exec_channel src;
1818 union tgsi_exec_channel dst;
1819
1820 fetch_source(mach, &src, &inst->Src[0], CHAN_X, src_datatype);
1821 op(&dst, &src);
1822 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1823 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1824 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
1825 }
1826 }
1827 }
1828
1829 static void
1830 exec_vector_unary(struct tgsi_exec_machine *mach,
1831 const struct tgsi_full_instruction *inst,
1832 micro_unary_op op,
1833 enum tgsi_exec_datatype dst_datatype,
1834 enum tgsi_exec_datatype src_datatype)
1835 {
1836 unsigned int chan;
1837 struct tgsi_exec_vector dst;
1838
1839 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1840 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1841 union tgsi_exec_channel src;
1842
1843 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
1844 op(&dst.xyzw[chan], &src);
1845 }
1846 }
1847 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1848 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1849 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
1850 }
1851 }
1852 }
1853
1854 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
1855 const union tgsi_exec_channel *src0,
1856 const union tgsi_exec_channel *src1);
1857
1858 static void
1859 exec_vector_binary(struct tgsi_exec_machine *mach,
1860 const struct tgsi_full_instruction *inst,
1861 micro_binary_op op,
1862 enum tgsi_exec_datatype dst_datatype,
1863 enum tgsi_exec_datatype src_datatype)
1864 {
1865 unsigned int chan;
1866 struct tgsi_exec_vector dst;
1867
1868 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1869 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1870 union tgsi_exec_channel src[2];
1871
1872 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
1873 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
1874 op(&dst.xyzw[chan], &src[0], &src[1]);
1875 }
1876 }
1877 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1878 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1879 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
1880 }
1881 }
1882 }
1883
1884 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
1885 const union tgsi_exec_channel *src0,
1886 const union tgsi_exec_channel *src1,
1887 const union tgsi_exec_channel *src2);
1888
1889 static void
1890 exec_vector_trinary(struct tgsi_exec_machine *mach,
1891 const struct tgsi_full_instruction *inst,
1892 micro_trinary_op op,
1893 enum tgsi_exec_datatype dst_datatype,
1894 enum tgsi_exec_datatype src_datatype)
1895 {
1896 unsigned int chan;
1897 struct tgsi_exec_vector dst;
1898
1899 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1900 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1901 union tgsi_exec_channel src[3];
1902
1903 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
1904 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
1905 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
1906 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
1907 }
1908 }
1909 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1910 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1911 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
1912 }
1913 }
1914 }
1915
1916 static void
1917 exec_dp3(struct tgsi_exec_machine *mach,
1918 const struct tgsi_full_instruction *inst)
1919 {
1920 unsigned int chan;
1921 union tgsi_exec_channel arg[3];
1922
1923 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1924 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1925 micro_mul(&arg[2], &arg[0], &arg[1]);
1926
1927 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
1928 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
1929 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
1930 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
1931 }
1932
1933 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1934 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1935 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1936 }
1937 }
1938 }
1939
1940 static void
1941 exec_dp4(struct tgsi_exec_machine *mach,
1942 const struct tgsi_full_instruction *inst)
1943 {
1944 unsigned int chan;
1945 union tgsi_exec_channel arg[3];
1946
1947 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1948 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1949 micro_mul(&arg[2], &arg[0], &arg[1]);
1950
1951 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
1952 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
1953 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
1954 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
1955 }
1956
1957 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1958 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1959 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1960 }
1961 }
1962 }
1963
1964 static void
1965 exec_dp2a(struct tgsi_exec_machine *mach,
1966 const struct tgsi_full_instruction *inst)
1967 {
1968 unsigned int chan;
1969 union tgsi_exec_channel arg[3];
1970
1971 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1972 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1973 micro_mul(&arg[2], &arg[0], &arg[1]);
1974
1975 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
1976 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
1977 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
1978
1979 fetch_source(mach, &arg[1], &inst->Src[2], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1980 micro_add(&arg[0], &arg[0], &arg[1]);
1981
1982 for (chan = 0; chan < NUM_CHANNELS; chan++) {
1983 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1984 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1985 }
1986 }
1987 }
1988
1989 static void
1990 exec_dph(struct tgsi_exec_machine *mach,
1991 const struct tgsi_full_instruction *inst)
1992 {
1993 unsigned int chan;
1994 union tgsi_exec_channel arg[3];
1995
1996 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1997 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
1998 micro_mul(&arg[2], &arg[0], &arg[1]);
1999
2000 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2001 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2002 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2003
2004 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2005 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2006 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2007
2008 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_W, TGSI_EXEC_DATA_FLOAT);
2009 micro_add(&arg[0], &arg[0], &arg[1]);
2010
2011 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2012 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2013 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2014 }
2015 }
2016 }
2017
2018 static void
2019 exec_dp2(struct tgsi_exec_machine *mach,
2020 const struct tgsi_full_instruction *inst)
2021 {
2022 unsigned int chan;
2023 union tgsi_exec_channel arg[3];
2024
2025 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2026 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2027 micro_mul(&arg[2], &arg[0], &arg[1]);
2028
2029 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2030 fetch_source(mach, &arg[1], &inst->Src[1], CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2031 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2032
2033 for (chan = 0; chan < NUM_CHANNELS; chan++) {
2034 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2035 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2036 }
2037 }
2038 }
2039
2040 static void
2041 exec_nrm4(struct tgsi_exec_machine *mach,
2042 const struct tgsi_full_instruction *inst)
2043 {
2044 unsigned int chan;
2045 union tgsi_exec_channel arg[4];
2046 union tgsi_exec_channel scale;
2047
2048 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2049 micro_mul(&scale, &arg[0], &arg[0]);
2050
2051 for (chan = CHAN_Y; chan <= CHAN_W; chan++) {
2052 union tgsi_exec_channel product;
2053
2054 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2055 micro_mul(&product, &arg[chan], &arg[chan]);
2056 micro_add(&scale, &scale, &product);
2057 }
2058
2059 micro_rsq(&scale, &scale);
2060
2061 for (chan = CHAN_X; chan <= CHAN_W; chan++) {
2062 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2063 micro_mul(&arg[chan], &arg[chan], &scale);
2064 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2065 }
2066 }
2067 }
2068
2069 static void
2070 exec_nrm3(struct tgsi_exec_machine *mach,
2071 const struct tgsi_full_instruction *inst)
2072 {
2073 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2074 unsigned int chan;
2075 union tgsi_exec_channel arg[3];
2076 union tgsi_exec_channel scale;
2077
2078 fetch_source(mach, &arg[0], &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_FLOAT);
2079 micro_mul(&scale, &arg[0], &arg[0]);
2080
2081 for (chan = CHAN_Y; chan <= CHAN_Z; chan++) {
2082 union tgsi_exec_channel product;
2083
2084 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2085 micro_mul(&product, &arg[chan], &arg[chan]);
2086 micro_add(&scale, &scale, &product);
2087 }
2088
2089 micro_rsq(&scale, &scale);
2090
2091 for (chan = CHAN_X; chan <= CHAN_Z; chan++) {
2092 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2093 micro_mul(&arg[chan], &arg[chan], &scale);
2094 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2095 }
2096 }
2097 }
2098
2099 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2100 store_dest(mach, &OneVec, &inst->Dst[0], inst, CHAN_W, TGSI_EXEC_DATA_FLOAT);
2101 }
2102 }
2103
2104 static void
2105 exec_break(struct tgsi_exec_machine *mach)
2106 {
2107 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
2108 /* turn off loop channels for each enabled exec channel */
2109 mach->LoopMask &= ~mach->ExecMask;
2110 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2111 UPDATE_EXEC_MASK(mach);
2112 } else {
2113 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
2114
2115 mach->Switch.mask = 0x0;
2116
2117 UPDATE_EXEC_MASK(mach);
2118 }
2119 }
2120
2121 static void
2122 exec_switch(struct tgsi_exec_machine *mach,
2123 const struct tgsi_full_instruction *inst)
2124 {
2125 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
2126 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
2127
2128 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
2129 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2130 mach->Switch.mask = 0x0;
2131 mach->Switch.defaultMask = 0x0;
2132
2133 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
2134 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
2135
2136 UPDATE_EXEC_MASK(mach);
2137 }
2138
2139 static void
2140 exec_case(struct tgsi_exec_machine *mach,
2141 const struct tgsi_full_instruction *inst)
2142 {
2143 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2144 union tgsi_exec_channel src;
2145 uint mask = 0;
2146
2147 fetch_source(mach, &src, &inst->Src[0], CHAN_X, TGSI_EXEC_DATA_UINT);
2148
2149 if (mach->Switch.selector.u[0] == src.u[0]) {
2150 mask |= 0x1;
2151 }
2152 if (mach->Switch.selector.u[1] == src.u[1]) {
2153 mask |= 0x2;
2154 }
2155 if (mach->Switch.selector.u[2] == src.u[2]) {
2156 mask |= 0x4;
2157 }
2158 if (mach->Switch.selector.u[3] == src.u[3]) {
2159 mask |= 0x8;
2160 }
2161
2162 mach->Switch.defaultMask |= mask;
2163
2164 mach->Switch.mask |= mask & prevMask;
2165
2166 UPDATE_EXEC_MASK(mach);
2167 }
2168
2169 static void
2170 exec_default(struct tgsi_exec_machine *mach)
2171 {
2172 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2173
2174 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
2175
2176 UPDATE_EXEC_MASK(mach);
2177 }
2178
2179 static void
2180 exec_endswitch(struct tgsi_exec_machine *mach)
2181 {
2182 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
2183 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
2184
2185 UPDATE_EXEC_MASK(mach);
2186 }
2187
2188 static void
2189 micro_i2f(union tgsi_exec_channel *dst,
2190 const union tgsi_exec_channel *src)
2191 {
2192 dst->f[0] = (float)src->i[0];
2193 dst->f[1] = (float)src->i[1];
2194 dst->f[2] = (float)src->i[2];
2195 dst->f[3] = (float)src->i[3];
2196 }
2197
2198 static void
2199 micro_not(union tgsi_exec_channel *dst,
2200 const union tgsi_exec_channel *src)
2201 {
2202 dst->u[0] = ~src->u[0];
2203 dst->u[1] = ~src->u[1];
2204 dst->u[2] = ~src->u[2];
2205 dst->u[3] = ~src->u[3];
2206 }
2207
2208 static void
2209 micro_shl(union tgsi_exec_channel *dst,
2210 const union tgsi_exec_channel *src0,
2211 const union tgsi_exec_channel *src1)
2212 {
2213 dst->u[0] = src0->u[0] << src1->u[0];
2214 dst->u[1] = src0->u[1] << src1->u[1];
2215 dst->u[2] = src0->u[2] << src1->u[2];
2216 dst->u[3] = src0->u[3] << src1->u[3];
2217 }
2218
2219 static void
2220 micro_and(union tgsi_exec_channel *dst,
2221 const union tgsi_exec_channel *src0,
2222 const union tgsi_exec_channel *src1)
2223 {
2224 dst->u[0] = src0->u[0] & src1->u[0];
2225 dst->u[1] = src0->u[1] & src1->u[1];
2226 dst->u[2] = src0->u[2] & src1->u[2];
2227 dst->u[3] = src0->u[3] & src1->u[3];
2228 }
2229
2230 static void
2231 micro_or(union tgsi_exec_channel *dst,
2232 const union tgsi_exec_channel *src0,
2233 const union tgsi_exec_channel *src1)
2234 {
2235 dst->u[0] = src0->u[0] | src1->u[0];
2236 dst->u[1] = src0->u[1] | src1->u[1];
2237 dst->u[2] = src0->u[2] | src1->u[2];
2238 dst->u[3] = src0->u[3] | src1->u[3];
2239 }
2240
2241 static void
2242 micro_xor(union tgsi_exec_channel *dst,
2243 const union tgsi_exec_channel *src0,
2244 const union tgsi_exec_channel *src1)
2245 {
2246 dst->u[0] = src0->u[0] ^ src1->u[0];
2247 dst->u[1] = src0->u[1] ^ src1->u[1];
2248 dst->u[2] = src0->u[2] ^ src1->u[2];
2249 dst->u[3] = src0->u[3] ^ src1->u[3];
2250 }
2251
2252 static void
2253 micro_f2i(union tgsi_exec_channel *dst,
2254 const union tgsi_exec_channel *src)
2255 {
2256 dst->i[0] = (int)src->f[0];
2257 dst->i[1] = (int)src->f[1];
2258 dst->i[2] = (int)src->f[2];
2259 dst->i[3] = (int)src->f[3];
2260 }
2261
2262 static void
2263 micro_idiv(union tgsi_exec_channel *dst,
2264 const union tgsi_exec_channel *src0,
2265 const union tgsi_exec_channel *src1)
2266 {
2267 dst->i[0] = src0->i[0] / src1->i[0];
2268 dst->i[1] = src0->i[1] / src1->i[1];
2269 dst->i[2] = src0->i[2] / src1->i[2];
2270 dst->i[3] = src0->i[3] / src1->i[3];
2271 }
2272
2273 static void
2274 micro_imax(union tgsi_exec_channel *dst,
2275 const union tgsi_exec_channel *src0,
2276 const union tgsi_exec_channel *src1)
2277 {
2278 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
2279 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
2280 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
2281 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
2282 }
2283
2284 static void
2285 micro_imin(union tgsi_exec_channel *dst,
2286 const union tgsi_exec_channel *src0,
2287 const union tgsi_exec_channel *src1)
2288 {
2289 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
2290 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
2291 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
2292 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
2293 }
2294
2295 static void
2296 micro_isge(union tgsi_exec_channel *dst,
2297 const union tgsi_exec_channel *src0,
2298 const union tgsi_exec_channel *src1)
2299 {
2300 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
2301 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
2302 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
2303 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
2304 }
2305
2306 static void
2307 micro_ishr(union tgsi_exec_channel *dst,
2308 const union tgsi_exec_channel *src0,
2309 const union tgsi_exec_channel *src1)
2310 {
2311 dst->i[0] = src0->i[0] >> src1->i[0];
2312 dst->i[1] = src0->i[1] >> src1->i[1];
2313 dst->i[2] = src0->i[2] >> src1->i[2];
2314 dst->i[3] = src0->i[3] >> src1->i[3];
2315 }
2316
2317 static void
2318 micro_islt(union tgsi_exec_channel *dst,
2319 const union tgsi_exec_channel *src0,
2320 const union tgsi_exec_channel *src1)
2321 {
2322 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
2323 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
2324 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
2325 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
2326 }
2327
2328 static void
2329 micro_f2u(union tgsi_exec_channel *dst,
2330 const union tgsi_exec_channel *src)
2331 {
2332 dst->u[0] = (uint)src->f[0];
2333 dst->u[1] = (uint)src->f[1];
2334 dst->u[2] = (uint)src->f[2];
2335 dst->u[3] = (uint)src->f[3];
2336 }
2337
2338 static void
2339 micro_u2f(union tgsi_exec_channel *dst,
2340 const union tgsi_exec_channel *src)
2341 {
2342 dst->f[0] = (float)src->u[0];
2343 dst->f[1] = (float)src->u[1];
2344 dst->f[2] = (float)src->u[2];
2345 dst->f[3] = (float)src->u[3];
2346 }
2347
2348 static void
2349 micro_uadd(union tgsi_exec_channel *dst,
2350 const union tgsi_exec_channel *src0,
2351 const union tgsi_exec_channel *src1)
2352 {
2353 dst->u[0] = src0->u[0] + src1->u[0];
2354 dst->u[1] = src0->u[1] + src1->u[1];
2355 dst->u[2] = src0->u[2] + src1->u[2];
2356 dst->u[3] = src0->u[3] + src1->u[3];
2357 }
2358
2359 static void
2360 micro_udiv(union tgsi_exec_channel *dst,
2361 const union tgsi_exec_channel *src0,
2362 const union tgsi_exec_channel *src1)
2363 {
2364 dst->u[0] = src0->u[0] / src1->u[0];
2365 dst->u[1] = src0->u[1] / src1->u[1];
2366 dst->u[2] = src0->u[2] / src1->u[2];
2367 dst->u[3] = src0->u[3] / src1->u[3];
2368 }
2369
2370 static void
2371 micro_umad(union tgsi_exec_channel *dst,
2372 const union tgsi_exec_channel *src0,
2373 const union tgsi_exec_channel *src1,
2374 const union tgsi_exec_channel *src2)
2375 {
2376 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
2377 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
2378 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
2379 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
2380 }
2381
2382 static void
2383 micro_umax(union tgsi_exec_channel *dst,
2384 const union tgsi_exec_channel *src0,
2385 const union tgsi_exec_channel *src1)
2386 {
2387 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
2388 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
2389 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
2390 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
2391 }
2392
2393 static void
2394 micro_umin(union tgsi_exec_channel *dst,
2395 const union tgsi_exec_channel *src0,
2396 const union tgsi_exec_channel *src1)
2397 {
2398 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
2399 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
2400 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
2401 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
2402 }
2403
2404 static void
2405 micro_umod(union tgsi_exec_channel *dst,
2406 const union tgsi_exec_channel *src0,
2407 const union tgsi_exec_channel *src1)
2408 {
2409 dst->u[0] = src0->u[0] % src1->u[0];
2410 dst->u[1] = src0->u[1] % src1->u[1];
2411 dst->u[2] = src0->u[2] % src1->u[2];
2412 dst->u[3] = src0->u[3] % src1->u[3];
2413 }
2414
2415 static void
2416 micro_umul(union tgsi_exec_channel *dst,
2417 const union tgsi_exec_channel *src0,
2418 const union tgsi_exec_channel *src1)
2419 {
2420 dst->u[0] = src0->u[0] * src1->u[0];
2421 dst->u[1] = src0->u[1] * src1->u[1];
2422 dst->u[2] = src0->u[2] * src1->u[2];
2423 dst->u[3] = src0->u[3] * src1->u[3];
2424 }
2425
2426 static void
2427 micro_useq(union tgsi_exec_channel *dst,
2428 const union tgsi_exec_channel *src0,
2429 const union tgsi_exec_channel *src1)
2430 {
2431 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
2432 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
2433 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
2434 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
2435 }
2436
2437 static void
2438 micro_usge(union tgsi_exec_channel *dst,
2439 const union tgsi_exec_channel *src0,
2440 const union tgsi_exec_channel *src1)
2441 {
2442 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
2443 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
2444 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
2445 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
2446 }
2447
2448 static void
2449 micro_ushr(union tgsi_exec_channel *dst,
2450 const union tgsi_exec_channel *src0,
2451 const union tgsi_exec_channel *src1)
2452 {
2453 dst->u[0] = src0->u[0] >> src1->u[0];
2454 dst->u[1] = src0->u[1] >> src1->u[1];
2455 dst->u[2] = src0->u[2] >> src1->u[2];
2456 dst->u[3] = src0->u[3] >> src1->u[3];
2457 }
2458
2459 static void
2460 micro_uslt(union tgsi_exec_channel *dst,
2461 const union tgsi_exec_channel *src0,
2462 const union tgsi_exec_channel *src1)
2463 {
2464 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
2465 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
2466 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
2467 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
2468 }
2469
2470 static void
2471 micro_usne(union tgsi_exec_channel *dst,
2472 const union tgsi_exec_channel *src0,
2473 const union tgsi_exec_channel *src1)
2474 {
2475 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
2476 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
2477 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
2478 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
2479 }
2480
2481 static void
2482 exec_instruction(
2483 struct tgsi_exec_machine *mach,
2484 const struct tgsi_full_instruction *inst,
2485 int *pc )
2486 {
2487 uint chan_index;
2488 union tgsi_exec_channel r[10];
2489 union tgsi_exec_channel d[8];
2490
2491 (*pc)++;
2492
2493 switch (inst->Instruction.Opcode) {
2494 case TGSI_OPCODE_ARL:
2495 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
2496 break;
2497
2498 case TGSI_OPCODE_MOV:
2499 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
2500 break;
2501
2502 case TGSI_OPCODE_LIT:
2503 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y ) || IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2504 FETCH( &r[0], 0, CHAN_X );
2505 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2506 micro_max(&d[CHAN_Y], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2507 }
2508
2509 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2510 FETCH( &r[1], 0, CHAN_Y );
2511 micro_max( &r[1], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C] );
2512
2513 FETCH( &r[2], 0, CHAN_W );
2514 micro_min( &r[2], &r[2], &mach->Temps[TEMP_128_I].xyzw[TEMP_128_C] );
2515 micro_max( &r[2], &r[2], &mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C] );
2516 micro_pow( &r[1], &r[1], &r[2] );
2517 micro_lt(&d[CHAN_Z], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[0], &r[1], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C]);
2518 }
2519
2520 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2521 STORE(&d[CHAN_Y], 0, CHAN_Y);
2522 }
2523 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2524 STORE(&d[CHAN_Z], 0, CHAN_Z);
2525 }
2526 }
2527 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2528 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X );
2529 }
2530 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2531 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2532 }
2533 break;
2534
2535 case TGSI_OPCODE_RCP:
2536 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2537 break;
2538
2539 case TGSI_OPCODE_RSQ:
2540 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2541 break;
2542
2543 case TGSI_OPCODE_EXP:
2544 FETCH( &r[0], 0, CHAN_X );
2545 micro_flr( &r[1], &r[0] ); /* r1 = floor(r0) */
2546 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2547 micro_exp2( &r[2], &r[1] ); /* r2 = 2 ^ r1 */
2548 STORE( &r[2], 0, CHAN_X ); /* store r2 */
2549 }
2550 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2551 micro_sub( &r[2], &r[0], &r[1] ); /* r2 = r0 - r1 */
2552 STORE( &r[2], 0, CHAN_Y ); /* store r2 */
2553 }
2554 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2555 micro_exp2( &r[2], &r[0] ); /* r2 = 2 ^ r0 */
2556 STORE( &r[2], 0, CHAN_Z ); /* store r2 */
2557 }
2558 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2559 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2560 }
2561 break;
2562
2563 case TGSI_OPCODE_LOG:
2564 FETCH( &r[0], 0, CHAN_X );
2565 micro_abs( &r[2], &r[0] ); /* r2 = abs(r0) */
2566 micro_lg2( &r[1], &r[2] ); /* r1 = lg2(r2) */
2567 micro_flr( &r[0], &r[1] ); /* r0 = floor(r1) */
2568 if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
2569 STORE( &r[0], 0, CHAN_X );
2570 }
2571 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2572 micro_exp2( &r[0], &r[0] ); /* r0 = 2 ^ r0 */
2573 micro_div( &r[0], &r[2], &r[0] ); /* r0 = r2 / r0 */
2574 STORE( &r[0], 0, CHAN_Y );
2575 }
2576 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2577 STORE( &r[1], 0, CHAN_Z );
2578 }
2579 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2580 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2581 }
2582 break;
2583
2584 case TGSI_OPCODE_MUL:
2585 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2586 break;
2587
2588 case TGSI_OPCODE_ADD:
2589 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2590 break;
2591
2592 case TGSI_OPCODE_DP3:
2593 exec_dp3(mach, inst);
2594 break;
2595
2596 case TGSI_OPCODE_DP4:
2597 exec_dp4(mach, inst);
2598 break;
2599
2600 case TGSI_OPCODE_DST:
2601 if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
2602 FETCH( &r[0], 0, CHAN_Y );
2603 FETCH( &r[1], 1, CHAN_Y);
2604 micro_mul(&d[CHAN_Y], &r[0], &r[1]);
2605 }
2606 if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
2607 FETCH(&d[CHAN_Z], 0, CHAN_Z);
2608 }
2609 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2610 FETCH(&d[CHAN_W], 1, CHAN_W);
2611 }
2612
2613 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2614 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_X);
2615 }
2616 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2617 STORE(&d[CHAN_Y], 0, CHAN_Y);
2618 }
2619 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2620 STORE(&d[CHAN_Z], 0, CHAN_Z);
2621 }
2622 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2623 STORE(&d[CHAN_W], 0, CHAN_W);
2624 }
2625 break;
2626
2627 case TGSI_OPCODE_MIN:
2628 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2629 break;
2630
2631 case TGSI_OPCODE_MAX:
2632 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2633 break;
2634
2635 case TGSI_OPCODE_SLT:
2636 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2637 break;
2638
2639 case TGSI_OPCODE_SGE:
2640 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2641 break;
2642
2643 case TGSI_OPCODE_MAD:
2644 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2645 break;
2646
2647 case TGSI_OPCODE_SUB:
2648 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2649 break;
2650
2651 case TGSI_OPCODE_LRP:
2652 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2653 break;
2654
2655 case TGSI_OPCODE_CND:
2656 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2657 FETCH(&r[0], 0, chan_index);
2658 FETCH(&r[1], 1, chan_index);
2659 FETCH(&r[2], 2, chan_index);
2660 micro_lt(&d[chan_index], &mach->Temps[TEMP_HALF_I].xyzw[TEMP_HALF_C], &r[2], &r[0], &r[1]);
2661 }
2662 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2663 STORE(&d[chan_index], 0, chan_index);
2664 }
2665 break;
2666
2667 case TGSI_OPCODE_DP2A:
2668 exec_dp2a(mach, inst);
2669 break;
2670
2671 case TGSI_OPCODE_FRC:
2672 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2673 break;
2674
2675 case TGSI_OPCODE_CLAMP:
2676 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2677 FETCH(&r[0], 0, chan_index);
2678 FETCH(&r[1], 1, chan_index);
2679 micro_max(&r[0], &r[0], &r[1]);
2680 FETCH(&r[1], 2, chan_index);
2681 micro_min(&d[chan_index], &r[0], &r[1]);
2682 }
2683 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2684 STORE(&d[chan_index], 0, chan_index);
2685 }
2686 break;
2687
2688 case TGSI_OPCODE_FLR:
2689 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2690 break;
2691
2692 case TGSI_OPCODE_ROUND:
2693 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2694 break;
2695
2696 case TGSI_OPCODE_EX2:
2697 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2698 break;
2699
2700 case TGSI_OPCODE_LG2:
2701 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2702 break;
2703
2704 case TGSI_OPCODE_POW:
2705 FETCH(&r[0], 0, CHAN_X);
2706 FETCH(&r[1], 1, CHAN_X);
2707
2708 micro_pow( &r[0], &r[0], &r[1] );
2709
2710 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
2711 STORE( &r[0], 0, chan_index );
2712 }
2713 break;
2714
2715 case TGSI_OPCODE_XPD:
2716 FETCH(&r[0], 0, CHAN_Y);
2717 FETCH(&r[1], 1, CHAN_Z);
2718
2719 micro_mul( &r[2], &r[0], &r[1] );
2720
2721 FETCH(&r[3], 0, CHAN_Z);
2722 FETCH(&r[4], 1, CHAN_Y);
2723
2724 micro_mul( &r[5], &r[3], &r[4] );
2725 micro_sub(&d[CHAN_X], &r[2], &r[5]);
2726
2727 FETCH(&r[2], 1, CHAN_X);
2728
2729 micro_mul( &r[3], &r[3], &r[2] );
2730
2731 FETCH(&r[5], 0, CHAN_X);
2732
2733 micro_mul( &r[1], &r[1], &r[5] );
2734 micro_sub(&d[CHAN_Y], &r[3], &r[1]);
2735
2736 micro_mul( &r[5], &r[5], &r[4] );
2737 micro_mul( &r[0], &r[0], &r[2] );
2738 micro_sub(&d[CHAN_Z], &r[5], &r[0]);
2739
2740 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2741 STORE(&d[CHAN_X], 0, CHAN_X);
2742 }
2743 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2744 STORE(&d[CHAN_Y], 0, CHAN_Y);
2745 }
2746 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2747 STORE(&d[CHAN_Z], 0, CHAN_Z);
2748 }
2749 if (IS_CHANNEL_ENABLED( *inst, CHAN_W )) {
2750 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
2751 }
2752 break;
2753
2754 case TGSI_OPCODE_ABS:
2755 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2756 break;
2757
2758 case TGSI_OPCODE_RCC:
2759 FETCH(&r[0], 0, CHAN_X);
2760 micro_div(&r[0], &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], &r[0]);
2761 micro_float_clamp(&r[0], &r[0]);
2762 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2763 STORE(&r[0], 0, chan_index);
2764 }
2765 break;
2766
2767 case TGSI_OPCODE_DPH:
2768 exec_dph(mach, inst);
2769 break;
2770
2771 case TGSI_OPCODE_COS:
2772 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2773 break;
2774
2775 case TGSI_OPCODE_DDX:
2776 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2777 break;
2778
2779 case TGSI_OPCODE_DDY:
2780 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2781 break;
2782
2783 case TGSI_OPCODE_KILP:
2784 exec_kilp (mach, inst);
2785 break;
2786
2787 case TGSI_OPCODE_KIL:
2788 exec_kil (mach, inst);
2789 break;
2790
2791 case TGSI_OPCODE_PK2H:
2792 assert (0);
2793 break;
2794
2795 case TGSI_OPCODE_PK2US:
2796 assert (0);
2797 break;
2798
2799 case TGSI_OPCODE_PK4B:
2800 assert (0);
2801 break;
2802
2803 case TGSI_OPCODE_PK4UB:
2804 assert (0);
2805 break;
2806
2807 case TGSI_OPCODE_RFL:
2808 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2809 IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2810 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2811 /* r0 = dp3(src0, src0) */
2812 FETCH(&r[2], 0, CHAN_X);
2813 micro_mul(&r[0], &r[2], &r[2]);
2814 FETCH(&r[4], 0, CHAN_Y);
2815 micro_mul(&r[8], &r[4], &r[4]);
2816 micro_add(&r[0], &r[0], &r[8]);
2817 FETCH(&r[6], 0, CHAN_Z);
2818 micro_mul(&r[8], &r[6], &r[6]);
2819 micro_add(&r[0], &r[0], &r[8]);
2820
2821 /* r1 = dp3(src0, src1) */
2822 FETCH(&r[3], 1, CHAN_X);
2823 micro_mul(&r[1], &r[2], &r[3]);
2824 FETCH(&r[5], 1, CHAN_Y);
2825 micro_mul(&r[8], &r[4], &r[5]);
2826 micro_add(&r[1], &r[1], &r[8]);
2827 FETCH(&r[7], 1, CHAN_Z);
2828 micro_mul(&r[8], &r[6], &r[7]);
2829 micro_add(&r[1], &r[1], &r[8]);
2830
2831 /* r1 = 2 * r1 / r0 */
2832 micro_add(&r[1], &r[1], &r[1]);
2833 micro_div(&r[1], &r[1], &r[0]);
2834
2835 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2836 micro_mul(&r[2], &r[2], &r[1]);
2837 micro_sub(&r[2], &r[2], &r[3]);
2838 STORE(&r[2], 0, CHAN_X);
2839 }
2840 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2841 micro_mul(&r[4], &r[4], &r[1]);
2842 micro_sub(&r[4], &r[4], &r[5]);
2843 STORE(&r[4], 0, CHAN_Y);
2844 }
2845 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2846 micro_mul(&r[6], &r[6], &r[1]);
2847 micro_sub(&r[6], &r[6], &r[7]);
2848 STORE(&r[6], 0, CHAN_Z);
2849 }
2850 }
2851 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2852 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W);
2853 }
2854 break;
2855
2856 case TGSI_OPCODE_SEQ:
2857 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2858 break;
2859
2860 case TGSI_OPCODE_SFL:
2861 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2862 STORE(&mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, chan_index);
2863 }
2864 break;
2865
2866 case TGSI_OPCODE_SGT:
2867 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2868 break;
2869
2870 case TGSI_OPCODE_SIN:
2871 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2872 break;
2873
2874 case TGSI_OPCODE_SLE:
2875 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2876 break;
2877
2878 case TGSI_OPCODE_SNE:
2879 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
2880 break;
2881
2882 case TGSI_OPCODE_STR:
2883 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
2884 STORE(&mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, chan_index);
2885 }
2886 break;
2887
2888 case TGSI_OPCODE_TEX:
2889 /* simple texture lookup */
2890 /* src[0] = texcoord */
2891 /* src[1] = sampler unit */
2892 exec_tex(mach, inst, TEX_MODIFIER_NONE);
2893 break;
2894
2895 case TGSI_OPCODE_TXB:
2896 /* Texture lookup with lod bias */
2897 /* src[0] = texcoord (src[0].w = LOD bias) */
2898 /* src[1] = sampler unit */
2899 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS);
2900 break;
2901
2902 case TGSI_OPCODE_TXD:
2903 /* Texture lookup with explict partial derivatives */
2904 /* src[0] = texcoord */
2905 /* src[1] = d[strq]/dx */
2906 /* src[2] = d[strq]/dy */
2907 /* src[3] = sampler unit */
2908 exec_txd(mach, inst);
2909 break;
2910
2911 case TGSI_OPCODE_TXL:
2912 /* Texture lookup with explit LOD */
2913 /* src[0] = texcoord (src[0].w = LOD) */
2914 /* src[1] = sampler unit */
2915 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD);
2916 break;
2917
2918 case TGSI_OPCODE_TXP:
2919 /* Texture lookup with projection */
2920 /* src[0] = texcoord (src[0].w = projection) */
2921 /* src[1] = sampler unit */
2922 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED);
2923 break;
2924
2925 case TGSI_OPCODE_UP2H:
2926 assert (0);
2927 break;
2928
2929 case TGSI_OPCODE_UP2US:
2930 assert (0);
2931 break;
2932
2933 case TGSI_OPCODE_UP4B:
2934 assert (0);
2935 break;
2936
2937 case TGSI_OPCODE_UP4UB:
2938 assert (0);
2939 break;
2940
2941 case TGSI_OPCODE_X2D:
2942 FETCH(&r[0], 1, CHAN_X);
2943 FETCH(&r[1], 1, CHAN_Y);
2944 if (IS_CHANNEL_ENABLED(*inst, CHAN_X) ||
2945 IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2946 FETCH(&r[2], 2, CHAN_X);
2947 micro_mul(&r[2], &r[2], &r[0]);
2948 FETCH(&r[3], 2, CHAN_Y);
2949 micro_mul(&r[3], &r[3], &r[1]);
2950 micro_add(&r[2], &r[2], &r[3]);
2951 FETCH(&r[3], 0, CHAN_X);
2952 micro_add(&d[CHAN_X], &r[2], &r[3]);
2953
2954 }
2955 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y) ||
2956 IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2957 FETCH(&r[2], 2, CHAN_Z);
2958 micro_mul(&r[2], &r[2], &r[0]);
2959 FETCH(&r[3], 2, CHAN_W);
2960 micro_mul(&r[3], &r[3], &r[1]);
2961 micro_add(&r[2], &r[2], &r[3]);
2962 FETCH(&r[3], 0, CHAN_Y);
2963 micro_add(&d[CHAN_Y], &r[2], &r[3]);
2964
2965 }
2966 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
2967 STORE(&d[CHAN_X], 0, CHAN_X);
2968 }
2969 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
2970 STORE(&d[CHAN_Y], 0, CHAN_Y);
2971 }
2972 if (IS_CHANNEL_ENABLED(*inst, CHAN_Z)) {
2973 STORE(&d[CHAN_X], 0, CHAN_Z);
2974 }
2975 if (IS_CHANNEL_ENABLED(*inst, CHAN_W)) {
2976 STORE(&d[CHAN_Y], 0, CHAN_W);
2977 }
2978 break;
2979
2980 case TGSI_OPCODE_ARA:
2981 assert (0);
2982 break;
2983
2984 case TGSI_OPCODE_ARR:
2985 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
2986 break;
2987
2988 case TGSI_OPCODE_BRA:
2989 assert (0);
2990 break;
2991
2992 case TGSI_OPCODE_CAL:
2993 /* skip the call if no execution channels are enabled */
2994 if (mach->ExecMask) {
2995 /* do the call */
2996
2997 /* First, record the depths of the execution stacks.
2998 * This is important for deeply nested/looped return statements.
2999 * We have to unwind the stacks by the correct amount. For a
3000 * real code generator, we could determine the number of entries
3001 * to pop off each stack with simple static analysis and avoid
3002 * implementing this data structure at run time.
3003 */
3004 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3005 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3006 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3007 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3008 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3009 /* note that PC was already incremented above */
3010 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3011
3012 mach->CallStackTop++;
3013
3014 /* Second, push the Cond, Loop, Cont, Func stacks */
3015 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3016 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3017 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3018 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3019 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3020 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3021
3022 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3023 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3024 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3025 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3026 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3027 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3028
3029 /* Finally, jump to the subroutine */
3030 *pc = inst->Label.Label;
3031 }
3032 break;
3033
3034 case TGSI_OPCODE_RET:
3035 mach->FuncMask &= ~mach->ExecMask;
3036 UPDATE_EXEC_MASK(mach);
3037
3038 if (mach->FuncMask == 0x0) {
3039 /* really return now (otherwise, keep executing */
3040
3041 if (mach->CallStackTop == 0) {
3042 /* returning from main() */
3043 *pc = -1;
3044 return;
3045 }
3046
3047 assert(mach->CallStackTop > 0);
3048 mach->CallStackTop--;
3049
3050 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3051 mach->CondMask = mach->CondStack[mach->CondStackTop];
3052
3053 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3054 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3055
3056 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3057 mach->ContMask = mach->ContStack[mach->ContStackTop];
3058
3059 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3060 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3061
3062 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3063 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3064
3065 assert(mach->FuncStackTop > 0);
3066 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3067
3068 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3069
3070 UPDATE_EXEC_MASK(mach);
3071 }
3072 break;
3073
3074 case TGSI_OPCODE_SSG:
3075 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3076 break;
3077
3078 case TGSI_OPCODE_CMP:
3079 FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
3080 FETCH(&r[0], 0, chan_index);
3081 FETCH(&r[1], 1, chan_index);
3082 FETCH(&r[2], 2, chan_index);
3083 micro_lt(&d[chan_index], &r[0], &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], &r[1], &r[2]);
3084 }
3085 FOR_EACH_ENABLED_CHANNEL(*inst, chan_index) {
3086 STORE(&d[chan_index], 0, chan_index);
3087 }
3088 break;
3089
3090 case TGSI_OPCODE_SCS:
3091 if( IS_CHANNEL_ENABLED( *inst, CHAN_X ) || IS_CHANNEL_ENABLED( *inst, CHAN_Y ) ) {
3092 FETCH( &r[0], 0, CHAN_X );
3093 if (IS_CHANNEL_ENABLED(*inst, CHAN_X)) {
3094 micro_cos(&r[1], &r[0]);
3095 STORE(&r[1], 0, CHAN_X);
3096 }
3097 if (IS_CHANNEL_ENABLED(*inst, CHAN_Y)) {
3098 micro_sin(&r[1], &r[0]);
3099 STORE(&r[1], 0, CHAN_Y);
3100 }
3101 }
3102 if( IS_CHANNEL_ENABLED( *inst, CHAN_Z ) ) {
3103 STORE( &mach->Temps[TEMP_0_I].xyzw[TEMP_0_C], 0, CHAN_Z );
3104 }
3105 if( IS_CHANNEL_ENABLED( *inst, CHAN_W ) ) {
3106 STORE( &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C], 0, CHAN_W );
3107 }
3108 break;
3109
3110 case TGSI_OPCODE_NRM:
3111 exec_nrm3(mach, inst);
3112 break;
3113
3114 case TGSI_OPCODE_NRM4:
3115 exec_nrm4(mach, inst);
3116 break;
3117
3118 case TGSI_OPCODE_DIV:
3119 assert( 0 );
3120 break;
3121
3122 case TGSI_OPCODE_DP2:
3123 exec_dp2(mach, inst);
3124 break;
3125
3126 case TGSI_OPCODE_IF:
3127 /* push CondMask */
3128 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3129 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3130 FETCH( &r[0], 0, CHAN_X );
3131 /* update CondMask */
3132 if( ! r[0].u[0] ) {
3133 mach->CondMask &= ~0x1;
3134 }
3135 if( ! r[0].u[1] ) {
3136 mach->CondMask &= ~0x2;
3137 }
3138 if( ! r[0].u[2] ) {
3139 mach->CondMask &= ~0x4;
3140 }
3141 if( ! r[0].u[3] ) {
3142 mach->CondMask &= ~0x8;
3143 }
3144 UPDATE_EXEC_MASK(mach);
3145 /* Todo: If CondMask==0, jump to ELSE */
3146 break;
3147
3148 case TGSI_OPCODE_ELSE:
3149 /* invert CondMask wrt previous mask */
3150 {
3151 uint prevMask;
3152 assert(mach->CondStackTop > 0);
3153 prevMask = mach->CondStack[mach->CondStackTop - 1];
3154 mach->CondMask = ~mach->CondMask & prevMask;
3155 UPDATE_EXEC_MASK(mach);
3156 /* Todo: If CondMask==0, jump to ENDIF */
3157 }
3158 break;
3159
3160 case TGSI_OPCODE_ENDIF:
3161 /* pop CondMask */
3162 assert(mach->CondStackTop > 0);
3163 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3164 UPDATE_EXEC_MASK(mach);
3165 break;
3166
3167 case TGSI_OPCODE_END:
3168 /* halt execution */
3169 *pc = -1;
3170 break;
3171
3172 case TGSI_OPCODE_REP:
3173 assert (0);
3174 break;
3175
3176 case TGSI_OPCODE_ENDREP:
3177 assert (0);
3178 break;
3179
3180 case TGSI_OPCODE_PUSHA:
3181 assert (0);
3182 break;
3183
3184 case TGSI_OPCODE_POPA:
3185 assert (0);
3186 break;
3187
3188 case TGSI_OPCODE_CEIL:
3189 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3190 break;
3191
3192 case TGSI_OPCODE_I2F:
3193 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3194 break;
3195
3196 case TGSI_OPCODE_NOT:
3197 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3198 break;
3199
3200 case TGSI_OPCODE_TRUNC:
3201 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3202 break;
3203
3204 case TGSI_OPCODE_SHL:
3205 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3206 break;
3207
3208 case TGSI_OPCODE_AND:
3209 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3210 break;
3211
3212 case TGSI_OPCODE_OR:
3213 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3214 break;
3215
3216 case TGSI_OPCODE_MOD:
3217 assert (0);
3218 break;
3219
3220 case TGSI_OPCODE_XOR:
3221 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3222 break;
3223
3224 case TGSI_OPCODE_SAD:
3225 assert (0);
3226 break;
3227
3228 case TGSI_OPCODE_TXF:
3229 assert (0);
3230 break;
3231
3232 case TGSI_OPCODE_TXQ:
3233 assert (0);
3234 break;
3235
3236 case TGSI_OPCODE_EMIT:
3237 emit_vertex(mach);
3238 break;
3239
3240 case TGSI_OPCODE_ENDPRIM:
3241 emit_primitive(mach);
3242 break;
3243
3244 case TGSI_OPCODE_BGNFOR:
3245 assert(mach->LoopCounterStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3246 for (chan_index = 0; chan_index < 3; chan_index++) {
3247 FETCH( &mach->LoopCounterStack[mach->LoopCounterStackTop].xyzw[chan_index], 0, chan_index );
3248 }
3249 ++mach->LoopCounterStackTop;
3250 STORE(&mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X], 0, CHAN_X);
3251 /* update LoopMask */
3252 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[0] <= 0.0f) {
3253 mach->LoopMask &= ~0x1;
3254 }
3255 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[1] <= 0.0f) {
3256 mach->LoopMask &= ~0x2;
3257 }
3258 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[2] <= 0.0f) {
3259 mach->LoopMask &= ~0x4;
3260 }
3261 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[3] <= 0.0f) {
3262 mach->LoopMask &= ~0x8;
3263 }
3264 /* TODO: if mach->LoopMask == 0, jump to end of loop */
3265 UPDATE_EXEC_MASK(mach);
3266 /* fall-through (for now) */
3267 case TGSI_OPCODE_BGNLOOP:
3268 /* push LoopMask and ContMasks */
3269 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3270 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3271 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3272 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3273
3274 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3275 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3276 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
3277 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3278 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
3279 break;
3280
3281 case TGSI_OPCODE_ENDFOR:
3282 assert(mach->LoopCounterStackTop > 0);
3283 micro_sub(&mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y],
3284 &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y],
3285 &mach->Temps[TEMP_1_I].xyzw[TEMP_1_C]);
3286 /* update LoopMask */
3287 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[0] <= 0.0f) {
3288 mach->LoopMask &= ~0x1;
3289 }
3290 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[1] <= 0.0f) {
3291 mach->LoopMask &= ~0x2;
3292 }
3293 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[2] <= 0.0f) {
3294 mach->LoopMask &= ~0x4;
3295 }
3296 if (mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Y].f[3] <= 0.0f) {
3297 mach->LoopMask &= ~0x8;
3298 }
3299 micro_add(&mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X],
3300 &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_X],
3301 &mach->LoopCounterStack[mach->LoopCounterStackTop - 1].xyzw[CHAN_Z]);
3302 assert(mach->LoopLabelStackTop > 0);
3303 inst = mach->Instructions + mach->LoopLabelStack[mach->LoopLabelStackTop - 1];
3304 STORE(&mach->LoopCounterStack[mach->LoopCounterStackTop].xyzw[CHAN_X], 0, CHAN_X);
3305 /* Restore ContMask, but don't pop */
3306 assert(mach->ContStackTop > 0);
3307 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3308 UPDATE_EXEC_MASK(mach);
3309 if (mach->ExecMask) {
3310 /* repeat loop: jump to instruction just past BGNLOOP */
3311 assert(mach->LoopLabelStackTop > 0);
3312 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3313 }
3314 else {
3315 /* exit loop: pop LoopMask */
3316 assert(mach->LoopStackTop > 0);
3317 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3318 /* pop ContMask */
3319 assert(mach->ContStackTop > 0);
3320 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3321 assert(mach->LoopLabelStackTop > 0);
3322 --mach->LoopLabelStackTop;
3323 assert(mach->LoopCounterStackTop > 0);
3324 --mach->LoopCounterStackTop;
3325
3326 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3327 }
3328 UPDATE_EXEC_MASK(mach);
3329 break;
3330
3331 case TGSI_OPCODE_ENDLOOP:
3332 /* Restore ContMask, but don't pop */
3333 assert(mach->ContStackTop > 0);
3334 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
3335 UPDATE_EXEC_MASK(mach);
3336 if (mach->ExecMask) {
3337 /* repeat loop: jump to instruction just past BGNLOOP */
3338 assert(mach->LoopLabelStackTop > 0);
3339 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
3340 }
3341 else {
3342 /* exit loop: pop LoopMask */
3343 assert(mach->LoopStackTop > 0);
3344 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
3345 /* pop ContMask */
3346 assert(mach->ContStackTop > 0);
3347 mach->ContMask = mach->ContStack[--mach->ContStackTop];
3348 assert(mach->LoopLabelStackTop > 0);
3349 --mach->LoopLabelStackTop;
3350
3351 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3352 }
3353 UPDATE_EXEC_MASK(mach);
3354 break;
3355
3356 case TGSI_OPCODE_BRK:
3357 exec_break(mach);
3358 break;
3359
3360 case TGSI_OPCODE_CONT:
3361 /* turn off cont channels for each enabled exec channel */
3362 mach->ContMask &= ~mach->ExecMask;
3363 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3364 UPDATE_EXEC_MASK(mach);
3365 break;
3366
3367 case TGSI_OPCODE_BGNSUB:
3368 /* no-op */
3369 break;
3370
3371 case TGSI_OPCODE_ENDSUB:
3372 /*
3373 * XXX: This really should be a no-op. We should never reach this opcode.
3374 */
3375
3376 assert(mach->CallStackTop > 0);
3377 mach->CallStackTop--;
3378
3379 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3380 mach->CondMask = mach->CondStack[mach->CondStackTop];
3381
3382 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3383 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3384
3385 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3386 mach->ContMask = mach->ContStack[mach->ContStackTop];
3387
3388 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3389 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3390
3391 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3392 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3393
3394 assert(mach->FuncStackTop > 0);
3395 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3396
3397 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3398
3399 UPDATE_EXEC_MASK(mach);
3400 break;
3401
3402 case TGSI_OPCODE_NOP:
3403 break;
3404
3405 case TGSI_OPCODE_BREAKC:
3406 FETCH(&r[0], 0, CHAN_X);
3407 /* update CondMask */
3408 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
3409 mach->LoopMask &= ~0x1;
3410 }
3411 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
3412 mach->LoopMask &= ~0x2;
3413 }
3414 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
3415 mach->LoopMask &= ~0x4;
3416 }
3417 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
3418 mach->LoopMask &= ~0x8;
3419 }
3420 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3421 UPDATE_EXEC_MASK(mach);
3422 break;
3423
3424 case TGSI_OPCODE_F2I:
3425 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3426 break;
3427
3428 case TGSI_OPCODE_IDIV:
3429 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3430 break;
3431
3432 case TGSI_OPCODE_IMAX:
3433 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3434 break;
3435
3436 case TGSI_OPCODE_IMIN:
3437 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3438 break;
3439
3440 case TGSI_OPCODE_INEG:
3441 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3442 break;
3443
3444 case TGSI_OPCODE_ISGE:
3445 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3446 break;
3447
3448 case TGSI_OPCODE_ISHR:
3449 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3450 break;
3451
3452 case TGSI_OPCODE_ISLT:
3453 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3454 break;
3455
3456 case TGSI_OPCODE_F2U:
3457 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3458 break;
3459
3460 case TGSI_OPCODE_U2F:
3461 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
3462 break;
3463
3464 case TGSI_OPCODE_UADD:
3465 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3466 break;
3467
3468 case TGSI_OPCODE_UDIV:
3469 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3470 break;
3471
3472 case TGSI_OPCODE_UMAD:
3473 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3474 break;
3475
3476 case TGSI_OPCODE_UMAX:
3477 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3478 break;
3479
3480 case TGSI_OPCODE_UMIN:
3481 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3482 break;
3483
3484 case TGSI_OPCODE_UMOD:
3485 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3486 break;
3487
3488 case TGSI_OPCODE_UMUL:
3489 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3490 break;
3491
3492 case TGSI_OPCODE_USEQ:
3493 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3494 break;
3495
3496 case TGSI_OPCODE_USGE:
3497 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3498 break;
3499
3500 case TGSI_OPCODE_USHR:
3501 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3502 break;
3503
3504 case TGSI_OPCODE_USLT:
3505 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3506 break;
3507
3508 case TGSI_OPCODE_USNE:
3509 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3510 break;
3511
3512 case TGSI_OPCODE_SWITCH:
3513 exec_switch(mach, inst);
3514 break;
3515
3516 case TGSI_OPCODE_CASE:
3517 exec_case(mach, inst);
3518 break;
3519
3520 case TGSI_OPCODE_DEFAULT:
3521 exec_default(mach);
3522 break;
3523
3524 case TGSI_OPCODE_ENDSWITCH:
3525 exec_endswitch(mach);
3526 break;
3527
3528 default:
3529 assert( 0 );
3530 }
3531 }
3532
3533
3534 #define DEBUG_EXECUTION 0
3535
3536
3537 /**
3538 * Run TGSI interpreter.
3539 * \return bitmask of "alive" quad components
3540 */
3541 uint
3542 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
3543 {
3544 uint i;
3545 int pc = 0;
3546
3547 mach->CondMask = 0xf;
3548 mach->LoopMask = 0xf;
3549 mach->ContMask = 0xf;
3550 mach->FuncMask = 0xf;
3551 mach->ExecMask = 0xf;
3552
3553 mach->Switch.mask = 0xf;
3554
3555 assert(mach->CondStackTop == 0);
3556 assert(mach->LoopStackTop == 0);
3557 assert(mach->ContStackTop == 0);
3558 assert(mach->SwitchStackTop == 0);
3559 assert(mach->BreakStackTop == 0);
3560 assert(mach->CallStackTop == 0);
3561
3562 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
3563 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
3564
3565 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
3566 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
3567 mach->Primitives[0] = 0;
3568 }
3569
3570 for (i = 0; i < QUAD_SIZE; i++) {
3571 mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C].u[i] =
3572 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_X_SHIFT) |
3573 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Y_SHIFT) |
3574 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Z_SHIFT) |
3575 (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_W_SHIFT);
3576 }
3577
3578 /* execute declarations (interpolants) */
3579 for (i = 0; i < mach->NumDeclarations; i++) {
3580 exec_declaration( mach, mach->Declarations+i );
3581 }
3582
3583 {
3584 #if DEBUG_EXECUTION
3585 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
3586 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
3587 uint inst = 1;
3588
3589 memcpy(temps, mach->Temps, sizeof(temps));
3590 memcpy(outputs, mach->Outputs, sizeof(outputs));
3591 #endif
3592
3593 /* execute instructions, until pc is set to -1 */
3594 while (pc != -1) {
3595
3596 #if DEBUG_EXECUTION
3597 uint i;
3598
3599 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
3600 #endif
3601
3602 assert(pc < (int) mach->NumInstructions);
3603 exec_instruction(mach, mach->Instructions + pc, &pc);
3604
3605 #if DEBUG_EXECUTION
3606 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
3607 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
3608 uint j;
3609
3610 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
3611 debug_printf("TEMP[%2u] = ", i);
3612 for (j = 0; j < 4; j++) {
3613 if (j > 0) {
3614 debug_printf(" ");
3615 }
3616 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3617 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
3618 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
3619 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
3620 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
3621 }
3622 }
3623 }
3624 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
3625 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
3626 uint j;
3627
3628 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
3629 debug_printf("OUT[%2u] = ", i);
3630 for (j = 0; j < 4; j++) {
3631 if (j > 0) {
3632 debug_printf(" ");
3633 }
3634 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3635 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
3636 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
3637 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
3638 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
3639 }
3640 }
3641 }
3642 #endif
3643 }
3644 }
3645
3646 #if 0
3647 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
3648 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
3649 /*
3650 * Scale back depth component.
3651 */
3652 for (i = 0; i < 4; i++)
3653 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
3654 }
3655 #endif
3656
3657 assert(mach->CondStackTop == 0);
3658 assert(mach->LoopStackTop == 0);
3659 assert(mach->ContStackTop == 0);
3660 assert(mach->SwitchStackTop == 0);
3661 assert(mach->BreakStackTop == 0);
3662 assert(mach->CallStackTop == 0);
3663
3664 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3665 }