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gallium: Add support for 32x32 muls with 64 bit results
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define DEBUG_EXECUTION 0
66
67
68 #define FAST_MATH 0
69
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
74
75 static void
76 micro_abs(union tgsi_exec_channel *dst,
77 const union tgsi_exec_channel *src)
78 {
79 dst->f[0] = fabsf(src->f[0]);
80 dst->f[1] = fabsf(src->f[1]);
81 dst->f[2] = fabsf(src->f[2]);
82 dst->f[3] = fabsf(src->f[3]);
83 }
84
85 static void
86 micro_arl(union tgsi_exec_channel *dst,
87 const union tgsi_exec_channel *src)
88 {
89 dst->i[0] = (int)floorf(src->f[0]);
90 dst->i[1] = (int)floorf(src->f[1]);
91 dst->i[2] = (int)floorf(src->f[2]);
92 dst->i[3] = (int)floorf(src->f[3]);
93 }
94
95 static void
96 micro_arr(union tgsi_exec_channel *dst,
97 const union tgsi_exec_channel *src)
98 {
99 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
100 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
101 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
102 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
103 }
104
105 static void
106 micro_ceil(union tgsi_exec_channel *dst,
107 const union tgsi_exec_channel *src)
108 {
109 dst->f[0] = ceilf(src->f[0]);
110 dst->f[1] = ceilf(src->f[1]);
111 dst->f[2] = ceilf(src->f[2]);
112 dst->f[3] = ceilf(src->f[3]);
113 }
114
115 static void
116 micro_clamp(union tgsi_exec_channel *dst,
117 const union tgsi_exec_channel *src0,
118 const union tgsi_exec_channel *src1,
119 const union tgsi_exec_channel *src2)
120 {
121 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
122 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
123 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
124 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
125 }
126
127 static void
128 micro_cmp(union tgsi_exec_channel *dst,
129 const union tgsi_exec_channel *src0,
130 const union tgsi_exec_channel *src1,
131 const union tgsi_exec_channel *src2)
132 {
133 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
134 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
135 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
136 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
137 }
138
139 static void
140 micro_cnd(union tgsi_exec_channel *dst,
141 const union tgsi_exec_channel *src0,
142 const union tgsi_exec_channel *src1,
143 const union tgsi_exec_channel *src2)
144 {
145 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
146 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
147 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
148 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
149 }
150
151 static void
152 micro_cos(union tgsi_exec_channel *dst,
153 const union tgsi_exec_channel *src)
154 {
155 dst->f[0] = cosf(src->f[0]);
156 dst->f[1] = cosf(src->f[1]);
157 dst->f[2] = cosf(src->f[2]);
158 dst->f[3] = cosf(src->f[3]);
159 }
160
161 static void
162 micro_ddx(union tgsi_exec_channel *dst,
163 const union tgsi_exec_channel *src)
164 {
165 dst->f[0] =
166 dst->f[1] =
167 dst->f[2] =
168 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
169 }
170
171 static void
172 micro_ddy(union tgsi_exec_channel *dst,
173 const union tgsi_exec_channel *src)
174 {
175 dst->f[0] =
176 dst->f[1] =
177 dst->f[2] =
178 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
179 }
180
181 static void
182 micro_exp2(union tgsi_exec_channel *dst,
183 const union tgsi_exec_channel *src)
184 {
185 #if FAST_MATH
186 dst->f[0] = util_fast_exp2(src->f[0]);
187 dst->f[1] = util_fast_exp2(src->f[1]);
188 dst->f[2] = util_fast_exp2(src->f[2]);
189 dst->f[3] = util_fast_exp2(src->f[3]);
190 #else
191 #if DEBUG
192 /* Inf is okay for this instruction, so clamp it to silence assertions. */
193 uint i;
194 union tgsi_exec_channel clamped;
195
196 for (i = 0; i < 4; i++) {
197 if (src->f[i] > 127.99999f) {
198 clamped.f[i] = 127.99999f;
199 } else if (src->f[i] < -126.99999f) {
200 clamped.f[i] = -126.99999f;
201 } else {
202 clamped.f[i] = src->f[i];
203 }
204 }
205 src = &clamped;
206 #endif /* DEBUG */
207
208 dst->f[0] = powf(2.0f, src->f[0]);
209 dst->f[1] = powf(2.0f, src->f[1]);
210 dst->f[2] = powf(2.0f, src->f[2]);
211 dst->f[3] = powf(2.0f, src->f[3]);
212 #endif /* FAST_MATH */
213 }
214
215 static void
216 micro_flr(union tgsi_exec_channel *dst,
217 const union tgsi_exec_channel *src)
218 {
219 dst->f[0] = floorf(src->f[0]);
220 dst->f[1] = floorf(src->f[1]);
221 dst->f[2] = floorf(src->f[2]);
222 dst->f[3] = floorf(src->f[3]);
223 }
224
225 static void
226 micro_frc(union tgsi_exec_channel *dst,
227 const union tgsi_exec_channel *src)
228 {
229 dst->f[0] = src->f[0] - floorf(src->f[0]);
230 dst->f[1] = src->f[1] - floorf(src->f[1]);
231 dst->f[2] = src->f[2] - floorf(src->f[2]);
232 dst->f[3] = src->f[3] - floorf(src->f[3]);
233 }
234
235 static void
236 micro_iabs(union tgsi_exec_channel *dst,
237 const union tgsi_exec_channel *src)
238 {
239 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
240 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
241 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
242 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
243 }
244
245 static void
246 micro_ineg(union tgsi_exec_channel *dst,
247 const union tgsi_exec_channel *src)
248 {
249 dst->i[0] = -src->i[0];
250 dst->i[1] = -src->i[1];
251 dst->i[2] = -src->i[2];
252 dst->i[3] = -src->i[3];
253 }
254
255 static void
256 micro_lg2(union tgsi_exec_channel *dst,
257 const union tgsi_exec_channel *src)
258 {
259 #if FAST_MATH
260 dst->f[0] = util_fast_log2(src->f[0]);
261 dst->f[1] = util_fast_log2(src->f[1]);
262 dst->f[2] = util_fast_log2(src->f[2]);
263 dst->f[3] = util_fast_log2(src->f[3]);
264 #else
265 dst->f[0] = logf(src->f[0]) * 1.442695f;
266 dst->f[1] = logf(src->f[1]) * 1.442695f;
267 dst->f[2] = logf(src->f[2]) * 1.442695f;
268 dst->f[3] = logf(src->f[3]) * 1.442695f;
269 #endif
270 }
271
272 static void
273 micro_lrp(union tgsi_exec_channel *dst,
274 const union tgsi_exec_channel *src0,
275 const union tgsi_exec_channel *src1,
276 const union tgsi_exec_channel *src2)
277 {
278 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
279 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
280 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
281 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
282 }
283
284 static void
285 micro_mad(union tgsi_exec_channel *dst,
286 const union tgsi_exec_channel *src0,
287 const union tgsi_exec_channel *src1,
288 const union tgsi_exec_channel *src2)
289 {
290 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
291 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
292 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
293 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
294 }
295
296 static void
297 micro_mov(union tgsi_exec_channel *dst,
298 const union tgsi_exec_channel *src)
299 {
300 dst->u[0] = src->u[0];
301 dst->u[1] = src->u[1];
302 dst->u[2] = src->u[2];
303 dst->u[3] = src->u[3];
304 }
305
306 static void
307 micro_rcp(union tgsi_exec_channel *dst,
308 const union tgsi_exec_channel *src)
309 {
310 #if 0 /* for debugging */
311 assert(src->f[0] != 0.0f);
312 assert(src->f[1] != 0.0f);
313 assert(src->f[2] != 0.0f);
314 assert(src->f[3] != 0.0f);
315 #endif
316 dst->f[0] = 1.0f / src->f[0];
317 dst->f[1] = 1.0f / src->f[1];
318 dst->f[2] = 1.0f / src->f[2];
319 dst->f[3] = 1.0f / src->f[3];
320 }
321
322 static void
323 micro_rnd(union tgsi_exec_channel *dst,
324 const union tgsi_exec_channel *src)
325 {
326 dst->f[0] = floorf(src->f[0] + 0.5f);
327 dst->f[1] = floorf(src->f[1] + 0.5f);
328 dst->f[2] = floorf(src->f[2] + 0.5f);
329 dst->f[3] = floorf(src->f[3] + 0.5f);
330 }
331
332 static void
333 micro_rsq(union tgsi_exec_channel *dst,
334 const union tgsi_exec_channel *src)
335 {
336 #if 0 /* for debugging */
337 assert(src->f[0] != 0.0f);
338 assert(src->f[1] != 0.0f);
339 assert(src->f[2] != 0.0f);
340 assert(src->f[3] != 0.0f);
341 #endif
342 dst->f[0] = 1.0f / sqrtf(src->f[0]);
343 dst->f[1] = 1.0f / sqrtf(src->f[1]);
344 dst->f[2] = 1.0f / sqrtf(src->f[2]);
345 dst->f[3] = 1.0f / sqrtf(src->f[3]);
346 }
347
348 static void
349 micro_sqrt(union tgsi_exec_channel *dst,
350 const union tgsi_exec_channel *src)
351 {
352 dst->f[0] = sqrtf(src->f[0]);
353 dst->f[1] = sqrtf(src->f[1]);
354 dst->f[2] = sqrtf(src->f[2]);
355 dst->f[3] = sqrtf(src->f[3]);
356 }
357
358 static void
359 micro_seq(union tgsi_exec_channel *dst,
360 const union tgsi_exec_channel *src0,
361 const union tgsi_exec_channel *src1)
362 {
363 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
364 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
365 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
366 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
367 }
368
369 static void
370 micro_sge(union tgsi_exec_channel *dst,
371 const union tgsi_exec_channel *src0,
372 const union tgsi_exec_channel *src1)
373 {
374 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
375 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
376 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
377 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
378 }
379
380 static void
381 micro_sgn(union tgsi_exec_channel *dst,
382 const union tgsi_exec_channel *src)
383 {
384 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
385 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
386 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
387 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
388 }
389
390 static void
391 micro_isgn(union tgsi_exec_channel *dst,
392 const union tgsi_exec_channel *src)
393 {
394 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
395 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
396 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
397 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
398 }
399
400 static void
401 micro_sgt(union tgsi_exec_channel *dst,
402 const union tgsi_exec_channel *src0,
403 const union tgsi_exec_channel *src1)
404 {
405 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
406 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
407 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
408 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
409 }
410
411 static void
412 micro_sin(union tgsi_exec_channel *dst,
413 const union tgsi_exec_channel *src)
414 {
415 dst->f[0] = sinf(src->f[0]);
416 dst->f[1] = sinf(src->f[1]);
417 dst->f[2] = sinf(src->f[2]);
418 dst->f[3] = sinf(src->f[3]);
419 }
420
421 static void
422 micro_sle(union tgsi_exec_channel *dst,
423 const union tgsi_exec_channel *src0,
424 const union tgsi_exec_channel *src1)
425 {
426 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
427 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
428 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
429 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
430 }
431
432 static void
433 micro_slt(union tgsi_exec_channel *dst,
434 const union tgsi_exec_channel *src0,
435 const union tgsi_exec_channel *src1)
436 {
437 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
438 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
439 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
440 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
441 }
442
443 static void
444 micro_sne(union tgsi_exec_channel *dst,
445 const union tgsi_exec_channel *src0,
446 const union tgsi_exec_channel *src1)
447 {
448 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
449 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
450 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
451 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
452 }
453
454 static void
455 micro_sfl(union tgsi_exec_channel *dst)
456 {
457 dst->f[0] = 0.0f;
458 dst->f[1] = 0.0f;
459 dst->f[2] = 0.0f;
460 dst->f[3] = 0.0f;
461 }
462
463 static void
464 micro_str(union tgsi_exec_channel *dst)
465 {
466 dst->f[0] = 1.0f;
467 dst->f[1] = 1.0f;
468 dst->f[2] = 1.0f;
469 dst->f[3] = 1.0f;
470 }
471
472 static void
473 micro_trunc(union tgsi_exec_channel *dst,
474 const union tgsi_exec_channel *src)
475 {
476 dst->f[0] = (float)(int)src->f[0];
477 dst->f[1] = (float)(int)src->f[1];
478 dst->f[2] = (float)(int)src->f[2];
479 dst->f[3] = (float)(int)src->f[3];
480 }
481
482
483 enum tgsi_exec_datatype {
484 TGSI_EXEC_DATA_FLOAT,
485 TGSI_EXEC_DATA_INT,
486 TGSI_EXEC_DATA_UINT
487 };
488
489 /*
490 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
491 */
492 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
493 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
494 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
495 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
496 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
497 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
498
499
500 /** The execution mask depends on the conditional mask and the loop mask */
501 #define UPDATE_EXEC_MASK(MACH) \
502 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
503
504
505 static const union tgsi_exec_channel ZeroVec =
506 { { 0.0, 0.0, 0.0, 0.0 } };
507
508 static const union tgsi_exec_channel OneVec = {
509 {1.0f, 1.0f, 1.0f, 1.0f}
510 };
511
512 static const union tgsi_exec_channel P128Vec = {
513 {128.0f, 128.0f, 128.0f, 128.0f}
514 };
515
516 static const union tgsi_exec_channel M128Vec = {
517 {-128.0f, -128.0f, -128.0f, -128.0f}
518 };
519
520
521 /**
522 * Assert that none of the float values in 'chan' are infinite or NaN.
523 * NaN and Inf may occur normally during program execution and should
524 * not lead to crashes, etc. But when debugging, it's helpful to catch
525 * them.
526 */
527 static INLINE void
528 check_inf_or_nan(const union tgsi_exec_channel *chan)
529 {
530 assert(!util_is_inf_or_nan((chan)->f[0]));
531 assert(!util_is_inf_or_nan((chan)->f[1]));
532 assert(!util_is_inf_or_nan((chan)->f[2]));
533 assert(!util_is_inf_or_nan((chan)->f[3]));
534 }
535
536
537 #ifdef DEBUG
538 static void
539 print_chan(const char *msg, const union tgsi_exec_channel *chan)
540 {
541 debug_printf("%s = {%f, %f, %f, %f}\n",
542 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
543 }
544 #endif
545
546
547 #ifdef DEBUG
548 static void
549 print_temp(const struct tgsi_exec_machine *mach, uint index)
550 {
551 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
552 int i;
553 debug_printf("Temp[%u] =\n", index);
554 for (i = 0; i < 4; i++) {
555 debug_printf(" %c: { %f, %f, %f, %f }\n",
556 "XYZW"[i],
557 tmp->xyzw[i].f[0],
558 tmp->xyzw[i].f[1],
559 tmp->xyzw[i].f[2],
560 tmp->xyzw[i].f[3]);
561 }
562 }
563 #endif
564
565
566 void
567 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
568 unsigned num_bufs,
569 const void **bufs,
570 const unsigned *buf_sizes)
571 {
572 unsigned i;
573
574 for (i = 0; i < num_bufs; i++) {
575 mach->Consts[i] = bufs[i];
576 mach->ConstsSize[i] = buf_sizes[i];
577 }
578 }
579
580
581 /**
582 * Check if there's a potential src/dst register data dependency when
583 * using SOA execution.
584 * Example:
585 * MOV T, T.yxwz;
586 * This would expand into:
587 * MOV t0, t1;
588 * MOV t1, t0;
589 * MOV t2, t3;
590 * MOV t3, t2;
591 * The second instruction will have the wrong value for t0 if executed as-is.
592 */
593 boolean
594 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
595 {
596 uint i, chan;
597
598 uint writemask = inst->Dst[0].Register.WriteMask;
599 if (writemask == TGSI_WRITEMASK_X ||
600 writemask == TGSI_WRITEMASK_Y ||
601 writemask == TGSI_WRITEMASK_Z ||
602 writemask == TGSI_WRITEMASK_W ||
603 writemask == TGSI_WRITEMASK_NONE) {
604 /* no chance of data dependency */
605 return FALSE;
606 }
607
608 /* loop over src regs */
609 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
610 if ((inst->Src[i].Register.File ==
611 inst->Dst[0].Register.File) &&
612 ((inst->Src[i].Register.Index ==
613 inst->Dst[0].Register.Index) ||
614 inst->Src[i].Register.Indirect ||
615 inst->Dst[0].Register.Indirect)) {
616 /* loop over dest channels */
617 uint channelsWritten = 0x0;
618 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
619 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
620 /* check if we're reading a channel that's been written */
621 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
622 if (channelsWritten & (1 << swizzle)) {
623 return TRUE;
624 }
625
626 channelsWritten |= (1 << chan);
627 }
628 }
629 }
630 }
631 return FALSE;
632 }
633
634
635 /**
636 * Initialize machine state by expanding tokens to full instructions,
637 * allocating temporary storage, setting up constants, etc.
638 * After this, we can call tgsi_exec_machine_run() many times.
639 */
640 void
641 tgsi_exec_machine_bind_shader(
642 struct tgsi_exec_machine *mach,
643 const struct tgsi_token *tokens,
644 struct tgsi_sampler *sampler)
645 {
646 uint k;
647 struct tgsi_parse_context parse;
648 struct tgsi_full_instruction *instructions;
649 struct tgsi_full_declaration *declarations;
650 uint maxInstructions = 10, numInstructions = 0;
651 uint maxDeclarations = 10, numDeclarations = 0;
652
653 #if 0
654 tgsi_dump(tokens, 0);
655 #endif
656
657 util_init_math();
658
659
660 mach->Tokens = tokens;
661 mach->Sampler = sampler;
662
663 if (!tokens) {
664 /* unbind and free all */
665 FREE(mach->Declarations);
666 mach->Declarations = NULL;
667 mach->NumDeclarations = 0;
668
669 FREE(mach->Instructions);
670 mach->Instructions = NULL;
671 mach->NumInstructions = 0;
672
673 return;
674 }
675
676 k = tgsi_parse_init (&parse, mach->Tokens);
677 if (k != TGSI_PARSE_OK) {
678 debug_printf( "Problem parsing!\n" );
679 return;
680 }
681
682 mach->Processor = parse.FullHeader.Processor.Processor;
683 mach->ImmLimit = 0;
684 mach->NumOutputs = 0;
685
686 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
687 !mach->UsedGeometryShader) {
688 struct tgsi_exec_vector *inputs;
689 struct tgsi_exec_vector *outputs;
690
691 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
692 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS,
693 16);
694
695 if (!inputs)
696 return;
697
698 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
699 TGSI_MAX_TOTAL_VERTICES, 16);
700
701 if (!outputs) {
702 align_free(inputs);
703 return;
704 }
705
706 align_free(mach->Inputs);
707 align_free(mach->Outputs);
708
709 mach->Inputs = inputs;
710 mach->Outputs = outputs;
711 mach->UsedGeometryShader = TRUE;
712 }
713
714 declarations = (struct tgsi_full_declaration *)
715 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
716
717 if (!declarations) {
718 return;
719 }
720
721 instructions = (struct tgsi_full_instruction *)
722 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
723
724 if (!instructions) {
725 FREE( declarations );
726 return;
727 }
728
729 while( !tgsi_parse_end_of_tokens( &parse ) ) {
730 uint i;
731
732 tgsi_parse_token( &parse );
733 switch( parse.FullToken.Token.Type ) {
734 case TGSI_TOKEN_TYPE_DECLARATION:
735 /* save expanded declaration */
736 if (numDeclarations == maxDeclarations) {
737 declarations = REALLOC(declarations,
738 maxDeclarations
739 * sizeof(struct tgsi_full_declaration),
740 (maxDeclarations + 10)
741 * sizeof(struct tgsi_full_declaration));
742 maxDeclarations += 10;
743 }
744 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
745 unsigned reg;
746 for (reg = parse.FullToken.FullDeclaration.Range.First;
747 reg <= parse.FullToken.FullDeclaration.Range.Last;
748 ++reg) {
749 ++mach->NumOutputs;
750 }
751 }
752 memcpy(declarations + numDeclarations,
753 &parse.FullToken.FullDeclaration,
754 sizeof(declarations[0]));
755 numDeclarations++;
756 break;
757
758 case TGSI_TOKEN_TYPE_IMMEDIATE:
759 {
760 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
761 assert( size <= 4 );
762 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
763
764 for( i = 0; i < size; i++ ) {
765 mach->Imms[mach->ImmLimit][i] =
766 parse.FullToken.FullImmediate.u[i].Float;
767 }
768 mach->ImmLimit += 1;
769 }
770 break;
771
772 case TGSI_TOKEN_TYPE_INSTRUCTION:
773
774 /* save expanded instruction */
775 if (numInstructions == maxInstructions) {
776 instructions = REALLOC(instructions,
777 maxInstructions
778 * sizeof(struct tgsi_full_instruction),
779 (maxInstructions + 10)
780 * sizeof(struct tgsi_full_instruction));
781 maxInstructions += 10;
782 }
783
784 memcpy(instructions + numInstructions,
785 &parse.FullToken.FullInstruction,
786 sizeof(instructions[0]));
787
788 numInstructions++;
789 break;
790
791 case TGSI_TOKEN_TYPE_PROPERTY:
792 break;
793
794 default:
795 assert( 0 );
796 }
797 }
798 tgsi_parse_free (&parse);
799
800 FREE(mach->Declarations);
801 mach->Declarations = declarations;
802 mach->NumDeclarations = numDeclarations;
803
804 FREE(mach->Instructions);
805 mach->Instructions = instructions;
806 mach->NumInstructions = numInstructions;
807 }
808
809
810 struct tgsi_exec_machine *
811 tgsi_exec_machine_create( void )
812 {
813 struct tgsi_exec_machine *mach;
814 uint i;
815
816 mach = align_malloc( sizeof *mach, 16 );
817 if (!mach)
818 goto fail;
819
820 memset(mach, 0, sizeof(*mach));
821
822 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
823 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
824 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
825
826 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
827 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
828 if (!mach->Inputs || !mach->Outputs)
829 goto fail;
830
831 /* Setup constants needed by the SSE2 executor. */
832 for( i = 0; i < 4; i++ ) {
833 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
834 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
835 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
836 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
837 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
838 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
839 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
840 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
841 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
842 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
843 }
844
845 #ifdef DEBUG
846 /* silence warnings */
847 (void) print_chan;
848 (void) print_temp;
849 #endif
850
851 return mach;
852
853 fail:
854 if (mach) {
855 align_free(mach->Inputs);
856 align_free(mach->Outputs);
857 align_free(mach);
858 }
859 return NULL;
860 }
861
862
863 void
864 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
865 {
866 if (mach) {
867 FREE(mach->Instructions);
868 FREE(mach->Declarations);
869
870 align_free(mach->Inputs);
871 align_free(mach->Outputs);
872
873 align_free(mach);
874 }
875 }
876
877 static void
878 micro_add(union tgsi_exec_channel *dst,
879 const union tgsi_exec_channel *src0,
880 const union tgsi_exec_channel *src1)
881 {
882 dst->f[0] = src0->f[0] + src1->f[0];
883 dst->f[1] = src0->f[1] + src1->f[1];
884 dst->f[2] = src0->f[2] + src1->f[2];
885 dst->f[3] = src0->f[3] + src1->f[3];
886 }
887
888 static void
889 micro_div(
890 union tgsi_exec_channel *dst,
891 const union tgsi_exec_channel *src0,
892 const union tgsi_exec_channel *src1 )
893 {
894 if (src1->f[0] != 0) {
895 dst->f[0] = src0->f[0] / src1->f[0];
896 }
897 if (src1->f[1] != 0) {
898 dst->f[1] = src0->f[1] / src1->f[1];
899 }
900 if (src1->f[2] != 0) {
901 dst->f[2] = src0->f[2] / src1->f[2];
902 }
903 if (src1->f[3] != 0) {
904 dst->f[3] = src0->f[3] / src1->f[3];
905 }
906 }
907
908 static void
909 micro_rcc(union tgsi_exec_channel *dst,
910 const union tgsi_exec_channel *src)
911 {
912 uint i;
913
914 for (i = 0; i < 4; i++) {
915 float recip = 1.0f / src->f[i];
916
917 if (recip > 0.0f) {
918 if (recip > 1.884467e+019f) {
919 dst->f[i] = 1.884467e+019f;
920 }
921 else if (recip < 5.42101e-020f) {
922 dst->f[i] = 5.42101e-020f;
923 }
924 else {
925 dst->f[i] = recip;
926 }
927 }
928 else {
929 if (recip < -1.884467e+019f) {
930 dst->f[i] = -1.884467e+019f;
931 }
932 else if (recip > -5.42101e-020f) {
933 dst->f[i] = -5.42101e-020f;
934 }
935 else {
936 dst->f[i] = recip;
937 }
938 }
939 }
940 }
941
942 static void
943 micro_lt(
944 union tgsi_exec_channel *dst,
945 const union tgsi_exec_channel *src0,
946 const union tgsi_exec_channel *src1,
947 const union tgsi_exec_channel *src2,
948 const union tgsi_exec_channel *src3 )
949 {
950 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
951 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
952 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
953 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
954 }
955
956 static void
957 micro_max(union tgsi_exec_channel *dst,
958 const union tgsi_exec_channel *src0,
959 const union tgsi_exec_channel *src1)
960 {
961 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
962 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
963 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
964 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
965 }
966
967 static void
968 micro_min(union tgsi_exec_channel *dst,
969 const union tgsi_exec_channel *src0,
970 const union tgsi_exec_channel *src1)
971 {
972 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
973 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
974 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
975 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
976 }
977
978 static void
979 micro_mul(union tgsi_exec_channel *dst,
980 const union tgsi_exec_channel *src0,
981 const union tgsi_exec_channel *src1)
982 {
983 dst->f[0] = src0->f[0] * src1->f[0];
984 dst->f[1] = src0->f[1] * src1->f[1];
985 dst->f[2] = src0->f[2] * src1->f[2];
986 dst->f[3] = src0->f[3] * src1->f[3];
987 }
988
989 static void
990 micro_neg(
991 union tgsi_exec_channel *dst,
992 const union tgsi_exec_channel *src )
993 {
994 dst->f[0] = -src->f[0];
995 dst->f[1] = -src->f[1];
996 dst->f[2] = -src->f[2];
997 dst->f[3] = -src->f[3];
998 }
999
1000 static void
1001 micro_pow(
1002 union tgsi_exec_channel *dst,
1003 const union tgsi_exec_channel *src0,
1004 const union tgsi_exec_channel *src1 )
1005 {
1006 #if FAST_MATH
1007 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1008 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1009 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1010 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1011 #else
1012 dst->f[0] = powf( src0->f[0], src1->f[0] );
1013 dst->f[1] = powf( src0->f[1], src1->f[1] );
1014 dst->f[2] = powf( src0->f[2], src1->f[2] );
1015 dst->f[3] = powf( src0->f[3], src1->f[3] );
1016 #endif
1017 }
1018
1019 static void
1020 micro_sub(union tgsi_exec_channel *dst,
1021 const union tgsi_exec_channel *src0,
1022 const union tgsi_exec_channel *src1)
1023 {
1024 dst->f[0] = src0->f[0] - src1->f[0];
1025 dst->f[1] = src0->f[1] - src1->f[1];
1026 dst->f[2] = src0->f[2] - src1->f[2];
1027 dst->f[3] = src0->f[3] - src1->f[3];
1028 }
1029
1030 static void
1031 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1032 const uint chan_index,
1033 const uint file,
1034 const uint swizzle,
1035 const union tgsi_exec_channel *index,
1036 const union tgsi_exec_channel *index2D,
1037 union tgsi_exec_channel *chan)
1038 {
1039 uint i;
1040
1041 assert(swizzle < 4);
1042
1043 switch (file) {
1044 case TGSI_FILE_CONSTANT:
1045 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1046 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1047 assert(mach->Consts[index2D->i[i]]);
1048
1049 if (index->i[i] < 0) {
1050 chan->u[i] = 0;
1051 } else {
1052 /* NOTE: copying the const value as a uint instead of float */
1053 const uint constbuf = index2D->i[i];
1054 const uint *buf = (const uint *)mach->Consts[constbuf];
1055 const int pos = index->i[i] * 4 + swizzle;
1056 /* const buffer bounds check */
1057 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1058 if (0) {
1059 /* Debug: print warning */
1060 static int count = 0;
1061 if (count++ < 100)
1062 debug_printf("TGSI Exec: const buffer index %d"
1063 " out of bounds\n", pos);
1064 }
1065 chan->u[i] = 0;
1066 }
1067 else
1068 chan->u[i] = buf[pos];
1069 }
1070 }
1071 break;
1072
1073 case TGSI_FILE_INPUT:
1074 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1075 /*
1076 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1077 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1078 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1079 index2D->i[i], index->i[i]);
1080 }*/
1081 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1082 assert(pos >= 0);
1083 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1084 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1085 }
1086 break;
1087
1088 case TGSI_FILE_SYSTEM_VALUE:
1089 /* XXX no swizzling at this point. Will be needed if we put
1090 * gl_FragCoord, for example, in a sys value register.
1091 */
1092 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1093 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1094 }
1095 break;
1096
1097 case TGSI_FILE_TEMPORARY:
1098 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1099 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1100 assert(index2D->i[i] == 0);
1101
1102 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1103 }
1104 break;
1105
1106 case TGSI_FILE_IMMEDIATE:
1107 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1108 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1109 assert(index2D->i[i] == 0);
1110
1111 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1112 }
1113 break;
1114
1115 case TGSI_FILE_ADDRESS:
1116 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1117 assert(index->i[i] >= 0);
1118 assert(index2D->i[i] == 0);
1119
1120 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1121 }
1122 break;
1123
1124 case TGSI_FILE_PREDICATE:
1125 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1126 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1127 assert(index2D->i[i] == 0);
1128
1129 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1130 }
1131 break;
1132
1133 case TGSI_FILE_OUTPUT:
1134 /* vertex/fragment output vars can be read too */
1135 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1136 assert(index->i[i] >= 0);
1137 assert(index2D->i[i] == 0);
1138
1139 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1140 }
1141 break;
1142
1143 default:
1144 assert(0);
1145 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1146 chan->u[i] = 0;
1147 }
1148 }
1149 }
1150
1151 static void
1152 fetch_source(const struct tgsi_exec_machine *mach,
1153 union tgsi_exec_channel *chan,
1154 const struct tgsi_full_src_register *reg,
1155 const uint chan_index,
1156 enum tgsi_exec_datatype src_datatype)
1157 {
1158 union tgsi_exec_channel index;
1159 union tgsi_exec_channel index2D;
1160 uint swizzle;
1161
1162 /* We start with a direct index into a register file.
1163 *
1164 * file[1],
1165 * where:
1166 * file = Register.File
1167 * [1] = Register.Index
1168 */
1169 index.i[0] =
1170 index.i[1] =
1171 index.i[2] =
1172 index.i[3] = reg->Register.Index;
1173
1174 /* There is an extra source register that indirectly subscripts
1175 * a register file. The direct index now becomes an offset
1176 * that is being added to the indirect register.
1177 *
1178 * file[ind[2].x+1],
1179 * where:
1180 * ind = Indirect.File
1181 * [2] = Indirect.Index
1182 * .x = Indirect.SwizzleX
1183 */
1184 if (reg->Register.Indirect) {
1185 union tgsi_exec_channel index2;
1186 union tgsi_exec_channel indir_index;
1187 const uint execmask = mach->ExecMask;
1188 uint i;
1189
1190 /* which address register (always zero now) */
1191 index2.i[0] =
1192 index2.i[1] =
1193 index2.i[2] =
1194 index2.i[3] = reg->Indirect.Index;
1195 /* get current value of address register[swizzle] */
1196 swizzle = reg->Indirect.Swizzle;
1197 fetch_src_file_channel(mach,
1198 chan_index,
1199 reg->Indirect.File,
1200 swizzle,
1201 &index2,
1202 &ZeroVec,
1203 &indir_index);
1204
1205 /* add value of address register to the offset */
1206 index.i[0] += indir_index.i[0];
1207 index.i[1] += indir_index.i[1];
1208 index.i[2] += indir_index.i[2];
1209 index.i[3] += indir_index.i[3];
1210
1211 /* for disabled execution channels, zero-out the index to
1212 * avoid using a potential garbage value.
1213 */
1214 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1215 if ((execmask & (1 << i)) == 0)
1216 index.i[i] = 0;
1217 }
1218 }
1219
1220 /* There is an extra source register that is a second
1221 * subscript to a register file. Effectively it means that
1222 * the register file is actually a 2D array of registers.
1223 *
1224 * file[3][1],
1225 * where:
1226 * [3] = Dimension.Index
1227 */
1228 if (reg->Register.Dimension) {
1229 index2D.i[0] =
1230 index2D.i[1] =
1231 index2D.i[2] =
1232 index2D.i[3] = reg->Dimension.Index;
1233
1234 /* Again, the second subscript index can be addressed indirectly
1235 * identically to the first one.
1236 * Nothing stops us from indirectly addressing the indirect register,
1237 * but there is no need for that, so we won't exercise it.
1238 *
1239 * file[ind[4].y+3][1],
1240 * where:
1241 * ind = DimIndirect.File
1242 * [4] = DimIndirect.Index
1243 * .y = DimIndirect.SwizzleX
1244 */
1245 if (reg->Dimension.Indirect) {
1246 union tgsi_exec_channel index2;
1247 union tgsi_exec_channel indir_index;
1248 const uint execmask = mach->ExecMask;
1249 uint i;
1250
1251 index2.i[0] =
1252 index2.i[1] =
1253 index2.i[2] =
1254 index2.i[3] = reg->DimIndirect.Index;
1255
1256 swizzle = reg->DimIndirect.Swizzle;
1257 fetch_src_file_channel(mach,
1258 chan_index,
1259 reg->DimIndirect.File,
1260 swizzle,
1261 &index2,
1262 &ZeroVec,
1263 &indir_index);
1264
1265 index2D.i[0] += indir_index.i[0];
1266 index2D.i[1] += indir_index.i[1];
1267 index2D.i[2] += indir_index.i[2];
1268 index2D.i[3] += indir_index.i[3];
1269
1270 /* for disabled execution channels, zero-out the index to
1271 * avoid using a potential garbage value.
1272 */
1273 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1274 if ((execmask & (1 << i)) == 0) {
1275 index2D.i[i] = 0;
1276 }
1277 }
1278 }
1279
1280 /* If by any chance there was a need for a 3D array of register
1281 * files, we would have to check whether Dimension is followed
1282 * by a dimension register and continue the saga.
1283 */
1284 } else {
1285 index2D.i[0] =
1286 index2D.i[1] =
1287 index2D.i[2] =
1288 index2D.i[3] = 0;
1289 }
1290
1291 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1292 fetch_src_file_channel(mach,
1293 chan_index,
1294 reg->Register.File,
1295 swizzle,
1296 &index,
1297 &index2D,
1298 chan);
1299
1300 if (reg->Register.Absolute) {
1301 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1302 micro_abs(chan, chan);
1303 } else {
1304 micro_iabs(chan, chan);
1305 }
1306 }
1307
1308 if (reg->Register.Negate) {
1309 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1310 micro_neg(chan, chan);
1311 } else {
1312 micro_ineg(chan, chan);
1313 }
1314 }
1315 }
1316
1317 static void
1318 store_dest(struct tgsi_exec_machine *mach,
1319 const union tgsi_exec_channel *chan,
1320 const struct tgsi_full_dst_register *reg,
1321 const struct tgsi_full_instruction *inst,
1322 uint chan_index,
1323 enum tgsi_exec_datatype dst_datatype)
1324 {
1325 uint i;
1326 union tgsi_exec_channel null;
1327 union tgsi_exec_channel *dst;
1328 union tgsi_exec_channel index2D;
1329 uint execmask = mach->ExecMask;
1330 int offset = 0; /* indirection offset */
1331 int index;
1332
1333 /* for debugging */
1334 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1335 check_inf_or_nan(chan);
1336 }
1337
1338 /* There is an extra source register that indirectly subscripts
1339 * a register file. The direct index now becomes an offset
1340 * that is being added to the indirect register.
1341 *
1342 * file[ind[2].x+1],
1343 * where:
1344 * ind = Indirect.File
1345 * [2] = Indirect.Index
1346 * .x = Indirect.SwizzleX
1347 */
1348 if (reg->Register.Indirect) {
1349 union tgsi_exec_channel index;
1350 union tgsi_exec_channel indir_index;
1351 uint swizzle;
1352
1353 /* which address register (always zero for now) */
1354 index.i[0] =
1355 index.i[1] =
1356 index.i[2] =
1357 index.i[3] = reg->Indirect.Index;
1358
1359 /* get current value of address register[swizzle] */
1360 swizzle = reg->Indirect.Swizzle;
1361
1362 /* fetch values from the address/indirection register */
1363 fetch_src_file_channel(mach,
1364 chan_index,
1365 reg->Indirect.File,
1366 swizzle,
1367 &index,
1368 &ZeroVec,
1369 &indir_index);
1370
1371 /* save indirection offset */
1372 offset = indir_index.i[0];
1373 }
1374
1375 /* There is an extra source register that is a second
1376 * subscript to a register file. Effectively it means that
1377 * the register file is actually a 2D array of registers.
1378 *
1379 * file[3][1],
1380 * where:
1381 * [3] = Dimension.Index
1382 */
1383 if (reg->Register.Dimension) {
1384 index2D.i[0] =
1385 index2D.i[1] =
1386 index2D.i[2] =
1387 index2D.i[3] = reg->Dimension.Index;
1388
1389 /* Again, the second subscript index can be addressed indirectly
1390 * identically to the first one.
1391 * Nothing stops us from indirectly addressing the indirect register,
1392 * but there is no need for that, so we won't exercise it.
1393 *
1394 * file[ind[4].y+3][1],
1395 * where:
1396 * ind = DimIndirect.File
1397 * [4] = DimIndirect.Index
1398 * .y = DimIndirect.SwizzleX
1399 */
1400 if (reg->Dimension.Indirect) {
1401 union tgsi_exec_channel index2;
1402 union tgsi_exec_channel indir_index;
1403 const uint execmask = mach->ExecMask;
1404 unsigned swizzle;
1405 uint i;
1406
1407 index2.i[0] =
1408 index2.i[1] =
1409 index2.i[2] =
1410 index2.i[3] = reg->DimIndirect.Index;
1411
1412 swizzle = reg->DimIndirect.Swizzle;
1413 fetch_src_file_channel(mach,
1414 chan_index,
1415 reg->DimIndirect.File,
1416 swizzle,
1417 &index2,
1418 &ZeroVec,
1419 &indir_index);
1420
1421 index2D.i[0] += indir_index.i[0];
1422 index2D.i[1] += indir_index.i[1];
1423 index2D.i[2] += indir_index.i[2];
1424 index2D.i[3] += indir_index.i[3];
1425
1426 /* for disabled execution channels, zero-out the index to
1427 * avoid using a potential garbage value.
1428 */
1429 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1430 if ((execmask & (1 << i)) == 0) {
1431 index2D.i[i] = 0;
1432 }
1433 }
1434 }
1435
1436 /* If by any chance there was a need for a 3D array of register
1437 * files, we would have to check whether Dimension is followed
1438 * by a dimension register and continue the saga.
1439 */
1440 } else {
1441 index2D.i[0] =
1442 index2D.i[1] =
1443 index2D.i[2] =
1444 index2D.i[3] = 0;
1445 }
1446
1447 switch (reg->Register.File) {
1448 case TGSI_FILE_NULL:
1449 dst = &null;
1450 break;
1451
1452 case TGSI_FILE_OUTPUT:
1453 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1454 + reg->Register.Index;
1455 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1456 #if 0
1457 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1458 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1459 reg->Register.Index);
1460 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1461 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1462 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1463 if (execmask & (1 << i))
1464 debug_printf("%f, ", chan->f[i]);
1465 debug_printf(")\n");
1466 }
1467 #endif
1468 break;
1469
1470 case TGSI_FILE_TEMPORARY:
1471 index = reg->Register.Index;
1472 assert( index < TGSI_EXEC_NUM_TEMPS );
1473 dst = &mach->Temps[offset + index].xyzw[chan_index];
1474 break;
1475
1476 case TGSI_FILE_ADDRESS:
1477 index = reg->Register.Index;
1478 dst = &mach->Addrs[index].xyzw[chan_index];
1479 break;
1480
1481 case TGSI_FILE_PREDICATE:
1482 index = reg->Register.Index;
1483 assert(index < TGSI_EXEC_NUM_PREDS);
1484 dst = &mach->Predicates[index].xyzw[chan_index];
1485 break;
1486
1487 default:
1488 assert( 0 );
1489 return;
1490 }
1491
1492 if (inst->Instruction.Predicate) {
1493 uint swizzle;
1494 union tgsi_exec_channel *pred;
1495
1496 switch (chan_index) {
1497 case TGSI_CHAN_X:
1498 swizzle = inst->Predicate.SwizzleX;
1499 break;
1500 case TGSI_CHAN_Y:
1501 swizzle = inst->Predicate.SwizzleY;
1502 break;
1503 case TGSI_CHAN_Z:
1504 swizzle = inst->Predicate.SwizzleZ;
1505 break;
1506 case TGSI_CHAN_W:
1507 swizzle = inst->Predicate.SwizzleW;
1508 break;
1509 default:
1510 assert(0);
1511 return;
1512 }
1513
1514 assert(inst->Predicate.Index == 0);
1515
1516 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1517
1518 if (inst->Predicate.Negate) {
1519 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1520 if (pred->u[i]) {
1521 execmask &= ~(1 << i);
1522 }
1523 }
1524 } else {
1525 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1526 if (!pred->u[i]) {
1527 execmask &= ~(1 << i);
1528 }
1529 }
1530 }
1531 }
1532
1533 switch (inst->Instruction.Saturate) {
1534 case TGSI_SAT_NONE:
1535 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1536 if (execmask & (1 << i))
1537 dst->i[i] = chan->i[i];
1538 break;
1539
1540 case TGSI_SAT_ZERO_ONE:
1541 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1542 if (execmask & (1 << i)) {
1543 if (chan->f[i] < 0.0f)
1544 dst->f[i] = 0.0f;
1545 else if (chan->f[i] > 1.0f)
1546 dst->f[i] = 1.0f;
1547 else
1548 dst->i[i] = chan->i[i];
1549 }
1550 break;
1551
1552 case TGSI_SAT_MINUS_PLUS_ONE:
1553 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1554 if (execmask & (1 << i)) {
1555 if (chan->f[i] < -1.0f)
1556 dst->f[i] = -1.0f;
1557 else if (chan->f[i] > 1.0f)
1558 dst->f[i] = 1.0f;
1559 else
1560 dst->i[i] = chan->i[i];
1561 }
1562 break;
1563
1564 default:
1565 assert( 0 );
1566 }
1567 }
1568
1569 #define FETCH(VAL,INDEX,CHAN)\
1570 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1571
1572 #define IFETCH(VAL,INDEX,CHAN)\
1573 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1574
1575
1576 /**
1577 * Execute ARB-style KIL which is predicated by a src register.
1578 * Kill fragment if any of the four values is less than zero.
1579 */
1580 static void
1581 exec_kill_if(struct tgsi_exec_machine *mach,
1582 const struct tgsi_full_instruction *inst)
1583 {
1584 uint uniquemask;
1585 uint chan_index;
1586 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1587 union tgsi_exec_channel r[1];
1588
1589 /* This mask stores component bits that were already tested. */
1590 uniquemask = 0;
1591
1592 for (chan_index = 0; chan_index < 4; chan_index++)
1593 {
1594 uint swizzle;
1595 uint i;
1596
1597 /* unswizzle channel */
1598 swizzle = tgsi_util_get_full_src_register_swizzle (
1599 &inst->Src[0],
1600 chan_index);
1601
1602 /* check if the component has not been already tested */
1603 if (uniquemask & (1 << swizzle))
1604 continue;
1605 uniquemask |= 1 << swizzle;
1606
1607 FETCH(&r[0], 0, chan_index);
1608 for (i = 0; i < 4; i++)
1609 if (r[0].f[i] < 0.0f)
1610 kilmask |= 1 << i;
1611 }
1612
1613 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1614 }
1615
1616 /**
1617 * Unconditional fragment kill/discard.
1618 */
1619 static void
1620 exec_kill(struct tgsi_exec_machine *mach,
1621 const struct tgsi_full_instruction *inst)
1622 {
1623 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1624
1625 /* kill fragment for all fragments currently executing */
1626 kilmask = mach->ExecMask;
1627 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1628 }
1629
1630 static void
1631 emit_vertex(struct tgsi_exec_machine *mach)
1632 {
1633 /* FIXME: check for exec mask correctly
1634 unsigned i;
1635 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1636 if ((mach->ExecMask & (1 << i)))
1637 */
1638 if (mach->ExecMask) {
1639 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1640 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1641 }
1642 }
1643
1644 static void
1645 emit_primitive(struct tgsi_exec_machine *mach)
1646 {
1647 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1648 /* FIXME: check for exec mask correctly
1649 unsigned i;
1650 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1651 if ((mach->ExecMask & (1 << i)))
1652 */
1653 if (mach->ExecMask) {
1654 ++(*prim_count);
1655 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1656 mach->Primitives[*prim_count] = 0;
1657 }
1658 }
1659
1660 static void
1661 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1662 {
1663 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1664 int emitted_verts =
1665 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1666 if (emitted_verts) {
1667 emit_primitive(mach);
1668 }
1669 }
1670 }
1671
1672
1673 /*
1674 * Fetch four texture samples using STR texture coordinates.
1675 */
1676 static void
1677 fetch_texel( struct tgsi_sampler *sampler,
1678 const unsigned sview_idx,
1679 const unsigned sampler_idx,
1680 const union tgsi_exec_channel *s,
1681 const union tgsi_exec_channel *t,
1682 const union tgsi_exec_channel *p,
1683 const union tgsi_exec_channel *c0,
1684 const union tgsi_exec_channel *c1,
1685 float derivs[3][2][TGSI_QUAD_SIZE],
1686 const int8_t offset[3],
1687 enum tgsi_sampler_control control,
1688 union tgsi_exec_channel *r,
1689 union tgsi_exec_channel *g,
1690 union tgsi_exec_channel *b,
1691 union tgsi_exec_channel *a )
1692 {
1693 uint j;
1694 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1695
1696 /* FIXME: handle explicit derivs, offsets */
1697 sampler->get_samples(sampler, sview_idx, sampler_idx,
1698 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1699
1700 for (j = 0; j < 4; j++) {
1701 r->f[j] = rgba[0][j];
1702 g->f[j] = rgba[1][j];
1703 b->f[j] = rgba[2][j];
1704 a->f[j] = rgba[3][j];
1705 }
1706 }
1707
1708
1709 #define TEX_MODIFIER_NONE 0
1710 #define TEX_MODIFIER_PROJECTED 1
1711 #define TEX_MODIFIER_LOD_BIAS 2
1712 #define TEX_MODIFIER_EXPLICIT_LOD 3
1713 #define TEX_MODIFIER_LEVEL_ZERO 4
1714
1715
1716 /*
1717 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1718 */
1719 static void
1720 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1721 const struct tgsi_full_instruction *inst,
1722 int8_t offsets[3])
1723 {
1724 if (inst->Texture.NumOffsets == 1) {
1725 union tgsi_exec_channel index;
1726 union tgsi_exec_channel offset[3];
1727 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1728 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1729 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1730 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1731 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1732 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1733 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1734 offsets[0] = offset[0].i[0];
1735 offsets[1] = offset[1].i[0];
1736 offsets[2] = offset[2].i[0];
1737 } else {
1738 assert(inst->Texture.NumOffsets == 0);
1739 offsets[0] = offsets[1] = offsets[2] = 0;
1740 }
1741 }
1742
1743
1744 /*
1745 * Fetch dx and dy values for one channel (s, t or r).
1746 * Put dx values into one float array, dy values into another.
1747 */
1748 static void
1749 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1750 const struct tgsi_full_instruction *inst,
1751 unsigned regdsrcx,
1752 unsigned chan,
1753 float derivs[2][TGSI_QUAD_SIZE])
1754 {
1755 union tgsi_exec_channel d;
1756 FETCH(&d, regdsrcx, chan);
1757 derivs[0][0] = d.f[0];
1758 derivs[0][1] = d.f[1];
1759 derivs[0][2] = d.f[2];
1760 derivs[0][3] = d.f[3];
1761 FETCH(&d, regdsrcx + 1, chan);
1762 derivs[1][0] = d.f[0];
1763 derivs[1][1] = d.f[1];
1764 derivs[1][2] = d.f[2];
1765 derivs[1][3] = d.f[3];
1766 }
1767
1768
1769 /*
1770 * execute a texture instruction.
1771 *
1772 * modifier is used to control the channel routing for the\
1773 * instruction variants like proj, lod, and texture with lod bias.
1774 * sampler indicates which src register the sampler is contained in.
1775 */
1776 static void
1777 exec_tex(struct tgsi_exec_machine *mach,
1778 const struct tgsi_full_instruction *inst,
1779 uint modifier, uint sampler)
1780 {
1781 const uint unit = inst->Src[sampler].Register.Index;
1782 const union tgsi_exec_channel *args[5], *proj = NULL;
1783 union tgsi_exec_channel r[5];
1784 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
1785 uint chan;
1786 int8_t offsets[3];
1787 int dim, shadow_ref, i;
1788
1789 /* always fetch all 3 offsets, overkill but keeps code simple */
1790 fetch_texel_offsets(mach, inst, offsets);
1791
1792 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
1793 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
1794
1795 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, &shadow_ref);
1796
1797 assert(dim <= 4);
1798 if (shadow_ref >= 0)
1799 assert(shadow_ref >= dim && shadow_ref < Elements(args));
1800
1801 /* fetch modifier to the last argument */
1802 if (modifier != TEX_MODIFIER_NONE) {
1803 const int last = Elements(args) - 1;
1804
1805 /* fetch modifier from src0.w or src1.x */
1806 if (sampler == 1) {
1807 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
1808 FETCH(&r[last], 0, TGSI_CHAN_W);
1809 }
1810 else {
1811 assert(shadow_ref != 4);
1812 FETCH(&r[last], 1, TGSI_CHAN_X);
1813 }
1814
1815 if (modifier != TEX_MODIFIER_PROJECTED) {
1816 args[last] = &r[last];
1817 }
1818 else {
1819 proj = &r[last];
1820 args[last] = &ZeroVec;
1821 }
1822
1823 /* point unused arguments to zero vector */
1824 for (i = dim; i < last; i++)
1825 args[i] = &ZeroVec;
1826
1827 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
1828 control = tgsi_sampler_lod_explicit;
1829 else if (modifier == TEX_MODIFIER_LOD_BIAS)
1830 control = tgsi_sampler_lod_bias;
1831 }
1832 else {
1833 for (i = dim; i < Elements(args); i++)
1834 args[i] = &ZeroVec;
1835 }
1836
1837 /* fetch coordinates */
1838 for (i = 0; i < dim; i++) {
1839 FETCH(&r[i], 0, TGSI_CHAN_X + i);
1840
1841 if (proj)
1842 micro_div(&r[i], &r[i], proj);
1843
1844 args[i] = &r[i];
1845 }
1846
1847 /* fetch reference value */
1848 if (shadow_ref >= 0) {
1849 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
1850
1851 if (proj)
1852 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
1853
1854 args[shadow_ref] = &r[shadow_ref];
1855 }
1856
1857 fetch_texel(mach->Sampler, unit, unit,
1858 args[0], args[1], args[2], args[3], args[4],
1859 NULL, offsets, control,
1860 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1861
1862 #if 0
1863 debug_printf("fetch r: %g %g %g %g\n",
1864 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1865 debug_printf("fetch g: %g %g %g %g\n",
1866 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1867 debug_printf("fetch b: %g %g %g %g\n",
1868 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1869 debug_printf("fetch a: %g %g %g %g\n",
1870 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1871 #endif
1872
1873 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1874 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1875 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1876 }
1877 }
1878 }
1879
1880
1881 static void
1882 exec_txd(struct tgsi_exec_machine *mach,
1883 const struct tgsi_full_instruction *inst)
1884 {
1885 const uint unit = inst->Src[3].Register.Index;
1886 union tgsi_exec_channel r[4];
1887 float derivs[3][2][TGSI_QUAD_SIZE];
1888 uint chan;
1889 int8_t offsets[3];
1890
1891 /* always fetch all 3 offsets, overkill but keeps code simple */
1892 fetch_texel_offsets(mach, inst, offsets);
1893
1894 switch (inst->Texture.Texture) {
1895 case TGSI_TEXTURE_1D:
1896 FETCH(&r[0], 0, TGSI_CHAN_X);
1897
1898 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1899
1900 fetch_texel(mach->Sampler, unit, unit,
1901 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1902 derivs, offsets, tgsi_sampler_derivs_explicit,
1903 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1904 break;
1905
1906 case TGSI_TEXTURE_SHADOW1D:
1907 case TGSI_TEXTURE_1D_ARRAY:
1908 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1909 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
1910 FETCH(&r[0], 0, TGSI_CHAN_X);
1911 FETCH(&r[1], 0, TGSI_CHAN_Y);
1912 FETCH(&r[2], 0, TGSI_CHAN_Z);
1913
1914 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1915
1916 fetch_texel(mach->Sampler, unit, unit,
1917 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1918 derivs, offsets, tgsi_sampler_derivs_explicit,
1919 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1920 break;
1921
1922 case TGSI_TEXTURE_2D:
1923 case TGSI_TEXTURE_RECT:
1924 FETCH(&r[0], 0, TGSI_CHAN_X);
1925 FETCH(&r[1], 0, TGSI_CHAN_Y);
1926
1927 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1928 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1929
1930 fetch_texel(mach->Sampler, unit, unit,
1931 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1932 derivs, offsets, tgsi_sampler_derivs_explicit,
1933 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1934 break;
1935
1936
1937 case TGSI_TEXTURE_SHADOW2D:
1938 case TGSI_TEXTURE_SHADOWRECT:
1939 case TGSI_TEXTURE_2D_ARRAY:
1940 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1941 /* only SHADOW2D_ARRAY actually needs W */
1942 FETCH(&r[0], 0, TGSI_CHAN_X);
1943 FETCH(&r[1], 0, TGSI_CHAN_Y);
1944 FETCH(&r[2], 0, TGSI_CHAN_Z);
1945 FETCH(&r[3], 0, TGSI_CHAN_W);
1946
1947 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1948 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1949
1950 fetch_texel(mach->Sampler, unit, unit,
1951 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1952 derivs, offsets, tgsi_sampler_derivs_explicit,
1953 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1954 break;
1955
1956 case TGSI_TEXTURE_3D:
1957 case TGSI_TEXTURE_CUBE:
1958 case TGSI_TEXTURE_CUBE_ARRAY:
1959 /* only TEXTURE_CUBE_ARRAY actually needs W */
1960 FETCH(&r[0], 0, TGSI_CHAN_X);
1961 FETCH(&r[1], 0, TGSI_CHAN_Y);
1962 FETCH(&r[2], 0, TGSI_CHAN_Z);
1963 FETCH(&r[3], 0, TGSI_CHAN_W);
1964
1965 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1966 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1967 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
1968
1969 fetch_texel(mach->Sampler, unit, unit,
1970 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1971 derivs, offsets, tgsi_sampler_derivs_explicit,
1972 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1973 break;
1974
1975 default:
1976 assert(0);
1977 }
1978
1979 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1980 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1981 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1982 }
1983 }
1984 }
1985
1986
1987 static void
1988 exec_txf(struct tgsi_exec_machine *mach,
1989 const struct tgsi_full_instruction *inst)
1990 {
1991 const uint unit = inst->Src[1].Register.Index;
1992 union tgsi_exec_channel r[4];
1993 uint chan;
1994 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1995 int j;
1996 int8_t offsets[3];
1997 unsigned target;
1998
1999 /* always fetch all 3 offsets, overkill but keeps code simple */
2000 fetch_texel_offsets(mach, inst, offsets);
2001
2002 IFETCH(&r[3], 0, TGSI_CHAN_W);
2003
2004 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2005 target = mach->SamplerViews[unit].Resource;
2006 }
2007 else {
2008 target = inst->Texture.Texture;
2009 }
2010 switch(target) {
2011 case TGSI_TEXTURE_3D:
2012 case TGSI_TEXTURE_2D_ARRAY:
2013 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2014 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2015 /* fallthrough */
2016 case TGSI_TEXTURE_2D:
2017 case TGSI_TEXTURE_RECT:
2018 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2019 case TGSI_TEXTURE_SHADOW2D:
2020 case TGSI_TEXTURE_SHADOWRECT:
2021 case TGSI_TEXTURE_1D_ARRAY:
2022 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2023 /* fallthrough */
2024 case TGSI_TEXTURE_BUFFER:
2025 case TGSI_TEXTURE_1D:
2026 case TGSI_TEXTURE_SHADOW1D:
2027 IFETCH(&r[0], 0, TGSI_CHAN_X);
2028 break;
2029 default:
2030 assert(0);
2031 break;
2032 }
2033
2034 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2035 offsets, rgba);
2036
2037 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2038 r[0].f[j] = rgba[0][j];
2039 r[1].f[j] = rgba[1][j];
2040 r[2].f[j] = rgba[2][j];
2041 r[3].f[j] = rgba[3][j];
2042 }
2043
2044 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2045 unsigned char swizzles[4];
2046 swizzles[0] = inst->Src[1].Register.SwizzleX;
2047 swizzles[1] = inst->Src[1].Register.SwizzleY;
2048 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2049 swizzles[3] = inst->Src[1].Register.SwizzleW;
2050
2051 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2052 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2053 store_dest(mach, &r[swizzles[chan]],
2054 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2055 }
2056 }
2057 }
2058 else {
2059 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2060 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2061 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2062 }
2063 }
2064 }
2065 }
2066
2067 static void
2068 exec_txq(struct tgsi_exec_machine *mach,
2069 const struct tgsi_full_instruction *inst)
2070 {
2071 const uint unit = inst->Src[1].Register.Index;
2072 int result[4];
2073 union tgsi_exec_channel r[4], src;
2074 uint chan;
2075 int i,j;
2076
2077 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2078
2079 /* XXX: This interface can't return per-pixel values */
2080 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2081
2082 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2083 for (j = 0; j < 4; j++) {
2084 r[j].i[i] = result[j];
2085 }
2086 }
2087
2088 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2089 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2090 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2091 TGSI_EXEC_DATA_INT);
2092 }
2093 }
2094 }
2095
2096 static void
2097 exec_sample(struct tgsi_exec_machine *mach,
2098 const struct tgsi_full_instruction *inst,
2099 uint modifier, boolean compare)
2100 {
2101 const uint resource_unit = inst->Src[1].Register.Index;
2102 const uint sampler_unit = inst->Src[2].Register.Index;
2103 union tgsi_exec_channel r[4], c1;
2104 const union tgsi_exec_channel *lod = &ZeroVec;
2105 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2106 uint chan;
2107 unsigned char swizzles[4];
2108 int8_t offsets[3];
2109
2110 /* always fetch all 3 offsets, overkill but keeps code simple */
2111 fetch_texel_offsets(mach, inst, offsets);
2112
2113 assert(modifier != TEX_MODIFIER_PROJECTED);
2114
2115 if (modifier != TEX_MODIFIER_NONE) {
2116 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2117 FETCH(&c1, 3, TGSI_CHAN_X);
2118 lod = &c1;
2119 control = tgsi_sampler_lod_bias;
2120 }
2121 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2122 FETCH(&c1, 3, TGSI_CHAN_X);
2123 lod = &c1;
2124 control = tgsi_sampler_lod_explicit;
2125 }
2126 else {
2127 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2128 control = tgsi_sampler_lod_zero;
2129 }
2130 }
2131
2132 FETCH(&r[0], 0, TGSI_CHAN_X);
2133
2134 switch (mach->SamplerViews[resource_unit].Resource) {
2135 case TGSI_TEXTURE_1D:
2136 if (compare) {
2137 FETCH(&r[2], 3, TGSI_CHAN_X);
2138 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2139 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2140 NULL, offsets, control,
2141 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2142 }
2143 else {
2144 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2145 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2146 NULL, offsets, control,
2147 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2148 }
2149 break;
2150
2151 case TGSI_TEXTURE_1D_ARRAY:
2152 case TGSI_TEXTURE_2D:
2153 case TGSI_TEXTURE_RECT:
2154 FETCH(&r[1], 0, TGSI_CHAN_Y);
2155 if (compare) {
2156 FETCH(&r[2], 3, TGSI_CHAN_X);
2157 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2158 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2159 NULL, offsets, control,
2160 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2161 }
2162 else {
2163 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2164 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2165 NULL, offsets, control,
2166 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2167 }
2168 break;
2169
2170 case TGSI_TEXTURE_2D_ARRAY:
2171 case TGSI_TEXTURE_3D:
2172 case TGSI_TEXTURE_CUBE:
2173 FETCH(&r[1], 0, TGSI_CHAN_Y);
2174 FETCH(&r[2], 0, TGSI_CHAN_Z);
2175 if(compare) {
2176 FETCH(&r[3], 3, TGSI_CHAN_X);
2177 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2178 &r[0], &r[1], &r[2], &r[3], lod,
2179 NULL, offsets, control,
2180 &r[0], &r[1], &r[2], &r[3]);
2181 }
2182 else {
2183 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2184 &r[0], &r[1], &r[2], &ZeroVec, lod,
2185 NULL, offsets, control,
2186 &r[0], &r[1], &r[2], &r[3]);
2187 }
2188 break;
2189
2190 case TGSI_TEXTURE_CUBE_ARRAY:
2191 FETCH(&r[1], 0, TGSI_CHAN_Y);
2192 FETCH(&r[2], 0, TGSI_CHAN_Z);
2193 FETCH(&r[3], 0, TGSI_CHAN_W);
2194 if(compare) {
2195 FETCH(&r[4], 3, TGSI_CHAN_X);
2196 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2197 &r[0], &r[1], &r[2], &r[3], &r[4],
2198 NULL, offsets, control,
2199 &r[0], &r[1], &r[2], &r[3]);
2200 }
2201 else {
2202 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2203 &r[0], &r[1], &r[2], &r[3], lod,
2204 NULL, offsets, control,
2205 &r[0], &r[1], &r[2], &r[3]);
2206 }
2207 break;
2208
2209
2210 default:
2211 assert(0);
2212 }
2213
2214 swizzles[0] = inst->Src[1].Register.SwizzleX;
2215 swizzles[1] = inst->Src[1].Register.SwizzleY;
2216 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2217 swizzles[3] = inst->Src[1].Register.SwizzleW;
2218
2219 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2220 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2221 store_dest(mach, &r[swizzles[chan]],
2222 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2223 }
2224 }
2225 }
2226
2227 static void
2228 exec_sample_d(struct tgsi_exec_machine *mach,
2229 const struct tgsi_full_instruction *inst)
2230 {
2231 const uint resource_unit = inst->Src[1].Register.Index;
2232 const uint sampler_unit = inst->Src[2].Register.Index;
2233 union tgsi_exec_channel r[4];
2234 float derivs[3][2][TGSI_QUAD_SIZE];
2235 uint chan;
2236 unsigned char swizzles[4];
2237 int8_t offsets[3];
2238
2239 /* always fetch all 3 offsets, overkill but keeps code simple */
2240 fetch_texel_offsets(mach, inst, offsets);
2241
2242 FETCH(&r[0], 0, TGSI_CHAN_X);
2243
2244 switch (mach->SamplerViews[resource_unit].Resource) {
2245 case TGSI_TEXTURE_1D:
2246 case TGSI_TEXTURE_1D_ARRAY:
2247 /* only 1D array actually needs Y */
2248 FETCH(&r[1], 0, TGSI_CHAN_Y);
2249
2250 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2251
2252 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2253 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2254 derivs, offsets, tgsi_sampler_derivs_explicit,
2255 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2256 break;
2257
2258 case TGSI_TEXTURE_2D:
2259 case TGSI_TEXTURE_RECT:
2260 case TGSI_TEXTURE_2D_ARRAY:
2261 /* only 2D array actually needs Z */
2262 FETCH(&r[1], 0, TGSI_CHAN_Y);
2263 FETCH(&r[2], 0, TGSI_CHAN_Z);
2264
2265 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2266 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2267
2268 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2269 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2270 derivs, offsets, tgsi_sampler_derivs_explicit,
2271 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2272 break;
2273
2274 case TGSI_TEXTURE_3D:
2275 case TGSI_TEXTURE_CUBE:
2276 case TGSI_TEXTURE_CUBE_ARRAY:
2277 /* only cube array actually needs W */
2278 FETCH(&r[1], 0, TGSI_CHAN_Y);
2279 FETCH(&r[2], 0, TGSI_CHAN_Z);
2280 FETCH(&r[3], 0, TGSI_CHAN_W);
2281
2282 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2283 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2284 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2285
2286 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2287 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2288 derivs, offsets, tgsi_sampler_derivs_explicit,
2289 &r[0], &r[1], &r[2], &r[3]);
2290 break;
2291
2292 default:
2293 assert(0);
2294 }
2295
2296 swizzles[0] = inst->Src[1].Register.SwizzleX;
2297 swizzles[1] = inst->Src[1].Register.SwizzleY;
2298 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2299 swizzles[3] = inst->Src[1].Register.SwizzleW;
2300
2301 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2302 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2303 store_dest(mach, &r[swizzles[chan]],
2304 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2305 }
2306 }
2307 }
2308
2309
2310 /**
2311 * Evaluate a constant-valued coefficient at the position of the
2312 * current quad.
2313 */
2314 static void
2315 eval_constant_coef(
2316 struct tgsi_exec_machine *mach,
2317 unsigned attrib,
2318 unsigned chan )
2319 {
2320 unsigned i;
2321
2322 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2323 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2324 }
2325 }
2326
2327 /**
2328 * Evaluate a linear-valued coefficient at the position of the
2329 * current quad.
2330 */
2331 static void
2332 eval_linear_coef(
2333 struct tgsi_exec_machine *mach,
2334 unsigned attrib,
2335 unsigned chan )
2336 {
2337 const float x = mach->QuadPos.xyzw[0].f[0];
2338 const float y = mach->QuadPos.xyzw[1].f[0];
2339 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2340 const float dady = mach->InterpCoefs[attrib].dady[chan];
2341 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2342 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2343 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2344 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2345 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2346 }
2347
2348 /**
2349 * Evaluate a perspective-valued coefficient at the position of the
2350 * current quad.
2351 */
2352 static void
2353 eval_perspective_coef(
2354 struct tgsi_exec_machine *mach,
2355 unsigned attrib,
2356 unsigned chan )
2357 {
2358 const float x = mach->QuadPos.xyzw[0].f[0];
2359 const float y = mach->QuadPos.xyzw[1].f[0];
2360 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2361 const float dady = mach->InterpCoefs[attrib].dady[chan];
2362 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2363 const float *w = mach->QuadPos.xyzw[3].f;
2364 /* divide by W here */
2365 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2366 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2367 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2368 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2369 }
2370
2371
2372 typedef void (* eval_coef_func)(
2373 struct tgsi_exec_machine *mach,
2374 unsigned attrib,
2375 unsigned chan );
2376
2377 static void
2378 exec_declaration(struct tgsi_exec_machine *mach,
2379 const struct tgsi_full_declaration *decl)
2380 {
2381 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2382 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2383 return;
2384 }
2385
2386 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2387 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2388 uint first, last, mask;
2389
2390 first = decl->Range.First;
2391 last = decl->Range.Last;
2392 mask = decl->Declaration.UsageMask;
2393
2394 /* XXX we could remove this special-case code since
2395 * mach->InterpCoefs[first].a0 should already have the
2396 * front/back-face value. But we should first update the
2397 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2398 * Then, we could remove the tgsi_exec_machine::Face field.
2399 */
2400 /* XXX make FACE a system value */
2401 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2402 uint i;
2403
2404 assert(decl->Semantic.Index == 0);
2405 assert(first == last);
2406
2407 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2408 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2409 }
2410 } else {
2411 eval_coef_func eval;
2412 uint i, j;
2413
2414 switch (decl->Interp.Interpolate) {
2415 case TGSI_INTERPOLATE_CONSTANT:
2416 eval = eval_constant_coef;
2417 break;
2418
2419 case TGSI_INTERPOLATE_LINEAR:
2420 eval = eval_linear_coef;
2421 break;
2422
2423 case TGSI_INTERPOLATE_PERSPECTIVE:
2424 eval = eval_perspective_coef;
2425 break;
2426
2427 case TGSI_INTERPOLATE_COLOR:
2428 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2429 break;
2430
2431 default:
2432 assert(0);
2433 return;
2434 }
2435
2436 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2437 if (mask & (1 << j)) {
2438 for (i = first; i <= last; i++) {
2439 eval(mach, i, j);
2440 }
2441 }
2442 }
2443 }
2444
2445 if (DEBUG_EXECUTION) {
2446 uint i, j;
2447 for (i = first; i <= last; ++i) {
2448 debug_printf("IN[%2u] = ", i);
2449 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2450 if (j > 0) {
2451 debug_printf(" ");
2452 }
2453 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2454 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2455 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2456 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2457 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2458 }
2459 }
2460 }
2461 }
2462 }
2463
2464 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2465 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2466 }
2467 }
2468
2469
2470 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2471
2472 static void
2473 exec_vector(struct tgsi_exec_machine *mach,
2474 const struct tgsi_full_instruction *inst,
2475 micro_op op,
2476 enum tgsi_exec_datatype dst_datatype)
2477 {
2478 unsigned int chan;
2479
2480 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2481 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2482 union tgsi_exec_channel dst;
2483
2484 op(&dst);
2485 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2486 }
2487 }
2488 }
2489
2490 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2491 const union tgsi_exec_channel *src);
2492
2493 static void
2494 exec_scalar_unary(struct tgsi_exec_machine *mach,
2495 const struct tgsi_full_instruction *inst,
2496 micro_unary_op op,
2497 enum tgsi_exec_datatype dst_datatype,
2498 enum tgsi_exec_datatype src_datatype)
2499 {
2500 unsigned int chan;
2501 union tgsi_exec_channel src;
2502 union tgsi_exec_channel dst;
2503
2504 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2505 op(&dst, &src);
2506 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2507 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2508 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2509 }
2510 }
2511 }
2512
2513 static void
2514 exec_vector_unary(struct tgsi_exec_machine *mach,
2515 const struct tgsi_full_instruction *inst,
2516 micro_unary_op op,
2517 enum tgsi_exec_datatype dst_datatype,
2518 enum tgsi_exec_datatype src_datatype)
2519 {
2520 unsigned int chan;
2521 struct tgsi_exec_vector dst;
2522
2523 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2524 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2525 union tgsi_exec_channel src;
2526
2527 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2528 op(&dst.xyzw[chan], &src);
2529 }
2530 }
2531 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2532 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2533 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2534 }
2535 }
2536 }
2537
2538 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2539 const union tgsi_exec_channel *src0,
2540 const union tgsi_exec_channel *src1);
2541
2542 static void
2543 exec_scalar_binary(struct tgsi_exec_machine *mach,
2544 const struct tgsi_full_instruction *inst,
2545 micro_binary_op op,
2546 enum tgsi_exec_datatype dst_datatype,
2547 enum tgsi_exec_datatype src_datatype)
2548 {
2549 unsigned int chan;
2550 union tgsi_exec_channel src[2];
2551 union tgsi_exec_channel dst;
2552
2553 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2554 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2555 op(&dst, &src[0], &src[1]);
2556 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2557 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2558 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2559 }
2560 }
2561 }
2562
2563 static void
2564 exec_vector_binary(struct tgsi_exec_machine *mach,
2565 const struct tgsi_full_instruction *inst,
2566 micro_binary_op op,
2567 enum tgsi_exec_datatype dst_datatype,
2568 enum tgsi_exec_datatype src_datatype)
2569 {
2570 unsigned int chan;
2571 struct tgsi_exec_vector dst;
2572
2573 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2574 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2575 union tgsi_exec_channel src[2];
2576
2577 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2578 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2579 op(&dst.xyzw[chan], &src[0], &src[1]);
2580 }
2581 }
2582 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2583 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2584 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2585 }
2586 }
2587 }
2588
2589 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2590 const union tgsi_exec_channel *src0,
2591 const union tgsi_exec_channel *src1,
2592 const union tgsi_exec_channel *src2);
2593
2594 static void
2595 exec_vector_trinary(struct tgsi_exec_machine *mach,
2596 const struct tgsi_full_instruction *inst,
2597 micro_trinary_op op,
2598 enum tgsi_exec_datatype dst_datatype,
2599 enum tgsi_exec_datatype src_datatype)
2600 {
2601 unsigned int chan;
2602 struct tgsi_exec_vector dst;
2603
2604 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2605 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2606 union tgsi_exec_channel src[3];
2607
2608 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2609 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2610 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2611 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2612 }
2613 }
2614 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2615 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2616 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2617 }
2618 }
2619 }
2620
2621 static void
2622 exec_dp3(struct tgsi_exec_machine *mach,
2623 const struct tgsi_full_instruction *inst)
2624 {
2625 unsigned int chan;
2626 union tgsi_exec_channel arg[3];
2627
2628 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2629 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2630 micro_mul(&arg[2], &arg[0], &arg[1]);
2631
2632 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2633 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2634 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2635 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2636 }
2637
2638 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2639 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2640 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2641 }
2642 }
2643 }
2644
2645 static void
2646 exec_dp4(struct tgsi_exec_machine *mach,
2647 const struct tgsi_full_instruction *inst)
2648 {
2649 unsigned int chan;
2650 union tgsi_exec_channel arg[3];
2651
2652 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2653 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2654 micro_mul(&arg[2], &arg[0], &arg[1]);
2655
2656 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2657 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2658 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2659 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2660 }
2661
2662 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2663 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2664 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2665 }
2666 }
2667 }
2668
2669 static void
2670 exec_dp2a(struct tgsi_exec_machine *mach,
2671 const struct tgsi_full_instruction *inst)
2672 {
2673 unsigned int chan;
2674 union tgsi_exec_channel arg[3];
2675
2676 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2677 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2678 micro_mul(&arg[2], &arg[0], &arg[1]);
2679
2680 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2681 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2682 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2683
2684 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2685 micro_add(&arg[0], &arg[0], &arg[1]);
2686
2687 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2688 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2689 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2690 }
2691 }
2692 }
2693
2694 static void
2695 exec_dph(struct tgsi_exec_machine *mach,
2696 const struct tgsi_full_instruction *inst)
2697 {
2698 unsigned int chan;
2699 union tgsi_exec_channel arg[3];
2700
2701 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2702 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2703 micro_mul(&arg[2], &arg[0], &arg[1]);
2704
2705 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2706 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2707 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2708
2709 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2710 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2711 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2712
2713 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2714 micro_add(&arg[0], &arg[0], &arg[1]);
2715
2716 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2717 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2718 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2719 }
2720 }
2721 }
2722
2723 static void
2724 exec_dp2(struct tgsi_exec_machine *mach,
2725 const struct tgsi_full_instruction *inst)
2726 {
2727 unsigned int chan;
2728 union tgsi_exec_channel arg[3];
2729
2730 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2731 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2732 micro_mul(&arg[2], &arg[0], &arg[1]);
2733
2734 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2735 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2736 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2737
2738 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2739 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2740 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2741 }
2742 }
2743 }
2744
2745 static void
2746 exec_nrm4(struct tgsi_exec_machine *mach,
2747 const struct tgsi_full_instruction *inst)
2748 {
2749 unsigned int chan;
2750 union tgsi_exec_channel arg[4];
2751 union tgsi_exec_channel scale;
2752
2753 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2754 micro_mul(&scale, &arg[0], &arg[0]);
2755
2756 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2757 union tgsi_exec_channel product;
2758
2759 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2760 micro_mul(&product, &arg[chan], &arg[chan]);
2761 micro_add(&scale, &scale, &product);
2762 }
2763
2764 micro_rsq(&scale, &scale);
2765
2766 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_W; chan++) {
2767 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2768 micro_mul(&arg[chan], &arg[chan], &scale);
2769 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2770 }
2771 }
2772 }
2773
2774 static void
2775 exec_nrm3(struct tgsi_exec_machine *mach,
2776 const struct tgsi_full_instruction *inst)
2777 {
2778 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2779 unsigned int chan;
2780 union tgsi_exec_channel arg[3];
2781 union tgsi_exec_channel scale;
2782
2783 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2784 micro_mul(&scale, &arg[0], &arg[0]);
2785
2786 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2787 union tgsi_exec_channel product;
2788
2789 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2790 micro_mul(&product, &arg[chan], &arg[chan]);
2791 micro_add(&scale, &scale, &product);
2792 }
2793
2794 micro_rsq(&scale, &scale);
2795
2796 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_Z; chan++) {
2797 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2798 micro_mul(&arg[chan], &arg[chan], &scale);
2799 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2800 }
2801 }
2802 }
2803
2804 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2805 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2806 }
2807 }
2808
2809 static void
2810 exec_scs(struct tgsi_exec_machine *mach,
2811 const struct tgsi_full_instruction *inst)
2812 {
2813 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2814 union tgsi_exec_channel arg;
2815 union tgsi_exec_channel result;
2816
2817 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2818
2819 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2820 micro_cos(&result, &arg);
2821 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2822 }
2823 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2824 micro_sin(&result, &arg);
2825 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2826 }
2827 }
2828 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2829 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2830 }
2831 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2832 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2833 }
2834 }
2835
2836 static void
2837 exec_x2d(struct tgsi_exec_machine *mach,
2838 const struct tgsi_full_instruction *inst)
2839 {
2840 union tgsi_exec_channel r[4];
2841 union tgsi_exec_channel d[2];
2842
2843 fetch_source(mach, &r[0], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2844 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2845 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2846 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2847 micro_mul(&r[2], &r[2], &r[0]);
2848 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2849 micro_mul(&r[3], &r[3], &r[1]);
2850 micro_add(&r[2], &r[2], &r[3]);
2851 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2852 micro_add(&d[0], &r[2], &r[3]);
2853 }
2854 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2855 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2856 micro_mul(&r[2], &r[2], &r[0]);
2857 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2858 micro_mul(&r[3], &r[3], &r[1]);
2859 micro_add(&r[2], &r[2], &r[3]);
2860 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2861 micro_add(&d[1], &r[2], &r[3]);
2862 }
2863 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2864 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2865 }
2866 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2867 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2868 }
2869 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2870 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2871 }
2872 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2873 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2874 }
2875 }
2876
2877 static void
2878 exec_rfl(struct tgsi_exec_machine *mach,
2879 const struct tgsi_full_instruction *inst)
2880 {
2881 union tgsi_exec_channel r[9];
2882
2883 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2884 /* r0 = dp3(src0, src0) */
2885 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2886 micro_mul(&r[0], &r[2], &r[2]);
2887 fetch_source(mach, &r[4], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2888 micro_mul(&r[8], &r[4], &r[4]);
2889 micro_add(&r[0], &r[0], &r[8]);
2890 fetch_source(mach, &r[6], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2891 micro_mul(&r[8], &r[6], &r[6]);
2892 micro_add(&r[0], &r[0], &r[8]);
2893
2894 /* r1 = dp3(src0, src1) */
2895 fetch_source(mach, &r[3], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2896 micro_mul(&r[1], &r[2], &r[3]);
2897 fetch_source(mach, &r[5], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2898 micro_mul(&r[8], &r[4], &r[5]);
2899 micro_add(&r[1], &r[1], &r[8]);
2900 fetch_source(mach, &r[7], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2901 micro_mul(&r[8], &r[6], &r[7]);
2902 micro_add(&r[1], &r[1], &r[8]);
2903
2904 /* r1 = 2 * r1 / r0 */
2905 micro_add(&r[1], &r[1], &r[1]);
2906 micro_div(&r[1], &r[1], &r[0]);
2907
2908 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2909 micro_mul(&r[2], &r[2], &r[1]);
2910 micro_sub(&r[2], &r[2], &r[3]);
2911 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2912 }
2913 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2914 micro_mul(&r[4], &r[4], &r[1]);
2915 micro_sub(&r[4], &r[4], &r[5]);
2916 store_dest(mach, &r[4], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2917 }
2918 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2919 micro_mul(&r[6], &r[6], &r[1]);
2920 micro_sub(&r[6], &r[6], &r[7]);
2921 store_dest(mach, &r[6], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2922 }
2923 }
2924 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2925 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2926 }
2927 }
2928
2929 static void
2930 exec_xpd(struct tgsi_exec_machine *mach,
2931 const struct tgsi_full_instruction *inst)
2932 {
2933 union tgsi_exec_channel r[6];
2934 union tgsi_exec_channel d[3];
2935
2936 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2937 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2938
2939 micro_mul(&r[2], &r[0], &r[1]);
2940
2941 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2942 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2943
2944 micro_mul(&r[5], &r[3], &r[4] );
2945 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
2946
2947 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2948
2949 micro_mul(&r[3], &r[3], &r[2]);
2950
2951 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2952
2953 micro_mul(&r[1], &r[1], &r[5]);
2954 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
2955
2956 micro_mul(&r[5], &r[5], &r[4]);
2957 micro_mul(&r[0], &r[0], &r[2]);
2958 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
2959
2960 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2961 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2962 }
2963 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2964 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2965 }
2966 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2967 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2968 }
2969 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2970 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2971 }
2972 }
2973
2974 static void
2975 exec_dst(struct tgsi_exec_machine *mach,
2976 const struct tgsi_full_instruction *inst)
2977 {
2978 union tgsi_exec_channel r[2];
2979 union tgsi_exec_channel d[4];
2980
2981 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2982 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2983 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2984 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
2985 }
2986 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2987 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2988 }
2989 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2990 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2991 }
2992
2993 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2994 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2995 }
2996 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2997 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2998 }
2999 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3000 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3001 }
3002 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3003 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3004 }
3005 }
3006
3007 static void
3008 exec_log(struct tgsi_exec_machine *mach,
3009 const struct tgsi_full_instruction *inst)
3010 {
3011 union tgsi_exec_channel r[3];
3012
3013 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3014 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3015 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3016 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3017 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3018 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3019 }
3020 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3021 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3022 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3023 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3024 }
3025 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3026 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3027 }
3028 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3029 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3030 }
3031 }
3032
3033 static void
3034 exec_exp(struct tgsi_exec_machine *mach,
3035 const struct tgsi_full_instruction *inst)
3036 {
3037 union tgsi_exec_channel r[3];
3038
3039 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3040 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3041 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3042 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3043 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3044 }
3045 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3046 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3047 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3048 }
3049 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3050 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3051 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3052 }
3053 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3054 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3055 }
3056 }
3057
3058 static void
3059 exec_lit(struct tgsi_exec_machine *mach,
3060 const struct tgsi_full_instruction *inst)
3061 {
3062 union tgsi_exec_channel r[3];
3063 union tgsi_exec_channel d[3];
3064
3065 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3066 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3067 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3068 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3069 micro_max(&r[1], &r[1], &ZeroVec);
3070
3071 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3072 micro_min(&r[2], &r[2], &P128Vec);
3073 micro_max(&r[2], &r[2], &M128Vec);
3074 micro_pow(&r[1], &r[1], &r[2]);
3075 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3076 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3077 }
3078 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3079 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3080 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3081 }
3082 }
3083 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3084 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3085 }
3086
3087 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3088 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3089 }
3090 }
3091
3092 static void
3093 exec_break(struct tgsi_exec_machine *mach)
3094 {
3095 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3096 /* turn off loop channels for each enabled exec channel */
3097 mach->LoopMask &= ~mach->ExecMask;
3098 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3099 UPDATE_EXEC_MASK(mach);
3100 } else {
3101 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3102
3103 mach->Switch.mask = 0x0;
3104
3105 UPDATE_EXEC_MASK(mach);
3106 }
3107 }
3108
3109 static void
3110 exec_switch(struct tgsi_exec_machine *mach,
3111 const struct tgsi_full_instruction *inst)
3112 {
3113 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3114 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3115
3116 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3117 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3118 mach->Switch.mask = 0x0;
3119 mach->Switch.defaultMask = 0x0;
3120
3121 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3122 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3123
3124 UPDATE_EXEC_MASK(mach);
3125 }
3126
3127 static void
3128 exec_case(struct tgsi_exec_machine *mach,
3129 const struct tgsi_full_instruction *inst)
3130 {
3131 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3132 union tgsi_exec_channel src;
3133 uint mask = 0;
3134
3135 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3136
3137 if (mach->Switch.selector.u[0] == src.u[0]) {
3138 mask |= 0x1;
3139 }
3140 if (mach->Switch.selector.u[1] == src.u[1]) {
3141 mask |= 0x2;
3142 }
3143 if (mach->Switch.selector.u[2] == src.u[2]) {
3144 mask |= 0x4;
3145 }
3146 if (mach->Switch.selector.u[3] == src.u[3]) {
3147 mask |= 0x8;
3148 }
3149
3150 mach->Switch.defaultMask |= mask;
3151
3152 mach->Switch.mask |= mask & prevMask;
3153
3154 UPDATE_EXEC_MASK(mach);
3155 }
3156
3157 /* FIXME: this will only work if default is last */
3158 static void
3159 exec_default(struct tgsi_exec_machine *mach)
3160 {
3161 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3162
3163 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3164
3165 UPDATE_EXEC_MASK(mach);
3166 }
3167
3168 static void
3169 exec_endswitch(struct tgsi_exec_machine *mach)
3170 {
3171 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3172 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3173
3174 UPDATE_EXEC_MASK(mach);
3175 }
3176
3177 static void
3178 micro_i2f(union tgsi_exec_channel *dst,
3179 const union tgsi_exec_channel *src)
3180 {
3181 dst->f[0] = (float)src->i[0];
3182 dst->f[1] = (float)src->i[1];
3183 dst->f[2] = (float)src->i[2];
3184 dst->f[3] = (float)src->i[3];
3185 }
3186
3187 static void
3188 micro_not(union tgsi_exec_channel *dst,
3189 const union tgsi_exec_channel *src)
3190 {
3191 dst->u[0] = ~src->u[0];
3192 dst->u[1] = ~src->u[1];
3193 dst->u[2] = ~src->u[2];
3194 dst->u[3] = ~src->u[3];
3195 }
3196
3197 static void
3198 micro_shl(union tgsi_exec_channel *dst,
3199 const union tgsi_exec_channel *src0,
3200 const union tgsi_exec_channel *src1)
3201 {
3202 unsigned masked_count;
3203 masked_count = src1->u[0] & 0x1f;
3204 dst->u[0] = src0->u[0] << masked_count;
3205 masked_count = src1->u[1] & 0x1f;
3206 dst->u[1] = src0->u[1] << masked_count;
3207 masked_count = src1->u[2] & 0x1f;
3208 dst->u[2] = src0->u[2] << masked_count;
3209 masked_count = src1->u[3] & 0x1f;
3210 dst->u[3] = src0->u[3] << masked_count;
3211 }
3212
3213 static void
3214 micro_and(union tgsi_exec_channel *dst,
3215 const union tgsi_exec_channel *src0,
3216 const union tgsi_exec_channel *src1)
3217 {
3218 dst->u[0] = src0->u[0] & src1->u[0];
3219 dst->u[1] = src0->u[1] & src1->u[1];
3220 dst->u[2] = src0->u[2] & src1->u[2];
3221 dst->u[3] = src0->u[3] & src1->u[3];
3222 }
3223
3224 static void
3225 micro_or(union tgsi_exec_channel *dst,
3226 const union tgsi_exec_channel *src0,
3227 const union tgsi_exec_channel *src1)
3228 {
3229 dst->u[0] = src0->u[0] | src1->u[0];
3230 dst->u[1] = src0->u[1] | src1->u[1];
3231 dst->u[2] = src0->u[2] | src1->u[2];
3232 dst->u[3] = src0->u[3] | src1->u[3];
3233 }
3234
3235 static void
3236 micro_xor(union tgsi_exec_channel *dst,
3237 const union tgsi_exec_channel *src0,
3238 const union tgsi_exec_channel *src1)
3239 {
3240 dst->u[0] = src0->u[0] ^ src1->u[0];
3241 dst->u[1] = src0->u[1] ^ src1->u[1];
3242 dst->u[2] = src0->u[2] ^ src1->u[2];
3243 dst->u[3] = src0->u[3] ^ src1->u[3];
3244 }
3245
3246 static void
3247 micro_mod(union tgsi_exec_channel *dst,
3248 const union tgsi_exec_channel *src0,
3249 const union tgsi_exec_channel *src1)
3250 {
3251 dst->i[0] = src0->i[0] % src1->i[0];
3252 dst->i[1] = src0->i[1] % src1->i[1];
3253 dst->i[2] = src0->i[2] % src1->i[2];
3254 dst->i[3] = src0->i[3] % src1->i[3];
3255 }
3256
3257 static void
3258 micro_f2i(union tgsi_exec_channel *dst,
3259 const union tgsi_exec_channel *src)
3260 {
3261 dst->i[0] = (int)src->f[0];
3262 dst->i[1] = (int)src->f[1];
3263 dst->i[2] = (int)src->f[2];
3264 dst->i[3] = (int)src->f[3];
3265 }
3266
3267 static void
3268 micro_fseq(union tgsi_exec_channel *dst,
3269 const union tgsi_exec_channel *src0,
3270 const union tgsi_exec_channel *src1)
3271 {
3272 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
3273 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
3274 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
3275 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
3276 }
3277
3278 static void
3279 micro_fsge(union tgsi_exec_channel *dst,
3280 const union tgsi_exec_channel *src0,
3281 const union tgsi_exec_channel *src1)
3282 {
3283 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
3284 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
3285 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
3286 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
3287 }
3288
3289 static void
3290 micro_fslt(union tgsi_exec_channel *dst,
3291 const union tgsi_exec_channel *src0,
3292 const union tgsi_exec_channel *src1)
3293 {
3294 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
3295 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
3296 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
3297 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
3298 }
3299
3300 static void
3301 micro_fsne(union tgsi_exec_channel *dst,
3302 const union tgsi_exec_channel *src0,
3303 const union tgsi_exec_channel *src1)
3304 {
3305 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
3306 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
3307 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
3308 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
3309 }
3310
3311 static void
3312 micro_idiv(union tgsi_exec_channel *dst,
3313 const union tgsi_exec_channel *src0,
3314 const union tgsi_exec_channel *src1)
3315 {
3316 dst->i[0] = src0->i[0] / src1->i[0];
3317 dst->i[1] = src0->i[1] / src1->i[1];
3318 dst->i[2] = src0->i[2] / src1->i[2];
3319 dst->i[3] = src0->i[3] / src1->i[3];
3320 }
3321
3322 static void
3323 micro_imax(union tgsi_exec_channel *dst,
3324 const union tgsi_exec_channel *src0,
3325 const union tgsi_exec_channel *src1)
3326 {
3327 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3328 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3329 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3330 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3331 }
3332
3333 static void
3334 micro_imin(union tgsi_exec_channel *dst,
3335 const union tgsi_exec_channel *src0,
3336 const union tgsi_exec_channel *src1)
3337 {
3338 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3339 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3340 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3341 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3342 }
3343
3344 static void
3345 micro_isge(union tgsi_exec_channel *dst,
3346 const union tgsi_exec_channel *src0,
3347 const union tgsi_exec_channel *src1)
3348 {
3349 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3350 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3351 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3352 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3353 }
3354
3355 static void
3356 micro_ishr(union tgsi_exec_channel *dst,
3357 const union tgsi_exec_channel *src0,
3358 const union tgsi_exec_channel *src1)
3359 {
3360 unsigned masked_count;
3361 masked_count = src1->i[0] & 0x1f;
3362 dst->i[0] = src0->i[0] >> masked_count;
3363 masked_count = src1->i[1] & 0x1f;
3364 dst->i[1] = src0->i[1] >> masked_count;
3365 masked_count = src1->i[2] & 0x1f;
3366 dst->i[2] = src0->i[2] >> masked_count;
3367 masked_count = src1->i[3] & 0x1f;
3368 dst->i[3] = src0->i[3] >> masked_count;
3369 }
3370
3371 static void
3372 micro_islt(union tgsi_exec_channel *dst,
3373 const union tgsi_exec_channel *src0,
3374 const union tgsi_exec_channel *src1)
3375 {
3376 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3377 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3378 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3379 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3380 }
3381
3382 static void
3383 micro_f2u(union tgsi_exec_channel *dst,
3384 const union tgsi_exec_channel *src)
3385 {
3386 dst->u[0] = (uint)src->f[0];
3387 dst->u[1] = (uint)src->f[1];
3388 dst->u[2] = (uint)src->f[2];
3389 dst->u[3] = (uint)src->f[3];
3390 }
3391
3392 static void
3393 micro_u2f(union tgsi_exec_channel *dst,
3394 const union tgsi_exec_channel *src)
3395 {
3396 dst->f[0] = (float)src->u[0];
3397 dst->f[1] = (float)src->u[1];
3398 dst->f[2] = (float)src->u[2];
3399 dst->f[3] = (float)src->u[3];
3400 }
3401
3402 static void
3403 micro_uadd(union tgsi_exec_channel *dst,
3404 const union tgsi_exec_channel *src0,
3405 const union tgsi_exec_channel *src1)
3406 {
3407 dst->u[0] = src0->u[0] + src1->u[0];
3408 dst->u[1] = src0->u[1] + src1->u[1];
3409 dst->u[2] = src0->u[2] + src1->u[2];
3410 dst->u[3] = src0->u[3] + src1->u[3];
3411 }
3412
3413 static void
3414 micro_udiv(union tgsi_exec_channel *dst,
3415 const union tgsi_exec_channel *src0,
3416 const union tgsi_exec_channel *src1)
3417 {
3418 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
3419 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
3420 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
3421 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
3422 }
3423
3424 static void
3425 micro_umad(union tgsi_exec_channel *dst,
3426 const union tgsi_exec_channel *src0,
3427 const union tgsi_exec_channel *src1,
3428 const union tgsi_exec_channel *src2)
3429 {
3430 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3431 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3432 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3433 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3434 }
3435
3436 static void
3437 micro_umax(union tgsi_exec_channel *dst,
3438 const union tgsi_exec_channel *src0,
3439 const union tgsi_exec_channel *src1)
3440 {
3441 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3442 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3443 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3444 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3445 }
3446
3447 static void
3448 micro_umin(union tgsi_exec_channel *dst,
3449 const union tgsi_exec_channel *src0,
3450 const union tgsi_exec_channel *src1)
3451 {
3452 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3453 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3454 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3455 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3456 }
3457
3458 static void
3459 micro_umod(union tgsi_exec_channel *dst,
3460 const union tgsi_exec_channel *src0,
3461 const union tgsi_exec_channel *src1)
3462 {
3463 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
3464 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
3465 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
3466 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
3467 }
3468
3469 static void
3470 micro_umul(union tgsi_exec_channel *dst,
3471 const union tgsi_exec_channel *src0,
3472 const union tgsi_exec_channel *src1)
3473 {
3474 dst->u[0] = src0->u[0] * src1->u[0];
3475 dst->u[1] = src0->u[1] * src1->u[1];
3476 dst->u[2] = src0->u[2] * src1->u[2];
3477 dst->u[3] = src0->u[3] * src1->u[3];
3478 }
3479
3480 static void
3481 micro_imul_hi(union tgsi_exec_channel *dst,
3482 const union tgsi_exec_channel *src0,
3483 const union tgsi_exec_channel *src1)
3484 {
3485 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3486 dst->i[0] = I64M(src0->i[0], src1->i[0]);
3487 dst->i[1] = I64M(src0->i[1], src1->i[1]);
3488 dst->i[2] = I64M(src0->i[2], src1->i[2]);
3489 dst->i[3] = I64M(src0->i[3], src1->i[3]);
3490 #undef I64M
3491 }
3492
3493 static void
3494 micro_umul_hi(union tgsi_exec_channel *dst,
3495 const union tgsi_exec_channel *src0,
3496 const union tgsi_exec_channel *src1)
3497 {
3498 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3499 dst->u[0] = U64M(src0->u[0], src1->u[0]);
3500 dst->u[1] = U64M(src0->u[1], src1->u[1]);
3501 dst->u[2] = U64M(src0->u[2], src1->u[2]);
3502 dst->u[3] = U64M(src0->u[3], src1->u[3]);
3503 #undef U64M
3504 }
3505
3506 static void
3507 micro_useq(union tgsi_exec_channel *dst,
3508 const union tgsi_exec_channel *src0,
3509 const union tgsi_exec_channel *src1)
3510 {
3511 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3512 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3513 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3514 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3515 }
3516
3517 static void
3518 micro_usge(union tgsi_exec_channel *dst,
3519 const union tgsi_exec_channel *src0,
3520 const union tgsi_exec_channel *src1)
3521 {
3522 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3523 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3524 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3525 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3526 }
3527
3528 static void
3529 micro_ushr(union tgsi_exec_channel *dst,
3530 const union tgsi_exec_channel *src0,
3531 const union tgsi_exec_channel *src1)
3532 {
3533 unsigned masked_count;
3534 masked_count = src1->u[0] & 0x1f;
3535 dst->u[0] = src0->u[0] >> masked_count;
3536 masked_count = src1->u[1] & 0x1f;
3537 dst->u[1] = src0->u[1] >> masked_count;
3538 masked_count = src1->u[2] & 0x1f;
3539 dst->u[2] = src0->u[2] >> masked_count;
3540 masked_count = src1->u[3] & 0x1f;
3541 dst->u[3] = src0->u[3] >> masked_count;
3542 }
3543
3544 static void
3545 micro_uslt(union tgsi_exec_channel *dst,
3546 const union tgsi_exec_channel *src0,
3547 const union tgsi_exec_channel *src1)
3548 {
3549 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3550 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3551 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3552 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3553 }
3554
3555 static void
3556 micro_usne(union tgsi_exec_channel *dst,
3557 const union tgsi_exec_channel *src0,
3558 const union tgsi_exec_channel *src1)
3559 {
3560 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3561 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3562 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3563 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3564 }
3565
3566 static void
3567 micro_uarl(union tgsi_exec_channel *dst,
3568 const union tgsi_exec_channel *src)
3569 {
3570 dst->i[0] = src->u[0];
3571 dst->i[1] = src->u[1];
3572 dst->i[2] = src->u[2];
3573 dst->i[3] = src->u[3];
3574 }
3575
3576 static void
3577 micro_ucmp(union tgsi_exec_channel *dst,
3578 const union tgsi_exec_channel *src0,
3579 const union tgsi_exec_channel *src1,
3580 const union tgsi_exec_channel *src2)
3581 {
3582 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3583 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3584 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3585 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3586 }
3587
3588 static void
3589 exec_instruction(
3590 struct tgsi_exec_machine *mach,
3591 const struct tgsi_full_instruction *inst,
3592 int *pc )
3593 {
3594 union tgsi_exec_channel r[10];
3595
3596 (*pc)++;
3597
3598 switch (inst->Instruction.Opcode) {
3599 case TGSI_OPCODE_ARL:
3600 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3601 break;
3602
3603 case TGSI_OPCODE_MOV:
3604 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3605 break;
3606
3607 case TGSI_OPCODE_LIT:
3608 exec_lit(mach, inst);
3609 break;
3610
3611 case TGSI_OPCODE_RCP:
3612 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3613 break;
3614
3615 case TGSI_OPCODE_RSQ:
3616 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3617 break;
3618
3619 case TGSI_OPCODE_EXP:
3620 exec_exp(mach, inst);
3621 break;
3622
3623 case TGSI_OPCODE_LOG:
3624 exec_log(mach, inst);
3625 break;
3626
3627 case TGSI_OPCODE_MUL:
3628 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3629 break;
3630
3631 case TGSI_OPCODE_ADD:
3632 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3633 break;
3634
3635 case TGSI_OPCODE_DP3:
3636 exec_dp3(mach, inst);
3637 break;
3638
3639 case TGSI_OPCODE_DP4:
3640 exec_dp4(mach, inst);
3641 break;
3642
3643 case TGSI_OPCODE_DST:
3644 exec_dst(mach, inst);
3645 break;
3646
3647 case TGSI_OPCODE_MIN:
3648 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3649 break;
3650
3651 case TGSI_OPCODE_MAX:
3652 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3653 break;
3654
3655 case TGSI_OPCODE_SLT:
3656 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3657 break;
3658
3659 case TGSI_OPCODE_SGE:
3660 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3661 break;
3662
3663 case TGSI_OPCODE_MAD:
3664 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3665 break;
3666
3667 case TGSI_OPCODE_SUB:
3668 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3669 break;
3670
3671 case TGSI_OPCODE_LRP:
3672 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3673 break;
3674
3675 case TGSI_OPCODE_CND:
3676 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3677 break;
3678
3679 case TGSI_OPCODE_SQRT:
3680 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3681 break;
3682
3683 case TGSI_OPCODE_DP2A:
3684 exec_dp2a(mach, inst);
3685 break;
3686
3687 case TGSI_OPCODE_FRC:
3688 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3689 break;
3690
3691 case TGSI_OPCODE_CLAMP:
3692 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3693 break;
3694
3695 case TGSI_OPCODE_FLR:
3696 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3697 break;
3698
3699 case TGSI_OPCODE_ROUND:
3700 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3701 break;
3702
3703 case TGSI_OPCODE_EX2:
3704 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3705 break;
3706
3707 case TGSI_OPCODE_LG2:
3708 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3709 break;
3710
3711 case TGSI_OPCODE_POW:
3712 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3713 break;
3714
3715 case TGSI_OPCODE_XPD:
3716 exec_xpd(mach, inst);
3717 break;
3718
3719 case TGSI_OPCODE_ABS:
3720 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3721 break;
3722
3723 case TGSI_OPCODE_RCC:
3724 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3725 break;
3726
3727 case TGSI_OPCODE_DPH:
3728 exec_dph(mach, inst);
3729 break;
3730
3731 case TGSI_OPCODE_COS:
3732 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3733 break;
3734
3735 case TGSI_OPCODE_DDX:
3736 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3737 break;
3738
3739 case TGSI_OPCODE_DDY:
3740 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3741 break;
3742
3743 case TGSI_OPCODE_KILL:
3744 exec_kill (mach, inst);
3745 break;
3746
3747 case TGSI_OPCODE_KILL_IF:
3748 exec_kill_if (mach, inst);
3749 break;
3750
3751 case TGSI_OPCODE_PK2H:
3752 assert (0);
3753 break;
3754
3755 case TGSI_OPCODE_PK2US:
3756 assert (0);
3757 break;
3758
3759 case TGSI_OPCODE_PK4B:
3760 assert (0);
3761 break;
3762
3763 case TGSI_OPCODE_PK4UB:
3764 assert (0);
3765 break;
3766
3767 case TGSI_OPCODE_RFL:
3768 exec_rfl(mach, inst);
3769 break;
3770
3771 case TGSI_OPCODE_SEQ:
3772 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3773 break;
3774
3775 case TGSI_OPCODE_SFL:
3776 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3777 break;
3778
3779 case TGSI_OPCODE_SGT:
3780 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3781 break;
3782
3783 case TGSI_OPCODE_SIN:
3784 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3785 break;
3786
3787 case TGSI_OPCODE_SLE:
3788 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3789 break;
3790
3791 case TGSI_OPCODE_SNE:
3792 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3793 break;
3794
3795 case TGSI_OPCODE_STR:
3796 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3797 break;
3798
3799 case TGSI_OPCODE_TEX:
3800 /* simple texture lookup */
3801 /* src[0] = texcoord */
3802 /* src[1] = sampler unit */
3803 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
3804 break;
3805
3806 case TGSI_OPCODE_TXB:
3807 /* Texture lookup with lod bias */
3808 /* src[0] = texcoord (src[0].w = LOD bias) */
3809 /* src[1] = sampler unit */
3810 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
3811 break;
3812
3813 case TGSI_OPCODE_TXD:
3814 /* Texture lookup with explict partial derivatives */
3815 /* src[0] = texcoord */
3816 /* src[1] = d[strq]/dx */
3817 /* src[2] = d[strq]/dy */
3818 /* src[3] = sampler unit */
3819 exec_txd(mach, inst);
3820 break;
3821
3822 case TGSI_OPCODE_TXL:
3823 /* Texture lookup with explit LOD */
3824 /* src[0] = texcoord (src[0].w = LOD) */
3825 /* src[1] = sampler unit */
3826 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
3827 break;
3828
3829 case TGSI_OPCODE_TXP:
3830 /* Texture lookup with projection */
3831 /* src[0] = texcoord (src[0].w = projection) */
3832 /* src[1] = sampler unit */
3833 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
3834 break;
3835
3836 case TGSI_OPCODE_UP2H:
3837 assert (0);
3838 break;
3839
3840 case TGSI_OPCODE_UP2US:
3841 assert (0);
3842 break;
3843
3844 case TGSI_OPCODE_UP4B:
3845 assert (0);
3846 break;
3847
3848 case TGSI_OPCODE_UP4UB:
3849 assert (0);
3850 break;
3851
3852 case TGSI_OPCODE_X2D:
3853 exec_x2d(mach, inst);
3854 break;
3855
3856 case TGSI_OPCODE_ARA:
3857 assert (0);
3858 break;
3859
3860 case TGSI_OPCODE_ARR:
3861 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3862 break;
3863
3864 case TGSI_OPCODE_BRA:
3865 assert (0);
3866 break;
3867
3868 case TGSI_OPCODE_CAL:
3869 /* skip the call if no execution channels are enabled */
3870 if (mach->ExecMask) {
3871 /* do the call */
3872
3873 /* First, record the depths of the execution stacks.
3874 * This is important for deeply nested/looped return statements.
3875 * We have to unwind the stacks by the correct amount. For a
3876 * real code generator, we could determine the number of entries
3877 * to pop off each stack with simple static analysis and avoid
3878 * implementing this data structure at run time.
3879 */
3880 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3881 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3882 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3883 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3884 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3885 /* note that PC was already incremented above */
3886 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3887
3888 mach->CallStackTop++;
3889
3890 /* Second, push the Cond, Loop, Cont, Func stacks */
3891 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3892 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3893 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3894 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3895 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3896 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3897
3898 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3899 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3900 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3901 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3902 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3903 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3904
3905 /* Finally, jump to the subroutine */
3906 *pc = inst->Label.Label;
3907 }
3908 break;
3909
3910 case TGSI_OPCODE_RET:
3911 mach->FuncMask &= ~mach->ExecMask;
3912 UPDATE_EXEC_MASK(mach);
3913
3914 if (mach->FuncMask == 0x0) {
3915 /* really return now (otherwise, keep executing */
3916
3917 if (mach->CallStackTop == 0) {
3918 /* returning from main() */
3919 mach->CondStackTop = 0;
3920 mach->LoopStackTop = 0;
3921 *pc = -1;
3922 return;
3923 }
3924
3925 assert(mach->CallStackTop > 0);
3926 mach->CallStackTop--;
3927
3928 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3929 mach->CondMask = mach->CondStack[mach->CondStackTop];
3930
3931 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3932 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3933
3934 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3935 mach->ContMask = mach->ContStack[mach->ContStackTop];
3936
3937 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3938 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3939
3940 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3941 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3942
3943 assert(mach->FuncStackTop > 0);
3944 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3945
3946 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3947
3948 UPDATE_EXEC_MASK(mach);
3949 }
3950 break;
3951
3952 case TGSI_OPCODE_SSG:
3953 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3954 break;
3955
3956 case TGSI_OPCODE_CMP:
3957 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3958 break;
3959
3960 case TGSI_OPCODE_SCS:
3961 exec_scs(mach, inst);
3962 break;
3963
3964 case TGSI_OPCODE_NRM:
3965 exec_nrm3(mach, inst);
3966 break;
3967
3968 case TGSI_OPCODE_NRM4:
3969 exec_nrm4(mach, inst);
3970 break;
3971
3972 case TGSI_OPCODE_DIV:
3973 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3974 break;
3975
3976 case TGSI_OPCODE_DP2:
3977 exec_dp2(mach, inst);
3978 break;
3979
3980 case TGSI_OPCODE_IF:
3981 /* push CondMask */
3982 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3983 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3984 FETCH( &r[0], 0, TGSI_CHAN_X );
3985 /* update CondMask */
3986 if( ! r[0].f[0] ) {
3987 mach->CondMask &= ~0x1;
3988 }
3989 if( ! r[0].f[1] ) {
3990 mach->CondMask &= ~0x2;
3991 }
3992 if( ! r[0].f[2] ) {
3993 mach->CondMask &= ~0x4;
3994 }
3995 if( ! r[0].f[3] ) {
3996 mach->CondMask &= ~0x8;
3997 }
3998 UPDATE_EXEC_MASK(mach);
3999 /* Todo: If CondMask==0, jump to ELSE */
4000 break;
4001
4002 case TGSI_OPCODE_UIF:
4003 /* push CondMask */
4004 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4005 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4006 IFETCH( &r[0], 0, TGSI_CHAN_X );
4007 /* update CondMask */
4008 if( ! r[0].u[0] ) {
4009 mach->CondMask &= ~0x1;
4010 }
4011 if( ! r[0].u[1] ) {
4012 mach->CondMask &= ~0x2;
4013 }
4014 if( ! r[0].u[2] ) {
4015 mach->CondMask &= ~0x4;
4016 }
4017 if( ! r[0].u[3] ) {
4018 mach->CondMask &= ~0x8;
4019 }
4020 UPDATE_EXEC_MASK(mach);
4021 /* Todo: If CondMask==0, jump to ELSE */
4022 break;
4023
4024 case TGSI_OPCODE_ELSE:
4025 /* invert CondMask wrt previous mask */
4026 {
4027 uint prevMask;
4028 assert(mach->CondStackTop > 0);
4029 prevMask = mach->CondStack[mach->CondStackTop - 1];
4030 mach->CondMask = ~mach->CondMask & prevMask;
4031 UPDATE_EXEC_MASK(mach);
4032 /* Todo: If CondMask==0, jump to ENDIF */
4033 }
4034 break;
4035
4036 case TGSI_OPCODE_ENDIF:
4037 /* pop CondMask */
4038 assert(mach->CondStackTop > 0);
4039 mach->CondMask = mach->CondStack[--mach->CondStackTop];
4040 UPDATE_EXEC_MASK(mach);
4041 break;
4042
4043 case TGSI_OPCODE_END:
4044 /* make sure we end primitives which haven't
4045 * been explicitly emitted */
4046 conditional_emit_primitive(mach);
4047 /* halt execution */
4048 *pc = -1;
4049 break;
4050
4051 case TGSI_OPCODE_PUSHA:
4052 assert (0);
4053 break;
4054
4055 case TGSI_OPCODE_POPA:
4056 assert (0);
4057 break;
4058
4059 case TGSI_OPCODE_CEIL:
4060 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4061 break;
4062
4063 case TGSI_OPCODE_I2F:
4064 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
4065 break;
4066
4067 case TGSI_OPCODE_NOT:
4068 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4069 break;
4070
4071 case TGSI_OPCODE_TRUNC:
4072 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4073 break;
4074
4075 case TGSI_OPCODE_SHL:
4076 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4077 break;
4078
4079 case TGSI_OPCODE_AND:
4080 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4081 break;
4082
4083 case TGSI_OPCODE_OR:
4084 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4085 break;
4086
4087 case TGSI_OPCODE_MOD:
4088 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4089 break;
4090
4091 case TGSI_OPCODE_XOR:
4092 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4093 break;
4094
4095 case TGSI_OPCODE_SAD:
4096 assert (0);
4097 break;
4098
4099 case TGSI_OPCODE_TXF:
4100 exec_txf(mach, inst);
4101 break;
4102
4103 case TGSI_OPCODE_TXQ:
4104 exec_txq(mach, inst);
4105 break;
4106
4107 case TGSI_OPCODE_EMIT:
4108 emit_vertex(mach);
4109 break;
4110
4111 case TGSI_OPCODE_ENDPRIM:
4112 emit_primitive(mach);
4113 break;
4114
4115 case TGSI_OPCODE_BGNLOOP:
4116 /* push LoopMask and ContMasks */
4117 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4118 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4119 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4120 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4121
4122 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4123 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4124 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4125 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4126 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4127 break;
4128
4129 case TGSI_OPCODE_ENDLOOP:
4130 /* Restore ContMask, but don't pop */
4131 assert(mach->ContStackTop > 0);
4132 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4133 UPDATE_EXEC_MASK(mach);
4134 if (mach->ExecMask) {
4135 /* repeat loop: jump to instruction just past BGNLOOP */
4136 assert(mach->LoopLabelStackTop > 0);
4137 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4138 }
4139 else {
4140 /* exit loop: pop LoopMask */
4141 assert(mach->LoopStackTop > 0);
4142 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4143 /* pop ContMask */
4144 assert(mach->ContStackTop > 0);
4145 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4146 assert(mach->LoopLabelStackTop > 0);
4147 --mach->LoopLabelStackTop;
4148
4149 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4150 }
4151 UPDATE_EXEC_MASK(mach);
4152 break;
4153
4154 case TGSI_OPCODE_BRK:
4155 exec_break(mach);
4156 break;
4157
4158 case TGSI_OPCODE_CONT:
4159 /* turn off cont channels for each enabled exec channel */
4160 mach->ContMask &= ~mach->ExecMask;
4161 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4162 UPDATE_EXEC_MASK(mach);
4163 break;
4164
4165 case TGSI_OPCODE_BGNSUB:
4166 /* no-op */
4167 break;
4168
4169 case TGSI_OPCODE_ENDSUB:
4170 /*
4171 * XXX: This really should be a no-op. We should never reach this opcode.
4172 */
4173
4174 assert(mach->CallStackTop > 0);
4175 mach->CallStackTop--;
4176
4177 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4178 mach->CondMask = mach->CondStack[mach->CondStackTop];
4179
4180 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4181 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4182
4183 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4184 mach->ContMask = mach->ContStack[mach->ContStackTop];
4185
4186 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4187 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4188
4189 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4190 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4191
4192 assert(mach->FuncStackTop > 0);
4193 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4194
4195 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4196
4197 UPDATE_EXEC_MASK(mach);
4198 break;
4199
4200 case TGSI_OPCODE_NOP:
4201 break;
4202
4203 case TGSI_OPCODE_BREAKC:
4204 IFETCH(&r[0], 0, TGSI_CHAN_X);
4205 /* update CondMask */
4206 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4207 mach->LoopMask &= ~0x1;
4208 }
4209 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4210 mach->LoopMask &= ~0x2;
4211 }
4212 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4213 mach->LoopMask &= ~0x4;
4214 }
4215 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4216 mach->LoopMask &= ~0x8;
4217 }
4218 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4219 UPDATE_EXEC_MASK(mach);
4220 break;
4221
4222 case TGSI_OPCODE_F2I:
4223 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4224 break;
4225
4226 case TGSI_OPCODE_FSEQ:
4227 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4228 break;
4229
4230 case TGSI_OPCODE_FSGE:
4231 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4232 break;
4233
4234 case TGSI_OPCODE_FSLT:
4235 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4236 break;
4237
4238 case TGSI_OPCODE_FSNE:
4239 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4240 break;
4241
4242 case TGSI_OPCODE_IDIV:
4243 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4244 break;
4245
4246 case TGSI_OPCODE_IMAX:
4247 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4248 break;
4249
4250 case TGSI_OPCODE_IMIN:
4251 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4252 break;
4253
4254 case TGSI_OPCODE_INEG:
4255 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4256 break;
4257
4258 case TGSI_OPCODE_ISGE:
4259 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4260 break;
4261
4262 case TGSI_OPCODE_ISHR:
4263 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4264 break;
4265
4266 case TGSI_OPCODE_ISLT:
4267 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4268 break;
4269
4270 case TGSI_OPCODE_F2U:
4271 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4272 break;
4273
4274 case TGSI_OPCODE_U2F:
4275 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4276 break;
4277
4278 case TGSI_OPCODE_UADD:
4279 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4280 break;
4281
4282 case TGSI_OPCODE_UDIV:
4283 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4284 break;
4285
4286 case TGSI_OPCODE_UMAD:
4287 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4288 break;
4289
4290 case TGSI_OPCODE_UMAX:
4291 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4292 break;
4293
4294 case TGSI_OPCODE_UMIN:
4295 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4296 break;
4297
4298 case TGSI_OPCODE_UMOD:
4299 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4300 break;
4301
4302 case TGSI_OPCODE_UMUL:
4303 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4304 break;
4305
4306 case TGSI_OPCODE_IMUL_HI:
4307 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4308 break;
4309
4310 case TGSI_OPCODE_UMUL_HI:
4311 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4312 break;
4313
4314 case TGSI_OPCODE_USEQ:
4315 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4316 break;
4317
4318 case TGSI_OPCODE_USGE:
4319 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4320 break;
4321
4322 case TGSI_OPCODE_USHR:
4323 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4324 break;
4325
4326 case TGSI_OPCODE_USLT:
4327 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4328 break;
4329
4330 case TGSI_OPCODE_USNE:
4331 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4332 break;
4333
4334 case TGSI_OPCODE_SWITCH:
4335 exec_switch(mach, inst);
4336 break;
4337
4338 case TGSI_OPCODE_CASE:
4339 exec_case(mach, inst);
4340 break;
4341
4342 case TGSI_OPCODE_DEFAULT:
4343 exec_default(mach);
4344 break;
4345
4346 case TGSI_OPCODE_ENDSWITCH:
4347 exec_endswitch(mach);
4348 break;
4349
4350 case TGSI_OPCODE_SAMPLE_I:
4351 exec_txf(mach, inst);
4352 break;
4353
4354 case TGSI_OPCODE_SAMPLE_I_MS:
4355 assert(0);
4356 break;
4357
4358 case TGSI_OPCODE_SAMPLE:
4359 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4360 break;
4361
4362 case TGSI_OPCODE_SAMPLE_B:
4363 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4364 break;
4365
4366 case TGSI_OPCODE_SAMPLE_C:
4367 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4368 break;
4369
4370 case TGSI_OPCODE_SAMPLE_C_LZ:
4371 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4372 break;
4373
4374 case TGSI_OPCODE_SAMPLE_D:
4375 exec_sample_d(mach, inst);
4376 break;
4377
4378 case TGSI_OPCODE_SAMPLE_L:
4379 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4380 break;
4381
4382 case TGSI_OPCODE_GATHER4:
4383 assert(0);
4384 break;
4385
4386 case TGSI_OPCODE_SVIEWINFO:
4387 exec_txq(mach, inst);
4388 break;
4389
4390 case TGSI_OPCODE_SAMPLE_POS:
4391 assert(0);
4392 break;
4393
4394 case TGSI_OPCODE_SAMPLE_INFO:
4395 assert(0);
4396 break;
4397
4398 case TGSI_OPCODE_UARL:
4399 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4400 break;
4401
4402 case TGSI_OPCODE_UCMP:
4403 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4404 break;
4405
4406 case TGSI_OPCODE_IABS:
4407 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4408 break;
4409
4410 case TGSI_OPCODE_ISSG:
4411 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4412 break;
4413
4414 case TGSI_OPCODE_TEX2:
4415 /* simple texture lookup */
4416 /* src[0] = texcoord */
4417 /* src[1] = compare */
4418 /* src[2] = sampler unit */
4419 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4420 break;
4421 case TGSI_OPCODE_TXB2:
4422 /* simple texture lookup */
4423 /* src[0] = texcoord */
4424 /* src[1] = bias */
4425 /* src[2] = sampler unit */
4426 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4427 break;
4428 case TGSI_OPCODE_TXL2:
4429 /* simple texture lookup */
4430 /* src[0] = texcoord */
4431 /* src[1] = lod */
4432 /* src[2] = sampler unit */
4433 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4434 break;
4435 default:
4436 assert( 0 );
4437 }
4438 }
4439
4440
4441 /**
4442 * Run TGSI interpreter.
4443 * \return bitmask of "alive" quad components
4444 */
4445 uint
4446 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4447 {
4448 uint i;
4449 int pc = 0;
4450 uint default_mask = 0xf;
4451
4452 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4453 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4454
4455 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4456 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4457 mach->Primitives[0] = 0;
4458 /* GS runs on a single primitive for now */
4459 default_mask = 0x1;
4460 }
4461
4462 mach->CondMask = default_mask;
4463 mach->LoopMask = default_mask;
4464 mach->ContMask = default_mask;
4465 mach->FuncMask = default_mask;
4466 mach->ExecMask = default_mask;
4467
4468 mach->Switch.mask = default_mask;
4469
4470 assert(mach->CondStackTop == 0);
4471 assert(mach->LoopStackTop == 0);
4472 assert(mach->ContStackTop == 0);
4473 assert(mach->SwitchStackTop == 0);
4474 assert(mach->BreakStackTop == 0);
4475 assert(mach->CallStackTop == 0);
4476
4477
4478 /* execute declarations (interpolants) */
4479 for (i = 0; i < mach->NumDeclarations; i++) {
4480 exec_declaration( mach, mach->Declarations+i );
4481 }
4482
4483 {
4484 #if DEBUG_EXECUTION
4485 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4486 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4487 uint inst = 1;
4488
4489 memset(mach->Temps, 0, sizeof(temps));
4490 memset(mach->Outputs, 0, sizeof(outputs));
4491 memset(temps, 0, sizeof(temps));
4492 memset(outputs, 0, sizeof(outputs));
4493 #endif
4494
4495 /* execute instructions, until pc is set to -1 */
4496 while (pc != -1) {
4497
4498 #if DEBUG_EXECUTION
4499 uint i;
4500
4501 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4502 #endif
4503
4504 assert(pc < (int) mach->NumInstructions);
4505 exec_instruction(mach, mach->Instructions + pc, &pc);
4506
4507 #if DEBUG_EXECUTION
4508 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4509 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4510 uint j;
4511
4512 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4513 debug_printf("TEMP[%2u] = ", i);
4514 for (j = 0; j < 4; j++) {
4515 if (j > 0) {
4516 debug_printf(" ");
4517 }
4518 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4519 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4520 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4521 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4522 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4523 }
4524 }
4525 }
4526 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4527 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4528 uint j;
4529
4530 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4531 debug_printf("OUT[%2u] = ", i);
4532 for (j = 0; j < 4; j++) {
4533 if (j > 0) {
4534 debug_printf(" ");
4535 }
4536 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4537 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4538 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4539 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4540 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4541 }
4542 }
4543 }
4544 #endif
4545 }
4546 }
4547
4548 #if 0
4549 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4550 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4551 /*
4552 * Scale back depth component.
4553 */
4554 for (i = 0; i < 4; i++)
4555 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4556 }
4557 #endif
4558
4559 /* Strictly speaking, these assertions aren't really needed but they
4560 * can potentially catch some bugs in the control flow code.
4561 */
4562 assert(mach->CondStackTop == 0);
4563 assert(mach->LoopStackTop == 0);
4564 assert(mach->ContStackTop == 0);
4565 assert(mach->SwitchStackTop == 0);
4566 assert(mach->BreakStackTop == 0);
4567 assert(mach->CallStackTop == 0);
4568
4569 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4570 }