1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
67 #define DEBUG_EXECUTION 0
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
77 union tgsi_double_channel
{
78 double d
[TGSI_QUAD_SIZE
];
79 unsigned u
[TGSI_QUAD_SIZE
][2];
80 uint64_t u64
[TGSI_QUAD_SIZE
];
81 int64_t i64
[TGSI_QUAD_SIZE
];
84 struct tgsi_double_vector
{
85 union tgsi_double_channel xy
;
86 union tgsi_double_channel zw
;
90 micro_abs(union tgsi_exec_channel
*dst
,
91 const union tgsi_exec_channel
*src
)
93 dst
->f
[0] = fabsf(src
->f
[0]);
94 dst
->f
[1] = fabsf(src
->f
[1]);
95 dst
->f
[2] = fabsf(src
->f
[2]);
96 dst
->f
[3] = fabsf(src
->f
[3]);
100 micro_arl(union tgsi_exec_channel
*dst
,
101 const union tgsi_exec_channel
*src
)
103 dst
->i
[0] = (int)floorf(src
->f
[0]);
104 dst
->i
[1] = (int)floorf(src
->f
[1]);
105 dst
->i
[2] = (int)floorf(src
->f
[2]);
106 dst
->i
[3] = (int)floorf(src
->f
[3]);
110 micro_arr(union tgsi_exec_channel
*dst
,
111 const union tgsi_exec_channel
*src
)
113 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
114 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
115 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
116 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
120 micro_ceil(union tgsi_exec_channel
*dst
,
121 const union tgsi_exec_channel
*src
)
123 dst
->f
[0] = ceilf(src
->f
[0]);
124 dst
->f
[1] = ceilf(src
->f
[1]);
125 dst
->f
[2] = ceilf(src
->f
[2]);
126 dst
->f
[3] = ceilf(src
->f
[3]);
130 micro_clamp(union tgsi_exec_channel
*dst
,
131 const union tgsi_exec_channel
*src0
,
132 const union tgsi_exec_channel
*src1
,
133 const union tgsi_exec_channel
*src2
)
135 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src1
->f
[0] : src0
->f
[0] > src2
->f
[0] ? src2
->f
[0] : src0
->f
[0];
136 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src1
->f
[1] : src0
->f
[1] > src2
->f
[1] ? src2
->f
[1] : src0
->f
[1];
137 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src1
->f
[2] : src0
->f
[2] > src2
->f
[2] ? src2
->f
[2] : src0
->f
[2];
138 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src1
->f
[3] : src0
->f
[3] > src2
->f
[3] ? src2
->f
[3] : src0
->f
[3];
142 micro_cmp(union tgsi_exec_channel
*dst
,
143 const union tgsi_exec_channel
*src0
,
144 const union tgsi_exec_channel
*src1
,
145 const union tgsi_exec_channel
*src2
)
147 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
148 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
149 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
150 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
154 micro_cos(union tgsi_exec_channel
*dst
,
155 const union tgsi_exec_channel
*src
)
157 dst
->f
[0] = cosf(src
->f
[0]);
158 dst
->f
[1] = cosf(src
->f
[1]);
159 dst
->f
[2] = cosf(src
->f
[2]);
160 dst
->f
[3] = cosf(src
->f
[3]);
164 micro_d2f(union tgsi_exec_channel
*dst
,
165 const union tgsi_double_channel
*src
)
167 dst
->f
[0] = (float)src
->d
[0];
168 dst
->f
[1] = (float)src
->d
[1];
169 dst
->f
[2] = (float)src
->d
[2];
170 dst
->f
[3] = (float)src
->d
[3];
174 micro_d2i(union tgsi_exec_channel
*dst
,
175 const union tgsi_double_channel
*src
)
177 dst
->i
[0] = (int)src
->d
[0];
178 dst
->i
[1] = (int)src
->d
[1];
179 dst
->i
[2] = (int)src
->d
[2];
180 dst
->i
[3] = (int)src
->d
[3];
184 micro_d2u(union tgsi_exec_channel
*dst
,
185 const union tgsi_double_channel
*src
)
187 dst
->u
[0] = (unsigned)src
->d
[0];
188 dst
->u
[1] = (unsigned)src
->d
[1];
189 dst
->u
[2] = (unsigned)src
->d
[2];
190 dst
->u
[3] = (unsigned)src
->d
[3];
193 micro_dabs(union tgsi_double_channel
*dst
,
194 const union tgsi_double_channel
*src
)
196 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
197 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
198 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
199 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
203 micro_dadd(union tgsi_double_channel
*dst
,
204 const union tgsi_double_channel
*src
)
206 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
207 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
208 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
209 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
213 micro_ddx(union tgsi_exec_channel
*dst
,
214 const union tgsi_exec_channel
*src
)
219 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
223 micro_ddy(union tgsi_exec_channel
*dst
,
224 const union tgsi_exec_channel
*src
)
229 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
233 micro_dmul(union tgsi_double_channel
*dst
,
234 const union tgsi_double_channel
*src
)
236 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
237 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
238 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
239 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
243 micro_dmax(union tgsi_double_channel
*dst
,
244 const union tgsi_double_channel
*src
)
246 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
247 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
248 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
249 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
253 micro_dmin(union tgsi_double_channel
*dst
,
254 const union tgsi_double_channel
*src
)
256 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
257 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
258 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
259 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
263 micro_dneg(union tgsi_double_channel
*dst
,
264 const union tgsi_double_channel
*src
)
266 dst
->d
[0] = -src
->d
[0];
267 dst
->d
[1] = -src
->d
[1];
268 dst
->d
[2] = -src
->d
[2];
269 dst
->d
[3] = -src
->d
[3];
273 micro_dslt(union tgsi_double_channel
*dst
,
274 const union tgsi_double_channel
*src
)
276 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
277 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
278 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
279 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
283 micro_dsne(union tgsi_double_channel
*dst
,
284 const union tgsi_double_channel
*src
)
286 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
287 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
288 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
289 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
293 micro_dsge(union tgsi_double_channel
*dst
,
294 const union tgsi_double_channel
*src
)
296 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
297 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
298 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
299 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
303 micro_dseq(union tgsi_double_channel
*dst
,
304 const union tgsi_double_channel
*src
)
306 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
307 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
308 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
309 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
313 micro_drcp(union tgsi_double_channel
*dst
,
314 const union tgsi_double_channel
*src
)
316 dst
->d
[0] = 1.0 / src
->d
[0];
317 dst
->d
[1] = 1.0 / src
->d
[1];
318 dst
->d
[2] = 1.0 / src
->d
[2];
319 dst
->d
[3] = 1.0 / src
->d
[3];
323 micro_dsqrt(union tgsi_double_channel
*dst
,
324 const union tgsi_double_channel
*src
)
326 dst
->d
[0] = sqrt(src
->d
[0]);
327 dst
->d
[1] = sqrt(src
->d
[1]);
328 dst
->d
[2] = sqrt(src
->d
[2]);
329 dst
->d
[3] = sqrt(src
->d
[3]);
333 micro_drsq(union tgsi_double_channel
*dst
,
334 const union tgsi_double_channel
*src
)
336 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
337 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
338 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
339 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
343 micro_dmad(union tgsi_double_channel
*dst
,
344 const union tgsi_double_channel
*src
)
346 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
347 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
348 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
349 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
353 micro_dfrac(union tgsi_double_channel
*dst
,
354 const union tgsi_double_channel
*src
)
356 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
357 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
358 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
359 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
363 micro_dldexp(union tgsi_double_channel
*dst
,
364 const union tgsi_double_channel
*src0
,
365 union tgsi_exec_channel
*src1
)
367 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
368 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
369 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
370 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
374 micro_dfracexp(union tgsi_double_channel
*dst
,
375 union tgsi_exec_channel
*dst_exp
,
376 const union tgsi_double_channel
*src
)
378 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
379 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
380 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
381 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
385 micro_exp2(union tgsi_exec_channel
*dst
,
386 const union tgsi_exec_channel
*src
)
389 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
390 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
391 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
392 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
395 /* Inf is okay for this instruction, so clamp it to silence assertions. */
397 union tgsi_exec_channel clamped
;
399 for (i
= 0; i
< 4; i
++) {
400 if (src
->f
[i
] > 127.99999f
) {
401 clamped
.f
[i
] = 127.99999f
;
402 } else if (src
->f
[i
] < -126.99999f
) {
403 clamped
.f
[i
] = -126.99999f
;
405 clamped
.f
[i
] = src
->f
[i
];
411 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
412 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
413 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
414 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
415 #endif /* FAST_MATH */
419 micro_f2d(union tgsi_double_channel
*dst
,
420 const union tgsi_exec_channel
*src
)
422 dst
->d
[0] = (double)src
->f
[0];
423 dst
->d
[1] = (double)src
->f
[1];
424 dst
->d
[2] = (double)src
->f
[2];
425 dst
->d
[3] = (double)src
->f
[3];
429 micro_flr(union tgsi_exec_channel
*dst
,
430 const union tgsi_exec_channel
*src
)
432 dst
->f
[0] = floorf(src
->f
[0]);
433 dst
->f
[1] = floorf(src
->f
[1]);
434 dst
->f
[2] = floorf(src
->f
[2]);
435 dst
->f
[3] = floorf(src
->f
[3]);
439 micro_frc(union tgsi_exec_channel
*dst
,
440 const union tgsi_exec_channel
*src
)
442 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
443 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
444 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
445 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
449 micro_i2d(union tgsi_double_channel
*dst
,
450 const union tgsi_exec_channel
*src
)
452 dst
->d
[0] = (double)src
->i
[0];
453 dst
->d
[1] = (double)src
->i
[1];
454 dst
->d
[2] = (double)src
->i
[2];
455 dst
->d
[3] = (double)src
->i
[3];
459 micro_iabs(union tgsi_exec_channel
*dst
,
460 const union tgsi_exec_channel
*src
)
462 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
463 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
464 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
465 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
469 micro_ineg(union tgsi_exec_channel
*dst
,
470 const union tgsi_exec_channel
*src
)
472 dst
->i
[0] = -src
->i
[0];
473 dst
->i
[1] = -src
->i
[1];
474 dst
->i
[2] = -src
->i
[2];
475 dst
->i
[3] = -src
->i
[3];
479 micro_lg2(union tgsi_exec_channel
*dst
,
480 const union tgsi_exec_channel
*src
)
483 dst
->f
[0] = util_fast_log2(src
->f
[0]);
484 dst
->f
[1] = util_fast_log2(src
->f
[1]);
485 dst
->f
[2] = util_fast_log2(src
->f
[2]);
486 dst
->f
[3] = util_fast_log2(src
->f
[3]);
488 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
489 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
490 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
491 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
496 micro_lrp(union tgsi_exec_channel
*dst
,
497 const union tgsi_exec_channel
*src0
,
498 const union tgsi_exec_channel
*src1
,
499 const union tgsi_exec_channel
*src2
)
501 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
502 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
503 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
504 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
508 micro_mad(union tgsi_exec_channel
*dst
,
509 const union tgsi_exec_channel
*src0
,
510 const union tgsi_exec_channel
*src1
,
511 const union tgsi_exec_channel
*src2
)
513 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
514 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
515 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
516 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
520 micro_mov(union tgsi_exec_channel
*dst
,
521 const union tgsi_exec_channel
*src
)
523 dst
->u
[0] = src
->u
[0];
524 dst
->u
[1] = src
->u
[1];
525 dst
->u
[2] = src
->u
[2];
526 dst
->u
[3] = src
->u
[3];
530 micro_rcp(union tgsi_exec_channel
*dst
,
531 const union tgsi_exec_channel
*src
)
533 #if 0 /* for debugging */
534 assert(src
->f
[0] != 0.0f
);
535 assert(src
->f
[1] != 0.0f
);
536 assert(src
->f
[2] != 0.0f
);
537 assert(src
->f
[3] != 0.0f
);
539 dst
->f
[0] = 1.0f
/ src
->f
[0];
540 dst
->f
[1] = 1.0f
/ src
->f
[1];
541 dst
->f
[2] = 1.0f
/ src
->f
[2];
542 dst
->f
[3] = 1.0f
/ src
->f
[3];
546 micro_rnd(union tgsi_exec_channel
*dst
,
547 const union tgsi_exec_channel
*src
)
549 dst
->f
[0] = _mesa_roundevenf(src
->f
[0]);
550 dst
->f
[1] = _mesa_roundevenf(src
->f
[1]);
551 dst
->f
[2] = _mesa_roundevenf(src
->f
[2]);
552 dst
->f
[3] = _mesa_roundevenf(src
->f
[3]);
556 micro_rsq(union tgsi_exec_channel
*dst
,
557 const union tgsi_exec_channel
*src
)
559 #if 0 /* for debugging */
560 assert(src
->f
[0] != 0.0f
);
561 assert(src
->f
[1] != 0.0f
);
562 assert(src
->f
[2] != 0.0f
);
563 assert(src
->f
[3] != 0.0f
);
565 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
566 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
567 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
568 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
572 micro_sqrt(union tgsi_exec_channel
*dst
,
573 const union tgsi_exec_channel
*src
)
575 dst
->f
[0] = sqrtf(src
->f
[0]);
576 dst
->f
[1] = sqrtf(src
->f
[1]);
577 dst
->f
[2] = sqrtf(src
->f
[2]);
578 dst
->f
[3] = sqrtf(src
->f
[3]);
582 micro_seq(union tgsi_exec_channel
*dst
,
583 const union tgsi_exec_channel
*src0
,
584 const union tgsi_exec_channel
*src1
)
586 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
587 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
588 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
589 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
593 micro_sge(union tgsi_exec_channel
*dst
,
594 const union tgsi_exec_channel
*src0
,
595 const union tgsi_exec_channel
*src1
)
597 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
598 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
599 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
600 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
604 micro_sgn(union tgsi_exec_channel
*dst
,
605 const union tgsi_exec_channel
*src
)
607 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
608 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
609 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
610 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
614 micro_isgn(union tgsi_exec_channel
*dst
,
615 const union tgsi_exec_channel
*src
)
617 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
618 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
619 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
620 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
624 micro_sgt(union tgsi_exec_channel
*dst
,
625 const union tgsi_exec_channel
*src0
,
626 const union tgsi_exec_channel
*src1
)
628 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
629 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
630 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
631 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
635 micro_sin(union tgsi_exec_channel
*dst
,
636 const union tgsi_exec_channel
*src
)
638 dst
->f
[0] = sinf(src
->f
[0]);
639 dst
->f
[1] = sinf(src
->f
[1]);
640 dst
->f
[2] = sinf(src
->f
[2]);
641 dst
->f
[3] = sinf(src
->f
[3]);
645 micro_sle(union tgsi_exec_channel
*dst
,
646 const union tgsi_exec_channel
*src0
,
647 const union tgsi_exec_channel
*src1
)
649 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
650 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
651 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
652 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
656 micro_slt(union tgsi_exec_channel
*dst
,
657 const union tgsi_exec_channel
*src0
,
658 const union tgsi_exec_channel
*src1
)
660 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
661 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
662 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
663 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
667 micro_sne(union tgsi_exec_channel
*dst
,
668 const union tgsi_exec_channel
*src0
,
669 const union tgsi_exec_channel
*src1
)
671 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
672 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
673 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
674 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
678 micro_trunc(union tgsi_exec_channel
*dst
,
679 const union tgsi_exec_channel
*src
)
681 dst
->f
[0] = truncf(src
->f
[0]);
682 dst
->f
[1] = truncf(src
->f
[1]);
683 dst
->f
[2] = truncf(src
->f
[2]);
684 dst
->f
[3] = truncf(src
->f
[3]);
688 micro_u2d(union tgsi_double_channel
*dst
,
689 const union tgsi_exec_channel
*src
)
691 dst
->d
[0] = (double)src
->u
[0];
692 dst
->d
[1] = (double)src
->u
[1];
693 dst
->d
[2] = (double)src
->u
[2];
694 dst
->d
[3] = (double)src
->u
[3];
698 micro_i64abs(union tgsi_double_channel
*dst
,
699 const union tgsi_double_channel
*src
)
701 dst
->i64
[0] = src
->i64
[0] >= 0.0 ? src
->i64
[0] : -src
->i64
[0];
702 dst
->i64
[1] = src
->i64
[1] >= 0.0 ? src
->i64
[1] : -src
->i64
[1];
703 dst
->i64
[2] = src
->i64
[2] >= 0.0 ? src
->i64
[2] : -src
->i64
[2];
704 dst
->i64
[3] = src
->i64
[3] >= 0.0 ? src
->i64
[3] : -src
->i64
[3];
708 micro_i64sgn(union tgsi_double_channel
*dst
,
709 const union tgsi_double_channel
*src
)
711 dst
->i64
[0] = src
->i64
[0] < 0 ? -1 : src
->i64
[0] > 0 ? 1 : 0;
712 dst
->i64
[1] = src
->i64
[1] < 0 ? -1 : src
->i64
[1] > 0 ? 1 : 0;
713 dst
->i64
[2] = src
->i64
[2] < 0 ? -1 : src
->i64
[2] > 0 ? 1 : 0;
714 dst
->i64
[3] = src
->i64
[3] < 0 ? -1 : src
->i64
[3] > 0 ? 1 : 0;
718 micro_i64neg(union tgsi_double_channel
*dst
,
719 const union tgsi_double_channel
*src
)
721 dst
->i64
[0] = -src
->i64
[0];
722 dst
->i64
[1] = -src
->i64
[1];
723 dst
->i64
[2] = -src
->i64
[2];
724 dst
->i64
[3] = -src
->i64
[3];
728 micro_u64seq(union tgsi_double_channel
*dst
,
729 const union tgsi_double_channel
*src
)
731 dst
->u
[0][0] = src
[0].u64
[0] == src
[1].u64
[0] ? ~0U : 0U;
732 dst
->u
[1][0] = src
[0].u64
[1] == src
[1].u64
[1] ? ~0U : 0U;
733 dst
->u
[2][0] = src
[0].u64
[2] == src
[1].u64
[2] ? ~0U : 0U;
734 dst
->u
[3][0] = src
[0].u64
[3] == src
[1].u64
[3] ? ~0U : 0U;
738 micro_u64sne(union tgsi_double_channel
*dst
,
739 const union tgsi_double_channel
*src
)
741 dst
->u
[0][0] = src
[0].u64
[0] != src
[1].u64
[0] ? ~0U : 0U;
742 dst
->u
[1][0] = src
[0].u64
[1] != src
[1].u64
[1] ? ~0U : 0U;
743 dst
->u
[2][0] = src
[0].u64
[2] != src
[1].u64
[2] ? ~0U : 0U;
744 dst
->u
[3][0] = src
[0].u64
[3] != src
[1].u64
[3] ? ~0U : 0U;
748 micro_i64slt(union tgsi_double_channel
*dst
,
749 const union tgsi_double_channel
*src
)
751 dst
->u
[0][0] = src
[0].i64
[0] < src
[1].i64
[0] ? ~0U : 0U;
752 dst
->u
[1][0] = src
[0].i64
[1] < src
[1].i64
[1] ? ~0U : 0U;
753 dst
->u
[2][0] = src
[0].i64
[2] < src
[1].i64
[2] ? ~0U : 0U;
754 dst
->u
[3][0] = src
[0].i64
[3] < src
[1].i64
[3] ? ~0U : 0U;
758 micro_u64slt(union tgsi_double_channel
*dst
,
759 const union tgsi_double_channel
*src
)
761 dst
->u
[0][0] = src
[0].u64
[0] < src
[1].u64
[0] ? ~0U : 0U;
762 dst
->u
[1][0] = src
[0].u64
[1] < src
[1].u64
[1] ? ~0U : 0U;
763 dst
->u
[2][0] = src
[0].u64
[2] < src
[1].u64
[2] ? ~0U : 0U;
764 dst
->u
[3][0] = src
[0].u64
[3] < src
[1].u64
[3] ? ~0U : 0U;
768 micro_i64sge(union tgsi_double_channel
*dst
,
769 const union tgsi_double_channel
*src
)
771 dst
->u
[0][0] = src
[0].i64
[0] >= src
[1].i64
[0] ? ~0U : 0U;
772 dst
->u
[1][0] = src
[0].i64
[1] >= src
[1].i64
[1] ? ~0U : 0U;
773 dst
->u
[2][0] = src
[0].i64
[2] >= src
[1].i64
[2] ? ~0U : 0U;
774 dst
->u
[3][0] = src
[0].i64
[3] >= src
[1].i64
[3] ? ~0U : 0U;
778 micro_u64sge(union tgsi_double_channel
*dst
,
779 const union tgsi_double_channel
*src
)
781 dst
->u
[0][0] = src
[0].u64
[0] >= src
[1].u64
[0] ? ~0U : 0U;
782 dst
->u
[1][0] = src
[0].u64
[1] >= src
[1].u64
[1] ? ~0U : 0U;
783 dst
->u
[2][0] = src
[0].u64
[2] >= src
[1].u64
[2] ? ~0U : 0U;
784 dst
->u
[3][0] = src
[0].u64
[3] >= src
[1].u64
[3] ? ~0U : 0U;
788 micro_u64max(union tgsi_double_channel
*dst
,
789 const union tgsi_double_channel
*src
)
791 dst
->u64
[0] = src
[0].u64
[0] > src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
792 dst
->u64
[1] = src
[0].u64
[1] > src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
793 dst
->u64
[2] = src
[0].u64
[2] > src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
794 dst
->u64
[3] = src
[0].u64
[3] > src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
798 micro_i64max(union tgsi_double_channel
*dst
,
799 const union tgsi_double_channel
*src
)
801 dst
->i64
[0] = src
[0].i64
[0] > src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
802 dst
->i64
[1] = src
[0].i64
[1] > src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
803 dst
->i64
[2] = src
[0].i64
[2] > src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
804 dst
->i64
[3] = src
[0].i64
[3] > src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
808 micro_u64min(union tgsi_double_channel
*dst
,
809 const union tgsi_double_channel
*src
)
811 dst
->u64
[0] = src
[0].u64
[0] < src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
812 dst
->u64
[1] = src
[0].u64
[1] < src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
813 dst
->u64
[2] = src
[0].u64
[2] < src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
814 dst
->u64
[3] = src
[0].u64
[3] < src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
818 micro_i64min(union tgsi_double_channel
*dst
,
819 const union tgsi_double_channel
*src
)
821 dst
->i64
[0] = src
[0].i64
[0] < src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
822 dst
->i64
[1] = src
[0].i64
[1] < src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
823 dst
->i64
[2] = src
[0].i64
[2] < src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
824 dst
->i64
[3] = src
[0].i64
[3] < src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
828 micro_u64add(union tgsi_double_channel
*dst
,
829 const union tgsi_double_channel
*src
)
831 dst
->u64
[0] = src
[0].u64
[0] + src
[1].u64
[0];
832 dst
->u64
[1] = src
[0].u64
[1] + src
[1].u64
[1];
833 dst
->u64
[2] = src
[0].u64
[2] + src
[1].u64
[2];
834 dst
->u64
[3] = src
[0].u64
[3] + src
[1].u64
[3];
838 micro_u64mul(union tgsi_double_channel
*dst
,
839 const union tgsi_double_channel
*src
)
841 dst
->u64
[0] = src
[0].u64
[0] * src
[1].u64
[0];
842 dst
->u64
[1] = src
[0].u64
[1] * src
[1].u64
[1];
843 dst
->u64
[2] = src
[0].u64
[2] * src
[1].u64
[2];
844 dst
->u64
[3] = src
[0].u64
[3] * src
[1].u64
[3];
848 micro_u64div(union tgsi_double_channel
*dst
,
849 const union tgsi_double_channel
*src
)
851 dst
->u64
[0] = src
[0].u64
[0] / src
[1].u64
[0];
852 dst
->u64
[1] = src
[0].u64
[1] / src
[1].u64
[1];
853 dst
->u64
[2] = src
[0].u64
[2] / src
[1].u64
[2];
854 dst
->u64
[3] = src
[0].u64
[3] / src
[1].u64
[3];
858 micro_i64div(union tgsi_double_channel
*dst
,
859 const union tgsi_double_channel
*src
)
861 dst
->i64
[0] = src
[0].i64
[0] / src
[1].i64
[0];
862 dst
->i64
[1] = src
[0].i64
[1] / src
[1].i64
[1];
863 dst
->i64
[2] = src
[0].i64
[2] / src
[1].i64
[2];
864 dst
->i64
[3] = src
[0].i64
[3] / src
[1].i64
[3];
868 micro_u64mod(union tgsi_double_channel
*dst
,
869 const union tgsi_double_channel
*src
)
871 dst
->u64
[0] = src
[0].u64
[0] % src
[1].u64
[0];
872 dst
->u64
[1] = src
[0].u64
[1] % src
[1].u64
[1];
873 dst
->u64
[2] = src
[0].u64
[2] % src
[1].u64
[2];
874 dst
->u64
[3] = src
[0].u64
[3] % src
[1].u64
[3];
878 micro_i64mod(union tgsi_double_channel
*dst
,
879 const union tgsi_double_channel
*src
)
881 dst
->i64
[0] = src
[0].i64
[0] % src
[1].i64
[0];
882 dst
->i64
[1] = src
[0].i64
[1] % src
[1].i64
[1];
883 dst
->i64
[2] = src
[0].i64
[2] % src
[1].i64
[2];
884 dst
->i64
[3] = src
[0].i64
[3] % src
[1].i64
[3];
888 micro_u64shl(union tgsi_double_channel
*dst
,
889 const union tgsi_double_channel
*src0
,
890 union tgsi_exec_channel
*src1
)
892 unsigned masked_count
;
893 masked_count
= src1
->u
[0] & 0x3f;
894 dst
->u64
[0] = src0
->u64
[0] << masked_count
;
895 masked_count
= src1
->u
[1] & 0x3f;
896 dst
->u64
[1] = src0
->u64
[1] << masked_count
;
897 masked_count
= src1
->u
[2] & 0x3f;
898 dst
->u64
[2] = src0
->u64
[2] << masked_count
;
899 masked_count
= src1
->u
[3] & 0x3f;
900 dst
->u64
[3] = src0
->u64
[3] << masked_count
;
904 micro_i64shr(union tgsi_double_channel
*dst
,
905 const union tgsi_double_channel
*src0
,
906 union tgsi_exec_channel
*src1
)
908 unsigned masked_count
;
909 masked_count
= src1
->u
[0] & 0x3f;
910 dst
->i64
[0] = src0
->i64
[0] >> masked_count
;
911 masked_count
= src1
->u
[1] & 0x3f;
912 dst
->i64
[1] = src0
->i64
[1] >> masked_count
;
913 masked_count
= src1
->u
[2] & 0x3f;
914 dst
->i64
[2] = src0
->i64
[2] >> masked_count
;
915 masked_count
= src1
->u
[3] & 0x3f;
916 dst
->i64
[3] = src0
->i64
[3] >> masked_count
;
920 micro_u64shr(union tgsi_double_channel
*dst
,
921 const union tgsi_double_channel
*src0
,
922 union tgsi_exec_channel
*src1
)
924 unsigned masked_count
;
925 masked_count
= src1
->u
[0] & 0x3f;
926 dst
->u64
[0] = src0
->u64
[0] >> masked_count
;
927 masked_count
= src1
->u
[1] & 0x3f;
928 dst
->u64
[1] = src0
->u64
[1] >> masked_count
;
929 masked_count
= src1
->u
[2] & 0x3f;
930 dst
->u64
[2] = src0
->u64
[2] >> masked_count
;
931 masked_count
= src1
->u
[3] & 0x3f;
932 dst
->u64
[3] = src0
->u64
[3] >> masked_count
;
935 enum tgsi_exec_datatype
{
936 TGSI_EXEC_DATA_FLOAT
,
939 TGSI_EXEC_DATA_DOUBLE
,
940 TGSI_EXEC_DATA_INT64
,
941 TGSI_EXEC_DATA_UINT64
,
945 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
947 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
948 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
949 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
950 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
951 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
952 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
955 /** The execution mask depends on the conditional mask and the loop mask */
956 #define UPDATE_EXEC_MASK(MACH) \
957 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
960 static const union tgsi_exec_channel ZeroVec
=
961 { { 0.0, 0.0, 0.0, 0.0 } };
963 static const union tgsi_exec_channel OneVec
= {
964 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
967 static const union tgsi_exec_channel P128Vec
= {
968 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
971 static const union tgsi_exec_channel M128Vec
= {
972 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
977 * Assert that none of the float values in 'chan' are infinite or NaN.
978 * NaN and Inf may occur normally during program execution and should
979 * not lead to crashes, etc. But when debugging, it's helpful to catch
983 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
985 assert(!util_is_inf_or_nan((chan
)->f
[0]));
986 assert(!util_is_inf_or_nan((chan
)->f
[1]));
987 assert(!util_is_inf_or_nan((chan
)->f
[2]));
988 assert(!util_is_inf_or_nan((chan
)->f
[3]));
994 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
996 debug_printf("%s = {%f, %f, %f, %f}\n",
997 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
1004 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
1006 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
1008 debug_printf("Temp[%u] =\n", index
);
1009 for (i
= 0; i
< 4; i
++) {
1010 debug_printf(" %c: { %f, %f, %f, %f }\n",
1022 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
1025 const unsigned *buf_sizes
)
1029 for (i
= 0; i
< num_bufs
; i
++) {
1030 mach
->Consts
[i
] = bufs
[i
];
1031 mach
->ConstsSize
[i
] = buf_sizes
[i
];
1037 * Check if there's a potential src/dst register data dependency when
1038 * using SOA execution.
1041 * This would expand into:
1046 * The second instruction will have the wrong value for t0 if executed as-is.
1049 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
1053 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
1054 if (writemask
== TGSI_WRITEMASK_X
||
1055 writemask
== TGSI_WRITEMASK_Y
||
1056 writemask
== TGSI_WRITEMASK_Z
||
1057 writemask
== TGSI_WRITEMASK_W
||
1058 writemask
== TGSI_WRITEMASK_NONE
) {
1059 /* no chance of data dependency */
1063 /* loop over src regs */
1064 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1065 if ((inst
->Src
[i
].Register
.File
==
1066 inst
->Dst
[0].Register
.File
) &&
1067 ((inst
->Src
[i
].Register
.Index
==
1068 inst
->Dst
[0].Register
.Index
) ||
1069 inst
->Src
[i
].Register
.Indirect
||
1070 inst
->Dst
[0].Register
.Indirect
)) {
1071 /* loop over dest channels */
1072 uint channelsWritten
= 0x0;
1073 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1074 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1075 /* check if we're reading a channel that's been written */
1076 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
1077 if (channelsWritten
& (1 << swizzle
)) {
1081 channelsWritten
|= (1 << chan
);
1091 * Initialize machine state by expanding tokens to full instructions,
1092 * allocating temporary storage, setting up constants, etc.
1093 * After this, we can call tgsi_exec_machine_run() many times.
1096 tgsi_exec_machine_bind_shader(
1097 struct tgsi_exec_machine
*mach
,
1098 const struct tgsi_token
*tokens
,
1099 struct tgsi_sampler
*sampler
,
1100 struct tgsi_image
*image
,
1101 struct tgsi_buffer
*buffer
)
1104 struct tgsi_parse_context parse
;
1105 struct tgsi_full_instruction
*instructions
;
1106 struct tgsi_full_declaration
*declarations
;
1107 uint maxInstructions
= 10, numInstructions
= 0;
1108 uint maxDeclarations
= 10, numDeclarations
= 0;
1111 tgsi_dump(tokens
, 0);
1117 mach
->Tokens
= tokens
;
1118 mach
->Sampler
= sampler
;
1119 mach
->Image
= image
;
1120 mach
->Buffer
= buffer
;
1123 /* unbind and free all */
1124 FREE(mach
->Declarations
);
1125 mach
->Declarations
= NULL
;
1126 mach
->NumDeclarations
= 0;
1128 FREE(mach
->Instructions
);
1129 mach
->Instructions
= NULL
;
1130 mach
->NumInstructions
= 0;
1135 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
1136 if (k
!= TGSI_PARSE_OK
) {
1137 debug_printf( "Problem parsing!\n" );
1142 mach
->NumOutputs
= 0;
1144 for (k
= 0; k
< TGSI_SEMANTIC_COUNT
; k
++)
1145 mach
->SysSemanticToIndex
[k
] = -1;
1147 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
&&
1148 !mach
->UsedGeometryShader
) {
1149 struct tgsi_exec_vector
*inputs
;
1150 struct tgsi_exec_vector
*outputs
;
1152 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1153 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
1159 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1160 TGSI_MAX_TOTAL_VERTICES
, 16);
1167 align_free(mach
->Inputs
);
1168 align_free(mach
->Outputs
);
1170 mach
->Inputs
= inputs
;
1171 mach
->Outputs
= outputs
;
1172 mach
->UsedGeometryShader
= TRUE
;
1175 declarations
= (struct tgsi_full_declaration
*)
1176 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
1178 if (!declarations
) {
1182 instructions
= (struct tgsi_full_instruction
*)
1183 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
1185 if (!instructions
) {
1186 FREE( declarations
);
1190 while( !tgsi_parse_end_of_tokens( &parse
) ) {
1193 tgsi_parse_token( &parse
);
1194 switch( parse
.FullToken
.Token
.Type
) {
1195 case TGSI_TOKEN_TYPE_DECLARATION
:
1196 /* save expanded declaration */
1197 if (numDeclarations
== maxDeclarations
) {
1198 declarations
= REALLOC(declarations
,
1200 * sizeof(struct tgsi_full_declaration
),
1201 (maxDeclarations
+ 10)
1202 * sizeof(struct tgsi_full_declaration
));
1203 maxDeclarations
+= 10;
1205 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
1207 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
1208 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
1213 else if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1214 const struct tgsi_full_declaration
*decl
= &parse
.FullToken
.FullDeclaration
;
1215 mach
->SysSemanticToIndex
[decl
->Semantic
.Name
] = decl
->Range
.First
;
1218 memcpy(declarations
+ numDeclarations
,
1219 &parse
.FullToken
.FullDeclaration
,
1220 sizeof(declarations
[0]));
1224 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1226 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
1227 assert( size
<= 4 );
1228 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
1230 for( i
= 0; i
< size
; i
++ ) {
1231 mach
->Imms
[mach
->ImmLimit
][i
] =
1232 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
1234 mach
->ImmLimit
+= 1;
1238 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1240 /* save expanded instruction */
1241 if (numInstructions
== maxInstructions
) {
1242 instructions
= REALLOC(instructions
,
1244 * sizeof(struct tgsi_full_instruction
),
1245 (maxInstructions
+ 10)
1246 * sizeof(struct tgsi_full_instruction
));
1247 maxInstructions
+= 10;
1250 memcpy(instructions
+ numInstructions
,
1251 &parse
.FullToken
.FullInstruction
,
1252 sizeof(instructions
[0]));
1257 case TGSI_TOKEN_TYPE_PROPERTY
:
1258 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
1259 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1260 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1269 tgsi_parse_free (&parse
);
1271 FREE(mach
->Declarations
);
1272 mach
->Declarations
= declarations
;
1273 mach
->NumDeclarations
= numDeclarations
;
1275 FREE(mach
->Instructions
);
1276 mach
->Instructions
= instructions
;
1277 mach
->NumInstructions
= numInstructions
;
1281 struct tgsi_exec_machine
*
1282 tgsi_exec_machine_create(enum pipe_shader_type shader_type
)
1284 struct tgsi_exec_machine
*mach
;
1287 mach
= align_malloc( sizeof *mach
, 16 );
1291 memset(mach
, 0, sizeof(*mach
));
1293 mach
->ShaderType
= shader_type
;
1294 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1295 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1296 mach
->Predicates
= &mach
->Temps
[TGSI_EXEC_TEMP_P0
];
1298 if (shader_type
!= PIPE_SHADER_COMPUTE
) {
1299 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1300 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1301 if (!mach
->Inputs
|| !mach
->Outputs
)
1305 /* Setup constants needed by the SSE2 executor. */
1306 for( i
= 0; i
< 4; i
++ ) {
1307 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
1308 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
1309 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
1310 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
1311 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
1312 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
1313 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
1314 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
1315 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
1316 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
1320 /* silence warnings */
1329 align_free(mach
->Inputs
);
1330 align_free(mach
->Outputs
);
1338 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1341 FREE(mach
->Instructions
);
1342 FREE(mach
->Declarations
);
1344 align_free(mach
->Inputs
);
1345 align_free(mach
->Outputs
);
1352 micro_add(union tgsi_exec_channel
*dst
,
1353 const union tgsi_exec_channel
*src0
,
1354 const union tgsi_exec_channel
*src1
)
1356 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1357 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1358 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1359 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1364 union tgsi_exec_channel
*dst
,
1365 const union tgsi_exec_channel
*src0
,
1366 const union tgsi_exec_channel
*src1
)
1368 if (src1
->f
[0] != 0) {
1369 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1371 if (src1
->f
[1] != 0) {
1372 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1374 if (src1
->f
[2] != 0) {
1375 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1377 if (src1
->f
[3] != 0) {
1378 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1384 union tgsi_exec_channel
*dst
,
1385 const union tgsi_exec_channel
*src0
,
1386 const union tgsi_exec_channel
*src1
,
1387 const union tgsi_exec_channel
*src2
,
1388 const union tgsi_exec_channel
*src3
)
1390 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1391 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1392 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1393 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1397 micro_max(union tgsi_exec_channel
*dst
,
1398 const union tgsi_exec_channel
*src0
,
1399 const union tgsi_exec_channel
*src1
)
1401 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1402 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1403 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1404 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1408 micro_min(union tgsi_exec_channel
*dst
,
1409 const union tgsi_exec_channel
*src0
,
1410 const union tgsi_exec_channel
*src1
)
1412 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1413 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1414 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1415 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1419 micro_mul(union tgsi_exec_channel
*dst
,
1420 const union tgsi_exec_channel
*src0
,
1421 const union tgsi_exec_channel
*src1
)
1423 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1424 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1425 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1426 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1431 union tgsi_exec_channel
*dst
,
1432 const union tgsi_exec_channel
*src
)
1434 dst
->f
[0] = -src
->f
[0];
1435 dst
->f
[1] = -src
->f
[1];
1436 dst
->f
[2] = -src
->f
[2];
1437 dst
->f
[3] = -src
->f
[3];
1442 union tgsi_exec_channel
*dst
,
1443 const union tgsi_exec_channel
*src0
,
1444 const union tgsi_exec_channel
*src1
)
1447 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1448 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1449 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1450 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1452 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1453 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1454 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1455 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1460 micro_sub(union tgsi_exec_channel
*dst
,
1461 const union tgsi_exec_channel
*src0
,
1462 const union tgsi_exec_channel
*src1
)
1464 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1465 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1466 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1467 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1471 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1472 const uint chan_index
,
1475 const union tgsi_exec_channel
*index
,
1476 const union tgsi_exec_channel
*index2D
,
1477 union tgsi_exec_channel
*chan
)
1481 assert(swizzle
< 4);
1484 case TGSI_FILE_CONSTANT
:
1485 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1486 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1487 assert(mach
->Consts
[index2D
->i
[i
]]);
1489 if (index
->i
[i
] < 0) {
1492 /* NOTE: copying the const value as a uint instead of float */
1493 const uint constbuf
= index2D
->i
[i
];
1494 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1495 const int pos
= index
->i
[i
] * 4 + swizzle
;
1496 /* const buffer bounds check */
1497 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1499 /* Debug: print warning */
1500 static int count
= 0;
1502 debug_printf("TGSI Exec: const buffer index %d"
1503 " out of bounds\n", pos
);
1508 chan
->u
[i
] = buf
[pos
];
1513 case TGSI_FILE_INPUT
:
1514 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1516 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1517 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1518 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1519 index2D->i[i], index->i[i]);
1521 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1523 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1524 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1528 case TGSI_FILE_SYSTEM_VALUE
:
1529 /* XXX no swizzling at this point. Will be needed if we put
1530 * gl_FragCoord, for example, in a sys value register.
1532 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1533 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1537 case TGSI_FILE_TEMPORARY
:
1538 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1539 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1540 assert(index2D
->i
[i
] == 0);
1542 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1546 case TGSI_FILE_IMMEDIATE
:
1547 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1548 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1549 assert(index2D
->i
[i
] == 0);
1551 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1555 case TGSI_FILE_ADDRESS
:
1556 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1557 assert(index
->i
[i
] >= 0);
1558 assert(index2D
->i
[i
] == 0);
1560 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1564 case TGSI_FILE_PREDICATE
:
1565 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1566 assert(index
->i
[i
] >= 0 && index
->i
[i
] < TGSI_EXEC_NUM_PREDS
);
1567 assert(index2D
->i
[i
] == 0);
1569 chan
->u
[i
] = mach
->Predicates
[0].xyzw
[swizzle
].u
[i
];
1573 case TGSI_FILE_OUTPUT
:
1574 /* vertex/fragment output vars can be read too */
1575 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1576 assert(index
->i
[i
] >= 0);
1577 assert(index2D
->i
[i
] == 0);
1579 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1585 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1592 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1593 union tgsi_exec_channel
*chan
,
1594 const struct tgsi_full_src_register
*reg
,
1595 const uint chan_index
,
1596 enum tgsi_exec_datatype src_datatype
)
1598 union tgsi_exec_channel index
;
1599 union tgsi_exec_channel index2D
;
1602 /* We start with a direct index into a register file.
1606 * file = Register.File
1607 * [1] = Register.Index
1612 index
.i
[3] = reg
->Register
.Index
;
1614 /* There is an extra source register that indirectly subscripts
1615 * a register file. The direct index now becomes an offset
1616 * that is being added to the indirect register.
1620 * ind = Indirect.File
1621 * [2] = Indirect.Index
1622 * .x = Indirect.SwizzleX
1624 if (reg
->Register
.Indirect
) {
1625 union tgsi_exec_channel index2
;
1626 union tgsi_exec_channel indir_index
;
1627 const uint execmask
= mach
->ExecMask
;
1630 /* which address register (always zero now) */
1634 index2
.i
[3] = reg
->Indirect
.Index
;
1635 /* get current value of address register[swizzle] */
1636 swizzle
= reg
->Indirect
.Swizzle
;
1637 fetch_src_file_channel(mach
,
1645 /* add value of address register to the offset */
1646 index
.i
[0] += indir_index
.i
[0];
1647 index
.i
[1] += indir_index
.i
[1];
1648 index
.i
[2] += indir_index
.i
[2];
1649 index
.i
[3] += indir_index
.i
[3];
1651 /* for disabled execution channels, zero-out the index to
1652 * avoid using a potential garbage value.
1654 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1655 if ((execmask
& (1 << i
)) == 0)
1660 /* There is an extra source register that is a second
1661 * subscript to a register file. Effectively it means that
1662 * the register file is actually a 2D array of registers.
1666 * [3] = Dimension.Index
1668 if (reg
->Register
.Dimension
) {
1672 index2D
.i
[3] = reg
->Dimension
.Index
;
1674 /* Again, the second subscript index can be addressed indirectly
1675 * identically to the first one.
1676 * Nothing stops us from indirectly addressing the indirect register,
1677 * but there is no need for that, so we won't exercise it.
1679 * file[ind[4].y+3][1],
1681 * ind = DimIndirect.File
1682 * [4] = DimIndirect.Index
1683 * .y = DimIndirect.SwizzleX
1685 if (reg
->Dimension
.Indirect
) {
1686 union tgsi_exec_channel index2
;
1687 union tgsi_exec_channel indir_index
;
1688 const uint execmask
= mach
->ExecMask
;
1694 index2
.i
[3] = reg
->DimIndirect
.Index
;
1696 swizzle
= reg
->DimIndirect
.Swizzle
;
1697 fetch_src_file_channel(mach
,
1699 reg
->DimIndirect
.File
,
1705 index2D
.i
[0] += indir_index
.i
[0];
1706 index2D
.i
[1] += indir_index
.i
[1];
1707 index2D
.i
[2] += indir_index
.i
[2];
1708 index2D
.i
[3] += indir_index
.i
[3];
1710 /* for disabled execution channels, zero-out the index to
1711 * avoid using a potential garbage value.
1713 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1714 if ((execmask
& (1 << i
)) == 0) {
1720 /* If by any chance there was a need for a 3D array of register
1721 * files, we would have to check whether Dimension is followed
1722 * by a dimension register and continue the saga.
1731 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1732 fetch_src_file_channel(mach
,
1742 fetch_source(const struct tgsi_exec_machine
*mach
,
1743 union tgsi_exec_channel
*chan
,
1744 const struct tgsi_full_src_register
*reg
,
1745 const uint chan_index
,
1746 enum tgsi_exec_datatype src_datatype
)
1748 fetch_source_d(mach
, chan
, reg
, chan_index
, src_datatype
);
1750 if (reg
->Register
.Absolute
) {
1751 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1752 micro_abs(chan
, chan
);
1754 micro_iabs(chan
, chan
);
1758 if (reg
->Register
.Negate
) {
1759 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1760 micro_neg(chan
, chan
);
1762 micro_ineg(chan
, chan
);
1767 static union tgsi_exec_channel
*
1768 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1769 const union tgsi_exec_channel
*chan
,
1770 const struct tgsi_full_dst_register
*reg
,
1771 const struct tgsi_full_instruction
*inst
,
1773 enum tgsi_exec_datatype dst_datatype
)
1776 static union tgsi_exec_channel null
;
1777 union tgsi_exec_channel
*dst
;
1778 union tgsi_exec_channel index2D
;
1779 uint execmask
= mach
->ExecMask
;
1780 int offset
= 0; /* indirection offset */
1784 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1785 check_inf_or_nan(chan
);
1788 /* There is an extra source register that indirectly subscripts
1789 * a register file. The direct index now becomes an offset
1790 * that is being added to the indirect register.
1794 * ind = Indirect.File
1795 * [2] = Indirect.Index
1796 * .x = Indirect.SwizzleX
1798 if (reg
->Register
.Indirect
) {
1799 union tgsi_exec_channel index
;
1800 union tgsi_exec_channel indir_index
;
1803 /* which address register (always zero for now) */
1807 index
.i
[3] = reg
->Indirect
.Index
;
1809 /* get current value of address register[swizzle] */
1810 swizzle
= reg
->Indirect
.Swizzle
;
1812 /* fetch values from the address/indirection register */
1813 fetch_src_file_channel(mach
,
1821 /* save indirection offset */
1822 offset
= indir_index
.i
[0];
1825 /* There is an extra source register that is a second
1826 * subscript to a register file. Effectively it means that
1827 * the register file is actually a 2D array of registers.
1831 * [3] = Dimension.Index
1833 if (reg
->Register
.Dimension
) {
1837 index2D
.i
[3] = reg
->Dimension
.Index
;
1839 /* Again, the second subscript index can be addressed indirectly
1840 * identically to the first one.
1841 * Nothing stops us from indirectly addressing the indirect register,
1842 * but there is no need for that, so we won't exercise it.
1844 * file[ind[4].y+3][1],
1846 * ind = DimIndirect.File
1847 * [4] = DimIndirect.Index
1848 * .y = DimIndirect.SwizzleX
1850 if (reg
->Dimension
.Indirect
) {
1851 union tgsi_exec_channel index2
;
1852 union tgsi_exec_channel indir_index
;
1853 const uint execmask
= mach
->ExecMask
;
1860 index2
.i
[3] = reg
->DimIndirect
.Index
;
1862 swizzle
= reg
->DimIndirect
.Swizzle
;
1863 fetch_src_file_channel(mach
,
1865 reg
->DimIndirect
.File
,
1871 index2D
.i
[0] += indir_index
.i
[0];
1872 index2D
.i
[1] += indir_index
.i
[1];
1873 index2D
.i
[2] += indir_index
.i
[2];
1874 index2D
.i
[3] += indir_index
.i
[3];
1876 /* for disabled execution channels, zero-out the index to
1877 * avoid using a potential garbage value.
1879 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1880 if ((execmask
& (1 << i
)) == 0) {
1886 /* If by any chance there was a need for a 3D array of register
1887 * files, we would have to check whether Dimension is followed
1888 * by a dimension register and continue the saga.
1897 switch (reg
->Register
.File
) {
1898 case TGSI_FILE_NULL
:
1902 case TGSI_FILE_OUTPUT
:
1903 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1904 + reg
->Register
.Index
;
1905 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1907 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1908 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1909 reg
->Register
.Index
);
1910 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
1911 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1912 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1913 if (execmask
& (1 << i
))
1914 debug_printf("%f, ", chan
->f
[i
]);
1915 debug_printf(")\n");
1920 case TGSI_FILE_TEMPORARY
:
1921 index
= reg
->Register
.Index
;
1922 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1923 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1926 case TGSI_FILE_ADDRESS
:
1927 index
= reg
->Register
.Index
;
1928 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1931 case TGSI_FILE_PREDICATE
:
1932 index
= reg
->Register
.Index
;
1933 assert(index
< TGSI_EXEC_NUM_PREDS
);
1934 dst
= &mach
->Predicates
[index
].xyzw
[chan_index
];
1942 if (inst
->Instruction
.Predicate
) {
1944 union tgsi_exec_channel
*pred
;
1946 switch (chan_index
) {
1948 swizzle
= inst
->Predicate
.SwizzleX
;
1951 swizzle
= inst
->Predicate
.SwizzleY
;
1954 swizzle
= inst
->Predicate
.SwizzleZ
;
1957 swizzle
= inst
->Predicate
.SwizzleW
;
1964 assert(inst
->Predicate
.Index
== 0);
1966 pred
= &mach
->Predicates
[inst
->Predicate
.Index
].xyzw
[swizzle
];
1968 if (inst
->Predicate
.Negate
) {
1969 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1971 execmask
&= ~(1 << i
);
1975 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1977 execmask
&= ~(1 << i
);
1987 store_dest_double(struct tgsi_exec_machine
*mach
,
1988 const union tgsi_exec_channel
*chan
,
1989 const struct tgsi_full_dst_register
*reg
,
1990 const struct tgsi_full_instruction
*inst
,
1992 enum tgsi_exec_datatype dst_datatype
)
1994 union tgsi_exec_channel
*dst
;
1995 const uint execmask
= mach
->ExecMask
;
1998 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
2004 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
2005 if (execmask
& (1 << i
))
2006 dst
->i
[i
] = chan
->i
[i
];
2010 store_dest(struct tgsi_exec_machine
*mach
,
2011 const union tgsi_exec_channel
*chan
,
2012 const struct tgsi_full_dst_register
*reg
,
2013 const struct tgsi_full_instruction
*inst
,
2015 enum tgsi_exec_datatype dst_datatype
)
2017 union tgsi_exec_channel
*dst
;
2018 const uint execmask
= mach
->ExecMask
;
2021 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
2026 if (!inst
->Instruction
.Saturate
) {
2027 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
2028 if (execmask
& (1 << i
))
2029 dst
->i
[i
] = chan
->i
[i
];
2032 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
2033 if (execmask
& (1 << i
)) {
2034 if (chan
->f
[i
] < 0.0f
)
2036 else if (chan
->f
[i
] > 1.0f
)
2039 dst
->i
[i
] = chan
->i
[i
];
2044 #define FETCH(VAL,INDEX,CHAN)\
2045 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
2047 #define IFETCH(VAL,INDEX,CHAN)\
2048 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
2052 * Execute ARB-style KIL which is predicated by a src register.
2053 * Kill fragment if any of the four values is less than zero.
2056 exec_kill_if(struct tgsi_exec_machine
*mach
,
2057 const struct tgsi_full_instruction
*inst
)
2061 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2062 union tgsi_exec_channel r
[1];
2064 /* This mask stores component bits that were already tested. */
2067 for (chan_index
= 0; chan_index
< 4; chan_index
++)
2072 /* unswizzle channel */
2073 swizzle
= tgsi_util_get_full_src_register_swizzle (
2077 /* check if the component has not been already tested */
2078 if (uniquemask
& (1 << swizzle
))
2080 uniquemask
|= 1 << swizzle
;
2082 FETCH(&r
[0], 0, chan_index
);
2083 for (i
= 0; i
< 4; i
++)
2084 if (r
[0].f
[i
] < 0.0f
)
2088 /* restrict to fragments currently executing */
2089 kilmask
&= mach
->ExecMask
;
2091 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2095 * Unconditional fragment kill/discard.
2098 exec_kill(struct tgsi_exec_machine
*mach
,
2099 const struct tgsi_full_instruction
*inst
)
2101 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2103 /* kill fragment for all fragments currently executing */
2104 kilmask
= mach
->ExecMask
;
2105 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2109 emit_vertex(struct tgsi_exec_machine
*mach
)
2111 /* FIXME: check for exec mask correctly
2113 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2114 if ((mach->ExecMask & (1 << i)))
2116 if (mach
->ExecMask
) {
2117 if (mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]] >= mach
->MaxOutputVertices
)
2120 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
2121 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
2126 emit_primitive(struct tgsi_exec_machine
*mach
)
2128 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
2129 /* FIXME: check for exec mask correctly
2131 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2132 if ((mach->ExecMask & (1 << i)))
2134 if (mach
->ExecMask
) {
2136 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
2137 mach
->Primitives
[*prim_count
] = 0;
2142 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
2144 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
2146 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
2147 if (emitted_verts
) {
2148 emit_primitive(mach
);
2155 * Fetch four texture samples using STR texture coordinates.
2158 fetch_texel( struct tgsi_sampler
*sampler
,
2159 const unsigned sview_idx
,
2160 const unsigned sampler_idx
,
2161 const union tgsi_exec_channel
*s
,
2162 const union tgsi_exec_channel
*t
,
2163 const union tgsi_exec_channel
*p
,
2164 const union tgsi_exec_channel
*c0
,
2165 const union tgsi_exec_channel
*c1
,
2166 float derivs
[3][2][TGSI_QUAD_SIZE
],
2167 const int8_t offset
[3],
2168 enum tgsi_sampler_control control
,
2169 union tgsi_exec_channel
*r
,
2170 union tgsi_exec_channel
*g
,
2171 union tgsi_exec_channel
*b
,
2172 union tgsi_exec_channel
*a
)
2175 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2177 /* FIXME: handle explicit derivs, offsets */
2178 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
2179 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
2181 for (j
= 0; j
< 4; j
++) {
2182 r
->f
[j
] = rgba
[0][j
];
2183 g
->f
[j
] = rgba
[1][j
];
2184 b
->f
[j
] = rgba
[2][j
];
2185 a
->f
[j
] = rgba
[3][j
];
2190 #define TEX_MODIFIER_NONE 0
2191 #define TEX_MODIFIER_PROJECTED 1
2192 #define TEX_MODIFIER_LOD_BIAS 2
2193 #define TEX_MODIFIER_EXPLICIT_LOD 3
2194 #define TEX_MODIFIER_LEVEL_ZERO 4
2195 #define TEX_MODIFIER_GATHER 5
2198 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
2201 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
2202 const struct tgsi_full_instruction
*inst
,
2205 if (inst
->Texture
.NumOffsets
== 1) {
2206 union tgsi_exec_channel index
;
2207 union tgsi_exec_channel offset
[3];
2208 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
2209 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
2210 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
2211 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
2212 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
2213 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
2214 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
2215 offsets
[0] = offset
[0].i
[0];
2216 offsets
[1] = offset
[1].i
[0];
2217 offsets
[2] = offset
[2].i
[0];
2219 assert(inst
->Texture
.NumOffsets
== 0);
2220 offsets
[0] = offsets
[1] = offsets
[2] = 0;
2226 * Fetch dx and dy values for one channel (s, t or r).
2227 * Put dx values into one float array, dy values into another.
2230 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
2231 const struct tgsi_full_instruction
*inst
,
2234 float derivs
[2][TGSI_QUAD_SIZE
])
2236 union tgsi_exec_channel d
;
2237 FETCH(&d
, regdsrcx
, chan
);
2238 derivs
[0][0] = d
.f
[0];
2239 derivs
[0][1] = d
.f
[1];
2240 derivs
[0][2] = d
.f
[2];
2241 derivs
[0][3] = d
.f
[3];
2242 FETCH(&d
, regdsrcx
+ 1, chan
);
2243 derivs
[1][0] = d
.f
[0];
2244 derivs
[1][1] = d
.f
[1];
2245 derivs
[1][2] = d
.f
[2];
2246 derivs
[1][3] = d
.f
[3];
2250 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
2251 const struct tgsi_full_instruction
*inst
,
2256 if (inst
->Src
[sampler
].Register
.Indirect
) {
2257 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2258 union tgsi_exec_channel indir_index
, index2
;
2259 const uint execmask
= mach
->ExecMask
;
2263 index2
.i
[3] = reg
->Indirect
.Index
;
2265 fetch_src_file_channel(mach
,
2268 reg
->Indirect
.Swizzle
,
2272 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2273 if (execmask
& (1 << i
)) {
2274 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[i
];
2280 unit
= inst
->Src
[sampler
].Register
.Index
;
2286 * execute a texture instruction.
2288 * modifier is used to control the channel routing for the
2289 * instruction variants like proj, lod, and texture with lod bias.
2290 * sampler indicates which src register the sampler is contained in.
2293 exec_tex(struct tgsi_exec_machine
*mach
,
2294 const struct tgsi_full_instruction
*inst
,
2295 uint modifier
, uint sampler
)
2297 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2298 union tgsi_exec_channel r
[5];
2299 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2303 int dim
, shadow_ref
, i
;
2305 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2306 /* always fetch all 3 offsets, overkill but keeps code simple */
2307 fetch_texel_offsets(mach
, inst
, offsets
);
2309 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2310 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2312 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2313 shadow_ref
= tgsi_util_get_shadow_ref_src_index(inst
->Texture
.Texture
);
2316 if (shadow_ref
>= 0)
2317 assert(shadow_ref
>= dim
&& shadow_ref
< ARRAY_SIZE(args
));
2319 /* fetch modifier to the last argument */
2320 if (modifier
!= TEX_MODIFIER_NONE
) {
2321 const int last
= ARRAY_SIZE(args
) - 1;
2323 /* fetch modifier from src0.w or src1.x */
2325 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2326 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2329 assert(shadow_ref
!= 4);
2330 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2333 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2334 args
[last
] = &r
[last
];
2338 args
[last
] = &ZeroVec
;
2341 /* point unused arguments to zero vector */
2342 for (i
= dim
; i
< last
; i
++)
2345 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2346 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2347 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2348 control
= TGSI_SAMPLER_LOD_BIAS
;
2349 else if (modifier
== TEX_MODIFIER_GATHER
)
2350 control
= TGSI_SAMPLER_GATHER
;
2353 for (i
= dim
; i
< ARRAY_SIZE(args
); i
++)
2357 /* fetch coordinates */
2358 for (i
= 0; i
< dim
; i
++) {
2359 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2362 micro_div(&r
[i
], &r
[i
], proj
);
2367 /* fetch reference value */
2368 if (shadow_ref
>= 0) {
2369 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2372 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2374 args
[shadow_ref
] = &r
[shadow_ref
];
2377 fetch_texel(mach
->Sampler
, unit
, unit
,
2378 args
[0], args
[1], args
[2], args
[3], args
[4],
2379 NULL
, offsets
, control
,
2380 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2383 debug_printf("fetch r: %g %g %g %g\n",
2384 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2385 debug_printf("fetch g: %g %g %g %g\n",
2386 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2387 debug_printf("fetch b: %g %g %g %g\n",
2388 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2389 debug_printf("fetch a: %g %g %g %g\n",
2390 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2393 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2394 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2395 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2401 exec_lodq(struct tgsi_exec_machine
*mach
,
2402 const struct tgsi_full_instruction
*inst
)
2407 union tgsi_exec_channel coords
[4];
2408 const union tgsi_exec_channel
*args
[ARRAY_SIZE(coords
)];
2409 union tgsi_exec_channel r
[2];
2411 unit
= fetch_sampler_unit(mach
, inst
, 1);
2412 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2413 assert(dim
<= ARRAY_SIZE(coords
));
2414 /* fetch coordinates */
2415 for (i
= 0; i
< dim
; i
++) {
2416 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2417 args
[i
] = &coords
[i
];
2419 for (i
= dim
; i
< ARRAY_SIZE(coords
); i
++) {
2422 mach
->Sampler
->query_lod(mach
->Sampler
, unit
, unit
,
2427 TGSI_SAMPLER_LOD_NONE
,
2431 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2432 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2433 TGSI_EXEC_DATA_FLOAT
);
2435 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2436 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2437 TGSI_EXEC_DATA_FLOAT
);
2442 exec_txd(struct tgsi_exec_machine
*mach
,
2443 const struct tgsi_full_instruction
*inst
)
2445 union tgsi_exec_channel r
[4];
2446 float derivs
[3][2][TGSI_QUAD_SIZE
];
2451 unit
= fetch_sampler_unit(mach
, inst
, 3);
2452 /* always fetch all 3 offsets, overkill but keeps code simple */
2453 fetch_texel_offsets(mach
, inst
, offsets
);
2455 switch (inst
->Texture
.Texture
) {
2456 case TGSI_TEXTURE_1D
:
2457 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2459 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2461 fetch_texel(mach
->Sampler
, unit
, unit
,
2462 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2463 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2464 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2467 case TGSI_TEXTURE_SHADOW1D
:
2468 case TGSI_TEXTURE_1D_ARRAY
:
2469 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2470 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2471 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2472 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2473 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2475 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2477 fetch_texel(mach
->Sampler
, unit
, unit
,
2478 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2479 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2480 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2483 case TGSI_TEXTURE_2D
:
2484 case TGSI_TEXTURE_RECT
:
2485 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2486 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2488 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2489 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2491 fetch_texel(mach
->Sampler
, unit
, unit
,
2492 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2493 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2494 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2498 case TGSI_TEXTURE_SHADOW2D
:
2499 case TGSI_TEXTURE_SHADOWRECT
:
2500 case TGSI_TEXTURE_2D_ARRAY
:
2501 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2502 /* only SHADOW2D_ARRAY actually needs W */
2503 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2504 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2505 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2506 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2508 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2509 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2511 fetch_texel(mach
->Sampler
, unit
, unit
,
2512 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2513 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2514 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2517 case TGSI_TEXTURE_3D
:
2518 case TGSI_TEXTURE_CUBE
:
2519 case TGSI_TEXTURE_CUBE_ARRAY
:
2520 case TGSI_TEXTURE_SHADOWCUBE
:
2521 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2522 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2523 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2524 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2525 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2527 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2528 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2529 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2531 fetch_texel(mach
->Sampler
, unit
, unit
,
2532 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2533 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2534 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2541 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2542 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2543 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2550 exec_txf(struct tgsi_exec_machine
*mach
,
2551 const struct tgsi_full_instruction
*inst
)
2553 union tgsi_exec_channel r
[4];
2556 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2561 unit
= fetch_sampler_unit(mach
, inst
, 1);
2562 /* always fetch all 3 offsets, overkill but keeps code simple */
2563 fetch_texel_offsets(mach
, inst
, offsets
);
2565 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2567 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2568 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2569 target
= mach
->SamplerViews
[unit
].Resource
;
2572 target
= inst
->Texture
.Texture
;
2575 case TGSI_TEXTURE_3D
:
2576 case TGSI_TEXTURE_2D_ARRAY
:
2577 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2578 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2579 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2581 case TGSI_TEXTURE_2D
:
2582 case TGSI_TEXTURE_RECT
:
2583 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2584 case TGSI_TEXTURE_SHADOW2D
:
2585 case TGSI_TEXTURE_SHADOWRECT
:
2586 case TGSI_TEXTURE_1D_ARRAY
:
2587 case TGSI_TEXTURE_2D_MSAA
:
2588 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2590 case TGSI_TEXTURE_BUFFER
:
2591 case TGSI_TEXTURE_1D
:
2592 case TGSI_TEXTURE_SHADOW1D
:
2593 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2600 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2603 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2604 r
[0].f
[j
] = rgba
[0][j
];
2605 r
[1].f
[j
] = rgba
[1][j
];
2606 r
[2].f
[j
] = rgba
[2][j
];
2607 r
[3].f
[j
] = rgba
[3][j
];
2610 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2611 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2612 unsigned char swizzles
[4];
2613 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2614 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2615 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2616 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2618 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2619 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2620 store_dest(mach
, &r
[swizzles
[chan
]],
2621 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2626 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2627 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2628 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2635 exec_txq(struct tgsi_exec_machine
*mach
,
2636 const struct tgsi_full_instruction
*inst
)
2639 union tgsi_exec_channel r
[4], src
;
2644 unit
= fetch_sampler_unit(mach
, inst
, 1);
2646 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2648 /* XXX: This interface can't return per-pixel values */
2649 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2651 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2652 for (j
= 0; j
< 4; j
++) {
2653 r
[j
].i
[i
] = result
[j
];
2657 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2658 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2659 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2660 TGSI_EXEC_DATA_INT
);
2666 exec_sample(struct tgsi_exec_machine
*mach
,
2667 const struct tgsi_full_instruction
*inst
,
2668 uint modifier
, boolean compare
)
2670 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2671 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2672 union tgsi_exec_channel r
[5], c1
;
2673 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2674 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2676 unsigned char swizzles
[4];
2679 /* always fetch all 3 offsets, overkill but keeps code simple */
2680 fetch_texel_offsets(mach
, inst
, offsets
);
2682 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2684 if (modifier
!= TEX_MODIFIER_NONE
) {
2685 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2686 FETCH(&c1
, 3, TGSI_CHAN_X
);
2688 control
= TGSI_SAMPLER_LOD_BIAS
;
2690 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2691 FETCH(&c1
, 3, TGSI_CHAN_X
);
2693 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2696 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2697 control
= TGSI_SAMPLER_LOD_ZERO
;
2701 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2703 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2704 case TGSI_TEXTURE_1D
:
2706 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2707 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2708 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2709 NULL
, offsets
, control
,
2710 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2713 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2714 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2715 NULL
, offsets
, control
,
2716 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2720 case TGSI_TEXTURE_1D_ARRAY
:
2721 case TGSI_TEXTURE_2D
:
2722 case TGSI_TEXTURE_RECT
:
2723 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2725 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2726 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2727 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2728 NULL
, offsets
, control
,
2729 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2732 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2733 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2734 NULL
, offsets
, control
,
2735 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2739 case TGSI_TEXTURE_2D_ARRAY
:
2740 case TGSI_TEXTURE_3D
:
2741 case TGSI_TEXTURE_CUBE
:
2742 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2743 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2745 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2746 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2747 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2748 NULL
, offsets
, control
,
2749 &r
[0], &r
[1], &r
[2], &r
[3]);
2752 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2753 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2754 NULL
, offsets
, control
,
2755 &r
[0], &r
[1], &r
[2], &r
[3]);
2759 case TGSI_TEXTURE_CUBE_ARRAY
:
2760 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2761 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2762 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2764 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2765 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2766 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2767 NULL
, offsets
, control
,
2768 &r
[0], &r
[1], &r
[2], &r
[3]);
2771 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2772 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2773 NULL
, offsets
, control
,
2774 &r
[0], &r
[1], &r
[2], &r
[3]);
2783 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2784 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2785 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2786 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2788 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2789 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2790 store_dest(mach
, &r
[swizzles
[chan
]],
2791 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2797 exec_sample_d(struct tgsi_exec_machine
*mach
,
2798 const struct tgsi_full_instruction
*inst
)
2800 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2801 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2802 union tgsi_exec_channel r
[4];
2803 float derivs
[3][2][TGSI_QUAD_SIZE
];
2805 unsigned char swizzles
[4];
2808 /* always fetch all 3 offsets, overkill but keeps code simple */
2809 fetch_texel_offsets(mach
, inst
, offsets
);
2811 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2813 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2814 case TGSI_TEXTURE_1D
:
2815 case TGSI_TEXTURE_1D_ARRAY
:
2816 /* only 1D array actually needs Y */
2817 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2819 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2821 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2822 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2823 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2824 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2827 case TGSI_TEXTURE_2D
:
2828 case TGSI_TEXTURE_RECT
:
2829 case TGSI_TEXTURE_2D_ARRAY
:
2830 /* only 2D array actually needs Z */
2831 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2832 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2834 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2835 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2837 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2838 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2839 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2840 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2843 case TGSI_TEXTURE_3D
:
2844 case TGSI_TEXTURE_CUBE
:
2845 case TGSI_TEXTURE_CUBE_ARRAY
:
2846 /* only cube array actually needs W */
2847 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2848 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2849 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2851 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2852 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2853 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2855 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2856 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2857 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2858 &r
[0], &r
[1], &r
[2], &r
[3]);
2865 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2866 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2867 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2868 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2870 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2871 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2872 store_dest(mach
, &r
[swizzles
[chan
]],
2873 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2880 * Evaluate a constant-valued coefficient at the position of the
2885 struct tgsi_exec_machine
*mach
,
2891 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2892 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2897 * Evaluate a linear-valued coefficient at the position of the
2902 struct tgsi_exec_machine
*mach
,
2906 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2907 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2908 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2909 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2910 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2911 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2912 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2913 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2914 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2918 * Evaluate a perspective-valued coefficient at the position of the
2922 eval_perspective_coef(
2923 struct tgsi_exec_machine
*mach
,
2927 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2928 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2929 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2930 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2931 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2932 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2933 /* divide by W here */
2934 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2935 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2936 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2937 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2941 typedef void (* eval_coef_func
)(
2942 struct tgsi_exec_machine
*mach
,
2947 exec_declaration(struct tgsi_exec_machine
*mach
,
2948 const struct tgsi_full_declaration
*decl
)
2950 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2951 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2955 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
2956 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2957 uint first
, last
, mask
;
2959 first
= decl
->Range
.First
;
2960 last
= decl
->Range
.Last
;
2961 mask
= decl
->Declaration
.UsageMask
;
2963 /* XXX we could remove this special-case code since
2964 * mach->InterpCoefs[first].a0 should already have the
2965 * front/back-face value. But we should first update the
2966 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2967 * Then, we could remove the tgsi_exec_machine::Face field.
2969 /* XXX make FACE a system value */
2970 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2973 assert(decl
->Semantic
.Index
== 0);
2974 assert(first
== last
);
2976 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2977 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2980 eval_coef_func eval
;
2983 switch (decl
->Interp
.Interpolate
) {
2984 case TGSI_INTERPOLATE_CONSTANT
:
2985 eval
= eval_constant_coef
;
2988 case TGSI_INTERPOLATE_LINEAR
:
2989 eval
= eval_linear_coef
;
2992 case TGSI_INTERPOLATE_PERSPECTIVE
:
2993 eval
= eval_perspective_coef
;
2996 case TGSI_INTERPOLATE_COLOR
:
2997 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
3005 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
3006 if (mask
& (1 << j
)) {
3007 for (i
= first
; i
<= last
; i
++) {
3014 if (DEBUG_EXECUTION
) {
3016 for (i
= first
; i
<= last
; ++i
) {
3017 debug_printf("IN[%2u] = ", i
);
3018 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
3022 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3023 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
3024 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
3025 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
3026 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
3035 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
3036 const union tgsi_exec_channel
*src
);
3039 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
3040 const struct tgsi_full_instruction
*inst
,
3042 enum tgsi_exec_datatype dst_datatype
,
3043 enum tgsi_exec_datatype src_datatype
)
3046 union tgsi_exec_channel src
;
3047 union tgsi_exec_channel dst
;
3049 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3051 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3052 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3053 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3059 exec_vector_unary(struct tgsi_exec_machine
*mach
,
3060 const struct tgsi_full_instruction
*inst
,
3062 enum tgsi_exec_datatype dst_datatype
,
3063 enum tgsi_exec_datatype src_datatype
)
3066 struct tgsi_exec_vector dst
;
3068 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3069 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3070 union tgsi_exec_channel src
;
3072 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
3073 op(&dst
.xyzw
[chan
], &src
);
3076 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3077 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3078 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3083 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
3084 const union tgsi_exec_channel
*src0
,
3085 const union tgsi_exec_channel
*src1
);
3088 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
3089 const struct tgsi_full_instruction
*inst
,
3091 enum tgsi_exec_datatype dst_datatype
,
3092 enum tgsi_exec_datatype src_datatype
)
3095 union tgsi_exec_channel src
[2];
3096 union tgsi_exec_channel dst
;
3098 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3099 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
3100 op(&dst
, &src
[0], &src
[1]);
3101 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3102 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3103 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3109 exec_vector_binary(struct tgsi_exec_machine
*mach
,
3110 const struct tgsi_full_instruction
*inst
,
3112 enum tgsi_exec_datatype dst_datatype
,
3113 enum tgsi_exec_datatype src_datatype
)
3116 struct tgsi_exec_vector dst
;
3118 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3119 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3120 union tgsi_exec_channel src
[2];
3122 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3123 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3124 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
3127 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3128 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3129 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3134 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
3135 const union tgsi_exec_channel
*src0
,
3136 const union tgsi_exec_channel
*src1
,
3137 const union tgsi_exec_channel
*src2
);
3140 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
3141 const struct tgsi_full_instruction
*inst
,
3142 micro_trinary_op op
,
3143 enum tgsi_exec_datatype dst_datatype
,
3144 enum tgsi_exec_datatype src_datatype
)
3147 struct tgsi_exec_vector dst
;
3149 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3150 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3151 union tgsi_exec_channel src
[3];
3153 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3154 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3155 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3156 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3159 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3160 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3161 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3166 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
3167 const union tgsi_exec_channel
*src0
,
3168 const union tgsi_exec_channel
*src1
,
3169 const union tgsi_exec_channel
*src2
,
3170 const union tgsi_exec_channel
*src3
);
3173 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
3174 const struct tgsi_full_instruction
*inst
,
3175 micro_quaternary_op op
,
3176 enum tgsi_exec_datatype dst_datatype
,
3177 enum tgsi_exec_datatype src_datatype
)
3180 struct tgsi_exec_vector dst
;
3182 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3183 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3184 union tgsi_exec_channel src
[4];
3186 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3187 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3188 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3189 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
3190 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
3193 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3194 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3195 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3201 exec_dp3(struct tgsi_exec_machine
*mach
,
3202 const struct tgsi_full_instruction
*inst
)
3205 union tgsi_exec_channel arg
[3];
3207 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3208 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3209 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3211 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
3212 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3213 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3214 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3217 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3218 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3219 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3225 exec_dp4(struct tgsi_exec_machine
*mach
,
3226 const struct tgsi_full_instruction
*inst
)
3229 union tgsi_exec_channel arg
[3];
3231 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3232 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3233 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3235 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
3236 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3237 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3238 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3241 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3242 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3243 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3249 exec_dp2a(struct tgsi_exec_machine
*mach
,
3250 const struct tgsi_full_instruction
*inst
)
3253 union tgsi_exec_channel arg
[3];
3255 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3256 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3257 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3259 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3260 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3261 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
3263 fetch_source(mach
, &arg
[1], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3264 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3266 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3267 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3268 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3274 exec_dph(struct tgsi_exec_machine
*mach
,
3275 const struct tgsi_full_instruction
*inst
)
3278 union tgsi_exec_channel arg
[3];
3280 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3281 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3282 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3284 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3285 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3286 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3288 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3289 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3290 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
3292 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3293 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3295 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3296 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3297 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3303 exec_dp2(struct tgsi_exec_machine
*mach
,
3304 const struct tgsi_full_instruction
*inst
)
3307 union tgsi_exec_channel arg
[3];
3309 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3310 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3311 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3313 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3314 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3315 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3317 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3318 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3319 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3325 exec_pk2h(struct tgsi_exec_machine
*mach
,
3326 const struct tgsi_full_instruction
*inst
)
3329 union tgsi_exec_channel arg
[2], dst
;
3331 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3332 fetch_source(mach
, &arg
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3333 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3334 dst
.u
[chan
] = util_float_to_half(arg
[0].f
[chan
]) |
3335 (util_float_to_half(arg
[1].f
[chan
]) << 16);
3337 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3338 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3339 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_UINT
);
3345 exec_up2h(struct tgsi_exec_machine
*mach
,
3346 const struct tgsi_full_instruction
*inst
)
3349 union tgsi_exec_channel arg
, dst
[2];
3351 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3352 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3353 dst
[0].f
[chan
] = util_half_to_float(arg
.u
[chan
] & 0xffff);
3354 dst
[1].f
[chan
] = util_half_to_float(arg
.u
[chan
] >> 16);
3356 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3357 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3358 store_dest(mach
, &dst
[chan
& 1], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3364 exec_scs(struct tgsi_exec_machine
*mach
,
3365 const struct tgsi_full_instruction
*inst
)
3367 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
3368 union tgsi_exec_channel arg
;
3369 union tgsi_exec_channel result
;
3371 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3373 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3374 micro_cos(&result
, &arg
);
3375 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3377 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3378 micro_sin(&result
, &arg
);
3379 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3382 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3383 store_dest(mach
, &ZeroVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3385 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3386 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3391 exec_xpd(struct tgsi_exec_machine
*mach
,
3392 const struct tgsi_full_instruction
*inst
)
3394 union tgsi_exec_channel r
[6];
3395 union tgsi_exec_channel d
[3];
3397 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3398 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3400 micro_mul(&r
[2], &r
[0], &r
[1]);
3402 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3403 fetch_source(mach
, &r
[4], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3405 micro_mul(&r
[5], &r
[3], &r
[4] );
3406 micro_sub(&d
[TGSI_CHAN_X
], &r
[2], &r
[5]);
3408 fetch_source(mach
, &r
[2], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3410 micro_mul(&r
[3], &r
[3], &r
[2]);
3412 fetch_source(mach
, &r
[5], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3414 micro_mul(&r
[1], &r
[1], &r
[5]);
3415 micro_sub(&d
[TGSI_CHAN_Y
], &r
[3], &r
[1]);
3417 micro_mul(&r
[5], &r
[5], &r
[4]);
3418 micro_mul(&r
[0], &r
[0], &r
[2]);
3419 micro_sub(&d
[TGSI_CHAN_Z
], &r
[5], &r
[0]);
3421 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3422 store_dest(mach
, &d
[TGSI_CHAN_X
], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3424 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3425 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3427 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3428 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3430 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3431 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3436 exec_dst(struct tgsi_exec_machine
*mach
,
3437 const struct tgsi_full_instruction
*inst
)
3439 union tgsi_exec_channel r
[2];
3440 union tgsi_exec_channel d
[4];
3442 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3443 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3444 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3445 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3447 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3448 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3450 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3451 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3454 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3455 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3457 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3458 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3460 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3461 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3463 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3464 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3469 exec_log(struct tgsi_exec_machine
*mach
,
3470 const struct tgsi_full_instruction
*inst
)
3472 union tgsi_exec_channel r
[3];
3474 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3475 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3476 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3477 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3478 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3479 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3481 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3482 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3483 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3484 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3486 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3487 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3489 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3490 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3495 exec_exp(struct tgsi_exec_machine
*mach
,
3496 const struct tgsi_full_instruction
*inst
)
3498 union tgsi_exec_channel r
[3];
3500 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3501 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3502 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3503 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3504 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3506 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3507 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3508 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3510 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3511 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3512 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3514 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3515 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3520 exec_lit(struct tgsi_exec_machine
*mach
,
3521 const struct tgsi_full_instruction
*inst
)
3523 union tgsi_exec_channel r
[3];
3524 union tgsi_exec_channel d
[3];
3526 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3527 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3528 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3529 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3530 micro_max(&r
[1], &r
[1], &ZeroVec
);
3532 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3533 micro_min(&r
[2], &r
[2], &P128Vec
);
3534 micro_max(&r
[2], &r
[2], &M128Vec
);
3535 micro_pow(&r
[1], &r
[1], &r
[2]);
3536 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3537 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3539 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3540 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3541 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3544 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3545 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3548 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3549 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3554 exec_break(struct tgsi_exec_machine
*mach
)
3556 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3557 /* turn off loop channels for each enabled exec channel */
3558 mach
->LoopMask
&= ~mach
->ExecMask
;
3559 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3560 UPDATE_EXEC_MASK(mach
);
3562 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3564 mach
->Switch
.mask
= 0x0;
3566 UPDATE_EXEC_MASK(mach
);
3571 exec_switch(struct tgsi_exec_machine
*mach
,
3572 const struct tgsi_full_instruction
*inst
)
3574 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3575 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3577 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3578 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3579 mach
->Switch
.mask
= 0x0;
3580 mach
->Switch
.defaultMask
= 0x0;
3582 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3583 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3585 UPDATE_EXEC_MASK(mach
);
3589 exec_case(struct tgsi_exec_machine
*mach
,
3590 const struct tgsi_full_instruction
*inst
)
3592 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3593 union tgsi_exec_channel src
;
3596 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3598 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3601 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3604 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3607 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3611 mach
->Switch
.defaultMask
|= mask
;
3613 mach
->Switch
.mask
|= mask
& prevMask
;
3615 UPDATE_EXEC_MASK(mach
);
3618 /* FIXME: this will only work if default is last */
3620 exec_default(struct tgsi_exec_machine
*mach
)
3622 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3624 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3626 UPDATE_EXEC_MASK(mach
);
3630 exec_endswitch(struct tgsi_exec_machine
*mach
)
3632 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3633 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3635 UPDATE_EXEC_MASK(mach
);
3638 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3639 const union tgsi_double_channel
*src
);
3641 typedef void (* micro_dop_sop
)(union tgsi_double_channel
*dst
,
3642 const union tgsi_double_channel
*src0
,
3643 union tgsi_exec_channel
*src1
);
3645 typedef void (* micro_dop_s
)(union tgsi_double_channel
*dst
,
3646 const union tgsi_exec_channel
*src
);
3648 typedef void (* micro_sop_d
)(union tgsi_exec_channel
*dst
,
3649 const union tgsi_double_channel
*src
);
3652 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3653 union tgsi_double_channel
*chan
,
3654 const struct tgsi_full_src_register
*reg
,
3658 union tgsi_exec_channel src
[2];
3661 fetch_source_d(mach
, &src
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3662 fetch_source_d(mach
, &src
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3664 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3665 chan
->u
[i
][0] = src
[0].u
[i
];
3666 chan
->u
[i
][1] = src
[1].u
[i
];
3668 if (reg
->Register
.Absolute
) {
3669 micro_dabs(chan
, chan
);
3671 if (reg
->Register
.Negate
) {
3672 micro_dneg(chan
, chan
);
3677 store_double_channel(struct tgsi_exec_machine
*mach
,
3678 const union tgsi_double_channel
*chan
,
3679 const struct tgsi_full_dst_register
*reg
,
3680 const struct tgsi_full_instruction
*inst
,
3684 union tgsi_exec_channel dst
[2];
3686 union tgsi_double_channel temp
;
3687 const uint execmask
= mach
->ExecMask
;
3689 if (!inst
->Instruction
.Saturate
) {
3690 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3691 if (execmask
& (1 << i
)) {
3692 dst
[0].u
[i
] = chan
->u
[i
][0];
3693 dst
[1].u
[i
] = chan
->u
[i
][1];
3697 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3698 if (execmask
& (1 << i
)) {
3699 if (chan
->d
[i
] < 0.0)
3701 else if (chan
->d
[i
] > 1.0)
3704 temp
.d
[i
] = chan
->d
[i
];
3706 dst
[0].u
[i
] = temp
.u
[i
][0];
3707 dst
[1].u
[i
] = temp
.u
[i
][1];
3711 store_dest_double(mach
, &dst
[0], reg
, inst
, chan_0
, TGSI_EXEC_DATA_UINT
);
3713 store_dest_double(mach
, &dst
[1], reg
, inst
, chan_1
, TGSI_EXEC_DATA_UINT
);
3717 exec_double_unary(struct tgsi_exec_machine
*mach
,
3718 const struct tgsi_full_instruction
*inst
,
3721 union tgsi_double_channel src
;
3722 union tgsi_double_channel dst
;
3724 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3725 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3727 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3729 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3730 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3732 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3737 exec_double_binary(struct tgsi_exec_machine
*mach
,
3738 const struct tgsi_full_instruction
*inst
,
3740 enum tgsi_exec_datatype dst_datatype
)
3742 union tgsi_double_channel src
[2];
3743 union tgsi_double_channel dst
;
3744 int first_dest_chan
, second_dest_chan
;
3747 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3748 /* these are & because of the way DSLT etc store their destinations */
3749 if (wmask
& TGSI_WRITEMASK_XY
) {
3750 first_dest_chan
= TGSI_CHAN_X
;
3751 second_dest_chan
= TGSI_CHAN_Y
;
3752 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3753 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3754 second_dest_chan
= -1;
3757 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3758 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3760 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3763 if (wmask
& TGSI_WRITEMASK_ZW
) {
3764 first_dest_chan
= TGSI_CHAN_Z
;
3765 second_dest_chan
= TGSI_CHAN_W
;
3766 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3767 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3768 second_dest_chan
= -1;
3771 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3772 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3774 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3779 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3780 const struct tgsi_full_instruction
*inst
,
3783 union tgsi_double_channel src
[3];
3784 union tgsi_double_channel dst
;
3786 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3787 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3788 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3789 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3791 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3793 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3794 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3795 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3796 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3798 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3803 exec_dldexp(struct tgsi_exec_machine
*mach
,
3804 const struct tgsi_full_instruction
*inst
)
3806 union tgsi_double_channel src0
;
3807 union tgsi_exec_channel src1
;
3808 union tgsi_double_channel dst
;
3811 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3812 if (wmask
& TGSI_WRITEMASK_XY
) {
3813 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3814 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3815 micro_dldexp(&dst
, &src0
, &src1
);
3816 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3819 if (wmask
& TGSI_WRITEMASK_ZW
) {
3820 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3821 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3822 micro_dldexp(&dst
, &src0
, &src1
);
3823 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3828 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3829 const struct tgsi_full_instruction
*inst
)
3831 union tgsi_double_channel src
;
3832 union tgsi_double_channel dst
;
3833 union tgsi_exec_channel dst_exp
;
3835 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)) {
3836 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3837 micro_dfracexp(&dst
, &dst_exp
, &src
);
3838 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3839 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3841 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)) {
3842 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3843 micro_dfracexp(&dst
, &dst_exp
, &src
);
3844 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3845 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3850 exec_arg0_64_arg1_32(struct tgsi_exec_machine
*mach
,
3851 const struct tgsi_full_instruction
*inst
,
3854 union tgsi_double_channel src0
;
3855 union tgsi_exec_channel src1
;
3856 union tgsi_double_channel dst
;
3859 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3860 if (wmask
& TGSI_WRITEMASK_XY
) {
3861 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3862 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3863 op(&dst
, &src0
, &src1
);
3864 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3867 if (wmask
& TGSI_WRITEMASK_ZW
) {
3868 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3869 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3870 op(&dst
, &src0
, &src1
);
3871 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3876 get_image_coord_dim(unsigned tgsi_tex
)
3880 case TGSI_TEXTURE_BUFFER
:
3881 case TGSI_TEXTURE_1D
:
3884 case TGSI_TEXTURE_2D
:
3885 case TGSI_TEXTURE_RECT
:
3886 case TGSI_TEXTURE_1D_ARRAY
:
3887 case TGSI_TEXTURE_2D_MSAA
:
3890 case TGSI_TEXTURE_3D
:
3891 case TGSI_TEXTURE_CUBE
:
3892 case TGSI_TEXTURE_2D_ARRAY
:
3893 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3894 case TGSI_TEXTURE_CUBE_ARRAY
:
3898 assert(!"unknown texture target");
3907 get_image_coord_sample(unsigned tgsi_tex
)
3911 case TGSI_TEXTURE_2D_MSAA
:
3914 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3924 exec_load_img(struct tgsi_exec_machine
*mach
,
3925 const struct tgsi_full_instruction
*inst
)
3927 union tgsi_exec_channel r
[4], sample_r
;
3933 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3934 struct tgsi_image_params params
;
3935 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3937 unit
= fetch_sampler_unit(mach
, inst
, 0);
3938 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3939 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3942 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3944 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3945 params
.format
= inst
->Memory
.Format
;
3947 for (i
= 0; i
< dim
; i
++) {
3948 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3952 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3954 mach
->Image
->load(mach
->Image
, ¶ms
,
3955 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3957 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3958 r
[0].f
[j
] = rgba
[0][j
];
3959 r
[1].f
[j
] = rgba
[1][j
];
3960 r
[2].f
[j
] = rgba
[2][j
];
3961 r
[3].f
[j
] = rgba
[3][j
];
3963 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3964 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3965 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3971 exec_load_buf(struct tgsi_exec_machine
*mach
,
3972 const struct tgsi_full_instruction
*inst
)
3974 union tgsi_exec_channel r
[4];
3978 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3979 struct tgsi_buffer_params params
;
3980 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3982 unit
= fetch_sampler_unit(mach
, inst
, 0);
3984 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3986 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3988 mach
->Buffer
->load(mach
->Buffer
, ¶ms
,
3990 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3991 r
[0].f
[j
] = rgba
[0][j
];
3992 r
[1].f
[j
] = rgba
[1][j
];
3993 r
[2].f
[j
] = rgba
[2][j
];
3994 r
[3].f
[j
] = rgba
[3][j
];
3996 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3997 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3998 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4004 exec_load_mem(struct tgsi_exec_machine
*mach
,
4005 const struct tgsi_full_instruction
*inst
)
4007 union tgsi_exec_channel r
[4];
4009 char *ptr
= mach
->LocalMem
;
4013 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4014 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4020 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4021 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4022 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4023 memcpy(&r
[chan
].u
[j
], ptr
+ (4 * chan
), 4);
4028 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4029 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4030 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4036 exec_load(struct tgsi_exec_machine
*mach
,
4037 const struct tgsi_full_instruction
*inst
)
4039 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4040 exec_load_img(mach
, inst
);
4041 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4042 exec_load_buf(mach
, inst
);
4043 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4044 exec_load_mem(mach
, inst
);
4048 exec_store_img(struct tgsi_exec_machine
*mach
,
4049 const struct tgsi_full_instruction
*inst
)
4051 union tgsi_exec_channel r
[3], sample_r
;
4052 union tgsi_exec_channel value
[4];
4053 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4054 struct tgsi_image_params params
;
4059 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4060 unit
= inst
->Dst
[0].Register
.Index
;
4061 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4062 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4065 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4067 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4068 params
.format
= inst
->Memory
.Format
;
4070 for (i
= 0; i
< dim
; i
++) {
4071 IFETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
4074 for (i
= 0; i
< 4; i
++) {
4075 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4078 IFETCH(&sample_r
, 0, TGSI_CHAN_X
+ sample
);
4080 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4081 rgba
[0][j
] = value
[0].f
[j
];
4082 rgba
[1][j
] = value
[1].f
[j
];
4083 rgba
[2][j
] = value
[2].f
[j
];
4084 rgba
[3][j
] = value
[3].f
[j
];
4087 mach
->Image
->store(mach
->Image
, ¶ms
,
4088 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4093 exec_store_buf(struct tgsi_exec_machine
*mach
,
4094 const struct tgsi_full_instruction
*inst
)
4096 union tgsi_exec_channel r
[3];
4097 union tgsi_exec_channel value
[4];
4098 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4099 struct tgsi_buffer_params params
;
4102 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4104 unit
= inst
->Dst
[0].Register
.Index
;
4106 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4108 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4110 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4111 for (i
= 0; i
< 4; i
++) {
4112 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4115 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4116 rgba
[0][j
] = value
[0].f
[j
];
4117 rgba
[1][j
] = value
[1].f
[j
];
4118 rgba
[2][j
] = value
[2].f
[j
];
4119 rgba
[3][j
] = value
[3].f
[j
];
4122 mach
->Buffer
->store(mach
->Buffer
, ¶ms
,
4128 exec_store_mem(struct tgsi_exec_machine
*mach
,
4129 const struct tgsi_full_instruction
*inst
)
4131 union tgsi_exec_channel r
[3];
4132 union tgsi_exec_channel value
[4];
4134 char *ptr
= mach
->LocalMem
;
4135 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4136 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4138 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4140 for (i
= 0; i
< 4; i
++) {
4141 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4144 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4148 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4149 if (execmask
& (1 << i
)) {
4150 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4151 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4152 memcpy(ptr
+ (chan
* 4), &value
[chan
].u
[0], 4);
4160 exec_store(struct tgsi_exec_machine
*mach
,
4161 const struct tgsi_full_instruction
*inst
)
4163 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
)
4164 exec_store_img(mach
, inst
);
4165 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
)
4166 exec_store_buf(mach
, inst
);
4167 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
)
4168 exec_store_mem(mach
, inst
);
4172 exec_atomop_img(struct tgsi_exec_machine
*mach
,
4173 const struct tgsi_full_instruction
*inst
)
4175 union tgsi_exec_channel r
[4], sample_r
;
4176 union tgsi_exec_channel value
[4], value2
[4];
4177 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4178 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4179 struct tgsi_image_params params
;
4184 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4185 unit
= fetch_sampler_unit(mach
, inst
, 0);
4186 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4187 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4190 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4192 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4193 params
.format
= inst
->Memory
.Format
;
4195 for (i
= 0; i
< dim
; i
++) {
4196 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
4199 for (i
= 0; i
< 4; i
++) {
4200 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4201 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4202 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4205 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
4207 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4208 rgba
[0][j
] = value
[0].f
[j
];
4209 rgba
[1][j
] = value
[1].f
[j
];
4210 rgba
[2][j
] = value
[2].f
[j
];
4211 rgba
[3][j
] = value
[3].f
[j
];
4213 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4214 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4215 rgba2
[0][j
] = value2
[0].f
[j
];
4216 rgba2
[1][j
] = value2
[1].f
[j
];
4217 rgba2
[2][j
] = value2
[2].f
[j
];
4218 rgba2
[3][j
] = value2
[3].f
[j
];
4222 mach
->Image
->op(mach
->Image
, ¶ms
, inst
->Instruction
.Opcode
,
4223 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4226 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4227 r
[0].f
[j
] = rgba
[0][j
];
4228 r
[1].f
[j
] = rgba
[1][j
];
4229 r
[2].f
[j
] = rgba
[2][j
];
4230 r
[3].f
[j
] = rgba
[3][j
];
4232 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4233 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4234 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4240 exec_atomop_buf(struct tgsi_exec_machine
*mach
,
4241 const struct tgsi_full_instruction
*inst
)
4243 union tgsi_exec_channel r
[4];
4244 union tgsi_exec_channel value
[4], value2
[4];
4245 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4246 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4247 struct tgsi_buffer_params params
;
4250 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4252 unit
= fetch_sampler_unit(mach
, inst
, 0);
4254 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4256 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4258 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4260 for (i
= 0; i
< 4; i
++) {
4261 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4262 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4263 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4266 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4267 rgba
[0][j
] = value
[0].f
[j
];
4268 rgba
[1][j
] = value
[1].f
[j
];
4269 rgba
[2][j
] = value
[2].f
[j
];
4270 rgba
[3][j
] = value
[3].f
[j
];
4272 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4273 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4274 rgba2
[0][j
] = value2
[0].f
[j
];
4275 rgba2
[1][j
] = value2
[1].f
[j
];
4276 rgba2
[2][j
] = value2
[2].f
[j
];
4277 rgba2
[3][j
] = value2
[3].f
[j
];
4281 mach
->Buffer
->op(mach
->Buffer
, ¶ms
, inst
->Instruction
.Opcode
,
4285 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4286 r
[0].f
[j
] = rgba
[0][j
];
4287 r
[1].f
[j
] = rgba
[1][j
];
4288 r
[2].f
[j
] = rgba
[2][j
];
4289 r
[3].f
[j
] = rgba
[3][j
];
4291 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4292 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4293 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4299 exec_atomop_mem(struct tgsi_exec_machine
*mach
,
4300 const struct tgsi_full_instruction
*inst
)
4302 union tgsi_exec_channel r
[4];
4303 union tgsi_exec_channel value
[4], value2
[4];
4304 char *ptr
= mach
->LocalMem
;
4308 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4309 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4310 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4312 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4317 for (i
= 0; i
< 4; i
++) {
4318 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4319 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4320 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4323 memcpy(&r
[0].u
[0], ptr
, 4);
4325 switch (inst
->Instruction
.Opcode
) {
4326 case TGSI_OPCODE_ATOMUADD
:
4327 val
+= value
[0].u
[0];
4329 case TGSI_OPCODE_ATOMXOR
:
4330 val
^= value
[0].u
[0];
4332 case TGSI_OPCODE_ATOMOR
:
4333 val
|= value
[0].u
[0];
4335 case TGSI_OPCODE_ATOMAND
:
4336 val
&= value
[0].u
[0];
4338 case TGSI_OPCODE_ATOMUMIN
:
4339 val
= MIN2(val
, value
[0].u
[0]);
4341 case TGSI_OPCODE_ATOMUMAX
:
4342 val
= MAX2(val
, value
[0].u
[0]);
4344 case TGSI_OPCODE_ATOMIMIN
:
4345 val
= MIN2(r
[0].i
[0], value
[0].i
[0]);
4347 case TGSI_OPCODE_ATOMIMAX
:
4348 val
= MAX2(r
[0].i
[0], value
[0].i
[0]);
4350 case TGSI_OPCODE_ATOMXCHG
:
4351 val
= value
[0].i
[0];
4353 case TGSI_OPCODE_ATOMCAS
:
4354 if (val
== value
[0].u
[0])
4355 val
= value2
[0].u
[0];
4360 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
4361 if (execmask
& (1 << i
))
4362 memcpy(ptr
, &val
, 4);
4364 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4365 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4366 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4372 exec_atomop(struct tgsi_exec_machine
*mach
,
4373 const struct tgsi_full_instruction
*inst
)
4375 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4376 exec_atomop_img(mach
, inst
);
4377 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4378 exec_atomop_buf(mach
, inst
);
4379 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4380 exec_atomop_mem(mach
, inst
);
4384 exec_resq_img(struct tgsi_exec_machine
*mach
,
4385 const struct tgsi_full_instruction
*inst
)
4388 union tgsi_exec_channel r
[4];
4391 struct tgsi_image_params params
;
4392 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4394 unit
= fetch_sampler_unit(mach
, inst
, 0);
4396 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4398 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4399 params
.format
= inst
->Memory
.Format
;
4401 mach
->Image
->get_dims(mach
->Image
, ¶ms
, result
);
4403 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4404 for (j
= 0; j
< 4; j
++) {
4405 r
[j
].i
[i
] = result
[j
];
4409 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4410 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4411 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4412 TGSI_EXEC_DATA_INT
);
4418 exec_resq_buf(struct tgsi_exec_machine
*mach
,
4419 const struct tgsi_full_instruction
*inst
)
4422 union tgsi_exec_channel r
[4];
4425 struct tgsi_buffer_params params
;
4426 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4428 unit
= fetch_sampler_unit(mach
, inst
, 0);
4430 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4433 mach
->Buffer
->get_dims(mach
->Buffer
, ¶ms
, &result
);
4435 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4439 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4440 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4441 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4442 TGSI_EXEC_DATA_INT
);
4448 exec_resq(struct tgsi_exec_machine
*mach
,
4449 const struct tgsi_full_instruction
*inst
)
4451 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4452 exec_resq_img(mach
, inst
);
4454 exec_resq_buf(mach
, inst
);
4458 micro_f2u64(union tgsi_double_channel
*dst
,
4459 const union tgsi_exec_channel
*src
)
4461 dst
->u64
[0] = (uint64_t)src
->f
[0];
4462 dst
->u64
[1] = (uint64_t)src
->f
[1];
4463 dst
->u64
[2] = (uint64_t)src
->f
[2];
4464 dst
->u64
[3] = (uint64_t)src
->f
[3];
4468 micro_f2i64(union tgsi_double_channel
*dst
,
4469 const union tgsi_exec_channel
*src
)
4471 dst
->i64
[0] = (int64_t)src
->f
[0];
4472 dst
->i64
[1] = (int64_t)src
->f
[1];
4473 dst
->i64
[2] = (int64_t)src
->f
[2];
4474 dst
->i64
[3] = (int64_t)src
->f
[3];
4478 micro_u2i64(union tgsi_double_channel
*dst
,
4479 const union tgsi_exec_channel
*src
)
4481 dst
->u64
[0] = (uint64_t)src
->u
[0];
4482 dst
->u64
[1] = (uint64_t)src
->u
[1];
4483 dst
->u64
[2] = (uint64_t)src
->u
[2];
4484 dst
->u64
[3] = (uint64_t)src
->u
[3];
4488 micro_i2i64(union tgsi_double_channel
*dst
,
4489 const union tgsi_exec_channel
*src
)
4491 dst
->i64
[0] = (int64_t)src
->i
[0];
4492 dst
->i64
[1] = (int64_t)src
->i
[1];
4493 dst
->i64
[2] = (int64_t)src
->i
[2];
4494 dst
->i64
[3] = (int64_t)src
->i
[3];
4498 micro_d2u64(union tgsi_double_channel
*dst
,
4499 const union tgsi_double_channel
*src
)
4501 dst
->u64
[0] = (uint64_t)src
->d
[0];
4502 dst
->u64
[1] = (uint64_t)src
->d
[1];
4503 dst
->u64
[2] = (uint64_t)src
->d
[2];
4504 dst
->u64
[3] = (uint64_t)src
->d
[3];
4508 micro_d2i64(union tgsi_double_channel
*dst
,
4509 const union tgsi_double_channel
*src
)
4511 dst
->i64
[0] = (int64_t)src
->d
[0];
4512 dst
->i64
[1] = (int64_t)src
->d
[1];
4513 dst
->i64
[2] = (int64_t)src
->d
[2];
4514 dst
->i64
[3] = (int64_t)src
->d
[3];
4518 micro_u642d(union tgsi_double_channel
*dst
,
4519 const union tgsi_double_channel
*src
)
4521 dst
->d
[0] = (double)src
->u64
[0];
4522 dst
->d
[1] = (double)src
->u64
[1];
4523 dst
->d
[2] = (double)src
->u64
[2];
4524 dst
->d
[3] = (double)src
->u64
[3];
4528 micro_i642d(union tgsi_double_channel
*dst
,
4529 const union tgsi_double_channel
*src
)
4531 dst
->d
[0] = (double)src
->i64
[0];
4532 dst
->d
[1] = (double)src
->i64
[1];
4533 dst
->d
[2] = (double)src
->i64
[2];
4534 dst
->d
[3] = (double)src
->i64
[3];
4538 micro_u642f(union tgsi_exec_channel
*dst
,
4539 const union tgsi_double_channel
*src
)
4541 dst
->f
[0] = (float)src
->u64
[0];
4542 dst
->f
[1] = (float)src
->u64
[1];
4543 dst
->f
[2] = (float)src
->u64
[2];
4544 dst
->f
[3] = (float)src
->u64
[3];
4548 micro_i642f(union tgsi_exec_channel
*dst
,
4549 const union tgsi_double_channel
*src
)
4551 dst
->f
[0] = (float)src
->i64
[0];
4552 dst
->f
[1] = (float)src
->i64
[1];
4553 dst
->f
[2] = (float)src
->i64
[2];
4554 dst
->f
[3] = (float)src
->i64
[3];
4558 exec_t_2_64(struct tgsi_exec_machine
*mach
,
4559 const struct tgsi_full_instruction
*inst
,
4561 enum tgsi_exec_datatype src_datatype
)
4563 union tgsi_exec_channel src
;
4564 union tgsi_double_channel dst
;
4566 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
4567 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
4569 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
4571 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
4572 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, src_datatype
);
4574 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
4579 exec_64_2_t(struct tgsi_exec_machine
*mach
,
4580 const struct tgsi_full_instruction
*inst
,
4582 enum tgsi_exec_datatype dst_datatype
)
4584 union tgsi_double_channel src
;
4585 union tgsi_exec_channel dst
;
4586 int wm
= inst
->Dst
[0].Register
.WriteMask
;
4589 for (i
= 0; i
< 2; i
++) {
4592 wm
&= ~(1 << (bit
- 1));
4594 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
4596 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
4598 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, dst_datatype
);
4604 micro_i2f(union tgsi_exec_channel
*dst
,
4605 const union tgsi_exec_channel
*src
)
4607 dst
->f
[0] = (float)src
->i
[0];
4608 dst
->f
[1] = (float)src
->i
[1];
4609 dst
->f
[2] = (float)src
->i
[2];
4610 dst
->f
[3] = (float)src
->i
[3];
4614 micro_not(union tgsi_exec_channel
*dst
,
4615 const union tgsi_exec_channel
*src
)
4617 dst
->u
[0] = ~src
->u
[0];
4618 dst
->u
[1] = ~src
->u
[1];
4619 dst
->u
[2] = ~src
->u
[2];
4620 dst
->u
[3] = ~src
->u
[3];
4624 micro_shl(union tgsi_exec_channel
*dst
,
4625 const union tgsi_exec_channel
*src0
,
4626 const union tgsi_exec_channel
*src1
)
4628 unsigned masked_count
;
4629 masked_count
= src1
->u
[0] & 0x1f;
4630 dst
->u
[0] = src0
->u
[0] << masked_count
;
4631 masked_count
= src1
->u
[1] & 0x1f;
4632 dst
->u
[1] = src0
->u
[1] << masked_count
;
4633 masked_count
= src1
->u
[2] & 0x1f;
4634 dst
->u
[2] = src0
->u
[2] << masked_count
;
4635 masked_count
= src1
->u
[3] & 0x1f;
4636 dst
->u
[3] = src0
->u
[3] << masked_count
;
4640 micro_and(union tgsi_exec_channel
*dst
,
4641 const union tgsi_exec_channel
*src0
,
4642 const union tgsi_exec_channel
*src1
)
4644 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
4645 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
4646 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
4647 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
4651 micro_or(union tgsi_exec_channel
*dst
,
4652 const union tgsi_exec_channel
*src0
,
4653 const union tgsi_exec_channel
*src1
)
4655 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
4656 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
4657 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
4658 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
4662 micro_xor(union tgsi_exec_channel
*dst
,
4663 const union tgsi_exec_channel
*src0
,
4664 const union tgsi_exec_channel
*src1
)
4666 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
4667 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
4668 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
4669 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
4673 micro_mod(union tgsi_exec_channel
*dst
,
4674 const union tgsi_exec_channel
*src0
,
4675 const union tgsi_exec_channel
*src1
)
4677 dst
->i
[0] = src0
->i
[0] % src1
->i
[0];
4678 dst
->i
[1] = src0
->i
[1] % src1
->i
[1];
4679 dst
->i
[2] = src0
->i
[2] % src1
->i
[2];
4680 dst
->i
[3] = src0
->i
[3] % src1
->i
[3];
4684 micro_f2i(union tgsi_exec_channel
*dst
,
4685 const union tgsi_exec_channel
*src
)
4687 dst
->i
[0] = (int)src
->f
[0];
4688 dst
->i
[1] = (int)src
->f
[1];
4689 dst
->i
[2] = (int)src
->f
[2];
4690 dst
->i
[3] = (int)src
->f
[3];
4694 micro_fseq(union tgsi_exec_channel
*dst
,
4695 const union tgsi_exec_channel
*src0
,
4696 const union tgsi_exec_channel
*src1
)
4698 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
4699 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
4700 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
4701 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
4705 micro_fsge(union tgsi_exec_channel
*dst
,
4706 const union tgsi_exec_channel
*src0
,
4707 const union tgsi_exec_channel
*src1
)
4709 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
4710 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
4711 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
4712 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
4716 micro_fslt(union tgsi_exec_channel
*dst
,
4717 const union tgsi_exec_channel
*src0
,
4718 const union tgsi_exec_channel
*src1
)
4720 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
4721 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
4722 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
4723 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
4727 micro_fsne(union tgsi_exec_channel
*dst
,
4728 const union tgsi_exec_channel
*src0
,
4729 const union tgsi_exec_channel
*src1
)
4731 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
4732 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
4733 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
4734 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
4738 micro_idiv(union tgsi_exec_channel
*dst
,
4739 const union tgsi_exec_channel
*src0
,
4740 const union tgsi_exec_channel
*src1
)
4742 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
4743 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
4744 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
4745 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
4749 micro_imax(union tgsi_exec_channel
*dst
,
4750 const union tgsi_exec_channel
*src0
,
4751 const union tgsi_exec_channel
*src1
)
4753 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4754 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4755 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4756 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4760 micro_imin(union tgsi_exec_channel
*dst
,
4761 const union tgsi_exec_channel
*src0
,
4762 const union tgsi_exec_channel
*src1
)
4764 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4765 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4766 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4767 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4771 micro_isge(union tgsi_exec_channel
*dst
,
4772 const union tgsi_exec_channel
*src0
,
4773 const union tgsi_exec_channel
*src1
)
4775 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
4776 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
4777 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
4778 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
4782 micro_ishr(union tgsi_exec_channel
*dst
,
4783 const union tgsi_exec_channel
*src0
,
4784 const union tgsi_exec_channel
*src1
)
4786 unsigned masked_count
;
4787 masked_count
= src1
->i
[0] & 0x1f;
4788 dst
->i
[0] = src0
->i
[0] >> masked_count
;
4789 masked_count
= src1
->i
[1] & 0x1f;
4790 dst
->i
[1] = src0
->i
[1] >> masked_count
;
4791 masked_count
= src1
->i
[2] & 0x1f;
4792 dst
->i
[2] = src0
->i
[2] >> masked_count
;
4793 masked_count
= src1
->i
[3] & 0x1f;
4794 dst
->i
[3] = src0
->i
[3] >> masked_count
;
4798 micro_islt(union tgsi_exec_channel
*dst
,
4799 const union tgsi_exec_channel
*src0
,
4800 const union tgsi_exec_channel
*src1
)
4802 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
4803 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
4804 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
4805 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
4809 micro_f2u(union tgsi_exec_channel
*dst
,
4810 const union tgsi_exec_channel
*src
)
4812 dst
->u
[0] = (uint
)src
->f
[0];
4813 dst
->u
[1] = (uint
)src
->f
[1];
4814 dst
->u
[2] = (uint
)src
->f
[2];
4815 dst
->u
[3] = (uint
)src
->f
[3];
4819 micro_u2f(union tgsi_exec_channel
*dst
,
4820 const union tgsi_exec_channel
*src
)
4822 dst
->f
[0] = (float)src
->u
[0];
4823 dst
->f
[1] = (float)src
->u
[1];
4824 dst
->f
[2] = (float)src
->u
[2];
4825 dst
->f
[3] = (float)src
->u
[3];
4829 micro_uadd(union tgsi_exec_channel
*dst
,
4830 const union tgsi_exec_channel
*src0
,
4831 const union tgsi_exec_channel
*src1
)
4833 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
4834 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
4835 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
4836 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
4840 micro_udiv(union tgsi_exec_channel
*dst
,
4841 const union tgsi_exec_channel
*src0
,
4842 const union tgsi_exec_channel
*src1
)
4844 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
4845 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
4846 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
4847 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
4851 micro_umad(union tgsi_exec_channel
*dst
,
4852 const union tgsi_exec_channel
*src0
,
4853 const union tgsi_exec_channel
*src1
,
4854 const union tgsi_exec_channel
*src2
)
4856 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
4857 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
4858 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
4859 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
4863 micro_umax(union tgsi_exec_channel
*dst
,
4864 const union tgsi_exec_channel
*src0
,
4865 const union tgsi_exec_channel
*src1
)
4867 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4868 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4869 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4870 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4874 micro_umin(union tgsi_exec_channel
*dst
,
4875 const union tgsi_exec_channel
*src0
,
4876 const union tgsi_exec_channel
*src1
)
4878 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4879 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4880 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4881 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4885 micro_umod(union tgsi_exec_channel
*dst
,
4886 const union tgsi_exec_channel
*src0
,
4887 const union tgsi_exec_channel
*src1
)
4889 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
4890 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
4891 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
4892 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
4896 micro_umul(union tgsi_exec_channel
*dst
,
4897 const union tgsi_exec_channel
*src0
,
4898 const union tgsi_exec_channel
*src1
)
4900 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
4901 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
4902 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
4903 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
4907 micro_imul_hi(union tgsi_exec_channel
*dst
,
4908 const union tgsi_exec_channel
*src0
,
4909 const union tgsi_exec_channel
*src1
)
4911 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4912 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
4913 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
4914 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
4915 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
4920 micro_umul_hi(union tgsi_exec_channel
*dst
,
4921 const union tgsi_exec_channel
*src0
,
4922 const union tgsi_exec_channel
*src1
)
4924 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4925 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
4926 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
4927 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
4928 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
4933 micro_useq(union tgsi_exec_channel
*dst
,
4934 const union tgsi_exec_channel
*src0
,
4935 const union tgsi_exec_channel
*src1
)
4937 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
4938 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
4939 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
4940 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4944 micro_usge(union tgsi_exec_channel
*dst
,
4945 const union tgsi_exec_channel
*src0
,
4946 const union tgsi_exec_channel
*src1
)
4948 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4949 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4950 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4951 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
4955 micro_ushr(union tgsi_exec_channel
*dst
,
4956 const union tgsi_exec_channel
*src0
,
4957 const union tgsi_exec_channel
*src1
)
4959 unsigned masked_count
;
4960 masked_count
= src1
->u
[0] & 0x1f;
4961 dst
->u
[0] = src0
->u
[0] >> masked_count
;
4962 masked_count
= src1
->u
[1] & 0x1f;
4963 dst
->u
[1] = src0
->u
[1] >> masked_count
;
4964 masked_count
= src1
->u
[2] & 0x1f;
4965 dst
->u
[2] = src0
->u
[2] >> masked_count
;
4966 masked_count
= src1
->u
[3] & 0x1f;
4967 dst
->u
[3] = src0
->u
[3] >> masked_count
;
4971 micro_uslt(union tgsi_exec_channel
*dst
,
4972 const union tgsi_exec_channel
*src0
,
4973 const union tgsi_exec_channel
*src1
)
4975 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
4976 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
4977 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
4978 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
4982 micro_usne(union tgsi_exec_channel
*dst
,
4983 const union tgsi_exec_channel
*src0
,
4984 const union tgsi_exec_channel
*src1
)
4986 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
4987 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
4988 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
4989 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
4993 micro_uarl(union tgsi_exec_channel
*dst
,
4994 const union tgsi_exec_channel
*src
)
4996 dst
->i
[0] = src
->u
[0];
4997 dst
->i
[1] = src
->u
[1];
4998 dst
->i
[2] = src
->u
[2];
4999 dst
->i
[3] = src
->u
[3];
5003 micro_ucmp(union tgsi_exec_channel
*dst
,
5004 const union tgsi_exec_channel
*src0
,
5005 const union tgsi_exec_channel
*src1
,
5006 const union tgsi_exec_channel
*src2
)
5008 dst
->u
[0] = src0
->u
[0] ? src1
->u
[0] : src2
->u
[0];
5009 dst
->u
[1] = src0
->u
[1] ? src1
->u
[1] : src2
->u
[1];
5010 dst
->u
[2] = src0
->u
[2] ? src1
->u
[2] : src2
->u
[2];
5011 dst
->u
[3] = src0
->u
[3] ? src1
->u
[3] : src2
->u
[3];
5015 * Signed bitfield extract (i.e. sign-extend the extracted bits)
5018 micro_ibfe(union tgsi_exec_channel
*dst
,
5019 const union tgsi_exec_channel
*src0
,
5020 const union tgsi_exec_channel
*src1
,
5021 const union tgsi_exec_channel
*src2
)
5024 for (i
= 0; i
< 4; i
++) {
5025 int width
= src2
->i
[i
] & 0x1f;
5026 int offset
= src1
->i
[i
] & 0x1f;
5029 else if (width
+ offset
< 32)
5030 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
5032 dst
->i
[i
] = src0
->i
[i
] >> offset
;
5037 * Unsigned bitfield extract
5040 micro_ubfe(union tgsi_exec_channel
*dst
,
5041 const union tgsi_exec_channel
*src0
,
5042 const union tgsi_exec_channel
*src1
,
5043 const union tgsi_exec_channel
*src2
)
5046 for (i
= 0; i
< 4; i
++) {
5047 int width
= src2
->u
[i
] & 0x1f;
5048 int offset
= src1
->u
[i
] & 0x1f;
5051 else if (width
+ offset
< 32)
5052 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
5054 dst
->u
[i
] = src0
->u
[i
] >> offset
;
5059 * Bitfield insert: copy low bits from src1 into a region of src0.
5062 micro_bfi(union tgsi_exec_channel
*dst
,
5063 const union tgsi_exec_channel
*src0
,
5064 const union tgsi_exec_channel
*src1
,
5065 const union tgsi_exec_channel
*src2
,
5066 const union tgsi_exec_channel
*src3
)
5069 for (i
= 0; i
< 4; i
++) {
5070 int width
= src3
->u
[i
] & 0x1f;
5071 int offset
= src2
->u
[i
] & 0x1f;
5072 int bitmask
= ((1 << width
) - 1) << offset
;
5073 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
5078 micro_brev(union tgsi_exec_channel
*dst
,
5079 const union tgsi_exec_channel
*src
)
5081 dst
->u
[0] = util_bitreverse(src
->u
[0]);
5082 dst
->u
[1] = util_bitreverse(src
->u
[1]);
5083 dst
->u
[2] = util_bitreverse(src
->u
[2]);
5084 dst
->u
[3] = util_bitreverse(src
->u
[3]);
5088 micro_popc(union tgsi_exec_channel
*dst
,
5089 const union tgsi_exec_channel
*src
)
5091 dst
->u
[0] = util_bitcount(src
->u
[0]);
5092 dst
->u
[1] = util_bitcount(src
->u
[1]);
5093 dst
->u
[2] = util_bitcount(src
->u
[2]);
5094 dst
->u
[3] = util_bitcount(src
->u
[3]);
5098 micro_lsb(union tgsi_exec_channel
*dst
,
5099 const union tgsi_exec_channel
*src
)
5101 dst
->i
[0] = ffs(src
->u
[0]) - 1;
5102 dst
->i
[1] = ffs(src
->u
[1]) - 1;
5103 dst
->i
[2] = ffs(src
->u
[2]) - 1;
5104 dst
->i
[3] = ffs(src
->u
[3]) - 1;
5108 micro_imsb(union tgsi_exec_channel
*dst
,
5109 const union tgsi_exec_channel
*src
)
5111 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
5112 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
5113 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
5114 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
5118 micro_umsb(union tgsi_exec_channel
*dst
,
5119 const union tgsi_exec_channel
*src
)
5121 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
5122 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
5123 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
5124 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
5128 * Execute a TGSI instruction.
5129 * Returns TRUE if a barrier instruction is hit,
5134 struct tgsi_exec_machine
*mach
,
5135 const struct tgsi_full_instruction
*inst
,
5138 union tgsi_exec_channel r
[10];
5142 switch (inst
->Instruction
.Opcode
) {
5143 case TGSI_OPCODE_ARL
:
5144 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5147 case TGSI_OPCODE_MOV
:
5148 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5151 case TGSI_OPCODE_LIT
:
5152 exec_lit(mach
, inst
);
5155 case TGSI_OPCODE_RCP
:
5156 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5159 case TGSI_OPCODE_RSQ
:
5160 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5163 case TGSI_OPCODE_EXP
:
5164 exec_exp(mach
, inst
);
5167 case TGSI_OPCODE_LOG
:
5168 exec_log(mach
, inst
);
5171 case TGSI_OPCODE_MUL
:
5172 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5175 case TGSI_OPCODE_ADD
:
5176 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5179 case TGSI_OPCODE_DP3
:
5180 exec_dp3(mach
, inst
);
5183 case TGSI_OPCODE_DP4
:
5184 exec_dp4(mach
, inst
);
5187 case TGSI_OPCODE_DST
:
5188 exec_dst(mach
, inst
);
5191 case TGSI_OPCODE_MIN
:
5192 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5195 case TGSI_OPCODE_MAX
:
5196 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5199 case TGSI_OPCODE_SLT
:
5200 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5203 case TGSI_OPCODE_SGE
:
5204 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5207 case TGSI_OPCODE_MAD
:
5208 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5211 case TGSI_OPCODE_SUB
:
5212 exec_vector_binary(mach
, inst
, micro_sub
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5215 case TGSI_OPCODE_LRP
:
5216 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5219 case TGSI_OPCODE_SQRT
:
5220 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5223 case TGSI_OPCODE_DP2A
:
5224 exec_dp2a(mach
, inst
);
5227 case TGSI_OPCODE_FRC
:
5228 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5231 case TGSI_OPCODE_CLAMP
:
5232 exec_vector_trinary(mach
, inst
, micro_clamp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5235 case TGSI_OPCODE_FLR
:
5236 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5239 case TGSI_OPCODE_ROUND
:
5240 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5243 case TGSI_OPCODE_EX2
:
5244 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5247 case TGSI_OPCODE_LG2
:
5248 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5251 case TGSI_OPCODE_POW
:
5252 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5255 case TGSI_OPCODE_XPD
:
5256 exec_xpd(mach
, inst
);
5259 case TGSI_OPCODE_ABS
:
5260 exec_vector_unary(mach
, inst
, micro_abs
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5263 case TGSI_OPCODE_DPH
:
5264 exec_dph(mach
, inst
);
5267 case TGSI_OPCODE_COS
:
5268 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5271 case TGSI_OPCODE_DDX
:
5272 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5275 case TGSI_OPCODE_DDY
:
5276 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5279 case TGSI_OPCODE_KILL
:
5280 exec_kill (mach
, inst
);
5283 case TGSI_OPCODE_KILL_IF
:
5284 exec_kill_if (mach
, inst
);
5287 case TGSI_OPCODE_PK2H
:
5288 exec_pk2h(mach
, inst
);
5291 case TGSI_OPCODE_PK2US
:
5295 case TGSI_OPCODE_PK4B
:
5299 case TGSI_OPCODE_PK4UB
:
5303 case TGSI_OPCODE_SEQ
:
5304 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5307 case TGSI_OPCODE_SGT
:
5308 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5311 case TGSI_OPCODE_SIN
:
5312 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5315 case TGSI_OPCODE_SLE
:
5316 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5319 case TGSI_OPCODE_SNE
:
5320 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5323 case TGSI_OPCODE_TEX
:
5324 /* simple texture lookup */
5325 /* src[0] = texcoord */
5326 /* src[1] = sampler unit */
5327 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
5330 case TGSI_OPCODE_TXB
:
5331 /* Texture lookup with lod bias */
5332 /* src[0] = texcoord (src[0].w = LOD bias) */
5333 /* src[1] = sampler unit */
5334 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
5337 case TGSI_OPCODE_TXD
:
5338 /* Texture lookup with explict partial derivatives */
5339 /* src[0] = texcoord */
5340 /* src[1] = d[strq]/dx */
5341 /* src[2] = d[strq]/dy */
5342 /* src[3] = sampler unit */
5343 exec_txd(mach
, inst
);
5346 case TGSI_OPCODE_TXL
:
5347 /* Texture lookup with explit LOD */
5348 /* src[0] = texcoord (src[0].w = LOD) */
5349 /* src[1] = sampler unit */
5350 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
5353 case TGSI_OPCODE_TXP
:
5354 /* Texture lookup with projection */
5355 /* src[0] = texcoord (src[0].w = projection) */
5356 /* src[1] = sampler unit */
5357 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
5360 case TGSI_OPCODE_TG4
:
5361 /* src[0] = texcoord */
5362 /* src[1] = component */
5363 /* src[2] = sampler unit */
5364 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
5367 case TGSI_OPCODE_LODQ
:
5368 /* src[0] = texcoord */
5369 /* src[1] = sampler unit */
5370 exec_lodq(mach
, inst
);
5373 case TGSI_OPCODE_UP2H
:
5374 exec_up2h(mach
, inst
);
5377 case TGSI_OPCODE_UP2US
:
5381 case TGSI_OPCODE_UP4B
:
5385 case TGSI_OPCODE_UP4UB
:
5389 case TGSI_OPCODE_ARR
:
5390 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5393 case TGSI_OPCODE_CAL
:
5394 /* skip the call if no execution channels are enabled */
5395 if (mach
->ExecMask
) {
5398 /* First, record the depths of the execution stacks.
5399 * This is important for deeply nested/looped return statements.
5400 * We have to unwind the stacks by the correct amount. For a
5401 * real code generator, we could determine the number of entries
5402 * to pop off each stack with simple static analysis and avoid
5403 * implementing this data structure at run time.
5405 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
5406 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
5407 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
5408 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
5409 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
5410 /* note that PC was already incremented above */
5411 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
5413 mach
->CallStackTop
++;
5415 /* Second, push the Cond, Loop, Cont, Func stacks */
5416 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5417 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5418 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5419 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
5420 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5421 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
5423 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5424 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5425 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5426 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
5427 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5428 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
5430 /* Finally, jump to the subroutine. The label is a pointer
5431 * (an instruction number) to the BGNSUB instruction.
5433 *pc
= inst
->Label
.Label
;
5434 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
5435 == TGSI_OPCODE_BGNSUB
);
5439 case TGSI_OPCODE_RET
:
5440 mach
->FuncMask
&= ~mach
->ExecMask
;
5441 UPDATE_EXEC_MASK(mach
);
5443 if (mach
->FuncMask
== 0x0) {
5444 /* really return now (otherwise, keep executing */
5446 if (mach
->CallStackTop
== 0) {
5447 /* returning from main() */
5448 mach
->CondStackTop
= 0;
5449 mach
->LoopStackTop
= 0;
5450 mach
->ContStackTop
= 0;
5451 mach
->LoopLabelStackTop
= 0;
5452 mach
->SwitchStackTop
= 0;
5453 mach
->BreakStackTop
= 0;
5458 assert(mach
->CallStackTop
> 0);
5459 mach
->CallStackTop
--;
5461 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5462 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5464 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5465 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5467 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5468 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5470 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5471 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5473 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5474 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5476 assert(mach
->FuncStackTop
> 0);
5477 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5479 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5481 UPDATE_EXEC_MASK(mach
);
5485 case TGSI_OPCODE_SSG
:
5486 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5489 case TGSI_OPCODE_CMP
:
5490 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5493 case TGSI_OPCODE_SCS
:
5494 exec_scs(mach
, inst
);
5497 case TGSI_OPCODE_DIV
:
5498 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5501 case TGSI_OPCODE_DP2
:
5502 exec_dp2(mach
, inst
);
5505 case TGSI_OPCODE_IF
:
5507 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5508 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5509 FETCH( &r
[0], 0, TGSI_CHAN_X
);
5510 /* update CondMask */
5512 mach
->CondMask
&= ~0x1;
5515 mach
->CondMask
&= ~0x2;
5518 mach
->CondMask
&= ~0x4;
5521 mach
->CondMask
&= ~0x8;
5523 UPDATE_EXEC_MASK(mach
);
5524 /* Todo: If CondMask==0, jump to ELSE */
5527 case TGSI_OPCODE_UIF
:
5529 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5530 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5531 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
5532 /* update CondMask */
5534 mach
->CondMask
&= ~0x1;
5537 mach
->CondMask
&= ~0x2;
5540 mach
->CondMask
&= ~0x4;
5543 mach
->CondMask
&= ~0x8;
5545 UPDATE_EXEC_MASK(mach
);
5546 /* Todo: If CondMask==0, jump to ELSE */
5549 case TGSI_OPCODE_ELSE
:
5550 /* invert CondMask wrt previous mask */
5553 assert(mach
->CondStackTop
> 0);
5554 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
5555 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
5556 UPDATE_EXEC_MASK(mach
);
5557 /* Todo: If CondMask==0, jump to ENDIF */
5561 case TGSI_OPCODE_ENDIF
:
5563 assert(mach
->CondStackTop
> 0);
5564 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
5565 UPDATE_EXEC_MASK(mach
);
5568 case TGSI_OPCODE_END
:
5569 /* make sure we end primitives which haven't
5570 * been explicitly emitted */
5571 conditional_emit_primitive(mach
);
5572 /* halt execution */
5576 case TGSI_OPCODE_PUSHA
:
5580 case TGSI_OPCODE_POPA
:
5584 case TGSI_OPCODE_CEIL
:
5585 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5588 case TGSI_OPCODE_I2F
:
5589 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
5592 case TGSI_OPCODE_NOT
:
5593 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5596 case TGSI_OPCODE_TRUNC
:
5597 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5600 case TGSI_OPCODE_SHL
:
5601 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5604 case TGSI_OPCODE_AND
:
5605 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5608 case TGSI_OPCODE_OR
:
5609 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5612 case TGSI_OPCODE_MOD
:
5613 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5616 case TGSI_OPCODE_XOR
:
5617 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5620 case TGSI_OPCODE_SAD
:
5624 case TGSI_OPCODE_TXF
:
5625 exec_txf(mach
, inst
);
5628 case TGSI_OPCODE_TXQ
:
5629 exec_txq(mach
, inst
);
5632 case TGSI_OPCODE_EMIT
:
5636 case TGSI_OPCODE_ENDPRIM
:
5637 emit_primitive(mach
);
5640 case TGSI_OPCODE_BGNLOOP
:
5641 /* push LoopMask and ContMasks */
5642 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5643 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5644 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5645 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5647 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5648 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5649 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
5650 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5651 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
5654 case TGSI_OPCODE_ENDLOOP
:
5655 /* Restore ContMask, but don't pop */
5656 assert(mach
->ContStackTop
> 0);
5657 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
5658 UPDATE_EXEC_MASK(mach
);
5659 if (mach
->ExecMask
) {
5660 /* repeat loop: jump to instruction just past BGNLOOP */
5661 assert(mach
->LoopLabelStackTop
> 0);
5662 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
5665 /* exit loop: pop LoopMask */
5666 assert(mach
->LoopStackTop
> 0);
5667 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
5669 assert(mach
->ContStackTop
> 0);
5670 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
5671 assert(mach
->LoopLabelStackTop
> 0);
5672 --mach
->LoopLabelStackTop
;
5674 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
5676 UPDATE_EXEC_MASK(mach
);
5679 case TGSI_OPCODE_BRK
:
5683 case TGSI_OPCODE_CONT
:
5684 /* turn off cont channels for each enabled exec channel */
5685 mach
->ContMask
&= ~mach
->ExecMask
;
5686 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5687 UPDATE_EXEC_MASK(mach
);
5690 case TGSI_OPCODE_BGNSUB
:
5694 case TGSI_OPCODE_ENDSUB
:
5696 * XXX: This really should be a no-op. We should never reach this opcode.
5699 assert(mach
->CallStackTop
> 0);
5700 mach
->CallStackTop
--;
5702 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5703 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5705 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5706 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5708 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5709 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5711 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5712 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5714 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5715 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5717 assert(mach
->FuncStackTop
> 0);
5718 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5720 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5722 UPDATE_EXEC_MASK(mach
);
5725 case TGSI_OPCODE_NOP
:
5728 case TGSI_OPCODE_BREAKC
:
5729 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
5730 /* update CondMask */
5731 if (r
[0].u
[0] && (mach
->ExecMask
& 0x1)) {
5732 mach
->LoopMask
&= ~0x1;
5734 if (r
[0].u
[1] && (mach
->ExecMask
& 0x2)) {
5735 mach
->LoopMask
&= ~0x2;
5737 if (r
[0].u
[2] && (mach
->ExecMask
& 0x4)) {
5738 mach
->LoopMask
&= ~0x4;
5740 if (r
[0].u
[3] && (mach
->ExecMask
& 0x8)) {
5741 mach
->LoopMask
&= ~0x8;
5743 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5744 UPDATE_EXEC_MASK(mach
);
5747 case TGSI_OPCODE_F2I
:
5748 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5751 case TGSI_OPCODE_FSEQ
:
5752 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5755 case TGSI_OPCODE_FSGE
:
5756 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5759 case TGSI_OPCODE_FSLT
:
5760 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5763 case TGSI_OPCODE_FSNE
:
5764 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5767 case TGSI_OPCODE_IDIV
:
5768 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5771 case TGSI_OPCODE_IMAX
:
5772 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5775 case TGSI_OPCODE_IMIN
:
5776 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5779 case TGSI_OPCODE_INEG
:
5780 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5783 case TGSI_OPCODE_ISGE
:
5784 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5787 case TGSI_OPCODE_ISHR
:
5788 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5791 case TGSI_OPCODE_ISLT
:
5792 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5795 case TGSI_OPCODE_F2U
:
5796 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5799 case TGSI_OPCODE_U2F
:
5800 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
5803 case TGSI_OPCODE_UADD
:
5804 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5807 case TGSI_OPCODE_UDIV
:
5808 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5811 case TGSI_OPCODE_UMAD
:
5812 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5815 case TGSI_OPCODE_UMAX
:
5816 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5819 case TGSI_OPCODE_UMIN
:
5820 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5823 case TGSI_OPCODE_UMOD
:
5824 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5827 case TGSI_OPCODE_UMUL
:
5828 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5831 case TGSI_OPCODE_IMUL_HI
:
5832 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5835 case TGSI_OPCODE_UMUL_HI
:
5836 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5839 case TGSI_OPCODE_USEQ
:
5840 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5843 case TGSI_OPCODE_USGE
:
5844 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5847 case TGSI_OPCODE_USHR
:
5848 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5851 case TGSI_OPCODE_USLT
:
5852 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5855 case TGSI_OPCODE_USNE
:
5856 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5859 case TGSI_OPCODE_SWITCH
:
5860 exec_switch(mach
, inst
);
5863 case TGSI_OPCODE_CASE
:
5864 exec_case(mach
, inst
);
5867 case TGSI_OPCODE_DEFAULT
:
5871 case TGSI_OPCODE_ENDSWITCH
:
5872 exec_endswitch(mach
);
5875 case TGSI_OPCODE_SAMPLE_I
:
5876 exec_txf(mach
, inst
);
5879 case TGSI_OPCODE_SAMPLE_I_MS
:
5880 exec_txf(mach
, inst
);
5883 case TGSI_OPCODE_SAMPLE
:
5884 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
5887 case TGSI_OPCODE_SAMPLE_B
:
5888 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
5891 case TGSI_OPCODE_SAMPLE_C
:
5892 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
5895 case TGSI_OPCODE_SAMPLE_C_LZ
:
5896 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
5899 case TGSI_OPCODE_SAMPLE_D
:
5900 exec_sample_d(mach
, inst
);
5903 case TGSI_OPCODE_SAMPLE_L
:
5904 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
5907 case TGSI_OPCODE_GATHER4
:
5911 case TGSI_OPCODE_SVIEWINFO
:
5912 exec_txq(mach
, inst
);
5915 case TGSI_OPCODE_SAMPLE_POS
:
5919 case TGSI_OPCODE_SAMPLE_INFO
:
5923 case TGSI_OPCODE_UARL
:
5924 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5927 case TGSI_OPCODE_UCMP
:
5928 exec_vector_trinary(mach
, inst
, micro_ucmp
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5931 case TGSI_OPCODE_IABS
:
5932 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5935 case TGSI_OPCODE_ISSG
:
5936 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5939 case TGSI_OPCODE_TEX2
:
5940 /* simple texture lookup */
5941 /* src[0] = texcoord */
5942 /* src[1] = compare */
5943 /* src[2] = sampler unit */
5944 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
5946 case TGSI_OPCODE_TXB2
:
5947 /* simple texture lookup */
5948 /* src[0] = texcoord */
5950 /* src[2] = sampler unit */
5951 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
5953 case TGSI_OPCODE_TXL2
:
5954 /* simple texture lookup */
5955 /* src[0] = texcoord */
5957 /* src[2] = sampler unit */
5958 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
5961 case TGSI_OPCODE_IBFE
:
5962 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5964 case TGSI_OPCODE_UBFE
:
5965 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5967 case TGSI_OPCODE_BFI
:
5968 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5970 case TGSI_OPCODE_BREV
:
5971 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5973 case TGSI_OPCODE_POPC
:
5974 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5976 case TGSI_OPCODE_LSB
:
5977 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5979 case TGSI_OPCODE_IMSB
:
5980 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5982 case TGSI_OPCODE_UMSB
:
5983 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5986 case TGSI_OPCODE_F2D
:
5987 exec_t_2_64(mach
, inst
, micro_f2d
, TGSI_EXEC_DATA_FLOAT
);
5990 case TGSI_OPCODE_D2F
:
5991 exec_64_2_t(mach
, inst
, micro_d2f
, TGSI_EXEC_DATA_FLOAT
);
5994 case TGSI_OPCODE_DABS
:
5995 exec_double_unary(mach
, inst
, micro_dabs
);
5998 case TGSI_OPCODE_DNEG
:
5999 exec_double_unary(mach
, inst
, micro_dneg
);
6002 case TGSI_OPCODE_DADD
:
6003 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
6006 case TGSI_OPCODE_DMUL
:
6007 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
6010 case TGSI_OPCODE_DMAX
:
6011 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
6014 case TGSI_OPCODE_DMIN
:
6015 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
6018 case TGSI_OPCODE_DSLT
:
6019 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
6022 case TGSI_OPCODE_DSGE
:
6023 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
6026 case TGSI_OPCODE_DSEQ
:
6027 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
6030 case TGSI_OPCODE_DSNE
:
6031 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
6034 case TGSI_OPCODE_DRCP
:
6035 exec_double_unary(mach
, inst
, micro_drcp
);
6038 case TGSI_OPCODE_DSQRT
:
6039 exec_double_unary(mach
, inst
, micro_dsqrt
);
6042 case TGSI_OPCODE_DRSQ
:
6043 exec_double_unary(mach
, inst
, micro_drsq
);
6046 case TGSI_OPCODE_DMAD
:
6047 exec_double_trinary(mach
, inst
, micro_dmad
);
6050 case TGSI_OPCODE_DFRAC
:
6051 exec_double_unary(mach
, inst
, micro_dfrac
);
6054 case TGSI_OPCODE_DLDEXP
:
6055 exec_dldexp(mach
, inst
);
6058 case TGSI_OPCODE_DFRACEXP
:
6059 exec_dfracexp(mach
, inst
);
6062 case TGSI_OPCODE_I2D
:
6063 exec_t_2_64(mach
, inst
, micro_i2d
, TGSI_EXEC_DATA_INT
);
6066 case TGSI_OPCODE_D2I
:
6067 exec_64_2_t(mach
, inst
, micro_d2i
, TGSI_EXEC_DATA_INT
);
6070 case TGSI_OPCODE_U2D
:
6071 exec_t_2_64(mach
, inst
, micro_u2d
, TGSI_EXEC_DATA_UINT
);
6074 case TGSI_OPCODE_D2U
:
6075 exec_64_2_t(mach
, inst
, micro_d2u
, TGSI_EXEC_DATA_INT
);
6078 case TGSI_OPCODE_LOAD
:
6079 exec_load(mach
, inst
);
6082 case TGSI_OPCODE_STORE
:
6083 exec_store(mach
, inst
);
6086 case TGSI_OPCODE_ATOMUADD
:
6087 case TGSI_OPCODE_ATOMXCHG
:
6088 case TGSI_OPCODE_ATOMCAS
:
6089 case TGSI_OPCODE_ATOMAND
:
6090 case TGSI_OPCODE_ATOMOR
:
6091 case TGSI_OPCODE_ATOMXOR
:
6092 case TGSI_OPCODE_ATOMUMIN
:
6093 case TGSI_OPCODE_ATOMUMAX
:
6094 case TGSI_OPCODE_ATOMIMIN
:
6095 case TGSI_OPCODE_ATOMIMAX
:
6096 exec_atomop(mach
, inst
);
6099 case TGSI_OPCODE_RESQ
:
6100 exec_resq(mach
, inst
);
6102 case TGSI_OPCODE_BARRIER
:
6103 case TGSI_OPCODE_MEMBAR
:
6107 case TGSI_OPCODE_I64ABS
:
6108 exec_double_unary(mach
, inst
, micro_i64abs
);
6111 case TGSI_OPCODE_I64SSG
:
6112 exec_double_unary(mach
, inst
, micro_i64sgn
);
6115 case TGSI_OPCODE_I64NEG
:
6116 exec_double_unary(mach
, inst
, micro_i64neg
);
6119 case TGSI_OPCODE_U64SEQ
:
6120 exec_double_binary(mach
, inst
, micro_u64seq
, TGSI_EXEC_DATA_UINT
);
6123 case TGSI_OPCODE_U64SNE
:
6124 exec_double_binary(mach
, inst
, micro_u64sne
, TGSI_EXEC_DATA_UINT
);
6127 case TGSI_OPCODE_I64SLT
:
6128 exec_double_binary(mach
, inst
, micro_i64slt
, TGSI_EXEC_DATA_UINT
);
6130 case TGSI_OPCODE_U64SLT
:
6131 exec_double_binary(mach
, inst
, micro_u64slt
, TGSI_EXEC_DATA_UINT
);
6134 case TGSI_OPCODE_I64SGE
:
6135 exec_double_binary(mach
, inst
, micro_i64sge
, TGSI_EXEC_DATA_UINT
);
6137 case TGSI_OPCODE_U64SGE
:
6138 exec_double_binary(mach
, inst
, micro_u64sge
, TGSI_EXEC_DATA_UINT
);
6141 case TGSI_OPCODE_I64MIN
:
6142 exec_double_binary(mach
, inst
, micro_i64min
, TGSI_EXEC_DATA_INT64
);
6144 case TGSI_OPCODE_U64MIN
:
6145 exec_double_binary(mach
, inst
, micro_u64min
, TGSI_EXEC_DATA_UINT64
);
6147 case TGSI_OPCODE_I64MAX
:
6148 exec_double_binary(mach
, inst
, micro_i64max
, TGSI_EXEC_DATA_INT64
);
6150 case TGSI_OPCODE_U64MAX
:
6151 exec_double_binary(mach
, inst
, micro_u64max
, TGSI_EXEC_DATA_UINT64
);
6153 case TGSI_OPCODE_U64ADD
:
6154 exec_double_binary(mach
, inst
, micro_u64add
, TGSI_EXEC_DATA_UINT64
);
6156 case TGSI_OPCODE_U64MUL
:
6157 exec_double_binary(mach
, inst
, micro_u64mul
, TGSI_EXEC_DATA_UINT64
);
6159 case TGSI_OPCODE_U64SHL
:
6160 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shl
);
6162 case TGSI_OPCODE_I64SHR
:
6163 exec_arg0_64_arg1_32(mach
, inst
, micro_i64shr
);
6165 case TGSI_OPCODE_U64SHR
:
6166 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shr
);
6168 case TGSI_OPCODE_U64DIV
:
6169 exec_double_binary(mach
, inst
, micro_u64div
, TGSI_EXEC_DATA_UINT64
);
6171 case TGSI_OPCODE_I64DIV
:
6172 exec_double_binary(mach
, inst
, micro_i64div
, TGSI_EXEC_DATA_INT64
);
6174 case TGSI_OPCODE_U64MOD
:
6175 exec_double_binary(mach
, inst
, micro_u64mod
, TGSI_EXEC_DATA_UINT64
);
6177 case TGSI_OPCODE_I64MOD
:
6178 exec_double_binary(mach
, inst
, micro_i64mod
, TGSI_EXEC_DATA_INT64
);
6181 case TGSI_OPCODE_F2U64
:
6182 exec_t_2_64(mach
, inst
, micro_f2u64
, TGSI_EXEC_DATA_FLOAT
);
6185 case TGSI_OPCODE_F2I64
:
6186 exec_t_2_64(mach
, inst
, micro_f2i64
, TGSI_EXEC_DATA_FLOAT
);
6189 case TGSI_OPCODE_U2I64
:
6190 exec_t_2_64(mach
, inst
, micro_u2i64
, TGSI_EXEC_DATA_INT
);
6192 case TGSI_OPCODE_I2I64
:
6193 exec_t_2_64(mach
, inst
, micro_i2i64
, TGSI_EXEC_DATA_INT
);
6196 case TGSI_OPCODE_D2U64
:
6197 exec_double_unary(mach
, inst
, micro_d2u64
);
6200 case TGSI_OPCODE_D2I64
:
6201 exec_double_unary(mach
, inst
, micro_d2i64
);
6204 case TGSI_OPCODE_U642F
:
6205 exec_64_2_t(mach
, inst
, micro_u642f
, TGSI_EXEC_DATA_FLOAT
);
6207 case TGSI_OPCODE_I642F
:
6208 exec_64_2_t(mach
, inst
, micro_i642f
, TGSI_EXEC_DATA_FLOAT
);
6211 case TGSI_OPCODE_U642D
:
6212 exec_double_unary(mach
, inst
, micro_u642d
);
6214 case TGSI_OPCODE_I642D
:
6215 exec_double_unary(mach
, inst
, micro_i642d
);
6225 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine
*mach
)
6227 uint default_mask
= 0xf;
6229 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
6230 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
6232 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
6233 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
6234 mach
->Primitives
[0] = 0;
6235 /* GS runs on a single primitive for now */
6239 if (mach
->NonHelperMask
== 0)
6240 mach
->NonHelperMask
= default_mask
;
6241 mach
->CondMask
= default_mask
;
6242 mach
->LoopMask
= default_mask
;
6243 mach
->ContMask
= default_mask
;
6244 mach
->FuncMask
= default_mask
;
6245 mach
->ExecMask
= default_mask
;
6247 mach
->Switch
.mask
= default_mask
;
6249 assert(mach
->CondStackTop
== 0);
6250 assert(mach
->LoopStackTop
== 0);
6251 assert(mach
->ContStackTop
== 0);
6252 assert(mach
->SwitchStackTop
== 0);
6253 assert(mach
->BreakStackTop
== 0);
6254 assert(mach
->CallStackTop
== 0);
6258 * Run TGSI interpreter.
6259 * \return bitmask of "alive" quad components
6262 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
, int start_pc
)
6266 mach
->pc
= start_pc
;
6269 tgsi_exec_machine_setup_masks(mach
);
6271 /* execute declarations (interpolants) */
6272 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
6273 exec_declaration( mach
, mach
->Declarations
+i
);
6279 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
6280 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
6284 memset(mach
->Temps
, 0, sizeof(temps
));
6286 memset(mach
->Outputs
, 0, sizeof(outputs
));
6287 memset(temps
, 0, sizeof(temps
));
6288 memset(outputs
, 0, sizeof(outputs
));
6292 /* execute instructions, until pc is set to -1 */
6293 while (mach
->pc
!= -1) {
6294 boolean barrier_hit
;
6298 tgsi_dump_instruction(&mach
->Instructions
[mach
->pc
], inst
++);
6301 assert(mach
->pc
< (int) mach
->NumInstructions
);
6302 barrier_hit
= exec_instruction(mach
, mach
->Instructions
+ mach
->pc
, &mach
->pc
);
6304 /* for compute shaders if we hit a barrier return now for later rescheduling */
6305 if (barrier_hit
&& mach
->ShaderType
== PIPE_SHADER_COMPUTE
)
6309 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
6310 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
6313 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
6314 debug_printf("TEMP[%2u] = ", i
);
6315 for (j
= 0; j
< 4; j
++) {
6319 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6320 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
6321 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
6322 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
6323 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
6327 if (mach
->Outputs
) {
6328 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
6329 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
6332 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
6333 debug_printf("OUT[%2u] = ", i
);
6334 for (j
= 0; j
< 4; j
++) {
6338 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6339 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
6340 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
6341 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
6342 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
6352 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
6353 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
6355 * Scale back depth component.
6357 for (i
= 0; i
< 4; i
++)
6358 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
6362 /* Strictly speaking, these assertions aren't really needed but they
6363 * can potentially catch some bugs in the control flow code.
6365 assert(mach
->CondStackTop
== 0);
6366 assert(mach
->LoopStackTop
== 0);
6367 assert(mach
->ContStackTop
== 0);
6368 assert(mach
->SwitchStackTop
== 0);
6369 assert(mach
->BreakStackTop
== 0);
6370 assert(mach
->CallStackTop
== 0);
6372 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];