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[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define DEBUG_EXECUTION 0
66
67
68 #define FAST_MATH 0
69
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
74
75 static void
76 micro_abs(union tgsi_exec_channel *dst,
77 const union tgsi_exec_channel *src)
78 {
79 dst->f[0] = fabsf(src->f[0]);
80 dst->f[1] = fabsf(src->f[1]);
81 dst->f[2] = fabsf(src->f[2]);
82 dst->f[3] = fabsf(src->f[3]);
83 }
84
85 static void
86 micro_arl(union tgsi_exec_channel *dst,
87 const union tgsi_exec_channel *src)
88 {
89 dst->i[0] = (int)floorf(src->f[0]);
90 dst->i[1] = (int)floorf(src->f[1]);
91 dst->i[2] = (int)floorf(src->f[2]);
92 dst->i[3] = (int)floorf(src->f[3]);
93 }
94
95 static void
96 micro_arr(union tgsi_exec_channel *dst,
97 const union tgsi_exec_channel *src)
98 {
99 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
100 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
101 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
102 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
103 }
104
105 static void
106 micro_ceil(union tgsi_exec_channel *dst,
107 const union tgsi_exec_channel *src)
108 {
109 dst->f[0] = ceilf(src->f[0]);
110 dst->f[1] = ceilf(src->f[1]);
111 dst->f[2] = ceilf(src->f[2]);
112 dst->f[3] = ceilf(src->f[3]);
113 }
114
115 static void
116 micro_clamp(union tgsi_exec_channel *dst,
117 const union tgsi_exec_channel *src0,
118 const union tgsi_exec_channel *src1,
119 const union tgsi_exec_channel *src2)
120 {
121 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
122 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
123 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
124 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
125 }
126
127 static void
128 micro_cmp(union tgsi_exec_channel *dst,
129 const union tgsi_exec_channel *src0,
130 const union tgsi_exec_channel *src1,
131 const union tgsi_exec_channel *src2)
132 {
133 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
134 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
135 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
136 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
137 }
138
139 static void
140 micro_cos(union tgsi_exec_channel *dst,
141 const union tgsi_exec_channel *src)
142 {
143 dst->f[0] = cosf(src->f[0]);
144 dst->f[1] = cosf(src->f[1]);
145 dst->f[2] = cosf(src->f[2]);
146 dst->f[3] = cosf(src->f[3]);
147 }
148
149 static void
150 micro_ddx(union tgsi_exec_channel *dst,
151 const union tgsi_exec_channel *src)
152 {
153 dst->f[0] =
154 dst->f[1] =
155 dst->f[2] =
156 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
157 }
158
159 static void
160 micro_ddy(union tgsi_exec_channel *dst,
161 const union tgsi_exec_channel *src)
162 {
163 dst->f[0] =
164 dst->f[1] =
165 dst->f[2] =
166 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
167 }
168
169 static void
170 micro_exp2(union tgsi_exec_channel *dst,
171 const union tgsi_exec_channel *src)
172 {
173 #if FAST_MATH
174 dst->f[0] = util_fast_exp2(src->f[0]);
175 dst->f[1] = util_fast_exp2(src->f[1]);
176 dst->f[2] = util_fast_exp2(src->f[2]);
177 dst->f[3] = util_fast_exp2(src->f[3]);
178 #else
179 #if DEBUG
180 /* Inf is okay for this instruction, so clamp it to silence assertions. */
181 uint i;
182 union tgsi_exec_channel clamped;
183
184 for (i = 0; i < 4; i++) {
185 if (src->f[i] > 127.99999f) {
186 clamped.f[i] = 127.99999f;
187 } else if (src->f[i] < -126.99999f) {
188 clamped.f[i] = -126.99999f;
189 } else {
190 clamped.f[i] = src->f[i];
191 }
192 }
193 src = &clamped;
194 #endif /* DEBUG */
195
196 dst->f[0] = powf(2.0f, src->f[0]);
197 dst->f[1] = powf(2.0f, src->f[1]);
198 dst->f[2] = powf(2.0f, src->f[2]);
199 dst->f[3] = powf(2.0f, src->f[3]);
200 #endif /* FAST_MATH */
201 }
202
203 static void
204 micro_flr(union tgsi_exec_channel *dst,
205 const union tgsi_exec_channel *src)
206 {
207 dst->f[0] = floorf(src->f[0]);
208 dst->f[1] = floorf(src->f[1]);
209 dst->f[2] = floorf(src->f[2]);
210 dst->f[3] = floorf(src->f[3]);
211 }
212
213 static void
214 micro_frc(union tgsi_exec_channel *dst,
215 const union tgsi_exec_channel *src)
216 {
217 dst->f[0] = src->f[0] - floorf(src->f[0]);
218 dst->f[1] = src->f[1] - floorf(src->f[1]);
219 dst->f[2] = src->f[2] - floorf(src->f[2]);
220 dst->f[3] = src->f[3] - floorf(src->f[3]);
221 }
222
223 static void
224 micro_iabs(union tgsi_exec_channel *dst,
225 const union tgsi_exec_channel *src)
226 {
227 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
228 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
229 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
230 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
231 }
232
233 static void
234 micro_ineg(union tgsi_exec_channel *dst,
235 const union tgsi_exec_channel *src)
236 {
237 dst->i[0] = -src->i[0];
238 dst->i[1] = -src->i[1];
239 dst->i[2] = -src->i[2];
240 dst->i[3] = -src->i[3];
241 }
242
243 static void
244 micro_lg2(union tgsi_exec_channel *dst,
245 const union tgsi_exec_channel *src)
246 {
247 #if FAST_MATH
248 dst->f[0] = util_fast_log2(src->f[0]);
249 dst->f[1] = util_fast_log2(src->f[1]);
250 dst->f[2] = util_fast_log2(src->f[2]);
251 dst->f[3] = util_fast_log2(src->f[3]);
252 #else
253 dst->f[0] = logf(src->f[0]) * 1.442695f;
254 dst->f[1] = logf(src->f[1]) * 1.442695f;
255 dst->f[2] = logf(src->f[2]) * 1.442695f;
256 dst->f[3] = logf(src->f[3]) * 1.442695f;
257 #endif
258 }
259
260 static void
261 micro_lrp(union tgsi_exec_channel *dst,
262 const union tgsi_exec_channel *src0,
263 const union tgsi_exec_channel *src1,
264 const union tgsi_exec_channel *src2)
265 {
266 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
267 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
268 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
269 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
270 }
271
272 static void
273 micro_mad(union tgsi_exec_channel *dst,
274 const union tgsi_exec_channel *src0,
275 const union tgsi_exec_channel *src1,
276 const union tgsi_exec_channel *src2)
277 {
278 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
279 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
280 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
281 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
282 }
283
284 static void
285 micro_mov(union tgsi_exec_channel *dst,
286 const union tgsi_exec_channel *src)
287 {
288 dst->u[0] = src->u[0];
289 dst->u[1] = src->u[1];
290 dst->u[2] = src->u[2];
291 dst->u[3] = src->u[3];
292 }
293
294 static void
295 micro_rcp(union tgsi_exec_channel *dst,
296 const union tgsi_exec_channel *src)
297 {
298 #if 0 /* for debugging */
299 assert(src->f[0] != 0.0f);
300 assert(src->f[1] != 0.0f);
301 assert(src->f[2] != 0.0f);
302 assert(src->f[3] != 0.0f);
303 #endif
304 dst->f[0] = 1.0f / src->f[0];
305 dst->f[1] = 1.0f / src->f[1];
306 dst->f[2] = 1.0f / src->f[2];
307 dst->f[3] = 1.0f / src->f[3];
308 }
309
310 static void
311 micro_rnd(union tgsi_exec_channel *dst,
312 const union tgsi_exec_channel *src)
313 {
314 dst->f[0] = floorf(src->f[0] + 0.5f);
315 dst->f[1] = floorf(src->f[1] + 0.5f);
316 dst->f[2] = floorf(src->f[2] + 0.5f);
317 dst->f[3] = floorf(src->f[3] + 0.5f);
318 }
319
320 static void
321 micro_rsq(union tgsi_exec_channel *dst,
322 const union tgsi_exec_channel *src)
323 {
324 #if 0 /* for debugging */
325 assert(src->f[0] != 0.0f);
326 assert(src->f[1] != 0.0f);
327 assert(src->f[2] != 0.0f);
328 assert(src->f[3] != 0.0f);
329 #endif
330 dst->f[0] = 1.0f / sqrtf(src->f[0]);
331 dst->f[1] = 1.0f / sqrtf(src->f[1]);
332 dst->f[2] = 1.0f / sqrtf(src->f[2]);
333 dst->f[3] = 1.0f / sqrtf(src->f[3]);
334 }
335
336 static void
337 micro_sqrt(union tgsi_exec_channel *dst,
338 const union tgsi_exec_channel *src)
339 {
340 dst->f[0] = sqrtf(src->f[0]);
341 dst->f[1] = sqrtf(src->f[1]);
342 dst->f[2] = sqrtf(src->f[2]);
343 dst->f[3] = sqrtf(src->f[3]);
344 }
345
346 static void
347 micro_seq(union tgsi_exec_channel *dst,
348 const union tgsi_exec_channel *src0,
349 const union tgsi_exec_channel *src1)
350 {
351 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
352 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
353 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
354 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
355 }
356
357 static void
358 micro_sge(union tgsi_exec_channel *dst,
359 const union tgsi_exec_channel *src0,
360 const union tgsi_exec_channel *src1)
361 {
362 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
363 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
364 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
365 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
366 }
367
368 static void
369 micro_sgn(union tgsi_exec_channel *dst,
370 const union tgsi_exec_channel *src)
371 {
372 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
373 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
374 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
375 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
376 }
377
378 static void
379 micro_isgn(union tgsi_exec_channel *dst,
380 const union tgsi_exec_channel *src)
381 {
382 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
383 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
384 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
385 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
386 }
387
388 static void
389 micro_sgt(union tgsi_exec_channel *dst,
390 const union tgsi_exec_channel *src0,
391 const union tgsi_exec_channel *src1)
392 {
393 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
394 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
395 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
396 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
397 }
398
399 static void
400 micro_sin(union tgsi_exec_channel *dst,
401 const union tgsi_exec_channel *src)
402 {
403 dst->f[0] = sinf(src->f[0]);
404 dst->f[1] = sinf(src->f[1]);
405 dst->f[2] = sinf(src->f[2]);
406 dst->f[3] = sinf(src->f[3]);
407 }
408
409 static void
410 micro_sle(union tgsi_exec_channel *dst,
411 const union tgsi_exec_channel *src0,
412 const union tgsi_exec_channel *src1)
413 {
414 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
415 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
416 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
417 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
418 }
419
420 static void
421 micro_slt(union tgsi_exec_channel *dst,
422 const union tgsi_exec_channel *src0,
423 const union tgsi_exec_channel *src1)
424 {
425 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
426 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
427 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
428 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
429 }
430
431 static void
432 micro_sne(union tgsi_exec_channel *dst,
433 const union tgsi_exec_channel *src0,
434 const union tgsi_exec_channel *src1)
435 {
436 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
437 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
438 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
439 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
440 }
441
442 static void
443 micro_trunc(union tgsi_exec_channel *dst,
444 const union tgsi_exec_channel *src)
445 {
446 dst->f[0] = (float)(int)src->f[0];
447 dst->f[1] = (float)(int)src->f[1];
448 dst->f[2] = (float)(int)src->f[2];
449 dst->f[3] = (float)(int)src->f[3];
450 }
451
452
453 enum tgsi_exec_datatype {
454 TGSI_EXEC_DATA_FLOAT,
455 TGSI_EXEC_DATA_INT,
456 TGSI_EXEC_DATA_UINT
457 };
458
459 /*
460 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
461 */
462 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
463 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
464 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
465 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
466 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
467 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
468
469
470 /** The execution mask depends on the conditional mask and the loop mask */
471 #define UPDATE_EXEC_MASK(MACH) \
472 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
473
474
475 static const union tgsi_exec_channel ZeroVec =
476 { { 0.0, 0.0, 0.0, 0.0 } };
477
478 static const union tgsi_exec_channel OneVec = {
479 {1.0f, 1.0f, 1.0f, 1.0f}
480 };
481
482 static const union tgsi_exec_channel P128Vec = {
483 {128.0f, 128.0f, 128.0f, 128.0f}
484 };
485
486 static const union tgsi_exec_channel M128Vec = {
487 {-128.0f, -128.0f, -128.0f, -128.0f}
488 };
489
490
491 /**
492 * Assert that none of the float values in 'chan' are infinite or NaN.
493 * NaN and Inf may occur normally during program execution and should
494 * not lead to crashes, etc. But when debugging, it's helpful to catch
495 * them.
496 */
497 static INLINE void
498 check_inf_or_nan(const union tgsi_exec_channel *chan)
499 {
500 assert(!util_is_inf_or_nan((chan)->f[0]));
501 assert(!util_is_inf_or_nan((chan)->f[1]));
502 assert(!util_is_inf_or_nan((chan)->f[2]));
503 assert(!util_is_inf_or_nan((chan)->f[3]));
504 }
505
506
507 #ifdef DEBUG
508 static void
509 print_chan(const char *msg, const union tgsi_exec_channel *chan)
510 {
511 debug_printf("%s = {%f, %f, %f, %f}\n",
512 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
513 }
514 #endif
515
516
517 #ifdef DEBUG
518 static void
519 print_temp(const struct tgsi_exec_machine *mach, uint index)
520 {
521 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
522 int i;
523 debug_printf("Temp[%u] =\n", index);
524 for (i = 0; i < 4; i++) {
525 debug_printf(" %c: { %f, %f, %f, %f }\n",
526 "XYZW"[i],
527 tmp->xyzw[i].f[0],
528 tmp->xyzw[i].f[1],
529 tmp->xyzw[i].f[2],
530 tmp->xyzw[i].f[3]);
531 }
532 }
533 #endif
534
535
536 void
537 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
538 unsigned num_bufs,
539 const void **bufs,
540 const unsigned *buf_sizes)
541 {
542 unsigned i;
543
544 for (i = 0; i < num_bufs; i++) {
545 mach->Consts[i] = bufs[i];
546 mach->ConstsSize[i] = buf_sizes[i];
547 }
548 }
549
550
551 /**
552 * Check if there's a potential src/dst register data dependency when
553 * using SOA execution.
554 * Example:
555 * MOV T, T.yxwz;
556 * This would expand into:
557 * MOV t0, t1;
558 * MOV t1, t0;
559 * MOV t2, t3;
560 * MOV t3, t2;
561 * The second instruction will have the wrong value for t0 if executed as-is.
562 */
563 boolean
564 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
565 {
566 uint i, chan;
567
568 uint writemask = inst->Dst[0].Register.WriteMask;
569 if (writemask == TGSI_WRITEMASK_X ||
570 writemask == TGSI_WRITEMASK_Y ||
571 writemask == TGSI_WRITEMASK_Z ||
572 writemask == TGSI_WRITEMASK_W ||
573 writemask == TGSI_WRITEMASK_NONE) {
574 /* no chance of data dependency */
575 return FALSE;
576 }
577
578 /* loop over src regs */
579 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
580 if ((inst->Src[i].Register.File ==
581 inst->Dst[0].Register.File) &&
582 ((inst->Src[i].Register.Index ==
583 inst->Dst[0].Register.Index) ||
584 inst->Src[i].Register.Indirect ||
585 inst->Dst[0].Register.Indirect)) {
586 /* loop over dest channels */
587 uint channelsWritten = 0x0;
588 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
589 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
590 /* check if we're reading a channel that's been written */
591 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
592 if (channelsWritten & (1 << swizzle)) {
593 return TRUE;
594 }
595
596 channelsWritten |= (1 << chan);
597 }
598 }
599 }
600 }
601 return FALSE;
602 }
603
604
605 /**
606 * Initialize machine state by expanding tokens to full instructions,
607 * allocating temporary storage, setting up constants, etc.
608 * After this, we can call tgsi_exec_machine_run() many times.
609 */
610 void
611 tgsi_exec_machine_bind_shader(
612 struct tgsi_exec_machine *mach,
613 const struct tgsi_token *tokens,
614 struct tgsi_sampler *sampler)
615 {
616 uint k;
617 struct tgsi_parse_context parse;
618 struct tgsi_full_instruction *instructions;
619 struct tgsi_full_declaration *declarations;
620 uint maxInstructions = 10, numInstructions = 0;
621 uint maxDeclarations = 10, numDeclarations = 0;
622
623 #if 0
624 tgsi_dump(tokens, 0);
625 #endif
626
627 util_init_math();
628
629
630 mach->Tokens = tokens;
631 mach->Sampler = sampler;
632
633 if (!tokens) {
634 /* unbind and free all */
635 FREE(mach->Declarations);
636 mach->Declarations = NULL;
637 mach->NumDeclarations = 0;
638
639 FREE(mach->Instructions);
640 mach->Instructions = NULL;
641 mach->NumInstructions = 0;
642
643 return;
644 }
645
646 k = tgsi_parse_init (&parse, mach->Tokens);
647 if (k != TGSI_PARSE_OK) {
648 debug_printf( "Problem parsing!\n" );
649 return;
650 }
651
652 mach->Processor = parse.FullHeader.Processor.Processor;
653 mach->ImmLimit = 0;
654 mach->NumOutputs = 0;
655
656 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
657 !mach->UsedGeometryShader) {
658 struct tgsi_exec_vector *inputs;
659 struct tgsi_exec_vector *outputs;
660
661 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
662 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
663 16);
664
665 if (!inputs)
666 return;
667
668 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
669 TGSI_MAX_TOTAL_VERTICES, 16);
670
671 if (!outputs) {
672 align_free(inputs);
673 return;
674 }
675
676 align_free(mach->Inputs);
677 align_free(mach->Outputs);
678
679 mach->Inputs = inputs;
680 mach->Outputs = outputs;
681 mach->UsedGeometryShader = TRUE;
682 }
683
684 declarations = (struct tgsi_full_declaration *)
685 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
686
687 if (!declarations) {
688 return;
689 }
690
691 instructions = (struct tgsi_full_instruction *)
692 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
693
694 if (!instructions) {
695 FREE( declarations );
696 return;
697 }
698
699 while( !tgsi_parse_end_of_tokens( &parse ) ) {
700 uint i;
701
702 tgsi_parse_token( &parse );
703 switch( parse.FullToken.Token.Type ) {
704 case TGSI_TOKEN_TYPE_DECLARATION:
705 /* save expanded declaration */
706 if (numDeclarations == maxDeclarations) {
707 declarations = REALLOC(declarations,
708 maxDeclarations
709 * sizeof(struct tgsi_full_declaration),
710 (maxDeclarations + 10)
711 * sizeof(struct tgsi_full_declaration));
712 maxDeclarations += 10;
713 }
714 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
715 unsigned reg;
716 for (reg = parse.FullToken.FullDeclaration.Range.First;
717 reg <= parse.FullToken.FullDeclaration.Range.Last;
718 ++reg) {
719 ++mach->NumOutputs;
720 }
721 }
722 memcpy(declarations + numDeclarations,
723 &parse.FullToken.FullDeclaration,
724 sizeof(declarations[0]));
725 numDeclarations++;
726 break;
727
728 case TGSI_TOKEN_TYPE_IMMEDIATE:
729 {
730 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
731 assert( size <= 4 );
732 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
733
734 for( i = 0; i < size; i++ ) {
735 mach->Imms[mach->ImmLimit][i] =
736 parse.FullToken.FullImmediate.u[i].Float;
737 }
738 mach->ImmLimit += 1;
739 }
740 break;
741
742 case TGSI_TOKEN_TYPE_INSTRUCTION:
743
744 /* save expanded instruction */
745 if (numInstructions == maxInstructions) {
746 instructions = REALLOC(instructions,
747 maxInstructions
748 * sizeof(struct tgsi_full_instruction),
749 (maxInstructions + 10)
750 * sizeof(struct tgsi_full_instruction));
751 maxInstructions += 10;
752 }
753
754 memcpy(instructions + numInstructions,
755 &parse.FullToken.FullInstruction,
756 sizeof(instructions[0]));
757
758 numInstructions++;
759 break;
760
761 case TGSI_TOKEN_TYPE_PROPERTY:
762 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY) {
763 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
764 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
765 }
766 }
767 break;
768
769 default:
770 assert( 0 );
771 }
772 }
773 tgsi_parse_free (&parse);
774
775 FREE(mach->Declarations);
776 mach->Declarations = declarations;
777 mach->NumDeclarations = numDeclarations;
778
779 FREE(mach->Instructions);
780 mach->Instructions = instructions;
781 mach->NumInstructions = numInstructions;
782 }
783
784
785 struct tgsi_exec_machine *
786 tgsi_exec_machine_create( void )
787 {
788 struct tgsi_exec_machine *mach;
789 uint i;
790
791 mach = align_malloc( sizeof *mach, 16 );
792 if (!mach)
793 goto fail;
794
795 memset(mach, 0, sizeof(*mach));
796
797 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
798 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
799 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
800
801 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
802 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
803 if (!mach->Inputs || !mach->Outputs)
804 goto fail;
805
806 /* Setup constants needed by the SSE2 executor. */
807 for( i = 0; i < 4; i++ ) {
808 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
809 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
810 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
811 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
812 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
813 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
814 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
815 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
816 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
817 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
818 }
819
820 #ifdef DEBUG
821 /* silence warnings */
822 (void) print_chan;
823 (void) print_temp;
824 #endif
825
826 return mach;
827
828 fail:
829 if (mach) {
830 align_free(mach->Inputs);
831 align_free(mach->Outputs);
832 align_free(mach);
833 }
834 return NULL;
835 }
836
837
838 void
839 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
840 {
841 if (mach) {
842 FREE(mach->Instructions);
843 FREE(mach->Declarations);
844
845 align_free(mach->Inputs);
846 align_free(mach->Outputs);
847
848 align_free(mach);
849 }
850 }
851
852 static void
853 micro_add(union tgsi_exec_channel *dst,
854 const union tgsi_exec_channel *src0,
855 const union tgsi_exec_channel *src1)
856 {
857 dst->f[0] = src0->f[0] + src1->f[0];
858 dst->f[1] = src0->f[1] + src1->f[1];
859 dst->f[2] = src0->f[2] + src1->f[2];
860 dst->f[3] = src0->f[3] + src1->f[3];
861 }
862
863 static void
864 micro_div(
865 union tgsi_exec_channel *dst,
866 const union tgsi_exec_channel *src0,
867 const union tgsi_exec_channel *src1 )
868 {
869 if (src1->f[0] != 0) {
870 dst->f[0] = src0->f[0] / src1->f[0];
871 }
872 if (src1->f[1] != 0) {
873 dst->f[1] = src0->f[1] / src1->f[1];
874 }
875 if (src1->f[2] != 0) {
876 dst->f[2] = src0->f[2] / src1->f[2];
877 }
878 if (src1->f[3] != 0) {
879 dst->f[3] = src0->f[3] / src1->f[3];
880 }
881 }
882
883 static void
884 micro_lt(
885 union tgsi_exec_channel *dst,
886 const union tgsi_exec_channel *src0,
887 const union tgsi_exec_channel *src1,
888 const union tgsi_exec_channel *src2,
889 const union tgsi_exec_channel *src3 )
890 {
891 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
892 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
893 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
894 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
895 }
896
897 static void
898 micro_max(union tgsi_exec_channel *dst,
899 const union tgsi_exec_channel *src0,
900 const union tgsi_exec_channel *src1)
901 {
902 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
903 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
904 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
905 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
906 }
907
908 static void
909 micro_min(union tgsi_exec_channel *dst,
910 const union tgsi_exec_channel *src0,
911 const union tgsi_exec_channel *src1)
912 {
913 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
914 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
915 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
916 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
917 }
918
919 static void
920 micro_mul(union tgsi_exec_channel *dst,
921 const union tgsi_exec_channel *src0,
922 const union tgsi_exec_channel *src1)
923 {
924 dst->f[0] = src0->f[0] * src1->f[0];
925 dst->f[1] = src0->f[1] * src1->f[1];
926 dst->f[2] = src0->f[2] * src1->f[2];
927 dst->f[3] = src0->f[3] * src1->f[3];
928 }
929
930 static void
931 micro_neg(
932 union tgsi_exec_channel *dst,
933 const union tgsi_exec_channel *src )
934 {
935 dst->f[0] = -src->f[0];
936 dst->f[1] = -src->f[1];
937 dst->f[2] = -src->f[2];
938 dst->f[3] = -src->f[3];
939 }
940
941 static void
942 micro_pow(
943 union tgsi_exec_channel *dst,
944 const union tgsi_exec_channel *src0,
945 const union tgsi_exec_channel *src1 )
946 {
947 #if FAST_MATH
948 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
949 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
950 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
951 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
952 #else
953 dst->f[0] = powf( src0->f[0], src1->f[0] );
954 dst->f[1] = powf( src0->f[1], src1->f[1] );
955 dst->f[2] = powf( src0->f[2], src1->f[2] );
956 dst->f[3] = powf( src0->f[3], src1->f[3] );
957 #endif
958 }
959
960 static void
961 micro_sub(union tgsi_exec_channel *dst,
962 const union tgsi_exec_channel *src0,
963 const union tgsi_exec_channel *src1)
964 {
965 dst->f[0] = src0->f[0] - src1->f[0];
966 dst->f[1] = src0->f[1] - src1->f[1];
967 dst->f[2] = src0->f[2] - src1->f[2];
968 dst->f[3] = src0->f[3] - src1->f[3];
969 }
970
971 static void
972 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
973 const uint chan_index,
974 const uint file,
975 const uint swizzle,
976 const union tgsi_exec_channel *index,
977 const union tgsi_exec_channel *index2D,
978 union tgsi_exec_channel *chan)
979 {
980 uint i;
981
982 assert(swizzle < 4);
983
984 switch (file) {
985 case TGSI_FILE_CONSTANT:
986 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
987 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
988 assert(mach->Consts[index2D->i[i]]);
989
990 if (index->i[i] < 0) {
991 chan->u[i] = 0;
992 } else {
993 /* NOTE: copying the const value as a uint instead of float */
994 const uint constbuf = index2D->i[i];
995 const uint *buf = (const uint *)mach->Consts[constbuf];
996 const int pos = index->i[i] * 4 + swizzle;
997 /* const buffer bounds check */
998 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
999 if (0) {
1000 /* Debug: print warning */
1001 static int count = 0;
1002 if (count++ < 100)
1003 debug_printf("TGSI Exec: const buffer index %d"
1004 " out of bounds\n", pos);
1005 }
1006 chan->u[i] = 0;
1007 }
1008 else
1009 chan->u[i] = buf[pos];
1010 }
1011 }
1012 break;
1013
1014 case TGSI_FILE_INPUT:
1015 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1016 /*
1017 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1018 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1019 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1020 index2D->i[i], index->i[i]);
1021 }*/
1022 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1023 assert(pos >= 0);
1024 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1025 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1026 }
1027 break;
1028
1029 case TGSI_FILE_SYSTEM_VALUE:
1030 /* XXX no swizzling at this point. Will be needed if we put
1031 * gl_FragCoord, for example, in a sys value register.
1032 */
1033 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1034 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1035 }
1036 break;
1037
1038 case TGSI_FILE_TEMPORARY:
1039 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1040 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1041 assert(index2D->i[i] == 0);
1042
1043 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1044 }
1045 break;
1046
1047 case TGSI_FILE_IMMEDIATE:
1048 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1049 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1050 assert(index2D->i[i] == 0);
1051
1052 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1053 }
1054 break;
1055
1056 case TGSI_FILE_ADDRESS:
1057 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1058 assert(index->i[i] >= 0);
1059 assert(index2D->i[i] == 0);
1060
1061 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1062 }
1063 break;
1064
1065 case TGSI_FILE_PREDICATE:
1066 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1067 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1068 assert(index2D->i[i] == 0);
1069
1070 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1071 }
1072 break;
1073
1074 case TGSI_FILE_OUTPUT:
1075 /* vertex/fragment output vars can be read too */
1076 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1077 assert(index->i[i] >= 0);
1078 assert(index2D->i[i] == 0);
1079
1080 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1081 }
1082 break;
1083
1084 default:
1085 assert(0);
1086 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1087 chan->u[i] = 0;
1088 }
1089 }
1090 }
1091
1092 static void
1093 fetch_source(const struct tgsi_exec_machine *mach,
1094 union tgsi_exec_channel *chan,
1095 const struct tgsi_full_src_register *reg,
1096 const uint chan_index,
1097 enum tgsi_exec_datatype src_datatype)
1098 {
1099 union tgsi_exec_channel index;
1100 union tgsi_exec_channel index2D;
1101 uint swizzle;
1102
1103 /* We start with a direct index into a register file.
1104 *
1105 * file[1],
1106 * where:
1107 * file = Register.File
1108 * [1] = Register.Index
1109 */
1110 index.i[0] =
1111 index.i[1] =
1112 index.i[2] =
1113 index.i[3] = reg->Register.Index;
1114
1115 /* There is an extra source register that indirectly subscripts
1116 * a register file. The direct index now becomes an offset
1117 * that is being added to the indirect register.
1118 *
1119 * file[ind[2].x+1],
1120 * where:
1121 * ind = Indirect.File
1122 * [2] = Indirect.Index
1123 * .x = Indirect.SwizzleX
1124 */
1125 if (reg->Register.Indirect) {
1126 union tgsi_exec_channel index2;
1127 union tgsi_exec_channel indir_index;
1128 const uint execmask = mach->ExecMask;
1129 uint i;
1130
1131 /* which address register (always zero now) */
1132 index2.i[0] =
1133 index2.i[1] =
1134 index2.i[2] =
1135 index2.i[3] = reg->Indirect.Index;
1136 /* get current value of address register[swizzle] */
1137 swizzle = reg->Indirect.Swizzle;
1138 fetch_src_file_channel(mach,
1139 chan_index,
1140 reg->Indirect.File,
1141 swizzle,
1142 &index2,
1143 &ZeroVec,
1144 &indir_index);
1145
1146 /* add value of address register to the offset */
1147 index.i[0] += indir_index.i[0];
1148 index.i[1] += indir_index.i[1];
1149 index.i[2] += indir_index.i[2];
1150 index.i[3] += indir_index.i[3];
1151
1152 /* for disabled execution channels, zero-out the index to
1153 * avoid using a potential garbage value.
1154 */
1155 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1156 if ((execmask & (1 << i)) == 0)
1157 index.i[i] = 0;
1158 }
1159 }
1160
1161 /* There is an extra source register that is a second
1162 * subscript to a register file. Effectively it means that
1163 * the register file is actually a 2D array of registers.
1164 *
1165 * file[3][1],
1166 * where:
1167 * [3] = Dimension.Index
1168 */
1169 if (reg->Register.Dimension) {
1170 index2D.i[0] =
1171 index2D.i[1] =
1172 index2D.i[2] =
1173 index2D.i[3] = reg->Dimension.Index;
1174
1175 /* Again, the second subscript index can be addressed indirectly
1176 * identically to the first one.
1177 * Nothing stops us from indirectly addressing the indirect register,
1178 * but there is no need for that, so we won't exercise it.
1179 *
1180 * file[ind[4].y+3][1],
1181 * where:
1182 * ind = DimIndirect.File
1183 * [4] = DimIndirect.Index
1184 * .y = DimIndirect.SwizzleX
1185 */
1186 if (reg->Dimension.Indirect) {
1187 union tgsi_exec_channel index2;
1188 union tgsi_exec_channel indir_index;
1189 const uint execmask = mach->ExecMask;
1190 uint i;
1191
1192 index2.i[0] =
1193 index2.i[1] =
1194 index2.i[2] =
1195 index2.i[3] = reg->DimIndirect.Index;
1196
1197 swizzle = reg->DimIndirect.Swizzle;
1198 fetch_src_file_channel(mach,
1199 chan_index,
1200 reg->DimIndirect.File,
1201 swizzle,
1202 &index2,
1203 &ZeroVec,
1204 &indir_index);
1205
1206 index2D.i[0] += indir_index.i[0];
1207 index2D.i[1] += indir_index.i[1];
1208 index2D.i[2] += indir_index.i[2];
1209 index2D.i[3] += indir_index.i[3];
1210
1211 /* for disabled execution channels, zero-out the index to
1212 * avoid using a potential garbage value.
1213 */
1214 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1215 if ((execmask & (1 << i)) == 0) {
1216 index2D.i[i] = 0;
1217 }
1218 }
1219 }
1220
1221 /* If by any chance there was a need for a 3D array of register
1222 * files, we would have to check whether Dimension is followed
1223 * by a dimension register and continue the saga.
1224 */
1225 } else {
1226 index2D.i[0] =
1227 index2D.i[1] =
1228 index2D.i[2] =
1229 index2D.i[3] = 0;
1230 }
1231
1232 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1233 fetch_src_file_channel(mach,
1234 chan_index,
1235 reg->Register.File,
1236 swizzle,
1237 &index,
1238 &index2D,
1239 chan);
1240
1241 if (reg->Register.Absolute) {
1242 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1243 micro_abs(chan, chan);
1244 } else {
1245 micro_iabs(chan, chan);
1246 }
1247 }
1248
1249 if (reg->Register.Negate) {
1250 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1251 micro_neg(chan, chan);
1252 } else {
1253 micro_ineg(chan, chan);
1254 }
1255 }
1256 }
1257
1258 static void
1259 store_dest(struct tgsi_exec_machine *mach,
1260 const union tgsi_exec_channel *chan,
1261 const struct tgsi_full_dst_register *reg,
1262 const struct tgsi_full_instruction *inst,
1263 uint chan_index,
1264 enum tgsi_exec_datatype dst_datatype)
1265 {
1266 uint i;
1267 union tgsi_exec_channel null;
1268 union tgsi_exec_channel *dst;
1269 union tgsi_exec_channel index2D;
1270 uint execmask = mach->ExecMask;
1271 int offset = 0; /* indirection offset */
1272 int index;
1273
1274 /* for debugging */
1275 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1276 check_inf_or_nan(chan);
1277 }
1278
1279 /* There is an extra source register that indirectly subscripts
1280 * a register file. The direct index now becomes an offset
1281 * that is being added to the indirect register.
1282 *
1283 * file[ind[2].x+1],
1284 * where:
1285 * ind = Indirect.File
1286 * [2] = Indirect.Index
1287 * .x = Indirect.SwizzleX
1288 */
1289 if (reg->Register.Indirect) {
1290 union tgsi_exec_channel index;
1291 union tgsi_exec_channel indir_index;
1292 uint swizzle;
1293
1294 /* which address register (always zero for now) */
1295 index.i[0] =
1296 index.i[1] =
1297 index.i[2] =
1298 index.i[3] = reg->Indirect.Index;
1299
1300 /* get current value of address register[swizzle] */
1301 swizzle = reg->Indirect.Swizzle;
1302
1303 /* fetch values from the address/indirection register */
1304 fetch_src_file_channel(mach,
1305 chan_index,
1306 reg->Indirect.File,
1307 swizzle,
1308 &index,
1309 &ZeroVec,
1310 &indir_index);
1311
1312 /* save indirection offset */
1313 offset = indir_index.i[0];
1314 }
1315
1316 /* There is an extra source register that is a second
1317 * subscript to a register file. Effectively it means that
1318 * the register file is actually a 2D array of registers.
1319 *
1320 * file[3][1],
1321 * where:
1322 * [3] = Dimension.Index
1323 */
1324 if (reg->Register.Dimension) {
1325 index2D.i[0] =
1326 index2D.i[1] =
1327 index2D.i[2] =
1328 index2D.i[3] = reg->Dimension.Index;
1329
1330 /* Again, the second subscript index can be addressed indirectly
1331 * identically to the first one.
1332 * Nothing stops us from indirectly addressing the indirect register,
1333 * but there is no need for that, so we won't exercise it.
1334 *
1335 * file[ind[4].y+3][1],
1336 * where:
1337 * ind = DimIndirect.File
1338 * [4] = DimIndirect.Index
1339 * .y = DimIndirect.SwizzleX
1340 */
1341 if (reg->Dimension.Indirect) {
1342 union tgsi_exec_channel index2;
1343 union tgsi_exec_channel indir_index;
1344 const uint execmask = mach->ExecMask;
1345 unsigned swizzle;
1346 uint i;
1347
1348 index2.i[0] =
1349 index2.i[1] =
1350 index2.i[2] =
1351 index2.i[3] = reg->DimIndirect.Index;
1352
1353 swizzle = reg->DimIndirect.Swizzle;
1354 fetch_src_file_channel(mach,
1355 chan_index,
1356 reg->DimIndirect.File,
1357 swizzle,
1358 &index2,
1359 &ZeroVec,
1360 &indir_index);
1361
1362 index2D.i[0] += indir_index.i[0];
1363 index2D.i[1] += indir_index.i[1];
1364 index2D.i[2] += indir_index.i[2];
1365 index2D.i[3] += indir_index.i[3];
1366
1367 /* for disabled execution channels, zero-out the index to
1368 * avoid using a potential garbage value.
1369 */
1370 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1371 if ((execmask & (1 << i)) == 0) {
1372 index2D.i[i] = 0;
1373 }
1374 }
1375 }
1376
1377 /* If by any chance there was a need for a 3D array of register
1378 * files, we would have to check whether Dimension is followed
1379 * by a dimension register and continue the saga.
1380 */
1381 } else {
1382 index2D.i[0] =
1383 index2D.i[1] =
1384 index2D.i[2] =
1385 index2D.i[3] = 0;
1386 }
1387
1388 switch (reg->Register.File) {
1389 case TGSI_FILE_NULL:
1390 dst = &null;
1391 break;
1392
1393 case TGSI_FILE_OUTPUT:
1394 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1395 + reg->Register.Index;
1396 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1397 #if 0
1398 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1399 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1400 reg->Register.Index);
1401 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1402 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1403 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1404 if (execmask & (1 << i))
1405 debug_printf("%f, ", chan->f[i]);
1406 debug_printf(")\n");
1407 }
1408 #endif
1409 break;
1410
1411 case TGSI_FILE_TEMPORARY:
1412 index = reg->Register.Index;
1413 assert( index < TGSI_EXEC_NUM_TEMPS );
1414 dst = &mach->Temps[offset + index].xyzw[chan_index];
1415 break;
1416
1417 case TGSI_FILE_ADDRESS:
1418 index = reg->Register.Index;
1419 dst = &mach->Addrs[index].xyzw[chan_index];
1420 break;
1421
1422 case TGSI_FILE_PREDICATE:
1423 index = reg->Register.Index;
1424 assert(index < TGSI_EXEC_NUM_PREDS);
1425 dst = &mach->Predicates[index].xyzw[chan_index];
1426 break;
1427
1428 default:
1429 assert( 0 );
1430 return;
1431 }
1432
1433 if (inst->Instruction.Predicate) {
1434 uint swizzle;
1435 union tgsi_exec_channel *pred;
1436
1437 switch (chan_index) {
1438 case TGSI_CHAN_X:
1439 swizzle = inst->Predicate.SwizzleX;
1440 break;
1441 case TGSI_CHAN_Y:
1442 swizzle = inst->Predicate.SwizzleY;
1443 break;
1444 case TGSI_CHAN_Z:
1445 swizzle = inst->Predicate.SwizzleZ;
1446 break;
1447 case TGSI_CHAN_W:
1448 swizzle = inst->Predicate.SwizzleW;
1449 break;
1450 default:
1451 assert(0);
1452 return;
1453 }
1454
1455 assert(inst->Predicate.Index == 0);
1456
1457 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1458
1459 if (inst->Predicate.Negate) {
1460 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1461 if (pred->u[i]) {
1462 execmask &= ~(1 << i);
1463 }
1464 }
1465 } else {
1466 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1467 if (!pred->u[i]) {
1468 execmask &= ~(1 << i);
1469 }
1470 }
1471 }
1472 }
1473
1474 switch (inst->Instruction.Saturate) {
1475 case TGSI_SAT_NONE:
1476 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1477 if (execmask & (1 << i))
1478 dst->i[i] = chan->i[i];
1479 break;
1480
1481 case TGSI_SAT_ZERO_ONE:
1482 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1483 if (execmask & (1 << i)) {
1484 if (chan->f[i] < 0.0f)
1485 dst->f[i] = 0.0f;
1486 else if (chan->f[i] > 1.0f)
1487 dst->f[i] = 1.0f;
1488 else
1489 dst->i[i] = chan->i[i];
1490 }
1491 break;
1492
1493 case TGSI_SAT_MINUS_PLUS_ONE:
1494 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1495 if (execmask & (1 << i)) {
1496 if (chan->f[i] < -1.0f)
1497 dst->f[i] = -1.0f;
1498 else if (chan->f[i] > 1.0f)
1499 dst->f[i] = 1.0f;
1500 else
1501 dst->i[i] = chan->i[i];
1502 }
1503 break;
1504
1505 default:
1506 assert( 0 );
1507 }
1508 }
1509
1510 #define FETCH(VAL,INDEX,CHAN)\
1511 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1512
1513 #define IFETCH(VAL,INDEX,CHAN)\
1514 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1515
1516
1517 /**
1518 * Execute ARB-style KIL which is predicated by a src register.
1519 * Kill fragment if any of the four values is less than zero.
1520 */
1521 static void
1522 exec_kill_if(struct tgsi_exec_machine *mach,
1523 const struct tgsi_full_instruction *inst)
1524 {
1525 uint uniquemask;
1526 uint chan_index;
1527 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1528 union tgsi_exec_channel r[1];
1529
1530 /* This mask stores component bits that were already tested. */
1531 uniquemask = 0;
1532
1533 for (chan_index = 0; chan_index < 4; chan_index++)
1534 {
1535 uint swizzle;
1536 uint i;
1537
1538 /* unswizzle channel */
1539 swizzle = tgsi_util_get_full_src_register_swizzle (
1540 &inst->Src[0],
1541 chan_index);
1542
1543 /* check if the component has not been already tested */
1544 if (uniquemask & (1 << swizzle))
1545 continue;
1546 uniquemask |= 1 << swizzle;
1547
1548 FETCH(&r[0], 0, chan_index);
1549 for (i = 0; i < 4; i++)
1550 if (r[0].f[i] < 0.0f)
1551 kilmask |= 1 << i;
1552 }
1553
1554 /* restrict to fragments currently executing */
1555 kilmask &= mach->ExecMask;
1556
1557 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1558 }
1559
1560 /**
1561 * Unconditional fragment kill/discard.
1562 */
1563 static void
1564 exec_kill(struct tgsi_exec_machine *mach,
1565 const struct tgsi_full_instruction *inst)
1566 {
1567 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1568
1569 /* kill fragment for all fragments currently executing */
1570 kilmask = mach->ExecMask;
1571 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1572 }
1573
1574 static void
1575 emit_vertex(struct tgsi_exec_machine *mach)
1576 {
1577 /* FIXME: check for exec mask correctly
1578 unsigned i;
1579 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1580 if ((mach->ExecMask & (1 << i)))
1581 */
1582 if (mach->ExecMask) {
1583 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1584 return;
1585
1586 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1587 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1588 }
1589 }
1590
1591 static void
1592 emit_primitive(struct tgsi_exec_machine *mach)
1593 {
1594 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1595 /* FIXME: check for exec mask correctly
1596 unsigned i;
1597 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1598 if ((mach->ExecMask & (1 << i)))
1599 */
1600 if (mach->ExecMask) {
1601 ++(*prim_count);
1602 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1603 mach->Primitives[*prim_count] = 0;
1604 }
1605 }
1606
1607 static void
1608 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1609 {
1610 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1611 int emitted_verts =
1612 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1613 if (emitted_verts) {
1614 emit_primitive(mach);
1615 }
1616 }
1617 }
1618
1619
1620 /*
1621 * Fetch four texture samples using STR texture coordinates.
1622 */
1623 static void
1624 fetch_texel( struct tgsi_sampler *sampler,
1625 const unsigned sview_idx,
1626 const unsigned sampler_idx,
1627 const union tgsi_exec_channel *s,
1628 const union tgsi_exec_channel *t,
1629 const union tgsi_exec_channel *p,
1630 const union tgsi_exec_channel *c0,
1631 const union tgsi_exec_channel *c1,
1632 float derivs[3][2][TGSI_QUAD_SIZE],
1633 const int8_t offset[3],
1634 enum tgsi_sampler_control control,
1635 union tgsi_exec_channel *r,
1636 union tgsi_exec_channel *g,
1637 union tgsi_exec_channel *b,
1638 union tgsi_exec_channel *a )
1639 {
1640 uint j;
1641 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1642
1643 /* FIXME: handle explicit derivs, offsets */
1644 sampler->get_samples(sampler, sview_idx, sampler_idx,
1645 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1646
1647 for (j = 0; j < 4; j++) {
1648 r->f[j] = rgba[0][j];
1649 g->f[j] = rgba[1][j];
1650 b->f[j] = rgba[2][j];
1651 a->f[j] = rgba[3][j];
1652 }
1653 }
1654
1655
1656 #define TEX_MODIFIER_NONE 0
1657 #define TEX_MODIFIER_PROJECTED 1
1658 #define TEX_MODIFIER_LOD_BIAS 2
1659 #define TEX_MODIFIER_EXPLICIT_LOD 3
1660 #define TEX_MODIFIER_LEVEL_ZERO 4
1661
1662
1663 /*
1664 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1665 */
1666 static void
1667 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1668 const struct tgsi_full_instruction *inst,
1669 int8_t offsets[3])
1670 {
1671 if (inst->Texture.NumOffsets == 1) {
1672 union tgsi_exec_channel index;
1673 union tgsi_exec_channel offset[3];
1674 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1675 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1676 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1677 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1678 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1679 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1680 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1681 offsets[0] = offset[0].i[0];
1682 offsets[1] = offset[1].i[0];
1683 offsets[2] = offset[2].i[0];
1684 } else {
1685 assert(inst->Texture.NumOffsets == 0);
1686 offsets[0] = offsets[1] = offsets[2] = 0;
1687 }
1688 }
1689
1690
1691 /*
1692 * Fetch dx and dy values for one channel (s, t or r).
1693 * Put dx values into one float array, dy values into another.
1694 */
1695 static void
1696 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1697 const struct tgsi_full_instruction *inst,
1698 unsigned regdsrcx,
1699 unsigned chan,
1700 float derivs[2][TGSI_QUAD_SIZE])
1701 {
1702 union tgsi_exec_channel d;
1703 FETCH(&d, regdsrcx, chan);
1704 derivs[0][0] = d.f[0];
1705 derivs[0][1] = d.f[1];
1706 derivs[0][2] = d.f[2];
1707 derivs[0][3] = d.f[3];
1708 FETCH(&d, regdsrcx + 1, chan);
1709 derivs[1][0] = d.f[0];
1710 derivs[1][1] = d.f[1];
1711 derivs[1][2] = d.f[2];
1712 derivs[1][3] = d.f[3];
1713 }
1714
1715
1716 /*
1717 * execute a texture instruction.
1718 *
1719 * modifier is used to control the channel routing for the\
1720 * instruction variants like proj, lod, and texture with lod bias.
1721 * sampler indicates which src register the sampler is contained in.
1722 */
1723 static void
1724 exec_tex(struct tgsi_exec_machine *mach,
1725 const struct tgsi_full_instruction *inst,
1726 uint modifier, uint sampler)
1727 {
1728 const uint unit = inst->Src[sampler].Register.Index;
1729 const union tgsi_exec_channel *args[5], *proj = NULL;
1730 union tgsi_exec_channel r[5];
1731 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
1732 uint chan;
1733 int8_t offsets[3];
1734 int dim, shadow_ref, i;
1735
1736 /* always fetch all 3 offsets, overkill but keeps code simple */
1737 fetch_texel_offsets(mach, inst, offsets);
1738
1739 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
1740 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
1741
1742 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, &shadow_ref);
1743
1744 assert(dim <= 4);
1745 if (shadow_ref >= 0)
1746 assert(shadow_ref >= dim && shadow_ref < Elements(args));
1747
1748 /* fetch modifier to the last argument */
1749 if (modifier != TEX_MODIFIER_NONE) {
1750 const int last = Elements(args) - 1;
1751
1752 /* fetch modifier from src0.w or src1.x */
1753 if (sampler == 1) {
1754 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
1755 FETCH(&r[last], 0, TGSI_CHAN_W);
1756 }
1757 else {
1758 assert(shadow_ref != 4);
1759 FETCH(&r[last], 1, TGSI_CHAN_X);
1760 }
1761
1762 if (modifier != TEX_MODIFIER_PROJECTED) {
1763 args[last] = &r[last];
1764 }
1765 else {
1766 proj = &r[last];
1767 args[last] = &ZeroVec;
1768 }
1769
1770 /* point unused arguments to zero vector */
1771 for (i = dim; i < last; i++)
1772 args[i] = &ZeroVec;
1773
1774 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
1775 control = tgsi_sampler_lod_explicit;
1776 else if (modifier == TEX_MODIFIER_LOD_BIAS)
1777 control = tgsi_sampler_lod_bias;
1778 }
1779 else {
1780 for (i = dim; i < Elements(args); i++)
1781 args[i] = &ZeroVec;
1782 }
1783
1784 /* fetch coordinates */
1785 for (i = 0; i < dim; i++) {
1786 FETCH(&r[i], 0, TGSI_CHAN_X + i);
1787
1788 if (proj)
1789 micro_div(&r[i], &r[i], proj);
1790
1791 args[i] = &r[i];
1792 }
1793
1794 /* fetch reference value */
1795 if (shadow_ref >= 0) {
1796 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
1797
1798 if (proj)
1799 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
1800
1801 args[shadow_ref] = &r[shadow_ref];
1802 }
1803
1804 fetch_texel(mach->Sampler, unit, unit,
1805 args[0], args[1], args[2], args[3], args[4],
1806 NULL, offsets, control,
1807 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1808
1809 #if 0
1810 debug_printf("fetch r: %g %g %g %g\n",
1811 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1812 debug_printf("fetch g: %g %g %g %g\n",
1813 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1814 debug_printf("fetch b: %g %g %g %g\n",
1815 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1816 debug_printf("fetch a: %g %g %g %g\n",
1817 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1818 #endif
1819
1820 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1821 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1822 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1823 }
1824 }
1825 }
1826
1827
1828 static void
1829 exec_txd(struct tgsi_exec_machine *mach,
1830 const struct tgsi_full_instruction *inst)
1831 {
1832 const uint unit = inst->Src[3].Register.Index;
1833 union tgsi_exec_channel r[4];
1834 float derivs[3][2][TGSI_QUAD_SIZE];
1835 uint chan;
1836 int8_t offsets[3];
1837
1838 /* always fetch all 3 offsets, overkill but keeps code simple */
1839 fetch_texel_offsets(mach, inst, offsets);
1840
1841 switch (inst->Texture.Texture) {
1842 case TGSI_TEXTURE_1D:
1843 FETCH(&r[0], 0, TGSI_CHAN_X);
1844
1845 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1846
1847 fetch_texel(mach->Sampler, unit, unit,
1848 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1849 derivs, offsets, tgsi_sampler_derivs_explicit,
1850 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1851 break;
1852
1853 case TGSI_TEXTURE_SHADOW1D:
1854 case TGSI_TEXTURE_1D_ARRAY:
1855 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1856 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
1857 FETCH(&r[0], 0, TGSI_CHAN_X);
1858 FETCH(&r[1], 0, TGSI_CHAN_Y);
1859 FETCH(&r[2], 0, TGSI_CHAN_Z);
1860
1861 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1862
1863 fetch_texel(mach->Sampler, unit, unit,
1864 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1865 derivs, offsets, tgsi_sampler_derivs_explicit,
1866 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1867 break;
1868
1869 case TGSI_TEXTURE_2D:
1870 case TGSI_TEXTURE_RECT:
1871 FETCH(&r[0], 0, TGSI_CHAN_X);
1872 FETCH(&r[1], 0, TGSI_CHAN_Y);
1873
1874 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1875 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1876
1877 fetch_texel(mach->Sampler, unit, unit,
1878 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1879 derivs, offsets, tgsi_sampler_derivs_explicit,
1880 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1881 break;
1882
1883
1884 case TGSI_TEXTURE_SHADOW2D:
1885 case TGSI_TEXTURE_SHADOWRECT:
1886 case TGSI_TEXTURE_2D_ARRAY:
1887 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1888 /* only SHADOW2D_ARRAY actually needs W */
1889 FETCH(&r[0], 0, TGSI_CHAN_X);
1890 FETCH(&r[1], 0, TGSI_CHAN_Y);
1891 FETCH(&r[2], 0, TGSI_CHAN_Z);
1892 FETCH(&r[3], 0, TGSI_CHAN_W);
1893
1894 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1895 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1896
1897 fetch_texel(mach->Sampler, unit, unit,
1898 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1899 derivs, offsets, tgsi_sampler_derivs_explicit,
1900 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1901 break;
1902
1903 case TGSI_TEXTURE_3D:
1904 case TGSI_TEXTURE_CUBE:
1905 case TGSI_TEXTURE_CUBE_ARRAY:
1906 case TGSI_TEXTURE_SHADOWCUBE:
1907 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
1908 FETCH(&r[0], 0, TGSI_CHAN_X);
1909 FETCH(&r[1], 0, TGSI_CHAN_Y);
1910 FETCH(&r[2], 0, TGSI_CHAN_Z);
1911 FETCH(&r[3], 0, TGSI_CHAN_W);
1912
1913 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1914 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1915 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
1916
1917 fetch_texel(mach->Sampler, unit, unit,
1918 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1919 derivs, offsets, tgsi_sampler_derivs_explicit,
1920 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1921 break;
1922
1923 default:
1924 assert(0);
1925 }
1926
1927 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1928 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1929 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1930 }
1931 }
1932 }
1933
1934
1935 static void
1936 exec_txf(struct tgsi_exec_machine *mach,
1937 const struct tgsi_full_instruction *inst)
1938 {
1939 const uint unit = inst->Src[1].Register.Index;
1940 union tgsi_exec_channel r[4];
1941 uint chan;
1942 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1943 int j;
1944 int8_t offsets[3];
1945 unsigned target;
1946
1947 /* always fetch all 3 offsets, overkill but keeps code simple */
1948 fetch_texel_offsets(mach, inst, offsets);
1949
1950 IFETCH(&r[3], 0, TGSI_CHAN_W);
1951
1952 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
1953 target = mach->SamplerViews[unit].Resource;
1954 }
1955 else {
1956 target = inst->Texture.Texture;
1957 }
1958 switch(target) {
1959 case TGSI_TEXTURE_3D:
1960 case TGSI_TEXTURE_2D_ARRAY:
1961 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1962 case TGSI_TEXTURE_2D_ARRAY_MSAA:
1963 IFETCH(&r[2], 0, TGSI_CHAN_Z);
1964 /* fallthrough */
1965 case TGSI_TEXTURE_2D:
1966 case TGSI_TEXTURE_RECT:
1967 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1968 case TGSI_TEXTURE_SHADOW2D:
1969 case TGSI_TEXTURE_SHADOWRECT:
1970 case TGSI_TEXTURE_1D_ARRAY:
1971 case TGSI_TEXTURE_2D_MSAA:
1972 IFETCH(&r[1], 0, TGSI_CHAN_Y);
1973 /* fallthrough */
1974 case TGSI_TEXTURE_BUFFER:
1975 case TGSI_TEXTURE_1D:
1976 case TGSI_TEXTURE_SHADOW1D:
1977 IFETCH(&r[0], 0, TGSI_CHAN_X);
1978 break;
1979 default:
1980 assert(0);
1981 break;
1982 }
1983
1984 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
1985 offsets, rgba);
1986
1987 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
1988 r[0].f[j] = rgba[0][j];
1989 r[1].f[j] = rgba[1][j];
1990 r[2].f[j] = rgba[2][j];
1991 r[3].f[j] = rgba[3][j];
1992 }
1993
1994 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
1995 unsigned char swizzles[4];
1996 swizzles[0] = inst->Src[1].Register.SwizzleX;
1997 swizzles[1] = inst->Src[1].Register.SwizzleY;
1998 swizzles[2] = inst->Src[1].Register.SwizzleZ;
1999 swizzles[3] = inst->Src[1].Register.SwizzleW;
2000
2001 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2002 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2003 store_dest(mach, &r[swizzles[chan]],
2004 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2005 }
2006 }
2007 }
2008 else {
2009 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2010 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2011 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2012 }
2013 }
2014 }
2015 }
2016
2017 static void
2018 exec_txq(struct tgsi_exec_machine *mach,
2019 const struct tgsi_full_instruction *inst)
2020 {
2021 const uint unit = inst->Src[1].Register.Index;
2022 int result[4];
2023 union tgsi_exec_channel r[4], src;
2024 uint chan;
2025 int i,j;
2026
2027 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2028
2029 /* XXX: This interface can't return per-pixel values */
2030 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2031
2032 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2033 for (j = 0; j < 4; j++) {
2034 r[j].i[i] = result[j];
2035 }
2036 }
2037
2038 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2039 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2040 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2041 TGSI_EXEC_DATA_INT);
2042 }
2043 }
2044 }
2045
2046 static void
2047 exec_sample(struct tgsi_exec_machine *mach,
2048 const struct tgsi_full_instruction *inst,
2049 uint modifier, boolean compare)
2050 {
2051 const uint resource_unit = inst->Src[1].Register.Index;
2052 const uint sampler_unit = inst->Src[2].Register.Index;
2053 union tgsi_exec_channel r[4], c1;
2054 const union tgsi_exec_channel *lod = &ZeroVec;
2055 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2056 uint chan;
2057 unsigned char swizzles[4];
2058 int8_t offsets[3];
2059
2060 /* always fetch all 3 offsets, overkill but keeps code simple */
2061 fetch_texel_offsets(mach, inst, offsets);
2062
2063 assert(modifier != TEX_MODIFIER_PROJECTED);
2064
2065 if (modifier != TEX_MODIFIER_NONE) {
2066 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2067 FETCH(&c1, 3, TGSI_CHAN_X);
2068 lod = &c1;
2069 control = tgsi_sampler_lod_bias;
2070 }
2071 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2072 FETCH(&c1, 3, TGSI_CHAN_X);
2073 lod = &c1;
2074 control = tgsi_sampler_lod_explicit;
2075 }
2076 else {
2077 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2078 control = tgsi_sampler_lod_zero;
2079 }
2080 }
2081
2082 FETCH(&r[0], 0, TGSI_CHAN_X);
2083
2084 switch (mach->SamplerViews[resource_unit].Resource) {
2085 case TGSI_TEXTURE_1D:
2086 if (compare) {
2087 FETCH(&r[2], 3, TGSI_CHAN_X);
2088 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2089 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2090 NULL, offsets, control,
2091 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2092 }
2093 else {
2094 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2095 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2096 NULL, offsets, control,
2097 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2098 }
2099 break;
2100
2101 case TGSI_TEXTURE_1D_ARRAY:
2102 case TGSI_TEXTURE_2D:
2103 case TGSI_TEXTURE_RECT:
2104 FETCH(&r[1], 0, TGSI_CHAN_Y);
2105 if (compare) {
2106 FETCH(&r[2], 3, TGSI_CHAN_X);
2107 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2108 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2109 NULL, offsets, control,
2110 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2111 }
2112 else {
2113 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2114 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2115 NULL, offsets, control,
2116 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2117 }
2118 break;
2119
2120 case TGSI_TEXTURE_2D_ARRAY:
2121 case TGSI_TEXTURE_3D:
2122 case TGSI_TEXTURE_CUBE:
2123 FETCH(&r[1], 0, TGSI_CHAN_Y);
2124 FETCH(&r[2], 0, TGSI_CHAN_Z);
2125 if(compare) {
2126 FETCH(&r[3], 3, TGSI_CHAN_X);
2127 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2128 &r[0], &r[1], &r[2], &r[3], lod,
2129 NULL, offsets, control,
2130 &r[0], &r[1], &r[2], &r[3]);
2131 }
2132 else {
2133 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2134 &r[0], &r[1], &r[2], &ZeroVec, lod,
2135 NULL, offsets, control,
2136 &r[0], &r[1], &r[2], &r[3]);
2137 }
2138 break;
2139
2140 case TGSI_TEXTURE_CUBE_ARRAY:
2141 FETCH(&r[1], 0, TGSI_CHAN_Y);
2142 FETCH(&r[2], 0, TGSI_CHAN_Z);
2143 FETCH(&r[3], 0, TGSI_CHAN_W);
2144 if(compare) {
2145 FETCH(&r[4], 3, TGSI_CHAN_X);
2146 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2147 &r[0], &r[1], &r[2], &r[3], &r[4],
2148 NULL, offsets, control,
2149 &r[0], &r[1], &r[2], &r[3]);
2150 }
2151 else {
2152 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2153 &r[0], &r[1], &r[2], &r[3], lod,
2154 NULL, offsets, control,
2155 &r[0], &r[1], &r[2], &r[3]);
2156 }
2157 break;
2158
2159
2160 default:
2161 assert(0);
2162 }
2163
2164 swizzles[0] = inst->Src[1].Register.SwizzleX;
2165 swizzles[1] = inst->Src[1].Register.SwizzleY;
2166 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2167 swizzles[3] = inst->Src[1].Register.SwizzleW;
2168
2169 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2170 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2171 store_dest(mach, &r[swizzles[chan]],
2172 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2173 }
2174 }
2175 }
2176
2177 static void
2178 exec_sample_d(struct tgsi_exec_machine *mach,
2179 const struct tgsi_full_instruction *inst)
2180 {
2181 const uint resource_unit = inst->Src[1].Register.Index;
2182 const uint sampler_unit = inst->Src[2].Register.Index;
2183 union tgsi_exec_channel r[4];
2184 float derivs[3][2][TGSI_QUAD_SIZE];
2185 uint chan;
2186 unsigned char swizzles[4];
2187 int8_t offsets[3];
2188
2189 /* always fetch all 3 offsets, overkill but keeps code simple */
2190 fetch_texel_offsets(mach, inst, offsets);
2191
2192 FETCH(&r[0], 0, TGSI_CHAN_X);
2193
2194 switch (mach->SamplerViews[resource_unit].Resource) {
2195 case TGSI_TEXTURE_1D:
2196 case TGSI_TEXTURE_1D_ARRAY:
2197 /* only 1D array actually needs Y */
2198 FETCH(&r[1], 0, TGSI_CHAN_Y);
2199
2200 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2201
2202 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2203 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2204 derivs, offsets, tgsi_sampler_derivs_explicit,
2205 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2206 break;
2207
2208 case TGSI_TEXTURE_2D:
2209 case TGSI_TEXTURE_RECT:
2210 case TGSI_TEXTURE_2D_ARRAY:
2211 /* only 2D array actually needs Z */
2212 FETCH(&r[1], 0, TGSI_CHAN_Y);
2213 FETCH(&r[2], 0, TGSI_CHAN_Z);
2214
2215 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2216 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2217
2218 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2219 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2220 derivs, offsets, tgsi_sampler_derivs_explicit,
2221 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2222 break;
2223
2224 case TGSI_TEXTURE_3D:
2225 case TGSI_TEXTURE_CUBE:
2226 case TGSI_TEXTURE_CUBE_ARRAY:
2227 /* only cube array actually needs W */
2228 FETCH(&r[1], 0, TGSI_CHAN_Y);
2229 FETCH(&r[2], 0, TGSI_CHAN_Z);
2230 FETCH(&r[3], 0, TGSI_CHAN_W);
2231
2232 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2233 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2234 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2235
2236 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2237 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2238 derivs, offsets, tgsi_sampler_derivs_explicit,
2239 &r[0], &r[1], &r[2], &r[3]);
2240 break;
2241
2242 default:
2243 assert(0);
2244 }
2245
2246 swizzles[0] = inst->Src[1].Register.SwizzleX;
2247 swizzles[1] = inst->Src[1].Register.SwizzleY;
2248 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2249 swizzles[3] = inst->Src[1].Register.SwizzleW;
2250
2251 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2252 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2253 store_dest(mach, &r[swizzles[chan]],
2254 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2255 }
2256 }
2257 }
2258
2259
2260 /**
2261 * Evaluate a constant-valued coefficient at the position of the
2262 * current quad.
2263 */
2264 static void
2265 eval_constant_coef(
2266 struct tgsi_exec_machine *mach,
2267 unsigned attrib,
2268 unsigned chan )
2269 {
2270 unsigned i;
2271
2272 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2273 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2274 }
2275 }
2276
2277 /**
2278 * Evaluate a linear-valued coefficient at the position of the
2279 * current quad.
2280 */
2281 static void
2282 eval_linear_coef(
2283 struct tgsi_exec_machine *mach,
2284 unsigned attrib,
2285 unsigned chan )
2286 {
2287 const float x = mach->QuadPos.xyzw[0].f[0];
2288 const float y = mach->QuadPos.xyzw[1].f[0];
2289 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2290 const float dady = mach->InterpCoefs[attrib].dady[chan];
2291 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2292 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2293 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2294 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2295 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2296 }
2297
2298 /**
2299 * Evaluate a perspective-valued coefficient at the position of the
2300 * current quad.
2301 */
2302 static void
2303 eval_perspective_coef(
2304 struct tgsi_exec_machine *mach,
2305 unsigned attrib,
2306 unsigned chan )
2307 {
2308 const float x = mach->QuadPos.xyzw[0].f[0];
2309 const float y = mach->QuadPos.xyzw[1].f[0];
2310 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2311 const float dady = mach->InterpCoefs[attrib].dady[chan];
2312 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2313 const float *w = mach->QuadPos.xyzw[3].f;
2314 /* divide by W here */
2315 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2316 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2317 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2318 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2319 }
2320
2321
2322 typedef void (* eval_coef_func)(
2323 struct tgsi_exec_machine *mach,
2324 unsigned attrib,
2325 unsigned chan );
2326
2327 static void
2328 exec_declaration(struct tgsi_exec_machine *mach,
2329 const struct tgsi_full_declaration *decl)
2330 {
2331 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2332 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2333 return;
2334 }
2335
2336 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2337 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2338 uint first, last, mask;
2339
2340 first = decl->Range.First;
2341 last = decl->Range.Last;
2342 mask = decl->Declaration.UsageMask;
2343
2344 /* XXX we could remove this special-case code since
2345 * mach->InterpCoefs[first].a0 should already have the
2346 * front/back-face value. But we should first update the
2347 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2348 * Then, we could remove the tgsi_exec_machine::Face field.
2349 */
2350 /* XXX make FACE a system value */
2351 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2352 uint i;
2353
2354 assert(decl->Semantic.Index == 0);
2355 assert(first == last);
2356
2357 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2358 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2359 }
2360 } else {
2361 eval_coef_func eval;
2362 uint i, j;
2363
2364 switch (decl->Interp.Interpolate) {
2365 case TGSI_INTERPOLATE_CONSTANT:
2366 eval = eval_constant_coef;
2367 break;
2368
2369 case TGSI_INTERPOLATE_LINEAR:
2370 eval = eval_linear_coef;
2371 break;
2372
2373 case TGSI_INTERPOLATE_PERSPECTIVE:
2374 eval = eval_perspective_coef;
2375 break;
2376
2377 case TGSI_INTERPOLATE_COLOR:
2378 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2379 break;
2380
2381 default:
2382 assert(0);
2383 return;
2384 }
2385
2386 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2387 if (mask & (1 << j)) {
2388 for (i = first; i <= last; i++) {
2389 eval(mach, i, j);
2390 }
2391 }
2392 }
2393 }
2394
2395 if (DEBUG_EXECUTION) {
2396 uint i, j;
2397 for (i = first; i <= last; ++i) {
2398 debug_printf("IN[%2u] = ", i);
2399 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2400 if (j > 0) {
2401 debug_printf(" ");
2402 }
2403 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2404 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2405 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2406 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2407 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2408 }
2409 }
2410 }
2411 }
2412 }
2413
2414 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2415 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2416 }
2417 }
2418
2419 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2420 const union tgsi_exec_channel *src);
2421
2422 static void
2423 exec_scalar_unary(struct tgsi_exec_machine *mach,
2424 const struct tgsi_full_instruction *inst,
2425 micro_unary_op op,
2426 enum tgsi_exec_datatype dst_datatype,
2427 enum tgsi_exec_datatype src_datatype)
2428 {
2429 unsigned int chan;
2430 union tgsi_exec_channel src;
2431 union tgsi_exec_channel dst;
2432
2433 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2434 op(&dst, &src);
2435 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2436 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2437 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2438 }
2439 }
2440 }
2441
2442 static void
2443 exec_vector_unary(struct tgsi_exec_machine *mach,
2444 const struct tgsi_full_instruction *inst,
2445 micro_unary_op op,
2446 enum tgsi_exec_datatype dst_datatype,
2447 enum tgsi_exec_datatype src_datatype)
2448 {
2449 unsigned int chan;
2450 struct tgsi_exec_vector dst;
2451
2452 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2453 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2454 union tgsi_exec_channel src;
2455
2456 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2457 op(&dst.xyzw[chan], &src);
2458 }
2459 }
2460 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2461 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2462 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2463 }
2464 }
2465 }
2466
2467 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2468 const union tgsi_exec_channel *src0,
2469 const union tgsi_exec_channel *src1);
2470
2471 static void
2472 exec_scalar_binary(struct tgsi_exec_machine *mach,
2473 const struct tgsi_full_instruction *inst,
2474 micro_binary_op op,
2475 enum tgsi_exec_datatype dst_datatype,
2476 enum tgsi_exec_datatype src_datatype)
2477 {
2478 unsigned int chan;
2479 union tgsi_exec_channel src[2];
2480 union tgsi_exec_channel dst;
2481
2482 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2483 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2484 op(&dst, &src[0], &src[1]);
2485 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2486 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2487 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2488 }
2489 }
2490 }
2491
2492 static void
2493 exec_vector_binary(struct tgsi_exec_machine *mach,
2494 const struct tgsi_full_instruction *inst,
2495 micro_binary_op op,
2496 enum tgsi_exec_datatype dst_datatype,
2497 enum tgsi_exec_datatype src_datatype)
2498 {
2499 unsigned int chan;
2500 struct tgsi_exec_vector dst;
2501
2502 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2503 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2504 union tgsi_exec_channel src[2];
2505
2506 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2507 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2508 op(&dst.xyzw[chan], &src[0], &src[1]);
2509 }
2510 }
2511 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2512 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2513 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2514 }
2515 }
2516 }
2517
2518 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2519 const union tgsi_exec_channel *src0,
2520 const union tgsi_exec_channel *src1,
2521 const union tgsi_exec_channel *src2);
2522
2523 static void
2524 exec_vector_trinary(struct tgsi_exec_machine *mach,
2525 const struct tgsi_full_instruction *inst,
2526 micro_trinary_op op,
2527 enum tgsi_exec_datatype dst_datatype,
2528 enum tgsi_exec_datatype src_datatype)
2529 {
2530 unsigned int chan;
2531 struct tgsi_exec_vector dst;
2532
2533 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2534 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2535 union tgsi_exec_channel src[3];
2536
2537 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2538 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2539 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2540 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2541 }
2542 }
2543 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2544 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2545 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2546 }
2547 }
2548 }
2549
2550 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2551 const union tgsi_exec_channel *src0,
2552 const union tgsi_exec_channel *src1,
2553 const union tgsi_exec_channel *src2,
2554 const union tgsi_exec_channel *src3);
2555
2556 static void
2557 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2558 const struct tgsi_full_instruction *inst,
2559 micro_quaternary_op op,
2560 enum tgsi_exec_datatype dst_datatype,
2561 enum tgsi_exec_datatype src_datatype)
2562 {
2563 unsigned int chan;
2564 struct tgsi_exec_vector dst;
2565
2566 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2567 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2568 union tgsi_exec_channel src[4];
2569
2570 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2571 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2572 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2573 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2574 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2575 }
2576 }
2577 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2578 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2579 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2580 }
2581 }
2582 }
2583
2584 static void
2585 exec_dp3(struct tgsi_exec_machine *mach,
2586 const struct tgsi_full_instruction *inst)
2587 {
2588 unsigned int chan;
2589 union tgsi_exec_channel arg[3];
2590
2591 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2592 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2593 micro_mul(&arg[2], &arg[0], &arg[1]);
2594
2595 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2596 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2597 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2598 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2599 }
2600
2601 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2602 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2603 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2604 }
2605 }
2606 }
2607
2608 static void
2609 exec_dp4(struct tgsi_exec_machine *mach,
2610 const struct tgsi_full_instruction *inst)
2611 {
2612 unsigned int chan;
2613 union tgsi_exec_channel arg[3];
2614
2615 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2616 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2617 micro_mul(&arg[2], &arg[0], &arg[1]);
2618
2619 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2620 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2621 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2622 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2623 }
2624
2625 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2626 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2627 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2628 }
2629 }
2630 }
2631
2632 static void
2633 exec_dp2a(struct tgsi_exec_machine *mach,
2634 const struct tgsi_full_instruction *inst)
2635 {
2636 unsigned int chan;
2637 union tgsi_exec_channel arg[3];
2638
2639 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2640 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2641 micro_mul(&arg[2], &arg[0], &arg[1]);
2642
2643 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2644 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2645 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2646
2647 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2648 micro_add(&arg[0], &arg[0], &arg[1]);
2649
2650 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2651 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2652 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2653 }
2654 }
2655 }
2656
2657 static void
2658 exec_dph(struct tgsi_exec_machine *mach,
2659 const struct tgsi_full_instruction *inst)
2660 {
2661 unsigned int chan;
2662 union tgsi_exec_channel arg[3];
2663
2664 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2665 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2666 micro_mul(&arg[2], &arg[0], &arg[1]);
2667
2668 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2669 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2670 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2671
2672 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2673 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2674 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2675
2676 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2677 micro_add(&arg[0], &arg[0], &arg[1]);
2678
2679 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2680 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2681 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2682 }
2683 }
2684 }
2685
2686 static void
2687 exec_dp2(struct tgsi_exec_machine *mach,
2688 const struct tgsi_full_instruction *inst)
2689 {
2690 unsigned int chan;
2691 union tgsi_exec_channel arg[3];
2692
2693 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2694 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2695 micro_mul(&arg[2], &arg[0], &arg[1]);
2696
2697 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2698 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2699 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2700
2701 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2702 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2703 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2704 }
2705 }
2706 }
2707
2708 static void
2709 exec_scs(struct tgsi_exec_machine *mach,
2710 const struct tgsi_full_instruction *inst)
2711 {
2712 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2713 union tgsi_exec_channel arg;
2714 union tgsi_exec_channel result;
2715
2716 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2717
2718 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2719 micro_cos(&result, &arg);
2720 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2721 }
2722 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2723 micro_sin(&result, &arg);
2724 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2725 }
2726 }
2727 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2728 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2729 }
2730 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2731 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2732 }
2733 }
2734
2735 static void
2736 exec_xpd(struct tgsi_exec_machine *mach,
2737 const struct tgsi_full_instruction *inst)
2738 {
2739 union tgsi_exec_channel r[6];
2740 union tgsi_exec_channel d[3];
2741
2742 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2743 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2744
2745 micro_mul(&r[2], &r[0], &r[1]);
2746
2747 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2748 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2749
2750 micro_mul(&r[5], &r[3], &r[4] );
2751 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
2752
2753 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2754
2755 micro_mul(&r[3], &r[3], &r[2]);
2756
2757 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2758
2759 micro_mul(&r[1], &r[1], &r[5]);
2760 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
2761
2762 micro_mul(&r[5], &r[5], &r[4]);
2763 micro_mul(&r[0], &r[0], &r[2]);
2764 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
2765
2766 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2767 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2768 }
2769 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2770 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2771 }
2772 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2773 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2774 }
2775 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2776 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2777 }
2778 }
2779
2780 static void
2781 exec_dst(struct tgsi_exec_machine *mach,
2782 const struct tgsi_full_instruction *inst)
2783 {
2784 union tgsi_exec_channel r[2];
2785 union tgsi_exec_channel d[4];
2786
2787 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2788 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2789 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2790 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
2791 }
2792 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2793 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2794 }
2795 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2796 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2797 }
2798
2799 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2800 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2801 }
2802 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2803 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2804 }
2805 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2806 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2807 }
2808 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2809 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2810 }
2811 }
2812
2813 static void
2814 exec_log(struct tgsi_exec_machine *mach,
2815 const struct tgsi_full_instruction *inst)
2816 {
2817 union tgsi_exec_channel r[3];
2818
2819 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2820 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
2821 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
2822 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
2823 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2824 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2825 }
2826 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2827 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
2828 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
2829 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2830 }
2831 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2832 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2833 }
2834 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2835 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2836 }
2837 }
2838
2839 static void
2840 exec_exp(struct tgsi_exec_machine *mach,
2841 const struct tgsi_full_instruction *inst)
2842 {
2843 union tgsi_exec_channel r[3];
2844
2845 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2846 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
2847 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2848 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
2849 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2850 }
2851 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2852 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
2853 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2854 }
2855 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2856 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
2857 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2858 }
2859 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2860 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2861 }
2862 }
2863
2864 static void
2865 exec_lit(struct tgsi_exec_machine *mach,
2866 const struct tgsi_full_instruction *inst)
2867 {
2868 union tgsi_exec_channel r[3];
2869 union tgsi_exec_channel d[3];
2870
2871 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
2872 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2873 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2874 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2875 micro_max(&r[1], &r[1], &ZeroVec);
2876
2877 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2878 micro_min(&r[2], &r[2], &P128Vec);
2879 micro_max(&r[2], &r[2], &M128Vec);
2880 micro_pow(&r[1], &r[1], &r[2]);
2881 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
2882 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2883 }
2884 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2885 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
2886 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2887 }
2888 }
2889 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2890 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2891 }
2892
2893 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2894 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2895 }
2896 }
2897
2898 static void
2899 exec_break(struct tgsi_exec_machine *mach)
2900 {
2901 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
2902 /* turn off loop channels for each enabled exec channel */
2903 mach->LoopMask &= ~mach->ExecMask;
2904 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2905 UPDATE_EXEC_MASK(mach);
2906 } else {
2907 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
2908
2909 mach->Switch.mask = 0x0;
2910
2911 UPDATE_EXEC_MASK(mach);
2912 }
2913 }
2914
2915 static void
2916 exec_switch(struct tgsi_exec_machine *mach,
2917 const struct tgsi_full_instruction *inst)
2918 {
2919 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
2920 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
2921
2922 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
2923 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
2924 mach->Switch.mask = 0x0;
2925 mach->Switch.defaultMask = 0x0;
2926
2927 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
2928 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
2929
2930 UPDATE_EXEC_MASK(mach);
2931 }
2932
2933 static void
2934 exec_case(struct tgsi_exec_machine *mach,
2935 const struct tgsi_full_instruction *inst)
2936 {
2937 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2938 union tgsi_exec_channel src;
2939 uint mask = 0;
2940
2941 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
2942
2943 if (mach->Switch.selector.u[0] == src.u[0]) {
2944 mask |= 0x1;
2945 }
2946 if (mach->Switch.selector.u[1] == src.u[1]) {
2947 mask |= 0x2;
2948 }
2949 if (mach->Switch.selector.u[2] == src.u[2]) {
2950 mask |= 0x4;
2951 }
2952 if (mach->Switch.selector.u[3] == src.u[3]) {
2953 mask |= 0x8;
2954 }
2955
2956 mach->Switch.defaultMask |= mask;
2957
2958 mach->Switch.mask |= mask & prevMask;
2959
2960 UPDATE_EXEC_MASK(mach);
2961 }
2962
2963 /* FIXME: this will only work if default is last */
2964 static void
2965 exec_default(struct tgsi_exec_machine *mach)
2966 {
2967 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2968
2969 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
2970
2971 UPDATE_EXEC_MASK(mach);
2972 }
2973
2974 static void
2975 exec_endswitch(struct tgsi_exec_machine *mach)
2976 {
2977 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
2978 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
2979
2980 UPDATE_EXEC_MASK(mach);
2981 }
2982
2983 static void
2984 micro_i2f(union tgsi_exec_channel *dst,
2985 const union tgsi_exec_channel *src)
2986 {
2987 dst->f[0] = (float)src->i[0];
2988 dst->f[1] = (float)src->i[1];
2989 dst->f[2] = (float)src->i[2];
2990 dst->f[3] = (float)src->i[3];
2991 }
2992
2993 static void
2994 micro_not(union tgsi_exec_channel *dst,
2995 const union tgsi_exec_channel *src)
2996 {
2997 dst->u[0] = ~src->u[0];
2998 dst->u[1] = ~src->u[1];
2999 dst->u[2] = ~src->u[2];
3000 dst->u[3] = ~src->u[3];
3001 }
3002
3003 static void
3004 micro_shl(union tgsi_exec_channel *dst,
3005 const union tgsi_exec_channel *src0,
3006 const union tgsi_exec_channel *src1)
3007 {
3008 unsigned masked_count;
3009 masked_count = src1->u[0] & 0x1f;
3010 dst->u[0] = src0->u[0] << masked_count;
3011 masked_count = src1->u[1] & 0x1f;
3012 dst->u[1] = src0->u[1] << masked_count;
3013 masked_count = src1->u[2] & 0x1f;
3014 dst->u[2] = src0->u[2] << masked_count;
3015 masked_count = src1->u[3] & 0x1f;
3016 dst->u[3] = src0->u[3] << masked_count;
3017 }
3018
3019 static void
3020 micro_and(union tgsi_exec_channel *dst,
3021 const union tgsi_exec_channel *src0,
3022 const union tgsi_exec_channel *src1)
3023 {
3024 dst->u[0] = src0->u[0] & src1->u[0];
3025 dst->u[1] = src0->u[1] & src1->u[1];
3026 dst->u[2] = src0->u[2] & src1->u[2];
3027 dst->u[3] = src0->u[3] & src1->u[3];
3028 }
3029
3030 static void
3031 micro_or(union tgsi_exec_channel *dst,
3032 const union tgsi_exec_channel *src0,
3033 const union tgsi_exec_channel *src1)
3034 {
3035 dst->u[0] = src0->u[0] | src1->u[0];
3036 dst->u[1] = src0->u[1] | src1->u[1];
3037 dst->u[2] = src0->u[2] | src1->u[2];
3038 dst->u[3] = src0->u[3] | src1->u[3];
3039 }
3040
3041 static void
3042 micro_xor(union tgsi_exec_channel *dst,
3043 const union tgsi_exec_channel *src0,
3044 const union tgsi_exec_channel *src1)
3045 {
3046 dst->u[0] = src0->u[0] ^ src1->u[0];
3047 dst->u[1] = src0->u[1] ^ src1->u[1];
3048 dst->u[2] = src0->u[2] ^ src1->u[2];
3049 dst->u[3] = src0->u[3] ^ src1->u[3];
3050 }
3051
3052 static void
3053 micro_mod(union tgsi_exec_channel *dst,
3054 const union tgsi_exec_channel *src0,
3055 const union tgsi_exec_channel *src1)
3056 {
3057 dst->i[0] = src0->i[0] % src1->i[0];
3058 dst->i[1] = src0->i[1] % src1->i[1];
3059 dst->i[2] = src0->i[2] % src1->i[2];
3060 dst->i[3] = src0->i[3] % src1->i[3];
3061 }
3062
3063 static void
3064 micro_f2i(union tgsi_exec_channel *dst,
3065 const union tgsi_exec_channel *src)
3066 {
3067 dst->i[0] = (int)src->f[0];
3068 dst->i[1] = (int)src->f[1];
3069 dst->i[2] = (int)src->f[2];
3070 dst->i[3] = (int)src->f[3];
3071 }
3072
3073 static void
3074 micro_fseq(union tgsi_exec_channel *dst,
3075 const union tgsi_exec_channel *src0,
3076 const union tgsi_exec_channel *src1)
3077 {
3078 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
3079 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
3080 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
3081 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
3082 }
3083
3084 static void
3085 micro_fsge(union tgsi_exec_channel *dst,
3086 const union tgsi_exec_channel *src0,
3087 const union tgsi_exec_channel *src1)
3088 {
3089 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
3090 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
3091 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
3092 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
3093 }
3094
3095 static void
3096 micro_fslt(union tgsi_exec_channel *dst,
3097 const union tgsi_exec_channel *src0,
3098 const union tgsi_exec_channel *src1)
3099 {
3100 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
3101 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
3102 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
3103 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
3104 }
3105
3106 static void
3107 micro_fsne(union tgsi_exec_channel *dst,
3108 const union tgsi_exec_channel *src0,
3109 const union tgsi_exec_channel *src1)
3110 {
3111 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
3112 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
3113 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
3114 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
3115 }
3116
3117 static void
3118 micro_idiv(union tgsi_exec_channel *dst,
3119 const union tgsi_exec_channel *src0,
3120 const union tgsi_exec_channel *src1)
3121 {
3122 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
3123 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
3124 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
3125 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
3126 }
3127
3128 static void
3129 micro_imax(union tgsi_exec_channel *dst,
3130 const union tgsi_exec_channel *src0,
3131 const union tgsi_exec_channel *src1)
3132 {
3133 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3134 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3135 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3136 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3137 }
3138
3139 static void
3140 micro_imin(union tgsi_exec_channel *dst,
3141 const union tgsi_exec_channel *src0,
3142 const union tgsi_exec_channel *src1)
3143 {
3144 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3145 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3146 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3147 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3148 }
3149
3150 static void
3151 micro_isge(union tgsi_exec_channel *dst,
3152 const union tgsi_exec_channel *src0,
3153 const union tgsi_exec_channel *src1)
3154 {
3155 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3156 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3157 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3158 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3159 }
3160
3161 static void
3162 micro_ishr(union tgsi_exec_channel *dst,
3163 const union tgsi_exec_channel *src0,
3164 const union tgsi_exec_channel *src1)
3165 {
3166 unsigned masked_count;
3167 masked_count = src1->i[0] & 0x1f;
3168 dst->i[0] = src0->i[0] >> masked_count;
3169 masked_count = src1->i[1] & 0x1f;
3170 dst->i[1] = src0->i[1] >> masked_count;
3171 masked_count = src1->i[2] & 0x1f;
3172 dst->i[2] = src0->i[2] >> masked_count;
3173 masked_count = src1->i[3] & 0x1f;
3174 dst->i[3] = src0->i[3] >> masked_count;
3175 }
3176
3177 static void
3178 micro_islt(union tgsi_exec_channel *dst,
3179 const union tgsi_exec_channel *src0,
3180 const union tgsi_exec_channel *src1)
3181 {
3182 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3183 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3184 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3185 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3186 }
3187
3188 static void
3189 micro_f2u(union tgsi_exec_channel *dst,
3190 const union tgsi_exec_channel *src)
3191 {
3192 dst->u[0] = (uint)src->f[0];
3193 dst->u[1] = (uint)src->f[1];
3194 dst->u[2] = (uint)src->f[2];
3195 dst->u[3] = (uint)src->f[3];
3196 }
3197
3198 static void
3199 micro_u2f(union tgsi_exec_channel *dst,
3200 const union tgsi_exec_channel *src)
3201 {
3202 dst->f[0] = (float)src->u[0];
3203 dst->f[1] = (float)src->u[1];
3204 dst->f[2] = (float)src->u[2];
3205 dst->f[3] = (float)src->u[3];
3206 }
3207
3208 static void
3209 micro_uadd(union tgsi_exec_channel *dst,
3210 const union tgsi_exec_channel *src0,
3211 const union tgsi_exec_channel *src1)
3212 {
3213 dst->u[0] = src0->u[0] + src1->u[0];
3214 dst->u[1] = src0->u[1] + src1->u[1];
3215 dst->u[2] = src0->u[2] + src1->u[2];
3216 dst->u[3] = src0->u[3] + src1->u[3];
3217 }
3218
3219 static void
3220 micro_udiv(union tgsi_exec_channel *dst,
3221 const union tgsi_exec_channel *src0,
3222 const union tgsi_exec_channel *src1)
3223 {
3224 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
3225 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
3226 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
3227 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
3228 }
3229
3230 static void
3231 micro_umad(union tgsi_exec_channel *dst,
3232 const union tgsi_exec_channel *src0,
3233 const union tgsi_exec_channel *src1,
3234 const union tgsi_exec_channel *src2)
3235 {
3236 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3237 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3238 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3239 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3240 }
3241
3242 static void
3243 micro_umax(union tgsi_exec_channel *dst,
3244 const union tgsi_exec_channel *src0,
3245 const union tgsi_exec_channel *src1)
3246 {
3247 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3248 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3249 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3250 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3251 }
3252
3253 static void
3254 micro_umin(union tgsi_exec_channel *dst,
3255 const union tgsi_exec_channel *src0,
3256 const union tgsi_exec_channel *src1)
3257 {
3258 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3259 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3260 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3261 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3262 }
3263
3264 static void
3265 micro_umod(union tgsi_exec_channel *dst,
3266 const union tgsi_exec_channel *src0,
3267 const union tgsi_exec_channel *src1)
3268 {
3269 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
3270 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
3271 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
3272 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
3273 }
3274
3275 static void
3276 micro_umul(union tgsi_exec_channel *dst,
3277 const union tgsi_exec_channel *src0,
3278 const union tgsi_exec_channel *src1)
3279 {
3280 dst->u[0] = src0->u[0] * src1->u[0];
3281 dst->u[1] = src0->u[1] * src1->u[1];
3282 dst->u[2] = src0->u[2] * src1->u[2];
3283 dst->u[3] = src0->u[3] * src1->u[3];
3284 }
3285
3286 static void
3287 micro_imul_hi(union tgsi_exec_channel *dst,
3288 const union tgsi_exec_channel *src0,
3289 const union tgsi_exec_channel *src1)
3290 {
3291 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3292 dst->i[0] = I64M(src0->i[0], src1->i[0]);
3293 dst->i[1] = I64M(src0->i[1], src1->i[1]);
3294 dst->i[2] = I64M(src0->i[2], src1->i[2]);
3295 dst->i[3] = I64M(src0->i[3], src1->i[3]);
3296 #undef I64M
3297 }
3298
3299 static void
3300 micro_umul_hi(union tgsi_exec_channel *dst,
3301 const union tgsi_exec_channel *src0,
3302 const union tgsi_exec_channel *src1)
3303 {
3304 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3305 dst->u[0] = U64M(src0->u[0], src1->u[0]);
3306 dst->u[1] = U64M(src0->u[1], src1->u[1]);
3307 dst->u[2] = U64M(src0->u[2], src1->u[2]);
3308 dst->u[3] = U64M(src0->u[3], src1->u[3]);
3309 #undef U64M
3310 }
3311
3312 static void
3313 micro_useq(union tgsi_exec_channel *dst,
3314 const union tgsi_exec_channel *src0,
3315 const union tgsi_exec_channel *src1)
3316 {
3317 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3318 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3319 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3320 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3321 }
3322
3323 static void
3324 micro_usge(union tgsi_exec_channel *dst,
3325 const union tgsi_exec_channel *src0,
3326 const union tgsi_exec_channel *src1)
3327 {
3328 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3329 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3330 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3331 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3332 }
3333
3334 static void
3335 micro_ushr(union tgsi_exec_channel *dst,
3336 const union tgsi_exec_channel *src0,
3337 const union tgsi_exec_channel *src1)
3338 {
3339 unsigned masked_count;
3340 masked_count = src1->u[0] & 0x1f;
3341 dst->u[0] = src0->u[0] >> masked_count;
3342 masked_count = src1->u[1] & 0x1f;
3343 dst->u[1] = src0->u[1] >> masked_count;
3344 masked_count = src1->u[2] & 0x1f;
3345 dst->u[2] = src0->u[2] >> masked_count;
3346 masked_count = src1->u[3] & 0x1f;
3347 dst->u[3] = src0->u[3] >> masked_count;
3348 }
3349
3350 static void
3351 micro_uslt(union tgsi_exec_channel *dst,
3352 const union tgsi_exec_channel *src0,
3353 const union tgsi_exec_channel *src1)
3354 {
3355 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3356 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3357 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3358 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3359 }
3360
3361 static void
3362 micro_usne(union tgsi_exec_channel *dst,
3363 const union tgsi_exec_channel *src0,
3364 const union tgsi_exec_channel *src1)
3365 {
3366 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3367 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3368 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3369 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3370 }
3371
3372 static void
3373 micro_uarl(union tgsi_exec_channel *dst,
3374 const union tgsi_exec_channel *src)
3375 {
3376 dst->i[0] = src->u[0];
3377 dst->i[1] = src->u[1];
3378 dst->i[2] = src->u[2];
3379 dst->i[3] = src->u[3];
3380 }
3381
3382 static void
3383 micro_ucmp(union tgsi_exec_channel *dst,
3384 const union tgsi_exec_channel *src0,
3385 const union tgsi_exec_channel *src1,
3386 const union tgsi_exec_channel *src2)
3387 {
3388 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3389 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3390 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3391 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3392 }
3393
3394 /**
3395 * Signed bitfield extract (i.e. sign-extend the extracted bits)
3396 */
3397 static void
3398 micro_ibfe(union tgsi_exec_channel *dst,
3399 const union tgsi_exec_channel *src0,
3400 const union tgsi_exec_channel *src1,
3401 const union tgsi_exec_channel *src2)
3402 {
3403 int i;
3404 for (i = 0; i < 4; i++) {
3405 int width = src2->i[i] & 0x1f;
3406 int offset = src1->i[i] & 0x1f;
3407 if (width == 0)
3408 dst->i[i] = 0;
3409 else if (width + offset < 32)
3410 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
3411 else
3412 dst->i[i] = src0->i[i] >> offset;
3413 }
3414 }
3415
3416 /**
3417 * Unsigned bitfield extract
3418 */
3419 static void
3420 micro_ubfe(union tgsi_exec_channel *dst,
3421 const union tgsi_exec_channel *src0,
3422 const union tgsi_exec_channel *src1,
3423 const union tgsi_exec_channel *src2)
3424 {
3425 int i;
3426 for (i = 0; i < 4; i++) {
3427 int width = src2->u[i] & 0x1f;
3428 int offset = src1->u[i] & 0x1f;
3429 if (width == 0)
3430 dst->u[i] = 0;
3431 else if (width + offset < 32)
3432 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
3433 else
3434 dst->u[i] = src0->u[i] >> offset;
3435 }
3436 }
3437
3438 /**
3439 * Bitfield insert: copy low bits from src1 into a region of src0.
3440 */
3441 static void
3442 micro_bfi(union tgsi_exec_channel *dst,
3443 const union tgsi_exec_channel *src0,
3444 const union tgsi_exec_channel *src1,
3445 const union tgsi_exec_channel *src2,
3446 const union tgsi_exec_channel *src3)
3447 {
3448 int i;
3449 for (i = 0; i < 4; i++) {
3450 int width = src3->u[i] & 0x1f;
3451 int offset = src2->u[i] & 0x1f;
3452 int bitmask = ((1 << width) - 1) << offset;
3453 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
3454 }
3455 }
3456
3457 static void
3458 micro_brev(union tgsi_exec_channel *dst,
3459 const union tgsi_exec_channel *src)
3460 {
3461 dst->u[0] = util_bitreverse(src->u[0]);
3462 dst->u[1] = util_bitreverse(src->u[1]);
3463 dst->u[2] = util_bitreverse(src->u[2]);
3464 dst->u[3] = util_bitreverse(src->u[3]);
3465 }
3466
3467 static void
3468 micro_popc(union tgsi_exec_channel *dst,
3469 const union tgsi_exec_channel *src)
3470 {
3471 dst->u[0] = util_bitcount(src->u[0]);
3472 dst->u[1] = util_bitcount(src->u[1]);
3473 dst->u[2] = util_bitcount(src->u[2]);
3474 dst->u[3] = util_bitcount(src->u[3]);
3475 }
3476
3477 static void
3478 micro_lsb(union tgsi_exec_channel *dst,
3479 const union tgsi_exec_channel *src)
3480 {
3481 dst->i[0] = ffs(src->u[0]) - 1;
3482 dst->i[1] = ffs(src->u[1]) - 1;
3483 dst->i[2] = ffs(src->u[2]) - 1;
3484 dst->i[3] = ffs(src->u[3]) - 1;
3485 }
3486
3487 static void
3488 micro_imsb(union tgsi_exec_channel *dst,
3489 const union tgsi_exec_channel *src)
3490 {
3491 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
3492 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
3493 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
3494 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
3495 }
3496
3497 static void
3498 micro_umsb(union tgsi_exec_channel *dst,
3499 const union tgsi_exec_channel *src)
3500 {
3501 dst->i[0] = util_last_bit(src->u[0]) - 1;
3502 dst->i[1] = util_last_bit(src->u[1]) - 1;
3503 dst->i[2] = util_last_bit(src->u[2]) - 1;
3504 dst->i[3] = util_last_bit(src->u[3]) - 1;
3505 }
3506
3507 static void
3508 exec_instruction(
3509 struct tgsi_exec_machine *mach,
3510 const struct tgsi_full_instruction *inst,
3511 int *pc )
3512 {
3513 union tgsi_exec_channel r[10];
3514
3515 (*pc)++;
3516
3517 switch (inst->Instruction.Opcode) {
3518 case TGSI_OPCODE_ARL:
3519 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3520 break;
3521
3522 case TGSI_OPCODE_MOV:
3523 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3524 break;
3525
3526 case TGSI_OPCODE_LIT:
3527 exec_lit(mach, inst);
3528 break;
3529
3530 case TGSI_OPCODE_RCP:
3531 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3532 break;
3533
3534 case TGSI_OPCODE_RSQ:
3535 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3536 break;
3537
3538 case TGSI_OPCODE_EXP:
3539 exec_exp(mach, inst);
3540 break;
3541
3542 case TGSI_OPCODE_LOG:
3543 exec_log(mach, inst);
3544 break;
3545
3546 case TGSI_OPCODE_MUL:
3547 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3548 break;
3549
3550 case TGSI_OPCODE_ADD:
3551 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3552 break;
3553
3554 case TGSI_OPCODE_DP3:
3555 exec_dp3(mach, inst);
3556 break;
3557
3558 case TGSI_OPCODE_DP4:
3559 exec_dp4(mach, inst);
3560 break;
3561
3562 case TGSI_OPCODE_DST:
3563 exec_dst(mach, inst);
3564 break;
3565
3566 case TGSI_OPCODE_MIN:
3567 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3568 break;
3569
3570 case TGSI_OPCODE_MAX:
3571 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3572 break;
3573
3574 case TGSI_OPCODE_SLT:
3575 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3576 break;
3577
3578 case TGSI_OPCODE_SGE:
3579 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3580 break;
3581
3582 case TGSI_OPCODE_MAD:
3583 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3584 break;
3585
3586 case TGSI_OPCODE_SUB:
3587 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3588 break;
3589
3590 case TGSI_OPCODE_LRP:
3591 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3592 break;
3593
3594 case TGSI_OPCODE_SQRT:
3595 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3596 break;
3597
3598 case TGSI_OPCODE_DP2A:
3599 exec_dp2a(mach, inst);
3600 break;
3601
3602 case TGSI_OPCODE_FRC:
3603 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3604 break;
3605
3606 case TGSI_OPCODE_CLAMP:
3607 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3608 break;
3609
3610 case TGSI_OPCODE_FLR:
3611 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3612 break;
3613
3614 case TGSI_OPCODE_ROUND:
3615 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3616 break;
3617
3618 case TGSI_OPCODE_EX2:
3619 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3620 break;
3621
3622 case TGSI_OPCODE_LG2:
3623 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3624 break;
3625
3626 case TGSI_OPCODE_POW:
3627 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3628 break;
3629
3630 case TGSI_OPCODE_XPD:
3631 exec_xpd(mach, inst);
3632 break;
3633
3634 case TGSI_OPCODE_ABS:
3635 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3636 break;
3637
3638 case TGSI_OPCODE_DPH:
3639 exec_dph(mach, inst);
3640 break;
3641
3642 case TGSI_OPCODE_COS:
3643 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3644 break;
3645
3646 case TGSI_OPCODE_DDX:
3647 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3648 break;
3649
3650 case TGSI_OPCODE_DDY:
3651 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3652 break;
3653
3654 case TGSI_OPCODE_KILL:
3655 exec_kill (mach, inst);
3656 break;
3657
3658 case TGSI_OPCODE_KILL_IF:
3659 exec_kill_if (mach, inst);
3660 break;
3661
3662 case TGSI_OPCODE_PK2H:
3663 assert (0);
3664 break;
3665
3666 case TGSI_OPCODE_PK2US:
3667 assert (0);
3668 break;
3669
3670 case TGSI_OPCODE_PK4B:
3671 assert (0);
3672 break;
3673
3674 case TGSI_OPCODE_PK4UB:
3675 assert (0);
3676 break;
3677
3678 case TGSI_OPCODE_SEQ:
3679 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3680 break;
3681
3682 case TGSI_OPCODE_SGT:
3683 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3684 break;
3685
3686 case TGSI_OPCODE_SIN:
3687 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3688 break;
3689
3690 case TGSI_OPCODE_SLE:
3691 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3692 break;
3693
3694 case TGSI_OPCODE_SNE:
3695 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3696 break;
3697
3698 case TGSI_OPCODE_TEX:
3699 /* simple texture lookup */
3700 /* src[0] = texcoord */
3701 /* src[1] = sampler unit */
3702 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
3703 break;
3704
3705 case TGSI_OPCODE_TXB:
3706 /* Texture lookup with lod bias */
3707 /* src[0] = texcoord (src[0].w = LOD bias) */
3708 /* src[1] = sampler unit */
3709 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
3710 break;
3711
3712 case TGSI_OPCODE_TXD:
3713 /* Texture lookup with explict partial derivatives */
3714 /* src[0] = texcoord */
3715 /* src[1] = d[strq]/dx */
3716 /* src[2] = d[strq]/dy */
3717 /* src[3] = sampler unit */
3718 exec_txd(mach, inst);
3719 break;
3720
3721 case TGSI_OPCODE_TXL:
3722 /* Texture lookup with explit LOD */
3723 /* src[0] = texcoord (src[0].w = LOD) */
3724 /* src[1] = sampler unit */
3725 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
3726 break;
3727
3728 case TGSI_OPCODE_TXP:
3729 /* Texture lookup with projection */
3730 /* src[0] = texcoord (src[0].w = projection) */
3731 /* src[1] = sampler unit */
3732 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
3733 break;
3734
3735 case TGSI_OPCODE_UP2H:
3736 assert (0);
3737 break;
3738
3739 case TGSI_OPCODE_UP2US:
3740 assert (0);
3741 break;
3742
3743 case TGSI_OPCODE_UP4B:
3744 assert (0);
3745 break;
3746
3747 case TGSI_OPCODE_UP4UB:
3748 assert (0);
3749 break;
3750
3751 case TGSI_OPCODE_ARR:
3752 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3753 break;
3754
3755 case TGSI_OPCODE_CAL:
3756 /* skip the call if no execution channels are enabled */
3757 if (mach->ExecMask) {
3758 /* do the call */
3759
3760 /* First, record the depths of the execution stacks.
3761 * This is important for deeply nested/looped return statements.
3762 * We have to unwind the stacks by the correct amount. For a
3763 * real code generator, we could determine the number of entries
3764 * to pop off each stack with simple static analysis and avoid
3765 * implementing this data structure at run time.
3766 */
3767 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3768 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3769 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3770 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3771 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3772 /* note that PC was already incremented above */
3773 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3774
3775 mach->CallStackTop++;
3776
3777 /* Second, push the Cond, Loop, Cont, Func stacks */
3778 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3779 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3780 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3781 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3782 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3783 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3784
3785 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3786 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3787 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3788 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3789 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3790 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3791
3792 /* Finally, jump to the subroutine */
3793 *pc = inst->Label.Label;
3794 }
3795 break;
3796
3797 case TGSI_OPCODE_RET:
3798 mach->FuncMask &= ~mach->ExecMask;
3799 UPDATE_EXEC_MASK(mach);
3800
3801 if (mach->FuncMask == 0x0) {
3802 /* really return now (otherwise, keep executing */
3803
3804 if (mach->CallStackTop == 0) {
3805 /* returning from main() */
3806 mach->CondStackTop = 0;
3807 mach->LoopStackTop = 0;
3808 *pc = -1;
3809 return;
3810 }
3811
3812 assert(mach->CallStackTop > 0);
3813 mach->CallStackTop--;
3814
3815 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3816 mach->CondMask = mach->CondStack[mach->CondStackTop];
3817
3818 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3819 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3820
3821 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3822 mach->ContMask = mach->ContStack[mach->ContStackTop];
3823
3824 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3825 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3826
3827 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3828 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3829
3830 assert(mach->FuncStackTop > 0);
3831 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3832
3833 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3834
3835 UPDATE_EXEC_MASK(mach);
3836 }
3837 break;
3838
3839 case TGSI_OPCODE_SSG:
3840 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3841 break;
3842
3843 case TGSI_OPCODE_CMP:
3844 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3845 break;
3846
3847 case TGSI_OPCODE_SCS:
3848 exec_scs(mach, inst);
3849 break;
3850
3851 case TGSI_OPCODE_DIV:
3852 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3853 break;
3854
3855 case TGSI_OPCODE_DP2:
3856 exec_dp2(mach, inst);
3857 break;
3858
3859 case TGSI_OPCODE_IF:
3860 /* push CondMask */
3861 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3862 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3863 FETCH( &r[0], 0, TGSI_CHAN_X );
3864 /* update CondMask */
3865 if( ! r[0].f[0] ) {
3866 mach->CondMask &= ~0x1;
3867 }
3868 if( ! r[0].f[1] ) {
3869 mach->CondMask &= ~0x2;
3870 }
3871 if( ! r[0].f[2] ) {
3872 mach->CondMask &= ~0x4;
3873 }
3874 if( ! r[0].f[3] ) {
3875 mach->CondMask &= ~0x8;
3876 }
3877 UPDATE_EXEC_MASK(mach);
3878 /* Todo: If CondMask==0, jump to ELSE */
3879 break;
3880
3881 case TGSI_OPCODE_UIF:
3882 /* push CondMask */
3883 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3884 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3885 IFETCH( &r[0], 0, TGSI_CHAN_X );
3886 /* update CondMask */
3887 if( ! r[0].u[0] ) {
3888 mach->CondMask &= ~0x1;
3889 }
3890 if( ! r[0].u[1] ) {
3891 mach->CondMask &= ~0x2;
3892 }
3893 if( ! r[0].u[2] ) {
3894 mach->CondMask &= ~0x4;
3895 }
3896 if( ! r[0].u[3] ) {
3897 mach->CondMask &= ~0x8;
3898 }
3899 UPDATE_EXEC_MASK(mach);
3900 /* Todo: If CondMask==0, jump to ELSE */
3901 break;
3902
3903 case TGSI_OPCODE_ELSE:
3904 /* invert CondMask wrt previous mask */
3905 {
3906 uint prevMask;
3907 assert(mach->CondStackTop > 0);
3908 prevMask = mach->CondStack[mach->CondStackTop - 1];
3909 mach->CondMask = ~mach->CondMask & prevMask;
3910 UPDATE_EXEC_MASK(mach);
3911 /* Todo: If CondMask==0, jump to ENDIF */
3912 }
3913 break;
3914
3915 case TGSI_OPCODE_ENDIF:
3916 /* pop CondMask */
3917 assert(mach->CondStackTop > 0);
3918 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3919 UPDATE_EXEC_MASK(mach);
3920 break;
3921
3922 case TGSI_OPCODE_END:
3923 /* make sure we end primitives which haven't
3924 * been explicitly emitted */
3925 conditional_emit_primitive(mach);
3926 /* halt execution */
3927 *pc = -1;
3928 break;
3929
3930 case TGSI_OPCODE_PUSHA:
3931 assert (0);
3932 break;
3933
3934 case TGSI_OPCODE_POPA:
3935 assert (0);
3936 break;
3937
3938 case TGSI_OPCODE_CEIL:
3939 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3940 break;
3941
3942 case TGSI_OPCODE_I2F:
3943 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3944 break;
3945
3946 case TGSI_OPCODE_NOT:
3947 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3948 break;
3949
3950 case TGSI_OPCODE_TRUNC:
3951 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3952 break;
3953
3954 case TGSI_OPCODE_SHL:
3955 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3956 break;
3957
3958 case TGSI_OPCODE_AND:
3959 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3960 break;
3961
3962 case TGSI_OPCODE_OR:
3963 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3964 break;
3965
3966 case TGSI_OPCODE_MOD:
3967 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3968 break;
3969
3970 case TGSI_OPCODE_XOR:
3971 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3972 break;
3973
3974 case TGSI_OPCODE_SAD:
3975 assert (0);
3976 break;
3977
3978 case TGSI_OPCODE_TXF:
3979 exec_txf(mach, inst);
3980 break;
3981
3982 case TGSI_OPCODE_TXQ:
3983 exec_txq(mach, inst);
3984 break;
3985
3986 case TGSI_OPCODE_EMIT:
3987 emit_vertex(mach);
3988 break;
3989
3990 case TGSI_OPCODE_ENDPRIM:
3991 emit_primitive(mach);
3992 break;
3993
3994 case TGSI_OPCODE_BGNLOOP:
3995 /* push LoopMask and ContMasks */
3996 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3997 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3998 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3999 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4000
4001 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4002 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4003 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4004 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4005 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4006 break;
4007
4008 case TGSI_OPCODE_ENDLOOP:
4009 /* Restore ContMask, but don't pop */
4010 assert(mach->ContStackTop > 0);
4011 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4012 UPDATE_EXEC_MASK(mach);
4013 if (mach->ExecMask) {
4014 /* repeat loop: jump to instruction just past BGNLOOP */
4015 assert(mach->LoopLabelStackTop > 0);
4016 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4017 }
4018 else {
4019 /* exit loop: pop LoopMask */
4020 assert(mach->LoopStackTop > 0);
4021 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4022 /* pop ContMask */
4023 assert(mach->ContStackTop > 0);
4024 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4025 assert(mach->LoopLabelStackTop > 0);
4026 --mach->LoopLabelStackTop;
4027
4028 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4029 }
4030 UPDATE_EXEC_MASK(mach);
4031 break;
4032
4033 case TGSI_OPCODE_BRK:
4034 exec_break(mach);
4035 break;
4036
4037 case TGSI_OPCODE_CONT:
4038 /* turn off cont channels for each enabled exec channel */
4039 mach->ContMask &= ~mach->ExecMask;
4040 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4041 UPDATE_EXEC_MASK(mach);
4042 break;
4043
4044 case TGSI_OPCODE_BGNSUB:
4045 /* no-op */
4046 break;
4047
4048 case TGSI_OPCODE_ENDSUB:
4049 /*
4050 * XXX: This really should be a no-op. We should never reach this opcode.
4051 */
4052
4053 assert(mach->CallStackTop > 0);
4054 mach->CallStackTop--;
4055
4056 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4057 mach->CondMask = mach->CondStack[mach->CondStackTop];
4058
4059 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4060 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4061
4062 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4063 mach->ContMask = mach->ContStack[mach->ContStackTop];
4064
4065 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4066 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4067
4068 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4069 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4070
4071 assert(mach->FuncStackTop > 0);
4072 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4073
4074 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4075
4076 UPDATE_EXEC_MASK(mach);
4077 break;
4078
4079 case TGSI_OPCODE_NOP:
4080 break;
4081
4082 case TGSI_OPCODE_BREAKC:
4083 IFETCH(&r[0], 0, TGSI_CHAN_X);
4084 /* update CondMask */
4085 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4086 mach->LoopMask &= ~0x1;
4087 }
4088 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4089 mach->LoopMask &= ~0x2;
4090 }
4091 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4092 mach->LoopMask &= ~0x4;
4093 }
4094 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4095 mach->LoopMask &= ~0x8;
4096 }
4097 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4098 UPDATE_EXEC_MASK(mach);
4099 break;
4100
4101 case TGSI_OPCODE_F2I:
4102 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4103 break;
4104
4105 case TGSI_OPCODE_FSEQ:
4106 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4107 break;
4108
4109 case TGSI_OPCODE_FSGE:
4110 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4111 break;
4112
4113 case TGSI_OPCODE_FSLT:
4114 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4115 break;
4116
4117 case TGSI_OPCODE_FSNE:
4118 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4119 break;
4120
4121 case TGSI_OPCODE_IDIV:
4122 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4123 break;
4124
4125 case TGSI_OPCODE_IMAX:
4126 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4127 break;
4128
4129 case TGSI_OPCODE_IMIN:
4130 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4131 break;
4132
4133 case TGSI_OPCODE_INEG:
4134 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4135 break;
4136
4137 case TGSI_OPCODE_ISGE:
4138 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4139 break;
4140
4141 case TGSI_OPCODE_ISHR:
4142 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4143 break;
4144
4145 case TGSI_OPCODE_ISLT:
4146 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4147 break;
4148
4149 case TGSI_OPCODE_F2U:
4150 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4151 break;
4152
4153 case TGSI_OPCODE_U2F:
4154 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4155 break;
4156
4157 case TGSI_OPCODE_UADD:
4158 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4159 break;
4160
4161 case TGSI_OPCODE_UDIV:
4162 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4163 break;
4164
4165 case TGSI_OPCODE_UMAD:
4166 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4167 break;
4168
4169 case TGSI_OPCODE_UMAX:
4170 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4171 break;
4172
4173 case TGSI_OPCODE_UMIN:
4174 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4175 break;
4176
4177 case TGSI_OPCODE_UMOD:
4178 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4179 break;
4180
4181 case TGSI_OPCODE_UMUL:
4182 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4183 break;
4184
4185 case TGSI_OPCODE_IMUL_HI:
4186 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4187 break;
4188
4189 case TGSI_OPCODE_UMUL_HI:
4190 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4191 break;
4192
4193 case TGSI_OPCODE_USEQ:
4194 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4195 break;
4196
4197 case TGSI_OPCODE_USGE:
4198 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4199 break;
4200
4201 case TGSI_OPCODE_USHR:
4202 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4203 break;
4204
4205 case TGSI_OPCODE_USLT:
4206 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4207 break;
4208
4209 case TGSI_OPCODE_USNE:
4210 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4211 break;
4212
4213 case TGSI_OPCODE_SWITCH:
4214 exec_switch(mach, inst);
4215 break;
4216
4217 case TGSI_OPCODE_CASE:
4218 exec_case(mach, inst);
4219 break;
4220
4221 case TGSI_OPCODE_DEFAULT:
4222 exec_default(mach);
4223 break;
4224
4225 case TGSI_OPCODE_ENDSWITCH:
4226 exec_endswitch(mach);
4227 break;
4228
4229 case TGSI_OPCODE_SAMPLE_I:
4230 exec_txf(mach, inst);
4231 break;
4232
4233 case TGSI_OPCODE_SAMPLE_I_MS:
4234 assert(0);
4235 break;
4236
4237 case TGSI_OPCODE_SAMPLE:
4238 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4239 break;
4240
4241 case TGSI_OPCODE_SAMPLE_B:
4242 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4243 break;
4244
4245 case TGSI_OPCODE_SAMPLE_C:
4246 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4247 break;
4248
4249 case TGSI_OPCODE_SAMPLE_C_LZ:
4250 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4251 break;
4252
4253 case TGSI_OPCODE_SAMPLE_D:
4254 exec_sample_d(mach, inst);
4255 break;
4256
4257 case TGSI_OPCODE_SAMPLE_L:
4258 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4259 break;
4260
4261 case TGSI_OPCODE_GATHER4:
4262 assert(0);
4263 break;
4264
4265 case TGSI_OPCODE_SVIEWINFO:
4266 exec_txq(mach, inst);
4267 break;
4268
4269 case TGSI_OPCODE_SAMPLE_POS:
4270 assert(0);
4271 break;
4272
4273 case TGSI_OPCODE_SAMPLE_INFO:
4274 assert(0);
4275 break;
4276
4277 case TGSI_OPCODE_UARL:
4278 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4279 break;
4280
4281 case TGSI_OPCODE_UCMP:
4282 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4283 break;
4284
4285 case TGSI_OPCODE_IABS:
4286 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4287 break;
4288
4289 case TGSI_OPCODE_ISSG:
4290 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4291 break;
4292
4293 case TGSI_OPCODE_TEX2:
4294 /* simple texture lookup */
4295 /* src[0] = texcoord */
4296 /* src[1] = compare */
4297 /* src[2] = sampler unit */
4298 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4299 break;
4300 case TGSI_OPCODE_TXB2:
4301 /* simple texture lookup */
4302 /* src[0] = texcoord */
4303 /* src[1] = bias */
4304 /* src[2] = sampler unit */
4305 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4306 break;
4307 case TGSI_OPCODE_TXL2:
4308 /* simple texture lookup */
4309 /* src[0] = texcoord */
4310 /* src[1] = lod */
4311 /* src[2] = sampler unit */
4312 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4313 break;
4314
4315 case TGSI_OPCODE_IBFE:
4316 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4317 break;
4318 case TGSI_OPCODE_UBFE:
4319 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4320 break;
4321 case TGSI_OPCODE_BFI:
4322 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4323 break;
4324 case TGSI_OPCODE_BREV:
4325 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4326 break;
4327 case TGSI_OPCODE_POPC:
4328 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4329 break;
4330 case TGSI_OPCODE_LSB:
4331 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4332 break;
4333 case TGSI_OPCODE_IMSB:
4334 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4335 break;
4336 case TGSI_OPCODE_UMSB:
4337 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4338 break;
4339 default:
4340 assert( 0 );
4341 }
4342 }
4343
4344
4345 /**
4346 * Run TGSI interpreter.
4347 * \return bitmask of "alive" quad components
4348 */
4349 uint
4350 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4351 {
4352 uint i;
4353 int pc = 0;
4354 uint default_mask = 0xf;
4355
4356 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4357 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4358
4359 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4360 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4361 mach->Primitives[0] = 0;
4362 /* GS runs on a single primitive for now */
4363 default_mask = 0x1;
4364 }
4365
4366 mach->CondMask = default_mask;
4367 mach->LoopMask = default_mask;
4368 mach->ContMask = default_mask;
4369 mach->FuncMask = default_mask;
4370 mach->ExecMask = default_mask;
4371
4372 mach->Switch.mask = default_mask;
4373
4374 assert(mach->CondStackTop == 0);
4375 assert(mach->LoopStackTop == 0);
4376 assert(mach->ContStackTop == 0);
4377 assert(mach->SwitchStackTop == 0);
4378 assert(mach->BreakStackTop == 0);
4379 assert(mach->CallStackTop == 0);
4380
4381
4382 /* execute declarations (interpolants) */
4383 for (i = 0; i < mach->NumDeclarations; i++) {
4384 exec_declaration( mach, mach->Declarations+i );
4385 }
4386
4387 {
4388 #if DEBUG_EXECUTION
4389 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4390 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4391 uint inst = 1;
4392
4393 memset(mach->Temps, 0, sizeof(temps));
4394 memset(mach->Outputs, 0, sizeof(outputs));
4395 memset(temps, 0, sizeof(temps));
4396 memset(outputs, 0, sizeof(outputs));
4397 #endif
4398
4399 /* execute instructions, until pc is set to -1 */
4400 while (pc != -1) {
4401
4402 #if DEBUG_EXECUTION
4403 uint i;
4404
4405 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4406 #endif
4407
4408 assert(pc < (int) mach->NumInstructions);
4409 exec_instruction(mach, mach->Instructions + pc, &pc);
4410
4411 #if DEBUG_EXECUTION
4412 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4413 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4414 uint j;
4415
4416 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4417 debug_printf("TEMP[%2u] = ", i);
4418 for (j = 0; j < 4; j++) {
4419 if (j > 0) {
4420 debug_printf(" ");
4421 }
4422 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4423 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4424 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4425 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4426 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4427 }
4428 }
4429 }
4430 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4431 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4432 uint j;
4433
4434 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4435 debug_printf("OUT[%2u] = ", i);
4436 for (j = 0; j < 4; j++) {
4437 if (j > 0) {
4438 debug_printf(" ");
4439 }
4440 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4441 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4442 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4443 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4444 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4445 }
4446 }
4447 }
4448 #endif
4449 }
4450 }
4451
4452 #if 0
4453 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4454 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4455 /*
4456 * Scale back depth component.
4457 */
4458 for (i = 0; i < 4; i++)
4459 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4460 }
4461 #endif
4462
4463 /* Strictly speaking, these assertions aren't really needed but they
4464 * can potentially catch some bugs in the control flow code.
4465 */
4466 assert(mach->CondStackTop == 0);
4467 assert(mach->LoopStackTop == 0);
4468 assert(mach->ContStackTop == 0);
4469 assert(mach->SwitchStackTop == 0);
4470 assert(mach->BreakStackTop == 0);
4471 assert(mach->CallStackTop == 0);
4472
4473 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4474 }