1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
67 #define DEBUG_EXECUTION 0
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
77 union tgsi_double_channel
{
78 double d
[TGSI_QUAD_SIZE
];
79 unsigned u
[TGSI_QUAD_SIZE
][2];
80 uint64_t u64
[TGSI_QUAD_SIZE
];
81 int64_t i64
[TGSI_QUAD_SIZE
];
84 struct tgsi_double_vector
{
85 union tgsi_double_channel xy
;
86 union tgsi_double_channel zw
;
90 micro_abs(union tgsi_exec_channel
*dst
,
91 const union tgsi_exec_channel
*src
)
93 dst
->f
[0] = fabsf(src
->f
[0]);
94 dst
->f
[1] = fabsf(src
->f
[1]);
95 dst
->f
[2] = fabsf(src
->f
[2]);
96 dst
->f
[3] = fabsf(src
->f
[3]);
100 micro_arl(union tgsi_exec_channel
*dst
,
101 const union tgsi_exec_channel
*src
)
103 dst
->i
[0] = (int)floorf(src
->f
[0]);
104 dst
->i
[1] = (int)floorf(src
->f
[1]);
105 dst
->i
[2] = (int)floorf(src
->f
[2]);
106 dst
->i
[3] = (int)floorf(src
->f
[3]);
110 micro_arr(union tgsi_exec_channel
*dst
,
111 const union tgsi_exec_channel
*src
)
113 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
114 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
115 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
116 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
120 micro_ceil(union tgsi_exec_channel
*dst
,
121 const union tgsi_exec_channel
*src
)
123 dst
->f
[0] = ceilf(src
->f
[0]);
124 dst
->f
[1] = ceilf(src
->f
[1]);
125 dst
->f
[2] = ceilf(src
->f
[2]);
126 dst
->f
[3] = ceilf(src
->f
[3]);
130 micro_cmp(union tgsi_exec_channel
*dst
,
131 const union tgsi_exec_channel
*src0
,
132 const union tgsi_exec_channel
*src1
,
133 const union tgsi_exec_channel
*src2
)
135 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
136 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
137 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
138 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
142 micro_cos(union tgsi_exec_channel
*dst
,
143 const union tgsi_exec_channel
*src
)
145 dst
->f
[0] = cosf(src
->f
[0]);
146 dst
->f
[1] = cosf(src
->f
[1]);
147 dst
->f
[2] = cosf(src
->f
[2]);
148 dst
->f
[3] = cosf(src
->f
[3]);
152 micro_d2f(union tgsi_exec_channel
*dst
,
153 const union tgsi_double_channel
*src
)
155 dst
->f
[0] = (float)src
->d
[0];
156 dst
->f
[1] = (float)src
->d
[1];
157 dst
->f
[2] = (float)src
->d
[2];
158 dst
->f
[3] = (float)src
->d
[3];
162 micro_d2i(union tgsi_exec_channel
*dst
,
163 const union tgsi_double_channel
*src
)
165 dst
->i
[0] = (int)src
->d
[0];
166 dst
->i
[1] = (int)src
->d
[1];
167 dst
->i
[2] = (int)src
->d
[2];
168 dst
->i
[3] = (int)src
->d
[3];
172 micro_d2u(union tgsi_exec_channel
*dst
,
173 const union tgsi_double_channel
*src
)
175 dst
->u
[0] = (unsigned)src
->d
[0];
176 dst
->u
[1] = (unsigned)src
->d
[1];
177 dst
->u
[2] = (unsigned)src
->d
[2];
178 dst
->u
[3] = (unsigned)src
->d
[3];
181 micro_dabs(union tgsi_double_channel
*dst
,
182 const union tgsi_double_channel
*src
)
184 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
185 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
186 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
187 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
191 micro_dadd(union tgsi_double_channel
*dst
,
192 const union tgsi_double_channel
*src
)
194 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
195 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
196 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
197 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
201 micro_ddiv(union tgsi_double_channel
*dst
,
202 const union tgsi_double_channel
*src
)
204 dst
->d
[0] = src
[0].d
[0] / src
[1].d
[0];
205 dst
->d
[1] = src
[0].d
[1] / src
[1].d
[1];
206 dst
->d
[2] = src
[0].d
[2] / src
[1].d
[2];
207 dst
->d
[3] = src
[0].d
[3] / src
[1].d
[3];
211 micro_ddx(union tgsi_exec_channel
*dst
,
212 const union tgsi_exec_channel
*src
)
217 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
221 micro_ddx_fine(union tgsi_exec_channel
*dst
,
222 const union tgsi_exec_channel
*src
)
225 dst
->f
[1] = src
->f
[TILE_TOP_RIGHT
] - src
->f
[TILE_TOP_LEFT
];
227 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
232 micro_ddy(union tgsi_exec_channel
*dst
,
233 const union tgsi_exec_channel
*src
)
238 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
242 micro_ddy_fine(union tgsi_exec_channel
*dst
,
243 const union tgsi_exec_channel
*src
)
246 dst
->f
[2] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
248 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_TOP_RIGHT
];
252 micro_dmul(union tgsi_double_channel
*dst
,
253 const union tgsi_double_channel
*src
)
255 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
256 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
257 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
258 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
262 micro_dmax(union tgsi_double_channel
*dst
,
263 const union tgsi_double_channel
*src
)
265 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
266 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
267 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
268 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
272 micro_dmin(union tgsi_double_channel
*dst
,
273 const union tgsi_double_channel
*src
)
275 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
276 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
277 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
278 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
282 micro_dneg(union tgsi_double_channel
*dst
,
283 const union tgsi_double_channel
*src
)
285 dst
->d
[0] = -src
->d
[0];
286 dst
->d
[1] = -src
->d
[1];
287 dst
->d
[2] = -src
->d
[2];
288 dst
->d
[3] = -src
->d
[3];
292 micro_dslt(union tgsi_double_channel
*dst
,
293 const union tgsi_double_channel
*src
)
295 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
296 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
297 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
298 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
302 micro_dsne(union tgsi_double_channel
*dst
,
303 const union tgsi_double_channel
*src
)
305 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
306 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
307 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
308 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
312 micro_dsge(union tgsi_double_channel
*dst
,
313 const union tgsi_double_channel
*src
)
315 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
316 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
317 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
318 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
322 micro_dseq(union tgsi_double_channel
*dst
,
323 const union tgsi_double_channel
*src
)
325 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
326 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
327 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
328 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
332 micro_drcp(union tgsi_double_channel
*dst
,
333 const union tgsi_double_channel
*src
)
335 dst
->d
[0] = 1.0 / src
->d
[0];
336 dst
->d
[1] = 1.0 / src
->d
[1];
337 dst
->d
[2] = 1.0 / src
->d
[2];
338 dst
->d
[3] = 1.0 / src
->d
[3];
342 micro_dsqrt(union tgsi_double_channel
*dst
,
343 const union tgsi_double_channel
*src
)
345 dst
->d
[0] = sqrt(src
->d
[0]);
346 dst
->d
[1] = sqrt(src
->d
[1]);
347 dst
->d
[2] = sqrt(src
->d
[2]);
348 dst
->d
[3] = sqrt(src
->d
[3]);
352 micro_drsq(union tgsi_double_channel
*dst
,
353 const union tgsi_double_channel
*src
)
355 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
356 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
357 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
358 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
362 micro_dmad(union tgsi_double_channel
*dst
,
363 const union tgsi_double_channel
*src
)
365 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
366 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
367 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
368 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
372 micro_dfrac(union tgsi_double_channel
*dst
,
373 const union tgsi_double_channel
*src
)
375 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
376 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
377 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
378 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
382 micro_dldexp(union tgsi_double_channel
*dst
,
383 const union tgsi_double_channel
*src0
,
384 union tgsi_exec_channel
*src1
)
386 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
387 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
388 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
389 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
393 micro_dfracexp(union tgsi_double_channel
*dst
,
394 union tgsi_exec_channel
*dst_exp
,
395 const union tgsi_double_channel
*src
)
397 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
398 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
399 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
400 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
404 micro_exp2(union tgsi_exec_channel
*dst
,
405 const union tgsi_exec_channel
*src
)
408 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
409 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
410 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
411 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
414 /* Inf is okay for this instruction, so clamp it to silence assertions. */
416 union tgsi_exec_channel clamped
;
418 for (i
= 0; i
< 4; i
++) {
419 if (src
->f
[i
] > 127.99999f
) {
420 clamped
.f
[i
] = 127.99999f
;
421 } else if (src
->f
[i
] < -126.99999f
) {
422 clamped
.f
[i
] = -126.99999f
;
424 clamped
.f
[i
] = src
->f
[i
];
430 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
431 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
432 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
433 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
434 #endif /* FAST_MATH */
438 micro_f2d(union tgsi_double_channel
*dst
,
439 const union tgsi_exec_channel
*src
)
441 dst
->d
[0] = (double)src
->f
[0];
442 dst
->d
[1] = (double)src
->f
[1];
443 dst
->d
[2] = (double)src
->f
[2];
444 dst
->d
[3] = (double)src
->f
[3];
448 micro_flr(union tgsi_exec_channel
*dst
,
449 const union tgsi_exec_channel
*src
)
451 dst
->f
[0] = floorf(src
->f
[0]);
452 dst
->f
[1] = floorf(src
->f
[1]);
453 dst
->f
[2] = floorf(src
->f
[2]);
454 dst
->f
[3] = floorf(src
->f
[3]);
458 micro_frc(union tgsi_exec_channel
*dst
,
459 const union tgsi_exec_channel
*src
)
461 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
462 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
463 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
464 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
468 micro_i2d(union tgsi_double_channel
*dst
,
469 const union tgsi_exec_channel
*src
)
471 dst
->d
[0] = (double)src
->i
[0];
472 dst
->d
[1] = (double)src
->i
[1];
473 dst
->d
[2] = (double)src
->i
[2];
474 dst
->d
[3] = (double)src
->i
[3];
478 micro_iabs(union tgsi_exec_channel
*dst
,
479 const union tgsi_exec_channel
*src
)
481 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
482 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
483 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
484 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
488 micro_ineg(union tgsi_exec_channel
*dst
,
489 const union tgsi_exec_channel
*src
)
491 dst
->i
[0] = -src
->i
[0];
492 dst
->i
[1] = -src
->i
[1];
493 dst
->i
[2] = -src
->i
[2];
494 dst
->i
[3] = -src
->i
[3];
498 micro_lg2(union tgsi_exec_channel
*dst
,
499 const union tgsi_exec_channel
*src
)
502 dst
->f
[0] = util_fast_log2(src
->f
[0]);
503 dst
->f
[1] = util_fast_log2(src
->f
[1]);
504 dst
->f
[2] = util_fast_log2(src
->f
[2]);
505 dst
->f
[3] = util_fast_log2(src
->f
[3]);
507 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
508 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
509 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
510 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
515 micro_lrp(union tgsi_exec_channel
*dst
,
516 const union tgsi_exec_channel
*src0
,
517 const union tgsi_exec_channel
*src1
,
518 const union tgsi_exec_channel
*src2
)
520 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
521 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
522 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
523 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
527 micro_mad(union tgsi_exec_channel
*dst
,
528 const union tgsi_exec_channel
*src0
,
529 const union tgsi_exec_channel
*src1
,
530 const union tgsi_exec_channel
*src2
)
532 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
533 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
534 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
535 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
539 micro_mov(union tgsi_exec_channel
*dst
,
540 const union tgsi_exec_channel
*src
)
542 dst
->u
[0] = src
->u
[0];
543 dst
->u
[1] = src
->u
[1];
544 dst
->u
[2] = src
->u
[2];
545 dst
->u
[3] = src
->u
[3];
549 micro_rcp(union tgsi_exec_channel
*dst
,
550 const union tgsi_exec_channel
*src
)
552 #if 0 /* for debugging */
553 assert(src
->f
[0] != 0.0f
);
554 assert(src
->f
[1] != 0.0f
);
555 assert(src
->f
[2] != 0.0f
);
556 assert(src
->f
[3] != 0.0f
);
558 dst
->f
[0] = 1.0f
/ src
->f
[0];
559 dst
->f
[1] = 1.0f
/ src
->f
[1];
560 dst
->f
[2] = 1.0f
/ src
->f
[2];
561 dst
->f
[3] = 1.0f
/ src
->f
[3];
565 micro_rnd(union tgsi_exec_channel
*dst
,
566 const union tgsi_exec_channel
*src
)
568 dst
->f
[0] = _mesa_roundevenf(src
->f
[0]);
569 dst
->f
[1] = _mesa_roundevenf(src
->f
[1]);
570 dst
->f
[2] = _mesa_roundevenf(src
->f
[2]);
571 dst
->f
[3] = _mesa_roundevenf(src
->f
[3]);
575 micro_rsq(union tgsi_exec_channel
*dst
,
576 const union tgsi_exec_channel
*src
)
578 #if 0 /* for debugging */
579 assert(src
->f
[0] != 0.0f
);
580 assert(src
->f
[1] != 0.0f
);
581 assert(src
->f
[2] != 0.0f
);
582 assert(src
->f
[3] != 0.0f
);
584 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
585 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
586 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
587 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
591 micro_sqrt(union tgsi_exec_channel
*dst
,
592 const union tgsi_exec_channel
*src
)
594 dst
->f
[0] = sqrtf(src
->f
[0]);
595 dst
->f
[1] = sqrtf(src
->f
[1]);
596 dst
->f
[2] = sqrtf(src
->f
[2]);
597 dst
->f
[3] = sqrtf(src
->f
[3]);
601 micro_seq(union tgsi_exec_channel
*dst
,
602 const union tgsi_exec_channel
*src0
,
603 const union tgsi_exec_channel
*src1
)
605 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
606 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
607 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
608 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
612 micro_sge(union tgsi_exec_channel
*dst
,
613 const union tgsi_exec_channel
*src0
,
614 const union tgsi_exec_channel
*src1
)
616 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
617 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
618 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
619 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
623 micro_sgn(union tgsi_exec_channel
*dst
,
624 const union tgsi_exec_channel
*src
)
626 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
627 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
628 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
629 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
633 micro_isgn(union tgsi_exec_channel
*dst
,
634 const union tgsi_exec_channel
*src
)
636 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
637 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
638 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
639 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
643 micro_sgt(union tgsi_exec_channel
*dst
,
644 const union tgsi_exec_channel
*src0
,
645 const union tgsi_exec_channel
*src1
)
647 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
648 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
649 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
650 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
654 micro_sin(union tgsi_exec_channel
*dst
,
655 const union tgsi_exec_channel
*src
)
657 dst
->f
[0] = sinf(src
->f
[0]);
658 dst
->f
[1] = sinf(src
->f
[1]);
659 dst
->f
[2] = sinf(src
->f
[2]);
660 dst
->f
[3] = sinf(src
->f
[3]);
664 micro_sle(union tgsi_exec_channel
*dst
,
665 const union tgsi_exec_channel
*src0
,
666 const union tgsi_exec_channel
*src1
)
668 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
669 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
670 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
671 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
675 micro_slt(union tgsi_exec_channel
*dst
,
676 const union tgsi_exec_channel
*src0
,
677 const union tgsi_exec_channel
*src1
)
679 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
680 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
681 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
682 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
686 micro_sne(union tgsi_exec_channel
*dst
,
687 const union tgsi_exec_channel
*src0
,
688 const union tgsi_exec_channel
*src1
)
690 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
691 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
692 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
693 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
697 micro_trunc(union tgsi_exec_channel
*dst
,
698 const union tgsi_exec_channel
*src
)
700 dst
->f
[0] = truncf(src
->f
[0]);
701 dst
->f
[1] = truncf(src
->f
[1]);
702 dst
->f
[2] = truncf(src
->f
[2]);
703 dst
->f
[3] = truncf(src
->f
[3]);
707 micro_u2d(union tgsi_double_channel
*dst
,
708 const union tgsi_exec_channel
*src
)
710 dst
->d
[0] = (double)src
->u
[0];
711 dst
->d
[1] = (double)src
->u
[1];
712 dst
->d
[2] = (double)src
->u
[2];
713 dst
->d
[3] = (double)src
->u
[3];
717 micro_i64abs(union tgsi_double_channel
*dst
,
718 const union tgsi_double_channel
*src
)
720 dst
->i64
[0] = src
->i64
[0] >= 0.0 ? src
->i64
[0] : -src
->i64
[0];
721 dst
->i64
[1] = src
->i64
[1] >= 0.0 ? src
->i64
[1] : -src
->i64
[1];
722 dst
->i64
[2] = src
->i64
[2] >= 0.0 ? src
->i64
[2] : -src
->i64
[2];
723 dst
->i64
[3] = src
->i64
[3] >= 0.0 ? src
->i64
[3] : -src
->i64
[3];
727 micro_i64sgn(union tgsi_double_channel
*dst
,
728 const union tgsi_double_channel
*src
)
730 dst
->i64
[0] = src
->i64
[0] < 0 ? -1 : src
->i64
[0] > 0 ? 1 : 0;
731 dst
->i64
[1] = src
->i64
[1] < 0 ? -1 : src
->i64
[1] > 0 ? 1 : 0;
732 dst
->i64
[2] = src
->i64
[2] < 0 ? -1 : src
->i64
[2] > 0 ? 1 : 0;
733 dst
->i64
[3] = src
->i64
[3] < 0 ? -1 : src
->i64
[3] > 0 ? 1 : 0;
737 micro_i64neg(union tgsi_double_channel
*dst
,
738 const union tgsi_double_channel
*src
)
740 dst
->i64
[0] = -src
->i64
[0];
741 dst
->i64
[1] = -src
->i64
[1];
742 dst
->i64
[2] = -src
->i64
[2];
743 dst
->i64
[3] = -src
->i64
[3];
747 micro_u64seq(union tgsi_double_channel
*dst
,
748 const union tgsi_double_channel
*src
)
750 dst
->u
[0][0] = src
[0].u64
[0] == src
[1].u64
[0] ? ~0U : 0U;
751 dst
->u
[1][0] = src
[0].u64
[1] == src
[1].u64
[1] ? ~0U : 0U;
752 dst
->u
[2][0] = src
[0].u64
[2] == src
[1].u64
[2] ? ~0U : 0U;
753 dst
->u
[3][0] = src
[0].u64
[3] == src
[1].u64
[3] ? ~0U : 0U;
757 micro_u64sne(union tgsi_double_channel
*dst
,
758 const union tgsi_double_channel
*src
)
760 dst
->u
[0][0] = src
[0].u64
[0] != src
[1].u64
[0] ? ~0U : 0U;
761 dst
->u
[1][0] = src
[0].u64
[1] != src
[1].u64
[1] ? ~0U : 0U;
762 dst
->u
[2][0] = src
[0].u64
[2] != src
[1].u64
[2] ? ~0U : 0U;
763 dst
->u
[3][0] = src
[0].u64
[3] != src
[1].u64
[3] ? ~0U : 0U;
767 micro_i64slt(union tgsi_double_channel
*dst
,
768 const union tgsi_double_channel
*src
)
770 dst
->u
[0][0] = src
[0].i64
[0] < src
[1].i64
[0] ? ~0U : 0U;
771 dst
->u
[1][0] = src
[0].i64
[1] < src
[1].i64
[1] ? ~0U : 0U;
772 dst
->u
[2][0] = src
[0].i64
[2] < src
[1].i64
[2] ? ~0U : 0U;
773 dst
->u
[3][0] = src
[0].i64
[3] < src
[1].i64
[3] ? ~0U : 0U;
777 micro_u64slt(union tgsi_double_channel
*dst
,
778 const union tgsi_double_channel
*src
)
780 dst
->u
[0][0] = src
[0].u64
[0] < src
[1].u64
[0] ? ~0U : 0U;
781 dst
->u
[1][0] = src
[0].u64
[1] < src
[1].u64
[1] ? ~0U : 0U;
782 dst
->u
[2][0] = src
[0].u64
[2] < src
[1].u64
[2] ? ~0U : 0U;
783 dst
->u
[3][0] = src
[0].u64
[3] < src
[1].u64
[3] ? ~0U : 0U;
787 micro_i64sge(union tgsi_double_channel
*dst
,
788 const union tgsi_double_channel
*src
)
790 dst
->u
[0][0] = src
[0].i64
[0] >= src
[1].i64
[0] ? ~0U : 0U;
791 dst
->u
[1][0] = src
[0].i64
[1] >= src
[1].i64
[1] ? ~0U : 0U;
792 dst
->u
[2][0] = src
[0].i64
[2] >= src
[1].i64
[2] ? ~0U : 0U;
793 dst
->u
[3][0] = src
[0].i64
[3] >= src
[1].i64
[3] ? ~0U : 0U;
797 micro_u64sge(union tgsi_double_channel
*dst
,
798 const union tgsi_double_channel
*src
)
800 dst
->u
[0][0] = src
[0].u64
[0] >= src
[1].u64
[0] ? ~0U : 0U;
801 dst
->u
[1][0] = src
[0].u64
[1] >= src
[1].u64
[1] ? ~0U : 0U;
802 dst
->u
[2][0] = src
[0].u64
[2] >= src
[1].u64
[2] ? ~0U : 0U;
803 dst
->u
[3][0] = src
[0].u64
[3] >= src
[1].u64
[3] ? ~0U : 0U;
807 micro_u64max(union tgsi_double_channel
*dst
,
808 const union tgsi_double_channel
*src
)
810 dst
->u64
[0] = src
[0].u64
[0] > src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
811 dst
->u64
[1] = src
[0].u64
[1] > src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
812 dst
->u64
[2] = src
[0].u64
[2] > src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
813 dst
->u64
[3] = src
[0].u64
[3] > src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
817 micro_i64max(union tgsi_double_channel
*dst
,
818 const union tgsi_double_channel
*src
)
820 dst
->i64
[0] = src
[0].i64
[0] > src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
821 dst
->i64
[1] = src
[0].i64
[1] > src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
822 dst
->i64
[2] = src
[0].i64
[2] > src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
823 dst
->i64
[3] = src
[0].i64
[3] > src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
827 micro_u64min(union tgsi_double_channel
*dst
,
828 const union tgsi_double_channel
*src
)
830 dst
->u64
[0] = src
[0].u64
[0] < src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
831 dst
->u64
[1] = src
[0].u64
[1] < src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
832 dst
->u64
[2] = src
[0].u64
[2] < src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
833 dst
->u64
[3] = src
[0].u64
[3] < src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
837 micro_i64min(union tgsi_double_channel
*dst
,
838 const union tgsi_double_channel
*src
)
840 dst
->i64
[0] = src
[0].i64
[0] < src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
841 dst
->i64
[1] = src
[0].i64
[1] < src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
842 dst
->i64
[2] = src
[0].i64
[2] < src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
843 dst
->i64
[3] = src
[0].i64
[3] < src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
847 micro_u64add(union tgsi_double_channel
*dst
,
848 const union tgsi_double_channel
*src
)
850 dst
->u64
[0] = src
[0].u64
[0] + src
[1].u64
[0];
851 dst
->u64
[1] = src
[0].u64
[1] + src
[1].u64
[1];
852 dst
->u64
[2] = src
[0].u64
[2] + src
[1].u64
[2];
853 dst
->u64
[3] = src
[0].u64
[3] + src
[1].u64
[3];
857 micro_u64mul(union tgsi_double_channel
*dst
,
858 const union tgsi_double_channel
*src
)
860 dst
->u64
[0] = src
[0].u64
[0] * src
[1].u64
[0];
861 dst
->u64
[1] = src
[0].u64
[1] * src
[1].u64
[1];
862 dst
->u64
[2] = src
[0].u64
[2] * src
[1].u64
[2];
863 dst
->u64
[3] = src
[0].u64
[3] * src
[1].u64
[3];
867 micro_u64div(union tgsi_double_channel
*dst
,
868 const union tgsi_double_channel
*src
)
870 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] / src
[1].u64
[0] : ~0ull;
871 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] / src
[1].u64
[1] : ~0ull;
872 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] / src
[1].u64
[2] : ~0ull;
873 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] / src
[1].u64
[3] : ~0ull;
877 micro_i64div(union tgsi_double_channel
*dst
,
878 const union tgsi_double_channel
*src
)
880 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] / src
[1].i64
[0] : 0;
881 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] / src
[1].i64
[1] : 0;
882 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] / src
[1].i64
[2] : 0;
883 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] / src
[1].i64
[3] : 0;
887 micro_u64mod(union tgsi_double_channel
*dst
,
888 const union tgsi_double_channel
*src
)
890 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] % src
[1].u64
[0] : ~0ull;
891 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] % src
[1].u64
[1] : ~0ull;
892 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] % src
[1].u64
[2] : ~0ull;
893 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] % src
[1].u64
[3] : ~0ull;
897 micro_i64mod(union tgsi_double_channel
*dst
,
898 const union tgsi_double_channel
*src
)
900 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] % src
[1].i64
[0] : ~0ll;
901 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] % src
[1].i64
[1] : ~0ll;
902 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] % src
[1].i64
[2] : ~0ll;
903 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] % src
[1].i64
[3] : ~0ll;
907 micro_u64shl(union tgsi_double_channel
*dst
,
908 const union tgsi_double_channel
*src0
,
909 union tgsi_exec_channel
*src1
)
911 unsigned masked_count
;
912 masked_count
= src1
->u
[0] & 0x3f;
913 dst
->u64
[0] = src0
->u64
[0] << masked_count
;
914 masked_count
= src1
->u
[1] & 0x3f;
915 dst
->u64
[1] = src0
->u64
[1] << masked_count
;
916 masked_count
= src1
->u
[2] & 0x3f;
917 dst
->u64
[2] = src0
->u64
[2] << masked_count
;
918 masked_count
= src1
->u
[3] & 0x3f;
919 dst
->u64
[3] = src0
->u64
[3] << masked_count
;
923 micro_i64shr(union tgsi_double_channel
*dst
,
924 const union tgsi_double_channel
*src0
,
925 union tgsi_exec_channel
*src1
)
927 unsigned masked_count
;
928 masked_count
= src1
->u
[0] & 0x3f;
929 dst
->i64
[0] = src0
->i64
[0] >> masked_count
;
930 masked_count
= src1
->u
[1] & 0x3f;
931 dst
->i64
[1] = src0
->i64
[1] >> masked_count
;
932 masked_count
= src1
->u
[2] & 0x3f;
933 dst
->i64
[2] = src0
->i64
[2] >> masked_count
;
934 masked_count
= src1
->u
[3] & 0x3f;
935 dst
->i64
[3] = src0
->i64
[3] >> masked_count
;
939 micro_u64shr(union tgsi_double_channel
*dst
,
940 const union tgsi_double_channel
*src0
,
941 union tgsi_exec_channel
*src1
)
943 unsigned masked_count
;
944 masked_count
= src1
->u
[0] & 0x3f;
945 dst
->u64
[0] = src0
->u64
[0] >> masked_count
;
946 masked_count
= src1
->u
[1] & 0x3f;
947 dst
->u64
[1] = src0
->u64
[1] >> masked_count
;
948 masked_count
= src1
->u
[2] & 0x3f;
949 dst
->u64
[2] = src0
->u64
[2] >> masked_count
;
950 masked_count
= src1
->u
[3] & 0x3f;
951 dst
->u64
[3] = src0
->u64
[3] >> masked_count
;
954 enum tgsi_exec_datatype
{
955 TGSI_EXEC_DATA_FLOAT
,
958 TGSI_EXEC_DATA_DOUBLE
,
959 TGSI_EXEC_DATA_INT64
,
960 TGSI_EXEC_DATA_UINT64
,
964 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
966 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
967 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
968 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
969 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
970 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
971 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
972 #define TEMP_PRIMITIVE_S1_I TGSI_EXEC_TEMP_PRIMITIVE_S1_I
973 #define TEMP_PRIMITIVE_S1_C TGSI_EXEC_TEMP_PRIMITIVE_S1_C
974 #define TEMP_PRIMITIVE_S2_I TGSI_EXEC_TEMP_PRIMITIVE_S2_I
975 #define TEMP_PRIMITIVE_S2_C TGSI_EXEC_TEMP_PRIMITIVE_S2_C
976 #define TEMP_PRIMITIVE_S3_I TGSI_EXEC_TEMP_PRIMITIVE_S3_I
977 #define TEMP_PRIMITIVE_S3_C TGSI_EXEC_TEMP_PRIMITIVE_S3_C
979 static const struct {
982 } temp_prim_idxs
[] = {
983 { TEMP_PRIMITIVE_I
, TEMP_PRIMITIVE_C
},
984 { TEMP_PRIMITIVE_S1_I
, TEMP_PRIMITIVE_S1_C
},
985 { TEMP_PRIMITIVE_S2_I
, TEMP_PRIMITIVE_S2_C
},
986 { TEMP_PRIMITIVE_S3_I
, TEMP_PRIMITIVE_S3_C
},
989 /** The execution mask depends on the conditional mask and the loop mask */
990 #define UPDATE_EXEC_MASK(MACH) \
991 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
994 static const union tgsi_exec_channel ZeroVec
=
995 { { 0.0, 0.0, 0.0, 0.0 } };
997 static const union tgsi_exec_channel OneVec
= {
998 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
1001 static const union tgsi_exec_channel P128Vec
= {
1002 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
1005 static const union tgsi_exec_channel M128Vec
= {
1006 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
1011 * Assert that none of the float values in 'chan' are infinite or NaN.
1012 * NaN and Inf may occur normally during program execution and should
1013 * not lead to crashes, etc. But when debugging, it's helpful to catch
1017 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
1019 assert(!util_is_inf_or_nan((chan
)->f
[0]));
1020 assert(!util_is_inf_or_nan((chan
)->f
[1]));
1021 assert(!util_is_inf_or_nan((chan
)->f
[2]));
1022 assert(!util_is_inf_or_nan((chan
)->f
[3]));
1028 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
1030 debug_printf("%s = {%f, %f, %f, %f}\n",
1031 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
1038 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
1040 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
1042 debug_printf("Temp[%u] =\n", index
);
1043 for (i
= 0; i
< 4; i
++) {
1044 debug_printf(" %c: { %f, %f, %f, %f }\n",
1056 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
1059 const unsigned *buf_sizes
)
1063 for (i
= 0; i
< num_bufs
; i
++) {
1064 mach
->Consts
[i
] = bufs
[i
];
1065 mach
->ConstsSize
[i
] = buf_sizes
[i
];
1070 * Initialize machine state by expanding tokens to full instructions,
1071 * allocating temporary storage, setting up constants, etc.
1072 * After this, we can call tgsi_exec_machine_run() many times.
1075 tgsi_exec_machine_bind_shader(
1076 struct tgsi_exec_machine
*mach
,
1077 const struct tgsi_token
*tokens
,
1078 struct tgsi_sampler
*sampler
,
1079 struct tgsi_image
*image
,
1080 struct tgsi_buffer
*buffer
)
1083 struct tgsi_parse_context parse
;
1084 struct tgsi_full_instruction
*instructions
;
1085 struct tgsi_full_declaration
*declarations
;
1086 uint maxInstructions
= 10, numInstructions
= 0;
1087 uint maxDeclarations
= 10, numDeclarations
= 0;
1090 tgsi_dump(tokens
, 0);
1096 mach
->Tokens
= tokens
;
1097 mach
->Sampler
= sampler
;
1098 mach
->Image
= image
;
1099 mach
->Buffer
= buffer
;
1102 /* unbind and free all */
1103 FREE(mach
->Declarations
);
1104 mach
->Declarations
= NULL
;
1105 mach
->NumDeclarations
= 0;
1107 FREE(mach
->Instructions
);
1108 mach
->Instructions
= NULL
;
1109 mach
->NumInstructions
= 0;
1114 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
1115 if (k
!= TGSI_PARSE_OK
) {
1116 debug_printf( "Problem parsing!\n" );
1121 mach
->NumOutputs
= 0;
1123 for (k
= 0; k
< TGSI_SEMANTIC_COUNT
; k
++)
1124 mach
->SysSemanticToIndex
[k
] = -1;
1126 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
&&
1127 !mach
->UsedGeometryShader
) {
1128 struct tgsi_exec_vector
*inputs
;
1129 struct tgsi_exec_vector
*outputs
;
1131 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1132 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
1138 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1139 TGSI_MAX_TOTAL_VERTICES
, 16);
1146 align_free(mach
->Inputs
);
1147 align_free(mach
->Outputs
);
1149 mach
->Inputs
= inputs
;
1150 mach
->Outputs
= outputs
;
1151 mach
->UsedGeometryShader
= TRUE
;
1154 declarations
= (struct tgsi_full_declaration
*)
1155 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
1157 if (!declarations
) {
1161 instructions
= (struct tgsi_full_instruction
*)
1162 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
1164 if (!instructions
) {
1165 FREE( declarations
);
1169 while( !tgsi_parse_end_of_tokens( &parse
) ) {
1172 tgsi_parse_token( &parse
);
1173 switch( parse
.FullToken
.Token
.Type
) {
1174 case TGSI_TOKEN_TYPE_DECLARATION
:
1175 /* save expanded declaration */
1176 if (numDeclarations
== maxDeclarations
) {
1177 declarations
= REALLOC(declarations
,
1179 * sizeof(struct tgsi_full_declaration
),
1180 (maxDeclarations
+ 10)
1181 * sizeof(struct tgsi_full_declaration
));
1182 maxDeclarations
+= 10;
1184 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
1186 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
1187 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
1192 else if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1193 const struct tgsi_full_declaration
*decl
= &parse
.FullToken
.FullDeclaration
;
1194 mach
->SysSemanticToIndex
[decl
->Semantic
.Name
] = decl
->Range
.First
;
1197 memcpy(declarations
+ numDeclarations
,
1198 &parse
.FullToken
.FullDeclaration
,
1199 sizeof(declarations
[0]));
1203 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1205 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
1206 assert( size
<= 4 );
1207 if (mach
->ImmLimit
>= mach
->ImmsReserved
) {
1208 unsigned newReserved
= mach
->ImmsReserved
? 2 * mach
->ImmsReserved
: 128;
1209 float4
*imms
= REALLOC(mach
->Imms
, mach
->ImmsReserved
, newReserved
* sizeof(float4
));
1211 mach
->ImmsReserved
= newReserved
;
1214 debug_printf("Unable to (re)allocate space for immidiate constants\n");
1219 for( i
= 0; i
< size
; i
++ ) {
1220 mach
->Imms
[mach
->ImmLimit
][i
] =
1221 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
1223 mach
->ImmLimit
+= 1;
1227 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1229 /* save expanded instruction */
1230 if (numInstructions
== maxInstructions
) {
1231 instructions
= REALLOC(instructions
,
1233 * sizeof(struct tgsi_full_instruction
),
1234 (maxInstructions
+ 10)
1235 * sizeof(struct tgsi_full_instruction
));
1236 maxInstructions
+= 10;
1239 memcpy(instructions
+ numInstructions
,
1240 &parse
.FullToken
.FullInstruction
,
1241 sizeof(instructions
[0]));
1246 case TGSI_TOKEN_TYPE_PROPERTY
:
1247 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
1248 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1249 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1258 tgsi_parse_free (&parse
);
1260 FREE(mach
->Declarations
);
1261 mach
->Declarations
= declarations
;
1262 mach
->NumDeclarations
= numDeclarations
;
1264 FREE(mach
->Instructions
);
1265 mach
->Instructions
= instructions
;
1266 mach
->NumInstructions
= numInstructions
;
1270 struct tgsi_exec_machine
*
1271 tgsi_exec_machine_create(enum pipe_shader_type shader_type
)
1273 struct tgsi_exec_machine
*mach
;
1276 mach
= align_malloc( sizeof *mach
, 16 );
1280 memset(mach
, 0, sizeof(*mach
));
1282 mach
->ShaderType
= shader_type
;
1283 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1284 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1286 if (shader_type
!= PIPE_SHADER_COMPUTE
) {
1287 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1288 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1289 if (!mach
->Inputs
|| !mach
->Outputs
)
1293 if (shader_type
== PIPE_SHADER_FRAGMENT
) {
1294 mach
->InputSampleOffsetApply
= align_malloc(sizeof(apply_sample_offset_func
) * PIPE_MAX_SHADER_INPUTS
, 16);
1295 if (!mach
->InputSampleOffsetApply
)
1300 /* silence warnings */
1309 align_free(mach
->InputSampleOffsetApply
);
1310 align_free(mach
->Inputs
);
1311 align_free(mach
->Outputs
);
1319 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1322 FREE(mach
->Instructions
);
1323 FREE(mach
->Declarations
);
1326 align_free(mach
->InputSampleOffsetApply
);
1327 align_free(mach
->Inputs
);
1328 align_free(mach
->Outputs
);
1335 micro_add(union tgsi_exec_channel
*dst
,
1336 const union tgsi_exec_channel
*src0
,
1337 const union tgsi_exec_channel
*src1
)
1339 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1340 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1341 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1342 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1347 union tgsi_exec_channel
*dst
,
1348 const union tgsi_exec_channel
*src0
,
1349 const union tgsi_exec_channel
*src1
)
1351 if (src1
->f
[0] != 0) {
1352 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1354 if (src1
->f
[1] != 0) {
1355 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1357 if (src1
->f
[2] != 0) {
1358 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1360 if (src1
->f
[3] != 0) {
1361 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1367 union tgsi_exec_channel
*dst
,
1368 const union tgsi_exec_channel
*src0
,
1369 const union tgsi_exec_channel
*src1
,
1370 const union tgsi_exec_channel
*src2
,
1371 const union tgsi_exec_channel
*src3
)
1373 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1374 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1375 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1376 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1380 micro_max(union tgsi_exec_channel
*dst
,
1381 const union tgsi_exec_channel
*src0
,
1382 const union tgsi_exec_channel
*src1
)
1384 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1385 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1386 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1387 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1391 micro_min(union tgsi_exec_channel
*dst
,
1392 const union tgsi_exec_channel
*src0
,
1393 const union tgsi_exec_channel
*src1
)
1395 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1396 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1397 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1398 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1402 micro_mul(union tgsi_exec_channel
*dst
,
1403 const union tgsi_exec_channel
*src0
,
1404 const union tgsi_exec_channel
*src1
)
1406 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1407 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1408 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1409 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1414 union tgsi_exec_channel
*dst
,
1415 const union tgsi_exec_channel
*src
)
1417 dst
->f
[0] = -src
->f
[0];
1418 dst
->f
[1] = -src
->f
[1];
1419 dst
->f
[2] = -src
->f
[2];
1420 dst
->f
[3] = -src
->f
[3];
1425 union tgsi_exec_channel
*dst
,
1426 const union tgsi_exec_channel
*src0
,
1427 const union tgsi_exec_channel
*src1
)
1430 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1431 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1432 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1433 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1435 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1436 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1437 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1438 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1443 micro_ldexp(union tgsi_exec_channel
*dst
,
1444 const union tgsi_exec_channel
*src0
,
1445 const union tgsi_exec_channel
*src1
)
1447 dst
->f
[0] = ldexpf(src0
->f
[0], src1
->i
[0]);
1448 dst
->f
[1] = ldexpf(src0
->f
[1], src1
->i
[1]);
1449 dst
->f
[2] = ldexpf(src0
->f
[2], src1
->i
[2]);
1450 dst
->f
[3] = ldexpf(src0
->f
[3], src1
->i
[3]);
1454 micro_sub(union tgsi_exec_channel
*dst
,
1455 const union tgsi_exec_channel
*src0
,
1456 const union tgsi_exec_channel
*src1
)
1458 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1459 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1460 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1461 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1465 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1468 const union tgsi_exec_channel
*index
,
1469 const union tgsi_exec_channel
*index2D
,
1470 union tgsi_exec_channel
*chan
)
1474 assert(swizzle
< 4);
1477 case TGSI_FILE_CONSTANT
:
1478 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1479 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1480 assert(mach
->Consts
[index2D
->i
[i
]]);
1482 if (index
->i
[i
] < 0) {
1485 /* NOTE: copying the const value as a uint instead of float */
1486 const uint constbuf
= index2D
->i
[i
];
1487 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1488 const int pos
= index
->i
[i
] * 4 + swizzle
;
1489 /* const buffer bounds check */
1490 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1492 /* Debug: print warning */
1493 static int count
= 0;
1495 debug_printf("TGSI Exec: const buffer index %d"
1496 " out of bounds\n", pos
);
1501 chan
->u
[i
] = buf
[pos
];
1506 case TGSI_FILE_INPUT
:
1507 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1509 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1510 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1511 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1512 index2D->i[i], index->i[i]);
1514 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1516 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1517 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1521 case TGSI_FILE_SYSTEM_VALUE
:
1522 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1523 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1527 case TGSI_FILE_TEMPORARY
:
1528 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1529 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1530 assert(index2D
->i
[i
] == 0);
1532 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1536 case TGSI_FILE_IMMEDIATE
:
1537 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1538 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1539 assert(index2D
->i
[i
] == 0);
1541 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1545 case TGSI_FILE_ADDRESS
:
1546 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1547 assert(index
->i
[i
] >= 0);
1548 assert(index2D
->i
[i
] == 0);
1550 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1554 case TGSI_FILE_OUTPUT
:
1555 /* vertex/fragment output vars can be read too */
1556 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1557 assert(index
->i
[i
] >= 0);
1558 assert(index2D
->i
[i
] == 0);
1560 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1566 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1573 get_index_registers(const struct tgsi_exec_machine
*mach
,
1574 const struct tgsi_full_src_register
*reg
,
1575 union tgsi_exec_channel
*index
,
1576 union tgsi_exec_channel
*index2D
)
1580 /* We start with a direct index into a register file.
1584 * file = Register.File
1585 * [1] = Register.Index
1590 index
->i
[3] = reg
->Register
.Index
;
1592 /* There is an extra source register that indirectly subscripts
1593 * a register file. The direct index now becomes an offset
1594 * that is being added to the indirect register.
1598 * ind = Indirect.File
1599 * [2] = Indirect.Index
1600 * .x = Indirect.SwizzleX
1602 if (reg
->Register
.Indirect
) {
1603 union tgsi_exec_channel index2
;
1604 union tgsi_exec_channel indir_index
;
1605 const uint execmask
= mach
->ExecMask
;
1608 /* which address register (always zero now) */
1612 index2
.i
[3] = reg
->Indirect
.Index
;
1613 /* get current value of address register[swizzle] */
1614 swizzle
= reg
->Indirect
.Swizzle
;
1615 fetch_src_file_channel(mach
,
1622 /* add value of address register to the offset */
1623 index
->i
[0] += indir_index
.i
[0];
1624 index
->i
[1] += indir_index
.i
[1];
1625 index
->i
[2] += indir_index
.i
[2];
1626 index
->i
[3] += indir_index
.i
[3];
1628 /* for disabled execution channels, zero-out the index to
1629 * avoid using a potential garbage value.
1631 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1632 if ((execmask
& (1 << i
)) == 0)
1637 /* There is an extra source register that is a second
1638 * subscript to a register file. Effectively it means that
1639 * the register file is actually a 2D array of registers.
1643 * [3] = Dimension.Index
1645 if (reg
->Register
.Dimension
) {
1649 index2D
->i
[3] = reg
->Dimension
.Index
;
1651 /* Again, the second subscript index can be addressed indirectly
1652 * identically to the first one.
1653 * Nothing stops us from indirectly addressing the indirect register,
1654 * but there is no need for that, so we won't exercise it.
1656 * file[ind[4].y+3][1],
1658 * ind = DimIndirect.File
1659 * [4] = DimIndirect.Index
1660 * .y = DimIndirect.SwizzleX
1662 if (reg
->Dimension
.Indirect
) {
1663 union tgsi_exec_channel index2
;
1664 union tgsi_exec_channel indir_index
;
1665 const uint execmask
= mach
->ExecMask
;
1671 index2
.i
[3] = reg
->DimIndirect
.Index
;
1673 swizzle
= reg
->DimIndirect
.Swizzle
;
1674 fetch_src_file_channel(mach
,
1675 reg
->DimIndirect
.File
,
1681 index2D
->i
[0] += indir_index
.i
[0];
1682 index2D
->i
[1] += indir_index
.i
[1];
1683 index2D
->i
[2] += indir_index
.i
[2];
1684 index2D
->i
[3] += indir_index
.i
[3];
1686 /* for disabled execution channels, zero-out the index to
1687 * avoid using a potential garbage value.
1689 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1690 if ((execmask
& (1 << i
)) == 0) {
1696 /* If by any chance there was a need for a 3D array of register
1697 * files, we would have to check whether Dimension is followed
1698 * by a dimension register and continue the saga.
1710 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1711 union tgsi_exec_channel
*chan
,
1712 const struct tgsi_full_src_register
*reg
,
1713 const uint chan_index
)
1715 union tgsi_exec_channel index
;
1716 union tgsi_exec_channel index2D
;
1719 get_index_registers(mach
, reg
, &index
, &index2D
);
1722 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1723 fetch_src_file_channel(mach
,
1732 fetch_source(const struct tgsi_exec_machine
*mach
,
1733 union tgsi_exec_channel
*chan
,
1734 const struct tgsi_full_src_register
*reg
,
1735 const uint chan_index
,
1736 enum tgsi_exec_datatype src_datatype
)
1738 fetch_source_d(mach
, chan
, reg
, chan_index
);
1740 if (reg
->Register
.Absolute
) {
1741 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1742 micro_abs(chan
, chan
);
1744 micro_iabs(chan
, chan
);
1748 if (reg
->Register
.Negate
) {
1749 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1750 micro_neg(chan
, chan
);
1752 micro_ineg(chan
, chan
);
1757 static union tgsi_exec_channel
*
1758 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1759 const union tgsi_exec_channel
*chan
,
1760 const struct tgsi_full_dst_register
*reg
,
1762 enum tgsi_exec_datatype dst_datatype
)
1764 static union tgsi_exec_channel null
;
1765 union tgsi_exec_channel
*dst
;
1766 union tgsi_exec_channel index2D
;
1767 int offset
= 0; /* indirection offset */
1771 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1772 check_inf_or_nan(chan
);
1775 /* There is an extra source register that indirectly subscripts
1776 * a register file. The direct index now becomes an offset
1777 * that is being added to the indirect register.
1781 * ind = Indirect.File
1782 * [2] = Indirect.Index
1783 * .x = Indirect.SwizzleX
1785 if (reg
->Register
.Indirect
) {
1786 union tgsi_exec_channel index
;
1787 union tgsi_exec_channel indir_index
;
1790 /* which address register (always zero for now) */
1794 index
.i
[3] = reg
->Indirect
.Index
;
1796 /* get current value of address register[swizzle] */
1797 swizzle
= reg
->Indirect
.Swizzle
;
1799 /* fetch values from the address/indirection register */
1800 fetch_src_file_channel(mach
,
1807 /* save indirection offset */
1808 offset
= indir_index
.i
[0];
1811 /* There is an extra source register that is a second
1812 * subscript to a register file. Effectively it means that
1813 * the register file is actually a 2D array of registers.
1817 * [3] = Dimension.Index
1819 if (reg
->Register
.Dimension
) {
1823 index2D
.i
[3] = reg
->Dimension
.Index
;
1825 /* Again, the second subscript index can be addressed indirectly
1826 * identically to the first one.
1827 * Nothing stops us from indirectly addressing the indirect register,
1828 * but there is no need for that, so we won't exercise it.
1830 * file[ind[4].y+3][1],
1832 * ind = DimIndirect.File
1833 * [4] = DimIndirect.Index
1834 * .y = DimIndirect.SwizzleX
1836 if (reg
->Dimension
.Indirect
) {
1837 union tgsi_exec_channel index2
;
1838 union tgsi_exec_channel indir_index
;
1839 const uint execmask
= mach
->ExecMask
;
1846 index2
.i
[3] = reg
->DimIndirect
.Index
;
1848 swizzle
= reg
->DimIndirect
.Swizzle
;
1849 fetch_src_file_channel(mach
,
1850 reg
->DimIndirect
.File
,
1856 index2D
.i
[0] += indir_index
.i
[0];
1857 index2D
.i
[1] += indir_index
.i
[1];
1858 index2D
.i
[2] += indir_index
.i
[2];
1859 index2D
.i
[3] += indir_index
.i
[3];
1861 /* for disabled execution channels, zero-out the index to
1862 * avoid using a potential garbage value.
1864 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1865 if ((execmask
& (1 << i
)) == 0) {
1871 /* If by any chance there was a need for a 3D array of register
1872 * files, we would have to check whether Dimension is followed
1873 * by a dimension register and continue the saga.
1882 switch (reg
->Register
.File
) {
1883 case TGSI_FILE_NULL
:
1887 case TGSI_FILE_OUTPUT
:
1888 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1889 + reg
->Register
.Index
;
1890 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1892 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1893 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1894 reg
->Register
.Index
);
1895 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
1896 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1897 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1898 if (execmask
& (1 << i
))
1899 debug_printf("%f, ", chan
->f
[i
]);
1900 debug_printf(")\n");
1905 case TGSI_FILE_TEMPORARY
:
1906 index
= reg
->Register
.Index
;
1907 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1908 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1911 case TGSI_FILE_ADDRESS
:
1912 index
= reg
->Register
.Index
;
1913 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1925 store_dest_double(struct tgsi_exec_machine
*mach
,
1926 const union tgsi_exec_channel
*chan
,
1927 const struct tgsi_full_dst_register
*reg
,
1929 enum tgsi_exec_datatype dst_datatype
)
1931 union tgsi_exec_channel
*dst
;
1932 const uint execmask
= mach
->ExecMask
;
1935 dst
= store_dest_dstret(mach
, chan
, reg
, chan_index
, dst_datatype
);
1940 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1941 if (execmask
& (1 << i
))
1942 dst
->i
[i
] = chan
->i
[i
];
1946 store_dest(struct tgsi_exec_machine
*mach
,
1947 const union tgsi_exec_channel
*chan
,
1948 const struct tgsi_full_dst_register
*reg
,
1949 const struct tgsi_full_instruction
*inst
,
1951 enum tgsi_exec_datatype dst_datatype
)
1953 union tgsi_exec_channel
*dst
;
1954 const uint execmask
= mach
->ExecMask
;
1957 dst
= store_dest_dstret(mach
, chan
, reg
, chan_index
, dst_datatype
);
1961 if (!inst
->Instruction
.Saturate
) {
1962 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1963 if (execmask
& (1 << i
))
1964 dst
->i
[i
] = chan
->i
[i
];
1967 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1968 if (execmask
& (1 << i
)) {
1969 if (chan
->f
[i
] < 0.0f
)
1971 else if (chan
->f
[i
] > 1.0f
)
1974 dst
->i
[i
] = chan
->i
[i
];
1979 #define FETCH(VAL,INDEX,CHAN)\
1980 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1982 #define IFETCH(VAL,INDEX,CHAN)\
1983 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1987 * Execute ARB-style KIL which is predicated by a src register.
1988 * Kill fragment if any of the four values is less than zero.
1991 exec_kill_if(struct tgsi_exec_machine
*mach
,
1992 const struct tgsi_full_instruction
*inst
)
1996 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1997 union tgsi_exec_channel r
[1];
1999 /* This mask stores component bits that were already tested. */
2002 for (chan_index
= 0; chan_index
< 4; chan_index
++)
2007 /* unswizzle channel */
2008 swizzle
= tgsi_util_get_full_src_register_swizzle (
2012 /* check if the component has not been already tested */
2013 if (uniquemask
& (1 << swizzle
))
2015 uniquemask
|= 1 << swizzle
;
2017 FETCH(&r
[0], 0, chan_index
);
2018 for (i
= 0; i
< 4; i
++)
2019 if (r
[0].f
[i
] < 0.0f
)
2023 /* restrict to fragments currently executing */
2024 kilmask
&= mach
->ExecMask
;
2026 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2030 * Unconditional fragment kill/discard.
2033 exec_kill(struct tgsi_exec_machine
*mach
)
2035 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2037 /* kill fragment for all fragments currently executing */
2038 kilmask
= mach
->ExecMask
;
2039 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2043 emit_vertex(struct tgsi_exec_machine
*mach
,
2044 const struct tgsi_full_instruction
*inst
)
2046 union tgsi_exec_channel r
[1];
2048 unsigned *prim_count
;
2049 /* FIXME: check for exec mask correctly
2051 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2052 if ((mach->ExecMask & (1 << i)))
2054 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2055 stream_id
= r
[0].u
[0];
2056 prim_count
= &mach
->Temps
[temp_prim_idxs
[stream_id
].idx
].xyzw
[temp_prim_idxs
[stream_id
].chan
].u
[0];
2057 if (mach
->ExecMask
) {
2058 if (mach
->Primitives
[stream_id
][*prim_count
] >= mach
->MaxOutputVertices
)
2061 if (mach
->Primitives
[stream_id
][*prim_count
] == 0)
2062 mach
->PrimitiveOffsets
[stream_id
][*prim_count
] = mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0];
2063 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
2064 mach
->Primitives
[stream_id
][*prim_count
]++;
2069 emit_primitive(struct tgsi_exec_machine
*mach
,
2070 const struct tgsi_full_instruction
*inst
)
2072 unsigned *prim_count
;
2073 union tgsi_exec_channel r
[1];
2074 unsigned stream_id
= 0;
2075 /* FIXME: check for exec mask correctly
2077 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2078 if ((mach->ExecMask & (1 << i)))
2081 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2082 stream_id
= r
[0].u
[0];
2084 prim_count
= &mach
->Temps
[temp_prim_idxs
[stream_id
].idx
].xyzw
[temp_prim_idxs
[stream_id
].chan
].u
[0];
2085 if (mach
->ExecMask
) {
2087 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
2088 mach
->Primitives
[stream_id
][*prim_count
] = 0;
2093 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
2095 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
2097 mach
->Primitives
[0][mach
->Temps
[temp_prim_idxs
[0].idx
].xyzw
[temp_prim_idxs
[0].chan
].u
[0]];
2098 if (emitted_verts
) {
2099 emit_primitive(mach
, NULL
);
2106 * Fetch four texture samples using STR texture coordinates.
2109 fetch_texel( struct tgsi_sampler
*sampler
,
2110 const unsigned sview_idx
,
2111 const unsigned sampler_idx
,
2112 const union tgsi_exec_channel
*s
,
2113 const union tgsi_exec_channel
*t
,
2114 const union tgsi_exec_channel
*p
,
2115 const union tgsi_exec_channel
*c0
,
2116 const union tgsi_exec_channel
*c1
,
2117 float derivs
[3][2][TGSI_QUAD_SIZE
],
2118 const int8_t offset
[3],
2119 enum tgsi_sampler_control control
,
2120 union tgsi_exec_channel
*r
,
2121 union tgsi_exec_channel
*g
,
2122 union tgsi_exec_channel
*b
,
2123 union tgsi_exec_channel
*a
)
2126 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2128 /* FIXME: handle explicit derivs, offsets */
2129 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
2130 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
2132 for (j
= 0; j
< 4; j
++) {
2133 r
->f
[j
] = rgba
[0][j
];
2134 g
->f
[j
] = rgba
[1][j
];
2135 b
->f
[j
] = rgba
[2][j
];
2136 a
->f
[j
] = rgba
[3][j
];
2141 #define TEX_MODIFIER_NONE 0
2142 #define TEX_MODIFIER_PROJECTED 1
2143 #define TEX_MODIFIER_LOD_BIAS 2
2144 #define TEX_MODIFIER_EXPLICIT_LOD 3
2145 #define TEX_MODIFIER_LEVEL_ZERO 4
2146 #define TEX_MODIFIER_GATHER 5
2149 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
2152 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
2153 const struct tgsi_full_instruction
*inst
,
2156 if (inst
->Texture
.NumOffsets
== 1) {
2157 union tgsi_exec_channel index
;
2158 union tgsi_exec_channel offset
[3];
2159 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
2160 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2161 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
2162 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2163 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
2164 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2165 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
2166 offsets
[0] = offset
[0].i
[0];
2167 offsets
[1] = offset
[1].i
[0];
2168 offsets
[2] = offset
[2].i
[0];
2170 assert(inst
->Texture
.NumOffsets
== 0);
2171 offsets
[0] = offsets
[1] = offsets
[2] = 0;
2177 * Fetch dx and dy values for one channel (s, t or r).
2178 * Put dx values into one float array, dy values into another.
2181 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
2182 const struct tgsi_full_instruction
*inst
,
2185 float derivs
[2][TGSI_QUAD_SIZE
])
2187 union tgsi_exec_channel d
;
2188 FETCH(&d
, regdsrcx
, chan
);
2189 derivs
[0][0] = d
.f
[0];
2190 derivs
[0][1] = d
.f
[1];
2191 derivs
[0][2] = d
.f
[2];
2192 derivs
[0][3] = d
.f
[3];
2193 FETCH(&d
, regdsrcx
+ 1, chan
);
2194 derivs
[1][0] = d
.f
[0];
2195 derivs
[1][1] = d
.f
[1];
2196 derivs
[1][2] = d
.f
[2];
2197 derivs
[1][3] = d
.f
[3];
2201 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
2202 const struct tgsi_full_instruction
*inst
,
2207 if (inst
->Src
[sampler
].Register
.Indirect
) {
2208 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2209 union tgsi_exec_channel indir_index
, index2
;
2210 const uint execmask
= mach
->ExecMask
;
2214 index2
.i
[3] = reg
->Indirect
.Index
;
2216 fetch_src_file_channel(mach
,
2218 reg
->Indirect
.Swizzle
,
2222 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2223 if (execmask
& (1 << i
)) {
2224 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[i
];
2230 unit
= inst
->Src
[sampler
].Register
.Index
;
2236 * execute a texture instruction.
2238 * modifier is used to control the channel routing for the
2239 * instruction variants like proj, lod, and texture with lod bias.
2240 * sampler indicates which src register the sampler is contained in.
2243 exec_tex(struct tgsi_exec_machine
*mach
,
2244 const struct tgsi_full_instruction
*inst
,
2245 uint modifier
, uint sampler
)
2247 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2248 union tgsi_exec_channel r
[5];
2249 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2253 int dim
, shadow_ref
, i
;
2255 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2256 /* always fetch all 3 offsets, overkill but keeps code simple */
2257 fetch_texel_offsets(mach
, inst
, offsets
);
2259 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2260 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2262 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2263 shadow_ref
= tgsi_util_get_shadow_ref_src_index(inst
->Texture
.Texture
);
2266 if (shadow_ref
>= 0)
2267 assert(shadow_ref
>= dim
&& shadow_ref
< (int)ARRAY_SIZE(args
));
2269 /* fetch modifier to the last argument */
2270 if (modifier
!= TEX_MODIFIER_NONE
) {
2271 const int last
= ARRAY_SIZE(args
) - 1;
2273 /* fetch modifier from src0.w or src1.x */
2275 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2276 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2279 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2282 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2283 args
[last
] = &r
[last
];
2287 args
[last
] = &ZeroVec
;
2290 /* point unused arguments to zero vector */
2291 for (i
= dim
; i
< last
; i
++)
2294 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2295 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2296 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2297 control
= TGSI_SAMPLER_LOD_BIAS
;
2298 else if (modifier
== TEX_MODIFIER_GATHER
)
2299 control
= TGSI_SAMPLER_GATHER
;
2302 for (i
= dim
; i
< (int)ARRAY_SIZE(args
); i
++)
2306 /* fetch coordinates */
2307 for (i
= 0; i
< dim
; i
++) {
2308 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2311 micro_div(&r
[i
], &r
[i
], proj
);
2316 /* fetch reference value */
2317 if (shadow_ref
>= 0) {
2318 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2321 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2323 args
[shadow_ref
] = &r
[shadow_ref
];
2326 fetch_texel(mach
->Sampler
, unit
, unit
,
2327 args
[0], args
[1], args
[2], args
[3], args
[4],
2328 NULL
, offsets
, control
,
2329 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2332 debug_printf("fetch r: %g %g %g %g\n",
2333 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2334 debug_printf("fetch g: %g %g %g %g\n",
2335 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2336 debug_printf("fetch b: %g %g %g %g\n",
2337 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2338 debug_printf("fetch a: %g %g %g %g\n",
2339 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2342 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2343 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2344 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2350 exec_lodq(struct tgsi_exec_machine
*mach
,
2351 const struct tgsi_full_instruction
*inst
)
2353 uint resource_unit
, sampler_unit
;
2356 union tgsi_exec_channel coords
[4];
2357 const union tgsi_exec_channel
*args
[ARRAY_SIZE(coords
)];
2358 union tgsi_exec_channel r
[2];
2360 resource_unit
= fetch_sampler_unit(mach
, inst
, 1);
2361 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LOD
) {
2362 uint target
= mach
->SamplerViews
[resource_unit
].Resource
;
2363 dim
= tgsi_util_get_texture_coord_dim(target
);
2364 sampler_unit
= fetch_sampler_unit(mach
, inst
, 2);
2366 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2367 sampler_unit
= resource_unit
;
2369 assert(dim
<= ARRAY_SIZE(coords
));
2370 /* fetch coordinates */
2371 for (i
= 0; i
< dim
; i
++) {
2372 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2373 args
[i
] = &coords
[i
];
2375 for (i
= dim
; i
< ARRAY_SIZE(coords
); i
++) {
2378 mach
->Sampler
->query_lod(mach
->Sampler
, resource_unit
, sampler_unit
,
2383 TGSI_SAMPLER_LOD_NONE
,
2387 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2388 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2389 TGSI_EXEC_DATA_FLOAT
);
2391 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2392 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2393 TGSI_EXEC_DATA_FLOAT
);
2395 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LOD
) {
2396 unsigned char swizzles
[4];
2398 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2399 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2400 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2401 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2403 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2404 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2405 if (swizzles
[chan
] >= 2) {
2406 store_dest(mach
, &ZeroVec
,
2407 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2409 store_dest(mach
, &r
[swizzles
[chan
]],
2410 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2415 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2416 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2417 TGSI_EXEC_DATA_FLOAT
);
2419 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2420 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2421 TGSI_EXEC_DATA_FLOAT
);
2427 exec_txd(struct tgsi_exec_machine
*mach
,
2428 const struct tgsi_full_instruction
*inst
)
2430 union tgsi_exec_channel r
[4];
2431 float derivs
[3][2][TGSI_QUAD_SIZE
];
2436 unit
= fetch_sampler_unit(mach
, inst
, 3);
2437 /* always fetch all 3 offsets, overkill but keeps code simple */
2438 fetch_texel_offsets(mach
, inst
, offsets
);
2440 switch (inst
->Texture
.Texture
) {
2441 case TGSI_TEXTURE_1D
:
2442 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2444 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2446 fetch_texel(mach
->Sampler
, unit
, unit
,
2447 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2448 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2449 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2452 case TGSI_TEXTURE_SHADOW1D
:
2453 case TGSI_TEXTURE_1D_ARRAY
:
2454 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2455 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2456 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2457 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2458 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2460 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2462 fetch_texel(mach
->Sampler
, unit
, unit
,
2463 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2464 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2465 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2468 case TGSI_TEXTURE_2D
:
2469 case TGSI_TEXTURE_RECT
:
2470 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2471 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2473 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2474 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2476 fetch_texel(mach
->Sampler
, unit
, unit
,
2477 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2478 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2479 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2483 case TGSI_TEXTURE_SHADOW2D
:
2484 case TGSI_TEXTURE_SHADOWRECT
:
2485 case TGSI_TEXTURE_2D_ARRAY
:
2486 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2487 /* only SHADOW2D_ARRAY actually needs W */
2488 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2489 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2490 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2491 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2493 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2494 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2496 fetch_texel(mach
->Sampler
, unit
, unit
,
2497 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2498 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2499 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2502 case TGSI_TEXTURE_3D
:
2503 case TGSI_TEXTURE_CUBE
:
2504 case TGSI_TEXTURE_CUBE_ARRAY
:
2505 case TGSI_TEXTURE_SHADOWCUBE
:
2506 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2507 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2508 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2509 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2510 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2512 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2513 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2514 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2516 fetch_texel(mach
->Sampler
, unit
, unit
,
2517 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2518 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2519 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2526 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2527 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2528 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2535 exec_txf(struct tgsi_exec_machine
*mach
,
2536 const struct tgsi_full_instruction
*inst
)
2538 union tgsi_exec_channel r
[4];
2541 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2546 unit
= fetch_sampler_unit(mach
, inst
, 1);
2547 /* always fetch all 3 offsets, overkill but keeps code simple */
2548 fetch_texel_offsets(mach
, inst
, offsets
);
2550 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2552 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2553 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2554 target
= mach
->SamplerViews
[unit
].Resource
;
2557 target
= inst
->Texture
.Texture
;
2560 case TGSI_TEXTURE_3D
:
2561 case TGSI_TEXTURE_2D_ARRAY
:
2562 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2563 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2564 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2566 case TGSI_TEXTURE_2D
:
2567 case TGSI_TEXTURE_RECT
:
2568 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2569 case TGSI_TEXTURE_SHADOW2D
:
2570 case TGSI_TEXTURE_SHADOWRECT
:
2571 case TGSI_TEXTURE_1D_ARRAY
:
2572 case TGSI_TEXTURE_2D_MSAA
:
2573 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2575 case TGSI_TEXTURE_BUFFER
:
2576 case TGSI_TEXTURE_1D
:
2577 case TGSI_TEXTURE_SHADOW1D
:
2578 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2585 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2588 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2589 r
[0].f
[j
] = rgba
[0][j
];
2590 r
[1].f
[j
] = rgba
[1][j
];
2591 r
[2].f
[j
] = rgba
[2][j
];
2592 r
[3].f
[j
] = rgba
[3][j
];
2595 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2596 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2597 unsigned char swizzles
[4];
2598 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2599 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2600 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2601 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2603 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2604 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2605 store_dest(mach
, &r
[swizzles
[chan
]],
2606 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2611 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2612 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2613 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2620 exec_txq(struct tgsi_exec_machine
*mach
,
2621 const struct tgsi_full_instruction
*inst
)
2624 union tgsi_exec_channel r
[4], src
;
2629 unit
= fetch_sampler_unit(mach
, inst
, 1);
2631 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2633 /* XXX: This interface can't return per-pixel values */
2634 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2636 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2637 for (j
= 0; j
< 4; j
++) {
2638 r
[j
].i
[i
] = result
[j
];
2642 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2643 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2644 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2645 TGSI_EXEC_DATA_INT
);
2651 exec_sample(struct tgsi_exec_machine
*mach
,
2652 const struct tgsi_full_instruction
*inst
,
2653 uint modifier
, boolean compare
)
2655 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2656 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2657 union tgsi_exec_channel r
[5], c1
;
2658 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2659 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2661 unsigned char swizzles
[4];
2664 /* always fetch all 3 offsets, overkill but keeps code simple */
2665 fetch_texel_offsets(mach
, inst
, offsets
);
2667 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2669 if (modifier
!= TEX_MODIFIER_NONE
) {
2670 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2671 FETCH(&c1
, 3, TGSI_CHAN_X
);
2673 control
= TGSI_SAMPLER_LOD_BIAS
;
2675 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2676 FETCH(&c1
, 3, TGSI_CHAN_X
);
2678 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2680 else if (modifier
== TEX_MODIFIER_GATHER
) {
2681 control
= TGSI_SAMPLER_GATHER
;
2684 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2685 control
= TGSI_SAMPLER_LOD_ZERO
;
2689 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2691 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2692 case TGSI_TEXTURE_1D
:
2694 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2695 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2696 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2697 NULL
, offsets
, control
,
2698 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2701 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2702 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2703 NULL
, offsets
, control
,
2704 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2708 case TGSI_TEXTURE_1D_ARRAY
:
2709 case TGSI_TEXTURE_2D
:
2710 case TGSI_TEXTURE_RECT
:
2711 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2713 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2714 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2715 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2716 NULL
, offsets
, control
,
2717 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2720 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2721 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2722 NULL
, offsets
, control
,
2723 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2727 case TGSI_TEXTURE_2D_ARRAY
:
2728 case TGSI_TEXTURE_3D
:
2729 case TGSI_TEXTURE_CUBE
:
2730 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2731 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2733 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2734 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2735 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2736 NULL
, offsets
, control
,
2737 &r
[0], &r
[1], &r
[2], &r
[3]);
2740 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2741 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2742 NULL
, offsets
, control
,
2743 &r
[0], &r
[1], &r
[2], &r
[3]);
2747 case TGSI_TEXTURE_CUBE_ARRAY
:
2748 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2749 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2750 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2752 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2753 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2754 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2755 NULL
, offsets
, control
,
2756 &r
[0], &r
[1], &r
[2], &r
[3]);
2759 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2760 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2761 NULL
, offsets
, control
,
2762 &r
[0], &r
[1], &r
[2], &r
[3]);
2771 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2772 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2773 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2774 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2776 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2777 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2778 store_dest(mach
, &r
[swizzles
[chan
]],
2779 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2785 exec_sample_d(struct tgsi_exec_machine
*mach
,
2786 const struct tgsi_full_instruction
*inst
)
2788 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2789 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2790 union tgsi_exec_channel r
[4];
2791 float derivs
[3][2][TGSI_QUAD_SIZE
];
2793 unsigned char swizzles
[4];
2796 /* always fetch all 3 offsets, overkill but keeps code simple */
2797 fetch_texel_offsets(mach
, inst
, offsets
);
2799 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2801 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2802 case TGSI_TEXTURE_1D
:
2803 case TGSI_TEXTURE_1D_ARRAY
:
2804 /* only 1D array actually needs Y */
2805 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2807 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2809 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2810 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2811 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2812 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2815 case TGSI_TEXTURE_2D
:
2816 case TGSI_TEXTURE_RECT
:
2817 case TGSI_TEXTURE_2D_ARRAY
:
2818 /* only 2D array actually needs Z */
2819 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2820 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2822 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2823 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2825 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2826 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2827 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2828 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2831 case TGSI_TEXTURE_3D
:
2832 case TGSI_TEXTURE_CUBE
:
2833 case TGSI_TEXTURE_CUBE_ARRAY
:
2834 /* only cube array actually needs W */
2835 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2836 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2837 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2839 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2840 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2841 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2843 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2844 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2845 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2846 &r
[0], &r
[1], &r
[2], &r
[3]);
2853 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2854 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2855 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2856 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2858 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2859 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2860 store_dest(mach
, &r
[swizzles
[chan
]],
2861 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2868 * Evaluate a constant-valued coefficient at the position of the
2873 struct tgsi_exec_machine
*mach
,
2879 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2880 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2885 interp_constant_offset(
2886 UNUSED
const struct tgsi_exec_machine
*mach
,
2887 UNUSED
unsigned attrib
,
2888 UNUSED
unsigned chan
,
2891 UNUSED
union tgsi_exec_channel
*out_chan
)
2896 * Evaluate a linear-valued coefficient at the position of the
2900 interp_linear_offset(
2901 const struct tgsi_exec_machine
*mach
,
2906 union tgsi_exec_channel
*out_chan
)
2908 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2909 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2910 const float delta
= ofs_x
* dadx
+ ofs_y
* dady
;
2911 out_chan
->f
[0] += delta
;
2912 out_chan
->f
[1] += delta
;
2913 out_chan
->f
[2] += delta
;
2914 out_chan
->f
[3] += delta
;
2918 eval_linear_coef(struct tgsi_exec_machine
*mach
,
2922 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2923 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2924 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2925 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2926 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2928 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2929 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2930 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2931 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2935 * Evaluate a perspective-valued coefficient at the position of the
2940 interp_perspective_offset(
2941 const struct tgsi_exec_machine
*mach
,
2946 union tgsi_exec_channel
*out_chan
)
2948 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2949 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2950 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2951 const float delta
= ofs_x
* dadx
+ ofs_y
* dady
;
2952 out_chan
->f
[0] += delta
/ w
[0];
2953 out_chan
->f
[1] += delta
/ w
[1];
2954 out_chan
->f
[2] += delta
/ w
[2];
2955 out_chan
->f
[3] += delta
/ w
[3];
2959 eval_perspective_coef(
2960 struct tgsi_exec_machine
*mach
,
2964 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2965 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2966 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2967 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2968 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2969 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2970 /* divide by W here */
2971 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2972 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2973 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2974 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2978 typedef void (* eval_coef_func
)(
2979 struct tgsi_exec_machine
*mach
,
2984 exec_declaration(struct tgsi_exec_machine
*mach
,
2985 const struct tgsi_full_declaration
*decl
)
2987 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2988 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2992 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
2993 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2994 uint first
, last
, mask
;
2996 first
= decl
->Range
.First
;
2997 last
= decl
->Range
.Last
;
2998 mask
= decl
->Declaration
.UsageMask
;
3000 /* XXX we could remove this special-case code since
3001 * mach->InterpCoefs[first].a0 should already have the
3002 * front/back-face value. But we should first update the
3003 * ureg code to emit the right UsageMask value (WRITEMASK_X).
3004 * Then, we could remove the tgsi_exec_machine::Face field.
3006 /* XXX make FACE a system value */
3007 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
3010 assert(decl
->Semantic
.Index
== 0);
3011 assert(first
== last
);
3013 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3014 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
3017 eval_coef_func eval
;
3018 apply_sample_offset_func interp
;
3021 switch (decl
->Interp
.Interpolate
) {
3022 case TGSI_INTERPOLATE_CONSTANT
:
3023 eval
= eval_constant_coef
;
3024 interp
= interp_constant_offset
;
3027 case TGSI_INTERPOLATE_LINEAR
:
3028 eval
= eval_linear_coef
;
3029 interp
= interp_linear_offset
;
3032 case TGSI_INTERPOLATE_PERSPECTIVE
:
3033 eval
= eval_perspective_coef
;
3034 interp
= interp_perspective_offset
;
3037 case TGSI_INTERPOLATE_COLOR
:
3038 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
3039 interp
= mach
->flatshade_color
? interp_constant_offset
: interp_perspective_offset
;
3047 for (i
= first
; i
<= last
; i
++)
3048 mach
->InputSampleOffsetApply
[i
] = interp
;
3050 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
3051 if (mask
& (1 << j
)) {
3052 for (i
= first
; i
<= last
; i
++) {
3059 if (DEBUG_EXECUTION
) {
3061 for (i
= first
; i
<= last
; ++i
) {
3062 debug_printf("IN[%2u] = ", i
);
3063 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
3067 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3068 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
3069 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
3070 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
3071 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
3080 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
3081 const union tgsi_exec_channel
*src
);
3084 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
3085 const struct tgsi_full_instruction
*inst
,
3087 enum tgsi_exec_datatype dst_datatype
,
3088 enum tgsi_exec_datatype src_datatype
)
3091 union tgsi_exec_channel src
;
3092 union tgsi_exec_channel dst
;
3094 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3096 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3097 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3098 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3104 exec_vector_unary(struct tgsi_exec_machine
*mach
,
3105 const struct tgsi_full_instruction
*inst
,
3107 enum tgsi_exec_datatype dst_datatype
,
3108 enum tgsi_exec_datatype src_datatype
)
3111 struct tgsi_exec_vector dst
;
3113 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3114 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3115 union tgsi_exec_channel src
;
3117 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
3118 op(&dst
.xyzw
[chan
], &src
);
3121 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3122 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3123 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3128 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
3129 const union tgsi_exec_channel
*src0
,
3130 const union tgsi_exec_channel
*src1
);
3133 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
3134 const struct tgsi_full_instruction
*inst
,
3136 enum tgsi_exec_datatype dst_datatype
,
3137 enum tgsi_exec_datatype src_datatype
)
3140 union tgsi_exec_channel src
[2];
3141 union tgsi_exec_channel dst
;
3143 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3144 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
3145 op(&dst
, &src
[0], &src
[1]);
3146 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3147 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3148 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3154 exec_vector_binary(struct tgsi_exec_machine
*mach
,
3155 const struct tgsi_full_instruction
*inst
,
3157 enum tgsi_exec_datatype dst_datatype
,
3158 enum tgsi_exec_datatype src_datatype
)
3161 struct tgsi_exec_vector dst
;
3163 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3164 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3165 union tgsi_exec_channel src
[2];
3167 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3168 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3169 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
3172 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3173 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3174 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3179 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
3180 const union tgsi_exec_channel
*src0
,
3181 const union tgsi_exec_channel
*src1
,
3182 const union tgsi_exec_channel
*src2
);
3185 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
3186 const struct tgsi_full_instruction
*inst
,
3187 micro_trinary_op op
,
3188 enum tgsi_exec_datatype dst_datatype
,
3189 enum tgsi_exec_datatype src_datatype
)
3192 struct tgsi_exec_vector dst
;
3194 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3195 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3196 union tgsi_exec_channel src
[3];
3198 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3199 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3200 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3201 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3204 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3205 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3206 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3211 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
3212 const union tgsi_exec_channel
*src0
,
3213 const union tgsi_exec_channel
*src1
,
3214 const union tgsi_exec_channel
*src2
,
3215 const union tgsi_exec_channel
*src3
);
3218 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
3219 const struct tgsi_full_instruction
*inst
,
3220 micro_quaternary_op op
,
3221 enum tgsi_exec_datatype dst_datatype
,
3222 enum tgsi_exec_datatype src_datatype
)
3225 struct tgsi_exec_vector dst
;
3227 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3228 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3229 union tgsi_exec_channel src
[4];
3231 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3232 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3233 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3234 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
3235 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
3238 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3239 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3240 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3246 exec_dp3(struct tgsi_exec_machine
*mach
,
3247 const struct tgsi_full_instruction
*inst
)
3250 union tgsi_exec_channel arg
[3];
3252 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3253 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3254 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3256 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
3257 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3258 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3259 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3262 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3263 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3264 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3270 exec_dp4(struct tgsi_exec_machine
*mach
,
3271 const struct tgsi_full_instruction
*inst
)
3274 union tgsi_exec_channel arg
[3];
3276 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3277 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3278 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3280 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
3281 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3282 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3283 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3286 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3287 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3288 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3294 exec_dp2(struct tgsi_exec_machine
*mach
,
3295 const struct tgsi_full_instruction
*inst
)
3298 union tgsi_exec_channel arg
[3];
3300 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3301 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3302 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3304 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3305 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3306 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3308 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3309 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3310 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3316 exec_pk2h(struct tgsi_exec_machine
*mach
,
3317 const struct tgsi_full_instruction
*inst
)
3320 union tgsi_exec_channel arg
[2], dst
;
3322 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3323 fetch_source(mach
, &arg
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3324 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3325 dst
.u
[chan
] = util_float_to_half(arg
[0].f
[chan
]) |
3326 (util_float_to_half(arg
[1].f
[chan
]) << 16);
3328 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3329 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3330 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_UINT
);
3336 exec_up2h(struct tgsi_exec_machine
*mach
,
3337 const struct tgsi_full_instruction
*inst
)
3340 union tgsi_exec_channel arg
, dst
[2];
3342 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3343 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3344 dst
[0].f
[chan
] = util_half_to_float(arg
.u
[chan
] & 0xffff);
3345 dst
[1].f
[chan
] = util_half_to_float(arg
.u
[chan
] >> 16);
3347 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3348 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3349 store_dest(mach
, &dst
[chan
& 1], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3355 micro_ucmp(union tgsi_exec_channel
*dst
,
3356 const union tgsi_exec_channel
*src0
,
3357 const union tgsi_exec_channel
*src1
,
3358 const union tgsi_exec_channel
*src2
)
3360 dst
->f
[0] = src0
->u
[0] ? src1
->f
[0] : src2
->f
[0];
3361 dst
->f
[1] = src0
->u
[1] ? src1
->f
[1] : src2
->f
[1];
3362 dst
->f
[2] = src0
->u
[2] ? src1
->f
[2] : src2
->f
[2];
3363 dst
->f
[3] = src0
->u
[3] ? src1
->f
[3] : src2
->f
[3];
3367 exec_ucmp(struct tgsi_exec_machine
*mach
,
3368 const struct tgsi_full_instruction
*inst
)
3371 struct tgsi_exec_vector dst
;
3373 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3374 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3375 union tgsi_exec_channel src
[3];
3377 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
,
3378 TGSI_EXEC_DATA_UINT
);
3379 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
,
3380 TGSI_EXEC_DATA_FLOAT
);
3381 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
,
3382 TGSI_EXEC_DATA_FLOAT
);
3383 micro_ucmp(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3386 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3387 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3388 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
,
3389 TGSI_EXEC_DATA_FLOAT
);
3395 exec_dst(struct tgsi_exec_machine
*mach
,
3396 const struct tgsi_full_instruction
*inst
)
3398 union tgsi_exec_channel r
[2];
3399 union tgsi_exec_channel d
[4];
3401 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3402 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3403 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3404 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3406 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3407 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3409 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3410 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3413 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3414 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3416 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3417 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3419 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3420 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3422 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3423 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3428 exec_log(struct tgsi_exec_machine
*mach
,
3429 const struct tgsi_full_instruction
*inst
)
3431 union tgsi_exec_channel r
[3];
3433 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3434 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3435 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3436 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3437 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3438 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3440 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3441 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3442 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3443 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3445 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3446 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3448 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3449 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3454 exec_exp(struct tgsi_exec_machine
*mach
,
3455 const struct tgsi_full_instruction
*inst
)
3457 union tgsi_exec_channel r
[3];
3459 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3460 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3461 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3462 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3463 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3465 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3466 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3467 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3469 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3470 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3471 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3473 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3474 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3479 exec_lit(struct tgsi_exec_machine
*mach
,
3480 const struct tgsi_full_instruction
*inst
)
3482 union tgsi_exec_channel r
[3];
3483 union tgsi_exec_channel d
[3];
3485 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3486 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3487 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3488 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3489 micro_max(&r
[1], &r
[1], &ZeroVec
);
3491 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3492 micro_min(&r
[2], &r
[2], &P128Vec
);
3493 micro_max(&r
[2], &r
[2], &M128Vec
);
3494 micro_pow(&r
[1], &r
[1], &r
[2]);
3495 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3496 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3498 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3499 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3500 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3503 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3504 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3507 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3508 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3513 exec_break(struct tgsi_exec_machine
*mach
)
3515 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3516 /* turn off loop channels for each enabled exec channel */
3517 mach
->LoopMask
&= ~mach
->ExecMask
;
3518 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3519 UPDATE_EXEC_MASK(mach
);
3521 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3523 mach
->Switch
.mask
= 0x0;
3525 UPDATE_EXEC_MASK(mach
);
3530 exec_switch(struct tgsi_exec_machine
*mach
,
3531 const struct tgsi_full_instruction
*inst
)
3533 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3534 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3536 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3537 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3538 mach
->Switch
.mask
= 0x0;
3539 mach
->Switch
.defaultMask
= 0x0;
3541 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3542 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3544 UPDATE_EXEC_MASK(mach
);
3548 exec_case(struct tgsi_exec_machine
*mach
,
3549 const struct tgsi_full_instruction
*inst
)
3551 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3552 union tgsi_exec_channel src
;
3555 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3557 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3560 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3563 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3566 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3570 mach
->Switch
.defaultMask
|= mask
;
3572 mach
->Switch
.mask
|= mask
& prevMask
;
3574 UPDATE_EXEC_MASK(mach
);
3577 /* FIXME: this will only work if default is last */
3579 exec_default(struct tgsi_exec_machine
*mach
)
3581 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3583 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3585 UPDATE_EXEC_MASK(mach
);
3589 exec_endswitch(struct tgsi_exec_machine
*mach
)
3591 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3592 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3594 UPDATE_EXEC_MASK(mach
);
3597 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3598 const union tgsi_double_channel
*src
);
3600 typedef void (* micro_dop_sop
)(union tgsi_double_channel
*dst
,
3601 const union tgsi_double_channel
*src0
,
3602 union tgsi_exec_channel
*src1
);
3604 typedef void (* micro_dop_s
)(union tgsi_double_channel
*dst
,
3605 const union tgsi_exec_channel
*src
);
3607 typedef void (* micro_sop_d
)(union tgsi_exec_channel
*dst
,
3608 const union tgsi_double_channel
*src
);
3611 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3612 union tgsi_double_channel
*chan
,
3613 const struct tgsi_full_src_register
*reg
,
3617 union tgsi_exec_channel src
[2];
3620 fetch_source_d(mach
, &src
[0], reg
, chan_0
);
3621 fetch_source_d(mach
, &src
[1], reg
, chan_1
);
3623 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3624 chan
->u
[i
][0] = src
[0].u
[i
];
3625 chan
->u
[i
][1] = src
[1].u
[i
];
3627 if (reg
->Register
.Absolute
) {
3628 micro_dabs(chan
, chan
);
3630 if (reg
->Register
.Negate
) {
3631 micro_dneg(chan
, chan
);
3636 store_double_channel(struct tgsi_exec_machine
*mach
,
3637 const union tgsi_double_channel
*chan
,
3638 const struct tgsi_full_dst_register
*reg
,
3639 const struct tgsi_full_instruction
*inst
,
3643 union tgsi_exec_channel dst
[2];
3645 union tgsi_double_channel temp
;
3646 const uint execmask
= mach
->ExecMask
;
3648 if (!inst
->Instruction
.Saturate
) {
3649 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3650 if (execmask
& (1 << i
)) {
3651 dst
[0].u
[i
] = chan
->u
[i
][0];
3652 dst
[1].u
[i
] = chan
->u
[i
][1];
3656 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3657 if (execmask
& (1 << i
)) {
3658 if (chan
->d
[i
] < 0.0)
3660 else if (chan
->d
[i
] > 1.0)
3663 temp
.d
[i
] = chan
->d
[i
];
3665 dst
[0].u
[i
] = temp
.u
[i
][0];
3666 dst
[1].u
[i
] = temp
.u
[i
][1];
3670 store_dest_double(mach
, &dst
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3671 if (chan_1
!= (unsigned)-1)
3672 store_dest_double(mach
, &dst
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3676 exec_double_unary(struct tgsi_exec_machine
*mach
,
3677 const struct tgsi_full_instruction
*inst
,
3680 union tgsi_double_channel src
;
3681 union tgsi_double_channel dst
;
3683 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3684 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3686 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3688 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3689 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3691 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3696 exec_double_binary(struct tgsi_exec_machine
*mach
,
3697 const struct tgsi_full_instruction
*inst
,
3699 enum tgsi_exec_datatype dst_datatype
)
3701 union tgsi_double_channel src
[2];
3702 union tgsi_double_channel dst
;
3703 int first_dest_chan
, second_dest_chan
;
3706 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3707 /* these are & because of the way DSLT etc store their destinations */
3708 if (wmask
& TGSI_WRITEMASK_XY
) {
3709 first_dest_chan
= TGSI_CHAN_X
;
3710 second_dest_chan
= TGSI_CHAN_Y
;
3711 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3712 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3713 second_dest_chan
= -1;
3716 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3717 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3719 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3722 if (wmask
& TGSI_WRITEMASK_ZW
) {
3723 first_dest_chan
= TGSI_CHAN_Z
;
3724 second_dest_chan
= TGSI_CHAN_W
;
3725 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3726 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3727 second_dest_chan
= -1;
3730 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3731 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3733 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3738 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3739 const struct tgsi_full_instruction
*inst
,
3742 union tgsi_double_channel src
[3];
3743 union tgsi_double_channel dst
;
3745 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3746 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3747 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3748 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3750 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3752 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3753 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3754 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3755 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3757 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3762 exec_dldexp(struct tgsi_exec_machine
*mach
,
3763 const struct tgsi_full_instruction
*inst
)
3765 union tgsi_double_channel src0
;
3766 union tgsi_exec_channel src1
;
3767 union tgsi_double_channel dst
;
3770 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3771 if (wmask
& TGSI_WRITEMASK_XY
) {
3772 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3773 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3774 micro_dldexp(&dst
, &src0
, &src1
);
3775 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3778 if (wmask
& TGSI_WRITEMASK_ZW
) {
3779 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3780 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3781 micro_dldexp(&dst
, &src0
, &src1
);
3782 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3787 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3788 const struct tgsi_full_instruction
*inst
)
3790 union tgsi_double_channel src
;
3791 union tgsi_double_channel dst
;
3792 union tgsi_exec_channel dst_exp
;
3794 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3795 micro_dfracexp(&dst
, &dst_exp
, &src
);
3796 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)
3797 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3798 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)
3799 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3800 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3801 if (inst
->Dst
[1].Register
.WriteMask
& (1 << chan
))
3802 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, chan
, TGSI_EXEC_DATA_INT
);
3807 exec_arg0_64_arg1_32(struct tgsi_exec_machine
*mach
,
3808 const struct tgsi_full_instruction
*inst
,
3811 union tgsi_double_channel src0
;
3812 union tgsi_exec_channel src1
;
3813 union tgsi_double_channel dst
;
3816 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3817 if (wmask
& TGSI_WRITEMASK_XY
) {
3818 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3819 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3820 op(&dst
, &src0
, &src1
);
3821 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3824 if (wmask
& TGSI_WRITEMASK_ZW
) {
3825 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3826 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3827 op(&dst
, &src0
, &src1
);
3828 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3833 get_image_coord_dim(unsigned tgsi_tex
)
3837 case TGSI_TEXTURE_BUFFER
:
3838 case TGSI_TEXTURE_1D
:
3841 case TGSI_TEXTURE_2D
:
3842 case TGSI_TEXTURE_RECT
:
3843 case TGSI_TEXTURE_1D_ARRAY
:
3844 case TGSI_TEXTURE_2D_MSAA
:
3847 case TGSI_TEXTURE_3D
:
3848 case TGSI_TEXTURE_CUBE
:
3849 case TGSI_TEXTURE_2D_ARRAY
:
3850 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3851 case TGSI_TEXTURE_CUBE_ARRAY
:
3855 assert(!"unknown texture target");
3864 get_image_coord_sample(unsigned tgsi_tex
)
3868 case TGSI_TEXTURE_2D_MSAA
:
3871 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3881 exec_load_img(struct tgsi_exec_machine
*mach
,
3882 const struct tgsi_full_instruction
*inst
)
3884 union tgsi_exec_channel r
[4], sample_r
;
3890 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3891 struct tgsi_image_params params
;
3892 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3894 unit
= fetch_sampler_unit(mach
, inst
, 0);
3895 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3896 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3899 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3901 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3902 params
.format
= inst
->Memory
.Format
;
3904 for (i
= 0; i
< dim
; i
++) {
3905 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3909 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3911 mach
->Image
->load(mach
->Image
, ¶ms
,
3912 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3914 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3915 r
[0].f
[j
] = rgba
[0][j
];
3916 r
[1].f
[j
] = rgba
[1][j
];
3917 r
[2].f
[j
] = rgba
[2][j
];
3918 r
[3].f
[j
] = rgba
[3][j
];
3920 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3921 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3922 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3928 exec_load_buf(struct tgsi_exec_machine
*mach
,
3929 const struct tgsi_full_instruction
*inst
)
3931 union tgsi_exec_channel r
[4];
3935 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3936 struct tgsi_buffer_params params
;
3937 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3939 unit
= fetch_sampler_unit(mach
, inst
, 0);
3941 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3943 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3945 mach
->Buffer
->load(mach
->Buffer
, ¶ms
,
3947 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3948 r
[0].f
[j
] = rgba
[0][j
];
3949 r
[1].f
[j
] = rgba
[1][j
];
3950 r
[2].f
[j
] = rgba
[2][j
];
3951 r
[3].f
[j
] = rgba
[3][j
];
3953 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3954 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3955 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3961 exec_load_mem(struct tgsi_exec_machine
*mach
,
3962 const struct tgsi_full_instruction
*inst
)
3964 union tgsi_exec_channel r
[4];
3966 char *ptr
= mach
->LocalMem
;
3970 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3971 if (r
[0].u
[0] >= mach
->LocalMemSize
)
3977 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3978 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3979 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3980 memcpy(&r
[chan
].u
[j
], ptr
+ (4 * chan
), 4);
3985 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3986 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3987 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3993 exec_load(struct tgsi_exec_machine
*mach
,
3994 const struct tgsi_full_instruction
*inst
)
3996 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
3997 exec_load_img(mach
, inst
);
3998 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
3999 exec_load_buf(mach
, inst
);
4000 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4001 exec_load_mem(mach
, inst
);
4005 fetch_store_img_unit(struct tgsi_exec_machine
*mach
,
4006 const struct tgsi_full_dst_register
*dst
)
4010 if (dst
->Register
.Indirect
) {
4011 union tgsi_exec_channel indir_index
, index2
;
4012 const uint execmask
= mach
->ExecMask
;
4016 index2
.i
[3] = dst
->Indirect
.Index
;
4018 fetch_src_file_channel(mach
,
4020 dst
->Indirect
.Swizzle
,
4024 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4025 if (execmask
& (1 << i
)) {
4026 unit
= dst
->Register
.Index
+ indir_index
.i
[i
];
4031 unit
= dst
->Register
.Index
;
4037 exec_store_img(struct tgsi_exec_machine
*mach
,
4038 const struct tgsi_full_instruction
*inst
)
4040 union tgsi_exec_channel r
[3], sample_r
;
4041 union tgsi_exec_channel value
[4];
4042 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4043 struct tgsi_image_params params
;
4048 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4049 unit
= fetch_store_img_unit(mach
, &inst
->Dst
[0]);
4050 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4051 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4054 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4056 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4057 params
.format
= inst
->Memory
.Format
;
4059 for (i
= 0; i
< dim
; i
++) {
4060 IFETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
4063 for (i
= 0; i
< 4; i
++) {
4064 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4067 IFETCH(&sample_r
, 0, TGSI_CHAN_X
+ sample
);
4069 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4070 rgba
[0][j
] = value
[0].f
[j
];
4071 rgba
[1][j
] = value
[1].f
[j
];
4072 rgba
[2][j
] = value
[2].f
[j
];
4073 rgba
[3][j
] = value
[3].f
[j
];
4076 mach
->Image
->store(mach
->Image
, ¶ms
,
4077 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4082 exec_store_buf(struct tgsi_exec_machine
*mach
,
4083 const struct tgsi_full_instruction
*inst
)
4085 union tgsi_exec_channel r
[3];
4086 union tgsi_exec_channel value
[4];
4087 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4088 struct tgsi_buffer_params params
;
4091 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4093 unit
= fetch_store_img_unit(mach
, &inst
->Dst
[0]);
4095 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4097 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4099 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4100 for (i
= 0; i
< 4; i
++) {
4101 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4104 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4105 rgba
[0][j
] = value
[0].f
[j
];
4106 rgba
[1][j
] = value
[1].f
[j
];
4107 rgba
[2][j
] = value
[2].f
[j
];
4108 rgba
[3][j
] = value
[3].f
[j
];
4111 mach
->Buffer
->store(mach
->Buffer
, ¶ms
,
4117 exec_store_mem(struct tgsi_exec_machine
*mach
,
4118 const struct tgsi_full_instruction
*inst
)
4120 union tgsi_exec_channel r
[3];
4121 union tgsi_exec_channel value
[4];
4123 char *ptr
= mach
->LocalMem
;
4124 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4125 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4127 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4129 for (i
= 0; i
< 4; i
++) {
4130 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4133 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4137 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4138 if (execmask
& (1 << i
)) {
4139 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4140 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4141 memcpy(ptr
+ (chan
* 4), &value
[chan
].u
[0], 4);
4149 exec_store(struct tgsi_exec_machine
*mach
,
4150 const struct tgsi_full_instruction
*inst
)
4152 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
)
4153 exec_store_img(mach
, inst
);
4154 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
)
4155 exec_store_buf(mach
, inst
);
4156 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
)
4157 exec_store_mem(mach
, inst
);
4161 exec_atomop_img(struct tgsi_exec_machine
*mach
,
4162 const struct tgsi_full_instruction
*inst
)
4164 union tgsi_exec_channel r
[4], sample_r
;
4165 union tgsi_exec_channel value
[4], value2
[4];
4166 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4167 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4168 struct tgsi_image_params params
;
4173 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4174 unit
= fetch_sampler_unit(mach
, inst
, 0);
4175 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4176 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4179 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4181 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4182 params
.format
= inst
->Memory
.Format
;
4184 for (i
= 0; i
< dim
; i
++) {
4185 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
4188 for (i
= 0; i
< 4; i
++) {
4189 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4190 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4191 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4194 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
4196 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4197 rgba
[0][j
] = value
[0].f
[j
];
4198 rgba
[1][j
] = value
[1].f
[j
];
4199 rgba
[2][j
] = value
[2].f
[j
];
4200 rgba
[3][j
] = value
[3].f
[j
];
4202 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4203 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4204 rgba2
[0][j
] = value2
[0].f
[j
];
4205 rgba2
[1][j
] = value2
[1].f
[j
];
4206 rgba2
[2][j
] = value2
[2].f
[j
];
4207 rgba2
[3][j
] = value2
[3].f
[j
];
4211 mach
->Image
->op(mach
->Image
, ¶ms
, inst
->Instruction
.Opcode
,
4212 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4215 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4216 r
[0].f
[j
] = rgba
[0][j
];
4217 r
[1].f
[j
] = rgba
[1][j
];
4218 r
[2].f
[j
] = rgba
[2][j
];
4219 r
[3].f
[j
] = rgba
[3][j
];
4221 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4222 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4223 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4229 exec_atomop_buf(struct tgsi_exec_machine
*mach
,
4230 const struct tgsi_full_instruction
*inst
)
4232 union tgsi_exec_channel r
[4];
4233 union tgsi_exec_channel value
[4], value2
[4];
4234 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4235 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4236 struct tgsi_buffer_params params
;
4239 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4241 unit
= fetch_sampler_unit(mach
, inst
, 0);
4243 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4245 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4247 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4249 for (i
= 0; i
< 4; i
++) {
4250 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4251 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4252 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4255 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4256 rgba
[0][j
] = value
[0].f
[j
];
4257 rgba
[1][j
] = value
[1].f
[j
];
4258 rgba
[2][j
] = value
[2].f
[j
];
4259 rgba
[3][j
] = value
[3].f
[j
];
4261 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4262 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4263 rgba2
[0][j
] = value2
[0].f
[j
];
4264 rgba2
[1][j
] = value2
[1].f
[j
];
4265 rgba2
[2][j
] = value2
[2].f
[j
];
4266 rgba2
[3][j
] = value2
[3].f
[j
];
4270 mach
->Buffer
->op(mach
->Buffer
, ¶ms
, inst
->Instruction
.Opcode
,
4274 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4275 r
[0].f
[j
] = rgba
[0][j
];
4276 r
[1].f
[j
] = rgba
[1][j
];
4277 r
[2].f
[j
] = rgba
[2][j
];
4278 r
[3].f
[j
] = rgba
[3][j
];
4280 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4281 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4282 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4288 exec_atomop_mem(struct tgsi_exec_machine
*mach
,
4289 const struct tgsi_full_instruction
*inst
)
4291 union tgsi_exec_channel r
[4];
4292 union tgsi_exec_channel value
[4], value2
[4];
4293 char *ptr
= mach
->LocalMem
;
4297 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4298 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4299 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4301 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4306 for (i
= 0; i
< 4; i
++) {
4307 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4308 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4309 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4312 memcpy(&r
[0].u
[0], ptr
, 4);
4314 switch (inst
->Instruction
.Opcode
) {
4315 case TGSI_OPCODE_ATOMUADD
:
4316 val
+= value
[0].u
[0];
4318 case TGSI_OPCODE_ATOMXOR
:
4319 val
^= value
[0].u
[0];
4321 case TGSI_OPCODE_ATOMOR
:
4322 val
|= value
[0].u
[0];
4324 case TGSI_OPCODE_ATOMAND
:
4325 val
&= value
[0].u
[0];
4327 case TGSI_OPCODE_ATOMUMIN
:
4328 val
= MIN2(val
, value
[0].u
[0]);
4330 case TGSI_OPCODE_ATOMUMAX
:
4331 val
= MAX2(val
, value
[0].u
[0]);
4333 case TGSI_OPCODE_ATOMIMIN
:
4334 val
= MIN2(r
[0].i
[0], value
[0].i
[0]);
4336 case TGSI_OPCODE_ATOMIMAX
:
4337 val
= MAX2(r
[0].i
[0], value
[0].i
[0]);
4339 case TGSI_OPCODE_ATOMXCHG
:
4340 val
= value
[0].i
[0];
4342 case TGSI_OPCODE_ATOMCAS
:
4343 if (val
== value
[0].u
[0])
4344 val
= value2
[0].u
[0];
4346 case TGSI_OPCODE_ATOMFADD
:
4347 val
= fui(r
[0].f
[0] + value
[0].f
[0]);
4352 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
4353 if (execmask
& (1 << i
))
4354 memcpy(ptr
, &val
, 4);
4356 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4357 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4358 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4364 exec_atomop(struct tgsi_exec_machine
*mach
,
4365 const struct tgsi_full_instruction
*inst
)
4367 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4368 exec_atomop_img(mach
, inst
);
4369 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4370 exec_atomop_buf(mach
, inst
);
4371 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4372 exec_atomop_mem(mach
, inst
);
4376 exec_resq_img(struct tgsi_exec_machine
*mach
,
4377 const struct tgsi_full_instruction
*inst
)
4380 union tgsi_exec_channel r
[4];
4383 struct tgsi_image_params params
;
4384 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4386 unit
= fetch_sampler_unit(mach
, inst
, 0);
4388 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4390 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4391 params
.format
= inst
->Memory
.Format
;
4393 mach
->Image
->get_dims(mach
->Image
, ¶ms
, result
);
4395 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4396 for (j
= 0; j
< 4; j
++) {
4397 r
[j
].i
[i
] = result
[j
];
4401 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4402 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4403 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4404 TGSI_EXEC_DATA_INT
);
4410 exec_resq_buf(struct tgsi_exec_machine
*mach
,
4411 const struct tgsi_full_instruction
*inst
)
4414 union tgsi_exec_channel r
[4];
4417 struct tgsi_buffer_params params
;
4418 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4420 unit
= fetch_sampler_unit(mach
, inst
, 0);
4422 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4425 mach
->Buffer
->get_dims(mach
->Buffer
, ¶ms
, &result
);
4427 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4431 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4432 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4433 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4434 TGSI_EXEC_DATA_INT
);
4440 exec_resq(struct tgsi_exec_machine
*mach
,
4441 const struct tgsi_full_instruction
*inst
)
4443 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4444 exec_resq_img(mach
, inst
);
4446 exec_resq_buf(mach
, inst
);
4450 micro_f2u64(union tgsi_double_channel
*dst
,
4451 const union tgsi_exec_channel
*src
)
4453 dst
->u64
[0] = (uint64_t)src
->f
[0];
4454 dst
->u64
[1] = (uint64_t)src
->f
[1];
4455 dst
->u64
[2] = (uint64_t)src
->f
[2];
4456 dst
->u64
[3] = (uint64_t)src
->f
[3];
4460 micro_f2i64(union tgsi_double_channel
*dst
,
4461 const union tgsi_exec_channel
*src
)
4463 dst
->i64
[0] = (int64_t)src
->f
[0];
4464 dst
->i64
[1] = (int64_t)src
->f
[1];
4465 dst
->i64
[2] = (int64_t)src
->f
[2];
4466 dst
->i64
[3] = (int64_t)src
->f
[3];
4470 micro_u2i64(union tgsi_double_channel
*dst
,
4471 const union tgsi_exec_channel
*src
)
4473 dst
->u64
[0] = (uint64_t)src
->u
[0];
4474 dst
->u64
[1] = (uint64_t)src
->u
[1];
4475 dst
->u64
[2] = (uint64_t)src
->u
[2];
4476 dst
->u64
[3] = (uint64_t)src
->u
[3];
4480 micro_i2i64(union tgsi_double_channel
*dst
,
4481 const union tgsi_exec_channel
*src
)
4483 dst
->i64
[0] = (int64_t)src
->i
[0];
4484 dst
->i64
[1] = (int64_t)src
->i
[1];
4485 dst
->i64
[2] = (int64_t)src
->i
[2];
4486 dst
->i64
[3] = (int64_t)src
->i
[3];
4490 micro_d2u64(union tgsi_double_channel
*dst
,
4491 const union tgsi_double_channel
*src
)
4493 dst
->u64
[0] = (uint64_t)src
->d
[0];
4494 dst
->u64
[1] = (uint64_t)src
->d
[1];
4495 dst
->u64
[2] = (uint64_t)src
->d
[2];
4496 dst
->u64
[3] = (uint64_t)src
->d
[3];
4500 micro_d2i64(union tgsi_double_channel
*dst
,
4501 const union tgsi_double_channel
*src
)
4503 dst
->i64
[0] = (int64_t)src
->d
[0];
4504 dst
->i64
[1] = (int64_t)src
->d
[1];
4505 dst
->i64
[2] = (int64_t)src
->d
[2];
4506 dst
->i64
[3] = (int64_t)src
->d
[3];
4510 micro_u642d(union tgsi_double_channel
*dst
,
4511 const union tgsi_double_channel
*src
)
4513 dst
->d
[0] = (double)src
->u64
[0];
4514 dst
->d
[1] = (double)src
->u64
[1];
4515 dst
->d
[2] = (double)src
->u64
[2];
4516 dst
->d
[3] = (double)src
->u64
[3];
4520 micro_i642d(union tgsi_double_channel
*dst
,
4521 const union tgsi_double_channel
*src
)
4523 dst
->d
[0] = (double)src
->i64
[0];
4524 dst
->d
[1] = (double)src
->i64
[1];
4525 dst
->d
[2] = (double)src
->i64
[2];
4526 dst
->d
[3] = (double)src
->i64
[3];
4530 micro_u642f(union tgsi_exec_channel
*dst
,
4531 const union tgsi_double_channel
*src
)
4533 dst
->f
[0] = (float)src
->u64
[0];
4534 dst
->f
[1] = (float)src
->u64
[1];
4535 dst
->f
[2] = (float)src
->u64
[2];
4536 dst
->f
[3] = (float)src
->u64
[3];
4540 micro_i642f(union tgsi_exec_channel
*dst
,
4541 const union tgsi_double_channel
*src
)
4543 dst
->f
[0] = (float)src
->i64
[0];
4544 dst
->f
[1] = (float)src
->i64
[1];
4545 dst
->f
[2] = (float)src
->i64
[2];
4546 dst
->f
[3] = (float)src
->i64
[3];
4550 exec_t_2_64(struct tgsi_exec_machine
*mach
,
4551 const struct tgsi_full_instruction
*inst
,
4553 enum tgsi_exec_datatype src_datatype
)
4555 union tgsi_exec_channel src
;
4556 union tgsi_double_channel dst
;
4558 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
4559 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
4561 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
4563 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
4564 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, src_datatype
);
4566 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
4571 exec_64_2_t(struct tgsi_exec_machine
*mach
,
4572 const struct tgsi_full_instruction
*inst
,
4574 enum tgsi_exec_datatype dst_datatype
)
4576 union tgsi_double_channel src
;
4577 union tgsi_exec_channel dst
;
4578 int wm
= inst
->Dst
[0].Register
.WriteMask
;
4581 for (i
= 0; i
< 2; i
++) {
4584 wm
&= ~(1 << (bit
- 1));
4586 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
4588 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
4590 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, dst_datatype
);
4596 micro_i2f(union tgsi_exec_channel
*dst
,
4597 const union tgsi_exec_channel
*src
)
4599 dst
->f
[0] = (float)src
->i
[0];
4600 dst
->f
[1] = (float)src
->i
[1];
4601 dst
->f
[2] = (float)src
->i
[2];
4602 dst
->f
[3] = (float)src
->i
[3];
4606 micro_not(union tgsi_exec_channel
*dst
,
4607 const union tgsi_exec_channel
*src
)
4609 dst
->u
[0] = ~src
->u
[0];
4610 dst
->u
[1] = ~src
->u
[1];
4611 dst
->u
[2] = ~src
->u
[2];
4612 dst
->u
[3] = ~src
->u
[3];
4616 micro_shl(union tgsi_exec_channel
*dst
,
4617 const union tgsi_exec_channel
*src0
,
4618 const union tgsi_exec_channel
*src1
)
4620 unsigned masked_count
;
4621 masked_count
= src1
->u
[0] & 0x1f;
4622 dst
->u
[0] = src0
->u
[0] << masked_count
;
4623 masked_count
= src1
->u
[1] & 0x1f;
4624 dst
->u
[1] = src0
->u
[1] << masked_count
;
4625 masked_count
= src1
->u
[2] & 0x1f;
4626 dst
->u
[2] = src0
->u
[2] << masked_count
;
4627 masked_count
= src1
->u
[3] & 0x1f;
4628 dst
->u
[3] = src0
->u
[3] << masked_count
;
4632 micro_and(union tgsi_exec_channel
*dst
,
4633 const union tgsi_exec_channel
*src0
,
4634 const union tgsi_exec_channel
*src1
)
4636 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
4637 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
4638 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
4639 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
4643 micro_or(union tgsi_exec_channel
*dst
,
4644 const union tgsi_exec_channel
*src0
,
4645 const union tgsi_exec_channel
*src1
)
4647 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
4648 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
4649 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
4650 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
4654 micro_xor(union tgsi_exec_channel
*dst
,
4655 const union tgsi_exec_channel
*src0
,
4656 const union tgsi_exec_channel
*src1
)
4658 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
4659 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
4660 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
4661 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
4665 micro_mod(union tgsi_exec_channel
*dst
,
4666 const union tgsi_exec_channel
*src0
,
4667 const union tgsi_exec_channel
*src1
)
4669 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] % src1
->i
[0] : ~0;
4670 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] % src1
->i
[1] : ~0;
4671 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] % src1
->i
[2] : ~0;
4672 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] % src1
->i
[3] : ~0;
4676 micro_f2i(union tgsi_exec_channel
*dst
,
4677 const union tgsi_exec_channel
*src
)
4679 dst
->i
[0] = (int)src
->f
[0];
4680 dst
->i
[1] = (int)src
->f
[1];
4681 dst
->i
[2] = (int)src
->f
[2];
4682 dst
->i
[3] = (int)src
->f
[3];
4686 micro_fseq(union tgsi_exec_channel
*dst
,
4687 const union tgsi_exec_channel
*src0
,
4688 const union tgsi_exec_channel
*src1
)
4690 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
4691 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
4692 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
4693 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
4697 micro_fsge(union tgsi_exec_channel
*dst
,
4698 const union tgsi_exec_channel
*src0
,
4699 const union tgsi_exec_channel
*src1
)
4701 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
4702 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
4703 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
4704 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
4708 micro_fslt(union tgsi_exec_channel
*dst
,
4709 const union tgsi_exec_channel
*src0
,
4710 const union tgsi_exec_channel
*src1
)
4712 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
4713 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
4714 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
4715 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
4719 micro_fsne(union tgsi_exec_channel
*dst
,
4720 const union tgsi_exec_channel
*src0
,
4721 const union tgsi_exec_channel
*src1
)
4723 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
4724 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
4725 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
4726 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
4730 micro_idiv(union tgsi_exec_channel
*dst
,
4731 const union tgsi_exec_channel
*src0
,
4732 const union tgsi_exec_channel
*src1
)
4734 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
4735 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
4736 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
4737 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
4741 micro_imax(union tgsi_exec_channel
*dst
,
4742 const union tgsi_exec_channel
*src0
,
4743 const union tgsi_exec_channel
*src1
)
4745 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4746 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4747 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4748 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4752 micro_imin(union tgsi_exec_channel
*dst
,
4753 const union tgsi_exec_channel
*src0
,
4754 const union tgsi_exec_channel
*src1
)
4756 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4757 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4758 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4759 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4763 micro_isge(union tgsi_exec_channel
*dst
,
4764 const union tgsi_exec_channel
*src0
,
4765 const union tgsi_exec_channel
*src1
)
4767 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
4768 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
4769 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
4770 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
4774 micro_ishr(union tgsi_exec_channel
*dst
,
4775 const union tgsi_exec_channel
*src0
,
4776 const union tgsi_exec_channel
*src1
)
4778 unsigned masked_count
;
4779 masked_count
= src1
->i
[0] & 0x1f;
4780 dst
->i
[0] = src0
->i
[0] >> masked_count
;
4781 masked_count
= src1
->i
[1] & 0x1f;
4782 dst
->i
[1] = src0
->i
[1] >> masked_count
;
4783 masked_count
= src1
->i
[2] & 0x1f;
4784 dst
->i
[2] = src0
->i
[2] >> masked_count
;
4785 masked_count
= src1
->i
[3] & 0x1f;
4786 dst
->i
[3] = src0
->i
[3] >> masked_count
;
4790 micro_islt(union tgsi_exec_channel
*dst
,
4791 const union tgsi_exec_channel
*src0
,
4792 const union tgsi_exec_channel
*src1
)
4794 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
4795 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
4796 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
4797 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
4801 micro_f2u(union tgsi_exec_channel
*dst
,
4802 const union tgsi_exec_channel
*src
)
4804 dst
->u
[0] = (uint
)src
->f
[0];
4805 dst
->u
[1] = (uint
)src
->f
[1];
4806 dst
->u
[2] = (uint
)src
->f
[2];
4807 dst
->u
[3] = (uint
)src
->f
[3];
4811 micro_u2f(union tgsi_exec_channel
*dst
,
4812 const union tgsi_exec_channel
*src
)
4814 dst
->f
[0] = (float)src
->u
[0];
4815 dst
->f
[1] = (float)src
->u
[1];
4816 dst
->f
[2] = (float)src
->u
[2];
4817 dst
->f
[3] = (float)src
->u
[3];
4821 micro_uadd(union tgsi_exec_channel
*dst
,
4822 const union tgsi_exec_channel
*src0
,
4823 const union tgsi_exec_channel
*src1
)
4825 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
4826 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
4827 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
4828 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
4832 micro_udiv(union tgsi_exec_channel
*dst
,
4833 const union tgsi_exec_channel
*src0
,
4834 const union tgsi_exec_channel
*src1
)
4836 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
4837 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
4838 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
4839 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
4843 micro_umad(union tgsi_exec_channel
*dst
,
4844 const union tgsi_exec_channel
*src0
,
4845 const union tgsi_exec_channel
*src1
,
4846 const union tgsi_exec_channel
*src2
)
4848 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
4849 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
4850 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
4851 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
4855 micro_umax(union tgsi_exec_channel
*dst
,
4856 const union tgsi_exec_channel
*src0
,
4857 const union tgsi_exec_channel
*src1
)
4859 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4860 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4861 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4862 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4866 micro_umin(union tgsi_exec_channel
*dst
,
4867 const union tgsi_exec_channel
*src0
,
4868 const union tgsi_exec_channel
*src1
)
4870 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4871 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4872 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4873 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4877 micro_umod(union tgsi_exec_channel
*dst
,
4878 const union tgsi_exec_channel
*src0
,
4879 const union tgsi_exec_channel
*src1
)
4881 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
4882 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
4883 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
4884 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
4888 micro_umul(union tgsi_exec_channel
*dst
,
4889 const union tgsi_exec_channel
*src0
,
4890 const union tgsi_exec_channel
*src1
)
4892 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
4893 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
4894 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
4895 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
4899 micro_imul_hi(union tgsi_exec_channel
*dst
,
4900 const union tgsi_exec_channel
*src0
,
4901 const union tgsi_exec_channel
*src1
)
4903 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4904 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
4905 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
4906 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
4907 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
4912 micro_umul_hi(union tgsi_exec_channel
*dst
,
4913 const union tgsi_exec_channel
*src0
,
4914 const union tgsi_exec_channel
*src1
)
4916 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4917 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
4918 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
4919 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
4920 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
4925 micro_useq(union tgsi_exec_channel
*dst
,
4926 const union tgsi_exec_channel
*src0
,
4927 const union tgsi_exec_channel
*src1
)
4929 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
4930 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
4931 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
4932 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4936 micro_usge(union tgsi_exec_channel
*dst
,
4937 const union tgsi_exec_channel
*src0
,
4938 const union tgsi_exec_channel
*src1
)
4940 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4941 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4942 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4943 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
4947 micro_ushr(union tgsi_exec_channel
*dst
,
4948 const union tgsi_exec_channel
*src0
,
4949 const union tgsi_exec_channel
*src1
)
4951 unsigned masked_count
;
4952 masked_count
= src1
->u
[0] & 0x1f;
4953 dst
->u
[0] = src0
->u
[0] >> masked_count
;
4954 masked_count
= src1
->u
[1] & 0x1f;
4955 dst
->u
[1] = src0
->u
[1] >> masked_count
;
4956 masked_count
= src1
->u
[2] & 0x1f;
4957 dst
->u
[2] = src0
->u
[2] >> masked_count
;
4958 masked_count
= src1
->u
[3] & 0x1f;
4959 dst
->u
[3] = src0
->u
[3] >> masked_count
;
4963 micro_uslt(union tgsi_exec_channel
*dst
,
4964 const union tgsi_exec_channel
*src0
,
4965 const union tgsi_exec_channel
*src1
)
4967 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
4968 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
4969 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
4970 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
4974 micro_usne(union tgsi_exec_channel
*dst
,
4975 const union tgsi_exec_channel
*src0
,
4976 const union tgsi_exec_channel
*src1
)
4978 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
4979 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
4980 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
4981 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
4985 micro_uarl(union tgsi_exec_channel
*dst
,
4986 const union tgsi_exec_channel
*src
)
4988 dst
->i
[0] = src
->u
[0];
4989 dst
->i
[1] = src
->u
[1];
4990 dst
->i
[2] = src
->u
[2];
4991 dst
->i
[3] = src
->u
[3];
4995 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4998 micro_ibfe(union tgsi_exec_channel
*dst
,
4999 const union tgsi_exec_channel
*src0
,
5000 const union tgsi_exec_channel
*src1
,
5001 const union tgsi_exec_channel
*src2
)
5004 for (i
= 0; i
< 4; i
++) {
5005 int width
= src2
->i
[i
];
5006 int offset
= src1
->i
[i
] & 0x1f;
5007 if (width
== 32 && offset
== 0) {
5008 dst
->i
[i
] = src0
->i
[i
];
5014 else if (width
+ offset
< 32)
5015 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
5017 dst
->i
[i
] = src0
->i
[i
] >> offset
;
5022 * Unsigned bitfield extract
5025 micro_ubfe(union tgsi_exec_channel
*dst
,
5026 const union tgsi_exec_channel
*src0
,
5027 const union tgsi_exec_channel
*src1
,
5028 const union tgsi_exec_channel
*src2
)
5031 for (i
= 0; i
< 4; i
++) {
5032 int width
= src2
->u
[i
];
5033 int offset
= src1
->u
[i
] & 0x1f;
5034 if (width
== 32 && offset
== 0) {
5035 dst
->u
[i
] = src0
->u
[i
];
5041 else if (width
+ offset
< 32)
5042 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
5044 dst
->u
[i
] = src0
->u
[i
] >> offset
;
5049 * Bitfield insert: copy low bits from src1 into a region of src0.
5052 micro_bfi(union tgsi_exec_channel
*dst
,
5053 const union tgsi_exec_channel
*src0
,
5054 const union tgsi_exec_channel
*src1
,
5055 const union tgsi_exec_channel
*src2
,
5056 const union tgsi_exec_channel
*src3
)
5059 for (i
= 0; i
< 4; i
++) {
5060 int width
= src3
->u
[i
];
5061 int offset
= src2
->u
[i
] & 0x1f;
5063 dst
->u
[i
] = src1
->u
[i
];
5065 int bitmask
= ((1 << width
) - 1) << offset
;
5066 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
5072 micro_brev(union tgsi_exec_channel
*dst
,
5073 const union tgsi_exec_channel
*src
)
5075 dst
->u
[0] = util_bitreverse(src
->u
[0]);
5076 dst
->u
[1] = util_bitreverse(src
->u
[1]);
5077 dst
->u
[2] = util_bitreverse(src
->u
[2]);
5078 dst
->u
[3] = util_bitreverse(src
->u
[3]);
5082 micro_popc(union tgsi_exec_channel
*dst
,
5083 const union tgsi_exec_channel
*src
)
5085 dst
->u
[0] = util_bitcount(src
->u
[0]);
5086 dst
->u
[1] = util_bitcount(src
->u
[1]);
5087 dst
->u
[2] = util_bitcount(src
->u
[2]);
5088 dst
->u
[3] = util_bitcount(src
->u
[3]);
5092 micro_lsb(union tgsi_exec_channel
*dst
,
5093 const union tgsi_exec_channel
*src
)
5095 dst
->i
[0] = ffs(src
->u
[0]) - 1;
5096 dst
->i
[1] = ffs(src
->u
[1]) - 1;
5097 dst
->i
[2] = ffs(src
->u
[2]) - 1;
5098 dst
->i
[3] = ffs(src
->u
[3]) - 1;
5102 micro_imsb(union tgsi_exec_channel
*dst
,
5103 const union tgsi_exec_channel
*src
)
5105 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
5106 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
5107 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
5108 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
5112 micro_umsb(union tgsi_exec_channel
*dst
,
5113 const union tgsi_exec_channel
*src
)
5115 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
5116 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
5117 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
5118 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
5123 exec_interp_at_sample(struct tgsi_exec_machine
*mach
,
5124 const struct tgsi_full_instruction
*inst
)
5126 union tgsi_exec_channel index
;
5127 union tgsi_exec_channel index2D
;
5128 union tgsi_exec_channel result
[TGSI_NUM_CHANNELS
];
5129 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
5131 assert(reg
->Register
.File
== TGSI_FILE_INPUT
);
5132 assert(inst
->Src
[1].Register
.File
== TGSI_FILE_IMMEDIATE
);
5134 get_index_registers(mach
, reg
, &index
, &index2D
);
5135 float sample
= mach
->Imms
[inst
->Src
[1].Register
.Index
][inst
->Src
[1].Register
.SwizzleX
];
5137 /* Short cut: sample 0 is like a normal fetch */
5138 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
5139 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)))
5142 fetch_src_file_channel(mach
, TGSI_FILE_INPUT
, chan
, &index
, &index2D
,
5144 if (sample
!= 0.0f
) {
5146 /* TODO: define the samples > 0, but so far we only do fake MSAA */
5150 unsigned pos
= index2D
.i
[chan
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
.i
[chan
];
5152 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
5153 mach
->InputSampleOffsetApply
[pos
](mach
, pos
, chan
, x
, y
, &result
[chan
]);
5155 store_dest(mach
, &result
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
5161 exec_interp_at_offset(struct tgsi_exec_machine
*mach
,
5162 const struct tgsi_full_instruction
*inst
)
5164 union tgsi_exec_channel index
;
5165 union tgsi_exec_channel index2D
;
5166 union tgsi_exec_channel ofsx
;
5167 union tgsi_exec_channel ofsy
;
5168 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
5170 assert(reg
->Register
.File
== TGSI_FILE_INPUT
);
5172 get_index_registers(mach
, reg
, &index
, &index2D
);
5173 unsigned pos
= index2D
.i
[0] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
.i
[0];
5175 fetch_source(mach
, &ofsx
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
5176 fetch_source(mach
, &ofsy
, &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
5178 for (int chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
5179 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)))
5181 union tgsi_exec_channel result
;
5182 fetch_src_file_channel(mach
, TGSI_FILE_INPUT
, chan
, &index
, &index2D
, &result
);
5183 mach
->InputSampleOffsetApply
[pos
](mach
, pos
, chan
, ofsx
.f
[chan
], ofsy
.f
[chan
], &result
);
5184 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
5190 exec_interp_at_centroid(struct tgsi_exec_machine
*mach
,
5191 const struct tgsi_full_instruction
*inst
)
5193 union tgsi_exec_channel index
;
5194 union tgsi_exec_channel index2D
;
5195 union tgsi_exec_channel result
[TGSI_NUM_CHANNELS
];
5196 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
5198 assert(reg
->Register
.File
== TGSI_FILE_INPUT
);
5199 get_index_registers(mach
, reg
, &index
, &index2D
);
5201 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
5202 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)))
5205 /* Here we should add the change to use a sample that lies within the
5206 * primitive (Section 15.2):
5208 * "When interpolating variables declared using centroid in ,
5209 * the variable is sampled at a location within the pixel covered
5210 * by the primitive generating the fragment.
5212 * The built-in functions interpolateAtCentroid ... will sample
5213 * variables as though they were declared with the centroid ...
5216 * Since we only support 1 sample currently, this is just a pass-through.
5218 fetch_src_file_channel(mach
, TGSI_FILE_INPUT
, chan
, &index
, &index2D
,
5220 store_dest(mach
, &result
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
5227 * Execute a TGSI instruction.
5228 * Returns TRUE if a barrier instruction is hit,
5233 struct tgsi_exec_machine
*mach
,
5234 const struct tgsi_full_instruction
*inst
,
5237 union tgsi_exec_channel r
[10];
5241 switch (inst
->Instruction
.Opcode
) {
5242 case TGSI_OPCODE_ARL
:
5243 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5246 case TGSI_OPCODE_MOV
:
5247 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5250 case TGSI_OPCODE_LIT
:
5251 exec_lit(mach
, inst
);
5254 case TGSI_OPCODE_RCP
:
5255 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5258 case TGSI_OPCODE_RSQ
:
5259 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5262 case TGSI_OPCODE_EXP
:
5263 exec_exp(mach
, inst
);
5266 case TGSI_OPCODE_LOG
:
5267 exec_log(mach
, inst
);
5270 case TGSI_OPCODE_MUL
:
5271 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5274 case TGSI_OPCODE_ADD
:
5275 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5278 case TGSI_OPCODE_DP3
:
5279 exec_dp3(mach
, inst
);
5282 case TGSI_OPCODE_DP4
:
5283 exec_dp4(mach
, inst
);
5286 case TGSI_OPCODE_DST
:
5287 exec_dst(mach
, inst
);
5290 case TGSI_OPCODE_MIN
:
5291 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5294 case TGSI_OPCODE_MAX
:
5295 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5298 case TGSI_OPCODE_SLT
:
5299 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5302 case TGSI_OPCODE_SGE
:
5303 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5306 case TGSI_OPCODE_MAD
:
5307 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5310 case TGSI_OPCODE_LRP
:
5311 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5314 case TGSI_OPCODE_SQRT
:
5315 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5318 case TGSI_OPCODE_FRC
:
5319 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5322 case TGSI_OPCODE_FLR
:
5323 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5326 case TGSI_OPCODE_ROUND
:
5327 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5330 case TGSI_OPCODE_EX2
:
5331 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5334 case TGSI_OPCODE_LG2
:
5335 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5338 case TGSI_OPCODE_POW
:
5339 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5342 case TGSI_OPCODE_LDEXP
:
5343 exec_vector_binary(mach
, inst
, micro_ldexp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5346 case TGSI_OPCODE_COS
:
5347 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5350 case TGSI_OPCODE_DDX_FINE
:
5351 exec_vector_unary(mach
, inst
, micro_ddx_fine
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5354 case TGSI_OPCODE_DDX
:
5355 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5358 case TGSI_OPCODE_DDY_FINE
:
5359 exec_vector_unary(mach
, inst
, micro_ddy_fine
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5362 case TGSI_OPCODE_DDY
:
5363 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5366 case TGSI_OPCODE_KILL
:
5370 case TGSI_OPCODE_KILL_IF
:
5371 exec_kill_if (mach
, inst
);
5374 case TGSI_OPCODE_PK2H
:
5375 exec_pk2h(mach
, inst
);
5378 case TGSI_OPCODE_PK2US
:
5382 case TGSI_OPCODE_PK4B
:
5386 case TGSI_OPCODE_PK4UB
:
5390 case TGSI_OPCODE_SEQ
:
5391 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5394 case TGSI_OPCODE_SGT
:
5395 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5398 case TGSI_OPCODE_SIN
:
5399 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5402 case TGSI_OPCODE_SLE
:
5403 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5406 case TGSI_OPCODE_SNE
:
5407 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5410 case TGSI_OPCODE_TEX
:
5411 /* simple texture lookup */
5412 /* src[0] = texcoord */
5413 /* src[1] = sampler unit */
5414 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
5417 case TGSI_OPCODE_TXB
:
5418 /* Texture lookup with lod bias */
5419 /* src[0] = texcoord (src[0].w = LOD bias) */
5420 /* src[1] = sampler unit */
5421 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
5424 case TGSI_OPCODE_TXD
:
5425 /* Texture lookup with explict partial derivatives */
5426 /* src[0] = texcoord */
5427 /* src[1] = d[strq]/dx */
5428 /* src[2] = d[strq]/dy */
5429 /* src[3] = sampler unit */
5430 exec_txd(mach
, inst
);
5433 case TGSI_OPCODE_TXL
:
5434 /* Texture lookup with explit LOD */
5435 /* src[0] = texcoord (src[0].w = LOD) */
5436 /* src[1] = sampler unit */
5437 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
5440 case TGSI_OPCODE_TXP
:
5441 /* Texture lookup with projection */
5442 /* src[0] = texcoord (src[0].w = projection) */
5443 /* src[1] = sampler unit */
5444 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
5447 case TGSI_OPCODE_TG4
:
5448 /* src[0] = texcoord */
5449 /* src[1] = component */
5450 /* src[2] = sampler unit */
5451 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
5454 case TGSI_OPCODE_LODQ
:
5455 /* src[0] = texcoord */
5456 /* src[1] = sampler unit */
5457 exec_lodq(mach
, inst
);
5460 case TGSI_OPCODE_UP2H
:
5461 exec_up2h(mach
, inst
);
5464 case TGSI_OPCODE_UP2US
:
5468 case TGSI_OPCODE_UP4B
:
5472 case TGSI_OPCODE_UP4UB
:
5476 case TGSI_OPCODE_ARR
:
5477 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5480 case TGSI_OPCODE_CAL
:
5481 /* skip the call if no execution channels are enabled */
5482 if (mach
->ExecMask
) {
5485 /* First, record the depths of the execution stacks.
5486 * This is important for deeply nested/looped return statements.
5487 * We have to unwind the stacks by the correct amount. For a
5488 * real code generator, we could determine the number of entries
5489 * to pop off each stack with simple static analysis and avoid
5490 * implementing this data structure at run time.
5492 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
5493 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
5494 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
5495 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
5496 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
5497 /* note that PC was already incremented above */
5498 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
5500 mach
->CallStackTop
++;
5502 /* Second, push the Cond, Loop, Cont, Func stacks */
5503 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5504 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5505 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5506 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
5507 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5508 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
5510 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5511 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5512 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5513 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
5514 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5515 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
5517 /* Finally, jump to the subroutine. The label is a pointer
5518 * (an instruction number) to the BGNSUB instruction.
5520 *pc
= inst
->Label
.Label
;
5521 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
5522 == TGSI_OPCODE_BGNSUB
);
5526 case TGSI_OPCODE_RET
:
5527 mach
->FuncMask
&= ~mach
->ExecMask
;
5528 UPDATE_EXEC_MASK(mach
);
5530 if (mach
->FuncMask
== 0x0) {
5531 /* really return now (otherwise, keep executing */
5533 if (mach
->CallStackTop
== 0) {
5534 /* returning from main() */
5535 mach
->CondStackTop
= 0;
5536 mach
->LoopStackTop
= 0;
5537 mach
->ContStackTop
= 0;
5538 mach
->LoopLabelStackTop
= 0;
5539 mach
->SwitchStackTop
= 0;
5540 mach
->BreakStackTop
= 0;
5545 assert(mach
->CallStackTop
> 0);
5546 mach
->CallStackTop
--;
5548 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5549 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5551 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5552 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5554 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5555 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5557 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5558 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5560 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5561 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5563 assert(mach
->FuncStackTop
> 0);
5564 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5566 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5568 UPDATE_EXEC_MASK(mach
);
5572 case TGSI_OPCODE_SSG
:
5573 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5576 case TGSI_OPCODE_CMP
:
5577 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5580 case TGSI_OPCODE_DIV
:
5581 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5584 case TGSI_OPCODE_DP2
:
5585 exec_dp2(mach
, inst
);
5588 case TGSI_OPCODE_IF
:
5590 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5591 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5592 FETCH( &r
[0], 0, TGSI_CHAN_X
);
5593 /* update CondMask */
5595 mach
->CondMask
&= ~0x1;
5598 mach
->CondMask
&= ~0x2;
5601 mach
->CondMask
&= ~0x4;
5604 mach
->CondMask
&= ~0x8;
5606 UPDATE_EXEC_MASK(mach
);
5607 /* Todo: If CondMask==0, jump to ELSE */
5610 case TGSI_OPCODE_UIF
:
5612 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5613 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5614 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
5615 /* update CondMask */
5617 mach
->CondMask
&= ~0x1;
5620 mach
->CondMask
&= ~0x2;
5623 mach
->CondMask
&= ~0x4;
5626 mach
->CondMask
&= ~0x8;
5628 UPDATE_EXEC_MASK(mach
);
5629 /* Todo: If CondMask==0, jump to ELSE */
5632 case TGSI_OPCODE_ELSE
:
5633 /* invert CondMask wrt previous mask */
5636 assert(mach
->CondStackTop
> 0);
5637 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
5638 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
5639 UPDATE_EXEC_MASK(mach
);
5640 /* Todo: If CondMask==0, jump to ENDIF */
5644 case TGSI_OPCODE_ENDIF
:
5646 assert(mach
->CondStackTop
> 0);
5647 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
5648 UPDATE_EXEC_MASK(mach
);
5651 case TGSI_OPCODE_END
:
5652 /* make sure we end primitives which haven't
5653 * been explicitly emitted */
5654 conditional_emit_primitive(mach
);
5655 /* halt execution */
5659 case TGSI_OPCODE_CEIL
:
5660 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5663 case TGSI_OPCODE_I2F
:
5664 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
5667 case TGSI_OPCODE_NOT
:
5668 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5671 case TGSI_OPCODE_TRUNC
:
5672 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5675 case TGSI_OPCODE_SHL
:
5676 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5679 case TGSI_OPCODE_AND
:
5680 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5683 case TGSI_OPCODE_OR
:
5684 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5687 case TGSI_OPCODE_MOD
:
5688 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5691 case TGSI_OPCODE_XOR
:
5692 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5695 case TGSI_OPCODE_TXF
:
5696 exec_txf(mach
, inst
);
5699 case TGSI_OPCODE_TXQ
:
5700 exec_txq(mach
, inst
);
5703 case TGSI_OPCODE_EMIT
:
5704 emit_vertex(mach
, inst
);
5707 case TGSI_OPCODE_ENDPRIM
:
5708 emit_primitive(mach
, inst
);
5711 case TGSI_OPCODE_BGNLOOP
:
5712 /* push LoopMask and ContMasks */
5713 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5714 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5715 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5716 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5718 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5719 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5720 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
5721 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5722 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
5725 case TGSI_OPCODE_ENDLOOP
:
5726 /* Restore ContMask, but don't pop */
5727 assert(mach
->ContStackTop
> 0);
5728 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
5729 UPDATE_EXEC_MASK(mach
);
5730 if (mach
->ExecMask
) {
5731 /* repeat loop: jump to instruction just past BGNLOOP */
5732 assert(mach
->LoopLabelStackTop
> 0);
5733 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
5736 /* exit loop: pop LoopMask */
5737 assert(mach
->LoopStackTop
> 0);
5738 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
5740 assert(mach
->ContStackTop
> 0);
5741 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
5742 assert(mach
->LoopLabelStackTop
> 0);
5743 --mach
->LoopLabelStackTop
;
5745 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
5747 UPDATE_EXEC_MASK(mach
);
5750 case TGSI_OPCODE_BRK
:
5754 case TGSI_OPCODE_CONT
:
5755 /* turn off cont channels for each enabled exec channel */
5756 mach
->ContMask
&= ~mach
->ExecMask
;
5757 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5758 UPDATE_EXEC_MASK(mach
);
5761 case TGSI_OPCODE_BGNSUB
:
5765 case TGSI_OPCODE_ENDSUB
:
5767 * XXX: This really should be a no-op. We should never reach this opcode.
5770 assert(mach
->CallStackTop
> 0);
5771 mach
->CallStackTop
--;
5773 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5774 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5776 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5777 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5779 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5780 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5782 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5783 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5785 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5786 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5788 assert(mach
->FuncStackTop
> 0);
5789 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5791 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5793 UPDATE_EXEC_MASK(mach
);
5796 case TGSI_OPCODE_NOP
:
5799 case TGSI_OPCODE_F2I
:
5800 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5803 case TGSI_OPCODE_FSEQ
:
5804 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5807 case TGSI_OPCODE_FSGE
:
5808 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5811 case TGSI_OPCODE_FSLT
:
5812 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5815 case TGSI_OPCODE_FSNE
:
5816 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5819 case TGSI_OPCODE_IDIV
:
5820 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5823 case TGSI_OPCODE_IMAX
:
5824 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5827 case TGSI_OPCODE_IMIN
:
5828 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5831 case TGSI_OPCODE_INEG
:
5832 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5835 case TGSI_OPCODE_ISGE
:
5836 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5839 case TGSI_OPCODE_ISHR
:
5840 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5843 case TGSI_OPCODE_ISLT
:
5844 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5847 case TGSI_OPCODE_F2U
:
5848 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5851 case TGSI_OPCODE_U2F
:
5852 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
5855 case TGSI_OPCODE_UADD
:
5856 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5859 case TGSI_OPCODE_UDIV
:
5860 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5863 case TGSI_OPCODE_UMAD
:
5864 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5867 case TGSI_OPCODE_UMAX
:
5868 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5871 case TGSI_OPCODE_UMIN
:
5872 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5875 case TGSI_OPCODE_UMOD
:
5876 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5879 case TGSI_OPCODE_UMUL
:
5880 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5883 case TGSI_OPCODE_IMUL_HI
:
5884 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5887 case TGSI_OPCODE_UMUL_HI
:
5888 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5891 case TGSI_OPCODE_USEQ
:
5892 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5895 case TGSI_OPCODE_USGE
:
5896 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5899 case TGSI_OPCODE_USHR
:
5900 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5903 case TGSI_OPCODE_USLT
:
5904 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5907 case TGSI_OPCODE_USNE
:
5908 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5911 case TGSI_OPCODE_SWITCH
:
5912 exec_switch(mach
, inst
);
5915 case TGSI_OPCODE_CASE
:
5916 exec_case(mach
, inst
);
5919 case TGSI_OPCODE_DEFAULT
:
5923 case TGSI_OPCODE_ENDSWITCH
:
5924 exec_endswitch(mach
);
5927 case TGSI_OPCODE_SAMPLE_I
:
5928 exec_txf(mach
, inst
);
5931 case TGSI_OPCODE_SAMPLE_I_MS
:
5932 exec_txf(mach
, inst
);
5935 case TGSI_OPCODE_SAMPLE
:
5936 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
5939 case TGSI_OPCODE_SAMPLE_B
:
5940 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
5943 case TGSI_OPCODE_SAMPLE_C
:
5944 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
5947 case TGSI_OPCODE_SAMPLE_C_LZ
:
5948 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
5951 case TGSI_OPCODE_SAMPLE_D
:
5952 exec_sample_d(mach
, inst
);
5955 case TGSI_OPCODE_SAMPLE_L
:
5956 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
5959 case TGSI_OPCODE_GATHER4
:
5960 exec_sample(mach
, inst
, TEX_MODIFIER_GATHER
, FALSE
);
5963 case TGSI_OPCODE_SVIEWINFO
:
5964 exec_txq(mach
, inst
);
5967 case TGSI_OPCODE_SAMPLE_POS
:
5971 case TGSI_OPCODE_SAMPLE_INFO
:
5975 case TGSI_OPCODE_LOD
:
5976 exec_lodq(mach
, inst
);
5979 case TGSI_OPCODE_UARL
:
5980 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5983 case TGSI_OPCODE_UCMP
:
5984 exec_ucmp(mach
, inst
);
5987 case TGSI_OPCODE_IABS
:
5988 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5991 case TGSI_OPCODE_ISSG
:
5992 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5995 case TGSI_OPCODE_TEX2
:
5996 /* simple texture lookup */
5997 /* src[0] = texcoord */
5998 /* src[1] = compare */
5999 /* src[2] = sampler unit */
6000 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
6002 case TGSI_OPCODE_TXB2
:
6003 /* simple texture lookup */
6004 /* src[0] = texcoord */
6006 /* src[2] = sampler unit */
6007 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
6009 case TGSI_OPCODE_TXL2
:
6010 /* simple texture lookup */
6011 /* src[0] = texcoord */
6013 /* src[2] = sampler unit */
6014 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
6017 case TGSI_OPCODE_IBFE
:
6018 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
6020 case TGSI_OPCODE_UBFE
:
6021 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
6023 case TGSI_OPCODE_BFI
:
6024 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
6026 case TGSI_OPCODE_BREV
:
6027 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
6029 case TGSI_OPCODE_POPC
:
6030 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
6032 case TGSI_OPCODE_LSB
:
6033 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
6035 case TGSI_OPCODE_IMSB
:
6036 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
6038 case TGSI_OPCODE_UMSB
:
6039 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
6042 case TGSI_OPCODE_F2D
:
6043 exec_t_2_64(mach
, inst
, micro_f2d
, TGSI_EXEC_DATA_FLOAT
);
6046 case TGSI_OPCODE_D2F
:
6047 exec_64_2_t(mach
, inst
, micro_d2f
, TGSI_EXEC_DATA_FLOAT
);
6050 case TGSI_OPCODE_DABS
:
6051 exec_double_unary(mach
, inst
, micro_dabs
);
6054 case TGSI_OPCODE_DNEG
:
6055 exec_double_unary(mach
, inst
, micro_dneg
);
6058 case TGSI_OPCODE_DADD
:
6059 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
6062 case TGSI_OPCODE_DDIV
:
6063 exec_double_binary(mach
, inst
, micro_ddiv
, TGSI_EXEC_DATA_DOUBLE
);
6066 case TGSI_OPCODE_DMUL
:
6067 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
6070 case TGSI_OPCODE_DMAX
:
6071 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
6074 case TGSI_OPCODE_DMIN
:
6075 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
6078 case TGSI_OPCODE_DSLT
:
6079 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
6082 case TGSI_OPCODE_DSGE
:
6083 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
6086 case TGSI_OPCODE_DSEQ
:
6087 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
6090 case TGSI_OPCODE_DSNE
:
6091 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
6094 case TGSI_OPCODE_DRCP
:
6095 exec_double_unary(mach
, inst
, micro_drcp
);
6098 case TGSI_OPCODE_DSQRT
:
6099 exec_double_unary(mach
, inst
, micro_dsqrt
);
6102 case TGSI_OPCODE_DRSQ
:
6103 exec_double_unary(mach
, inst
, micro_drsq
);
6106 case TGSI_OPCODE_DMAD
:
6107 exec_double_trinary(mach
, inst
, micro_dmad
);
6110 case TGSI_OPCODE_DFRAC
:
6111 exec_double_unary(mach
, inst
, micro_dfrac
);
6114 case TGSI_OPCODE_DLDEXP
:
6115 exec_dldexp(mach
, inst
);
6118 case TGSI_OPCODE_DFRACEXP
:
6119 exec_dfracexp(mach
, inst
);
6122 case TGSI_OPCODE_I2D
:
6123 exec_t_2_64(mach
, inst
, micro_i2d
, TGSI_EXEC_DATA_INT
);
6126 case TGSI_OPCODE_D2I
:
6127 exec_64_2_t(mach
, inst
, micro_d2i
, TGSI_EXEC_DATA_INT
);
6130 case TGSI_OPCODE_U2D
:
6131 exec_t_2_64(mach
, inst
, micro_u2d
, TGSI_EXEC_DATA_UINT
);
6134 case TGSI_OPCODE_D2U
:
6135 exec_64_2_t(mach
, inst
, micro_d2u
, TGSI_EXEC_DATA_INT
);
6138 case TGSI_OPCODE_LOAD
:
6139 exec_load(mach
, inst
);
6142 case TGSI_OPCODE_STORE
:
6143 exec_store(mach
, inst
);
6146 case TGSI_OPCODE_ATOMUADD
:
6147 case TGSI_OPCODE_ATOMXCHG
:
6148 case TGSI_OPCODE_ATOMCAS
:
6149 case TGSI_OPCODE_ATOMAND
:
6150 case TGSI_OPCODE_ATOMOR
:
6151 case TGSI_OPCODE_ATOMXOR
:
6152 case TGSI_OPCODE_ATOMUMIN
:
6153 case TGSI_OPCODE_ATOMUMAX
:
6154 case TGSI_OPCODE_ATOMIMIN
:
6155 case TGSI_OPCODE_ATOMIMAX
:
6156 case TGSI_OPCODE_ATOMFADD
:
6157 exec_atomop(mach
, inst
);
6160 case TGSI_OPCODE_RESQ
:
6161 exec_resq(mach
, inst
);
6163 case TGSI_OPCODE_BARRIER
:
6164 case TGSI_OPCODE_MEMBAR
:
6168 case TGSI_OPCODE_I64ABS
:
6169 exec_double_unary(mach
, inst
, micro_i64abs
);
6172 case TGSI_OPCODE_I64SSG
:
6173 exec_double_unary(mach
, inst
, micro_i64sgn
);
6176 case TGSI_OPCODE_I64NEG
:
6177 exec_double_unary(mach
, inst
, micro_i64neg
);
6180 case TGSI_OPCODE_U64SEQ
:
6181 exec_double_binary(mach
, inst
, micro_u64seq
, TGSI_EXEC_DATA_UINT
);
6184 case TGSI_OPCODE_U64SNE
:
6185 exec_double_binary(mach
, inst
, micro_u64sne
, TGSI_EXEC_DATA_UINT
);
6188 case TGSI_OPCODE_I64SLT
:
6189 exec_double_binary(mach
, inst
, micro_i64slt
, TGSI_EXEC_DATA_UINT
);
6191 case TGSI_OPCODE_U64SLT
:
6192 exec_double_binary(mach
, inst
, micro_u64slt
, TGSI_EXEC_DATA_UINT
);
6195 case TGSI_OPCODE_I64SGE
:
6196 exec_double_binary(mach
, inst
, micro_i64sge
, TGSI_EXEC_DATA_UINT
);
6198 case TGSI_OPCODE_U64SGE
:
6199 exec_double_binary(mach
, inst
, micro_u64sge
, TGSI_EXEC_DATA_UINT
);
6202 case TGSI_OPCODE_I64MIN
:
6203 exec_double_binary(mach
, inst
, micro_i64min
, TGSI_EXEC_DATA_INT64
);
6205 case TGSI_OPCODE_U64MIN
:
6206 exec_double_binary(mach
, inst
, micro_u64min
, TGSI_EXEC_DATA_UINT64
);
6208 case TGSI_OPCODE_I64MAX
:
6209 exec_double_binary(mach
, inst
, micro_i64max
, TGSI_EXEC_DATA_INT64
);
6211 case TGSI_OPCODE_U64MAX
:
6212 exec_double_binary(mach
, inst
, micro_u64max
, TGSI_EXEC_DATA_UINT64
);
6214 case TGSI_OPCODE_U64ADD
:
6215 exec_double_binary(mach
, inst
, micro_u64add
, TGSI_EXEC_DATA_UINT64
);
6217 case TGSI_OPCODE_U64MUL
:
6218 exec_double_binary(mach
, inst
, micro_u64mul
, TGSI_EXEC_DATA_UINT64
);
6220 case TGSI_OPCODE_U64SHL
:
6221 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shl
);
6223 case TGSI_OPCODE_I64SHR
:
6224 exec_arg0_64_arg1_32(mach
, inst
, micro_i64shr
);
6226 case TGSI_OPCODE_U64SHR
:
6227 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shr
);
6229 case TGSI_OPCODE_U64DIV
:
6230 exec_double_binary(mach
, inst
, micro_u64div
, TGSI_EXEC_DATA_UINT64
);
6232 case TGSI_OPCODE_I64DIV
:
6233 exec_double_binary(mach
, inst
, micro_i64div
, TGSI_EXEC_DATA_INT64
);
6235 case TGSI_OPCODE_U64MOD
:
6236 exec_double_binary(mach
, inst
, micro_u64mod
, TGSI_EXEC_DATA_UINT64
);
6238 case TGSI_OPCODE_I64MOD
:
6239 exec_double_binary(mach
, inst
, micro_i64mod
, TGSI_EXEC_DATA_INT64
);
6242 case TGSI_OPCODE_F2U64
:
6243 exec_t_2_64(mach
, inst
, micro_f2u64
, TGSI_EXEC_DATA_FLOAT
);
6246 case TGSI_OPCODE_F2I64
:
6247 exec_t_2_64(mach
, inst
, micro_f2i64
, TGSI_EXEC_DATA_FLOAT
);
6250 case TGSI_OPCODE_U2I64
:
6251 exec_t_2_64(mach
, inst
, micro_u2i64
, TGSI_EXEC_DATA_INT
);
6253 case TGSI_OPCODE_I2I64
:
6254 exec_t_2_64(mach
, inst
, micro_i2i64
, TGSI_EXEC_DATA_INT
);
6257 case TGSI_OPCODE_D2U64
:
6258 exec_double_unary(mach
, inst
, micro_d2u64
);
6261 case TGSI_OPCODE_D2I64
:
6262 exec_double_unary(mach
, inst
, micro_d2i64
);
6265 case TGSI_OPCODE_U642F
:
6266 exec_64_2_t(mach
, inst
, micro_u642f
, TGSI_EXEC_DATA_FLOAT
);
6268 case TGSI_OPCODE_I642F
:
6269 exec_64_2_t(mach
, inst
, micro_i642f
, TGSI_EXEC_DATA_FLOAT
);
6272 case TGSI_OPCODE_U642D
:
6273 exec_double_unary(mach
, inst
, micro_u642d
);
6275 case TGSI_OPCODE_I642D
:
6276 exec_double_unary(mach
, inst
, micro_i642d
);
6278 case TGSI_OPCODE_INTERP_SAMPLE
:
6279 exec_interp_at_sample(mach
, inst
);
6281 case TGSI_OPCODE_INTERP_OFFSET
:
6282 exec_interp_at_offset(mach
, inst
);
6284 case TGSI_OPCODE_INTERP_CENTROID
:
6285 exec_interp_at_centroid(mach
, inst
);
6294 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine
*mach
)
6296 uint default_mask
= 0xf;
6298 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
6299 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
6301 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
6302 for (unsigned i
= 0; i
< TGSI_MAX_VERTEX_STREAMS
; i
++) {
6303 mach
->Temps
[temp_prim_idxs
[i
].idx
].xyzw
[temp_prim_idxs
[i
].chan
].u
[0] = 0;
6304 mach
->Primitives
[i
][0] = 0;
6306 /* GS runs on a single primitive for now */
6310 if (mach
->NonHelperMask
== 0)
6311 mach
->NonHelperMask
= default_mask
;
6312 mach
->CondMask
= default_mask
;
6313 mach
->LoopMask
= default_mask
;
6314 mach
->ContMask
= default_mask
;
6315 mach
->FuncMask
= default_mask
;
6316 mach
->ExecMask
= default_mask
;
6318 mach
->Switch
.mask
= default_mask
;
6320 assert(mach
->CondStackTop
== 0);
6321 assert(mach
->LoopStackTop
== 0);
6322 assert(mach
->ContStackTop
== 0);
6323 assert(mach
->SwitchStackTop
== 0);
6324 assert(mach
->BreakStackTop
== 0);
6325 assert(mach
->CallStackTop
== 0);
6329 * Run TGSI interpreter.
6330 * \return bitmask of "alive" quad components
6333 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
, int start_pc
)
6337 mach
->pc
= start_pc
;
6340 tgsi_exec_machine_setup_masks(mach
);
6342 /* execute declarations (interpolants) */
6343 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
6344 exec_declaration( mach
, mach
->Declarations
+i
);
6350 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
6351 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
6355 memset(mach
->Temps
, 0, sizeof(temps
));
6357 memset(mach
->Outputs
, 0, sizeof(outputs
));
6358 memset(temps
, 0, sizeof(temps
));
6359 memset(outputs
, 0, sizeof(outputs
));
6363 /* execute instructions, until pc is set to -1 */
6364 while (mach
->pc
!= -1) {
6365 boolean barrier_hit
;
6369 tgsi_dump_instruction(&mach
->Instructions
[mach
->pc
], inst
++);
6372 assert(mach
->pc
< (int) mach
->NumInstructions
);
6373 barrier_hit
= exec_instruction(mach
, mach
->Instructions
+ mach
->pc
, &mach
->pc
);
6375 /* for compute shaders if we hit a barrier return now for later rescheduling */
6376 if (barrier_hit
&& mach
->ShaderType
== PIPE_SHADER_COMPUTE
)
6380 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
6381 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
6384 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
6385 debug_printf("TEMP[%2u] = ", i
);
6386 for (j
= 0; j
< 4; j
++) {
6390 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6391 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
6392 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
6393 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
6394 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
6398 if (mach
->Outputs
) {
6399 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
6400 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
6403 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
6404 debug_printf("OUT[%2u] = ", i
);
6405 for (j
= 0; j
< 4; j
++) {
6409 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6410 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
6411 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
6412 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
6413 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
6423 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
6424 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
6426 * Scale back depth component.
6428 for (i
= 0; i
< 4; i
++)
6429 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
6433 /* Strictly speaking, these assertions aren't really needed but they
6434 * can potentially catch some bugs in the control flow code.
6436 assert(mach
->CondStackTop
== 0);
6437 assert(mach
->LoopStackTop
== 0);
6438 assert(mach
->ContStackTop
== 0);
6439 assert(mach
->SwitchStackTop
== 0);
6440 assert(mach
->BreakStackTop
== 0);
6441 assert(mach
->CallStackTop
== 0);
6443 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];