projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
softpipe: try to beat new dx10-style sample opcodes into shape
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define FAST_MATH 0
66
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
71
72 static void
73 micro_abs(union tgsi_exec_channel *dst,
74 const union tgsi_exec_channel *src)
75 {
76 dst->f[0] = fabsf(src->f[0]);
77 dst->f[1] = fabsf(src->f[1]);
78 dst->f[2] = fabsf(src->f[2]);
79 dst->f[3] = fabsf(src->f[3]);
80 }
81
82 static void
83 micro_arl(union tgsi_exec_channel *dst,
84 const union tgsi_exec_channel *src)
85 {
86 dst->i[0] = (int)floorf(src->f[0]);
87 dst->i[1] = (int)floorf(src->f[1]);
88 dst->i[2] = (int)floorf(src->f[2]);
89 dst->i[3] = (int)floorf(src->f[3]);
90 }
91
92 static void
93 micro_arr(union tgsi_exec_channel *dst,
94 const union tgsi_exec_channel *src)
95 {
96 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
97 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
98 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
99 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
100 }
101
102 static void
103 micro_ceil(union tgsi_exec_channel *dst,
104 const union tgsi_exec_channel *src)
105 {
106 dst->f[0] = ceilf(src->f[0]);
107 dst->f[1] = ceilf(src->f[1]);
108 dst->f[2] = ceilf(src->f[2]);
109 dst->f[3] = ceilf(src->f[3]);
110 }
111
112 static void
113 micro_clamp(union tgsi_exec_channel *dst,
114 const union tgsi_exec_channel *src0,
115 const union tgsi_exec_channel *src1,
116 const union tgsi_exec_channel *src2)
117 {
118 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
119 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
120 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
121 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
122 }
123
124 static void
125 micro_cmp(union tgsi_exec_channel *dst,
126 const union tgsi_exec_channel *src0,
127 const union tgsi_exec_channel *src1,
128 const union tgsi_exec_channel *src2)
129 {
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
134 }
135
136 static void
137 micro_cnd(union tgsi_exec_channel *dst,
138 const union tgsi_exec_channel *src0,
139 const union tgsi_exec_channel *src1,
140 const union tgsi_exec_channel *src2)
141 {
142 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
143 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
144 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
145 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
146 }
147
148 static void
149 micro_cos(union tgsi_exec_channel *dst,
150 const union tgsi_exec_channel *src)
151 {
152 dst->f[0] = cosf(src->f[0]);
153 dst->f[1] = cosf(src->f[1]);
154 dst->f[2] = cosf(src->f[2]);
155 dst->f[3] = cosf(src->f[3]);
156 }
157
158 static void
159 micro_ddx(union tgsi_exec_channel *dst,
160 const union tgsi_exec_channel *src)
161 {
162 dst->f[0] =
163 dst->f[1] =
164 dst->f[2] =
165 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
166 }
167
168 static void
169 micro_ddy(union tgsi_exec_channel *dst,
170 const union tgsi_exec_channel *src)
171 {
172 dst->f[0] =
173 dst->f[1] =
174 dst->f[2] =
175 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
176 }
177
178 static void
179 micro_exp2(union tgsi_exec_channel *dst,
180 const union tgsi_exec_channel *src)
181 {
182 #if FAST_MATH
183 dst->f[0] = util_fast_exp2(src->f[0]);
184 dst->f[1] = util_fast_exp2(src->f[1]);
185 dst->f[2] = util_fast_exp2(src->f[2]);
186 dst->f[3] = util_fast_exp2(src->f[3]);
187 #else
188 #if DEBUG
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
190 uint i;
191 union tgsi_exec_channel clamped;
192
193 for (i = 0; i < 4; i++) {
194 if (src->f[i] > 127.99999f) {
195 clamped.f[i] = 127.99999f;
196 } else if (src->f[i] < -126.99999f) {
197 clamped.f[i] = -126.99999f;
198 } else {
199 clamped.f[i] = src->f[i];
200 }
201 }
202 src = &clamped;
203 #endif /* DEBUG */
204
205 dst->f[0] = powf(2.0f, src->f[0]);
206 dst->f[1] = powf(2.0f, src->f[1]);
207 dst->f[2] = powf(2.0f, src->f[2]);
208 dst->f[3] = powf(2.0f, src->f[3]);
209 #endif /* FAST_MATH */
210 }
211
212 static void
213 micro_flr(union tgsi_exec_channel *dst,
214 const union tgsi_exec_channel *src)
215 {
216 dst->f[0] = floorf(src->f[0]);
217 dst->f[1] = floorf(src->f[1]);
218 dst->f[2] = floorf(src->f[2]);
219 dst->f[3] = floorf(src->f[3]);
220 }
221
222 static void
223 micro_frc(union tgsi_exec_channel *dst,
224 const union tgsi_exec_channel *src)
225 {
226 dst->f[0] = src->f[0] - floorf(src->f[0]);
227 dst->f[1] = src->f[1] - floorf(src->f[1]);
228 dst->f[2] = src->f[2] - floorf(src->f[2]);
229 dst->f[3] = src->f[3] - floorf(src->f[3]);
230 }
231
232 static void
233 micro_iabs(union tgsi_exec_channel *dst,
234 const union tgsi_exec_channel *src)
235 {
236 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
237 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
238 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
239 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
240 }
241
242 static void
243 micro_ineg(union tgsi_exec_channel *dst,
244 const union tgsi_exec_channel *src)
245 {
246 dst->i[0] = -src->i[0];
247 dst->i[1] = -src->i[1];
248 dst->i[2] = -src->i[2];
249 dst->i[3] = -src->i[3];
250 }
251
252 static void
253 micro_lg2(union tgsi_exec_channel *dst,
254 const union tgsi_exec_channel *src)
255 {
256 #if FAST_MATH
257 dst->f[0] = util_fast_log2(src->f[0]);
258 dst->f[1] = util_fast_log2(src->f[1]);
259 dst->f[2] = util_fast_log2(src->f[2]);
260 dst->f[3] = util_fast_log2(src->f[3]);
261 #else
262 dst->f[0] = logf(src->f[0]) * 1.442695f;
263 dst->f[1] = logf(src->f[1]) * 1.442695f;
264 dst->f[2] = logf(src->f[2]) * 1.442695f;
265 dst->f[3] = logf(src->f[3]) * 1.442695f;
266 #endif
267 }
268
269 static void
270 micro_lrp(union tgsi_exec_channel *dst,
271 const union tgsi_exec_channel *src0,
272 const union tgsi_exec_channel *src1,
273 const union tgsi_exec_channel *src2)
274 {
275 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
276 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
277 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
278 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
279 }
280
281 static void
282 micro_mad(union tgsi_exec_channel *dst,
283 const union tgsi_exec_channel *src0,
284 const union tgsi_exec_channel *src1,
285 const union tgsi_exec_channel *src2)
286 {
287 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
288 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
289 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
290 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
291 }
292
293 static void
294 micro_mov(union tgsi_exec_channel *dst,
295 const union tgsi_exec_channel *src)
296 {
297 dst->u[0] = src->u[0];
298 dst->u[1] = src->u[1];
299 dst->u[2] = src->u[2];
300 dst->u[3] = src->u[3];
301 }
302
303 static void
304 micro_rcp(union tgsi_exec_channel *dst,
305 const union tgsi_exec_channel *src)
306 {
307 #if 0 /* for debugging */
308 assert(src->f[0] != 0.0f);
309 assert(src->f[1] != 0.0f);
310 assert(src->f[2] != 0.0f);
311 assert(src->f[3] != 0.0f);
312 #endif
313 dst->f[0] = 1.0f / src->f[0];
314 dst->f[1] = 1.0f / src->f[1];
315 dst->f[2] = 1.0f / src->f[2];
316 dst->f[3] = 1.0f / src->f[3];
317 }
318
319 static void
320 micro_rnd(union tgsi_exec_channel *dst,
321 const union tgsi_exec_channel *src)
322 {
323 dst->f[0] = floorf(src->f[0] + 0.5f);
324 dst->f[1] = floorf(src->f[1] + 0.5f);
325 dst->f[2] = floorf(src->f[2] + 0.5f);
326 dst->f[3] = floorf(src->f[3] + 0.5f);
327 }
328
329 static void
330 micro_rsq(union tgsi_exec_channel *dst,
331 const union tgsi_exec_channel *src)
332 {
333 #if 0 /* for debugging */
334 assert(src->f[0] != 0.0f);
335 assert(src->f[1] != 0.0f);
336 assert(src->f[2] != 0.0f);
337 assert(src->f[3] != 0.0f);
338 #endif
339 dst->f[0] = 1.0f / sqrtf(fabsf(src->f[0]));
340 dst->f[1] = 1.0f / sqrtf(fabsf(src->f[1]));
341 dst->f[2] = 1.0f / sqrtf(fabsf(src->f[2]));
342 dst->f[3] = 1.0f / sqrtf(fabsf(src->f[3]));
343 }
344
345 static void
346 micro_sqrt(union tgsi_exec_channel *dst,
347 const union tgsi_exec_channel *src)
348 {
349 dst->f[0] = sqrtf(fabsf(src->f[0]));
350 dst->f[1] = sqrtf(fabsf(src->f[1]));
351 dst->f[2] = sqrtf(fabsf(src->f[2]));
352 dst->f[3] = sqrtf(fabsf(src->f[3]));
353 }
354
355 static void
356 micro_seq(union tgsi_exec_channel *dst,
357 const union tgsi_exec_channel *src0,
358 const union tgsi_exec_channel *src1)
359 {
360 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
361 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
362 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
363 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
364 }
365
366 static void
367 micro_sge(union tgsi_exec_channel *dst,
368 const union tgsi_exec_channel *src0,
369 const union tgsi_exec_channel *src1)
370 {
371 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
372 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
373 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
374 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
375 }
376
377 static void
378 micro_sgn(union tgsi_exec_channel *dst,
379 const union tgsi_exec_channel *src)
380 {
381 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
382 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
383 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
384 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
385 }
386
387 static void
388 micro_isgn(union tgsi_exec_channel *dst,
389 const union tgsi_exec_channel *src)
390 {
391 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
392 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
393 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
394 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
395 }
396
397 static void
398 micro_sgt(union tgsi_exec_channel *dst,
399 const union tgsi_exec_channel *src0,
400 const union tgsi_exec_channel *src1)
401 {
402 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
403 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
404 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
405 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
406 }
407
408 static void
409 micro_sin(union tgsi_exec_channel *dst,
410 const union tgsi_exec_channel *src)
411 {
412 dst->f[0] = sinf(src->f[0]);
413 dst->f[1] = sinf(src->f[1]);
414 dst->f[2] = sinf(src->f[2]);
415 dst->f[3] = sinf(src->f[3]);
416 }
417
418 static void
419 micro_sle(union tgsi_exec_channel *dst,
420 const union tgsi_exec_channel *src0,
421 const union tgsi_exec_channel *src1)
422 {
423 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
424 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
425 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
426 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
427 }
428
429 static void
430 micro_slt(union tgsi_exec_channel *dst,
431 const union tgsi_exec_channel *src0,
432 const union tgsi_exec_channel *src1)
433 {
434 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
435 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
436 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
437 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
438 }
439
440 static void
441 micro_sne(union tgsi_exec_channel *dst,
442 const union tgsi_exec_channel *src0,
443 const union tgsi_exec_channel *src1)
444 {
445 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
446 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
447 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
448 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
449 }
450
451 static void
452 micro_sfl(union tgsi_exec_channel *dst)
453 {
454 dst->f[0] = 0.0f;
455 dst->f[1] = 0.0f;
456 dst->f[2] = 0.0f;
457 dst->f[3] = 0.0f;
458 }
459
460 static void
461 micro_str(union tgsi_exec_channel *dst)
462 {
463 dst->f[0] = 1.0f;
464 dst->f[1] = 1.0f;
465 dst->f[2] = 1.0f;
466 dst->f[3] = 1.0f;
467 }
468
469 static void
470 micro_trunc(union tgsi_exec_channel *dst,
471 const union tgsi_exec_channel *src)
472 {
473 dst->f[0] = (float)(int)src->f[0];
474 dst->f[1] = (float)(int)src->f[1];
475 dst->f[2] = (float)(int)src->f[2];
476 dst->f[3] = (float)(int)src->f[3];
477 }
478
479
480 enum tgsi_exec_datatype {
481 TGSI_EXEC_DATA_FLOAT,
482 TGSI_EXEC_DATA_INT,
483 TGSI_EXEC_DATA_UINT
484 };
485
486 /*
487 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
488 */
489 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
490 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
491 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
492 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
493 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
494 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
495
496
497 /** The execution mask depends on the conditional mask and the loop mask */
498 #define UPDATE_EXEC_MASK(MACH) \
499 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
500
501
502 static const union tgsi_exec_channel ZeroVec =
503 { { 0.0, 0.0, 0.0, 0.0 } };
504
505 static const union tgsi_exec_channel OneVec = {
506 {1.0f, 1.0f, 1.0f, 1.0f}
507 };
508
509 static const union tgsi_exec_channel P128Vec = {
510 {128.0f, 128.0f, 128.0f, 128.0f}
511 };
512
513 static const union tgsi_exec_channel M128Vec = {
514 {-128.0f, -128.0f, -128.0f, -128.0f}
515 };
516
517
518 /**
519 * Assert that none of the float values in 'chan' are infinite or NaN.
520 * NaN and Inf may occur normally during program execution and should
521 * not lead to crashes, etc. But when debugging, it's helpful to catch
522 * them.
523 */
524 static INLINE void
525 check_inf_or_nan(const union tgsi_exec_channel *chan)
526 {
527 assert(!util_is_inf_or_nan((chan)->f[0]));
528 assert(!util_is_inf_or_nan((chan)->f[1]));
529 assert(!util_is_inf_or_nan((chan)->f[2]));
530 assert(!util_is_inf_or_nan((chan)->f[3]));
531 }
532
533
534 #ifdef DEBUG
535 static void
536 print_chan(const char *msg, const union tgsi_exec_channel *chan)
537 {
538 debug_printf("%s = {%f, %f, %f, %f}\n",
539 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
540 }
541 #endif
542
543
544 #ifdef DEBUG
545 static void
546 print_temp(const struct tgsi_exec_machine *mach, uint index)
547 {
548 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
549 int i;
550 debug_printf("Temp[%u] =\n", index);
551 for (i = 0; i < 4; i++) {
552 debug_printf(" %c: { %f, %f, %f, %f }\n",
553 "XYZW"[i],
554 tmp->xyzw[i].f[0],
555 tmp->xyzw[i].f[1],
556 tmp->xyzw[i].f[2],
557 tmp->xyzw[i].f[3]);
558 }
559 }
560 #endif
561
562
563 void
564 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
565 unsigned num_bufs,
566 const void **bufs,
567 const unsigned *buf_sizes)
568 {
569 unsigned i;
570
571 for (i = 0; i < num_bufs; i++) {
572 mach->Consts[i] = bufs[i];
573 mach->ConstsSize[i] = buf_sizes[i];
574 }
575 }
576
577
578 /**
579 * Check if there's a potential src/dst register data dependency when
580 * using SOA execution.
581 * Example:
582 * MOV T, T.yxwz;
583 * This would expand into:
584 * MOV t0, t1;
585 * MOV t1, t0;
586 * MOV t2, t3;
587 * MOV t3, t2;
588 * The second instruction will have the wrong value for t0 if executed as-is.
589 */
590 boolean
591 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
592 {
593 uint i, chan;
594
595 uint writemask = inst->Dst[0].Register.WriteMask;
596 if (writemask == TGSI_WRITEMASK_X ||
597 writemask == TGSI_WRITEMASK_Y ||
598 writemask == TGSI_WRITEMASK_Z ||
599 writemask == TGSI_WRITEMASK_W ||
600 writemask == TGSI_WRITEMASK_NONE) {
601 /* no chance of data dependency */
602 return FALSE;
603 }
604
605 /* loop over src regs */
606 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
607 if ((inst->Src[i].Register.File ==
608 inst->Dst[0].Register.File) &&
609 ((inst->Src[i].Register.Index ==
610 inst->Dst[0].Register.Index) ||
611 inst->Src[i].Register.Indirect ||
612 inst->Dst[0].Register.Indirect)) {
613 /* loop over dest channels */
614 uint channelsWritten = 0x0;
615 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
616 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
617 /* check if we're reading a channel that's been written */
618 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
619 if (channelsWritten & (1 << swizzle)) {
620 return TRUE;
621 }
622
623 channelsWritten |= (1 << chan);
624 }
625 }
626 }
627 }
628 return FALSE;
629 }
630
631
632 /**
633 * Initialize machine state by expanding tokens to full instructions,
634 * allocating temporary storage, setting up constants, etc.
635 * After this, we can call tgsi_exec_machine_run() many times.
636 */
637 void
638 tgsi_exec_machine_bind_shader(
639 struct tgsi_exec_machine *mach,
640 const struct tgsi_token *tokens,
641 uint numSamplers,
642 struct tgsi_sampler **samplers)
643 {
644 uint k;
645 struct tgsi_parse_context parse;
646 struct tgsi_full_instruction *instructions;
647 struct tgsi_full_declaration *declarations;
648 uint maxInstructions = 10, numInstructions = 0;
649 uint maxDeclarations = 10, numDeclarations = 0;
650
651 #if 0
652 tgsi_dump(tokens, 0);
653 #endif
654
655 util_init_math();
656
657 if (numSamplers) {
658 assert(samplers);
659 }
660
661 mach->Tokens = tokens;
662 mach->Samplers = samplers;
663
664 if (!tokens) {
665 /* unbind and free all */
666 FREE(mach->Declarations);
667 mach->Declarations = NULL;
668 mach->NumDeclarations = 0;
669
670 FREE(mach->Instructions);
671 mach->Instructions = NULL;
672 mach->NumInstructions = 0;
673
674 return;
675 }
676
677 k = tgsi_parse_init (&parse, mach->Tokens);
678 if (k != TGSI_PARSE_OK) {
679 debug_printf( "Problem parsing!\n" );
680 return;
681 }
682
683 mach->Processor = parse.FullHeader.Processor.Processor;
684 mach->ImmLimit = 0;
685
686 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
687 !mach->UsedGeometryShader) {
688 struct tgsi_exec_vector *inputs;
689 struct tgsi_exec_vector *outputs;
690
691 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
692 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS,
693 16);
694
695 if (!inputs)
696 return;
697
698 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
699 TGSI_MAX_TOTAL_VERTICES, 16);
700
701 if (!outputs) {
702 align_free(inputs);
703 return;
704 }
705
706 align_free(mach->Inputs);
707 align_free(mach->Outputs);
708
709 mach->Inputs = inputs;
710 mach->Outputs = outputs;
711 mach->UsedGeometryShader = TRUE;
712 }
713
714 declarations = (struct tgsi_full_declaration *)
715 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
716
717 if (!declarations) {
718 return;
719 }
720
721 instructions = (struct tgsi_full_instruction *)
722 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
723
724 if (!instructions) {
725 FREE( declarations );
726 return;
727 }
728
729 while( !tgsi_parse_end_of_tokens( &parse ) ) {
730 uint i;
731
732 tgsi_parse_token( &parse );
733 switch( parse.FullToken.Token.Type ) {
734 case TGSI_TOKEN_TYPE_DECLARATION:
735 /* save expanded declaration */
736 if (numDeclarations == maxDeclarations) {
737 declarations = REALLOC(declarations,
738 maxDeclarations
739 * sizeof(struct tgsi_full_declaration),
740 (maxDeclarations + 10)
741 * sizeof(struct tgsi_full_declaration));
742 maxDeclarations += 10;
743 }
744 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
745 unsigned reg;
746 for (reg = parse.FullToken.FullDeclaration.Range.First;
747 reg <= parse.FullToken.FullDeclaration.Range.Last;
748 ++reg) {
749 ++mach->NumOutputs;
750 }
751 }
752 if (parse.FullToken.FullDeclaration.Declaration.File ==
753 TGSI_FILE_IMMEDIATE_ARRAY) {
754 unsigned reg;
755 struct tgsi_full_declaration *decl =
756 &parse.FullToken.FullDeclaration;
757 debug_assert(decl->Range.Last < TGSI_EXEC_NUM_IMMEDIATES);
758 for (reg = decl->Range.First; reg <= decl->Range.Last; ++reg) {
759 for( i = 0; i < 4; i++ ) {
760 int idx = reg * 4 + i;
761 mach->ImmArray[reg][i] = decl->ImmediateData.u[idx].Float;
762 }
763 }
764 }
765 memcpy(declarations + numDeclarations,
766 &parse.FullToken.FullDeclaration,
767 sizeof(declarations[0]));
768 numDeclarations++;
769 break;
770
771 case TGSI_TOKEN_TYPE_IMMEDIATE:
772 {
773 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
774 assert( size <= 4 );
775 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
776
777 for( i = 0; i < size; i++ ) {
778 mach->Imms[mach->ImmLimit][i] =
779 parse.FullToken.FullImmediate.u[i].Float;
780 }
781 mach->ImmLimit += 1;
782 }
783 break;
784
785 case TGSI_TOKEN_TYPE_INSTRUCTION:
786
787 /* save expanded instruction */
788 if (numInstructions == maxInstructions) {
789 instructions = REALLOC(instructions,
790 maxInstructions
791 * sizeof(struct tgsi_full_instruction),
792 (maxInstructions + 10)
793 * sizeof(struct tgsi_full_instruction));
794 maxInstructions += 10;
795 }
796
797 memcpy(instructions + numInstructions,
798 &parse.FullToken.FullInstruction,
799 sizeof(instructions[0]));
800
801 numInstructions++;
802 break;
803
804 case TGSI_TOKEN_TYPE_PROPERTY:
805 break;
806
807 default:
808 assert( 0 );
809 }
810 }
811 tgsi_parse_free (&parse);
812
813 FREE(mach->Declarations);
814 mach->Declarations = declarations;
815 mach->NumDeclarations = numDeclarations;
816
817 FREE(mach->Instructions);
818 mach->Instructions = instructions;
819 mach->NumInstructions = numInstructions;
820 }
821
822
823 struct tgsi_exec_machine *
824 tgsi_exec_machine_create( void )
825 {
826 struct tgsi_exec_machine *mach;
827 uint i;
828
829 mach = align_malloc( sizeof *mach, 16 );
830 if (!mach)
831 goto fail;
832
833 memset(mach, 0, sizeof(*mach));
834
835 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
836 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
837 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
838
839 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
840 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
841 if (!mach->Inputs || !mach->Outputs)
842 goto fail;
843
844 /* Setup constants needed by the SSE2 executor. */
845 for( i = 0; i < 4; i++ ) {
846 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
847 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
848 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
849 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
850 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
851 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
852 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
853 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
854 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
855 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
856 }
857
858 #ifdef DEBUG
859 /* silence warnings */
860 (void) print_chan;
861 (void) print_temp;
862 #endif
863
864 return mach;
865
866 fail:
867 if (mach) {
868 align_free(mach->Inputs);
869 align_free(mach->Outputs);
870 align_free(mach);
871 }
872 return NULL;
873 }
874
875
876 void
877 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
878 {
879 if (mach) {
880 FREE(mach->Instructions);
881 FREE(mach->Declarations);
882
883 align_free(mach->Inputs);
884 align_free(mach->Outputs);
885
886 align_free(mach);
887 }
888 }
889
890 static void
891 micro_add(union tgsi_exec_channel *dst,
892 const union tgsi_exec_channel *src0,
893 const union tgsi_exec_channel *src1)
894 {
895 dst->f[0] = src0->f[0] + src1->f[0];
896 dst->f[1] = src0->f[1] + src1->f[1];
897 dst->f[2] = src0->f[2] + src1->f[2];
898 dst->f[3] = src0->f[3] + src1->f[3];
899 }
900
901 static void
902 micro_div(
903 union tgsi_exec_channel *dst,
904 const union tgsi_exec_channel *src0,
905 const union tgsi_exec_channel *src1 )
906 {
907 if (src1->f[0] != 0) {
908 dst->f[0] = src0->f[0] / src1->f[0];
909 }
910 if (src1->f[1] != 0) {
911 dst->f[1] = src0->f[1] / src1->f[1];
912 }
913 if (src1->f[2] != 0) {
914 dst->f[2] = src0->f[2] / src1->f[2];
915 }
916 if (src1->f[3] != 0) {
917 dst->f[3] = src0->f[3] / src1->f[3];
918 }
919 }
920
921 static void
922 micro_rcc(union tgsi_exec_channel *dst,
923 const union tgsi_exec_channel *src)
924 {
925 uint i;
926
927 for (i = 0; i < 4; i++) {
928 float recip = 1.0f / src->f[i];
929
930 if (recip > 0.0f) {
931 if (recip > 1.884467e+019f) {
932 dst->f[i] = 1.884467e+019f;
933 }
934 else if (recip < 5.42101e-020f) {
935 dst->f[i] = 5.42101e-020f;
936 }
937 else {
938 dst->f[i] = recip;
939 }
940 }
941 else {
942 if (recip < -1.884467e+019f) {
943 dst->f[i] = -1.884467e+019f;
944 }
945 else if (recip > -5.42101e-020f) {
946 dst->f[i] = -5.42101e-020f;
947 }
948 else {
949 dst->f[i] = recip;
950 }
951 }
952 }
953 }
954
955 static void
956 micro_lt(
957 union tgsi_exec_channel *dst,
958 const union tgsi_exec_channel *src0,
959 const union tgsi_exec_channel *src1,
960 const union tgsi_exec_channel *src2,
961 const union tgsi_exec_channel *src3 )
962 {
963 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
964 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
965 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
966 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
967 }
968
969 static void
970 micro_max(union tgsi_exec_channel *dst,
971 const union tgsi_exec_channel *src0,
972 const union tgsi_exec_channel *src1)
973 {
974 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
975 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
976 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
977 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
978 }
979
980 static void
981 micro_min(union tgsi_exec_channel *dst,
982 const union tgsi_exec_channel *src0,
983 const union tgsi_exec_channel *src1)
984 {
985 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
986 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
987 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
988 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
989 }
990
991 static void
992 micro_mul(union tgsi_exec_channel *dst,
993 const union tgsi_exec_channel *src0,
994 const union tgsi_exec_channel *src1)
995 {
996 dst->f[0] = src0->f[0] * src1->f[0];
997 dst->f[1] = src0->f[1] * src1->f[1];
998 dst->f[2] = src0->f[2] * src1->f[2];
999 dst->f[3] = src0->f[3] * src1->f[3];
1000 }
1001
1002 static void
1003 micro_neg(
1004 union tgsi_exec_channel *dst,
1005 const union tgsi_exec_channel *src )
1006 {
1007 dst->f[0] = -src->f[0];
1008 dst->f[1] = -src->f[1];
1009 dst->f[2] = -src->f[2];
1010 dst->f[3] = -src->f[3];
1011 }
1012
1013 static void
1014 micro_pow(
1015 union tgsi_exec_channel *dst,
1016 const union tgsi_exec_channel *src0,
1017 const union tgsi_exec_channel *src1 )
1018 {
1019 #if FAST_MATH
1020 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1021 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1022 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1023 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1024 #else
1025 dst->f[0] = powf( src0->f[0], src1->f[0] );
1026 dst->f[1] = powf( src0->f[1], src1->f[1] );
1027 dst->f[2] = powf( src0->f[2], src1->f[2] );
1028 dst->f[3] = powf( src0->f[3], src1->f[3] );
1029 #endif
1030 }
1031
1032 static void
1033 micro_sub(union tgsi_exec_channel *dst,
1034 const union tgsi_exec_channel *src0,
1035 const union tgsi_exec_channel *src1)
1036 {
1037 dst->f[0] = src0->f[0] - src1->f[0];
1038 dst->f[1] = src0->f[1] - src1->f[1];
1039 dst->f[2] = src0->f[2] - src1->f[2];
1040 dst->f[3] = src0->f[3] - src1->f[3];
1041 }
1042
1043 static void
1044 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1045 const uint chan_index,
1046 const uint file,
1047 const uint swizzle,
1048 const union tgsi_exec_channel *index,
1049 const union tgsi_exec_channel *index2D,
1050 union tgsi_exec_channel *chan)
1051 {
1052 uint i;
1053
1054 assert(swizzle < 4);
1055
1056 switch (file) {
1057 case TGSI_FILE_CONSTANT:
1058 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1059 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1060 assert(mach->Consts[index2D->i[i]]);
1061
1062 if (index->i[i] < 0) {
1063 chan->u[i] = 0;
1064 } else {
1065 /* NOTE: copying the const value as a uint instead of float */
1066 const uint constbuf = index2D->i[i];
1067 const uint *buf = (const uint *)mach->Consts[constbuf];
1068 const int pos = index->i[i] * 4 + swizzle;
1069 /* const buffer bounds check */
1070 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1071 if (0) {
1072 /* Debug: print warning */
1073 static int count = 0;
1074 if (count++ < 100)
1075 debug_printf("TGSI Exec: const buffer index %d"
1076 " out of bounds\n", pos);
1077 }
1078 chan->u[i] = 0;
1079 }
1080 else
1081 chan->u[i] = buf[pos];
1082 }
1083 }
1084 break;
1085
1086 case TGSI_FILE_INPUT:
1087 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1088 /*
1089 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1090 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1091 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1092 index2D->i[i], index->i[i]);
1093 }*/
1094 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1095 assert(pos >= 0);
1096 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1097 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1098 }
1099 break;
1100
1101 case TGSI_FILE_SYSTEM_VALUE:
1102 /* XXX no swizzling at this point. Will be needed if we put
1103 * gl_FragCoord, for example, in a sys value register.
1104 */
1105 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1106 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1107 }
1108 break;
1109
1110 case TGSI_FILE_TEMPORARY:
1111 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1112 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1113 assert(index2D->i[i] == 0);
1114
1115 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1116 }
1117 break;
1118
1119 case TGSI_FILE_TEMPORARY_ARRAY:
1120 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1121 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1122 assert(index2D->i[i] < TGSI_EXEC_NUM_TEMP_ARRAYS);
1123
1124 chan->u[i] =
1125 mach->TempArray[index2D->i[i]][index->i[i]].xyzw[swizzle].u[i];
1126 }
1127 break;
1128
1129 case TGSI_FILE_IMMEDIATE:
1130 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1131 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1132 assert(index2D->i[i] == 0);
1133
1134 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1135 }
1136 break;
1137
1138 case TGSI_FILE_IMMEDIATE_ARRAY:
1139 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1140 assert(index2D->i[i] == 0);
1141
1142 chan->f[i] = mach->ImmArray[index->i[i]][swizzle];
1143 }
1144 break;
1145
1146 case TGSI_FILE_ADDRESS:
1147 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1148 assert(index->i[i] >= 0);
1149 assert(index2D->i[i] == 0);
1150
1151 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1152 }
1153 break;
1154
1155 case TGSI_FILE_PREDICATE:
1156 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1157 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1158 assert(index2D->i[i] == 0);
1159
1160 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1161 }
1162 break;
1163
1164 case TGSI_FILE_OUTPUT:
1165 /* vertex/fragment output vars can be read too */
1166 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1167 assert(index->i[i] >= 0);
1168 assert(index2D->i[i] == 0);
1169
1170 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1171 }
1172 break;
1173
1174 default:
1175 assert(0);
1176 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1177 chan->u[i] = 0;
1178 }
1179 }
1180 }
1181
1182 static void
1183 fetch_source(const struct tgsi_exec_machine *mach,
1184 union tgsi_exec_channel *chan,
1185 const struct tgsi_full_src_register *reg,
1186 const uint chan_index,
1187 enum tgsi_exec_datatype src_datatype)
1188 {
1189 union tgsi_exec_channel index;
1190 union tgsi_exec_channel index2D;
1191 uint swizzle;
1192
1193 /* We start with a direct index into a register file.
1194 *
1195 * file[1],
1196 * where:
1197 * file = Register.File
1198 * [1] = Register.Index
1199 */
1200 index.i[0] =
1201 index.i[1] =
1202 index.i[2] =
1203 index.i[3] = reg->Register.Index;
1204
1205 /* There is an extra source register that indirectly subscripts
1206 * a register file. The direct index now becomes an offset
1207 * that is being added to the indirect register.
1208 *
1209 * file[ind[2].x+1],
1210 * where:
1211 * ind = Indirect.File
1212 * [2] = Indirect.Index
1213 * .x = Indirect.SwizzleX
1214 */
1215 if (reg->Register.Indirect) {
1216 union tgsi_exec_channel index2;
1217 union tgsi_exec_channel indir_index;
1218 const uint execmask = mach->ExecMask;
1219 uint i;
1220
1221 /* which address register (always zero now) */
1222 index2.i[0] =
1223 index2.i[1] =
1224 index2.i[2] =
1225 index2.i[3] = reg->Indirect.Index;
1226 /* get current value of address register[swizzle] */
1227 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, TGSI_CHAN_X );
1228 fetch_src_file_channel(mach,
1229 chan_index,
1230 reg->Indirect.File,
1231 swizzle,
1232 &index2,
1233 &ZeroVec,
1234 &indir_index);
1235
1236 /* add value of address register to the offset */
1237 index.i[0] += indir_index.i[0];
1238 index.i[1] += indir_index.i[1];
1239 index.i[2] += indir_index.i[2];
1240 index.i[3] += indir_index.i[3];
1241
1242 /* for disabled execution channels, zero-out the index to
1243 * avoid using a potential garbage value.
1244 */
1245 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1246 if ((execmask & (1 << i)) == 0)
1247 index.i[i] = 0;
1248 }
1249 }
1250
1251 /* There is an extra source register that is a second
1252 * subscript to a register file. Effectively it means that
1253 * the register file is actually a 2D array of registers.
1254 *
1255 * file[3][1],
1256 * where:
1257 * [3] = Dimension.Index
1258 */
1259 if (reg->Register.Dimension) {
1260 index2D.i[0] =
1261 index2D.i[1] =
1262 index2D.i[2] =
1263 index2D.i[3] = reg->Dimension.Index;
1264
1265 /* Again, the second subscript index can be addressed indirectly
1266 * identically to the first one.
1267 * Nothing stops us from indirectly addressing the indirect register,
1268 * but there is no need for that, so we won't exercise it.
1269 *
1270 * file[ind[4].y+3][1],
1271 * where:
1272 * ind = DimIndirect.File
1273 * [4] = DimIndirect.Index
1274 * .y = DimIndirect.SwizzleX
1275 */
1276 if (reg->Dimension.Indirect) {
1277 union tgsi_exec_channel index2;
1278 union tgsi_exec_channel indir_index;
1279 const uint execmask = mach->ExecMask;
1280 uint i;
1281
1282 index2.i[0] =
1283 index2.i[1] =
1284 index2.i[2] =
1285 index2.i[3] = reg->DimIndirect.Index;
1286
1287 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, TGSI_CHAN_X );
1288 fetch_src_file_channel(mach,
1289 chan_index,
1290 reg->DimIndirect.File,
1291 swizzle,
1292 &index2,
1293 &ZeroVec,
1294 &indir_index);
1295
1296 index2D.i[0] += indir_index.i[0];
1297 index2D.i[1] += indir_index.i[1];
1298 index2D.i[2] += indir_index.i[2];
1299 index2D.i[3] += indir_index.i[3];
1300
1301 /* for disabled execution channels, zero-out the index to
1302 * avoid using a potential garbage value.
1303 */
1304 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1305 if ((execmask & (1 << i)) == 0) {
1306 index2D.i[i] = 0;
1307 }
1308 }
1309 }
1310
1311 /* If by any chance there was a need for a 3D array of register
1312 * files, we would have to check whether Dimension is followed
1313 * by a dimension register and continue the saga.
1314 */
1315 } else {
1316 index2D.i[0] =
1317 index2D.i[1] =
1318 index2D.i[2] =
1319 index2D.i[3] = 0;
1320 }
1321
1322 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1323 fetch_src_file_channel(mach,
1324 chan_index,
1325 reg->Register.File,
1326 swizzle,
1327 &index,
1328 &index2D,
1329 chan);
1330
1331 if (reg->Register.Absolute) {
1332 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1333 micro_abs(chan, chan);
1334 } else {
1335 micro_iabs(chan, chan);
1336 }
1337 }
1338
1339 if (reg->Register.Negate) {
1340 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1341 micro_neg(chan, chan);
1342 } else {
1343 micro_ineg(chan, chan);
1344 }
1345 }
1346 }
1347
1348 static void
1349 store_dest(struct tgsi_exec_machine *mach,
1350 const union tgsi_exec_channel *chan,
1351 const struct tgsi_full_dst_register *reg,
1352 const struct tgsi_full_instruction *inst,
1353 uint chan_index,
1354 enum tgsi_exec_datatype dst_datatype)
1355 {
1356 uint i;
1357 union tgsi_exec_channel null;
1358 union tgsi_exec_channel *dst;
1359 union tgsi_exec_channel index2D;
1360 uint execmask = mach->ExecMask;
1361 int offset = 0; /* indirection offset */
1362 int index;
1363
1364 /* for debugging */
1365 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1366 check_inf_or_nan(chan);
1367 }
1368
1369 /* There is an extra source register that indirectly subscripts
1370 * a register file. The direct index now becomes an offset
1371 * that is being added to the indirect register.
1372 *
1373 * file[ind[2].x+1],
1374 * where:
1375 * ind = Indirect.File
1376 * [2] = Indirect.Index
1377 * .x = Indirect.SwizzleX
1378 */
1379 if (reg->Register.Indirect) {
1380 union tgsi_exec_channel index;
1381 union tgsi_exec_channel indir_index;
1382 uint swizzle;
1383
1384 /* which address register (always zero for now) */
1385 index.i[0] =
1386 index.i[1] =
1387 index.i[2] =
1388 index.i[3] = reg->Indirect.Index;
1389
1390 /* get current value of address register[swizzle] */
1391 swizzle = tgsi_util_get_src_register_swizzle( &reg->Indirect, TGSI_CHAN_X );
1392
1393 /* fetch values from the address/indirection register */
1394 fetch_src_file_channel(mach,
1395 chan_index,
1396 reg->Indirect.File,
1397 swizzle,
1398 &index,
1399 &ZeroVec,
1400 &indir_index);
1401
1402 /* save indirection offset */
1403 offset = indir_index.i[0];
1404 }
1405
1406 /* There is an extra source register that is a second
1407 * subscript to a register file. Effectively it means that
1408 * the register file is actually a 2D array of registers.
1409 *
1410 * file[3][1],
1411 * where:
1412 * [3] = Dimension.Index
1413 */
1414 if (reg->Register.Dimension) {
1415 index2D.i[0] =
1416 index2D.i[1] =
1417 index2D.i[2] =
1418 index2D.i[3] = reg->Dimension.Index;
1419
1420 /* Again, the second subscript index can be addressed indirectly
1421 * identically to the first one.
1422 * Nothing stops us from indirectly addressing the indirect register,
1423 * but there is no need for that, so we won't exercise it.
1424 *
1425 * file[ind[4].y+3][1],
1426 * where:
1427 * ind = DimIndirect.File
1428 * [4] = DimIndirect.Index
1429 * .y = DimIndirect.SwizzleX
1430 */
1431 if (reg->Dimension.Indirect) {
1432 union tgsi_exec_channel index2;
1433 union tgsi_exec_channel indir_index;
1434 const uint execmask = mach->ExecMask;
1435 unsigned swizzle;
1436 uint i;
1437
1438 index2.i[0] =
1439 index2.i[1] =
1440 index2.i[2] =
1441 index2.i[3] = reg->DimIndirect.Index;
1442
1443 swizzle = tgsi_util_get_src_register_swizzle( &reg->DimIndirect, TGSI_CHAN_X );
1444 fetch_src_file_channel(mach,
1445 chan_index,
1446 reg->DimIndirect.File,
1447 swizzle,
1448 &index2,
1449 &ZeroVec,
1450 &indir_index);
1451
1452 index2D.i[0] += indir_index.i[0];
1453 index2D.i[1] += indir_index.i[1];
1454 index2D.i[2] += indir_index.i[2];
1455 index2D.i[3] += indir_index.i[3];
1456
1457 /* for disabled execution channels, zero-out the index to
1458 * avoid using a potential garbage value.
1459 */
1460 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1461 if ((execmask & (1 << i)) == 0) {
1462 index2D.i[i] = 0;
1463 }
1464 }
1465 }
1466
1467 /* If by any chance there was a need for a 3D array of register
1468 * files, we would have to check whether Dimension is followed
1469 * by a dimension register and continue the saga.
1470 */
1471 } else {
1472 index2D.i[0] =
1473 index2D.i[1] =
1474 index2D.i[2] =
1475 index2D.i[3] = 0;
1476 }
1477
1478 switch (reg->Register.File) {
1479 case TGSI_FILE_NULL:
1480 dst = &null;
1481 break;
1482
1483 case TGSI_FILE_OUTPUT:
1484 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1485 + reg->Register.Index;
1486 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1487 #if 0
1488 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1489 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1490 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1491 if (execmask & (1 << i))
1492 fprintf(stderr, "%f, ", chan->f[i]);
1493 fprintf(stderr, ")\n");
1494 }
1495 #endif
1496 break;
1497
1498 case TGSI_FILE_TEMPORARY:
1499 index = reg->Register.Index;
1500 assert( index < TGSI_EXEC_NUM_TEMPS );
1501 dst = &mach->Temps[offset + index].xyzw[chan_index];
1502 break;
1503
1504 case TGSI_FILE_TEMPORARY_ARRAY:
1505 index = reg->Register.Index;
1506 assert( index < TGSI_EXEC_NUM_TEMPS );
1507 assert( index2D.i[0] < TGSI_EXEC_NUM_TEMP_ARRAYS );
1508 /* XXX we use index2D.i[0] here but somehow we might
1509 * end up with someone trying to store indirectly in
1510 * different buffers */
1511 dst = &mach->TempArray[index2D.i[0]][offset + index].xyzw[chan_index];
1512 break;
1513
1514 case TGSI_FILE_ADDRESS:
1515 index = reg->Register.Index;
1516 dst = &mach->Addrs[index].xyzw[chan_index];
1517 break;
1518
1519 case TGSI_FILE_PREDICATE:
1520 index = reg->Register.Index;
1521 assert(index < TGSI_EXEC_NUM_PREDS);
1522 dst = &mach->Predicates[index].xyzw[chan_index];
1523 break;
1524
1525 default:
1526 assert( 0 );
1527 return;
1528 }
1529
1530 if (inst->Instruction.Predicate) {
1531 uint swizzle;
1532 union tgsi_exec_channel *pred;
1533
1534 switch (chan_index) {
1535 case TGSI_CHAN_X:
1536 swizzle = inst->Predicate.SwizzleX;
1537 break;
1538 case TGSI_CHAN_Y:
1539 swizzle = inst->Predicate.SwizzleY;
1540 break;
1541 case TGSI_CHAN_Z:
1542 swizzle = inst->Predicate.SwizzleZ;
1543 break;
1544 case TGSI_CHAN_W:
1545 swizzle = inst->Predicate.SwizzleW;
1546 break;
1547 default:
1548 assert(0);
1549 return;
1550 }
1551
1552 assert(inst->Predicate.Index == 0);
1553
1554 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1555
1556 if (inst->Predicate.Negate) {
1557 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1558 if (pred->u[i]) {
1559 execmask &= ~(1 << i);
1560 }
1561 }
1562 } else {
1563 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1564 if (!pred->u[i]) {
1565 execmask &= ~(1 << i);
1566 }
1567 }
1568 }
1569 }
1570
1571 switch (inst->Instruction.Saturate) {
1572 case TGSI_SAT_NONE:
1573 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1574 if (execmask & (1 << i))
1575 dst->i[i] = chan->i[i];
1576 break;
1577
1578 case TGSI_SAT_ZERO_ONE:
1579 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1580 if (execmask & (1 << i)) {
1581 if (chan->f[i] < 0.0f)
1582 dst->f[i] = 0.0f;
1583 else if (chan->f[i] > 1.0f)
1584 dst->f[i] = 1.0f;
1585 else
1586 dst->i[i] = chan->i[i];
1587 }
1588 break;
1589
1590 case TGSI_SAT_MINUS_PLUS_ONE:
1591 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1592 if (execmask & (1 << i)) {
1593 if (chan->f[i] < -1.0f)
1594 dst->f[i] = -1.0f;
1595 else if (chan->f[i] > 1.0f)
1596 dst->f[i] = 1.0f;
1597 else
1598 dst->i[i] = chan->i[i];
1599 }
1600 break;
1601
1602 default:
1603 assert( 0 );
1604 }
1605 }
1606
1607 #define FETCH(VAL,INDEX,CHAN)\
1608 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1609
1610 #define IFETCH(VAL,INDEX,CHAN)\
1611 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1612
1613
1614 /**
1615 * Execute ARB-style KIL which is predicated by a src register.
1616 * Kill fragment if any of the four values is less than zero.
1617 */
1618 static void
1619 exec_kil(struct tgsi_exec_machine *mach,
1620 const struct tgsi_full_instruction *inst)
1621 {
1622 uint uniquemask;
1623 uint chan_index;
1624 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1625 union tgsi_exec_channel r[1];
1626
1627 /* This mask stores component bits that were already tested. */
1628 uniquemask = 0;
1629
1630 for (chan_index = 0; chan_index < 4; chan_index++)
1631 {
1632 uint swizzle;
1633 uint i;
1634
1635 /* unswizzle channel */
1636 swizzle = tgsi_util_get_full_src_register_swizzle (
1637 &inst->Src[0],
1638 chan_index);
1639
1640 /* check if the component has not been already tested */
1641 if (uniquemask & (1 << swizzle))
1642 continue;
1643 uniquemask |= 1 << swizzle;
1644
1645 FETCH(&r[0], 0, chan_index);
1646 for (i = 0; i < 4; i++)
1647 if (r[0].f[i] < 0.0f)
1648 kilmask |= 1 << i;
1649 }
1650
1651 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1652 }
1653
1654 /**
1655 * Execute NVIDIA-style KIL which is predicated by a condition code.
1656 * Kill fragment if the condition code is TRUE.
1657 */
1658 static void
1659 exec_kilp(struct tgsi_exec_machine *mach,
1660 const struct tgsi_full_instruction *inst)
1661 {
1662 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1663
1664 /* "unconditional" kil */
1665 kilmask = mach->ExecMask;
1666 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1667 }
1668
1669 static void
1670 emit_vertex(struct tgsi_exec_machine *mach)
1671 {
1672 /* FIXME: check for exec mask correctly
1673 unsigned i;
1674 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1675 if ((mach->ExecMask & (1 << i)))
1676 */
1677 if (mach->ExecMask) {
1678 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1679 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1680 }
1681 }
1682
1683 static void
1684 emit_primitive(struct tgsi_exec_machine *mach)
1685 {
1686 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1687 /* FIXME: check for exec mask correctly
1688 unsigned i;
1689 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1690 if ((mach->ExecMask & (1 << i)))
1691 */
1692 if (mach->ExecMask) {
1693 ++(*prim_count);
1694 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1695 mach->Primitives[*prim_count] = 0;
1696 }
1697 }
1698
1699 static void
1700 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1701 {
1702 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1703 int emitted_verts =
1704 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1705 if (emitted_verts) {
1706 emit_primitive(mach);
1707 }
1708 }
1709 }
1710
1711
1712 /*
1713 * Fetch four texture samples using STR texture coordinates.
1714 */
1715 static void
1716 fetch_texel( struct tgsi_sampler *sampler,
1717 const union tgsi_exec_channel *s,
1718 const union tgsi_exec_channel *t,
1719 const union tgsi_exec_channel *p,
1720 const union tgsi_exec_channel *c0,
1721 const union tgsi_exec_channel *c1,
1722 enum tgsi_sampler_control control,
1723 union tgsi_exec_channel *r,
1724 union tgsi_exec_channel *g,
1725 union tgsi_exec_channel *b,
1726 union tgsi_exec_channel *a )
1727 {
1728 uint j;
1729 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1730
1731 sampler->get_samples(sampler, s->f, t->f, p->f, c0->f, c1->f, control, rgba);
1732
1733 for (j = 0; j < 4; j++) {
1734 r->f[j] = rgba[0][j];
1735 g->f[j] = rgba[1][j];
1736 b->f[j] = rgba[2][j];
1737 a->f[j] = rgba[3][j];
1738 }
1739 }
1740
1741
1742 #define TEX_MODIFIER_NONE 0
1743 #define TEX_MODIFIER_PROJECTED 1
1744 #define TEX_MODIFIER_LOD_BIAS 2
1745 #define TEX_MODIFIER_EXPLICIT_LOD 3
1746 #define TEX_MODIFIER_LEVEL_ZERO 4
1747
1748 /*
1749 * execute a texture instruction.
1750 *
1751 * modifier is used to control the channel routing for the\
1752 * instruction variants like proj, lod, and texture with lod bias.
1753 * sampler indicates which src register the sampler is contained in.
1754 */
1755 static void
1756 exec_tex(struct tgsi_exec_machine *mach,
1757 const struct tgsi_full_instruction *inst,
1758 uint modifier, uint sampler)
1759 {
1760 const uint unit = inst->Src[sampler].Register.Index;
1761 union tgsi_exec_channel r[4], cubearraycomp, cubelod;
1762 const union tgsi_exec_channel *lod = &ZeroVec;
1763 enum tgsi_sampler_control control;
1764 uint chan;
1765
1766 if (modifier != TEX_MODIFIER_NONE && (sampler == 1)) {
1767 FETCH(&r[3], 0, TGSI_CHAN_W);
1768 if (modifier != TEX_MODIFIER_PROJECTED) {
1769 lod = &r[3];
1770 }
1771 }
1772
1773 if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
1774 control = tgsi_sampler_lod_explicit;
1775 } else {
1776 control = tgsi_sampler_lod_bias;
1777 }
1778
1779 switch (inst->Texture.Texture) {
1780 case TGSI_TEXTURE_1D:
1781 FETCH(&r[0], 0, TGSI_CHAN_X);
1782
1783 if (modifier == TEX_MODIFIER_PROJECTED) {
1784 micro_div(&r[0], &r[0], &r[3]);
1785 }
1786
1787 fetch_texel(mach->Samplers[unit],
1788 &r[0], &ZeroVec, &ZeroVec, lod, &ZeroVec, /* S, T, P, LOD */
1789 control,
1790 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1791 break;
1792 case TGSI_TEXTURE_SHADOW1D:
1793 FETCH(&r[0], 0, TGSI_CHAN_X);
1794 FETCH(&r[2], 0, TGSI_CHAN_Z);
1795
1796 if (modifier == TEX_MODIFIER_PROJECTED) {
1797 micro_div(&r[0], &r[0], &r[3]);
1798 }
1799
1800 fetch_texel(mach->Samplers[unit],
1801 &r[0], &ZeroVec, &r[2], lod, &ZeroVec, /* S, T, P, LOD */
1802 control,
1803 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1804 break;
1805
1806 case TGSI_TEXTURE_2D:
1807 case TGSI_TEXTURE_RECT:
1808 case TGSI_TEXTURE_SHADOW2D:
1809 case TGSI_TEXTURE_SHADOWRECT:
1810 FETCH(&r[0], 0, TGSI_CHAN_X);
1811 FETCH(&r[1], 0, TGSI_CHAN_Y);
1812 FETCH(&r[2], 0, TGSI_CHAN_Z);
1813
1814 if (modifier == TEX_MODIFIER_PROJECTED) {
1815 micro_div(&r[0], &r[0], &r[3]);
1816 micro_div(&r[1], &r[1], &r[3]);
1817 micro_div(&r[2], &r[2], &r[3]);
1818 }
1819
1820 fetch_texel(mach->Samplers[unit],
1821 &r[0], &r[1], &r[2], lod, &ZeroVec, /* S, T, P, LOD */
1822 control,
1823 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1824 break;
1825
1826 case TGSI_TEXTURE_1D_ARRAY:
1827 FETCH(&r[0], 0, TGSI_CHAN_X);
1828 FETCH(&r[1], 0, TGSI_CHAN_Y);
1829
1830 if (modifier == TEX_MODIFIER_PROJECTED) {
1831 micro_div(&r[0], &r[0], &r[3]);
1832 }
1833
1834 fetch_texel(mach->Samplers[unit],
1835 &r[0], &r[1], &ZeroVec, lod, &ZeroVec, /* S, T, P, LOD */
1836 control,
1837 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1838 break;
1839 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1840 FETCH(&r[0], 0, TGSI_CHAN_X);
1841 FETCH(&r[1], 0, TGSI_CHAN_Y);
1842 FETCH(&r[2], 0, TGSI_CHAN_Z);
1843
1844 if (modifier == TEX_MODIFIER_PROJECTED) {
1845 micro_div(&r[0], &r[0], &r[3]);
1846 }
1847
1848 fetch_texel(mach->Samplers[unit],
1849 &r[0], &r[1], &r[2], lod, &ZeroVec, /* S, T, P, LOD */
1850 control,
1851 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1852 break;
1853
1854 case TGSI_TEXTURE_2D_ARRAY:
1855 FETCH(&r[0], 0, TGSI_CHAN_X);
1856 FETCH(&r[1], 0, TGSI_CHAN_Y);
1857 FETCH(&r[2], 0, TGSI_CHAN_Z);
1858
1859 if (modifier == TEX_MODIFIER_PROJECTED) {
1860 micro_div(&r[0], &r[0], &r[3]);
1861 micro_div(&r[1], &r[1], &r[3]);
1862 }
1863
1864 fetch_texel(mach->Samplers[unit],
1865 &r[0], &r[1], &r[2], lod, &ZeroVec, /* S, T, P, LOD */
1866 control,
1867 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1868 break;
1869 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1870 case TGSI_TEXTURE_SHADOWCUBE:
1871 FETCH(&r[0], 0, TGSI_CHAN_X);
1872 FETCH(&r[1], 0, TGSI_CHAN_Y);
1873 FETCH(&r[2], 0, TGSI_CHAN_Z);
1874 FETCH(&r[3], 0, TGSI_CHAN_W);
1875
1876 fetch_texel(mach->Samplers[unit],
1877 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* S, T, P, LOD */
1878 control,
1879 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1880 break;
1881 case TGSI_TEXTURE_CUBE_ARRAY:
1882 FETCH(&r[0], 0, TGSI_CHAN_X);
1883 FETCH(&r[1], 0, TGSI_CHAN_Y);
1884 FETCH(&r[2], 0, TGSI_CHAN_Z);
1885 FETCH(&r[3], 0, TGSI_CHAN_W);
1886
1887 if (modifier == TEX_MODIFIER_EXPLICIT_LOD ||
1888 modifier == TEX_MODIFIER_LOD_BIAS)
1889 FETCH(&cubelod, 1, TGSI_CHAN_X);
1890 else
1891 cubelod = ZeroVec;
1892
1893 fetch_texel(mach->Samplers[unit],
1894 &r[0], &r[1], &r[2], &r[3], &cubelod, /* S, T, P, LOD */
1895 control,
1896 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1897 break;
1898 case TGSI_TEXTURE_3D:
1899 case TGSI_TEXTURE_CUBE:
1900 FETCH(&r[0], 0, TGSI_CHAN_X);
1901 FETCH(&r[1], 0, TGSI_CHAN_Y);
1902 FETCH(&r[2], 0, TGSI_CHAN_Z);
1903
1904 if (modifier == TEX_MODIFIER_PROJECTED) {
1905 micro_div(&r[0], &r[0], &r[3]);
1906 micro_div(&r[1], &r[1], &r[3]);
1907 micro_div(&r[2], &r[2], &r[3]);
1908 }
1909
1910 fetch_texel(mach->Samplers[unit],
1911 &r[0], &r[1], &r[2], lod, &ZeroVec,
1912 control,
1913 &r[0], &r[1], &r[2], &r[3]);
1914 break;
1915
1916 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1917 FETCH(&r[0], 0, TGSI_CHAN_X);
1918 FETCH(&r[1], 0, TGSI_CHAN_Y);
1919 FETCH(&r[2], 0, TGSI_CHAN_Z);
1920 FETCH(&r[3], 0, TGSI_CHAN_W);
1921
1922 FETCH(&cubearraycomp, 1, TGSI_CHAN_X);
1923
1924 fetch_texel(mach->Samplers[unit],
1925 &r[0], &r[1], &r[2], &r[3], &cubearraycomp, /* S, T, P, LOD */
1926 control,
1927 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1928 break;
1929 default:
1930 assert(0);
1931 }
1932
1933 #if 0
1934 debug_printf("fetch r: %g %g %g %g\n",
1935 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1936 debug_printf("fetch g: %g %g %g %g\n",
1937 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1938 debug_printf("fetch b: %g %g %g %g\n",
1939 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1940 debug_printf("fetch a: %g %g %g %g\n",
1941 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1942 #endif
1943
1944 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1945 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1946 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1947 }
1948 }
1949 }
1950
1951 static void
1952 exec_txd(struct tgsi_exec_machine *mach,
1953 const struct tgsi_full_instruction *inst)
1954 {
1955 const uint unit = inst->Src[3].Register.Index;
1956 union tgsi_exec_channel r[4];
1957 uint chan;
1958
1959 /*
1960 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1961 */
1962
1963 switch (inst->Texture.Texture) {
1964 case TGSI_TEXTURE_1D:
1965 case TGSI_TEXTURE_SHADOW1D:
1966
1967 FETCH(&r[0], 0, TGSI_CHAN_X);
1968
1969 fetch_texel(mach->Samplers[unit],
1970 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
1971 tgsi_sampler_lod_bias,
1972 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1973 break;
1974
1975 case TGSI_TEXTURE_1D_ARRAY:
1976 case TGSI_TEXTURE_2D:
1977 case TGSI_TEXTURE_RECT:
1978 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1979 case TGSI_TEXTURE_SHADOW2D:
1980 case TGSI_TEXTURE_SHADOWRECT:
1981
1982 FETCH(&r[0], 0, TGSI_CHAN_X);
1983 FETCH(&r[1], 0, TGSI_CHAN_Y);
1984 FETCH(&r[2], 0, TGSI_CHAN_Z);
1985
1986 fetch_texel(mach->Samplers[unit],
1987 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
1988 tgsi_sampler_lod_bias,
1989 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1990 break;
1991
1992 case TGSI_TEXTURE_2D_ARRAY:
1993 case TGSI_TEXTURE_3D:
1994 case TGSI_TEXTURE_CUBE:
1995 case TGSI_TEXTURE_CUBE_ARRAY:
1996 FETCH(&r[0], 0, TGSI_CHAN_X);
1997 FETCH(&r[1], 0, TGSI_CHAN_Y);
1998 FETCH(&r[2], 0, TGSI_CHAN_Z);
1999
2000 fetch_texel(mach->Samplers[unit],
2001 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec,
2002 tgsi_sampler_lod_bias,
2003 &r[0], &r[1], &r[2], &r[3]);
2004 break;
2005
2006 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2007
2008 FETCH(&r[0], 0, TGSI_CHAN_X);
2009 FETCH(&r[1], 0, TGSI_CHAN_Y);
2010 FETCH(&r[2], 0, TGSI_CHAN_Z);
2011 FETCH(&r[3], 0, TGSI_CHAN_W);
2012
2013 fetch_texel(mach->Samplers[unit],
2014 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2015 tgsi_sampler_lod_bias,
2016 &r[0], &r[1], &r[2], &r[3]);
2017 break;
2018
2019 default:
2020 assert(0);
2021 }
2022
2023 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2024 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2025 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2026 }
2027 }
2028 }
2029
2030
2031 static void
2032 exec_txf(struct tgsi_exec_machine *mach,
2033 const struct tgsi_full_instruction *inst)
2034 {
2035 struct tgsi_sampler *sampler;
2036 const uint unit = inst->Src[2].Register.Index;
2037 union tgsi_exec_channel r[4];
2038 union tgsi_exec_channel offset[3];
2039 uint chan;
2040 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2041 int j;
2042 int8_t offsets[3];
2043
2044 if (inst->Texture.NumOffsets == 1) {
2045 union tgsi_exec_channel index;
2046 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
2047 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2048 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
2049 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2050 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
2051 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2052 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
2053 offsets[0] = offset[0].i[0];
2054 offsets[1] = offset[1].i[0];
2055 offsets[2] = offset[2].i[0];
2056 } else
2057 offsets[0] = offsets[1] = offsets[2] = 0;
2058
2059 IFETCH(&r[3], 0, TGSI_CHAN_W);
2060
2061 switch(inst->Texture.Texture) {
2062 case TGSI_TEXTURE_3D:
2063 case TGSI_TEXTURE_2D_ARRAY:
2064 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2065 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2066 /* fallthrough */
2067 case TGSI_TEXTURE_2D:
2068 case TGSI_TEXTURE_RECT:
2069 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2070 case TGSI_TEXTURE_SHADOW2D:
2071 case TGSI_TEXTURE_SHADOWRECT:
2072 case TGSI_TEXTURE_1D_ARRAY:
2073 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2074 /* fallthrough */
2075 case TGSI_TEXTURE_BUFFER:
2076 case TGSI_TEXTURE_1D:
2077 case TGSI_TEXTURE_SHADOW1D:
2078 IFETCH(&r[0], 0, TGSI_CHAN_X);
2079 break;
2080 default:
2081 assert(0);
2082 break;
2083 }
2084
2085 sampler = mach->Samplers[unit];
2086 sampler->get_texel(sampler, r[0].i, r[1].i, r[2].i, r[3].i,
2087 offsets, rgba);
2088
2089 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2090 r[0].f[j] = rgba[0][j];
2091 r[1].f[j] = rgba[1][j];
2092 r[2].f[j] = rgba[2][j];
2093 r[3].f[j] = rgba[3][j];
2094 }
2095
2096 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2097 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2098 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2099 }
2100 }
2101 }
2102
2103 static void
2104 exec_txq(struct tgsi_exec_machine *mach,
2105 const struct tgsi_full_instruction *inst)
2106 {
2107 struct tgsi_sampler *sampler;
2108 const uint unit = inst->Src[1].Register.Index;
2109 int result[4];
2110 union tgsi_exec_channel r[4], src;
2111 uint chan;
2112 int i,j;
2113
2114 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2115 sampler = mach->Samplers[unit];
2116
2117 sampler->get_dims(sampler, src.i[0], result);
2118
2119 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2120 for (j = 0; j < 4; j++) {
2121 r[j].i[i] = result[j];
2122 }
2123 }
2124
2125 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2126 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2127 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2128 TGSI_EXEC_DATA_INT);
2129 }
2130 }
2131 }
2132
2133 static void
2134 exec_sample(struct tgsi_exec_machine *mach,
2135 const struct tgsi_full_instruction *inst,
2136 uint modifier, boolean compare)
2137 {
2138 const uint resource_unit = inst->Src[1].Register.Index;
2139 const uint sampler_unit = inst->Src[2].Register.Index;
2140 union tgsi_exec_channel r[4];
2141 const union tgsi_exec_channel *lod = &ZeroVec;
2142 enum tgsi_sampler_control control;
2143 uint chan;
2144
2145 assert(modifier != TEX_MODIFIER_PROJECTED);
2146
2147 if (modifier != TEX_MODIFIER_NONE) {
2148 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2149 FETCH(&r[3], 3, TGSI_CHAN_X);
2150 lod = &r[3];
2151 }
2152 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2153 FETCH(&r[3], 0, TGSI_CHAN_W);
2154 lod = &r[3];
2155 }
2156 else
2157 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2158 }
2159
2160 if (modifier == TEX_MODIFIER_EXPLICIT_LOD ||
2161 modifier == TEX_MODIFIER_LEVEL_ZERO) {
2162 control = tgsi_sampler_lod_explicit;
2163 } else {
2164 control = tgsi_sampler_lod_bias;
2165 }
2166
2167 FETCH(&r[0], 0, TGSI_CHAN_X);
2168
2169 switch (mach->SamplerViews[resource_unit].Resource) {
2170 case TGSI_TEXTURE_1D:
2171 if (compare) {
2172 FETCH(&r[2], 3, TGSI_CHAN_X);
2173 fetch_texel(mach->Samplers[sampler_unit],
2174 &r[0], &ZeroVec, &r[2], lod, &ZeroVec, /* S, T, P, LOD */
2175 control,
2176 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2177 }
2178 else {
2179 fetch_texel(mach->Samplers[sampler_unit],
2180 &r[0], &ZeroVec, &ZeroVec, lod, &ZeroVec, /* S, T, P, LOD */
2181 control,
2182 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2183 }
2184 break;
2185
2186 case TGSI_TEXTURE_1D_ARRAY:
2187 case TGSI_TEXTURE_2D:
2188 case TGSI_TEXTURE_RECT:
2189 FETCH(&r[1], 0, TGSI_CHAN_Y);
2190 if (compare) {
2191 FETCH(&r[2], 3, TGSI_CHAN_X);
2192 fetch_texel(mach->Samplers[sampler_unit],
2193 &r[0], &r[1], &r[2], lod, &ZeroVec, /* S, T, P, LOD */
2194 control,
2195 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2196 }
2197 else {
2198 fetch_texel(mach->Samplers[sampler_unit],
2199 &r[0], &r[1], &ZeroVec, lod, &ZeroVec, /* S, T, P, LOD */
2200 control,
2201 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2202 }
2203 break;
2204
2205 case TGSI_TEXTURE_2D_ARRAY:
2206 case TGSI_TEXTURE_3D:
2207 case TGSI_TEXTURE_CUBE:
2208 FETCH(&r[1], 0, TGSI_CHAN_Y);
2209 FETCH(&r[2], 0, TGSI_CHAN_Z);
2210 if(compare) {
2211 FETCH(&r[3], 3, TGSI_CHAN_X);
2212 fetch_texel(mach->Samplers[sampler_unit],
2213 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2214 control,
2215 &r[0], &r[1], &r[2], &r[3]);
2216 }
2217 else {
2218 fetch_texel(mach->Samplers[sampler_unit],
2219 &r[0], &r[1], &r[2], lod, &ZeroVec,
2220 control,
2221 &r[0], &r[1], &r[2], &r[3]);
2222 }
2223 break;
2224
2225 case TGSI_TEXTURE_CUBE_ARRAY:
2226 FETCH(&r[1], 0, TGSI_CHAN_Y);
2227 FETCH(&r[2], 0, TGSI_CHAN_Z);
2228 FETCH(&r[3], 0, TGSI_CHAN_W);
2229 if(compare) {
2230 assert(modifier == TEX_MODIFIER_NONE);
2231 /*
2232 * FIXME: lod bias and explicit lod are prohibited but
2233 * for sample_c_lz we pass the level zero info as explicit
2234 * lod 0.
2235 */
2236 FETCH(&r[4], 3, TGSI_CHAN_X);
2237 fetch_texel(mach->Samplers[sampler_unit],
2238 &r[0], &r[1], &r[2], &r[3], &r[4],
2239 control,
2240 &r[0], &r[1], &r[2], &r[3]);
2241 }
2242 else {
2243 fetch_texel(mach->Samplers[sampler_unit],
2244 &r[0], &r[1], &r[2], &r[3], lod,
2245 control,
2246 &r[0], &r[1], &r[2], &r[3]);
2247 }
2248 break;
2249
2250
2251 default:
2252 assert(0);
2253 }
2254
2255 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2256 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2257 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2258 }
2259 }
2260 }
2261
2262 static void
2263 exec_sample_d(struct tgsi_exec_machine *mach,
2264 const struct tgsi_full_instruction *inst)
2265 {
2266 const uint resource_unit = inst->Src[1].Register.Index;
2267 const uint sampler_unit = inst->Src[2].Register.Index;
2268 union tgsi_exec_channel r[4];
2269 uint chan;
2270 /*
2271 * XXX: This is fake SAMPLE_D -- the derivatives are not taken into account, yet.
2272 */
2273
2274 switch (mach->SamplerViews[resource_unit].Resource) {
2275 case TGSI_TEXTURE_1D:
2276 FETCH(&r[0], 0, TGSI_CHAN_X);
2277
2278 fetch_texel(mach->Samplers[sampler_unit],
2279 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, BIAS */
2280 tgsi_sampler_lod_bias,
2281 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2282 break;
2283
2284 case TGSI_TEXTURE_2D:
2285 case TGSI_TEXTURE_RECT:
2286 FETCH(&r[0], 0, TGSI_CHAN_X);
2287 FETCH(&r[1], 0, TGSI_CHAN_Y);
2288
2289 fetch_texel(mach->Samplers[sampler_unit],
2290 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* inputs */
2291 tgsi_sampler_lod_bias,
2292 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2293 break;
2294
2295 case TGSI_TEXTURE_3D:
2296 case TGSI_TEXTURE_CUBE:
2297 FETCH(&r[0], 0, TGSI_CHAN_X);
2298 FETCH(&r[1], 0, TGSI_CHAN_Y);
2299 FETCH(&r[2], 0, TGSI_CHAN_Z);
2300
2301 fetch_texel(mach->Samplers[sampler_unit],
2302 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec,
2303 tgsi_sampler_lod_bias,
2304 &r[0], &r[1], &r[2], &r[3]);
2305 break;
2306
2307 case TGSI_TEXTURE_CUBE_ARRAY:
2308 FETCH(&r[0], 0, TGSI_CHAN_X);
2309 FETCH(&r[1], 0, TGSI_CHAN_Y);
2310 FETCH(&r[2], 0, TGSI_CHAN_Z);
2311 FETCH(&r[3], 0, TGSI_CHAN_W);
2312
2313 fetch_texel(mach->Samplers[sampler_unit],
2314 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2315 tgsi_sampler_lod_bias,
2316 &r[0], &r[1], &r[2], &r[3]);
2317 break;
2318
2319 default:
2320 assert(0);
2321 }
2322
2323 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2324 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2325 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2326 }
2327 }
2328 }
2329
2330
2331 /**
2332 * Evaluate a constant-valued coefficient at the position of the
2333 * current quad.
2334 */
2335 static void
2336 eval_constant_coef(
2337 struct tgsi_exec_machine *mach,
2338 unsigned attrib,
2339 unsigned chan )
2340 {
2341 unsigned i;
2342
2343 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2344 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2345 }
2346 }
2347
2348 /**
2349 * Evaluate a linear-valued coefficient at the position of the
2350 * current quad.
2351 */
2352 static void
2353 eval_linear_coef(
2354 struct tgsi_exec_machine *mach,
2355 unsigned attrib,
2356 unsigned chan )
2357 {
2358 const float x = mach->QuadPos.xyzw[0].f[0];
2359 const float y = mach->QuadPos.xyzw[1].f[0];
2360 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2361 const float dady = mach->InterpCoefs[attrib].dady[chan];
2362 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2363 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2364 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2365 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2366 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2367 }
2368
2369 /**
2370 * Evaluate a perspective-valued coefficient at the position of the
2371 * current quad.
2372 */
2373 static void
2374 eval_perspective_coef(
2375 struct tgsi_exec_machine *mach,
2376 unsigned attrib,
2377 unsigned chan )
2378 {
2379 const float x = mach->QuadPos.xyzw[0].f[0];
2380 const float y = mach->QuadPos.xyzw[1].f[0];
2381 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2382 const float dady = mach->InterpCoefs[attrib].dady[chan];
2383 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2384 const float *w = mach->QuadPos.xyzw[3].f;
2385 /* divide by W here */
2386 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2387 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2388 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2389 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2390 }
2391
2392
2393 typedef void (* eval_coef_func)(
2394 struct tgsi_exec_machine *mach,
2395 unsigned attrib,
2396 unsigned chan );
2397
2398 static void
2399 exec_declaration(struct tgsi_exec_machine *mach,
2400 const struct tgsi_full_declaration *decl)
2401 {
2402 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2403 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2404 return;
2405 }
2406
2407 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2408 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2409 uint first, last, mask;
2410
2411 first = decl->Range.First;
2412 last = decl->Range.Last;
2413 mask = decl->Declaration.UsageMask;
2414
2415 /* XXX we could remove this special-case code since
2416 * mach->InterpCoefs[first].a0 should already have the
2417 * front/back-face value. But we should first update the
2418 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2419 * Then, we could remove the tgsi_exec_machine::Face field.
2420 */
2421 /* XXX make FACE a system value */
2422 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2423 uint i;
2424
2425 assert(decl->Semantic.Index == 0);
2426 assert(first == last);
2427
2428 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2429 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2430 }
2431 } else {
2432 eval_coef_func eval;
2433 uint i, j;
2434
2435 switch (decl->Interp.Interpolate) {
2436 case TGSI_INTERPOLATE_CONSTANT:
2437 eval = eval_constant_coef;
2438 break;
2439
2440 case TGSI_INTERPOLATE_LINEAR:
2441 eval = eval_linear_coef;
2442 break;
2443
2444 case TGSI_INTERPOLATE_PERSPECTIVE:
2445 eval = eval_perspective_coef;
2446 break;
2447
2448 case TGSI_INTERPOLATE_COLOR:
2449 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2450 break;
2451
2452 default:
2453 assert(0);
2454 return;
2455 }
2456
2457 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2458 if (mask & (1 << j)) {
2459 for (i = first; i <= last; i++) {
2460 eval(mach, i, j);
2461 }
2462 }
2463 }
2464 }
2465 }
2466 }
2467
2468 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2469 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2470 }
2471 }
2472
2473
2474 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2475
2476 static void
2477 exec_vector(struct tgsi_exec_machine *mach,
2478 const struct tgsi_full_instruction *inst,
2479 micro_op op,
2480 enum tgsi_exec_datatype dst_datatype)
2481 {
2482 unsigned int chan;
2483
2484 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2485 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2486 union tgsi_exec_channel dst;
2487
2488 op(&dst);
2489 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2490 }
2491 }
2492 }
2493
2494 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2495 const union tgsi_exec_channel *src);
2496
2497 static void
2498 exec_scalar_unary(struct tgsi_exec_machine *mach,
2499 const struct tgsi_full_instruction *inst,
2500 micro_unary_op op,
2501 enum tgsi_exec_datatype dst_datatype,
2502 enum tgsi_exec_datatype src_datatype)
2503 {
2504 unsigned int chan;
2505 union tgsi_exec_channel src;
2506 union tgsi_exec_channel dst;
2507
2508 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2509 op(&dst, &src);
2510 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2511 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2512 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2513 }
2514 }
2515 }
2516
2517 static void
2518 exec_vector_unary(struct tgsi_exec_machine *mach,
2519 const struct tgsi_full_instruction *inst,
2520 micro_unary_op op,
2521 enum tgsi_exec_datatype dst_datatype,
2522 enum tgsi_exec_datatype src_datatype)
2523 {
2524 unsigned int chan;
2525 struct tgsi_exec_vector dst;
2526
2527 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2528 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2529 union tgsi_exec_channel src;
2530
2531 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2532 op(&dst.xyzw[chan], &src);
2533 }
2534 }
2535 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2536 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2537 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2538 }
2539 }
2540 }
2541
2542 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2543 const union tgsi_exec_channel *src0,
2544 const union tgsi_exec_channel *src1);
2545
2546 static void
2547 exec_scalar_binary(struct tgsi_exec_machine *mach,
2548 const struct tgsi_full_instruction *inst,
2549 micro_binary_op op,
2550 enum tgsi_exec_datatype dst_datatype,
2551 enum tgsi_exec_datatype src_datatype)
2552 {
2553 unsigned int chan;
2554 union tgsi_exec_channel src[2];
2555 union tgsi_exec_channel dst;
2556
2557 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2558 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_Y, src_datatype);
2559 op(&dst, &src[0], &src[1]);
2560 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2561 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2562 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2563 }
2564 }
2565 }
2566
2567 static void
2568 exec_vector_binary(struct tgsi_exec_machine *mach,
2569 const struct tgsi_full_instruction *inst,
2570 micro_binary_op op,
2571 enum tgsi_exec_datatype dst_datatype,
2572 enum tgsi_exec_datatype src_datatype)
2573 {
2574 unsigned int chan;
2575 struct tgsi_exec_vector dst;
2576
2577 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2578 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2579 union tgsi_exec_channel src[2];
2580
2581 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2582 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2583 op(&dst.xyzw[chan], &src[0], &src[1]);
2584 }
2585 }
2586 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2587 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2588 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2589 }
2590 }
2591 }
2592
2593 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2594 const union tgsi_exec_channel *src0,
2595 const union tgsi_exec_channel *src1,
2596 const union tgsi_exec_channel *src2);
2597
2598 static void
2599 exec_vector_trinary(struct tgsi_exec_machine *mach,
2600 const struct tgsi_full_instruction *inst,
2601 micro_trinary_op op,
2602 enum tgsi_exec_datatype dst_datatype,
2603 enum tgsi_exec_datatype src_datatype)
2604 {
2605 unsigned int chan;
2606 struct tgsi_exec_vector dst;
2607
2608 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2609 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2610 union tgsi_exec_channel src[3];
2611
2612 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2613 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2614 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2615 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2616 }
2617 }
2618 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2619 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2620 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2621 }
2622 }
2623 }
2624
2625 static void
2626 exec_dp3(struct tgsi_exec_machine *mach,
2627 const struct tgsi_full_instruction *inst)
2628 {
2629 unsigned int chan;
2630 union tgsi_exec_channel arg[3];
2631
2632 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2633 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2634 micro_mul(&arg[2], &arg[0], &arg[1]);
2635
2636 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2637 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2638 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2639 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2640 }
2641
2642 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2643 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2644 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2645 }
2646 }
2647 }
2648
2649 static void
2650 exec_dp4(struct tgsi_exec_machine *mach,
2651 const struct tgsi_full_instruction *inst)
2652 {
2653 unsigned int chan;
2654 union tgsi_exec_channel arg[3];
2655
2656 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2657 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2658 micro_mul(&arg[2], &arg[0], &arg[1]);
2659
2660 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2661 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2662 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2663 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2664 }
2665
2666 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2667 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2668 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2669 }
2670 }
2671 }
2672
2673 static void
2674 exec_dp2a(struct tgsi_exec_machine *mach,
2675 const struct tgsi_full_instruction *inst)
2676 {
2677 unsigned int chan;
2678 union tgsi_exec_channel arg[3];
2679
2680 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2681 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2682 micro_mul(&arg[2], &arg[0], &arg[1]);
2683
2684 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2685 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2686 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2687
2688 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2689 micro_add(&arg[0], &arg[0], &arg[1]);
2690
2691 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2692 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2693 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2694 }
2695 }
2696 }
2697
2698 static void
2699 exec_dph(struct tgsi_exec_machine *mach,
2700 const struct tgsi_full_instruction *inst)
2701 {
2702 unsigned int chan;
2703 union tgsi_exec_channel arg[3];
2704
2705 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2706 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2707 micro_mul(&arg[2], &arg[0], &arg[1]);
2708
2709 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2710 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2711 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2712
2713 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2714 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2715 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2716
2717 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2718 micro_add(&arg[0], &arg[0], &arg[1]);
2719
2720 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2721 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2722 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2723 }
2724 }
2725 }
2726
2727 static void
2728 exec_dp2(struct tgsi_exec_machine *mach,
2729 const struct tgsi_full_instruction *inst)
2730 {
2731 unsigned int chan;
2732 union tgsi_exec_channel arg[3];
2733
2734 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2735 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2736 micro_mul(&arg[2], &arg[0], &arg[1]);
2737
2738 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2739 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2740 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2741
2742 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2743 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2744 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2745 }
2746 }
2747 }
2748
2749 static void
2750 exec_nrm4(struct tgsi_exec_machine *mach,
2751 const struct tgsi_full_instruction *inst)
2752 {
2753 unsigned int chan;
2754 union tgsi_exec_channel arg[4];
2755 union tgsi_exec_channel scale;
2756
2757 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2758 micro_mul(&scale, &arg[0], &arg[0]);
2759
2760 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2761 union tgsi_exec_channel product;
2762
2763 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2764 micro_mul(&product, &arg[chan], &arg[chan]);
2765 micro_add(&scale, &scale, &product);
2766 }
2767
2768 micro_rsq(&scale, &scale);
2769
2770 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_W; chan++) {
2771 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2772 micro_mul(&arg[chan], &arg[chan], &scale);
2773 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2774 }
2775 }
2776 }
2777
2778 static void
2779 exec_nrm3(struct tgsi_exec_machine *mach,
2780 const struct tgsi_full_instruction *inst)
2781 {
2782 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2783 unsigned int chan;
2784 union tgsi_exec_channel arg[3];
2785 union tgsi_exec_channel scale;
2786
2787 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2788 micro_mul(&scale, &arg[0], &arg[0]);
2789
2790 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2791 union tgsi_exec_channel product;
2792
2793 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2794 micro_mul(&product, &arg[chan], &arg[chan]);
2795 micro_add(&scale, &scale, &product);
2796 }
2797
2798 micro_rsq(&scale, &scale);
2799
2800 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_Z; chan++) {
2801 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2802 micro_mul(&arg[chan], &arg[chan], &scale);
2803 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2804 }
2805 }
2806 }
2807
2808 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2809 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2810 }
2811 }
2812
2813 static void
2814 exec_scs(struct tgsi_exec_machine *mach,
2815 const struct tgsi_full_instruction *inst)
2816 {
2817 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2818 union tgsi_exec_channel arg;
2819 union tgsi_exec_channel result;
2820
2821 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2822
2823 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2824 micro_cos(&result, &arg);
2825 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2826 }
2827 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2828 micro_sin(&result, &arg);
2829 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2830 }
2831 }
2832 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2833 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2834 }
2835 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2836 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2837 }
2838 }
2839
2840 static void
2841 exec_x2d(struct tgsi_exec_machine *mach,
2842 const struct tgsi_full_instruction *inst)
2843 {
2844 union tgsi_exec_channel r[4];
2845 union tgsi_exec_channel d[2];
2846
2847 fetch_source(mach, &r[0], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2848 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2849 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2850 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2851 micro_mul(&r[2], &r[2], &r[0]);
2852 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2853 micro_mul(&r[3], &r[3], &r[1]);
2854 micro_add(&r[2], &r[2], &r[3]);
2855 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2856 micro_add(&d[0], &r[2], &r[3]);
2857 }
2858 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2859 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2860 micro_mul(&r[2], &r[2], &r[0]);
2861 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2862 micro_mul(&r[3], &r[3], &r[1]);
2863 micro_add(&r[2], &r[2], &r[3]);
2864 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2865 micro_add(&d[1], &r[2], &r[3]);
2866 }
2867 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2868 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2869 }
2870 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2871 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2872 }
2873 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2874 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2875 }
2876 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2877 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2878 }
2879 }
2880
2881 static void
2882 exec_rfl(struct tgsi_exec_machine *mach,
2883 const struct tgsi_full_instruction *inst)
2884 {
2885 union tgsi_exec_channel r[9];
2886
2887 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2888 /* r0 = dp3(src0, src0) */
2889 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2890 micro_mul(&r[0], &r[2], &r[2]);
2891 fetch_source(mach, &r[4], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2892 micro_mul(&r[8], &r[4], &r[4]);
2893 micro_add(&r[0], &r[0], &r[8]);
2894 fetch_source(mach, &r[6], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2895 micro_mul(&r[8], &r[6], &r[6]);
2896 micro_add(&r[0], &r[0], &r[8]);
2897
2898 /* r1 = dp3(src0, src1) */
2899 fetch_source(mach, &r[3], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2900 micro_mul(&r[1], &r[2], &r[3]);
2901 fetch_source(mach, &r[5], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2902 micro_mul(&r[8], &r[4], &r[5]);
2903 micro_add(&r[1], &r[1], &r[8]);
2904 fetch_source(mach, &r[7], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2905 micro_mul(&r[8], &r[6], &r[7]);
2906 micro_add(&r[1], &r[1], &r[8]);
2907
2908 /* r1 = 2 * r1 / r0 */
2909 micro_add(&r[1], &r[1], &r[1]);
2910 micro_div(&r[1], &r[1], &r[0]);
2911
2912 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2913 micro_mul(&r[2], &r[2], &r[1]);
2914 micro_sub(&r[2], &r[2], &r[3]);
2915 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2916 }
2917 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2918 micro_mul(&r[4], &r[4], &r[1]);
2919 micro_sub(&r[4], &r[4], &r[5]);
2920 store_dest(mach, &r[4], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2921 }
2922 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2923 micro_mul(&r[6], &r[6], &r[1]);
2924 micro_sub(&r[6], &r[6], &r[7]);
2925 store_dest(mach, &r[6], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2926 }
2927 }
2928 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2929 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2930 }
2931 }
2932
2933 static void
2934 exec_xpd(struct tgsi_exec_machine *mach,
2935 const struct tgsi_full_instruction *inst)
2936 {
2937 union tgsi_exec_channel r[6];
2938 union tgsi_exec_channel d[3];
2939
2940 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2941 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2942
2943 micro_mul(&r[2], &r[0], &r[1]);
2944
2945 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2946 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2947
2948 micro_mul(&r[5], &r[3], &r[4] );
2949 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
2950
2951 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2952
2953 micro_mul(&r[3], &r[3], &r[2]);
2954
2955 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2956
2957 micro_mul(&r[1], &r[1], &r[5]);
2958 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
2959
2960 micro_mul(&r[5], &r[5], &r[4]);
2961 micro_mul(&r[0], &r[0], &r[2]);
2962 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
2963
2964 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2965 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2966 }
2967 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2968 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2969 }
2970 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2971 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2972 }
2973 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2974 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2975 }
2976 }
2977
2978 static void
2979 exec_dst(struct tgsi_exec_machine *mach,
2980 const struct tgsi_full_instruction *inst)
2981 {
2982 union tgsi_exec_channel r[2];
2983 union tgsi_exec_channel d[4];
2984
2985 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2986 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2987 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2988 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
2989 }
2990 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2991 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2992 }
2993 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2994 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2995 }
2996
2997 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2998 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2999 }
3000 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3001 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3002 }
3003 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3004 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3005 }
3006 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3007 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3008 }
3009 }
3010
3011 static void
3012 exec_log(struct tgsi_exec_machine *mach,
3013 const struct tgsi_full_instruction *inst)
3014 {
3015 union tgsi_exec_channel r[3];
3016
3017 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3018 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3019 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3020 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3021 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3022 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3023 }
3024 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3025 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3026 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3027 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3028 }
3029 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3030 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3031 }
3032 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3033 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3034 }
3035 }
3036
3037 static void
3038 exec_exp(struct tgsi_exec_machine *mach,
3039 const struct tgsi_full_instruction *inst)
3040 {
3041 union tgsi_exec_channel r[3];
3042
3043 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3044 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3045 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3046 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3047 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3048 }
3049 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3050 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3051 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3052 }
3053 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3054 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3055 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3056 }
3057 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3058 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3059 }
3060 }
3061
3062 static void
3063 exec_lit(struct tgsi_exec_machine *mach,
3064 const struct tgsi_full_instruction *inst)
3065 {
3066 union tgsi_exec_channel r[3];
3067 union tgsi_exec_channel d[3];
3068
3069 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3070 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3071 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3072 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3073 micro_max(&r[1], &r[1], &ZeroVec);
3074
3075 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3076 micro_min(&r[2], &r[2], &P128Vec);
3077 micro_max(&r[2], &r[2], &M128Vec);
3078 micro_pow(&r[1], &r[1], &r[2]);
3079 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3080 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3081 }
3082 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3083 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3084 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3085 }
3086 }
3087 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3088 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3089 }
3090
3091 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3092 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3093 }
3094 }
3095
3096 static void
3097 exec_break(struct tgsi_exec_machine *mach)
3098 {
3099 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3100 /* turn off loop channels for each enabled exec channel */
3101 mach->LoopMask &= ~mach->ExecMask;
3102 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3103 UPDATE_EXEC_MASK(mach);
3104 } else {
3105 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3106
3107 mach->Switch.mask = 0x0;
3108
3109 UPDATE_EXEC_MASK(mach);
3110 }
3111 }
3112
3113 static void
3114 exec_switch(struct tgsi_exec_machine *mach,
3115 const struct tgsi_full_instruction *inst)
3116 {
3117 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3118 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3119
3120 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3121 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3122 mach->Switch.mask = 0x0;
3123 mach->Switch.defaultMask = 0x0;
3124
3125 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3126 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3127
3128 UPDATE_EXEC_MASK(mach);
3129 }
3130
3131 static void
3132 exec_case(struct tgsi_exec_machine *mach,
3133 const struct tgsi_full_instruction *inst)
3134 {
3135 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3136 union tgsi_exec_channel src;
3137 uint mask = 0;
3138
3139 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3140
3141 if (mach->Switch.selector.u[0] == src.u[0]) {
3142 mask |= 0x1;
3143 }
3144 if (mach->Switch.selector.u[1] == src.u[1]) {
3145 mask |= 0x2;
3146 }
3147 if (mach->Switch.selector.u[2] == src.u[2]) {
3148 mask |= 0x4;
3149 }
3150 if (mach->Switch.selector.u[3] == src.u[3]) {
3151 mask |= 0x8;
3152 }
3153
3154 mach->Switch.defaultMask |= mask;
3155
3156 mach->Switch.mask |= mask & prevMask;
3157
3158 UPDATE_EXEC_MASK(mach);
3159 }
3160
3161 static void
3162 exec_default(struct tgsi_exec_machine *mach)
3163 {
3164 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3165
3166 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3167
3168 UPDATE_EXEC_MASK(mach);
3169 }
3170
3171 static void
3172 exec_endswitch(struct tgsi_exec_machine *mach)
3173 {
3174 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3175 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3176
3177 UPDATE_EXEC_MASK(mach);
3178 }
3179
3180 static void
3181 micro_i2f(union tgsi_exec_channel *dst,
3182 const union tgsi_exec_channel *src)
3183 {
3184 dst->f[0] = (float)src->i[0];
3185 dst->f[1] = (float)src->i[1];
3186 dst->f[2] = (float)src->i[2];
3187 dst->f[3] = (float)src->i[3];
3188 }
3189
3190 static void
3191 micro_not(union tgsi_exec_channel *dst,
3192 const union tgsi_exec_channel *src)
3193 {
3194 dst->u[0] = ~src->u[0];
3195 dst->u[1] = ~src->u[1];
3196 dst->u[2] = ~src->u[2];
3197 dst->u[3] = ~src->u[3];
3198 }
3199
3200 static void
3201 micro_shl(union tgsi_exec_channel *dst,
3202 const union tgsi_exec_channel *src0,
3203 const union tgsi_exec_channel *src1)
3204 {
3205 dst->u[0] = src0->u[0] << src1->u[0];
3206 dst->u[1] = src0->u[1] << src1->u[1];
3207 dst->u[2] = src0->u[2] << src1->u[2];
3208 dst->u[3] = src0->u[3] << src1->u[3];
3209 }
3210
3211 static void
3212 micro_and(union tgsi_exec_channel *dst,
3213 const union tgsi_exec_channel *src0,
3214 const union tgsi_exec_channel *src1)
3215 {
3216 dst->u[0] = src0->u[0] & src1->u[0];
3217 dst->u[1] = src0->u[1] & src1->u[1];
3218 dst->u[2] = src0->u[2] & src1->u[2];
3219 dst->u[3] = src0->u[3] & src1->u[3];
3220 }
3221
3222 static void
3223 micro_or(union tgsi_exec_channel *dst,
3224 const union tgsi_exec_channel *src0,
3225 const union tgsi_exec_channel *src1)
3226 {
3227 dst->u[0] = src0->u[0] | src1->u[0];
3228 dst->u[1] = src0->u[1] | src1->u[1];
3229 dst->u[2] = src0->u[2] | src1->u[2];
3230 dst->u[3] = src0->u[3] | src1->u[3];
3231 }
3232
3233 static void
3234 micro_xor(union tgsi_exec_channel *dst,
3235 const union tgsi_exec_channel *src0,
3236 const union tgsi_exec_channel *src1)
3237 {
3238 dst->u[0] = src0->u[0] ^ src1->u[0];
3239 dst->u[1] = src0->u[1] ^ src1->u[1];
3240 dst->u[2] = src0->u[2] ^ src1->u[2];
3241 dst->u[3] = src0->u[3] ^ src1->u[3];
3242 }
3243
3244 static void
3245 micro_mod(union tgsi_exec_channel *dst,
3246 const union tgsi_exec_channel *src0,
3247 const union tgsi_exec_channel *src1)
3248 {
3249 dst->i[0] = src0->i[0] % src1->i[0];
3250 dst->i[1] = src0->i[1] % src1->i[1];
3251 dst->i[2] = src0->i[2] % src1->i[2];
3252 dst->i[3] = src0->i[3] % src1->i[3];
3253 }
3254
3255 static void
3256 micro_f2i(union tgsi_exec_channel *dst,
3257 const union tgsi_exec_channel *src)
3258 {
3259 dst->i[0] = (int)src->f[0];
3260 dst->i[1] = (int)src->f[1];
3261 dst->i[2] = (int)src->f[2];
3262 dst->i[3] = (int)src->f[3];
3263 }
3264
3265 static void
3266 micro_idiv(union tgsi_exec_channel *dst,
3267 const union tgsi_exec_channel *src0,
3268 const union tgsi_exec_channel *src1)
3269 {
3270 dst->i[0] = src0->i[0] / src1->i[0];
3271 dst->i[1] = src0->i[1] / src1->i[1];
3272 dst->i[2] = src0->i[2] / src1->i[2];
3273 dst->i[3] = src0->i[3] / src1->i[3];
3274 }
3275
3276 static void
3277 micro_imax(union tgsi_exec_channel *dst,
3278 const union tgsi_exec_channel *src0,
3279 const union tgsi_exec_channel *src1)
3280 {
3281 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3282 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3283 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3284 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3285 }
3286
3287 static void
3288 micro_imin(union tgsi_exec_channel *dst,
3289 const union tgsi_exec_channel *src0,
3290 const union tgsi_exec_channel *src1)
3291 {
3292 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3293 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3294 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3295 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3296 }
3297
3298 static void
3299 micro_isge(union tgsi_exec_channel *dst,
3300 const union tgsi_exec_channel *src0,
3301 const union tgsi_exec_channel *src1)
3302 {
3303 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3304 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3305 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3306 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3307 }
3308
3309 static void
3310 micro_ishr(union tgsi_exec_channel *dst,
3311 const union tgsi_exec_channel *src0,
3312 const union tgsi_exec_channel *src1)
3313 {
3314 dst->i[0] = src0->i[0] >> src1->i[0];
3315 dst->i[1] = src0->i[1] >> src1->i[1];
3316 dst->i[2] = src0->i[2] >> src1->i[2];
3317 dst->i[3] = src0->i[3] >> src1->i[3];
3318 }
3319
3320 static void
3321 micro_islt(union tgsi_exec_channel *dst,
3322 const union tgsi_exec_channel *src0,
3323 const union tgsi_exec_channel *src1)
3324 {
3325 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3326 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3327 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3328 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3329 }
3330
3331 static void
3332 micro_f2u(union tgsi_exec_channel *dst,
3333 const union tgsi_exec_channel *src)
3334 {
3335 dst->u[0] = (uint)src->f[0];
3336 dst->u[1] = (uint)src->f[1];
3337 dst->u[2] = (uint)src->f[2];
3338 dst->u[3] = (uint)src->f[3];
3339 }
3340
3341 static void
3342 micro_u2f(union tgsi_exec_channel *dst,
3343 const union tgsi_exec_channel *src)
3344 {
3345 dst->f[0] = (float)src->u[0];
3346 dst->f[1] = (float)src->u[1];
3347 dst->f[2] = (float)src->u[2];
3348 dst->f[3] = (float)src->u[3];
3349 }
3350
3351 static void
3352 micro_uadd(union tgsi_exec_channel *dst,
3353 const union tgsi_exec_channel *src0,
3354 const union tgsi_exec_channel *src1)
3355 {
3356 dst->u[0] = src0->u[0] + src1->u[0];
3357 dst->u[1] = src0->u[1] + src1->u[1];
3358 dst->u[2] = src0->u[2] + src1->u[2];
3359 dst->u[3] = src0->u[3] + src1->u[3];
3360 }
3361
3362 static void
3363 micro_udiv(union tgsi_exec_channel *dst,
3364 const union tgsi_exec_channel *src0,
3365 const union tgsi_exec_channel *src1)
3366 {
3367 dst->u[0] = src0->u[0] / src1->u[0];
3368 dst->u[1] = src0->u[1] / src1->u[1];
3369 dst->u[2] = src0->u[2] / src1->u[2];
3370 dst->u[3] = src0->u[3] / src1->u[3];
3371 }
3372
3373 static void
3374 micro_umad(union tgsi_exec_channel *dst,
3375 const union tgsi_exec_channel *src0,
3376 const union tgsi_exec_channel *src1,
3377 const union tgsi_exec_channel *src2)
3378 {
3379 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3380 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3381 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3382 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3383 }
3384
3385 static void
3386 micro_umax(union tgsi_exec_channel *dst,
3387 const union tgsi_exec_channel *src0,
3388 const union tgsi_exec_channel *src1)
3389 {
3390 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3391 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3392 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3393 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3394 }
3395
3396 static void
3397 micro_umin(union tgsi_exec_channel *dst,
3398 const union tgsi_exec_channel *src0,
3399 const union tgsi_exec_channel *src1)
3400 {
3401 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3402 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3403 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3404 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3405 }
3406
3407 static void
3408 micro_umod(union tgsi_exec_channel *dst,
3409 const union tgsi_exec_channel *src0,
3410 const union tgsi_exec_channel *src1)
3411 {
3412 dst->u[0] = src0->u[0] % src1->u[0];
3413 dst->u[1] = src0->u[1] % src1->u[1];
3414 dst->u[2] = src0->u[2] % src1->u[2];
3415 dst->u[3] = src0->u[3] % src1->u[3];
3416 }
3417
3418 static void
3419 micro_umul(union tgsi_exec_channel *dst,
3420 const union tgsi_exec_channel *src0,
3421 const union tgsi_exec_channel *src1)
3422 {
3423 dst->u[0] = src0->u[0] * src1->u[0];
3424 dst->u[1] = src0->u[1] * src1->u[1];
3425 dst->u[2] = src0->u[2] * src1->u[2];
3426 dst->u[3] = src0->u[3] * src1->u[3];
3427 }
3428
3429 static void
3430 micro_useq(union tgsi_exec_channel *dst,
3431 const union tgsi_exec_channel *src0,
3432 const union tgsi_exec_channel *src1)
3433 {
3434 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3435 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3436 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3437 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3438 }
3439
3440 static void
3441 micro_usge(union tgsi_exec_channel *dst,
3442 const union tgsi_exec_channel *src0,
3443 const union tgsi_exec_channel *src1)
3444 {
3445 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3446 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3447 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3448 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3449 }
3450
3451 static void
3452 micro_ushr(union tgsi_exec_channel *dst,
3453 const union tgsi_exec_channel *src0,
3454 const union tgsi_exec_channel *src1)
3455 {
3456 dst->u[0] = src0->u[0] >> src1->u[0];
3457 dst->u[1] = src0->u[1] >> src1->u[1];
3458 dst->u[2] = src0->u[2] >> src1->u[2];
3459 dst->u[3] = src0->u[3] >> src1->u[3];
3460 }
3461
3462 static void
3463 micro_uslt(union tgsi_exec_channel *dst,
3464 const union tgsi_exec_channel *src0,
3465 const union tgsi_exec_channel *src1)
3466 {
3467 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3468 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3469 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3470 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3471 }
3472
3473 static void
3474 micro_usne(union tgsi_exec_channel *dst,
3475 const union tgsi_exec_channel *src0,
3476 const union tgsi_exec_channel *src1)
3477 {
3478 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3479 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3480 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3481 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3482 }
3483
3484 static void
3485 micro_uarl(union tgsi_exec_channel *dst,
3486 const union tgsi_exec_channel *src)
3487 {
3488 dst->i[0] = src->u[0];
3489 dst->i[1] = src->u[1];
3490 dst->i[2] = src->u[2];
3491 dst->i[3] = src->u[3];
3492 }
3493
3494 static void
3495 micro_ucmp(union tgsi_exec_channel *dst,
3496 const union tgsi_exec_channel *src0,
3497 const union tgsi_exec_channel *src1,
3498 const union tgsi_exec_channel *src2)
3499 {
3500 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3501 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3502 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3503 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3504 }
3505
3506 static void
3507 exec_instruction(
3508 struct tgsi_exec_machine *mach,
3509 const struct tgsi_full_instruction *inst,
3510 int *pc )
3511 {
3512 union tgsi_exec_channel r[10];
3513
3514 (*pc)++;
3515
3516 switch (inst->Instruction.Opcode) {
3517 case TGSI_OPCODE_ARL:
3518 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3519 break;
3520
3521 case TGSI_OPCODE_MOV:
3522 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3523 break;
3524
3525 case TGSI_OPCODE_LIT:
3526 exec_lit(mach, inst);
3527 break;
3528
3529 case TGSI_OPCODE_RCP:
3530 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3531 break;
3532
3533 case TGSI_OPCODE_RSQ:
3534 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3535 break;
3536
3537 case TGSI_OPCODE_EXP:
3538 exec_exp(mach, inst);
3539 break;
3540
3541 case TGSI_OPCODE_LOG:
3542 exec_log(mach, inst);
3543 break;
3544
3545 case TGSI_OPCODE_MUL:
3546 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3547 break;
3548
3549 case TGSI_OPCODE_ADD:
3550 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3551 break;
3552
3553 case TGSI_OPCODE_DP3:
3554 exec_dp3(mach, inst);
3555 break;
3556
3557 case TGSI_OPCODE_DP4:
3558 exec_dp4(mach, inst);
3559 break;
3560
3561 case TGSI_OPCODE_DST:
3562 exec_dst(mach, inst);
3563 break;
3564
3565 case TGSI_OPCODE_MIN:
3566 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3567 break;
3568
3569 case TGSI_OPCODE_MAX:
3570 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3571 break;
3572
3573 case TGSI_OPCODE_SLT:
3574 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3575 break;
3576
3577 case TGSI_OPCODE_SGE:
3578 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3579 break;
3580
3581 case TGSI_OPCODE_MAD:
3582 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3583 break;
3584
3585 case TGSI_OPCODE_SUB:
3586 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3587 break;
3588
3589 case TGSI_OPCODE_LRP:
3590 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3591 break;
3592
3593 case TGSI_OPCODE_CND:
3594 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3595 break;
3596
3597 case TGSI_OPCODE_SQRT:
3598 exec_vector_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3599 break;
3600
3601 case TGSI_OPCODE_DP2A:
3602 exec_dp2a(mach, inst);
3603 break;
3604
3605 case TGSI_OPCODE_FRC:
3606 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3607 break;
3608
3609 case TGSI_OPCODE_CLAMP:
3610 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3611 break;
3612
3613 case TGSI_OPCODE_FLR:
3614 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3615 break;
3616
3617 case TGSI_OPCODE_ROUND:
3618 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3619 break;
3620
3621 case TGSI_OPCODE_EX2:
3622 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3623 break;
3624
3625 case TGSI_OPCODE_LG2:
3626 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3627 break;
3628
3629 case TGSI_OPCODE_POW:
3630 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3631 break;
3632
3633 case TGSI_OPCODE_XPD:
3634 exec_xpd(mach, inst);
3635 break;
3636
3637 case TGSI_OPCODE_ABS:
3638 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3639 break;
3640
3641 case TGSI_OPCODE_RCC:
3642 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3643 break;
3644
3645 case TGSI_OPCODE_DPH:
3646 exec_dph(mach, inst);
3647 break;
3648
3649 case TGSI_OPCODE_COS:
3650 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3651 break;
3652
3653 case TGSI_OPCODE_DDX:
3654 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3655 break;
3656
3657 case TGSI_OPCODE_DDY:
3658 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3659 break;
3660
3661 case TGSI_OPCODE_KILP:
3662 exec_kilp (mach, inst);
3663 break;
3664
3665 case TGSI_OPCODE_KIL:
3666 exec_kil (mach, inst);
3667 break;
3668
3669 case TGSI_OPCODE_PK2H:
3670 assert (0);
3671 break;
3672
3673 case TGSI_OPCODE_PK2US:
3674 assert (0);
3675 break;
3676
3677 case TGSI_OPCODE_PK4B:
3678 assert (0);
3679 break;
3680
3681 case TGSI_OPCODE_PK4UB:
3682 assert (0);
3683 break;
3684
3685 case TGSI_OPCODE_RFL:
3686 exec_rfl(mach, inst);
3687 break;
3688
3689 case TGSI_OPCODE_SEQ:
3690 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3691 break;
3692
3693 case TGSI_OPCODE_SFL:
3694 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3695 break;
3696
3697 case TGSI_OPCODE_SGT:
3698 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3699 break;
3700
3701 case TGSI_OPCODE_SIN:
3702 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3703 break;
3704
3705 case TGSI_OPCODE_SLE:
3706 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3707 break;
3708
3709 case TGSI_OPCODE_SNE:
3710 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3711 break;
3712
3713 case TGSI_OPCODE_STR:
3714 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3715 break;
3716
3717 case TGSI_OPCODE_TEX:
3718 /* simple texture lookup */
3719 /* src[0] = texcoord */
3720 /* src[1] = sampler unit */
3721 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
3722 break;
3723
3724 case TGSI_OPCODE_TXB:
3725 /* Texture lookup with lod bias */
3726 /* src[0] = texcoord (src[0].w = LOD bias) */
3727 /* src[1] = sampler unit */
3728 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
3729 break;
3730
3731 case TGSI_OPCODE_TXD:
3732 /* Texture lookup with explict partial derivatives */
3733 /* src[0] = texcoord */
3734 /* src[1] = d[strq]/dx */
3735 /* src[2] = d[strq]/dy */
3736 /* src[3] = sampler unit */
3737 exec_txd(mach, inst);
3738 break;
3739
3740 case TGSI_OPCODE_TXL:
3741 /* Texture lookup with explit LOD */
3742 /* src[0] = texcoord (src[0].w = LOD) */
3743 /* src[1] = sampler unit */
3744 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
3745 break;
3746
3747 case TGSI_OPCODE_TXP:
3748 /* Texture lookup with projection */
3749 /* src[0] = texcoord (src[0].w = projection) */
3750 /* src[1] = sampler unit */
3751 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
3752 break;
3753
3754 case TGSI_OPCODE_UP2H:
3755 assert (0);
3756 break;
3757
3758 case TGSI_OPCODE_UP2US:
3759 assert (0);
3760 break;
3761
3762 case TGSI_OPCODE_UP4B:
3763 assert (0);
3764 break;
3765
3766 case TGSI_OPCODE_UP4UB:
3767 assert (0);
3768 break;
3769
3770 case TGSI_OPCODE_X2D:
3771 exec_x2d(mach, inst);
3772 break;
3773
3774 case TGSI_OPCODE_ARA:
3775 assert (0);
3776 break;
3777
3778 case TGSI_OPCODE_ARR:
3779 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3780 break;
3781
3782 case TGSI_OPCODE_BRA:
3783 assert (0);
3784 break;
3785
3786 case TGSI_OPCODE_CAL:
3787 /* skip the call if no execution channels are enabled */
3788 if (mach->ExecMask) {
3789 /* do the call */
3790
3791 /* First, record the depths of the execution stacks.
3792 * This is important for deeply nested/looped return statements.
3793 * We have to unwind the stacks by the correct amount. For a
3794 * real code generator, we could determine the number of entries
3795 * to pop off each stack with simple static analysis and avoid
3796 * implementing this data structure at run time.
3797 */
3798 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3799 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3800 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3801 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3802 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3803 /* note that PC was already incremented above */
3804 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3805
3806 mach->CallStackTop++;
3807
3808 /* Second, push the Cond, Loop, Cont, Func stacks */
3809 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3810 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3811 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3812 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3813 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3814 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3815
3816 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3817 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3818 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3819 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3820 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3821 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3822
3823 /* Finally, jump to the subroutine */
3824 *pc = inst->Label.Label;
3825 }
3826 break;
3827
3828 case TGSI_OPCODE_RET:
3829 mach->FuncMask &= ~mach->ExecMask;
3830 UPDATE_EXEC_MASK(mach);
3831
3832 if (mach->FuncMask == 0x0) {
3833 /* really return now (otherwise, keep executing */
3834
3835 if (mach->CallStackTop == 0) {
3836 /* returning from main() */
3837 mach->CondStackTop = 0;
3838 mach->LoopStackTop = 0;
3839 *pc = -1;
3840 return;
3841 }
3842
3843 assert(mach->CallStackTop > 0);
3844 mach->CallStackTop--;
3845
3846 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3847 mach->CondMask = mach->CondStack[mach->CondStackTop];
3848
3849 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3850 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3851
3852 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3853 mach->ContMask = mach->ContStack[mach->ContStackTop];
3854
3855 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3856 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3857
3858 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3859 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3860
3861 assert(mach->FuncStackTop > 0);
3862 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3863
3864 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3865
3866 UPDATE_EXEC_MASK(mach);
3867 }
3868 break;
3869
3870 case TGSI_OPCODE_SSG:
3871 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3872 break;
3873
3874 case TGSI_OPCODE_CMP:
3875 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3876 break;
3877
3878 case TGSI_OPCODE_SCS:
3879 exec_scs(mach, inst);
3880 break;
3881
3882 case TGSI_OPCODE_NRM:
3883 exec_nrm3(mach, inst);
3884 break;
3885
3886 case TGSI_OPCODE_NRM4:
3887 exec_nrm4(mach, inst);
3888 break;
3889
3890 case TGSI_OPCODE_DIV:
3891 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3892 break;
3893
3894 case TGSI_OPCODE_DP2:
3895 exec_dp2(mach, inst);
3896 break;
3897
3898 case TGSI_OPCODE_IF:
3899 /* push CondMask */
3900 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3901 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3902 FETCH( &r[0], 0, TGSI_CHAN_X );
3903 /* update CondMask */
3904 if( ! r[0].u[0] ) {
3905 mach->CondMask &= ~0x1;
3906 }
3907 if( ! r[0].u[1] ) {
3908 mach->CondMask &= ~0x2;
3909 }
3910 if( ! r[0].u[2] ) {
3911 mach->CondMask &= ~0x4;
3912 }
3913 if( ! r[0].u[3] ) {
3914 mach->CondMask &= ~0x8;
3915 }
3916 UPDATE_EXEC_MASK(mach);
3917 /* Todo: If CondMask==0, jump to ELSE */
3918 break;
3919
3920 case TGSI_OPCODE_ELSE:
3921 /* invert CondMask wrt previous mask */
3922 {
3923 uint prevMask;
3924 assert(mach->CondStackTop > 0);
3925 prevMask = mach->CondStack[mach->CondStackTop - 1];
3926 mach->CondMask = ~mach->CondMask & prevMask;
3927 UPDATE_EXEC_MASK(mach);
3928 /* Todo: If CondMask==0, jump to ENDIF */
3929 }
3930 break;
3931
3932 case TGSI_OPCODE_ENDIF:
3933 /* pop CondMask */
3934 assert(mach->CondStackTop > 0);
3935 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3936 UPDATE_EXEC_MASK(mach);
3937 break;
3938
3939 case TGSI_OPCODE_END:
3940 /* make sure we end primitives which haven't
3941 * been explicitly emitted */
3942 conditional_emit_primitive(mach);
3943 /* halt execution */
3944 *pc = -1;
3945 break;
3946
3947 case TGSI_OPCODE_PUSHA:
3948 assert (0);
3949 break;
3950
3951 case TGSI_OPCODE_POPA:
3952 assert (0);
3953 break;
3954
3955 case TGSI_OPCODE_CEIL:
3956 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3957 break;
3958
3959 case TGSI_OPCODE_I2F:
3960 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3961 break;
3962
3963 case TGSI_OPCODE_NOT:
3964 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3965 break;
3966
3967 case TGSI_OPCODE_TRUNC:
3968 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3969 break;
3970
3971 case TGSI_OPCODE_SHL:
3972 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3973 break;
3974
3975 case TGSI_OPCODE_AND:
3976 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3977 break;
3978
3979 case TGSI_OPCODE_OR:
3980 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3981 break;
3982
3983 case TGSI_OPCODE_MOD:
3984 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3985 break;
3986
3987 case TGSI_OPCODE_XOR:
3988 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3989 break;
3990
3991 case TGSI_OPCODE_SAD:
3992 assert (0);
3993 break;
3994
3995 case TGSI_OPCODE_TXF:
3996 exec_txf(mach, inst);
3997 break;
3998
3999 case TGSI_OPCODE_TXQ:
4000 exec_txq(mach, inst);
4001 break;
4002
4003 case TGSI_OPCODE_EMIT:
4004 emit_vertex(mach);
4005 break;
4006
4007 case TGSI_OPCODE_ENDPRIM:
4008 emit_primitive(mach);
4009 break;
4010
4011 case TGSI_OPCODE_BGNLOOP:
4012 /* push LoopMask and ContMasks */
4013 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4014 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4015 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4016 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4017
4018 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4019 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4020 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4021 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4022 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4023 break;
4024
4025 case TGSI_OPCODE_ENDLOOP:
4026 /* Restore ContMask, but don't pop */
4027 assert(mach->ContStackTop > 0);
4028 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4029 UPDATE_EXEC_MASK(mach);
4030 if (mach->ExecMask) {
4031 /* repeat loop: jump to instruction just past BGNLOOP */
4032 assert(mach->LoopLabelStackTop > 0);
4033 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4034 }
4035 else {
4036 /* exit loop: pop LoopMask */
4037 assert(mach->LoopStackTop > 0);
4038 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4039 /* pop ContMask */
4040 assert(mach->ContStackTop > 0);
4041 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4042 assert(mach->LoopLabelStackTop > 0);
4043 --mach->LoopLabelStackTop;
4044
4045 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4046 }
4047 UPDATE_EXEC_MASK(mach);
4048 break;
4049
4050 case TGSI_OPCODE_BRK:
4051 exec_break(mach);
4052 break;
4053
4054 case TGSI_OPCODE_CONT:
4055 /* turn off cont channels for each enabled exec channel */
4056 mach->ContMask &= ~mach->ExecMask;
4057 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4058 UPDATE_EXEC_MASK(mach);
4059 break;
4060
4061 case TGSI_OPCODE_BGNSUB:
4062 /* no-op */
4063 break;
4064
4065 case TGSI_OPCODE_ENDSUB:
4066 /*
4067 * XXX: This really should be a no-op. We should never reach this opcode.
4068 */
4069
4070 assert(mach->CallStackTop > 0);
4071 mach->CallStackTop--;
4072
4073 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4074 mach->CondMask = mach->CondStack[mach->CondStackTop];
4075
4076 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4077 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4078
4079 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4080 mach->ContMask = mach->ContStack[mach->ContStackTop];
4081
4082 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4083 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4084
4085 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4086 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4087
4088 assert(mach->FuncStackTop > 0);
4089 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4090
4091 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4092
4093 UPDATE_EXEC_MASK(mach);
4094 break;
4095
4096 case TGSI_OPCODE_NOP:
4097 break;
4098
4099 case TGSI_OPCODE_BREAKC:
4100 FETCH(&r[0], 0, TGSI_CHAN_X);
4101 /* update CondMask */
4102 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4103 mach->LoopMask &= ~0x1;
4104 }
4105 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4106 mach->LoopMask &= ~0x2;
4107 }
4108 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4109 mach->LoopMask &= ~0x4;
4110 }
4111 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4112 mach->LoopMask &= ~0x8;
4113 }
4114 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4115 UPDATE_EXEC_MASK(mach);
4116 break;
4117
4118 case TGSI_OPCODE_F2I:
4119 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4120 break;
4121
4122 case TGSI_OPCODE_IDIV:
4123 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4124 break;
4125
4126 case TGSI_OPCODE_IMAX:
4127 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4128 break;
4129
4130 case TGSI_OPCODE_IMIN:
4131 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4132 break;
4133
4134 case TGSI_OPCODE_INEG:
4135 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4136 break;
4137
4138 case TGSI_OPCODE_ISGE:
4139 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4140 break;
4141
4142 case TGSI_OPCODE_ISHR:
4143 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4144 break;
4145
4146 case TGSI_OPCODE_ISLT:
4147 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4148 break;
4149
4150 case TGSI_OPCODE_F2U:
4151 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4152 break;
4153
4154 case TGSI_OPCODE_U2F:
4155 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4156 break;
4157
4158 case TGSI_OPCODE_UADD:
4159 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4160 break;
4161
4162 case TGSI_OPCODE_UDIV:
4163 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4164 break;
4165
4166 case TGSI_OPCODE_UMAD:
4167 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4168 break;
4169
4170 case TGSI_OPCODE_UMAX:
4171 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4172 break;
4173
4174 case TGSI_OPCODE_UMIN:
4175 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4176 break;
4177
4178 case TGSI_OPCODE_UMOD:
4179 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4180 break;
4181
4182 case TGSI_OPCODE_UMUL:
4183 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4184 break;
4185
4186 case TGSI_OPCODE_USEQ:
4187 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4188 break;
4189
4190 case TGSI_OPCODE_USGE:
4191 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4192 break;
4193
4194 case TGSI_OPCODE_USHR:
4195 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4196 break;
4197
4198 case TGSI_OPCODE_USLT:
4199 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4200 break;
4201
4202 case TGSI_OPCODE_USNE:
4203 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4204 break;
4205
4206 case TGSI_OPCODE_SWITCH:
4207 exec_switch(mach, inst);
4208 break;
4209
4210 case TGSI_OPCODE_CASE:
4211 exec_case(mach, inst);
4212 break;
4213
4214 case TGSI_OPCODE_DEFAULT:
4215 exec_default(mach);
4216 break;
4217
4218 case TGSI_OPCODE_ENDSWITCH:
4219 exec_endswitch(mach);
4220 break;
4221
4222 case TGSI_OPCODE_SAMPLE_I:
4223 assert(0);
4224 break;
4225
4226 case TGSI_OPCODE_SAMPLE_I_MS:
4227 assert(0);
4228 break;
4229
4230 case TGSI_OPCODE_SAMPLE:
4231 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4232 break;
4233
4234 case TGSI_OPCODE_SAMPLE_B:
4235 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4236 break;
4237
4238 case TGSI_OPCODE_SAMPLE_C:
4239 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4240 break;
4241
4242 case TGSI_OPCODE_SAMPLE_C_LZ:
4243 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4244 break;
4245
4246 case TGSI_OPCODE_SAMPLE_D:
4247 exec_sample_d(mach, inst);
4248 break;
4249
4250 case TGSI_OPCODE_SAMPLE_L:
4251 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4252 break;
4253
4254 case TGSI_OPCODE_GATHER4:
4255 assert(0);
4256 break;
4257
4258 case TGSI_OPCODE_SVIEWINFO:
4259 assert(0);
4260 break;
4261
4262 case TGSI_OPCODE_SAMPLE_POS:
4263 assert(0);
4264 break;
4265
4266 case TGSI_OPCODE_SAMPLE_INFO:
4267 assert(0);
4268 break;
4269
4270 case TGSI_OPCODE_UARL:
4271 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4272 break;
4273
4274 case TGSI_OPCODE_UCMP:
4275 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4276 break;
4277
4278 case TGSI_OPCODE_IABS:
4279 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4280 break;
4281
4282 case TGSI_OPCODE_ISSG:
4283 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4284 break;
4285
4286 case TGSI_OPCODE_TEX2:
4287 /* simple texture lookup */
4288 /* src[0] = texcoord */
4289 /* src[1] = compare */
4290 /* src[2] = sampler unit */
4291 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4292 break;
4293 case TGSI_OPCODE_TXB2:
4294 /* simple texture lookup */
4295 /* src[0] = texcoord */
4296 /* src[1] = bias */
4297 /* src[2] = sampler unit */
4298 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4299 break;
4300 case TGSI_OPCODE_TXL2:
4301 /* simple texture lookup */
4302 /* src[0] = texcoord */
4303 /* src[1] = lod */
4304 /* src[2] = sampler unit */
4305 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4306 break;
4307 default:
4308 assert( 0 );
4309 }
4310 }
4311
4312
4313 #define DEBUG_EXECUTION 0
4314
4315
4316 /**
4317 * Run TGSI interpreter.
4318 * \return bitmask of "alive" quad components
4319 */
4320 uint
4321 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4322 {
4323 uint i;
4324 int pc = 0;
4325
4326 mach->CondMask = 0xf;
4327 mach->LoopMask = 0xf;
4328 mach->ContMask = 0xf;
4329 mach->FuncMask = 0xf;
4330 mach->ExecMask = 0xf;
4331
4332 mach->Switch.mask = 0xf;
4333
4334 assert(mach->CondStackTop == 0);
4335 assert(mach->LoopStackTop == 0);
4336 assert(mach->ContStackTop == 0);
4337 assert(mach->SwitchStackTop == 0);
4338 assert(mach->BreakStackTop == 0);
4339 assert(mach->CallStackTop == 0);
4340
4341 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4342 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4343
4344 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4345 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4346 mach->Primitives[0] = 0;
4347 }
4348
4349 /* execute declarations (interpolants) */
4350 for (i = 0; i < mach->NumDeclarations; i++) {
4351 exec_declaration( mach, mach->Declarations+i );
4352 }
4353
4354 {
4355 #if DEBUG_EXECUTION
4356 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4357 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4358 uint inst = 1;
4359
4360 memcpy(temps, mach->Temps, sizeof(temps));
4361 memcpy(outputs, mach->Outputs, sizeof(outputs));
4362 #endif
4363
4364 /* execute instructions, until pc is set to -1 */
4365 while (pc != -1) {
4366
4367 #if DEBUG_EXECUTION
4368 uint i;
4369
4370 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4371 #endif
4372
4373 assert(pc < (int) mach->NumInstructions);
4374 exec_instruction(mach, mach->Instructions + pc, &pc);
4375
4376 #if DEBUG_EXECUTION
4377 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4378 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4379 uint j;
4380
4381 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4382 debug_printf("TEMP[%2u] = ", i);
4383 for (j = 0; j < 4; j++) {
4384 if (j > 0) {
4385 debug_printf(" ");
4386 }
4387 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4388 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4389 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4390 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4391 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4392 }
4393 }
4394 }
4395 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4396 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4397 uint j;
4398
4399 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4400 debug_printf("OUT[%2u] = ", i);
4401 for (j = 0; j < 4; j++) {
4402 if (j > 0) {
4403 debug_printf(" ");
4404 }
4405 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4406 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4407 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4408 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4409 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4410 }
4411 }
4412 }
4413 #endif
4414 }
4415 }
4416
4417 #if 0
4418 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4419 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4420 /*
4421 * Scale back depth component.
4422 */
4423 for (i = 0; i < 4; i++)
4424 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4425 }
4426 #endif
4427
4428 /* Strictly speaking, these assertions aren't really needed but they
4429 * can potentially catch some bugs in the control flow code.
4430 */
4431 assert(mach->CondStackTop == 0);
4432 assert(mach->LoopStackTop == 0);
4433 assert(mach->ContStackTop == 0);
4434 assert(mach->SwitchStackTop == 0);
4435 assert(mach->BreakStackTop == 0);
4436 assert(mach->CallStackTop == 0);
4437
4438 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4439 }